103 lines
2.5 KiB
VHDL
103 lines
2.5 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 05/04/2022 10:29:08 PM
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-- Design Name:
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-- Module Name: Serializer - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Serializer is
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Generic(
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row_cnt : Integer := 5
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);
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Port (
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col_0 : in std_logic_vector(row_cnt - 1 downto 0);
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col_1 : in std_logic_vector(row_cnt - 1 downto 0);
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col_2 : in std_logic_vector(row_cnt - 1 downto 0);
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col_3 : in std_logic_vector(row_cnt - 1 downto 0);
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col_4 : in std_logic_vector(row_cnt - 1 downto 0);
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in_clk : in std_logic;
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rst : in std_logic;
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ser_0 : out std_logic;
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ser_1 : out std_logic;
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ser_2 : out std_logic;
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ser_3 : out std_logic;
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ser_4 : out std_logic;
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reg_clk : out std_logic;
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out_clk : out std_logic
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);
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end Serializer;
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architecture Behavioral of Serializer is
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type state_type is (s0, s1, s2);
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signal state : state_type;
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signal shift_cnt : Integer := 0;
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signal out_clk_en : std_logic := '1';
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begin
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out_clk <= in_clk;
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process(in_clk, rst) is
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begin
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if rst = '0' then
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state <= s0;
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ser_0 <= '0';
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ser_1 <= '0';
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ser_2 <= '0';
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ser_3 <= '0';
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ser_4 <= '0';
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reg_clk <= '0';
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out_clk_en <= '0';
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shift_cnt <= 0;
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elsif falling_edge(in_clk) then
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shift_cnt <= shift_cnt + 1;
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ser_0 <= col_0(shift_cnt);
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ser_1 <= col_1(shift_cnt);
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ser_2 <= col_2(shift_cnt);
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ser_3 <= col_3(shift_cnt);
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ser_4 <= col_4(shift_cnt);
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if shift_cnt = 0 then
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reg_clk <= '1';
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end if;
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if shift_cnt = 1 then
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reg_clk <= '0';
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end if;
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if shift_cnt = row_cnt - 1 then
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shift_cnt <= 0;
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end if;
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end if;
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end process;
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end Behavioral; |