diff --git a/README.md b/README.md
index c5bc735..175620f 100644
Binary files a/README.md and b/README.md differ
diff --git a/Vitis/.metadata/.log b/Vitis/.metadata/.log
index d5ee139..1e5eb31 100644
--- a/Vitis/.metadata/.log
+++ b/Vitis/.metadata/.log
@@ -9141,3 +9141,9 @@ java.lang.Error
at org.eclipse.tcf.core.AbstractChannel$1$1.run(AbstractChannel.java:371)
at org.eclipse.tcf.EventQueue.run(EventQueue.java:98)
at java.base/java.lang.Thread.run(Thread.java:829)
+
+!ENTRY com.xilinx.sdk.utils 0 0 2022-10-11 18:46:18.100
+!MESSAGE XSCT Command: [disconnect tcfchan#5], Thread: Thread-259
+
+!ENTRY com.xilinx.sdk.utils 0 0 2022-10-11 18:46:18.181
+!MESSAGE XSCT command with result: [disconnect tcfchan#5], Result: [null, ]. Thread: Thread-259
diff --git a/Vitis/.metadata/.plugins/com.xilinx.sdk.targetmanager/dialog_settings.xml b/Vitis/.metadata/.plugins/com.xilinx.sdk.targetmanager/dialog_settings.xml
new file mode 100644
index 0000000..836fa60
--- /dev/null
+++ b/Vitis/.metadata/.plugins/com.xilinx.sdk.targetmanager/dialog_settings.xml
@@ -0,0 +1,4 @@
+
+
+
+
diff --git a/Vitis/.metadata/.plugins/org.eclipse.cdt.core/.log b/Vitis/.metadata/.plugins/org.eclipse.cdt.core/.log
index 594d305..9e21ec3 100644
--- a/Vitis/.metadata/.plugins/org.eclipse.cdt.core/.log
+++ b/Vitis/.metadata/.plugins/org.eclipse.cdt.core/.log
@@ -1,3 +1,4 @@
*** SESSION Oct 01, 2022 17:30:32.37 -------------------------------------------
*** SESSION Oct 01, 2022 18:12:01.54 -------------------------------------------
*** SESSION Oct 03, 2022 21:08:29.07 -------------------------------------------
+*** SESSION Oct 07, 2022 15:02:57.97 -------------------------------------------
diff --git a/Vitis/.metadata/.plugins/org.eclipse.cdt.core/phased_array.1664825649663.pdom b/Vitis/.metadata/.plugins/org.eclipse.cdt.core/phased_array.1664825649663.pdom
index fe108ca..7c6c57f 100644
Binary files a/Vitis/.metadata/.plugins/org.eclipse.cdt.core/phased_array.1664825649663.pdom and b/Vitis/.metadata/.plugins/org.eclipse.cdt.core/phased_array.1664825649663.pdom differ
diff --git a/Vitis/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml b/Vitis/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml
new file mode 100644
index 0000000..8e47957
--- /dev/null
+++ b/Vitis/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml
@@ -0,0 +1,7 @@
+
+
+
+
+
+
+
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/0/023252565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/0/023252565243001d18b399c1eb9b3628
deleted file mode 100644
index 9794da0..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/0/023252565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,350 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xenv_standalone.h
-*
-* Defines common services specified by xenv.h.
-*
-* @note
-* This file is not intended to be included directly by driver code.
-* Instead, the generic xenv.h file is intended to be included by driver
-* code.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a wgr 02/28/07 Added cache handling macros.
-* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
-* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
-* used under Xilinx standalone BSP.
-* 1.00a xd 11/03/04 Improved support for doxygen.
-* 1.00a rmm 03/21/02 First release
-* 1.00a wgr 03/22/07 Converted to new coding style.
-* 1.00a rpm 06/29/07 Added udelay macro for standalone
-* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
-* to in MICROBLAZE section
-* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
-*
-*
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XENV_STANDALONE_H
-#define XENV_STANDALONE_H
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-/******************************************************************************
- *
- * Get the processor dependent includes
- *
- ******************************************************************************/
-
-#include
-
-#if defined __MICROBLAZE__
-# include "mb_interface.h"
-# include "xparameters.h" /* XPAR constants used below in MB section */
-
-#elif defined __PPC__
-# include "sleep.h"
-# include "xcache_l.h" /* also include xcache_l.h for caching macros */
-#endif
-
-/******************************************************************************
- *
- * MEMCPY / MEMSET related macros.
- *
- * The following are straight forward implementations of memset and memcpy.
- *
- * NOTE: memcpy may not work if source and target memory area are overlapping.
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
- *
- * Copies a non-overlapping block of memory.
- *
- * @param DestPtr
- * Destination address to copy data to.
- *
- * @param SrcPtr
- * Source address to copy data from.
- *
- * @param Bytes
- * Number of bytes to copy.
- *
- * @return None.
- *
- * @note
- * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
- *
- * @note
- * This implementation MAY BREAK work if source and target memory
- * area are overlapping.
- *
- *****************************************************************************/
-
-#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
- memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
-
-
-
-/*****************************************************************************/
-/**
- *
- * Fills an area of memory with constant data.
- *
- * @param DestPtr
- * Destination address to copy data to.
- *
- * @param Data
- * Value to set.
- *
- * @param Bytes
- * Number of bytes to copy.
- *
- * @return None.
- *
- * @note
- * The use of XENV_MEM_FILL is deprecated. Use memset() instead.
- *
- *****************************************************************************/
-
-#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
- memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
-
-
-
-/******************************************************************************
- *
- * TIME related macros
- *
- ******************************************************************************/
-
-/**
- * A structure that contains a time stamp used by other time stamp macros
- * defined below. This structure is processor dependent.
- */
-typedef s32 XENV_TIME_STAMP;
-
-/*****************************************************************************/
-/**
- *
- * Time is derived from the 64 bit PPC timebase register
- *
- * @param StampPtr is the storage for the retrieved time stamp.
- *
- * @return None.
- *
- * @note
- *
- * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_GET(StampPtr)
-
-/*****************************************************************************/
-/**
- *
- * This macro is not yet implemented and always returns 0.
- *
- * @param Stamp1Ptr is the first sampled time stamp.
- * @param Stamp2Ptr is the second sampled time stamp.
- *
- * @return 0
- *
- * @note
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
-
-/*****************************************************************************/
-/**
- *
- * This macro is not yet implemented and always returns 0.
- *
- * @param Stamp1Ptr is the first sampled time stamp.
- * @param Stamp2Ptr is the second sampled time stamp.
- *
- * @return 0
- *
- * @note
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
-
-/*****************************************************************************/
-/**
- * XENV_USLEEP(unsigned delay)
- *
- * Delay the specified number of microseconds. Not implemented without OS
- * support.
- *
- * @param delay
- * Number of microseconds to delay.
- *
- * @return None.
- *
- *****************************************************************************/
-
-#ifdef __PPC__
-#define XENV_USLEEP(delay) usleep(delay)
-#define udelay(delay) usleep(delay)
-#else
-#define XENV_USLEEP(delay)
-#define udelay(delay)
-#endif
-
-
-/******************************************************************************
- *
- * CACHE handling macros / mappings
- *
- ******************************************************************************/
-/******************************************************************************
- *
- * Processor independent macros
- *
- ******************************************************************************/
-
-#define XCACHE_ENABLE_CACHE() \
- { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
-
-#define XCACHE_DISABLE_CACHE() \
- { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
-
-
-/******************************************************************************
- *
- * MicroBlaze case
- *
- * NOTE: Currently the following macros will only work on systems that contain
- * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
- * system is built using a xparameters.h file.
- *
- ******************************************************************************/
-
-#if defined __MICROBLAZE__
-
-/* Check if MicroBlaze data cache was built into the core.
- */
-#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
-# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
-# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
-# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
-
-# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
- microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
-
-#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
-# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
-#else
-# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
-#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
-
-#else
-# define XCACHE_ENABLE_DCACHE()
-# define XCACHE_DISABLE_DCACHE()
-# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
-#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
-
-
-/* Check if MicroBlaze instruction cache was built into the core.
- */
-#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
-# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
-# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
-
-# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
-
-# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
- microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
-
-#else
-# define XCACHE_ENABLE_ICACHE()
-# define XCACHE_DISABLE_ICACHE()
-#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
-
-
-/******************************************************************************
- *
- * PowerPC case
- *
- * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
- * specific memory region (0x80000001). Each bit (0-30) in the regions
- * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
- * range.
- *
- * regions --> cached address range
- * ------------|--------------------------------------------------
- * 0x80000000 | [0, 0x7FFFFFF]
- * 0x00000001 | [0xF8000000, 0xFFFFFFFF]
- * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
- *
- ******************************************************************************/
-
-#elif defined __PPC__
-
-#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
-#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
-#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
-#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
-
-#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
- XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
-
-#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
-
-#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
-
-
-/******************************************************************************
- *
- * Unknown processor / architecture
- *
- ******************************************************************************/
-
-#else
-/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* #ifndef XENV_STANDALONE_H */
-
- /**
- *@endcond
- */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/0/41b55f585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/0/41b55f585243001d18b399c1eb9b3628
deleted file mode 100644
index 973a707..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/0/41b55f585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,323 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xparameters_ps.h
-*
-* This file contains the address definitions for the hard peripherals
-* attached to the ARM Cortex A53 core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 5.00 pkp 05/29/14 First release
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 01/29/10 First release
-* 1.00a ecm 06/24/10 Moved the L1 and L2 specific function prototypes
-* to xil_cache_mach.h to give access to sophisticated users
-* 3.02a sdm 04/07/11 Updated Flush/InvalidateRange APIs to flush/invalidate
-* L1 and L2 caches in a single loop and used dsb, L2 sync
-* at the end of the loop.
-* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
-* APIs.
-* 3.07a asa 07/16/12 Corrected the L1 and L2 cache invalidation order.
-* 3.07a sgd 09/18/12 Corrected the L2 cache enable and disable sequence.
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-* 3.10a asa 05/13/13 Modified cache disable APIs. The L2 cache disable
-* operation was being done with L1 Data cache disabled. This is
-* fixed so that L2 cache disable operation happens independent of
-* L1 cache disable operation. This fixes CR #706464.
-* Changes are done to do a L2 cache sync (poll reg7_?cache_?sync).
-* This is done to fix the CR #700542.
-* 3.11a asa 09/23/13 Modified the Xil_DCacheFlushRange and
-* Xil_DCacheInvalidateRange to fix potential issues. Fixed other
-* relevant cache APIs to disable and enable back the interrupts.
-* This fixes CR #663885.
-* 3.11a asa 09/28/13 Made changes for L2 cache sync operation. It is found
-* out that for L2 cache flush/clean/invalidation by cache lines
-* does not need a cache sync as these are atomic nature. Similarly
-* figured out that for complete L2 cache flush/invalidation by way
-* we need to wait for some more time in a loop till the status
-* shows that the cache operation is completed.
-* 4.00 pkp 24/01/14 Modified Xil_DCacheInvalidateRange to fix the bug. Few
-* cache lines were missed to invalidate when unaligned address
-* invalidation was accommodated. That fixes CR #766768.
-* Also in Xil_L1DCacheInvalidate, while invalidating all L1D cache
-* stack memory which contains return address was invalidated. So
-* stack memory was flushed first and then L1D cache is invalidated.
-* This is done to fix CR #763829
-* 4.01 asa 05/09/14 Made changes in cortexa9/xil_cache.c to fix CR# 798230.
-* 4.02 pkp 06/27/14 Added notes to Xil_L1DCacheInvalidateRange function for
-* explanation of CR#785243
-* 5.00 kvn 12/15/14 Xil_L2CacheInvalidate was modified to fix CR# 838835. L2 Cache
-* has stack memory which has return address. Before invalidating
-* cache, stack memory was flushed first and L2 Cache is invalidated.
-* 5.01 pkp 05/12/15 Xil_DCacheInvalidateRange and Xil_DCacheFlushRange is modified
-* to remove unnecessary dsb in the APIs. Instead of using dsb
-* for L2 Cache, L2CacheSync has been used for each L2 cache line
-* and single dsb has been used for L1 cache. Also L2CacheSync is
-* added into Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate
-* and Xil_L2CacheInvalidate APIs are modified to flush the complete
-* stack instead of just System Stack
-* 5.03 pkp 10/07/15 L2 Cache functionalities are avoided for the OpenAMP slave
-* application(when USE_AMP flag is defined for BSP) as master CPU
-* would be utilizing L2 cache for its operation
-* 6.6 mus 12/07/17 Errata 753970 is not applicable for the PL130 cache controller
-* version r0p2, which is present in zynq. So,removed the handling
-* related to same.It fixes CR#989132.
-* 6.6 asa 16/01/18 Changes made in Xil_L1DCacheInvalidate and Xil_L2CacheInvalidate
-* routines to ensure the stack data flushed only when the respective
-* caches are enabled. This fixes CR-992023.
-* 7.5 mus 01/19/21 Implement workaround for errata#588369 in Xil_DCacheFlushRange.
-* It fixes CR#1086022.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xil_cache_l.h"
-#include "xil_io.h"
-#include "xpseudo_asm.h"
-#include "xparameters.h"
-#include "xreg_cortexa9.h"
-#include "xl2cc.h"
-#include "xil_errata.h"
-#include "xil_exception.h"
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#define IRQ_FIQ_MASK 0xC0U /* Mask IRQ and FIQ interrupts in cpsr */
-
-#ifdef __GNUC__
- extern s32 _stack_end;
- extern s32 __undef_stack;
-#endif
-
-#ifndef USE_AMP
-/****************************************************************************
-*
-* Access L2 Debug Control Register.
-*
-* @param Value, value to be written to Debug Control Register.
-*
-* @return None.
-*
-****************************************************************************/
-#ifdef __GNUC__
-static inline void Xil_L2WriteDebugCtrl(u32 Value)
-#else
-static void Xil_L2WriteDebugCtrl(u32 Value)
-#endif
-{
-#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DEBUG_CTRL_OFFSET, Value);
-#else
- (void)(Value);
-#endif
-}
-
-/****************************************************************************
-*
-* Perform L2 Cache Sync Operation.
-*
-* @return None.
-*
-****************************************************************************/
-#ifdef __GNUC__
-static inline void Xil_L2CacheSync(void)
-#else
-static void Xil_L2CacheSync(void)
-#endif
-{
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0U);
-}
-#endif
-/****************************************************************************/
-/**
-* @brief Enable the Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheEnable(void)
-{
- Xil_L1DCacheEnable();
-#ifndef USE_AMP
- Xil_L2CacheEnable();
-#endif
-}
-
-/****************************************************************************/
-/**
-* @brief Disable the Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheDisable(void)
-{
-#ifndef USE_AMP
- Xil_L2CacheDisable();
-#endif
- Xil_L1DCacheDisable();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the entire Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheInvalidate(void)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-#ifndef USE_AMP
- Xil_L2CacheInvalidate();
-#endif
- Xil_L1DCacheInvalidate();
-
- mtcpsr(currmask);
-}
-
-/*****************************************************************************/
-/**
-* @brief Invalidate a Data cache line. If the byte specified by the address
-* (adr) is cached by the Data cache, the cacheline containing that
-* byte is invalidated. If the cacheline is modified (dirty), the
-* modified contents are lost and are NOT written to the system memory
-* before the line is invalidated.
-*
-* @param adr: 32bit address of the data to be flushed.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_DCacheInvalidateLine(u32 adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-#ifndef USE_AMP
- Xil_L2CacheInvalidateLine(adr);
-#endif
- Xil_L1DCacheInvalidateLine(adr);
-
- mtcpsr(currmask);
-}
-
-
-/*****************************************************************************/
-/**
-* Invalidate the Data cache for the given address range.
-* If the bytes specified by the address range are cached by the Data
-* cache, the cachelines containing those bytes are invalidated. If
-* the cachelines are modified (dirty), the modified contents are lost
-* and NOT written to the system memory before the lines are
-* invalidated.
-*
-* In this function, if start address or end address is not aligned to
-* cache-line, particular cache-line containing unaligned start or end
-* address is flush first and then invalidated the others as
-* invalidating the same unaligned cache line may result into loss of
-* data. This issue raises few possibilities.
-*
-* If the address to be invalidated is not cache-line aligned, the
-* following choices are available:
-* 1. Invalidate the cache line when required and do not bother much
-* for the side effects. Though it sounds good, it can result in
-* hard-to-debug issues. The problem is, if some other variable are
-* allocated in the same cache line and had been recently updated
-* (in cache), the invalidation would result in loss of data.
-* 2. Flush the cache line first. This will ensure that if any other
-* variable present in the same cache line and updated recently are
-* flushed out to memory. Then it can safely be invalidated. Again it
-* sounds good, but this can result in issues. For example, when the
-* invalidation happens in a typical ISR (after a DMA transfer has
-* updated the memory), then flushing the cache line means, losing
-* data that were updated recently before the ISR got invoked.
-*
-* Linux prefers the second one. To have uniform implementation
-* (across standalone and Linux), the second option is implemented.
-* This being the case, following needs to be taken care of:
-* 1. Whenever possible, the addresses must be cache line aligned.
-* Please nore that, not just start address, even the end address must
-* be cache line aligned. If that is taken care of, this will always
-* work.
-* 2. Avoid situations where invalidation has to be done after the
-* data is updated by peripheral/DMA directly into the memory. It is
-* not tough to achieve (may be a bit risky). The common use case to
-* do invalidation is when a DMA happens. Generally for such use
-* cases, buffers can be allocated first and then start the DMA. The
-* practice that needs to be followed here is, immediately after
-* buffer allocation and before starting the DMA, do the invalidation.
-* With this approach, invalidation need not to be done after the DMA
-* transfer is over.
-*
-* This is going to always work if done carefully.
-* However, the concern is, there is no guarantee that invalidate has
-* not needed to be done after DMA is complete. For example, because
-* of some reasons if the first cache line or last cache line
-* (assuming the buffer in question comprises of multiple cache lines)
-* are brought into cache (between the time it is invalidated and DMA
-* completes) because of some speculative prefetching or reading data
-* for a variable present in the same cache line, then we will have to
-* invalidate the cache after DMA is complete.
-*
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
-{
- const u32 cacheline = 32U;
- u32 end;
- u32 tempadr = adr;
- u32 tempend;
- u32 currmask;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INVLD_PA_OFFSET);
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- end = tempadr + len;
- tempend = end;
- /* Select L1 Data cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
-
- if ((tempadr & (cacheline-1U)) != 0U) {
- tempadr &= (~(cacheline - 1U));
-
- Xil_L1DCacheFlushLine(tempadr);
-#ifndef USE_AMP
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
- Xil_L2CacheFlushLine(tempadr);
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- Xil_L2CacheSync();
-#endif
- tempadr += cacheline;
- }
- if ((tempend & (cacheline-1U)) != 0U) {
- tempend &= (~(cacheline - 1U));
-
- Xil_L1DCacheFlushLine(tempend);
-#ifndef USE_AMP
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
- Xil_L2CacheFlushLine(tempend);
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- Xil_L2CacheSync();
-#endif
- }
-
- while (tempadr < tempend) {
-#ifndef USE_AMP
- /* Invalidate L2 cache line */
- *L2CCOffset = tempadr;
- Xil_L2CacheSync();
-#endif
-
- /* Invalidate L1 Data cache line */
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_dc_line_mva_poc(tempadr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
- Reg = tempadr; }
-#endif
- tempadr += cacheline;
- }
- }
-
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the entire Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheFlush(void)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- Xil_L1DCacheFlush();
-#ifndef USE_AMP
- Xil_L2CacheFlush();
-#endif
- mtcpsr(currmask);
-}
-
-
-/****************************************************************************/
-/**
-* @brief Flush a Data cache line. If the byte specified by the address (adr)
-* is cached by the Data cache, the cacheline containing that byte is
-* invalidated. If the cacheline is modified (dirty), the entire
-* contents of the cacheline are written to system memory before the
-* line is invalidated.
-*
-* @param adr: 32bit address of the data to be flushed.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_DCacheFlushLine(u32 adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- Xil_L1DCacheFlushLine(adr);
-#ifndef USE_AMP
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
-
- Xil_L2CacheFlushLine(adr);
-
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- Xil_L2CacheSync();
-#endif
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the Data cache for the given address range.
-* If the bytes specified by the address range are cached by the
-* data cache, the cachelines containing those bytes are invalidated.
-* If the cachelines are modified (dirty), they are written to the
-* system memory before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be flushed.
-* @param len: Length of the range to be flushed in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheFlushRange(INTPTR adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- u32 currmask;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr &= ~(cacheline - 1U);
-#ifndef USE_AMP
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
-#endif
- while (LocalAddr < end) {
-
- /* Flush L1 Data cache line */
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
- Reg = LocalAddr; }
-#endif
-#ifndef USE_AMP
- /* Flush L2 cache line */
- *L2CCOffset = LocalAddr;
- Xil_L2CacheSync();
-#endif
- LocalAddr += cacheline;
- }
-#ifndef USE_AMP
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
-#endif
- }
- dsb();
- mtcpsr(currmask);
-}
-/****************************************************************************/
-/**
-* @brief Store a Data cache line. If the byte specified by the address (adr)
-* is cached by the Data cache and the cacheline is modified (dirty),
-* the entire contents of the cacheline are written to system memory.
-* After the store completes, the cacheline is marked as unmodified
-* (not dirty).
-*
-* @param adr: 32bit address of the data to be stored.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_DCacheStoreLine(u32 adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- Xil_L1DCacheStoreLine(adr);
-#ifndef USE_AMP
- Xil_L2CacheStoreLine(adr);
-#endif
- mtcpsr(currmask);
-}
-
-/***************************************************************************/
-/**
-* @brief Enable the instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ICacheEnable(void)
-{
- Xil_L1ICacheEnable();
-#ifndef USE_AMP
- Xil_L2CacheEnable();
-#endif
-}
-
-/***************************************************************************/
-/**
-* @brief Disable the instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ICacheDisable(void)
-{
-#ifndef USE_AMP
- Xil_L2CacheDisable();
-#endif
- Xil_L1ICacheDisable();
-}
-
-
-/****************************************************************************/
-/**
-* @brief Invalidate the entire instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ICacheInvalidate(void)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-#ifndef USE_AMP
- Xil_L2CacheInvalidate();
-#endif
- Xil_L1ICacheInvalidate();
-
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate an instruction cache line. If the instruction specified
-* by the address is cached by the instruction cache, the cacheline
-* containing that instruction is invalidated.
-*
-* @param adr: 32bit address of the instruction to be invalidated.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_ICacheInvalidateLine(u32 adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-#ifndef USE_AMP
- Xil_L2CacheInvalidateLine(adr);
-#endif
- Xil_L1ICacheInvalidateLine(adr);
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the instruction cache for the given address range.
-* If the instructions specified by the address range are cached by
-* the instrunction cache, the cachelines containing those
-* instructions are invalidated.
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INVLD_PA_OFFSET);
-
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Select cache L0 I-cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
-
- while (LocalAddr < end) {
-#ifndef USE_AMP
- /* Invalidate L2 cache line */
- *L2CCOffset = LocalAddr;
- dsb();
-#endif
-
- /* Invalidate L1 I-cache line */
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_ic_line_mva_pou(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
- Reg = LocalAddr; }
-#endif
-
- LocalAddr += cacheline;
- }
- }
-
- /* Wait for L1 and L2 invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Enable the level 1 Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1DCacheEnable(void)
-{
- register u32 CtrlReg;
-
- /* enable caches only if they are disabled */
-#ifdef __GNUC__
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
- CtrlReg = Reg; }
-#endif
- if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) {
- return;
- }
-
- /* clean and invalidate the Data cache */
- Xil_L1DCacheInvalidate();
-
- /* enable the Data cache */
- CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/***************************************************************************/
-/**
-* @brief Disable the level 1 Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1DCacheDisable(void)
-{
- register u32 CtrlReg;
-
- /* clean and invalidate the Data cache */
- Xil_L1DCacheFlush();
-
-#ifdef __GNUC__
- /* disable the Data cache */
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
- CtrlReg = Reg; }
-#endif
-
- CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the level 1 Data cache.
-*
-* @return None.
-*
-* @note In Cortex A9, there is no cp instruction for invalidating
-* the whole D-cache. This function invalidates each line by
-* set/way.
-*
-****************************************************************************/
-void Xil_L1DCacheInvalidate(void)
-{
- register u32 CsidReg, C7Reg;
- u32 CacheSize, LineSize, NumWays;
- u32 Way, WayIndex, Set, SetIndex, NumSet;
- u32 currmask;
-
-#ifdef __GNUC__
- u32 stack_start,stack_end,stack_size;
- register u32 CtrlReg;
-#endif
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
-#ifdef __GNUC__
- stack_end = (u32)&_stack_end;
- stack_start = (u32)&__undef_stack;
- stack_size=stack_start-stack_end;
-
- /* Check for the cache status. If cache is enabled, then only
- * flush stack memory to save return address. If cache is disabled,
- * don't flush anything as it might result in flushing stale date into
- * memory which is undesirable.
- * */
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) {
- Xil_DCacheFlushRange(stack_end, stack_size);
- }
-#endif
-
- /* Select cache level 0 and D cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
-
-#ifdef __GNUC__
- CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID);
- CsidReg = Reg; }
-#endif
- /* Determine Cache Size */
- CacheSize = (CsidReg >> 13U) & 0x1FFU;
- CacheSize +=1U;
- CacheSize *=128U; /* to get number of bytes */
-
- /* Number of Ways */
- NumWays = (CsidReg & 0x3ffU) >> 3U;
- NumWays += 1U;
-
- /* Get the cacheline size, way size, index size from csidr */
- LineSize = (CsidReg & 0x07U) + 4U;
-
- NumSet = CacheSize/NumWays;
- NumSet /= (0x00000001U << LineSize);
-
- Way = 0U;
- Set = 0U;
-
- /* Invalidate all the cachelines */
- for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set;
-
- /* Invalidate by Set/Way */
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_dc_line_sw(C7Reg);
-#else
- /*mtcp(XREG_CP15_INVAL_DC_LINE_SW, C7Reg), */
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_DC_LINE_SW);
- Reg = C7Reg; }
-#endif
- Set += (0x00000001U << LineSize);
- }
- Set=0U;
- Way += 0x40000000U;
- }
-
- /* Wait for L1 invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate a level 1 Data cache line. If the byte specified by the
-* address (Addr) is cached by the Data cache, the cacheline
-* containing that byte is invalidated. If the cacheline is modified
-* (dirty), the modified contents are lost and are NOT written to
-* system memory before the line is invalidated.
-*
-* @param adr: 32bit address of the data to be invalidated.
-*
-* @return None.
-*
-* @note The bottom 5 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L1DCacheInvalidateLine(u32 adr)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
- mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU)));
-
- /* Wait for L1 invalidate to complete */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the level 1 Data cache for the given address range.
-* If the bytes specified by the address range are cached by the Data
-* cache, the cachelines containing those bytes are invalidated. If the
-* cachelines are modified (dirty), the modified contents are lost and
-* NOT written to the system memory before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1DCacheInvalidateRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Select cache L0 D-cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
-
- while (LocalAddr < end) {
-
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_dc_line_mva_poc(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
- Reg = LocalAddr; }
-#endif
- LocalAddr += cacheline;
- }
- }
-
- /* Wait for L1 invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the level 1 Data cache.
-*
-* @return None.
-*
-* @note In Cortex A9, there is no cp instruction for flushing
-* the whole D-cache. Need to flush each line.
-*
-****************************************************************************/
-void Xil_L1DCacheFlush(void)
-{
- register u32 CsidReg, C7Reg;
- u32 CacheSize, LineSize, NumWays;
- u32 Way;
- u32 WayIndex, Set, SetIndex, NumSet;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- /* Select cache level 0 and D cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
-
-#ifdef __GNUC__
- CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID);
- CsidReg = Reg; }
-#endif
-
- /* Determine Cache Size */
-
- CacheSize = (CsidReg >> 13U) & 0x1FFU;
- CacheSize +=1U;
- CacheSize *=128U; /* to get number of bytes */
-
- /* Number of Ways */
- NumWays = (CsidReg & 0x3ffU) >> 3U;
- NumWays += 1U;
-
- /* Get the cacheline size, way size, index size from csidr */
- LineSize = (CsidReg & 0x07U) + 4U;
-
- NumSet = CacheSize/NumWays;
- NumSet /= (0x00000001U << LineSize);
-
- Way = 0U;
- Set = 0U;
-
- /* Invalidate all the cachelines */
- for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set;
- /* Flush by Set/Way */
-
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_clean_inval_dc_line_sw(C7Reg);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_SW);
- Reg = C7Reg; }
-#endif
- Set += (0x00000001U << LineSize);
- }
- Set = 0U;
- Way += 0x40000000U;
- }
-
- /* Wait for L1 flush to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush a level 1 Data cache line. If the byte specified by the
-* address (adr) is cached by the Data cache, the cacheline containing
-* that byte is invalidated. If the cacheline is modified (dirty), the
-* entire contents of the cacheline are written to system memory
-* before the line is invalidated.
-*
-* @param adr: 32bit address of the data to be flushed.
-*
-* @return None.
-*
-* @note The bottom 5 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L1DCacheFlushLine(u32 adr)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
- mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU)));
-
- /* Wait for L1 flush to complete */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the level 1 Data cache for the given address range.
-* If the bytes specified by the address range are cached by the Data
-* cache, the cacheline containing those bytes are invalidated. If the
-* cachelines are modified (dirty), they are written to system memory
-* before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be flushed.
-* @param len: Length of the range to be flushed in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1DCacheFlushRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Select cache L0 D-cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
-
- while (LocalAddr < end) {
-
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
- Reg = LocalAddr; }
-#endif
- LocalAddr += cacheline;
- }
- }
-
- /* Wait for L1 flush to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Store a level 1 Data cache line. If the byte specified by the
-* address (adr) is cached by the Data cache and the cacheline is
-* modified (dirty), the entire contents of the cacheline are written
-* to system memory. After the store completes, the cacheline is
-* marked as unmodified (not dirty).
-*
-* @param adr: Address to be stored.
-*
-* @return None.
-*
-* @note The bottom 5 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L1DCacheStoreLine(u32 adr)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
- mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1FU)));
-
- /* Wait for L1 store to complete */
- dsb();
-}
-
-
-/****************************************************************************/
-/**
-* @brief Enable the level 1 instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1ICacheEnable(void)
-{
- register u32 CtrlReg;
-
- /* enable caches only if they are disabled */
-#ifdef __GNUC__
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
- CtrlReg = Reg; }
-#endif
- if ((CtrlReg & (XREG_CP15_CONTROL_I_BIT)) != 0U) {
- return;
- }
-
- /* invalidate the instruction cache */
- mtcp(XREG_CP15_INVAL_IC_POU, 0U);
-
- /* enable the instruction cache */
- CtrlReg |= (XREG_CP15_CONTROL_I_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/****************************************************************************/
-/**
-* @brief Disable level 1 the instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1ICacheDisable(void)
-{
- register u32 CtrlReg;
-
- dsb();
-
- /* invalidate the instruction cache */
- mtcp(XREG_CP15_INVAL_IC_POU, 0U);
-
- /* disable the instruction cache */
-#ifdef __GNUC__
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
- CtrlReg = Reg; }
-#endif
- CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the entire level 1 instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1ICacheInvalidate(void)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
- /* invalidate the instruction cache */
- mtcp(XREG_CP15_INVAL_IC_POU, 0U);
-
- /* Wait for L1 invalidate to complete */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate a level 1 instruction cache line. If the instruction
-* specified by the address is cached by the instruction cache, the
-* cacheline containing that instruction is invalidated.
-*
-* @param adr: 32bit address of the instruction to be invalidated.
-*
-* @return None.
-*
-* @note The bottom 5 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L1ICacheInvalidateLine(u32 adr)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
- mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1FU)));
-
- /* Wait for L1 invalidate to complete */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the level 1 instruction cache for the given address
-* range. If the instrucions specified by the address range are cached
-* by the instruction cache, the cacheline containing those bytes are
-* invalidated.
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1ICacheInvalidateRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Select cache L0 I-cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
-
- while (LocalAddr < end) {
-
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_ic_line_mva_pou(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
- Reg = LocalAddr; }
-#endif
- LocalAddr += cacheline;
- }
- }
-
- /* Wait for L1 invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-#ifndef USE_AMP
-/****************************************************************************/
-/**
-* @brief Enable the L2 cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L2CacheEnable(void)
-{
- register u32 L2CCReg;
-
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
-
- /* only enable if L2CC is currently disabled */
- if ((L2CCReg & 0x01U) == 0U) {
- /* set up the way size and latencies */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
- XPS_L2CC_AUX_CNTRL_OFFSET);
- L2CCReg &= XPS_L2CC_AUX_REG_ZERO_MASK;
- L2CCReg |= XPS_L2CC_AUX_REG_DEFAULT_MASK;
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_AUX_CNTRL_OFFSET,
- L2CCReg);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_TAG_RAM_CNTRL_OFFSET,
- XPS_L2CC_TAG_RAM_DEFAULT_MASK);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DATA_RAM_CNTRL_OFFSET,
- XPS_L2CC_DATA_RAM_DEFAULT_MASK);
-
- /* Clear the pending interrupts */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
- XPS_L2CC_ISR_OFFSET);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_IAR_OFFSET, L2CCReg);
-
- Xil_L2CacheInvalidate();
- /* Enable the L2CC */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
- XPS_L2CC_CNTRL_OFFSET);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
- (L2CCReg | (0x01U)));
-
- Xil_L2CacheSync();
- /* synchronize the processor */
- dsb();
-
- }
-}
-
-/****************************************************************************/
-/**
-* @brief Disable the L2 cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L2CacheDisable(void)
-{
- register u32 L2CCReg;
-
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
-
- if((L2CCReg & 0x1U) != 0U) {
-
- /* Clean and Invalidate L2 Cache */
- Xil_L2CacheFlush();
-
- /* Disable the L2CC */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
- (L2CCReg & (~0x01U)));
- /* Wait for the cache operations to complete */
-
- dsb();
- }
-}
-
-/*****************************************************************************/
-/**
-* @brief Invalidate the entire level 2 cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L2CacheInvalidate(void)
-{
- #ifdef __GNUC__
- u32 stack_start,stack_end,stack_size;
- register u32 L2CCReg;
- stack_end = (u32)&_stack_end;
- stack_start = (u32)&__undef_stack;
- stack_size=stack_start-stack_end;
-
- /* Check for the cache status. If cache is enabled, then only
- * flush stack memory to save return address. If cache is disabled,
- * don't flush anything as it might result in flushing stale date into
- * memory which is undesirable.
- */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
- if ((L2CCReg & 0x01U) != 0U) {
- /*Flush stack memory to save return address*/
- Xil_DCacheFlushRange(stack_end, stack_size);
- }
-
- #endif
- u32 ResultDCache;
- /* Invalidate the caches */
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET,
- 0x0000FFFFU);
- ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)
- & 0x0000FFFFU;
- while(ResultDCache != (u32)0U) {
- ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)
- & 0x0000FFFFU;
- }
-
- /* Wait for the invalidate to complete */
- Xil_L2CacheSync();
-
- /* synchronize the processor */
- dsb();
-}
-
-/*****************************************************************************/
-/**
-* @brief Invalidate a level 2 cache line. If the byte specified by the
-* address (adr) is cached by the Data cache, the cacheline containing
-* that byte is invalidated. If the cacheline is modified (dirty),
-* the modified contents are lost and are NOT written to system memory
-* before the line is invalidated.
-*
-* @param adr: 32bit address of the data/instruction to be invalidated.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L2CacheInvalidateLine(u32 adr)
-{
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, (u32)adr);
- /* synchronize the processor */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the level 2 cache for the given address range.
-* If the bytes specified by the address range are cached by the L2
-* cache, the cacheline containing those bytes are invalidated. If the
-* cachelines are modified (dirty), the modified contents are lost and
-* are NOT written to system memory before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L2CacheInvalidateRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INVLD_PA_OFFSET);
-
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
-
- while (LocalAddr < end) {
- *L2CCOffset = LocalAddr;
- Xil_L2CacheSync();
- LocalAddr += cacheline;
- }
-
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- }
-
- /* synchronize the processor */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the entire level 2 cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L2CacheFlush(void)
-{
- u32 ResultL2Cache;
-
- /* Flush the caches */
-
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
-
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET,
- 0x0000FFFFU);
- ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
- & 0x0000FFFFU;
-
- while(ResultL2Cache != (u32)0U) {
- ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
- & 0x0000FFFFU;
- }
-
- Xil_L2CacheSync();
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
-
- /* synchronize the processor */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Flush a level 2 cache line. If the byte specified by the address
-* (adr) is cached by the L2 cache, the cacheline containing that
-* byte is invalidated. If the cacheline is modified (dirty), the
-* entire contents of the cacheline are written to system memory
-* before the line is invalidated.
-*
-* @param adr: 32bit address of the data/instruction to be flushed.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L2CacheFlushLine(u32 adr)
-{
-#ifdef CONFIG_PL310_ERRATA_588369
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, adr);
-#else
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET, adr);
-#endif
- /* synchronize the processor */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the level 2 cache for the given address range.
-* If the bytes specified by the address range are cached by the L2
-* cache, the cacheline containing those bytes are invalidated. If the
-* cachelines are modified (dirty), they are written to the system
-* memory before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be flushed.
-* @param len: Length of the range to be flushed in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L2CacheFlushRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
-
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
-
- while (LocalAddr < end) {
- *L2CCOffset = LocalAddr;
- Xil_L2CacheSync();
- LocalAddr += cacheline;
- }
-
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- }
- /* synchronize the processor */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Store a level 2 cache line. If the byte specified by the address
-* (adr) is cached by the L2 cache and the cacheline is modified
-* (dirty), the entire contents of the cacheline are written to
-* system memory. After the store completes, the cacheline is marked
-* as unmodified (not dirty).
-*
-* @param adr: 32bit address of the data/instruction to be stored.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L2CacheStoreLine(u32 adr)
-{
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
- /* synchronize the processor */
- dsb();
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/0/60f7de585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/0/60f7de585243001d18b399c1eb9b3628
deleted file mode 100644
index 684c01f..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/0/60f7de585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,112 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm_rvct.h
-*
-* This header file contains macros for using __inline assembler code. It is
-* written specifically for RVCT.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 11/18/09 First Release
-* 7.2 asa 04/03/20 Renamed the str macro to strw.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a ssb 12/22/11 First release based on the XPS/AXI XADC driver
-* 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xparameters.h"
-#include "xadcps.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-extern XAdcPs_Config XAdcPs_ConfigTable[];
-
-/*****************************************************************************/
-/**
-*
-* This function looks up the device configuration based on the unique device ID.
-* The table XAdcPs_ConfigTable contains the configuration info for each device
-* in the system.
-*
-* @param DeviceId contains the ID of the device for which the
-* device configuration pointer is to be returned.
-*
-* @return
-* - A pointer to the configuration found.
-* - NULL if the specified device ID was not found.
-*
-* @note None.
-*
-******************************************************************************/
-XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId)
-{
- XAdcPs_Config *CfgPtr = NULL;
- u32 Index;
-
- for (Index = 0U; Index < 1U; Index++) {
- if (XAdcPs_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XAdcPs_ConfigTable[Index];
- break;
- }
- }
-
- return CfgPtr;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/0/b0c8d1535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/0/b0c8d1535243001d18b399c1eb9b3628
deleted file mode 100644
index e79ba0d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/0/b0c8d1535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,788 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xqspips.h
-* @addtogroup qspips_v3_9
-* @{
-* @details
-*
-* This file contains the implementation of the XQspiPs driver. It supports only
-* master mode. User documentation for the driver functions is contained in this
-* file in the form of comment blocks at the front of each function.
-*
-* A QSPI device connects to an QSPI bus through a 4-wire serial interface.
-* The QSPI bus is a full-duplex, synchronous bus that facilitates communication
-* between one master and one slave. The device is always full-duplex,
-* which means that for every byte sent, one is received, and vice-versa.
-* The master controls the clock, so it can regulate when it wants to
-* send or receive data. The slave is under control of the master, it must
-* respond quickly since it has no control of the clock and must send/receive
-* data as fast or as slow as the master does.
-*
-* Linear Mode
-* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller�s
-* functionality by adding a linear addressing scheme that allows the SPI flash
-* memory subsystem to behave like a typical ROM device. The new feature hides
-* the normal SPI protocol from a master reading from the SPI flash memory. The
-* feature improves both the user friendliness and the overall read memory
-* throughput over that of the current Quad-SPI Controller by lessening the
-* amount of software overheads required and by the use of the faster AXI
-* interface.
-*
-* Initialization & Configuration
-*
-* The XQspiPs_Config structure is used by the driver to configure itself. This
-* configuration structure is typically created by the tool-chain based on HW
-* build properties.
-*
-* To support multiple runtime loading and initialization strategies employed by
-* various operating systems, the driver instance can be initialized in the
-* following way:
-* - XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find
-* static configuration structure defined in xqspips_g.c. This is setup
-* by the tools. For some operating systems the config structure will be
-* initialized by the software and this call is not needed.
-* - XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-* configuration structure provided by the caller. If running in a system
-* with address translation, the provided virtual memory base address
-* replaces the physical address present in the configuration structure.
-*
-* Multiple Masters
-*
-* More than one master can exist, but arbitration is the responsibility of
-* the higher layer software. The device driver does not perform any type of
-* arbitration.
-*
-* Modes of Operation
-*
-* There are four modes to perform a data transfer and the selection of a mode
-* is based on Chip Select(CS) and Start. These two options individually, can
-* be controlled either by software(Manual) or hardware(Auto).
-* - Auto CS: Chip select is automatically asserted as soon as the first word
-* is written into the TXFIFO and de asserted when the TXFIFO becomes
-* empty
-* - Manual CS: Software must assert and de assert CS.
-* - Auto Start: Data transmission starts as soon as there is data in the
-* TXFIFO and stalls when the TXFIFO is empty
-* - Manual Start: Software must start data transmission at the beginning of
-* the transaction or whenever the TXFIFO has become empty
-*
-* The preferred combination is Manual CS and Auto Start.
-* In this combination, the software asserts CS before loading any data into
-* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
-* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
-* data is available. If no further data, software disables CS.
-*
-* Risks/challenges of other combinations:
-* - Manual CS and Manual Start: Manual Start bit should be set after each
-* TXFIFO write otherwise there could be a race condition where the TXFIFO
-* becomes empty before the new word is written. In that case the
-* transmission stops.
-* - Auto CS with Manual or Auto Start: It is very difficult for software to
-* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted.
-* This results in a single transaction to be split into multiple pieces each
-* with its own chip select. This will result in garbage data to be sent.
-*
-* Interrupts
-*
-* The user must connect the interrupt handler of the driver,
-* XQspiPs_InterruptHandler, to an interrupt system such that it will be
-* called when an interrupt occurs. This function does not save and restore
-* the processor context such that the user must provide this processing.
-*
-* The driver handles the following interrupts:
-* - Data Transmit Register/FIFO Underflow
-* - Data Receive Register/FIFO Not Empty
-* - Data Transmit Register/FIFO Overwater
-* - Data Receive Register/FIFO Overrun
-*
-* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
-* QSPI device has transmitted the data available to transmit, and now its data
-* register and FIFO is ready to accept more data. The driver uses this
-* interrupt to indicate progress while sending data. The driver may have
-* more data to send, in which case the data transmit register and FIFO is
-* filled for subsequent transmission. When this interrupt arrives and all
-* the data has been sent, the driver invokes the status callback with a
-* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
-* all data has been sent.
-*
-* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
-* as slave, the QSPI device was required to transmit but there was no data
-* available to transmit in the transmit register (or FIFO). This may not
-* be an error if the master is not expecting data. But in the case where
-* the master is expecting data, this serves as a notification of such a
-* condition. The driver reports this condition to the upper layer
-* software through the status handler.
-*
-* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI
-* device received data and subsequently dropped the data because the data
-* receive register and FIFO was full. The driver reports this condition to the
-* upper layer software through the status handler. This likely indicates a
-* problem with the higher layer protocol, or a problem with the slave
-* performance.
-*
-*
-* Polled Operation
-*
-* Transfer in polled mode is supported through a separate interface function
-* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
-* this function blocks until all data has been sent/received.
-*
-* Device Busy
-*
-* Some operations are disallowed when the device is busy. The driver tracks
-* whether a device is busy. The device is considered busy when a data transfer
-* request is outstanding, and is considered not busy only when that transfer
-* completes (or is aborted with a mode fault error).
-*
-* Device Configuration
-*
-* The device can be configured in various ways during the FPGA implementation
-* process. Configuration parameters are stored in the xqspips_g.c file or
-* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry
-* contains configuration information for an QSPI device, including the base
-* address for the device.
-*
-* RTOS Independence
-*
-* This driver is intended to be RTOS and processor independent. It works with
-* physical addresses only. Any needs for dynamic memory management, threads or
-* thread mutual exclusion, virtual memory, or cache control must be satisfied
-* by the layer above this driver.
-*
-* NOTE: This driver was always tested with endianness set to little-endian.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
-* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
-* in xparameters.h
-* 2.00a kka 07/25/12 Added a few register defines for CR 670297
-* Removed code related to mode fault for CR 671468
-* The XQspiPs_SetSlaveSelect has been modified to remove
-* the argument of the slave select as the QSPI controller
-* only supports one slave.
-* XQspiPs_GetSlaveSelect API has been removed
-* Added a flag ShiftReadData to the instance structure
-*. and is used in the XQspiPs_GetReadData API.
-* The ShiftReadData Flag indicates whether the data
-* read from the Rx FIFO needs to be shifted
-* in cases where the data is less than 4 bytes
-* Removed the selection for the following options:
-* Master mode (XQSPIPS_MASTER_OPTION) and
-* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
-* as the QSPI driver supports the Master mode
-* and Flash Interface mode and doesnot support
-* Slave mode or the legacy mode.
-* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
-* APIs so that the last argument (IsInst) specifying whether
-* it is instruction or data has been removed. The first byte
-* in the SendBufPtr argument of these APIs specify the
-* instruction to be sent to the Flash Device.
-* This version of the driver fixes CRs 670197/663787/
-* 670297/671468.
-* Added the option for setting the Holdb_dr bit in the
-* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
-* is the option to be used for setting this bit in the
-* configuration register.
-* The XQspiPs_PolledTransfer function has been updated
-* to fill the data to fifo depth.
-* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
-* Added macros for Set/Get Rx Watermark. Changed QSPI
-* Enable/Disable macro argument from BaseAddress to
-* Instance Pointer. Added DelayNss argument to SetDelays
-* and GetDelays API's.
-* Created macros XQspiPs_IsManualStart and
-* XQspiPs_IsManualChipSelect.
-* Changed QSPI transfer logic for polled and interrupt
-* modes to be based on filled tx fifo count and receive
-* based on it. RXNEMPTY interrupt is not used.
-* Added assertions to XQspiPs_LqspiRead function.
-* SetDelays and GetDelays API's include DelayNss parameter.
-* Added defines for DelayNss,Rx Watermark,Interrupts
-* which need write to clear. Removed Read zeros mask from
-* LQSPI Config register. Renamed Fixed burst error to
-* data FSM error in LQSPI Status register.
-*
-* 2.02a hk 05/07/13 Added ConnectionMode to config structure.
-* Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
-* Added enable and disable to the XQspiPs_LqspiRead() function
-* Removed XQspi_Reset() in Set_Options() function when
-* LQSPI_MODE_OPTION is set.
-* Added instructions for bank selection, die erase and
-* flag status register to the flash instruction table
-* Handling for instructions not in flash instruction
-* table added. Checking for Tx FIFO empty when switching from
-* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
-* byte count 3 (spansion), instruction size and TXD register
-* changed accordingly. CR# 712502 and 703869.
-* Added prefix to constant definitions for ConnectionMode
-* Added (\#ifdef linear base address) in the Linear read function.
-* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to
-* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
-* XQspiPs_LqspiRead function. Fix for CR#718141.
-*
-* 2.03a hk 09/17/13 Modified polled and interrupt transfers to make use of
-* thresholds. This is to improve performance.
-* Added API's for QSPI reset and
-* linear mode initialization for boot.
-* Added RX and TX threshold reset to one in XQspiPs_Abort.
-* Added RX threshold reset(1) after transfer in polled and
-* interrupt transfers. Made changes to make sure threshold
-* change is done only when no transfer is in progress.
-* Updated linear init API for parallel and stacked modes.
-* CR#737760.
-* 3.1 hk 08/13/14 When writing to the configuration register, set/reset
-* required bits leaving reserved bits untouched. CR# 796813.
-* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
-* controller does not update FIFO status flags as expected
-* when thresholds are used.
-* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
-* to remove compilation warnings. CR# 868893.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/05/17 Modified Comment lines in functions of qspips
-* examples to recognize it as documentation block
-* and modified filename tag in
-* xqspips_dual_flash_stack_lqspi_example.c to include it in
-* doxygen examples.
-* 3.4 nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file
-* 3.5 tjs 08/21/18 Fixed compilation warnings for the ARMCC.
-* 3.5 tjs 07/16/18 Added support for low density ISSI flash parts.
-* 3.6 akm 03/28/19 Fixed memory leak issue while reading from qspi.(CR#1016357)
-* 3.6 akm 04/15/19 Modified FlashQuadEnable, FlashWrie and FlashErase APIs,
-* to wait for the on going operation to complete before
-* performing the next operation.
-* 3.6 akm 04/15/19 Modified the mask in XQspiPs_GetReadData() API to retrieve
-* configuration register values of both the Flashes in dual
-* parellel connection.
-* 3.7 akm 11/19/19 Fixed Coverity unused value warning in XQspiPs_PolledTransfer()
-* and XQspiPs_Transfer() APIs.
-* 3.7 akm 03/19/20 Modified XQspiPs_PolledTransfer(), XQspiPs_Transfer() and
-* XQspiPs_InterruptHandler() APIs to fill TX FIFO with valid
-* data when RX buffer is not NULL.
-* 3.8 akm 09/02/20 Updated the Makefile to support parallel make execution.
-*
-*
-*
-******************************************************************************/
-#ifndef XQSPIPS_H /* prevent circular inclusions */
-#define XQSPIPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xqspips_hw.h"
-#include
-
-/************************** Constant Definitions *****************************/
-
-/** @name Configuration options
- *
- * The following options are supported to enable/disable certain features of
- * an QSPI device. Each of the options is a bit mask, so more than one may be
- * specified.
- *
- *
- * The Active Low Clock option configures the device's clock polarity.
- * Setting this option means the clock is active low and the SCK signal idles
- * high. By default, the clock is active high and SCK idles low.
- *
- * The Clock Phase option configures the QSPI device for one of two
- * transfer formats. A clock phase of 0, the default, means data is valid on
- * the first SCK edge (rising or falling) after the slave select (SS) signal
- * has been asserted. A clock phase of 1 means data is valid on the second SCK
- * edge (rising or falling) after SS has been asserted.
- *
- *
- * The QSPI Force Slave Select option is used to enable manual control of
- * the slave select signal.
- * 0: The SPI_SS signal is controlled by the QSPI controller during
- * transfers. (Default)
- * 1: The SPI_SS signal is forced active (driven low) regardless of any
- * transfers in progress.
- *
- * NOTE: The driver will handle setting and clearing the Slave Select when
- * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
- * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the
- * processor cannot empty and refill the FIFOs before the TX FIFO is empty
- * When the QSPI hardware is controlling the Slave Select signals, this
- * will cause slave to be de-selected and terminate the transfer.
- *
- * The Manual Start option is used to enable manual control of
- * the Start command to perform data transfer.
- * 0: The Start command is controlled by the QSPI controller during
- * transfers(Default). Data transmission starts as soon as there is data in
- * the TXFIFO and stalls when the TXFIFO is empty
- * 1: The Start command must be issued by software to perform data transfer.
- * Bit 15 of Configuration register is used to issue Start command. This bit
- * must be set whenever TXFIFO is filled with new data.
- *
- * NOTE: The driver will set the Manual Start Enable bit in Configuration
- * Register, if Manual Start option is selected. Software will issue
- * Manual Start command whenever TXFIFO is filled with data. When there is
- * no further data, driver will clear the Manual Start Enable bit.
- *
- * @{
- */
-#define XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2 /**< Active Low Clock option */
-#define XQSPIPS_CLK_PHASE_1_OPTION 0x4 /**< Clock Phase one option */
-#define XQSPIPS_FORCE_SSELECT_OPTION 0x10 /**< Force Slave Select */
-#define XQSPIPS_MANUAL_START_OPTION 0x20 /**< Manual Start enable */
-#define XQSPIPS_LQSPI_MODE_OPTION 0x80 /**< Linear QPSI mode */
-#define XQSPIPS_HOLD_B_DRIVE_OPTION 0x100 /**< Drive HOLD_B Pin */
-/*@}*/
-
-
-/** @name QSPI Clock Prescaler options
- * The QSPI Clock Prescaler Configuration bits are used to program master mode
- * bit rate. The bit rate can be programmed in divide-by-two decrements from
- * pclk/2 to pclk/256.
- *
- * @{
- */
-#define XQSPIPS_CLK_PRESCALE_2 0x00 /**< PCLK/2 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_4 0x01 /**< PCLK/4 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_8 0x02 /**< PCLK/8 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_16 0x03 /**< PCLK/16 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_32 0x04 /**< PCLK/32 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_64 0x05 /**< PCLK/64 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_128 0x06 /**< PCLK/128 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_256 0x07 /**< PCLK/256 Prescaler */
-
-/*@}*/
-
-
-/** @name Callback events
- *
- * These constants specify the handler events that are passed to
- * a handler from the driver. These constants are not bit masks such that
- * only one will be passed at a time to the handler.
- *
- * @{
- */
-#define XQSPIPS_EVENT_TRANSFER_DONE 2 /**< Transfer done */
-#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
-#define XQSPIPS_EVENT_RECEIVE_OVERRUN 4 /**< Receive data loss because
- * RX FIFO full
- */
-/*@}*/
-
-/** @name Flash commands
- *
- * The following constants define most of the commands supported by flash
- * devices. Users can add more commands supported by the flash devices
- *
- * @{
- */
-#define XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */
-#define XQSPIPS_FLASH_OPCODE_PP 0x02 /* Page program */
-#define XQSPIPS_FLASH_OPCODE_NORM_READ 0x03 /* Normal read data bytes */
-#define XQSPIPS_FLASH_OPCODE_WRDS 0x04 /* Write disable */
-#define XQSPIPS_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */
-#define XQSPIPS_FLASH_OPCODE_WREN 0x06 /* Write enable */
-#define XQSPIPS_FLASH_OPCODE_FAST_READ 0x0B /* Fast read data bytes */
-#define XQSPIPS_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */
-#define XQSPIPS_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */
-#define XQSPIPS_FLASH_OPCODE_DUAL_READ 0x3B /* Dual read data bytes */
-#define XQSPIPS_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */
-#define XQSPIPS_FLASH_OPCODE_QUAD_READ 0x6B /* Quad read data bytes */
-#define XQSPIPS_FLASH_OPCODE_ERASE_SUS 0x75 /* Erase suspend */
-#define XQSPIPS_FLASH_OPCODE_ERASE_RES 0x7A /* Erase resume */
-#define XQSPIPS_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */
-#define XQSPIPS_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */
-#define XQSPIPS_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/
-#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */
-#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */
-#define XQSPIPS_FLASH_OPCODE_BRWR 0x17 /* Bank Register Write */
-#define XQSPIPS_FLASH_OPCODE_BRRD 0x16 /* Bank Register Read */
-/* Extende Address Register Write - Micron's equivalent of Bank Register */
-#define XQSPIPS_FLASH_OPCODE_EARWR 0xC5
-/* Extende Address Register Read - Micron's equivalent of Bank Register */
-#define XQSPIPS_FLASH_OPCODE_EARRD 0xC8
-#define XQSPIPS_FLASH_OPCODE_DIE_ERASE 0xC4
-#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR 0x70
-#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR 0x50
-#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG 0xE8 /* Lock Reg Read */
-#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG 0xE5 /* Lock Reg Write */
-
-/*@}*/
-
-/** @name Instruction size
- *
- * The following constants define numbers 1 to 4.
- * Used to identify whether TXD0,1,2 or 3 is to be used.
- *
- * @{
- */
-#define XQSPIPS_SIZE_ONE 1
-#define XQSPIPS_SIZE_TWO 2
-#define XQSPIPS_SIZE_THREE 3
-#define XQSPIPS_SIZE_FOUR 4
-
-/*@}*/
-
-/** @name ConnectionMode
- *
- * The following constants are the possible values of ConnectionMode in
- * Config structure.
- *
- * @{
- */
-#define XQSPIPS_CONNECTION_MODE_SINGLE 0
-#define XQSPIPS_CONNECTION_MODE_STACKED 1
-#define XQSPIPS_CONNECTION_MODE_PARALLEL 2
-
-/*@}*/
-
-/** @name FIFO threshold value
- *
- * This is the Rx FIFO threshold (in words) that was found to be most
- * optimal in terms of performance
- *
- * @{
- */
-#define XQSPIPS_RXFIFO_THRESHOLD_OPT 32
-
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-/**
- * The handler data type allows the user to define a callback function to
- * handle the asynchronous processing for the QSPI device. The application
- * using this driver is expected to define a handler of this type to support
- * interrupt driven mode. The handler executes in an interrupt context, so
- * only minimal processing should be performed.
- *
- * @param CallBackRef is the callback reference passed in by the upper
- * layer when setting the callback functions, and passed back to
- * the upper layer when the callback is invoked. Its type is
- * not important to the driver, so it is a void pointer.
- * @param StatusEvent holds one or more status events that have occurred.
- * See the XQspiPs_SetStatusHandler() for details on the status
- * events that can be passed in the callback.
- * @param ByteCount indicates how many bytes of data were successfully
- * transferred. This may be less than the number of bytes
- * requested if the status event indicates an error.
- */
-typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
- unsigned ByteCount);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of the device */
- u32 InputClockHz; /**< Input clock frequency */
- u8 ConnectionMode; /**< Single, Stacked and Parallel mode */
-} XQspiPs_Config;
-
-/**
- * The XQspiPs driver instance data. The user is required to allocate a
- * variable of this type for every QSPI device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XQspiPs_Config Config; /**< Configuration structure */
- u32 IsReady; /**< Device is initialized and ready */
-
- u8 *SendBufferPtr; /**< Buffer to send (state) */
- u8 *RecvBufferPtr; /**< Buffer to receive (state) */
- int RequestedBytes; /**< Number of bytes to transfer (state) */
- int RemainingBytes; /**< Number of bytes left to transfer(state) */
- u32 IsBusy; /**< A transfer is in progress (state) */
- XQspiPs_StatusHandler StatusHandler;
- void *StatusRef; /**< Callback reference for status handler */
- u32 ShiftReadData; /**< Flag to indicate whether the data
- * read from the Rx FIFO needs to be shifted
- * in cases where the data is less than 4
- * bytes
- */
-} XQspiPs;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/*
-*
-* Check in OptionsTable if Manual Start Option is enabled or disabled.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return
-* - TRUE if option is set
-* - FALSE if option is not set
-*
-* @note C-Style signature:
-* u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr);
-*
-*****************************************************************************/
-#define XQspiPs_IsManualStart(InstancePtr) \
- ((XQspiPs_GetOptions(InstancePtr) & \
- XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
-
-/****************************************************************************/
-/*
-*
-* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
-*
-* @param InstancePtr is a pointer to the XSpiPs instance.
-*
-* @return
-* - TRUE if option is set
-* - FALSE if option is not set
-*
-* @note C-Style signature:
-* u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr);
-*
-*****************************************************************************/
-#define XQspiPs_IsManualChipSelect(InstancePtr) \
- ((XQspiPs_GetOptions(InstancePtr) & \
- XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the slave idle count register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written, valid values are
-* 0-255.
-*
-* @return None
-*
-* @note C-Style signature:
-* void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr,
-* u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_SICR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_*
-* constants defined in xqspips_hw.h to interpret the bit-mask returned.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return An 8-bit value representing Slave Idle Count.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetSlaveIdle(InstancePtr) \
- XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_SICR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the transmit FIFO watermark register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written, valid values are 1-63.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr,
-* u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_TXWR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the transmit FIFO watermark register.
-* Valid values are in the range 1-63.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return A 6-bit value representing Tx Watermark level.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetTXWatermark(InstancePtr) \
- XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the receive FIFO watermark register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written, valid values are 1-63.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr,
-* u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_RXWR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the receive FIFO watermark register.
-* Valid values are in the range 1-63.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return A 6-bit value representing Rx Watermark level.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetRXWatermark(InstancePtr) \
- XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Enable the device and uninhibit master transactions.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_Enable(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_Enable(InstancePtr) \
- XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
- XQSPIPS_ER_ENABLE_MASK)
-
-/****************************************************************************/
-/**
-*
-* Disable the device.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_Disable(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_Disable(InstancePtr) \
- XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the Linear QSPI Configuration register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written to the Linear QSPI
-* configuration register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr,
-* u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the Linear QSPI Configuration register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return A 32-bit value representing the contents of the LQSPI Config
-* register.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetLqspiConfigReg(InstancePtr) \
- XQspiPs_In32((InstancePtr->Config.BaseAddress) + \
- XQSPIPS_LQSPI_CR_OFFSET)
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Initialization function, implemented in xqspips_sinit.c
- */
-XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
-
-/*
- * Functions implemented in xqspips.c
- */
-int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *Config,
- u32 EffectiveAddr);
-void XQspiPs_Reset(XQspiPs *InstancePtr);
-void XQspiPs_Abort(XQspiPs *InstancePtr);
-
-s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
- u32 ByteCount);
-s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
- u8 *RecvBufPtr, u32 ByteCount);
-int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
- u32 Address, unsigned ByteCount);
-
-int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
-
-void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
- XQspiPs_StatusHandler FuncPtr);
-void XQspiPs_InterruptHandler(void *InstancePtr);
-
-/*
- * Functions for selftest, in xqspips_selftest.c
- */
-int XQspiPs_SelfTest(XQspiPs *InstancePtr);
-
-/*
- * Functions for options, in xqspips_options.c
- */
-s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options);
-u32 XQspiPs_GetOptions(XQspiPs *InstancePtr);
-
-s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
-u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
-
-int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
- u8 DelayAfter, u8 DelayInit);
-void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
- u8 *DelayAfter, u8 *DelayInit);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/0/d04f84545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/0/d04f84545243001d18b399c1eb9b3628
deleted file mode 100644
index 1feacd9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/0/d04f84545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,87 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xdevcfg_hw.c
-* @addtogroup devcfg_v3_7
-* @{
-*
-* This file contains the implementation of the interface reset functionality
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 2.04a kpc 10/07/13 First release
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xdevcfg_hw.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-* This function perform the reset sequence to the given devcfg interface by
-* configuring the appropriate control bits in the devcfg specifc registers
-* the devcfg reset squence involves the following steps
-* Disable all the interuupts
-* Clear the status
-* Update relevant config registers with reset values
-* Disbale the looopback mode and pcap rate enable
-*
-* @param BaseAddress of the interface
-*
-* @return N/A
-*
-* @note
-* This function will not modify the slcr registers that are relavant for
-* devcfg controller
-******************************************************************************/
-void XDcfg_ResetHw(u32 BaseAddr)
-{
- u32 Regval = 0;
-
- /* Mask the interrupts */
- XDcfg_WriteReg(BaseAddr, XDCFG_INT_MASK_OFFSET,
- XDCFG_IXR_ALL_MASK);
- /* Clear the interuupt status */
- Regval = XDcfg_ReadReg(BaseAddr, XDCFG_INT_STS_OFFSET);
- XDcfg_WriteReg(BaseAddr, XDCFG_INT_STS_OFFSET, Regval);
- /* Clear the source address register */
- XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_ADDR_OFFSET, 0x0);
- /* Clear the destination address register */
- XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_ADDR_OFFSET, 0x0);
- /* Clear the source length register */
- XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_LEN_OFFSET, 0x0);
- /* Clear the destination length register */
- XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_LEN_OFFSET, 0x0);
- /* Clear the loopback enable bit */
- Regval = XDcfg_ReadReg(BaseAddr, XDCFG_MCTRL_OFFSET);
- Regval = Regval & ~XDCFG_MCTRL_PCAP_LPBK_MASK;
- XDcfg_WriteReg(BaseAddr, XDCFG_MCTRL_OFFSET, Regval);
- /*Reset the configuration register to reset value */
- XDcfg_WriteReg(BaseAddr, XDCFG_CFG_OFFSET,
- XDCFG_CONFIG_RESET_VALUE);
- /*Disable the PCAP rate enable bit */
- Regval = XDcfg_ReadReg(BaseAddr, XDCFG_CTRL_OFFSET);
- Regval = Regval & ~XDCFG_CTRL_PCAP_RATE_EN_MASK;
- XDcfg_WriteReg(BaseAddr, XDCFG_CTRL_OFFSET, Regval);
-
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1/00513e555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1/00513e555243001d18b399c1eb9b3628
deleted file mode 100644
index 97070df..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1/00513e555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,67 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2017 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_errata.h
-*
-* @addtogroup a53_errata Cortex A53 64 bit Processor Errata Support
-* @{
-* Various ARM errata are handled in the standalone BSP. The implementation for
-* errata handling follows ARM guidelines and is based on the open source Linux
-* support for these errata.
-*
-* @note
-* The errata handling is enabled by default. To disable handling of all the
-* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
-* disable errata on a per-erratum basis, un-define relevant macros in
-* xil_errata.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 6.4 mus 08/11/17 First release
-*
-*
-******************************************************************************/
-#ifndef XIL_ERRATA_H
-#define XIL_ERRATA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @name errata_definitions
- *
- * The errata conditions handled in the standalone BSP are listed below
- * @{
- */
-
-#define ENABLE_ARM_ERRATA 1
-
-#ifdef ENABLE_ARM_ERRATA
-
-/**
- * Errata No: 855873
- * Description: An eviction might overtake a cache clean operation
- */
-#define CONFIG_ARM_ERRATA_855873 1
-
-
-/*@}*/
-#endif /* ENABLE_ARM_ERRATA */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_ERRATA_H */
-/**
-* @} End of "addtogroup a53_errata".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1/13a13a585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1/13a13a585243001d18b399c1eb9b3628
deleted file mode 100644
index 4c9faef..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1/13a13a585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,16 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include
-
-/*
- * abort -- go out via exit...
- */
-__attribute__((weak)) void abort(void)
-{
- _exit(1);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1/20fa20545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1/20fa20545243001d18b399c1eb9b3628
deleted file mode 100644
index 6f40407..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1/20fa20545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,52 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xcoresightpsdcc.h
-* @addtogroup coresightps_dcc_v1_8
-* @{
-* @details
-*
-* CoreSight driver component.
-*
-* The coresight is a part of debug communication channel (DCC) group. Jtag UART
-* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
-* ARM target in XSDB console before running the jtag terminal command. Using the
-* coresight driver component, the output stream can be directed to a log file.
-*
-* @note None.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------
-* 1.00 kvn 02/14/15 First release
-* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
-* kvn 08/18/15 Modified Makefile according to compiler changes.
-* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
-* for MB BSPs. Instead it throws up a warning. This
-* fixes the CR#953056.
-* 1.5 sne 01/19/19 Fixed MISRA-C Violations CR#1025101.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#ifndef XCORESIGHTPSDCC_H /* prevent circular inclusions */
-#define XCORESIGHTPSDCC_H /* by using protection macros */
-#ifndef __MICROBLAZE__
-#include
-
-void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
-
-u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
-#endif
-#endif
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1/30eed8565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1/30eed8565243001d18b399c1eb9b3628
deleted file mode 100644
index 50df3c5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1/30eed8565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,128 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_clocking.c
-*
-* The xil_clocking.c file contains clocking related functions and macros.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 7.2 sd 02/06/20 First release of clocking
-* 7.2 sd 03/20/20 Added checking for isolation case
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 08/25/09 First release
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xil_testio.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ****************************/
-/************************** Function Prototypes *****************************/
-
-
-
-/**
- *
- * Endian swap a 16-bit word.
- * @param Data is the 16-bit word to be swapped.
- * @return The endian swapped value.
- *
- */
-static u16 Swap16(u16 Data)
-{
- return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U);
-}
-
-/**
- *
- * Endian swap a 32-bit word.
- * @param Data is the 32-bit word to be swapped.
- * @return The endian swapped value.
- *
- */
-static u32 Swap32(u32 Data)
-{
- u16 Lo16;
- u16 Hi16;
-
- u16 Swap16Lo;
- u16 Swap16Hi;
-
- Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU);
- Lo16 = (u16)(Data & 0x0000FFFFU);
-
- Swap16Lo = Swap16(Lo16);
- Swap16Hi = Swap16(Hi16);
-
- return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi);
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 8-bit wide register IO test where the
-* register is accessed using Xil_Out8 and Xil_In8, and comparing
-* the written values by reading them back.
-*
-* @param Addr: a pointer to the region of memory to be tested.
-* @param Length: Length of the block.
-* @param Value: constant used for writing the memory.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-
-s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value)
-{
- u8 ValueIn;
- s32 Index;
- s32 Status = 0;
-
- for (Index = 0; Index < Length; Index++) {
- Xil_Out8((INTPTR)Addr, Value);
-
- ValueIn = Xil_In8((INTPTR)Addr);
-
- if ((Value != ValueIn) && (Status == 0)) {
- Status = -1;
- break;
- }
- }
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 16-bit wide register IO test. Each location
-* is tested by sequentially writing a 16-bit wide register, reading
-* the register, and comparing value. This function tests three kinds
-* of register IO functions, normal register IO, little-endian register
-* IO, and big-endian register IO. When testing little/big-endian IO,
-* the function performs the following sequence, Xil_Out16LE/Xil_Out16BE,
-* Xil_In16, Compare In-Out values, Xil_Out16, Xil_In16LE/Xil_In16BE,
-* Compare In-Out values. Whether to swap the read-in value before
-* comparing is controlled by the 5th argument.
-*
-* @param Addr: a pointer to the region of memory to be tested.
-* @param Length: Length of the block.
-* @param Value: constant used for writing the memory.
-* @param Kind: Type of test. Acceptable values are:
-* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
-* @param Swap: indicates whether to byte swap the read-in value.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-
-s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap)
-{
- u16 *TempAddr16;
- u16 ValueIn = 0U;
- s32 Index;
- TempAddr16 = Addr;
- Xil_AssertNonvoid(TempAddr16 != NULL);
-
- for (Index = 0; Index < Length; Index++) {
- switch (Kind) {
- case XIL_TESTIO_LE:
- Xil_Out16LE((INTPTR)TempAddr16, Value);
- break;
- case XIL_TESTIO_BE:
- Xil_Out16BE((INTPTR)TempAddr16, Value);
- break;
- default:
- Xil_Out16((INTPTR)TempAddr16, Value);
- break;
- }
-
- ValueIn = Xil_In16((INTPTR)TempAddr16);
-
- if ((Kind != 0) && (Swap != 0)) {
- ValueIn = Swap16(ValueIn);
- }
-
- if (Value != ValueIn) {
- return -1;
- }
-
- /* second round */
- Xil_Out16((INTPTR)TempAddr16, Value);
-
- switch (Kind) {
- case XIL_TESTIO_LE:
- ValueIn = Xil_In16LE((INTPTR)TempAddr16);
- break;
- case XIL_TESTIO_BE:
- ValueIn = Xil_In16BE((INTPTR)TempAddr16);
- break;
- default:
- ValueIn = Xil_In16((INTPTR)TempAddr16);
- break;
- }
-
-
- if ((Kind != 0) && (Swap != 0)) {
- ValueIn = Swap16(ValueIn);
- }
-
- if (Value != ValueIn) {
- return -1;
- }
- TempAddr16 += sizeof(u16);
- }
- return 0;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 32-bit wide register IO test. Each location
-* is tested by sequentially writing a 32-bit wide register, reading
-* the register, and comparing value. This function tests three kinds
-* of register IO functions, normal register IO, little-endian register IO,
-* and big-endian register IO. When testing little/big-endian IO,
-* the function perform the following sequence, Xil_Out32LE/
-* Xil_Out32BE, Xil_In32, Compare, Xil_Out32, Xil_In32LE/Xil_In32BE, Compare.
-* Whether to swap the read-in value *before comparing is controlled
-* by the 5th argument.
-* @param Addr: a pointer to the region of memory to be tested.
-* @param Length: Length of the block.
-* @param Value: constant used for writing the memory.
-* @param Kind: type of test. Acceptable values are:
-* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
-* @param Swap: indicates whether to byte swap the read-in value.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
-{
- u32 *TempAddr;
- u32 ValueIn = 0U;
- s32 Index;
- TempAddr = Addr;
- Xil_AssertNonvoid(TempAddr != NULL);
-
- for (Index = 0; Index < Length; Index++) {
- switch (Kind) {
- case XIL_TESTIO_LE:
- Xil_Out32LE((INTPTR)TempAddr, Value);
- break;
- case XIL_TESTIO_BE:
- Xil_Out32BE((INTPTR)TempAddr, Value);
- break;
- default:
- Xil_Out32((INTPTR)TempAddr, Value);
- break;
- }
-
- ValueIn = Xil_In32((INTPTR)TempAddr);
-
- if ((Kind != 0) && (Swap != 0)) {
- ValueIn = Swap32(ValueIn);
- }
-
- if (Value != ValueIn) {
- return -1;
- }
-
- /* second round */
- Xil_Out32((INTPTR)TempAddr, Value);
-
-
- switch (Kind) {
- case XIL_TESTIO_LE:
- ValueIn = Xil_In32LE((INTPTR)TempAddr);
- break;
- case XIL_TESTIO_BE:
- ValueIn = Xil_In32BE((INTPTR)TempAddr);
- break;
- default:
- ValueIn = Xil_In32((INTPTR)TempAddr);
- break;
- }
-
- if ((Kind != 0) && (Swap != 0)) {
- ValueIn = Swap32(ValueIn);
- }
-
- if (Value != ValueIn) {
- return -1;
- }
- TempAddr += sizeof(u32);
- }
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1/c27dde545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1/c27dde545243001d18b399c1eb9b3628
deleted file mode 100644
index ddfa24c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1/c27dde545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,113 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xscutimer_selftest.c
-* @addtogroup scutimer_v2_3
-* @{
-*
-* Contains diagnostic self-test functions for the XScuTimer driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm 03/10/10 First release
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xscutimer.h"
-
-/************************** Constant Definitions *****************************/
-
-#define XSCUTIMER_SELFTEST_VALUE 0xA55AF00FU
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/****************************************************************************/
-/**
-*
-* Run a self-test on the timer. This test clears the timer enable bit in
-* the control register, writes to the timer load register and verifies the
-* value read back matches the value written and restores the control register
-* and the timer load register.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return
-* - XST_SUCCESS if self-test was successful.
-* - XST_FAILURE if self test was not successful.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XScuTimer_SelfTest(XScuTimer *InstancePtr)
-{
- u32 Register;
- u32 CtrlOrig;
- u32 LoadOrig;
- s32 Status;
-
- /*
- * Assert to ensure the inputs are valid and the instance has been
- * initialized.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Save the contents of the Control Register and stop the timer.
- */
- CtrlOrig = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
- XSCUTIMER_CONTROL_OFFSET);
- Register = CtrlOrig & (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK);
- XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
- XSCUTIMER_CONTROL_OFFSET, Register);
-
- /*
- * Save the contents of the Load Register.
- * Load a new test value in the Load Register, read it back and
- * compare it with the written value.
- */
- LoadOrig = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
- XSCUTIMER_LOAD_OFFSET);
- XScuTimer_LoadTimer(InstancePtr, XSCUTIMER_SELFTEST_VALUE);
- Register = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
- XSCUTIMER_LOAD_OFFSET);
-
- /*
- * Restore the contents of the Load Register and Control Register.
- */
- XScuTimer_LoadTimer(InstancePtr, LoadOrig);
- XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
- XSCUTIMER_CONTROL_OFFSET, CtrlOrig);
-
- /*
- * Return a Failure if the contents of the Load Register do not
- * match with the value written to it.
- */
- if (Register != XSCUTIMER_SELFTEST_VALUE) {
- Status = (s32)XST_FAILURE;
- }
- else {
- Status = (s32)XST_SUCCESS;
- }
-
- return Status;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/10/306a6b575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/10/306a6b575243001d18b399c1eb9b3628
deleted file mode 100644
index 1b7d881..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/10/306a6b575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,369 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xdevcfg_hw.h
-* @addtogroup devcfg_v3_7
-* @{
-*
-* This file contains the hardware interface to the Device Config Interface.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.01a nm 08/01/12 Added defines for the PS Version bits,
-* removed the FIFO Flush bits from the
-* Miscellaneous Control Reg
-* 2.03a nm 04/19/13 Fixed CR# 703728.
-* Updated the register definitions as per the latest TRM
-* version UG585 (v1.4) November 16, 2012.
-* 2.04a kpc 10/07/13 Added function prototype.
-* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
-*
-*
-******************************************************************************/
-#ifndef XDCFG_HW_H /* prevent circular inclusions */
-#define XDCFG_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- * Offsets of registers from the start of the device
- * @{
- */
-
-#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */
-#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */
-#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */
-#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */
-#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */
-#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */
-#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */
-#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */
-#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */
-#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */
-#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */
-#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */
-#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */
-#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */
-#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */
-
-/* @} */
-
-/** @name Control Register Bit definitions
- * @{
- */
-
-#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into
- * Secure Reset
- */
-#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to
- * Reset FPGA
- */
-#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */
-#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */
-#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */
-#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data
- * to FPGA every 4 PCAP
- * cycles
- */
-#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */
-#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */
-#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */
-#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */
-#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */
-#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */
-#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure
- * Status mask
- */
-#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive
- * Debug Enable
- */
-#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive
- * Debug Enable
- */
-#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug
- * Enable
- */
-#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug
- * Enable
- */
-#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */
-
-/* @} */
-
-/** @name Lock register bit definitions
- * @{
- */
-
-#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */
-#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */
-#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */
-#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and
- * USER_MODE
- */
-#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks
- * security config
- * including: DAP_En,
- * DBGEN,,
- * NIDEN, SPNIEN
- */
-/*@}*/
-
-
-
-/** @name Config Register Bit definitions
- * @{
- */
-#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO
- * Threshold Mask
- */
-#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold
- * Mask
- */
-#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active
- * clock edge
- */
-#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active
- * clock edge
- */
-#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address
- * increment mask
- */
-#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination
- * address increment
- * mask
- */
-/* @} */
-
-
-/** @name Interrupt Status/Mask Register Bit definitions
- * @{
- */
-#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during
- * HIZ
- */
-#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration
- * done
- */
-#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */
-#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during
- * configuration
- */
-#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration
- * reset
- */
-#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address
- * or Data or response
- * timeout
- */
-#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response
- * error
- */
-#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or
- * response timeout
- */
-#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response
- * error
- */
-#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */
-#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than
- * threshold */
-#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than
- * threshold */
-#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */
-#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue
- * overflow
- */
-#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */
-#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP
- * transfers Done
- */
-#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer
- * length error
- */
-#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */
-#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */
-#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */
-#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */
-#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */
-#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge
- * of Init Signal
- */
-#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge
- * of Init Signal
- */
-#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \
- XDCFG_IXR_AXI_WERR_MASK | \
- XDCFG_IXR_AXI_RTO_MASK | \
- XDCFG_IXR_AXI_RERR_MASK | \
- XDCFG_IXR_RX_FIFO_OV_MASK | \
- XDCFG_IXR_DMA_CMD_ERR_MASK |\
- XDCFG_IXR_DMA_Q_OV_MASK | \
- XDCFG_IXR_P2D_LEN_ERR_MASK |\
- XDCFG_IXR_PCFG_HMAC_ERR_MASK)
-
-
-#define XDCFG_IXR_ALL_MASK 0x00F7F8EF
-
-
-
-/* @} */
-
-
-/** @name Status Register Bit definitions
- * @{
- */
-#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command
- * Queue full
- */
-#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command
- * Queue empty
- */
-#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of
- * completed DMA
- * transfers
- */
-#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */
-#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */
-
-#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO
- * during HIZ
- */
-#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config
- * done
- */
-#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */
-#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during
- * config
- */
-#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset
- * POR Status
- */
-#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB
- * access
- */
-#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config
- * reset status
- */
-#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init
- * Status
- */
-#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008
- /**< BBRAM key
- * disable
- */
-#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security
- * Enable Status
- */
-#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG
- * Disable
- * status
- */
-/* @} */
-
-
-/** @name DMA Source/Destination Transfer Length Register Bit definitions
- * @{
- */
-#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */
-/*@}*/
-
-
-
-
-/** @name Miscellaneous Control Register Bit definitions
- * @{
- */
-#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */
-#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */
-#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */
-/* @} */
-
-/** @name FIFO Threshold Bit definitions
- * @{
- */
-
-#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */
-#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */
-#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */
-#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */
-/* @}*/
-
-
-/* Miscellaneous constant values */
-#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */
-#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/
-#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base
- * address
- */
-#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note C-style signature:
-* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XDcfg_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + (RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write to the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + (RegOffset), (Data))
-
-/************************** Function Prototypes ******************************/
-/*
- * Perform reset operation to the devcfg interface
- */
-void XDcfg_ResetHw(u32 BaseAddr);
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/10/41b148555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/10/41b148555243001d18b399c1eb9b3628
deleted file mode 100644
index fd281c5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/10/41b148555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,131 +0,0 @@
-/******************************************************************************
- * xen.h
- *
- * Guest OS interface to Xen.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Copyright (c) 2004, K A Fraser
- */
-/*
-Copyright DornerWorks 2016
-
-Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-following conditions are met:
-1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
-following disclaimer.
-
-THIS SOFTWARE IS PROVIDED BY DORNERWORKS FOR USE ON THE CONTRACTED PROJECT, AND ANY EXPRESS OR IMPLIED WARRANTY
-IS LIMITED TO THIS USE. FOR ALL OTHER USES THIS SOFTWARE IS PROVIDED ''AS IS'' AND ANY EXPRESS OR IMPLIED
-WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL DORNERWORKS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#ifndef __XEN_H_
-#define __XEN_H_
-
-/*
- * HYPERCALLS
- */
-
-/* `incontents 100 hcalls List of hypercalls
- * ` enum hypercall_num { // __HYPERVISOR_* => HYPERVISOR_*()
- */
-
-#define __HYPERVISOR_set_trap_table 0
-#define __HYPERVISOR_mmu_update 1
-#define __HYPERVISOR_set_gdt 2
-#define __HYPERVISOR_stack_switch 3
-#define __HYPERVISOR_set_callbacks 4
-#define __HYPERVISOR_fpu_taskswitch 5
-#define __HYPERVISOR_sched_op_compat 6 /* compat since 0x00030101 */
-#define __HYPERVISOR_platform_op 7
-#define __HYPERVISOR_set_debugreg 8
-#define __HYPERVISOR_get_debugreg 9
-#define __HYPERVISOR_update_descriptor 10
-#define __HYPERVISOR_memory_op 12
-#define __HYPERVISOR_multicall 13
-#define __HYPERVISOR_update_va_mapping 14
-#define __HYPERVISOR_set_timer_op 15
-#define __HYPERVISOR_event_channel_op_compat 16 /* compat since 0x00030202 */
-#define __HYPERVISOR_xen_version 17
-#define __HYPERVISOR_console_io 18
-#define __HYPERVISOR_physdev_op_compat 19 /* compat since 0x00030202 */
-#define __HYPERVISOR_grant_table_op 20
-#define __HYPERVISOR_vm_assist 21
-#define __HYPERVISOR_update_va_mapping_otherdomain 22
-#define __HYPERVISOR_iret 23 /* x86 only */
-#define __HYPERVISOR_vcpu_op 24
-#define __HYPERVISOR_set_segment_base 25 /* x86/64 only */
-#define __HYPERVISOR_mmuext_op 26
-#define __HYPERVISOR_xsm_op 27
-#define __HYPERVISOR_nmi_op 28
-#define __HYPERVISOR_sched_op 29
-#define __HYPERVISOR_callback_op 30
-#define __HYPERVISOR_xenoprof_op 31
-#define __HYPERVISOR_event_channel_op 32
-#define __HYPERVISOR_physdev_op 33
-#define __HYPERVISOR_hvm_op 34
-#define __HYPERVISOR_sysctl 35
-#define __HYPERVISOR_domctl 36
-#define __HYPERVISOR_kexec_op 37
-#define __HYPERVISOR_tmem_op 38
-#define __HYPERVISOR_xc_reserved_op 39 /* reserved for XenClient */
-
-/* Architecture-specific hypercall definitions. */
-#define __HYPERVISOR_arch_0 48
-#define __HYPERVISOR_arch_1 49
-#define __HYPERVISOR_arch_2 50
-#define __HYPERVISOR_arch_3 51
-#define __HYPERVISOR_arch_4 52
-#define __HYPERVISOR_arch_5 53
-#define __HYPERVISOR_arch_6 54
-#define __HYPERVISOR_arch_7 55
-
-/* ` } */
-
-/*
- * Commands to HYPERVISOR_console_io().
- */
-#define CONSOLEIO_write 0
-#define CONSOLEIO_read 1
-
-/*
- * Commands to HYPERVISOR_hvm_op
- */
-#define HVMOP_set_param 0
-#define HVMOP_get_param 1
-
-/* DOMID_SELF is used in certain contexts to refer to oneself. */
-#define DOMID_SELF (0x7FF0U)
-
-
-#define XENMEM_add_to_physmap 7
-
-
-/* Console debug shared memory ring and event channel */
-#define HVM_PARAM_CONSOLE_PFN 17
-#define HVM_PARAM_CONSOLE_EVTCHN 18
-
-
-#endif /* __XEN_PUBLIC_XEN_H__ */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/10/70fbf9515243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/10/70fbf9515243001d18b399c1eb9b3628
deleted file mode 100644
index 2c88e06..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/10/70fbf9515243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,26 +0,0 @@
-
-
- phased_array
- Created by Vitis v2021.2
-
-
-
-
- org.eclipse.cdt.managedbuilder.core.genmakebuilder
-
-
-
-
- org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
- full,incremental,
-
-
-
-
-
- com.xilinx.sdx.sdk.core.SdkProjectNature
- org.eclipse.cdt.core.cnature
- org.eclipse.cdt.managedbuilder.core.managedBuildNature
- org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/10/a1c09f575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/10/a1c09f575243001d18b399c1eb9b3628
deleted file mode 100644
index 4b6d75a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/10/a1c09f575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,261 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xscutimer_hw.h
-* @addtogroup scutimer_v2_3
-* @{
-*
-* This file contains the hardware interface to the Timer.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm 03/10/10 First release
-* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
-* and interrupt registers
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-#ifndef XSCUTIMER_HW_H /* prevent circular inclusions */
-#define XSCUTIMER_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- * Offsets of registers from the start of the device
- * @{
- */
-
-#define XSCUTIMER_LOAD_OFFSET 0x00U /**< Timer Load Register */
-#define XSCUTIMER_COUNTER_OFFSET 0x04U /**< Timer Counter Register */
-#define XSCUTIMER_CONTROL_OFFSET 0x08U /**< Timer Control Register */
-#define XSCUTIMER_ISR_OFFSET 0x0CU /**< Timer Interrupt
- Status Register */
-/* @} */
-
-/** @name Timer Control register
- * This register bits control the prescaler, Intr enable,
- * auto-reload and timer enable.
- * @{
- */
-
-#define XSCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
-#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8U
-#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004U /**< Intr enable */
-#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload */
-#define XSCUTIMER_CONTROL_ENABLE_MASK 0x00000001U /**< Timer enable */
-/* @} */
-
-/** @name Interrupt Status register
- * This register indicates the Timer counter register has reached zero.
- * @{
- */
-
-#define XSCUTIMER_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Write to the timer load register. This will also update the
-* timer counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetLoadReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer load register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer load register.
-*
-* @note C-style signature:
-* u32 XScuTimer_GetLoadReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetLoadReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the timer counter register.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the counter register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetCounterReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer counter register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer counter register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetCounterReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetCounterReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the timer load register. This will also update the
-* timer counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetControlReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer load register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer load register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetControlReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetControlReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the timer counter register.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the counter register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetIntrReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer counter register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer counter register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetIntrReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetIntrReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Read from the given Timer register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note C-style signature:
-* u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuTimer_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + (RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write to the given Timer register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + (RegOffset), (Data))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/10/a2ac43595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/10/a2ac43595243001d18b399c1eb9b3628
deleted file mode 100644
index e22e04d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/10/a2ac43595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,181 +0,0 @@
-/******************************************************************************/
-/**
-* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-* @file xil_util.h
-* @addtogroup common_utilities Common Utility APIs
-* @{
-* @details
-*
-* This file contains xil utility functions declaration
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.4 mmd 04/21/19 First release.
-* 6.5 kal 02/29/20 Added Xil_ConvertStringToHexBE API
-* 7.3 kal 06/30/20 Converted Xil_Ceil macro to API
-* rpo 08/19/20 Added function for read, modify and write
-* bsv 08/21/20 Added XSECURE_TEMPORAL_CHECK macro to add
-* redundancy in security critical functions, to avoid
-* glitches from altering the return values of security
-* critical functions. The macro requires a label to be
-* passed to "go to" in case of error.
-* kpt 09/03/20 Added XSECURE_TEMPORAL_IMPL macro for redundancy
-* kal 09/22/20 Changed the param type from const char to const char*
-* to avoid copying key onto stack
-* td 10/16/20 Added Xil_Strcpy, Xil_Strcat, Xil_SecureMemCpy and
-* Xil_MemCmp functions
-* am 10/13/20 Resolved Coverity warning
-* td 11/19/20 Updated XSECURE_TEMPORAL_CHECK and
-* XSECURE_TEMPORAL_IMPL to fix MISRA C Rule 15.3
-* 7.4 am 11/26/20 Added Xil_StrCpyRange function
-* 7.6 kpt 07/15/21 Added Xil_SecureZeroize function
-*
-*
-*
-*****************************************************************************/
-
-#ifndef XIL_UTIL_H_
-#define XIL_UTIL_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xstatus.h"
-
-/*************************** Constant Definitions *****************************/
-#define XIL_SIZE_OF_NIBBLE_IN_BITS 4U
-#define XIL_SIZE_OF_BYTE_IN_BITS 8U
-
-/* Maximum string length handled by Xil_ValidateHexStr function */
-#define XIL_MAX_HEX_STR_LEN 512U
-
-
-/****************** Macros (Inline Functions) Definitions *********************/
-#ifdef __GNUC__
-/******************************************************************************/
-/**
- *
- * Updates the return value of the called function into Var and VarTmp variables
- * for redundancy. This is to avoid glitches from altering the return values of
- * security critical functions.
- *
- * @param Var is the variable which holds the return value of function
- * executed
- * @param VarTmp is the variable which holds the value stored in Var
- * @param Function is the function to be executed
- * @param Other params are arguments to the called function
- *
- * @return None
- *
- ******************************************************************************/
-#define XSECURE_TEMPORAL_IMPL(Var, VarTmp, Function, ...) \
- { \
- Var = XST_FAILURE; \
- VarTmp = XST_FAILURE; \
- Var = Function(__VA_ARGS__); \
- VarTmp = Var; \
- }
-
-/******************************************************************************/
-/**
- *
- * Adds redundancy while checking the status of the called function.
- * This is to avoid glitches from altering the return values of security
- * critical functions. The macro requires a label to be passed to "go to"
- * in case of error.
- *
- * @param Label is the label defined in function and the control
- * will jump to the label in case of XST_FAILURE
- * @param Status is the variable which holds the return value of
- * function executed
- * @param Function is the function to be executed
- * @param Other params are arguments to the called function
- *
- * @return None
- *
- ******************************************************************************/
-#define XSECURE_TEMPORAL_CHECK(Label, Status, Function, ...) \
- { \
- volatile int StatusTmp = XST_FAILURE; \
- XSECURE_TEMPORAL_IMPL(Status, StatusTmp, Function, __VA_ARGS__); \
- if ((Status != XST_SUCCESS) || \
- (StatusTmp != XST_SUCCESS)) { \
- Status |= StatusTmp;\
- goto Label; \
- } \
- }
-#endif
-
-/*************************** Function Prototypes ******************************/
-/* Ceils the provided float value */
-int Xil_Ceil(float Value);
-
-/* Converts input character to nibble */
-u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num);
-
-/* Convert input hex string to array of 32-bits integers */
-u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len);
-
-/* Waits for specified event */
-u32 Xil_WaitForEvent(u32 RegAddr, u32 EventMask, u32 Event, u32 Timeout);
-
-/* Waits for specified events */
-u32 Xil_WaitForEvents(u32 EventsRegAddr, u32 EventsMask, u32 WaitEvents,
- u32 Timeout, u32* Events);
-
-/* Validate input hex character */
-u32 Xil_IsValidHexChar(const char *Ch);
-
-/* Validate the input string contains only hexadecimal characters */
-u32 Xil_ValidateHexStr(const char *HexStr);
-
-/* Convert string to hex numbers in little enidian format */
-u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len);
-
-/* Returns length of the input string */
-u32 Xil_Strnlen(const char *Str, u32 MaxLen);
-
-/* Convert string to hex numbers in big endian format */
-u32 Xil_ConvertStringToHexBE(const char * Str, u8 * Buf, u32 Len);
-
-/*Read, Modify and Write to an address*/
-void Xil_UtilRMW32(u32 Addr, u32 Mask, u32 Value);
-
-/* Copies source string to destination string */
-int Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size);
-
-/* Copies specified range from source string to destination string */
-int Xil_StrCpyRange(const u8 *Src, u8 *Dst, u32 From, u32 To, u32 MaxSrcLen,
- u32 MaxDstLen);
-
-/* Appends string2 to string1 */
-int Xil_Strcat(char* Str1Ptr, const char* Str2Ptr, const u32 Size);
-
-/* Copies Len bytes from source memory to destination memory */
-int Xil_SecureMemCpy(void * DestPtr, u32 DestPtrLen, const void * SrcPtr, u32 Len);
-
-/* Compares Len bytes from memory1 and memory2 */
-int Xil_MemCmp(const void * Buf1Ptr, const void * Buf2Ptr, u32 Len);
-
-/* Zeroizes the memory of given length */
-int Xil_SecureZeroize(u8 *DataPtr, const u32 Length);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_UTIL_H_ */
-/**
-* @} End of "addtogroup common_utilities".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/11/30e9d0545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/11/30e9d0545243001d18b399c1eb9b3628
deleted file mode 100644
index 229012b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/11/30e9d0545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,33 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 2021.2
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2022 Xilinx, Inc. All Rights Reserved.
-* SPDX-License-Identifier: MIT
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xscugic.h"
-
-/*
-* The configuration table for devices
-*/
-
-XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES] =
-{
- {
- XPAR_PS7_SCUGIC_0_DEVICE_ID,
- XPAR_PS7_SCUGIC_0_BASEADDR,
- XPAR_PS7_SCUGIC_0_DIST_BASEADDR,
- {{0}} /**< Initialize the HandlerTable to 0 */
- }
-};
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/11/50c38a555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/11/50c38a555243001d18b399c1eb9b3628
deleted file mode 100644
index 146017b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/11/50c38a555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,17 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: MIT
-*
-******************************************************************************/
-#include "xil_types.h"
-
-/* Stub for iserror() function */
-__attribute__((weak)) s32 _sys_iserror(s32 status)
-{
- if (status < 0) {
- return 1;
- }
-
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/11/a0d0c6575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/11/a0d0c6575243001d18b399c1eb9b3628
deleted file mode 100644
index 9e7a741..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/11/a0d0c6575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,284 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xdevcfg_intr.c
-* @addtogroup devcfg_v3_7
-* @{
-*
-* Contains the implementation of interrupt related functions of the XDcfg
-* driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
-* set the mask instead of oring it with the
-* value read from the interrupt status register
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xdevcfg.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/****************************************************************************/
-/**
-*
-* This function enables the specified interrupts in the device.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Mask is the bit-mask of the interrupts to be enabled.
-* Bit positions of 1 will be enabled. Bit positions of 0 will
-* keep the previous setting. This mask is formed by OR'ing
-* XDCFG_INT_* bits defined in xdevcfg_hw.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Enable the specified interrupts in the Interrupt Mask Register.
- */
- RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_MASK_OFFSET);
- RegValue &= ~(Mask & XDCFG_IXR_ALL_MASK);
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_MASK_OFFSET,
- RegValue);
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function disables the specified interrupts in the device.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Mask is the bit-mask of the interrupts to be disabled.
-* Bit positions of 1 will be disabled. Bit positions of 0 will
-* keep the previous setting. This mask is formed by OR'ing
-* XDCFG_INT_* bits defined in xdevcfg_hw.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Disable the specified interrupts in the Interrupt Mask Register.
- */
- RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_MASK_OFFSET);
- RegValue |= (Mask & XDCFG_IXR_ALL_MASK);
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_MASK_OFFSET,
- RegValue);
-}
-/****************************************************************************/
-/**
-*
-* This function returns the enabled interrupts read from the Interrupt Mask
-* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h
-* to interpret the returned value.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return A 32-bit value representing the contents of the IMR.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Return the value read from the Interrupt Mask Register.
- */
- return (~ XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_MASK_OFFSET));
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the interrupt status read from Interrupt Status
-* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h
-* to interpret the returned value.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return A 32-bit value representing the contents of the Interrupt
-* Status register.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Return the value read from the Interrupt Status register.
- */
- return XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_STS_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* This function clears the specified interrupts in the Interrupt Status
-* Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Mask is the bit-mask of the interrupts to be cleared.
-* Bit positions of 1 will be cleared. Bit positions of 0 will not
-* change the previous interrupt status. This mask is formed by
-* OR'ing XDCFG_INT_* bits which are defined in xdevcfg_hw.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_STS_OFFSET,
- Mask);
-
-}
-
-/*****************************************************************************/
-/**
-* The interrupt handler for the Device Config Interface.
-*
-* Events are signaled to upper layer for proper handling.
-*
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XDcfg_InterruptHandler(XDcfg *InstancePtr)
-{
- u32 IntrStatusReg;
-
- /*
- * Assert validates the input arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Interrupt status register.
- */
- IntrStatusReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_STS_OFFSET);
-
- /*
- * Write the status back to clear the interrupts so that no
- * subsequent interrupts are missed while processing this interrupt.
- * This also does the DMA acknowledgment automatically.
- */
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_STS_OFFSET, IntrStatusReg);
-
- /*
- * Signal application that there are events to handle.
- */
- InstancePtr->StatusHandler(InstancePtr->CallBackRef,
- IntrStatusReg);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the handler that will be called when an event (interrupt)
-* occurs that needs application's attention.
-*
-* @param InstancePtr is a pointer to the XDcfg instance
-* @param CallBackFunc is the address of the callback function.
-* @param CallBackRef is a user data item that will be passed to the
-* callback function when it is invoked.
-*
-* @return None.
-*
-* @note None.
-*
-*
-*****************************************************************************/
-void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
- void *CallBackRef)
-{
- /*
- * Asserts validate the input arguments
- * CallBackRef not checked, no way to know what is valid
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(CallBackFunc != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- InstancePtr->StatusHandler = (XDcfg_IntrHandler) CallBackFunc;
- InstancePtr->CallBackRef = CallBackRef;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/11/a17482575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/11/a17482575243001d18b399c1eb9b3628
deleted file mode 100644
index 878d575..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/11/a17482575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,261 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_misc_psreset_api.h
-*
-* This file contains the various register definitions and function prototypes for
-* implementing the reset functionality of zynq ps devices
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00b kpc 03/07/13 First release.
-*
-*
-******************************************************************************/
-
-#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */
-#define XIL_MISC_RESET_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/**
- *@cond nocomments
- */
-
-#define XDDRC_CTRL_BASEADDR 0xF8006000U
-#define XSLCR_BASEADDR 0xF8000000U
-/**< OCM configuration register */
-#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U)
-/**< SLCR unlock register */
-#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U)
-/**< SLCR GEM0 rx clock control register */
-#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U)
-/**< SLCR GEM1 rx clock control register */
-#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU)
-/**< SLCR GEM0 clock control register */
-#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U)
-/**< SLCR GEM1 clock control register */
-#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U)
-/**< SLCR SMC clock control register */
-#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U)
-/**< SLCR GEM reset control register */
-#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)
-/**< SLCR USB0 clock control register */
-#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U)
-/**< SLCR USB1 clock control register */
-#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U)
-/**< SLCR USB1 reset control register */
-#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)
-/**< SLCR SMC reset control register */
-#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)
-/**< SLCR Level shifter enable register */
-#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U)
-/**< SLCR ARM pll control register */
-#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U)
-/**< SLCR DDR pll control register */
-#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U)
-/**< SLCR IO pll control register */
-#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U)
-/**< SLCR ARM pll configuration register */
-#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U)
-/**< SLCR DDR pll configuration register */
-#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U)
-/**< SLCR IO pll configuration register */
-#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U)
-/**< SLCR ARM clock control register */
-#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U)
-/**< SLCR DDR clock control register */
-#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U)
-/**< SLCR MIO pin address register */
-#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U)
-/**< SLCR DMAC reset control address register */
-#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU)
-/**< SLCR USB reset control address register */
-/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/
-/**< SLCR GEM reset control address register */
-/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/
-/**< SLCR SDIO reset control address register */
-#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U)
-/**< SLCR SPI reset control address register */
-#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU)
-/**< SLCR CAN reset control address register */
-#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U)
-/**< SLCR I2C reset control address register */
-#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U)
-/**< SLCR UART reset control address register */
-#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U)
-/**< SLCR GPIO reset control address register */
-#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU)
-/**< SLCR LQSPI reset control address register */
-#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U)
-/**< SLCR SMC reset control address register */
-/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/
-/**< SLCR OCM reset control address register */
-#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U)
-
-/**< SMC mem controller clear config register */
-#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU
-/**< SMC idlecount configuration register */
-#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U
-#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U
-/**< SMC ECC configuration register */
-#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U
-/**< SMC ECC command 1 register */
-#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U
-/**< SMC ECC command 2 register */
-#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U
-
-/**< SLCR unlock code */
-#define XSLCR_UNLOCK_CODE 0x0000DF0DU
-
-/**< SMC mem clear configuration mask */
-#define XSMC_MEMC_CLR_CONFIG_MASK 0x000005FU
-/**< SMC ECC memconfig 1 reset value */
-#define XSMC_ECC_MEMCFG1_RESET_VAL 0x0000043U
-/**< SMC ECC memcommand 1 reset value */
-#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U
-/**< SMC ECC memcommand 2 reset value */
-#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U
-
-/**< DDR controller reset bit mask */
-#define XDDRPS_CTRL_RESET_MASK 0x00000001U
-/**< SLCR OCM configuration reset value*/
-#define XSLCR_OCM_CFG_RESETVAL 0x00000008U
-/**< SLCR OCM bank selection mask*/
-#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU
-/**< SLCR level shifter enable mask*/
-#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU
-
-/**< SLCR PLL register reset values */
-#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U
-#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U
-#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U
-#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U
-#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U
-#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U
-#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U
-#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U
-
-/**< SLCR MIO register default values */
-#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U
-#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U
-
-/**< SLCR Reset control registers default values */
-#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U
-#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U
-#define XSLCR_USB_RST_CTRL_VAL 0x00000003U
-#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U
-#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU
-#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU
-#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U
-#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U
-#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U
-#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U
-#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U
-#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U
-
-/**
- *@endcond
- */
-
-/**************************** Type Definitions *******************************/
-
-/* the following data type is used to hold a null terminated version string
- * consisting of the following format, "X.YYX"
- */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-/*
- * Performs reset operation to the ddr interface
- */
-void XDdr_ResetHw(void);
-/*
- * Map the ocm region to post bootrom state
- */
-void XOcm_Remap(void);
-/*
- * Performs the smc interface reset
- */
-void XSmc_ResetHw(u32 BaseAddress);
-/*
- * updates the MIO registers with reset values
- */
-void XSlcr_MioWriteResetValues(void);
-/*
- * updates the PLL and clock registers with reset values
- */
-void XSlcr_PllWriteResetValues(void);
-/*
- * Disables the level shifters
- */
-void XSlcr_DisableLevelShifters(void);
-/*
- * provides softreset to the GPIO interface
- */
-void XSlcr_GpioPsReset(void);
-/*
- * provides softreset to the DMA interface
- */
-void XSlcr_DmaPsReset(void);
-/*
- * provides softreset to the SMC interface
- */
-void XSlcr_SmcPsReset(void);
-/*
- * provides softreset to the CAN interface
- */
-void XSlcr_CanPsReset(void);
-/*
- * provides softreset to the Uart interface
- */
-void XSlcr_UartPsReset(void);
-/*
- * provides softreset to the I2C interface
- */
-void XSlcr_I2cPsReset(void);
-/*
- * provides softreset to the SPI interface
- */
-void XSlcr_SpiPsReset(void);
-/*
- * provides softreset to the QSPI interface
- */
-void XSlcr_QspiPsReset(void);
-/*
- * provides softreset to the USB interface
- */
-void XSlcr_UsbPsReset(void);
-/*
- * provides softreset to the GEM interface
- */
-void XSlcr_EmacPsReset(void);
-/*
- * provides softreset to the OCM interface
- */
-void XSlcr_OcmReset(void);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_MISC_RESET_H */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/12/10fd0d565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/12/10fd0d565243001d18b399c1eb9b3628
deleted file mode 100644
index e9a9ace..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/12/10fd0d565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,124 +0,0 @@
-;/******************************************************************************
-;* Copyright (c) 2020 - 2021 Xilinx, Inc. All rights reserved.
-;*
-;* SPDX-License-Identifier: MIT
-;*
-;******************************************************************************/
-;/*****************************************************************************/
-;/**
-;* @file asm_vectors.S
-;*
-;* This file contains the initial vector table for the Cortex R5 processor
-;* as per armclang compiler
-;*
-;*
-;* MODIFICATION HISTORY:
-;*
-;* Ver Who Date Changes
-;* ----- ------- -------- ---------------------------------------------------
-;* 7.3 dp 06/25/20 Initial version for armclang
-;*
-;*
-;* @note
-;*
-;* None.
-;*
-;******************************************************************************/
-
- EXPORT _vector_table
-
- IMPORT _boot
- IMPORT FIQInterrupt
- IMPORT IRQInterrupt
- IMPORT SWInterrupt
- IMPORT DataAbortInterrupt
- IMPORT PrefetchAbortInterrupt
- IMPORT UndefinedExceptionAddr
- IMPORT UndefinedException
- IMPORT DataAbortAddr
- IMPORT PrefetchAbortAddr
-
- EXPORT IRQHandler
-
- AREA |vectors|, CODE
- REQUIRE8 {TRUE}
- PRESERVE8 {TRUE}
- ENTRY ; Define this an entry point
-
-_vector_table
- ldr pc, =_boot
- ldr pc, =Undefined
- ldr pc, =SVCHandler
- ldr pc, =PrefetchAbortHandler
- ldr pc, =DataAbortHandler
- NOP ;Placeholder for address exception vector
- ldr pc, =IRQHandler
- ldr pc, =FIQHandler
-
-IRQHandler ;IRQ vector handler
- stmdb sp!,{r0-r3,r12,lr} ;state save from compiled code
-#ifndef __SOFTFP__
-
- vpush {d0-d7} ;Store floating point registers/
- vmrs r1, FPSCR
- push {r1}
- vmrs r1, FPEXC
- push {r1}
-#endif
- bl IRQInterrupt ;IRQ vector
-#ifndef __SOFTFP__
-
- pop {r1} ;Restore floating point registers
- vmsr FPEXC, r1
- pop {r1}
- vmsr FPSCR, r1
- vpop {d0-d7}
-#endif
- ldmia sp!,{r0-r3,r12,lr} ;state restore from compiled code
- subs pc, lr, #4 ;adjust return
-FIQHandler ;FIQ vector handler
- stmdb sp!,{r0-r3,r12,lr} ;state save from compiled code
-FIQLoop
- bl FIQInterrupt ;FIQ vector
- ldmia sp!,{r0-r3,r12,lr} ;state restore from compiled code
- subs pc, lr, #4 ;adjust return
-
-Undefined ;Undefined handler
- stmdb sp!,{r0-r3,r12,lr} ;state save from compiled code
- ldr r0, =UndefinedExceptionAddr
- sub r1, lr, #4
- str r1, [r0] ;Store address of instruction causing undefined exception
-
- bl UndefinedException ;UndefinedException: call C function here
- ldmia sp!,{r0-r3,r12,lr} ;state restore from compiled code
- movs pc, lr
-
-SVCHandler ;SWI handler
- stmdb sp!,{r0-r3,r12,lr} ;state save from compiled code
- tst r0, #0x20 ;check the T bit
- ldrneh r0, [lr,#-2] ;Thumb mode
- bicne r0, r0, #0xff00 ;Thumb mode
- ldreq r0, [lr,#-4] ;ARM mode
- biceq r0, r0, #0xff000000 ;ARM mode
- bl SWInterrupt ;SWInterrupt: call C function here
- ldmia sp!,{r0-r3,r12,lr} ;state restore from compiled code
- movs pc, lr ;adjust return
-
-DataAbortHandler ;Data Abort handler
- stmdb sp!,{r0-r3,r12,lr} ;state save from compiled code
- ldr r0, =DataAbortAddr
- sub r1, lr, #8
- str r1, [r0] ;Stores instruction causing data abort
- bl DataAbortInterrupt ;ataAbortInterrupt :call C function here
- ldmia sp!,{r0-r3,r12,lr} ;state restore from compiled code
- subs pc, lr, #8 ;adjust return
-
-PrefetchAbortHandler ;Prefetch Abort handler
- stmdb sp!,{r0-r3,r12,lr} ;state save from compiled code
- ldr r0, =PrefetchAbortAddr
- sub r1, lr, #4
- str r1, [r0] ;Stores instruction causing prefetch abort
- bl PrefetchAbortInterrupt ;PrefetchAbortInterrupt: call C function here
- ldmia sp!,{r0-r3,r12,lr} ;state restore from compiled code
- subs pc, lr, #4 ;adjust return
- END
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/12/204efb575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/12/204efb575243001d18b399c1eb9b3628
deleted file mode 100644
index 171e00b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/12/204efb575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1603 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xqspips.c
-* @addtogroup qspips_v3_9
-* @{
-*
-* Contains implements the interface functions of the XQspiPs driver.
-* See xqspips.h for a detailed description of the device and driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00 sdm 11/25/10 First release
-* 2.00a kka 07/25/12 Removed XQspiPs_GetWriteData API.
-* The XQspiPs_SetSlaveSelect has been modified to remove
-* the argument of the slave select as the QSPI controller
-* only supports one slave.
-* XQspiPs_GetSlaveSelect API has been removed
-* Added logic to XQspiPs_GetReadData to handle data
-* shift for normal data reads and instruction/status
-* reads differently based on the ShiftReadData flag.
-* Removed the selection for the following options:
-* Master mode (XQSPIPS_MASTER_OPTION) and
-* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
-* as the QSPI driver supports the Master mode
-* and Flash Interface mode and doesnot support
-* Slave mode or the legacy mode.
-* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
-* APIs so that the last argument (IsInst) specifying whether
-* it is instruction or data has been removed. The first byte
-* in the SendBufPtr argument of these APIs specify the
-* instruction to be sent to the Flash Device.
-* The XQspiPs_PolledTransfer function has been updated
-* to fill the data to fifo depth.
-* This version of the driver fixes CRs 670197/663787.
-* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
-* Created macros XQspiPs_IsManualStart and
-* XQspiPs_IsManualChipSelect.
-* Changed QSPI transfer logic for polled and interrupt
-* modes to be based on filled tx fifo count and receive
-* based on it. RXNEMPTY interrupt is not used.
-* Added assertions to XQspiPs_LqspiRead function.
-*
-* 2.02a hk 05/14/13 Added enable and disable to the XQspiPs_LqspiRead()
-* function
-* Added instructions for bank selection, die erase and
-* flag status register to the flash instruction table
-* Handling for instructions not in flash instruction
-* table added. Checking for Tx FIFO empty when switching from
-* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
-* byte count 3 (spansion), instruction size and TXD register
-* changed accordingly. CR# 712502 and 703869.
-* Added (#ifdef linear base address) in the Linear read function.
-* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to
-* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
-* XQspiPs_LqspiRead function. Fix for CR#718141
-*
-* 2.03a hk 09/05/13 Modified polled and interrupt transfers to make use of
-* thresholds. This is to improve performance.
-* Added RX and TX threshold reset to one in XQspiPs_Abort.
-* Added RX threshold reset(1) after transfer in polled and
-* interrupt transfers. Made changes to make sure threshold
-* change is done only when no transfer is in progress.
-* 3.1 hk 08/13/14 When writing to the configuration register, set/reset
-* required bits leaving reserved bits untouched. CR# 796813.
-* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
-* controller does not update FIFO status flags as expected
-* when thresholds are used.
-* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
-* to remove compilation warnings. CR# 868893.
-* 3.5 tjs 13/08/18 Fixed compilation warnings for ARMCC.
-* 3.6 akm 03/28/19 Fixed memory leak issue while reading from qspi.(CR#1016357)
-* 3.6 akm 04/15/19 Modified the mask in XQspiPs_GetReadData() API to retrieve
-* configuration register values of both the Flashes in dual
-* parellel connection.
-* 3.7 akm 11/19/19 Fixed Coverity unused value warning in XQspiPs_PolledTransfer()
-* and XQspiPs_Transfer() APIs.
-* 3.7 akm 03/19/20 Modified XQspiPs_PolledTransfer(), XQspiPs_Transfer() and
-* XQspiPs_InterruptHandler() APIs to fill TX FIFO with valid
-* data when RX buffer is not NULL.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xqspips.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef defines qspi flash instruction format
- */
-typedef struct {
- u8 OpCode; /**< Operational code of the instruction */
- u8 InstSize; /**< Size of the instruction including address bytes */
- u8 TxOffset; /**< Register address where instruction has to be
- written */
-} XQspiPsInstFormat;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define ARRAY_SIZE(Array) (sizeof(Array) / sizeof((Array)[0]))
-
-/************************** Function Prototypes ******************************/
-static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size);
-static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
- unsigned ByteCount);
-
-/************************** Variable Definitions *****************************/
-
-/*
- * List of all the QSPI instructions and its format
- */
-static XQspiPsInstFormat FlashInst[] = {
- { XQSPIPS_FLASH_OPCODE_WREN, 1, XQSPIPS_TXD_01_OFFSET },
- { XQSPIPS_FLASH_OPCODE_WRDS, 1, XQSPIPS_TXD_01_OFFSET },
- { XQSPIPS_FLASH_OPCODE_RDSR1, 2, XQSPIPS_TXD_10_OFFSET },
- { XQSPIPS_FLASH_OPCODE_RDSR2, 2, XQSPIPS_TXD_10_OFFSET },
- { XQSPIPS_FLASH_OPCODE_WRSR, 2, XQSPIPS_TXD_10_OFFSET },
- { XQSPIPS_FLASH_OPCODE_PP, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_SE, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_BE_32K, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_BE_4K, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_BE, 1, XQSPIPS_TXD_01_OFFSET },
- { XQSPIPS_FLASH_OPCODE_ERASE_SUS, 1, XQSPIPS_TXD_01_OFFSET },
- { XQSPIPS_FLASH_OPCODE_ERASE_RES, 1, XQSPIPS_TXD_01_OFFSET },
- { XQSPIPS_FLASH_OPCODE_RDID, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_NORM_READ, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_FAST_READ, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_DUAL_READ, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_QUAD_READ, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_DUAL_IO_READ, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_QUAD_IO_READ, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_BRWR, 2, XQSPIPS_TXD_10_OFFSET },
- { XQSPIPS_FLASH_OPCODE_BRRD, 2, XQSPIPS_TXD_10_OFFSET },
- { XQSPIPS_FLASH_OPCODE_EARWR, 2, XQSPIPS_TXD_10_OFFSET },
- { XQSPIPS_FLASH_OPCODE_EARRD, 2, XQSPIPS_TXD_10_OFFSET },
- { XQSPIPS_FLASH_OPCODE_DIE_ERASE, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_READ_FLAG_SR, 2, XQSPIPS_TXD_10_OFFSET },
- { XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR, 1, XQSPIPS_TXD_01_OFFSET },
- /* Add all the instructions supported by the flash device */
-};
-
-/*****************************************************************************/
-/**
-*
-* Initializes a specific XQspiPs instance such that the driver is ready to use.
-*
-* The state of the device after initialization is:
-* - Master mode
-* - Active high clock polarity
-* - Clock phase 0
-* - Baud rate divisor 2
-* - Transfer width 32
-* - Master reference clock = pclk
-* - No chip select active
-* - Manual CS and Manual Start disabled
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param ConfigPtr is a reference to a structure containing information
-* about a specific QSPI device. This function initializes an
-* InstancePtr object for a specific device specified by the
-* contents of Config.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. The caller is responsible for keeping the address
-* mapping from EffectiveAddr to the device physical base address
-* unchanged once this function is invoked. Unexpected errors may
-* occur if the address mapping changes after this function is
-* called. If address translation is not used, use
-* ConfigPtr->Config.BaseAddress for this device.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_DEVICE_IS_STARTED if the device is already started.
-* It must be stopped to re-initialize.
-*
-* @note None.
-*
-******************************************************************************/
-int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *ConfigPtr,
- u32 EffectiveAddr)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
-
- /*
- * If the device is busy, disallow the initialize and return a status
- * indicating it is already started. This allows the user to stop the
- * device and re-initialize, but prevents a user from inadvertently
- * initializing. This assumes the busy flag is cleared at startup.
- */
- if (InstancePtr->IsBusy == TRUE) {
- return XST_DEVICE_IS_STARTED;
- }
-
- /*
- * Set some default values.
- */
- InstancePtr->IsBusy = FALSE;
-
- InstancePtr->Config.BaseAddress = EffectiveAddr;
- InstancePtr->StatusHandler = StubStatusHandler;
-
- InstancePtr->SendBufferPtr = NULL;
- InstancePtr->RecvBufferPtr = NULL;
- InstancePtr->RequestedBytes = 0;
- InstancePtr->RemainingBytes = 0;
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- InstancePtr->Config.ConnectionMode = ConfigPtr->ConnectionMode;
-
- /*
- * Reset the QSPI device to get it into its initial state. It is
- * expected that device configuration will take place after this
- * initialization is done, but before the device is started.
- */
- XQspiPs_Reset(InstancePtr);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Resets the QSPI device. Reset must only be called after the driver has been
-* initialized. Any data transfer that is in progress is aborted.
-*
-* The upper layer software is responsible for re-configuring (if necessary)
-* and restarting the QSPI device after the reset.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XQspiPs_Reset(XQspiPs *InstancePtr)
-{
- u32 ConfigReg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Abort any transfer that is in progress
- */
- XQspiPs_Abort(InstancePtr);
-
- /*
- * Write default value to configuration register.
- * Do not modify reserved bits.
- */
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_RESET_MASK_SET;
- ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET,
- ConfigReg);
-}
-
-/*****************************************************************************/
-/**
-*
-* Aborts a transfer in progress by disabling the device and flush the RxFIFO.
-* The byte counts are cleared, the busy flag is cleared.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return None.
-*
-* @note
-*
-* This function does a read/modify/write of the config register. The user of
-* this function needs to take care of critical sections.
-*
-******************************************************************************/
-void XQspiPs_Abort(XQspiPs *InstancePtr)
-{
- u32 ConfigReg;
- u32 IsLock;
-
- XQspiPs_Disable(InstancePtr);
-
- /*
- * De-assert slave select lines.
- */
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
-
- /*
- * QSPI Software Reset
- */
- IsLock = XQspiPs_ReadReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCKSTA);
- if (IsLock) {
- XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_UNLOCK,
- SLCR_UNLOCK_MASK);
- }
- XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL,
- LQSPI_RST_CTRL_MASK);
- XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL, 0x0);
- if (IsLock) {
- XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCK,
- SLCR_LOCK_MASK);
- }
-
- /*
- * Set the RX and TX FIFO threshold to reset value (one)
- */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
-
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_TXWR_OFFSET, XQSPIPS_TXWR_RESET_VALUE);
-
- InstancePtr->RemainingBytes = 0;
- InstancePtr->RequestedBytes = 0;
- InstancePtr->IsBusy = FALSE;
-}
-
-/*****************************************************************************/
-/**
-*
-* Transfers specified data on the QSPI bus. Initiates bus communication and
-* sends/receives data to/from the selected QSPI slave. For every byte sent,
-* a byte is received.
-*
-* The caller has the option of providing two different buffers for send and
-* receive, or one buffer for both send and receive, or no buffer for receive.
-* The receive buffer must be at least as big as the send buffer to prevent
-* unwanted memory writes. This implies that the byte count passed in as an
-* argument must be the smaller of the two buffers if they differ in size.
-* Here are some sample usages:
-*
-* XQspiPs_Transfer(InstancePtr, SendBuf, RecvBuf, ByteCount)
-* The caller wishes to send and receive, and provides two different
-* buffers for send and receive.
-*
-* XQspiPs_Transfer(InstancePtr, SendBuf, NULL, ByteCount)
-* The caller wishes only to send and does not care about the received
-* data. The driver ignores the received data in this case.
-*
-* XQspiPs_Transfer(InstancePtr, SendBuf, SendBuf, ByteCount)
-* The caller wishes to send and receive, but provides the same buffer
-* for doing both. The driver sends the data and overwrites the send
-* buffer with received data as it transfers the data.
-*
-* XQspiPs_Transfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
-* The caller wishes to only receive and does not care about sending
-* data. In this case, the caller must still provide a send buffer, but
-* it can be the same as the receive buffer if the caller does not care
-* what it sends. The device must send N bytes of data if it wishes to
-* receive N bytes of data.
-*
-* Although this function takes entire buffers as arguments, the driver can only
-* transfer a limited number of bytes at a time, limited by the size of the
-* FIFO. A call to this function only starts the transfer, then subsequent
-* transfers of the data is performed by the interrupt service routine until
-* the entire buffer has been transferred. The status callback function is
-* called when the entire buffer has been sent/received.
-*
-* This function is non-blocking. The SetSlaveSelect function must be called
-* prior to this function.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param SendBufPtr is a pointer to a data buffer that needs to be
-* transmitted. This buffer must not be NULL.
-* @param RecvBufPtr is a pointer to a buffer for received data.
-* This argument can be NULL if do not care about receiving.
-* @param ByteCount contains the number of bytes to send/receive.
-* The number of bytes received always equals the number of bytes
-* sent.
-*
-* @return
-* - XST_SUCCESS if the buffers are successfully handed off to the
-* device for transfer.
-* - XST_DEVICE_BUSY indicates that a data transfer is already in
-* progress. This is determined by the driver.
-*
-* @note
-*
-* This function is not thread-safe. The higher layer software must ensure that
-* no two threads are transferring data on the QSPI bus at the same time.
-*
-******************************************************************************/
-s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
- u32 ByteCount)
-{
- u32 StatusReg;
- u32 ConfigReg;
- u8 Instruction;
- u32 Data;
- unsigned int Index;
- u8 TransCount = 0;
- XQspiPsInstFormat *CurrInst;
- XQspiPsInstFormat NewInst[2];
- u8 SwitchFlag = 0;
-
- CurrInst = &NewInst[0];
-
- /*
- * The RecvBufPtr argument can be null
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(SendBufPtr != NULL);
- Xil_AssertNonvoid(ByteCount > 0);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Check whether there is another transfer in progress. Not thread-safe.
- */
- if (InstancePtr->IsBusy) {
- return XST_DEVICE_BUSY;
- }
-
- /*
- * Set the busy flag, which will be cleared in the ISR when the
- * transfer is entirely done.
- */
- InstancePtr->IsBusy = TRUE;
-
- /*
- * Set up buffer pointers.
- */
- InstancePtr->SendBufferPtr = SendBufPtr;
- InstancePtr->RecvBufferPtr = RecvBufPtr;
-
- InstancePtr->RequestedBytes = ByteCount;
- InstancePtr->RemainingBytes = ByteCount;
-
- /*
- * The first byte with every chip-select assertion is always
- * expected to be an instruction for flash interface mode
- */
- Instruction = *InstancePtr->SendBufferPtr;
-
- for (Index = 0 ; Index < ARRAY_SIZE(FlashInst); Index++) {
- if (Instruction == FlashInst[Index].OpCode) {
- break;
- }
- }
-
- /*
- * Set the RX FIFO threshold
- */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT);
-
- /*
- * If the slave select is "Forced" or under manual control,
- * set the slave select now, before beginning the transfer.
- */
- if (XQspiPs_IsManualChipSelect(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET,
- ConfigReg);
- }
-
- /*
- * Enable the device.
- */
- XQspiPs_Enable(InstancePtr);
-
- /*
- * Clear all the interrupts.
- */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_SR_OFFSET,
- XQSPIPS_IXR_WR_TO_CLR_MASK);
-
- if (Index < ARRAY_SIZE(FlashInst)) {
- CurrInst = &FlashInst[Index];
- /*
- * Check for WRSR instruction which has different size for
- * Spansion (3 bytes) and Micron (2 bytes)
- */
- if ((CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) &&
- (ByteCount == 3)) {
- CurrInst->InstSize = 3;
- CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
- }
- }
-
- /*
- * If instruction not present in table
- */
- if (Index == ARRAY_SIZE(FlashInst)) {
- /*
- * Assign current instruction, size and TXD register to be used
- * The InstSize mentioned in case of instructions greater than
- * 4 bytes is not the actual size, but is indicative of
- * the TXD register used.
- * The remaining bytes of the instruction will be transmitted
- * through TXD0 below.
- */
- switch (ByteCount%4) {
- case XQSPIPS_SIZE_ONE:
- CurrInst->OpCode = Instruction;
- CurrInst->InstSize = XQSPIPS_SIZE_ONE;
- CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET;
- if (ByteCount > 4) {
- SwitchFlag = 1;
- }
- break;
- case XQSPIPS_SIZE_TWO:
- CurrInst->OpCode = Instruction;
- CurrInst->InstSize = XQSPIPS_SIZE_TWO;
- CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET;
- if (ByteCount > 4) {
- SwitchFlag = 1;
- }
- break;
- case XQSPIPS_SIZE_THREE:
- CurrInst->OpCode = Instruction;
- CurrInst->InstSize = XQSPIPS_SIZE_THREE;
- CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
- if (ByteCount > 4) {
- SwitchFlag = 1;
- }
- break;
- default:
- CurrInst->OpCode = Instruction;
- CurrInst->InstSize = XQSPIPS_SIZE_FOUR;
- CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET;
- break;
- }
- }
-
- /*
- * If the instruction size in not 4 bytes then the data received needs
- * to be shifted
- */
- if (CurrInst->InstSize != 4) {
- InstancePtr->ShiftReadData = 1;
- } else {
- InstancePtr->ShiftReadData = 0;
- }
-
- /* Get the complete command (flash inst + address/data) */
- Data = *((u32 *)InstancePtr->SendBufferPtr);
- InstancePtr->SendBufferPtr += CurrInst->InstSize;
- InstancePtr->RemainingBytes -= CurrInst->InstSize;
- if (InstancePtr->RemainingBytes < 0) {
- InstancePtr->RemainingBytes = 0;
- }
-
- /* Write the command to the FIFO */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- CurrInst->TxOffset, Data);
- TransCount++;
-
- /*
- * If switching from TXD1/2/3 to TXD0, then start transfer and
- * check for FIFO empty
- */
- if (SwitchFlag == 1) {
- /*
- * If, in Manual Start mode, start the transfer.
- */
- if (XQspiPs_IsManualStart(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(
- InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
- }
- /*
- * Wait for the transfer to finish by polling Tx fifo status.
- */
- do {
- StatusReg = XQspiPs_ReadReg(
- InstancePtr->Config.BaseAddress,
- XQSPIPS_SR_OFFSET);
- } while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0);
-
- }
-
- /*
- * Fill the Tx FIFO with as many bytes as it takes (or as many as
- * we have to send).
- */
- while ((InstancePtr->RemainingBytes > 0) &&
- (TransCount < XQSPIPS_FIFO_DEPTH)) {
- /*
- * In case of Write fill the Tx FIFO with data to be transmitted.
- * In case of Read fill the TX FIFO with first 4bytes(1Byte Command + 3Byte Address)
- * of data from TX Buffer and the remaining bytes(i.e., RequestedBytes - 4)
- * with DUMMY.
- */
- if(InstancePtr->RecvBufferPtr &&
- ((InstancePtr->RequestedBytes - InstancePtr->RemainingBytes) > 4)) {
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_TXD_00_OFFSET, XQSPIPS_DUMMY_TX_DATA);
- } else {
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_TXD_00_OFFSET,
- *((u32 *)InstancePtr->SendBufferPtr));
-
- InstancePtr->SendBufferPtr += 4;
- }
- InstancePtr->RemainingBytes -= 4;
- if (InstancePtr->RemainingBytes < 0) {
- InstancePtr->RemainingBytes = 0;
- }
- TransCount++;
- }
-
- /*
- * Enable QSPI interrupts (connecting to the interrupt controller and
- * enabling interrupts should have been done by the caller).
- */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_IER_OFFSET, XQSPIPS_IXR_RXNEMPTY_MASK |
- XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXOVR_MASK |
- XQSPIPS_IXR_TXUF_MASK);
-
- /*
- * If, in Manual Start mode, Start the transfer.
- */
- if (XQspiPs_IsManualStart(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-* Transfers specified data on the QSPI bus in polled mode.
-*
-* The caller has the option of providing two different buffers for send and
-* receive, or one buffer for both send and receive, or no buffer for receive.
-* The receive buffer must be at least as big as the send buffer to prevent
-* unwanted memory writes. This implies that the byte count passed in as an
-* argument must be the smaller of the two buffers if they differ in size.
-* Here are some sample usages:
-*
-* XQspiPs_PolledTransfer(InstancePtr, SendBuf, RecvBuf, ByteCount)
-* The caller wishes to send and receive, and provides two different
-* buffers for send and receive.
-*
-* XQspiPs_PolledTransfer(InstancePtr, SendBuf, NULL, ByteCount)
-* The caller wishes only to send and does not care about the received
-* data. The driver ignores the received data in this case.
-*
-* XQspiPs_PolledTransfer(InstancePtr, SendBuf, SendBuf, ByteCount)
-* The caller wishes to send and receive, but provides the same buffer
-* for doing both. The driver sends the data and overwrites the send
-* buffer with received data as it transfers the data.
-*
-* XQspiPs_PolledTransfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
-* The caller wishes to only receive and does not care about sending
-* data. In this case, the caller must still provide a send buffer, but
-* it can be the same as the receive buffer if the caller does not care
-* what it sends. The device must send N bytes of data if it wishes to
-* receive N bytes of data.
-*
-*
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param SendBufPtr is a pointer to a data buffer that needs to be
-* transmitted. This buffer must not be NULL.
-* @param RecvBufPtr is a pointer to a buffer for received data.
-* This argument can be NULL if do not care about receiving.
-* @param ByteCount contains the number of bytes to send/receive.
-* The number of bytes received always equals the number of bytes
-* sent.
-* @return
-* - XST_SUCCESS if the buffers are successfully handed off to the
-* device for transfer.
-* - XST_DEVICE_BUSY indicates that a data transfer is already in
-* progress. This is determined by the driver.
-*
-* @note
-*
-* This function is not thread-safe. The higher layer software must ensure that
-* no two threads are transferring data on the QSPI bus at the same time.
-*
-******************************************************************************/
-s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
- u8 *RecvBufPtr, u32 ByteCount)
-{
- u32 StatusReg;
- u32 ConfigReg;
- u8 Instruction;
- u32 Data;
- u8 TransCount;
- unsigned int Index;
- XQspiPsInstFormat *CurrInst;
- XQspiPsInstFormat NewInst[2];
- u8 SwitchFlag = 0;
- u8 IsManualStart = FALSE;
- u32 RxCount = 0;
-
- CurrInst = &NewInst[0];
- /*
- * The RecvBufPtr argument can be NULL.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(SendBufPtr != NULL);
- Xil_AssertNonvoid(ByteCount > 0);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Check whether there is another transfer in progress. Not thread-safe.
- */
- if (InstancePtr->IsBusy) {
- return XST_DEVICE_BUSY;
- }
-
- /*
- * Set the busy flag, which will be cleared when the transfer is
- * entirely done.
- */
- InstancePtr->IsBusy = TRUE;
-
- /*
- * Set up buffer pointers.
- */
- InstancePtr->SendBufferPtr = SendBufPtr;
- InstancePtr->RecvBufferPtr = RecvBufPtr;
-
- InstancePtr->RequestedBytes = ByteCount;
- InstancePtr->RemainingBytes = ByteCount;
-
- /*
- * The first byte with every chip-select assertion is always
- * expected to be an instruction for flash interface mode
- */
- Instruction = *InstancePtr->SendBufferPtr;
-
- for (Index = 0 ; Index < ARRAY_SIZE(FlashInst); Index++) {
- if (Instruction == FlashInst[Index].OpCode) {
- break;
- }
- }
-
- /*
- * Set the RX FIFO threshold
- */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT);
-
- /*
- * If the slave select is "Forced" or under manual control,
- * set the slave select now, before beginning the transfer.
- */
- if (XQspiPs_IsManualChipSelect(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET,
- ConfigReg);
- }
-
- /*
- * Enable the device.
- */
- XQspiPs_Enable(InstancePtr);
-
- if (Index < ARRAY_SIZE(FlashInst)) {
-
- CurrInst = &FlashInst[Index];
- /*
- * Check for WRSR instruction which has different size for
- * Spansion (3 bytes) and Micron (2 bytes)
- */
- if ((CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) &&
- (ByteCount == 3)) {
- CurrInst->InstSize = 3;
- CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
- }
- }
-
- /*
- * If instruction not present in table
- */
- if (Index == ARRAY_SIZE(FlashInst)) {
- /*
- * Assign current instruction, size and TXD register to be used.
- * The InstSize mentioned in case of instructions greater than 4 bytes
- * is not the actual size, but is indicative of the TXD register used.
- * The remaining bytes of the instruction will be transmitted
- * through TXD0 below.
- */
- switch (ByteCount % 4) {
- case XQSPIPS_SIZE_ONE:
- CurrInst->OpCode = Instruction;
- CurrInst->InstSize = XQSPIPS_SIZE_ONE;
- CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET;
- if (ByteCount > 4) {
- SwitchFlag = 1;
- }
- break;
- case XQSPIPS_SIZE_TWO:
- CurrInst->OpCode = Instruction;
- CurrInst->InstSize = XQSPIPS_SIZE_TWO;
- CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET;
- if (ByteCount > 4) {
- SwitchFlag = 1;
- }
- break;
- case XQSPIPS_SIZE_THREE:
- CurrInst->OpCode = Instruction;
- CurrInst->InstSize = XQSPIPS_SIZE_THREE;
- CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
- if (ByteCount > 4) {
- SwitchFlag = 1;
- }
- break;
- default:
- CurrInst->OpCode = Instruction;
- CurrInst->InstSize = XQSPIPS_SIZE_FOUR;
- CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET;
- break;
- }
- }
-
- /*
- * If the instruction size in not 4 bytes then the data received needs
- * to be shifted
- */
- if (CurrInst->InstSize != 4) {
- InstancePtr->ShiftReadData = 1;
- } else {
- InstancePtr->ShiftReadData = 0;
- }
- TransCount = 0;
- /* Get the complete command (flash inst + address/data) */
- Data = *((u32 *)InstancePtr->SendBufferPtr);
- InstancePtr->SendBufferPtr += CurrInst->InstSize;
- InstancePtr->RemainingBytes -= CurrInst->InstSize;
- if (InstancePtr->RemainingBytes < 0) {
- InstancePtr->RemainingBytes = 0;
- }
-
- /* Write the command to the FIFO */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- CurrInst->TxOffset, Data);
- ++TransCount;
-
- /*
- * If switching from TXD1/2/3 to TXD0, then start transfer and
- * check for FIFO empty
- */
- if (SwitchFlag == 1) {
- /*
- * If, in Manual Start mode, start the transfer.
- */
- if (XQspiPs_IsManualStart(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(
- InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
- }
- /*
- * Wait for the transfer to finish by polling Tx fifo status.
- */
- do {
- StatusReg = XQspiPs_ReadReg(
- InstancePtr->Config.BaseAddress,
- XQSPIPS_SR_OFFSET);
- } while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0);
-
- }
-
- /*
- * Check if manual start is selected and store it in a
- * local variable for reference. This is to avoid reading
- * the config register every time.
- */
- IsManualStart = XQspiPs_IsManualStart(InstancePtr);
- /*
- * Fill the DTR/FIFO with as many bytes as it will take (or as
- * many as we have to send).
- */
- while ((InstancePtr->RemainingBytes > 0) &&
- (TransCount < XQSPIPS_FIFO_DEPTH)) {
- /*
- * In case of Write fill the Tx FIFO with data to be transmitted.
- * In case of Read fill the TX FIFO with first 4bytes(1Byte Command + 3Byte Address)
- * of data from TX Buffer and the remaining bytes(i.e., RequestedBytes - 4)
- * with DUMMY.
- */
- if(InstancePtr->RecvBufferPtr &&
- ((InstancePtr->RequestedBytes - InstancePtr->RemainingBytes) > 4)) {
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_TXD_00_OFFSET, XQSPIPS_DUMMY_TX_DATA);
- } else {
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_TXD_00_OFFSET,
- *((u32 *)InstancePtr->SendBufferPtr));
-
- InstancePtr->SendBufferPtr += 4;
- }
- InstancePtr->RemainingBytes -= 4;
- if (InstancePtr->RemainingBytes < 0) {
- InstancePtr->RemainingBytes = 0;
- }
- ++TransCount;
- }
-
- while ((InstancePtr->RemainingBytes > 0) ||
- (InstancePtr->RequestedBytes > 0)) {
-
- /*
- * Fill the TX FIFO with RX threshold no. of entries (or as
- * many as we have to send, in case that's less).
- */
- while ((InstancePtr->RemainingBytes > 0) &&
- (TransCount < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
- /*
- * In case of Write fill the Tx FIFO with data to be transmitted.
- * In case of Read fill the TX FIFO with first 4bytes(1Byte Command + 3Byte Address)
- * of data from TX Buffer and the remaining bytes(i.e., RequestedBytes - 4)
- * with DUMMY.
- */
- if(InstancePtr->RecvBufferPtr &&
- ((InstancePtr->RequestedBytes - InstancePtr->RemainingBytes) > 4)) {
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_TXD_00_OFFSET, XQSPIPS_DUMMY_TX_DATA);
- } else {
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_TXD_00_OFFSET,
- *((u32 *)InstancePtr->SendBufferPtr));
-
- InstancePtr->SendBufferPtr += 4;
- }
- InstancePtr->RemainingBytes -= 4;
- if (InstancePtr->RemainingBytes < 0) {
- InstancePtr->RemainingBytes = 0;
- }
- ++TransCount;
- }
-
- /*
- * If, in Manual Start mode, start the transfer.
- */
- if (IsManualStart == TRUE) {
- ConfigReg = XQspiPs_ReadReg(
- InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
- }
-
- /*
- * Reset TransCount - this is only used to fill TX FIFO
- * in the above loop;
- * RxCount is used to keep track of data received
- */
- TransCount = 0;
-
- /*
- * Wait for RX FIFO to reach threshold (or)
- * TX FIFO to become empty.
- * The latter check is required for
- * small transfers (<32 words) and
- * when the last chunk in a large data transfer is < 32 words.
- */
-
- do {
- StatusReg = XQspiPs_ReadReg(
- InstancePtr->Config.BaseAddress,
- XQSPIPS_SR_OFFSET);
- } while (((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0) &&
- ((StatusReg & XQSPIPS_IXR_RXNEMPTY_MASK) == 0));
-
- /*
- * A transmit has just completed. Process received data
- * and check for more data to transmit.
- * First get the data received as a result of the
- * transmit that just completed. Receive data based on the
- * count obtained while filling tx fifo. Always get
- * the received data, but only fill the receive
- * buffer if it points to something (the upper layer
- * software may not care to receive data).
- */
- while ((InstancePtr->RequestedBytes > 0) &&
- (RxCount < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
- u32 Data;
-
- RxCount++;
-
- if (InstancePtr->RecvBufferPtr != NULL) {
- if (InstancePtr->RequestedBytes < 4) {
- Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_RXD_OFFSET);
- XQspiPs_GetReadData(InstancePtr, Data,
- InstancePtr->RequestedBytes);
- } else {
- (*(u32 *)InstancePtr->RecvBufferPtr) =
- XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_RXD_OFFSET);
- InstancePtr->RecvBufferPtr += 4;
- InstancePtr->RequestedBytes -= 4;
- if (InstancePtr->RequestedBytes < 0) {
- InstancePtr->RequestedBytes = 0;
- }
- }
- } else {
- Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_RXD_OFFSET);
- InstancePtr->RequestedBytes -= 4;
- }
- }
- RxCount = 0;
- }
-
- /*
- * If the Slave select lines are being manually controlled, disable
- * them because the transfer is complete.
- */
- if (XQspiPs_IsManualChipSelect(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
- }
-
- /*
- * Clear the busy flag.
- */
- InstancePtr->IsBusy = FALSE;
-
- /*
- * Disable the device.
- */
- XQspiPs_Disable(InstancePtr);
-
- /*
- * Reset the RX FIFO threshold to one
- */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Read the flash in Linear QSPI mode.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RecvBufPtr is a pointer to a buffer for received data.
-* @param Address is the starting address within the flash from
-* from where data needs to be read.
-* @param ByteCount contains the number of bytes to receive.
-*
-* @return
-* - XST_SUCCESS if read is performed
-* - XST_FAILURE if Linear mode is not set
-*
-* @note None.
-*
-*
-******************************************************************************/
-int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
- u32 Address, unsigned ByteCount)
-{
- int Status = (int)XST_SUCCESS;
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(RecvBufPtr != NULL);
- Xil_AssertNonvoid(ByteCount > 0);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-#ifndef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
-#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
-#endif
- /*
- * Enable the controller
- */
- XQspiPs_Enable(InstancePtr);
-
- if (XQspiPs_GetLqspiConfigReg(InstancePtr) &
- XQSPIPS_LQSPI_CR_LINEAR_MASK) {
- memcpy((void *)RecvBufPtr,
- (const void *)(XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR +
- Address),
- (size_t)ByteCount);
- Status = (int)XST_SUCCESS;
- } else {
- Status = (int)XST_FAILURE;
- }
-
- /*
- * Disable the controller
- */
- XQspiPs_Disable(InstancePtr);
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* Selects the slave with which the master communicates.
-*
-* The user is not allowed to select the slave while a transfer is in progress.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return
-* - XST_SUCCESS if the slave is selected or deselected
-* successfully.
-* - XST_DEVICE_BUSY if a transfer is in progress, slave cannot be
-* changed.
-*
-* @note
-*
-* This function only sets the slave which will be selected when a transfer
-* occurs. The slave is not selected when the QSPI is idle.
-*
-******************************************************************************/
-int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr)
-{
- u32 ConfigReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Do not allow the slave select to change while a transfer is in
- * progress. Not thread-safe.
- */
- if (InstancePtr->IsBusy) {
- return XST_DEVICE_BUSY;
- }
-
- /*
- * Select the slave
- */
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Sets the status callback function, the status handler, which the driver
-* calls when it encounters conditions that should be reported to upper
-* layer software. The handler executes in an interrupt context, so it must
-* minimize the amount of processing performed. One of the following status
-* events is passed to the status handler.
-*
-*
-*
-* XST_SPI_TRANSFER_DONE The requested data transfer is done
-*
-* XST_SPI_TRANSMIT_UNDERRUN As a slave device, the master clocked data
-* but there were none available in the transmit
-* register/FIFO. This typically means the slave
-* application did not issue a transfer request
-* fast enough, or the processor/driver could not
-* fill the transmit register/FIFO fast enough.
-*
-* XST_SPI_RECEIVE_OVERRUN The QSPI device lost data. Data was received
-* but the receive data register/FIFO was full.
-*
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param CallBackRef is the upper layer callback reference passed back
-* when the callback function is invoked.
-* @param FuncPtr is the pointer to the callback function.
-*
-* @return None.
-*
-* @note
-*
-* The handler is called within interrupt context, so it should do its work
-* quickly and queue potentially time-consuming work to a task-level thread.
-*
-******************************************************************************/
-void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
- XQspiPs_StatusHandler FuncPtr)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(FuncPtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- InstancePtr->StatusHandler = FuncPtr;
- InstancePtr->StatusRef = CallBackRef;
-}
-
-/*****************************************************************************/
-/**
-*
-* This is a stub for the status callback. The stub is here in case the upper
-* layers forget to set the handler.
-*
-* @param CallBackRef is a pointer to the upper layer callback reference
-* @param StatusEvent is the event that just occurred.
-* @param ByteCount is the number of bytes transferred up until the event
-* occurred.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
- unsigned ByteCount)
-{
- (void) CallBackRef;
- (void) StatusEvent;
- (void) ByteCount;
-
- Xil_AssertVoidAlways();
-}
-
-/*****************************************************************************/
-/**
-*
-* The interrupt handler for QSPI interrupts. This function must be connected
-* by the user to an interrupt controller.
-*
-* The interrupts that are handled are:
-*
-*
-* - Data Transmit Register (FIFO) Empty. This interrupt is generated when the
-* transmit register or FIFO is empty. The driver uses this interrupt during a
-* transmission to continually send/receive data until the transfer is done.
-*
-* - Data Transmit Register (FIFO) Underflow. This interrupt is generated when
-* the QSPI device, when configured as a slave, attempts to read an empty
-* DTR/FIFO. An empty DTR/FIFO usually means that software is not giving the
-* device data in a timely manner. No action is taken by the driver other than
-* to inform the upper layer software of the error.
-*
-* - Data Receive Register (FIFO) Overflow. This interrupt is generated when the
-* QSPI device attempts to write a received byte to an already full DRR/FIFO.
-* A full DRR/FIFO usually means software is not emptying the data in a timely
-* manner. No action is taken by the driver other than to inform the upper
-* layer software of the error.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return None.
-*
-* @note
-*
-* The slave select register is being set to deselect the slave when a transfer
-* is complete.
-*
-******************************************************************************/
-void XQspiPs_InterruptHandler(void *InstancePtr)
-{
- XQspiPs *QspiPtr = (XQspiPs *)InstancePtr;
- u32 IntrStatus;
- u32 ConfigReg;
- u32 Data;
- u32 TransCount;
- u32 Count = 0;
- unsigned BytesDone; /* Number of bytes done so far. */
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(QspiPtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Immediately clear the interrupts in case the ISR causes another
- * interrupt to be generated. If we clear at the end of the ISR,
- * we may miss newly generated interrupts. This occurs because we
- * transmit from within the ISR, which could potentially cause another
- * TX_EMPTY interrupt.
- */
- IntrStatus = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_SR_OFFSET);
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_SR_OFFSET,
- (IntrStatus & XQSPIPS_IXR_WR_TO_CLR_MASK));
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_IDR_OFFSET,
- XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXNEMPTY_MASK |
- XQSPIPS_IXR_RXOVR_MASK | XQSPIPS_IXR_TXUF_MASK);
-
- if ((IntrStatus & XQSPIPS_IXR_TXOW_MASK) ||
- (IntrStatus & XQSPIPS_IXR_RXNEMPTY_MASK)) {
-
- /*
- * Rx FIFO has just reached threshold no. of entries.
- * Read threshold no. of entries from RX FIFO
- * Another possibility of entering this loop is when
- * the last byte has been transmitted and TX FIFO is empty,
- * in which case, read all the data from RX FIFO.
- * Always get the received data, but only fill the
- * receive buffer if it is not null (it can be null when
- * the device does not care to receive data).
- */
- TransCount = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
- if (TransCount % 4) {
- TransCount = TransCount/4 + 1;
- } else {
- TransCount = TransCount/4;
- }
-
- while ((Count < TransCount) &&
- (Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
-
- if (QspiPtr->RecvBufferPtr != NULL) {
- if (QspiPtr->RequestedBytes < 4) {
- Data = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_RXD_OFFSET);
- XQspiPs_GetReadData(QspiPtr, Data,
- QspiPtr->RequestedBytes);
- } else {
- (*(u32 *)QspiPtr->RecvBufferPtr) =
- XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_RXD_OFFSET);
- QspiPtr->RecvBufferPtr += 4;
- QspiPtr->RequestedBytes -= 4;
- if (QspiPtr->RequestedBytes < 0) {
- QspiPtr->RequestedBytes = 0;
- }
- }
- } else {
- XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_RXD_OFFSET);
- QspiPtr->RequestedBytes -= 4;
- if (QspiPtr->RequestedBytes < 0) {
- QspiPtr->RequestedBytes = 0;
- }
-
- }
- Count++;
- }
- Count = 0;
- /*
- * Interrupt asserted as TX_OW got asserted
- * See if there is more data to send.
- * Fill TX FIFO with RX threshold no. of entries or
- * remaining entries (in case that is less than threshold)
- */
- while ((QspiPtr->RemainingBytes > 0) &&
- (Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
- /*
- * Send more data.
- * In case of Write fill the Tx FIFO with data to be transmitted.
- * In case of Read fill the TX FIFO with first 4bytes(1Byte Command + 3Byte Address)
- * of data from TX Buffer and the remaining bytes(i.e., RequestedBytes - 4)
- * with DUMMY.
- */
- if(QspiPtr->RecvBufferPtr &&
- ((QspiPtr->RequestedBytes - QspiPtr->RemainingBytes) > 4)) {
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_TXD_00_OFFSET, XQSPIPS_DUMMY_TX_DATA);
- } else {
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_TXD_00_OFFSET,
- *((u32 *)QspiPtr->SendBufferPtr));
-
- QspiPtr->SendBufferPtr += 4;
- }
- QspiPtr->RemainingBytes -= 4;
- if (QspiPtr->RemainingBytes < 0) {
- QspiPtr->RemainingBytes = 0;
- }
-
- Count++;
- }
-
- if ((QspiPtr->RemainingBytes == 0) &&
- (QspiPtr->RequestedBytes == 0)) {
- /*
- * No more data to send. Disable the interrupt
- * and inform the upper layer software that the
- * transfer is done. The interrupt will be re-enabled
- * when another transfer is initiated.
- */
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_IDR_OFFSET,
- XQSPIPS_IXR_RXNEMPTY_MASK |
- XQSPIPS_IXR_TXOW_MASK |
- XQSPIPS_IXR_RXOVR_MASK |
- XQSPIPS_IXR_TXUF_MASK);
-
- /*
- * If the Slave select is being manually controlled,
- * disable it because the transfer is complete.
- */
- if (XQspiPs_IsManualChipSelect(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(
- QspiPtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET,
- ConfigReg);
- }
-
- /*
- * Clear the busy flag.
- */
- QspiPtr->IsBusy = FALSE;
-
- /*
- * Disable the device.
- */
- XQspiPs_Disable(QspiPtr);
-
- /*
- * Reset the RX FIFO threshold to one
- */
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
-
- QspiPtr->StatusHandler(QspiPtr->StatusRef,
- XST_SPI_TRANSFER_DONE,
- QspiPtr->RequestedBytes);
- } else {
- /*
- * Enable the TXOW interrupt.
- */
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_IER_OFFSET,
- XQSPIPS_IXR_RXNEMPTY_MASK |
- XQSPIPS_IXR_TXOW_MASK |
- XQSPIPS_IXR_RXOVR_MASK |
- XQSPIPS_IXR_TXUF_MASK);
- /*
- * If, in Manual Start mode, start the transfer.
- */
- if (XQspiPs_IsManualStart(QspiPtr)) {
- ConfigReg = XQspiPs_ReadReg(
- QspiPtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
- XQspiPs_WriteReg(
- QspiPtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
- }
- }
- }
-
- /*
- * Check for overflow and underflow errors.
- */
- if (IntrStatus & XQSPIPS_IXR_RXOVR_MASK) {
- BytesDone = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
- QspiPtr->IsBusy = FALSE;
-
- /*
- * If the Slave select lines is being manually controlled,
- * disable it because the transfer is complete.
- */
- if (XQspiPs_IsManualChipSelect(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(
- QspiPtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
- }
-
- /*
- * Disable the device.
- */
- XQspiPs_Disable(QspiPtr);
-
- /*
- * Reset the RX FIFO threshold to one
- */
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
-
- QspiPtr->StatusHandler(QspiPtr->StatusRef,
- XST_SPI_RECEIVE_OVERRUN, BytesDone);
- }
-
- if (IntrStatus & XQSPIPS_IXR_TXUF_MASK) {
- BytesDone = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
-
- QspiPtr->IsBusy = FALSE;
- /*
- * If the Slave select lines is being manually controlled,
- * disable it because the transfer is complete.
- */
- if (XQspiPs_IsManualChipSelect(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(
- QspiPtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
- }
-
- /*
- * Disable the device.
- */
- XQspiPs_Disable(QspiPtr);
-
- /*
- * Reset the RX FIFO threshold to one
- */
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
-
- QspiPtr->StatusHandler(QspiPtr->StatusRef,
- XST_SPI_TRANSMIT_UNDERRUN, BytesDone);
- }
-}
-
-
-/*****************************************************************************/
-/**
-*
-* Copies data from Data to the Receive buffer.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param Data is the data which needs to be copied to the Rx buffer.
-* @param Size is the number of bytes to be copied to the Receive buffer.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size)
-{
- u8 DataByte3;
-
- if (InstancePtr->RecvBufferPtr) {
- switch (Size) {
- case 1:
- if (InstancePtr->ShiftReadData == 1) {
- *((u8 *)InstancePtr->RecvBufferPtr) =
- ((Data & 0xFF000000) >> 24);
- } else {
- *((u8 *)InstancePtr->RecvBufferPtr) =
- (Data & 0xFF);
- }
- InstancePtr->RecvBufferPtr += 1;
- break;
- case 2:
- if (InstancePtr->ShiftReadData == 1) {
- *((u16 *)InstancePtr->RecvBufferPtr) =
- ((Data >> 16) & 0xFF00) |
- ((Data >> 8) & 0xFF);
- } else {
- *((u16 *)InstancePtr->RecvBufferPtr) =
- (Data & 0xFFFF);
- }
- InstancePtr->RecvBufferPtr += 2;
- break;
- case 3:
- if (InstancePtr->ShiftReadData == 1) {
- *((u16 *)InstancePtr->RecvBufferPtr) =
- ((Data & 0x00FFFF00) >> 8);
- InstancePtr->RecvBufferPtr += 2;
- DataByte3 = ((Data & 0xFF000000) >> 24);
- *((u8 *)InstancePtr->RecvBufferPtr) = DataByte3;
- } else {
- *((u16 *)InstancePtr->RecvBufferPtr) =
- (Data & 0xFFFF);
- InstancePtr->RecvBufferPtr += 2;
- DataByte3 = ((Data & 0x00FF0000) >> 16);
- *((u8 *)InstancePtr->RecvBufferPtr) = DataByte3;
- }
- InstancePtr->RecvBufferPtr += 1;
- break;
- default:
- /* This will never execute */
- break;
- }
- }
- InstancePtr->ShiftReadData = 0;
- InstancePtr->RequestedBytes -= Size;
- if (InstancePtr->RequestedBytes < 0) {
- InstancePtr->RequestedBytes = 0;
- }
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/12/312e75575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/12/312e75575243001d18b399c1eb9b3628
deleted file mode 100644
index 9794da0..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/12/312e75575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,350 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xenv_standalone.h
-*
-* Defines common services specified by xenv.h.
-*
-* @note
-* This file is not intended to be included directly by driver code.
-* Instead, the generic xenv.h file is intended to be included by driver
-* code.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a wgr 02/28/07 Added cache handling macros.
-* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
-* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
-* used under Xilinx standalone BSP.
-* 1.00a xd 11/03/04 Improved support for doxygen.
-* 1.00a rmm 03/21/02 First release
-* 1.00a wgr 03/22/07 Converted to new coding style.
-* 1.00a rpm 06/29/07 Added udelay macro for standalone
-* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
-* to in MICROBLAZE section
-* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
-*
-*
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XENV_STANDALONE_H
-#define XENV_STANDALONE_H
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-/******************************************************************************
- *
- * Get the processor dependent includes
- *
- ******************************************************************************/
-
-#include
-
-#if defined __MICROBLAZE__
-# include "mb_interface.h"
-# include "xparameters.h" /* XPAR constants used below in MB section */
-
-#elif defined __PPC__
-# include "sleep.h"
-# include "xcache_l.h" /* also include xcache_l.h for caching macros */
-#endif
-
-/******************************************************************************
- *
- * MEMCPY / MEMSET related macros.
- *
- * The following are straight forward implementations of memset and memcpy.
- *
- * NOTE: memcpy may not work if source and target memory area are overlapping.
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
- *
- * Copies a non-overlapping block of memory.
- *
- * @param DestPtr
- * Destination address to copy data to.
- *
- * @param SrcPtr
- * Source address to copy data from.
- *
- * @param Bytes
- * Number of bytes to copy.
- *
- * @return None.
- *
- * @note
- * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
- *
- * @note
- * This implementation MAY BREAK work if source and target memory
- * area are overlapping.
- *
- *****************************************************************************/
-
-#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
- memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
-
-
-
-/*****************************************************************************/
-/**
- *
- * Fills an area of memory with constant data.
- *
- * @param DestPtr
- * Destination address to copy data to.
- *
- * @param Data
- * Value to set.
- *
- * @param Bytes
- * Number of bytes to copy.
- *
- * @return None.
- *
- * @note
- * The use of XENV_MEM_FILL is deprecated. Use memset() instead.
- *
- *****************************************************************************/
-
-#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
- memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
-
-
-
-/******************************************************************************
- *
- * TIME related macros
- *
- ******************************************************************************/
-
-/**
- * A structure that contains a time stamp used by other time stamp macros
- * defined below. This structure is processor dependent.
- */
-typedef s32 XENV_TIME_STAMP;
-
-/*****************************************************************************/
-/**
- *
- * Time is derived from the 64 bit PPC timebase register
- *
- * @param StampPtr is the storage for the retrieved time stamp.
- *
- * @return None.
- *
- * @note
- *
- * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_GET(StampPtr)
-
-/*****************************************************************************/
-/**
- *
- * This macro is not yet implemented and always returns 0.
- *
- * @param Stamp1Ptr is the first sampled time stamp.
- * @param Stamp2Ptr is the second sampled time stamp.
- *
- * @return 0
- *
- * @note
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
-
-/*****************************************************************************/
-/**
- *
- * This macro is not yet implemented and always returns 0.
- *
- * @param Stamp1Ptr is the first sampled time stamp.
- * @param Stamp2Ptr is the second sampled time stamp.
- *
- * @return 0
- *
- * @note
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
-
-/*****************************************************************************/
-/**
- * XENV_USLEEP(unsigned delay)
- *
- * Delay the specified number of microseconds. Not implemented without OS
- * support.
- *
- * @param delay
- * Number of microseconds to delay.
- *
- * @return None.
- *
- *****************************************************************************/
-
-#ifdef __PPC__
-#define XENV_USLEEP(delay) usleep(delay)
-#define udelay(delay) usleep(delay)
-#else
-#define XENV_USLEEP(delay)
-#define udelay(delay)
-#endif
-
-
-/******************************************************************************
- *
- * CACHE handling macros / mappings
- *
- ******************************************************************************/
-/******************************************************************************
- *
- * Processor independent macros
- *
- ******************************************************************************/
-
-#define XCACHE_ENABLE_CACHE() \
- { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
-
-#define XCACHE_DISABLE_CACHE() \
- { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
-
-
-/******************************************************************************
- *
- * MicroBlaze case
- *
- * NOTE: Currently the following macros will only work on systems that contain
- * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
- * system is built using a xparameters.h file.
- *
- ******************************************************************************/
-
-#if defined __MICROBLAZE__
-
-/* Check if MicroBlaze data cache was built into the core.
- */
-#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
-# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
-# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
-# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
-
-# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
- microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
-
-#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
-# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
-#else
-# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
-#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
-
-#else
-# define XCACHE_ENABLE_DCACHE()
-# define XCACHE_DISABLE_DCACHE()
-# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
-#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
-
-
-/* Check if MicroBlaze instruction cache was built into the core.
- */
-#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
-# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
-# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
-
-# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
-
-# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
- microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
-
-#else
-# define XCACHE_ENABLE_ICACHE()
-# define XCACHE_DISABLE_ICACHE()
-#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
-
-
-/******************************************************************************
- *
- * PowerPC case
- *
- * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
- * specific memory region (0x80000001). Each bit (0-30) in the regions
- * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
- * range.
- *
- * regions --> cached address range
- * ------------|--------------------------------------------------
- * 0x80000000 | [0, 0x7FFFFFF]
- * 0x00000001 | [0xF8000000, 0xFFFFFFFF]
- * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
- *
- ******************************************************************************/
-
-#elif defined __PPC__
-
-#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
-#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
-#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
-#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
-
-#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
- XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
-
-#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
-
-#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
-
-
-/******************************************************************************
- *
- * Unknown processor / architecture
- *
- ******************************************************************************/
-
-#else
-/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* #ifndef XENV_STANDALONE_H */
-
- /**
- *@endcond
- */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/12/50bb3e545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/12/50bb3e545243001d18b399c1eb9b3628
deleted file mode 100644
index 853ef6b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/12/50bb3e545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,412 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_io.h
-*
-* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
-*
-* The xil_io.h file contains the interface for the general I/O component, which
-* encapsulates the Input/Output functions for the processors that do not
-* require any special I/O handling.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/29/14 First release
-* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
-* ARM processors
-* 7.20 har 01/03/20 Added Xil_SecureOut32 for avoiding blindwrite for
-* CR-1049218
-* 7.30 kpt 09/21/20 Moved Xil_EndianSwap16 and Xil_EndianSwap32 to
-* xil_io.h and made them as static inline
-* am 10/13/20 Changed the return type of Xil_SecureOut32 function
-* from u32 to int
-* 7.50 dp 02/12/21 Fix compilation error in Xil_EndianSwap32() that occur
-* when -Werror=conversion compiler flag is enabled
-* 7.5 mus 05/17/21 Update the functions with comments. It fixes CR#1067739.
-*
-*
-******************************************************************************/
-
-#ifndef XIL_IO_H /* prevent circular inclusions */
-#define XIL_IO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_printf.h"
-#include "xstatus.h"
-
-#if defined (__MICROBLAZE__)
-#include "mb_interface.h"
-#else
-#include "xpseudo_asm.h"
-#endif
-
-/************************** Function Prototypes ******************************/
-#ifdef ENABLE_SAFETY
-extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
-#endif
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#if defined __GNUC__
-#if defined (__MICROBLAZE__)
-# define INST_SYNC mbar(0)
-# define DATA_SYNC mbar(1)
-# else
-# define SYNCHRONIZE_IO dmb()
-# define INST_SYNC isb()
-# define DATA_SYNC dsb()
-# endif
-#else
-# define SYNCHRONIZE_IO
-# define INST_SYNC
-# define DATA_SYNC
-# define INST_SYNC
-# define DATA_SYNC
-#endif
-
-#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
-#define INLINE inline
-#else
-#define INLINE __inline
-#endif
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading
-* from the specified address and returning the 8 bit Value read from
-* that address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 8 bit Value read from the specified input address.
-
-*
-******************************************************************************/
-static INLINE u8 Xil_In8(UINTPTR Addr)
-{
- return *(volatile u8 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading from
-* the specified address and returning the 16 bit Value read from that
-* address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 16 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u16 Xil_In16(UINTPTR Addr)
-{
- return *(volatile u16 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by
-* reading from the specified address and returning the 32 bit Value
-* read from that address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 32 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u32 Xil_In32(UINTPTR Addr)
-{
- return *(volatile u32 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading the
-* 64 bit Value read from that address.
-*
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 64 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u64 Xil_In64(UINTPTR Addr)
-{
- return *(volatile u64 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for an memory location by
-* writing the 8 bit Value to the the specified address.
-*
-* @param Addr: contains the address to perform the output operation
-* @param Value: contains the 8 bit Value to be written at the specified
-* address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
-{
- /* write 8 bit value to specified address */
- volatile u8 *LocalAddr = (volatile u8 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 16 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains the Value to be written at the specified address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
-{
- /* write 16 bit value to specified address */
- volatile u16 *LocalAddr = (volatile u16 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 32 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains the 32 bit Value to be written at the specified
-* address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
-{
- /* write 32 bit value to specified address */
-#ifndef ENABLE_SAFETY
- volatile u32 *LocalAddr = (volatile u32 *)Addr;
- *LocalAddr = Value;
-#else
- XStl_RegUpdate(Addr, Value);
-#endif
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 64 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains 64 bit Value to be written at the specified address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
-{
- /* write 64 bit value to specified address */
- volatile u64 *LocalAddr = (volatile u64 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
- *
- * @brief Performs an output operation for a memory location by writing the
- * 32 bit Value to the the specified address and then reading it
- * back to verify the value written in the register.
- *
- * @param Addr contains the address to perform the output operation
- * @param Value contains 32 bit Value to be written at the specified address
- *
- * @return Returns Status
- * - XST_SUCCESS on success
- * - XST_FAILURE on failure
- *
- *****************************************************************************/
-static INLINE int Xil_SecureOut32(UINTPTR Addr, u32 Value)
-{
- int Status = XST_FAILURE;
- u32 ReadReg;
- u32 ReadRegTemp;
-
- /* writing 32 bit value to specified address */
- Xil_Out32(Addr, Value);
-
- /* verify value written to specified address with multiple reads */
- ReadReg = Xil_In32(Addr);
- ReadRegTemp = Xil_In32(Addr);
-
- if( (ReadReg == Value) && (ReadRegTemp == Value) ) {
- Status = XST_SUCCESS;
- }
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a 16-bit endian conversion.
-*
-* @param Data: 16 bit value to be converted
-*
-* @return 16 bit Data with converted endianness
-*
-******************************************************************************/
-static INLINE __attribute__((always_inline)) u16 Xil_EndianSwap16(u16 Data)
-{
- return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a 32-bit endian conversion.
-*
-* @param Data: 32 bit value to be converted
-*
-* @return 32 bit data with converted endianness
-*
-******************************************************************************/
-static INLINE __attribute__((always_inline)) u32 Xil_EndianSwap32(u32 Data)
-{
- u16 LoWord;
- u16 HiWord;
-
- /* get each of the half words from the 32 bit word */
-
- LoWord = (u16) (Data & 0x0000FFFFU);
- HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
-
- /* byte swap each of the 16 bit half words */
-
- LoWord = (u16)(((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
- HiWord = (u16)(((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
-
- /* swap the half words before returning the value */
-
- return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-# define Xil_In16LE Xil_In16
-# define Xil_In32LE Xil_In32
-# define Xil_Out16LE Xil_Out16
-# define Xil_Out32LE Xil_Out32
-# define Xil_Htons Xil_EndianSwap16
-# define Xil_Htonl Xil_EndianSwap32
-# define Xil_Ntohs Xil_EndianSwap16
-# define Xil_Ntohl Xil_EndianSwap32
-# else
-# define Xil_In16BE Xil_In16
-# define Xil_In32BE Xil_In32
-# define Xil_Out16BE Xil_Out16
-# define Xil_Out32BE Xil_Out32
-# define Xil_Htons(Data) (Data)
-# define Xil_Htonl(Data) (Data)
-# define Xil_Ntohs(Data) (Data)
-# define Xil_Ntohl(Data) (Data)
-#endif
-#else
-# define Xil_In16LE Xil_In16
-# define Xil_In32LE Xil_In32
-# define Xil_Out16LE Xil_Out16
-# define Xil_Out32LE Xil_Out32
-# define Xil_Htons Xil_EndianSwap16
-# define Xil_Htonl Xil_EndianSwap32
-# define Xil_Ntohs Xil_EndianSwap16
-# define Xil_Ntohl Xil_EndianSwap32
-#endif
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE u16 Xil_In16BE(UINTPTR Addr)
-#else
-static INLINE u16 Xil_In16LE(UINTPTR Addr)
-#endif
-#else
-static INLINE u16 Xil_In16BE(UINTPTR Addr)
-#endif
-{
- u16 value = Xil_In16(Addr);
- return Xil_EndianSwap16(value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE u32 Xil_In32BE(UINTPTR Addr)
-#else
-static INLINE u32 Xil_In32LE(UINTPTR Addr)
-#endif
-#else
-static INLINE u32 Xil_In32BE(UINTPTR Addr)
-#endif
-{
- u32 value = Xil_In32(Addr);
- return Xil_EndianSwap32(value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
-#else
-static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
-#endif
-#else
-static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
-#endif
-{
- Value = Xil_EndianSwap16(Value);
- Xil_Out16(Addr, Value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
-#else
-static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
-#endif
-#else
-static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
-#endif
-{
- Value = Xil_EndianSwap32(Value);
- Xil_Out32(Addr, Value);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_io_interfacing_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/12/70de79b75243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/12/70de79b75243001d18b399c1eb9b3628
deleted file mode 100644
index c63db8f..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/12/70de79b75243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,11 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/12/a1dffc585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/12/a1dffc585243001d18b399c1eb9b3628
deleted file mode 100644
index a2443fe..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/12/a1dffc585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,100 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xtime_l.c
-*
-* This file contains low level functions to get/set time from the Global Timer
-* register in the ARM Cortex A9 MP core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 1.00a rp/sdm 11/03/09 Initial release.
-* 3.07a sgd 07/05/12 Updated get/set time functions to make use Global Timer
-* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
-* displaying same warnings multiple times. It fixes CR#1090562.
-*
-*
-* @note None.
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "xtime_l.h"
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER)
-#pragma message ("For the sleep routines, Global timer is being used")
-#endif
-/****************************************************************************/
-/**
-* @brief Set the time in the Global Timer Counter Register.
-*
-* @param Xtime_Global: 64-bit Value to be written to the Global Timer
-* Counter Register.
-*
-* @return None.
-*
-* @note When this function is called by any one processor in a multi-
-* processor environment, reference time will reset/lost for all
-* processors.
-*
-****************************************************************************/
-void XTime_SetTime(XTime Xtime_Global)
-{
- /* Disable Global Timer */
- Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x0);
-
- /* Updating Global Timer Counter Register */
- Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_LOWER_OFFSET, (u32)Xtime_Global);
- Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_UPPER_OFFSET,
- (u32)((u32)(Xtime_Global>>32U)));
-
- /* Enable Global Timer */
- Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x1);
-}
-
-/****************************************************************************/
-/**
-* @brief Get the time from the Global Timer Counter Register.
-*
-* @param Xtime_Global: Pointer to the 64-bit location which will be
-* updated with the current timer value.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XTime_GetTime(XTime *Xtime_Global)
-{
- u32 low;
- u32 high;
-
- /* Reading Global Timer Counter Register */
- do
- {
- high = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET);
- low = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_LOWER_OFFSET);
- } while(Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET) != high);
-
- *Xtime_Global = (((XTime) high) << 32U) | (XTime) low;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/12/d0496d585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/12/d0496d585243001d18b399c1eb9b3628
deleted file mode 100644
index 4366107..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/12/d0496d585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,118 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2017 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_smc.h
-*
-* @addtogroup a53_64_smc_api Cortex A53 64bit EL1 Non-secure SMC Call
-*
-* Cortex A53 64bit EL1 Non-secure SMC Call provides a C wrapper for calling
-* SMC from EL1 Non-secure application to request Secure monitor for secure
-* services. SMC calling conventions should be followed.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.2 pkp 02/16/17 First release
-* 6.4 mus 08/17/17 Added constant define for SMC ID , which is
-* intended to read the version/idcode of the
-* platform
-* 7.1 mus 07/31/19 Added support for Versal
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 01/29/10 First release
-* 1.00a ecm 06/24/10 Moved the L1 and L2 specific function prototypes
-* to xil_cache_mach.h to give access to sophisticated users
-* 3.02a sdm 04/07/11 Updated Flush/InvalidateRange APIs to flush/invalidate
-* L1 and L2 caches in a single loop and used dsb, L2 sync
-* at the end of the loop.
-* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
-* APIs.
-* 3.07a asa 07/16/12 Corrected the L1 and L2 cache invalidation order.
-* 3.07a sgd 09/18/12 Corrected the L2 cache enable and disable sequence.
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-* 3.10a asa 05/13/13 Modified cache disable APIs. The L2 cache disable
-* operation was being done with L1 Data cache disabled. This is
-* fixed so that L2 cache disable operation happens independent of
-* L1 cache disable operation. This fixes CR #706464.
-* Changes are done to do a L2 cache sync (poll reg7_?cache_?sync).
-* This is done to fix the CR #700542.
-* 3.11a asa 09/23/13 Modified the Xil_DCacheFlushRange and
-* Xil_DCacheInvalidateRange to fix potential issues. Fixed other
-* relevant cache APIs to disable and enable back the interrupts.
-* This fixes CR #663885.
-* 3.11a asa 09/28/13 Made changes for L2 cache sync operation. It is found
-* out that for L2 cache flush/clean/invalidation by cache lines
-* does not need a cache sync as these are atomic nature. Similarly
-* figured out that for complete L2 cache flush/invalidation by way
-* we need to wait for some more time in a loop till the status
-* shows that the cache operation is completed.
-* 4.00 pkp 24/01/14 Modified Xil_DCacheInvalidateRange to fix the bug. Few
-* cache lines were missed to invalidate when unaligned address
-* invalidation was accommodated. That fixes CR #766768.
-* Also in Xil_L1DCacheInvalidate, while invalidating all L1D cache
-* stack memory which contains return address was invalidated. So
-* stack memory was flushed first and then L1D cache is invalidated.
-* This is done to fix CR #763829
-* 4.01 asa 05/09/14 Made changes in cortexa9/xil_cache.c to fix CR# 798230.
-* 4.02 pkp 06/27/14 Added notes to Xil_L1DCacheInvalidateRange function for
-* explanation of CR#785243
-* 5.00 kvn 12/15/14 Xil_L2CacheInvalidate was modified to fix CR# 838835. L2 Cache
-* has stack memory which has return address. Before invalidating
-* cache, stack memory was flushed first and L2 Cache is invalidated.
-* 5.01 pkp 05/12/15 Xil_DCacheInvalidateRange and Xil_DCacheFlushRange is modified
-* to remove unnecessary dsb in the APIs. Instead of using dsb
-* for L2 Cache, L2CacheSync has been used for each L2 cache line
-* and single dsb has been used for L1 cache. Also L2CacheSync is
-* added into Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate
-* and Xil_L2CacheInvalidate APIs are modified to flush the complete
-* stack instead of just System Stack
-* 5.03 pkp 10/07/15 L2 Cache functionalities are avoided for the OpenAMP slave
-* application(when USE_AMP flag is defined for BSP) as master CPU
-* would be utilizing L2 cache for its operation
-* 6.6 mus 12/07/17 Errata 753970 is not applicable for the PL130 cache controller
-* version r0p2, which is present in zynq. So,removed the handling
-* related to same.It fixes CR#989132.
-* 6.6 asa 16/01/18 Changes made in Xil_L1DCacheInvalidate and Xil_L2CacheInvalidate
-* routines to ensure the stack data flushed only when the respective
-* caches are enabled. This fixes CR-992023.
-* 7.5 mus 01/19/21 Implement workaround for errata#588369 in Xil_DCacheFlushRange.
-* It fixes CR#1086022.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xil_cache_l.h"
-#include "xil_io.h"
-#include "xpseudo_asm.h"
-#include "xparameters.h"
-#include "xreg_cortexa9.h"
-#include "xl2cc.h"
-#include "xil_errata.h"
-#include "xil_exception.h"
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#define IRQ_FIQ_MASK 0xC0U /* Mask IRQ and FIQ interrupts in cpsr */
-
-#ifdef __GNUC__
- extern s32 _stack_end;
- extern s32 __undef_stack;
-#endif
-
-#ifndef USE_AMP
-/****************************************************************************
-*
-* Access L2 Debug Control Register.
-*
-* @param Value, value to be written to Debug Control Register.
-*
-* @return None.
-*
-****************************************************************************/
-#ifdef __GNUC__
-static inline void Xil_L2WriteDebugCtrl(u32 Value)
-#else
-static void Xil_L2WriteDebugCtrl(u32 Value)
-#endif
-{
-#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DEBUG_CTRL_OFFSET, Value);
-#else
- (void)(Value);
-#endif
-}
-
-/****************************************************************************
-*
-* Perform L2 Cache Sync Operation.
-*
-* @return None.
-*
-****************************************************************************/
-#ifdef __GNUC__
-static inline void Xil_L2CacheSync(void)
-#else
-static void Xil_L2CacheSync(void)
-#endif
-{
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0U);
-}
-#endif
-/****************************************************************************/
-/**
-* @brief Enable the Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheEnable(void)
-{
- Xil_L1DCacheEnable();
-#ifndef USE_AMP
- Xil_L2CacheEnable();
-#endif
-}
-
-/****************************************************************************/
-/**
-* @brief Disable the Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheDisable(void)
-{
-#ifndef USE_AMP
- Xil_L2CacheDisable();
-#endif
- Xil_L1DCacheDisable();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the entire Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheInvalidate(void)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-#ifndef USE_AMP
- Xil_L2CacheInvalidate();
-#endif
- Xil_L1DCacheInvalidate();
-
- mtcpsr(currmask);
-}
-
-/*****************************************************************************/
-/**
-* @brief Invalidate a Data cache line. If the byte specified by the address
-* (adr) is cached by the Data cache, the cacheline containing that
-* byte is invalidated. If the cacheline is modified (dirty), the
-* modified contents are lost and are NOT written to the system memory
-* before the line is invalidated.
-*
-* @param adr: 32bit address of the data to be flushed.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_DCacheInvalidateLine(u32 adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-#ifndef USE_AMP
- Xil_L2CacheInvalidateLine(adr);
-#endif
- Xil_L1DCacheInvalidateLine(adr);
-
- mtcpsr(currmask);
-}
-
-
-/*****************************************************************************/
-/**
-* Invalidate the Data cache for the given address range.
-* If the bytes specified by the address range are cached by the Data
-* cache, the cachelines containing those bytes are invalidated. If
-* the cachelines are modified (dirty), the modified contents are lost
-* and NOT written to the system memory before the lines are
-* invalidated.
-*
-* In this function, if start address or end address is not aligned to
-* cache-line, particular cache-line containing unaligned start or end
-* address is flush first and then invalidated the others as
-* invalidating the same unaligned cache line may result into loss of
-* data. This issue raises few possibilities.
-*
-* If the address to be invalidated is not cache-line aligned, the
-* following choices are available:
-* 1. Invalidate the cache line when required and do not bother much
-* for the side effects. Though it sounds good, it can result in
-* hard-to-debug issues. The problem is, if some other variable are
-* allocated in the same cache line and had been recently updated
-* (in cache), the invalidation would result in loss of data.
-* 2. Flush the cache line first. This will ensure that if any other
-* variable present in the same cache line and updated recently are
-* flushed out to memory. Then it can safely be invalidated. Again it
-* sounds good, but this can result in issues. For example, when the
-* invalidation happens in a typical ISR (after a DMA transfer has
-* updated the memory), then flushing the cache line means, losing
-* data that were updated recently before the ISR got invoked.
-*
-* Linux prefers the second one. To have uniform implementation
-* (across standalone and Linux), the second option is implemented.
-* This being the case, following needs to be taken care of:
-* 1. Whenever possible, the addresses must be cache line aligned.
-* Please nore that, not just start address, even the end address must
-* be cache line aligned. If that is taken care of, this will always
-* work.
-* 2. Avoid situations where invalidation has to be done after the
-* data is updated by peripheral/DMA directly into the memory. It is
-* not tough to achieve (may be a bit risky). The common use case to
-* do invalidation is when a DMA happens. Generally for such use
-* cases, buffers can be allocated first and then start the DMA. The
-* practice that needs to be followed here is, immediately after
-* buffer allocation and before starting the DMA, do the invalidation.
-* With this approach, invalidation need not to be done after the DMA
-* transfer is over.
-*
-* This is going to always work if done carefully.
-* However, the concern is, there is no guarantee that invalidate has
-* not needed to be done after DMA is complete. For example, because
-* of some reasons if the first cache line or last cache line
-* (assuming the buffer in question comprises of multiple cache lines)
-* are brought into cache (between the time it is invalidated and DMA
-* completes) because of some speculative prefetching or reading data
-* for a variable present in the same cache line, then we will have to
-* invalidate the cache after DMA is complete.
-*
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
-{
- const u32 cacheline = 32U;
- u32 end;
- u32 tempadr = adr;
- u32 tempend;
- u32 currmask;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INVLD_PA_OFFSET);
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- end = tempadr + len;
- tempend = end;
- /* Select L1 Data cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
-
- if ((tempadr & (cacheline-1U)) != 0U) {
- tempadr &= (~(cacheline - 1U));
-
- Xil_L1DCacheFlushLine(tempadr);
-#ifndef USE_AMP
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
- Xil_L2CacheFlushLine(tempadr);
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- Xil_L2CacheSync();
-#endif
- tempadr += cacheline;
- }
- if ((tempend & (cacheline-1U)) != 0U) {
- tempend &= (~(cacheline - 1U));
-
- Xil_L1DCacheFlushLine(tempend);
-#ifndef USE_AMP
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
- Xil_L2CacheFlushLine(tempend);
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- Xil_L2CacheSync();
-#endif
- }
-
- while (tempadr < tempend) {
-#ifndef USE_AMP
- /* Invalidate L2 cache line */
- *L2CCOffset = tempadr;
- Xil_L2CacheSync();
-#endif
-
- /* Invalidate L1 Data cache line */
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_dc_line_mva_poc(tempadr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
- Reg = tempadr; }
-#endif
- tempadr += cacheline;
- }
- }
-
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the entire Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheFlush(void)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- Xil_L1DCacheFlush();
-#ifndef USE_AMP
- Xil_L2CacheFlush();
-#endif
- mtcpsr(currmask);
-}
-
-
-/****************************************************************************/
-/**
-* @brief Flush a Data cache line. If the byte specified by the address (adr)
-* is cached by the Data cache, the cacheline containing that byte is
-* invalidated. If the cacheline is modified (dirty), the entire
-* contents of the cacheline are written to system memory before the
-* line is invalidated.
-*
-* @param adr: 32bit address of the data to be flushed.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_DCacheFlushLine(u32 adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- Xil_L1DCacheFlushLine(adr);
-#ifndef USE_AMP
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
-
- Xil_L2CacheFlushLine(adr);
-
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- Xil_L2CacheSync();
-#endif
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the Data cache for the given address range.
-* If the bytes specified by the address range are cached by the
-* data cache, the cachelines containing those bytes are invalidated.
-* If the cachelines are modified (dirty), they are written to the
-* system memory before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be flushed.
-* @param len: Length of the range to be flushed in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheFlushRange(INTPTR adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- u32 currmask;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr &= ~(cacheline - 1U);
-#ifndef USE_AMP
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
-#endif
- while (LocalAddr < end) {
-
- /* Flush L1 Data cache line */
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
- Reg = LocalAddr; }
-#endif
-#ifndef USE_AMP
- /* Flush L2 cache line */
- *L2CCOffset = LocalAddr;
- Xil_L2CacheSync();
-#endif
- LocalAddr += cacheline;
- }
-#ifndef USE_AMP
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
-#endif
- }
- dsb();
- mtcpsr(currmask);
-}
-/****************************************************************************/
-/**
-* @brief Store a Data cache line. If the byte specified by the address (adr)
-* is cached by the Data cache and the cacheline is modified (dirty),
-* the entire contents of the cacheline are written to system memory.
-* After the store completes, the cacheline is marked as unmodified
-* (not dirty).
-*
-* @param adr: 32bit address of the data to be stored.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_DCacheStoreLine(u32 adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- Xil_L1DCacheStoreLine(adr);
-#ifndef USE_AMP
- Xil_L2CacheStoreLine(adr);
-#endif
- mtcpsr(currmask);
-}
-
-/***************************************************************************/
-/**
-* @brief Enable the instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ICacheEnable(void)
-{
- Xil_L1ICacheEnable();
-#ifndef USE_AMP
- Xil_L2CacheEnable();
-#endif
-}
-
-/***************************************************************************/
-/**
-* @brief Disable the instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ICacheDisable(void)
-{
-#ifndef USE_AMP
- Xil_L2CacheDisable();
-#endif
- Xil_L1ICacheDisable();
-}
-
-
-/****************************************************************************/
-/**
-* @brief Invalidate the entire instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ICacheInvalidate(void)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-#ifndef USE_AMP
- Xil_L2CacheInvalidate();
-#endif
- Xil_L1ICacheInvalidate();
-
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate an instruction cache line. If the instruction specified
-* by the address is cached by the instruction cache, the cacheline
-* containing that instruction is invalidated.
-*
-* @param adr: 32bit address of the instruction to be invalidated.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_ICacheInvalidateLine(u32 adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-#ifndef USE_AMP
- Xil_L2CacheInvalidateLine(adr);
-#endif
- Xil_L1ICacheInvalidateLine(adr);
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the instruction cache for the given address range.
-* If the instructions specified by the address range are cached by
-* the instrunction cache, the cachelines containing those
-* instructions are invalidated.
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INVLD_PA_OFFSET);
-
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Select cache L0 I-cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
-
- while (LocalAddr < end) {
-#ifndef USE_AMP
- /* Invalidate L2 cache line */
- *L2CCOffset = LocalAddr;
- dsb();
-#endif
-
- /* Invalidate L1 I-cache line */
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_ic_line_mva_pou(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
- Reg = LocalAddr; }
-#endif
-
- LocalAddr += cacheline;
- }
- }
-
- /* Wait for L1 and L2 invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Enable the level 1 Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1DCacheEnable(void)
-{
- register u32 CtrlReg;
-
- /* enable caches only if they are disabled */
-#ifdef __GNUC__
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
- CtrlReg = Reg; }
-#endif
- if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) {
- return;
- }
-
- /* clean and invalidate the Data cache */
- Xil_L1DCacheInvalidate();
-
- /* enable the Data cache */
- CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/***************************************************************************/
-/**
-* @brief Disable the level 1 Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1DCacheDisable(void)
-{
- register u32 CtrlReg;
-
- /* clean and invalidate the Data cache */
- Xil_L1DCacheFlush();
-
-#ifdef __GNUC__
- /* disable the Data cache */
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
- CtrlReg = Reg; }
-#endif
-
- CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the level 1 Data cache.
-*
-* @return None.
-*
-* @note In Cortex A9, there is no cp instruction for invalidating
-* the whole D-cache. This function invalidates each line by
-* set/way.
-*
-****************************************************************************/
-void Xil_L1DCacheInvalidate(void)
-{
- register u32 CsidReg, C7Reg;
- u32 CacheSize, LineSize, NumWays;
- u32 Way, WayIndex, Set, SetIndex, NumSet;
- u32 currmask;
-
-#ifdef __GNUC__
- u32 stack_start,stack_end,stack_size;
- register u32 CtrlReg;
-#endif
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
-#ifdef __GNUC__
- stack_end = (u32)&_stack_end;
- stack_start = (u32)&__undef_stack;
- stack_size=stack_start-stack_end;
-
- /* Check for the cache status. If cache is enabled, then only
- * flush stack memory to save return address. If cache is disabled,
- * don't flush anything as it might result in flushing stale date into
- * memory which is undesirable.
- * */
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) {
- Xil_DCacheFlushRange(stack_end, stack_size);
- }
-#endif
-
- /* Select cache level 0 and D cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
-
-#ifdef __GNUC__
- CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID);
- CsidReg = Reg; }
-#endif
- /* Determine Cache Size */
- CacheSize = (CsidReg >> 13U) & 0x1FFU;
- CacheSize +=1U;
- CacheSize *=128U; /* to get number of bytes */
-
- /* Number of Ways */
- NumWays = (CsidReg & 0x3ffU) >> 3U;
- NumWays += 1U;
-
- /* Get the cacheline size, way size, index size from csidr */
- LineSize = (CsidReg & 0x07U) + 4U;
-
- NumSet = CacheSize/NumWays;
- NumSet /= (0x00000001U << LineSize);
-
- Way = 0U;
- Set = 0U;
-
- /* Invalidate all the cachelines */
- for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set;
-
- /* Invalidate by Set/Way */
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_dc_line_sw(C7Reg);
-#else
- /*mtcp(XREG_CP15_INVAL_DC_LINE_SW, C7Reg), */
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_DC_LINE_SW);
- Reg = C7Reg; }
-#endif
- Set += (0x00000001U << LineSize);
- }
- Set=0U;
- Way += 0x40000000U;
- }
-
- /* Wait for L1 invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate a level 1 Data cache line. If the byte specified by the
-* address (Addr) is cached by the Data cache, the cacheline
-* containing that byte is invalidated. If the cacheline is modified
-* (dirty), the modified contents are lost and are NOT written to
-* system memory before the line is invalidated.
-*
-* @param adr: 32bit address of the data to be invalidated.
-*
-* @return None.
-*
-* @note The bottom 5 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L1DCacheInvalidateLine(u32 adr)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
- mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU)));
-
- /* Wait for L1 invalidate to complete */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the level 1 Data cache for the given address range.
-* If the bytes specified by the address range are cached by the Data
-* cache, the cachelines containing those bytes are invalidated. If the
-* cachelines are modified (dirty), the modified contents are lost and
-* NOT written to the system memory before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1DCacheInvalidateRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Select cache L0 D-cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
-
- while (LocalAddr < end) {
-
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_dc_line_mva_poc(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
- Reg = LocalAddr; }
-#endif
- LocalAddr += cacheline;
- }
- }
-
- /* Wait for L1 invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the level 1 Data cache.
-*
-* @return None.
-*
-* @note In Cortex A9, there is no cp instruction for flushing
-* the whole D-cache. Need to flush each line.
-*
-****************************************************************************/
-void Xil_L1DCacheFlush(void)
-{
- register u32 CsidReg, C7Reg;
- u32 CacheSize, LineSize, NumWays;
- u32 Way;
- u32 WayIndex, Set, SetIndex, NumSet;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- /* Select cache level 0 and D cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
-
-#ifdef __GNUC__
- CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID);
- CsidReg = Reg; }
-#endif
-
- /* Determine Cache Size */
-
- CacheSize = (CsidReg >> 13U) & 0x1FFU;
- CacheSize +=1U;
- CacheSize *=128U; /* to get number of bytes */
-
- /* Number of Ways */
- NumWays = (CsidReg & 0x3ffU) >> 3U;
- NumWays += 1U;
-
- /* Get the cacheline size, way size, index size from csidr */
- LineSize = (CsidReg & 0x07U) + 4U;
-
- NumSet = CacheSize/NumWays;
- NumSet /= (0x00000001U << LineSize);
-
- Way = 0U;
- Set = 0U;
-
- /* Invalidate all the cachelines */
- for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set;
- /* Flush by Set/Way */
-
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_clean_inval_dc_line_sw(C7Reg);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_SW);
- Reg = C7Reg; }
-#endif
- Set += (0x00000001U << LineSize);
- }
- Set = 0U;
- Way += 0x40000000U;
- }
-
- /* Wait for L1 flush to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush a level 1 Data cache line. If the byte specified by the
-* address (adr) is cached by the Data cache, the cacheline containing
-* that byte is invalidated. If the cacheline is modified (dirty), the
-* entire contents of the cacheline are written to system memory
-* before the line is invalidated.
-*
-* @param adr: 32bit address of the data to be flushed.
-*
-* @return None.
-*
-* @note The bottom 5 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L1DCacheFlushLine(u32 adr)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
- mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU)));
-
- /* Wait for L1 flush to complete */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the level 1 Data cache for the given address range.
-* If the bytes specified by the address range are cached by the Data
-* cache, the cacheline containing those bytes are invalidated. If the
-* cachelines are modified (dirty), they are written to system memory
-* before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be flushed.
-* @param len: Length of the range to be flushed in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1DCacheFlushRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Select cache L0 D-cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
-
- while (LocalAddr < end) {
-
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
- Reg = LocalAddr; }
-#endif
- LocalAddr += cacheline;
- }
- }
-
- /* Wait for L1 flush to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Store a level 1 Data cache line. If the byte specified by the
-* address (adr) is cached by the Data cache and the cacheline is
-* modified (dirty), the entire contents of the cacheline are written
-* to system memory. After the store completes, the cacheline is
-* marked as unmodified (not dirty).
-*
-* @param adr: Address to be stored.
-*
-* @return None.
-*
-* @note The bottom 5 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L1DCacheStoreLine(u32 adr)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
- mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1FU)));
-
- /* Wait for L1 store to complete */
- dsb();
-}
-
-
-/****************************************************************************/
-/**
-* @brief Enable the level 1 instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1ICacheEnable(void)
-{
- register u32 CtrlReg;
-
- /* enable caches only if they are disabled */
-#ifdef __GNUC__
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
- CtrlReg = Reg; }
-#endif
- if ((CtrlReg & (XREG_CP15_CONTROL_I_BIT)) != 0U) {
- return;
- }
-
- /* invalidate the instruction cache */
- mtcp(XREG_CP15_INVAL_IC_POU, 0U);
-
- /* enable the instruction cache */
- CtrlReg |= (XREG_CP15_CONTROL_I_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/****************************************************************************/
-/**
-* @brief Disable level 1 the instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1ICacheDisable(void)
-{
- register u32 CtrlReg;
-
- dsb();
-
- /* invalidate the instruction cache */
- mtcp(XREG_CP15_INVAL_IC_POU, 0U);
-
- /* disable the instruction cache */
-#ifdef __GNUC__
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
- CtrlReg = Reg; }
-#endif
- CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the entire level 1 instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1ICacheInvalidate(void)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
- /* invalidate the instruction cache */
- mtcp(XREG_CP15_INVAL_IC_POU, 0U);
-
- /* Wait for L1 invalidate to complete */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate a level 1 instruction cache line. If the instruction
-* specified by the address is cached by the instruction cache, the
-* cacheline containing that instruction is invalidated.
-*
-* @param adr: 32bit address of the instruction to be invalidated.
-*
-* @return None.
-*
-* @note The bottom 5 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L1ICacheInvalidateLine(u32 adr)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
- mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1FU)));
-
- /* Wait for L1 invalidate to complete */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the level 1 instruction cache for the given address
-* range. If the instrucions specified by the address range are cached
-* by the instruction cache, the cacheline containing those bytes are
-* invalidated.
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1ICacheInvalidateRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Select cache L0 I-cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
-
- while (LocalAddr < end) {
-
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_ic_line_mva_pou(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
- Reg = LocalAddr; }
-#endif
- LocalAddr += cacheline;
- }
- }
-
- /* Wait for L1 invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-#ifndef USE_AMP
-/****************************************************************************/
-/**
-* @brief Enable the L2 cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L2CacheEnable(void)
-{
- register u32 L2CCReg;
-
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
-
- /* only enable if L2CC is currently disabled */
- if ((L2CCReg & 0x01U) == 0U) {
- /* set up the way size and latencies */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
- XPS_L2CC_AUX_CNTRL_OFFSET);
- L2CCReg &= XPS_L2CC_AUX_REG_ZERO_MASK;
- L2CCReg |= XPS_L2CC_AUX_REG_DEFAULT_MASK;
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_AUX_CNTRL_OFFSET,
- L2CCReg);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_TAG_RAM_CNTRL_OFFSET,
- XPS_L2CC_TAG_RAM_DEFAULT_MASK);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DATA_RAM_CNTRL_OFFSET,
- XPS_L2CC_DATA_RAM_DEFAULT_MASK);
-
- /* Clear the pending interrupts */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
- XPS_L2CC_ISR_OFFSET);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_IAR_OFFSET, L2CCReg);
-
- Xil_L2CacheInvalidate();
- /* Enable the L2CC */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
- XPS_L2CC_CNTRL_OFFSET);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
- (L2CCReg | (0x01U)));
-
- Xil_L2CacheSync();
- /* synchronize the processor */
- dsb();
-
- }
-}
-
-/****************************************************************************/
-/**
-* @brief Disable the L2 cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L2CacheDisable(void)
-{
- register u32 L2CCReg;
-
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
-
- if((L2CCReg & 0x1U) != 0U) {
-
- /* Clean and Invalidate L2 Cache */
- Xil_L2CacheFlush();
-
- /* Disable the L2CC */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
- (L2CCReg & (~0x01U)));
- /* Wait for the cache operations to complete */
-
- dsb();
- }
-}
-
-/*****************************************************************************/
-/**
-* @brief Invalidate the entire level 2 cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L2CacheInvalidate(void)
-{
- #ifdef __GNUC__
- u32 stack_start,stack_end,stack_size;
- register u32 L2CCReg;
- stack_end = (u32)&_stack_end;
- stack_start = (u32)&__undef_stack;
- stack_size=stack_start-stack_end;
-
- /* Check for the cache status. If cache is enabled, then only
- * flush stack memory to save return address. If cache is disabled,
- * don't flush anything as it might result in flushing stale date into
- * memory which is undesirable.
- */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
- if ((L2CCReg & 0x01U) != 0U) {
- /*Flush stack memory to save return address*/
- Xil_DCacheFlushRange(stack_end, stack_size);
- }
-
- #endif
- u32 ResultDCache;
- /* Invalidate the caches */
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET,
- 0x0000FFFFU);
- ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)
- & 0x0000FFFFU;
- while(ResultDCache != (u32)0U) {
- ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)
- & 0x0000FFFFU;
- }
-
- /* Wait for the invalidate to complete */
- Xil_L2CacheSync();
-
- /* synchronize the processor */
- dsb();
-}
-
-/*****************************************************************************/
-/**
-* @brief Invalidate a level 2 cache line. If the byte specified by the
-* address (adr) is cached by the Data cache, the cacheline containing
-* that byte is invalidated. If the cacheline is modified (dirty),
-* the modified contents are lost and are NOT written to system memory
-* before the line is invalidated.
-*
-* @param adr: 32bit address of the data/instruction to be invalidated.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L2CacheInvalidateLine(u32 adr)
-{
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, (u32)adr);
- /* synchronize the processor */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the level 2 cache for the given address range.
-* If the bytes specified by the address range are cached by the L2
-* cache, the cacheline containing those bytes are invalidated. If the
-* cachelines are modified (dirty), the modified contents are lost and
-* are NOT written to system memory before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L2CacheInvalidateRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INVLD_PA_OFFSET);
-
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
-
- while (LocalAddr < end) {
- *L2CCOffset = LocalAddr;
- Xil_L2CacheSync();
- LocalAddr += cacheline;
- }
-
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- }
-
- /* synchronize the processor */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the entire level 2 cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L2CacheFlush(void)
-{
- u32 ResultL2Cache;
-
- /* Flush the caches */
-
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
-
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET,
- 0x0000FFFFU);
- ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
- & 0x0000FFFFU;
-
- while(ResultL2Cache != (u32)0U) {
- ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
- & 0x0000FFFFU;
- }
-
- Xil_L2CacheSync();
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
-
- /* synchronize the processor */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Flush a level 2 cache line. If the byte specified by the address
-* (adr) is cached by the L2 cache, the cacheline containing that
-* byte is invalidated. If the cacheline is modified (dirty), the
-* entire contents of the cacheline are written to system memory
-* before the line is invalidated.
-*
-* @param adr: 32bit address of the data/instruction to be flushed.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L2CacheFlushLine(u32 adr)
-{
-#ifdef CONFIG_PL310_ERRATA_588369
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, adr);
-#else
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET, adr);
-#endif
- /* synchronize the processor */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the level 2 cache for the given address range.
-* If the bytes specified by the address range are cached by the L2
-* cache, the cacheline containing those bytes are invalidated. If the
-* cachelines are modified (dirty), they are written to the system
-* memory before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be flushed.
-* @param len: Length of the range to be flushed in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L2CacheFlushRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
-
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
-
- while (LocalAddr < end) {
- *L2CCOffset = LocalAddr;
- Xil_L2CacheSync();
- LocalAddr += cacheline;
- }
-
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- }
- /* synchronize the processor */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Store a level 2 cache line. If the byte specified by the address
-* (adr) is cached by the L2 cache and the cacheline is modified
-* (dirty), the entire contents of the cacheline are written to
-* system memory. After the store completes, the cacheline is marked
-* as unmodified (not dirty).
-*
-* @param adr: 32bit address of the data/instruction to be stored.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L2CacheStoreLine(u32 adr)
-{
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
- /* synchronize the processor */
- dsb();
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/13/3088f5545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/13/3088f5545243001d18b399c1eb9b3628
deleted file mode 100644
index 154f808..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/13/3088f5545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1564 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xsdps_card.c
-* @addtogroup sdps_v3_13
-* @{
-*
-* Contains the interface functions of the XSdPs driver.
-* See xsdps.h for a detailed description of the device and driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 3.9 mn 03/03/20 Restructured the code for more readability and modularity
-* mn 03/16/20 Move XSdPs_Select_Card API to User APIs
-* 3.10 mn 06/05/20 Check Transfer completion separately from XSdPs_Read and
-* XSdPs_Write APIs
-* mn 10/15/20 Modify power cycle API to poll for SD bus lines to go
-* low for versal platform
-* 3.12 sk 01/28/21 Added support for non-blocking write.
-* sk 02/12/21 Fix the issue in reading CID and CSD.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xsdps_core.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-* @brief
-* This function performs SD read in polled mode.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Arg is the address passed by the user that is to be sent as
-* argument along with the command.
-* @param BlkCnt - Block count passed by the user.
-* @param Buff - Pointer to the data buffer for a DMA transfer.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because another transfer
-* is in progress or command or data inhibit is set
-*
-******************************************************************************/
-s32 XSdPs_Read(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
-{
- s32 Status;
-
- XSdPs_SetupReadDma(InstancePtr, BlkCnt, InstancePtr->BlkSize, Buff);
-
- if (BlkCnt == 1U) {
- /* Send single block read command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD17, Arg, BlkCnt);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
- } else {
- /* Send multiple blocks read command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
- }
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function performs SD write in polled mode.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Arg is the address passed by the user that is to be sent as
-* argument along with the command.
-* @param BlkCnt - Block count passed by the user.
-* @param Buff - Pointer to the data buffer for a DMA transfer.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because another transfer
-* is in progress or command or data inhibit is set
-*
-******************************************************************************/
-s32 XSdPs_Write(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
-{
- s32 Status;
-
- XSdPs_SetupWriteDma(InstancePtr, BlkCnt, InstancePtr->BlkSize, Buff);
-
- if (BlkCnt == 1U) {
- /* Send single block write command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD24, Arg, BlkCnt);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
- } else {
- /* Send multiple blocks write command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
- }
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to check for the transfer complete.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if transfer was successful
-* - XST_FAILURE if failure
-* - XST_DEVICE_BUSY - if the transfer is still in progress
-*
-******************************************************************************/
-s32 XSdPs_CheckTransferComplete(XSdPs *InstancePtr)
-{
- u16 StatusReg;
- s32 Status;
-
- if (InstancePtr->IsBusy == FALSE) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /*
- * Check for transfer complete
- */
- StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET);
- if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
- /* Write to clear error bits */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET,
- XSDPS_ERROR_INTR_ALL_MASK);
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if ((StatusReg & XSDPS_INTR_TC_MASK) == 0U) {
- Status = XST_DEVICE_BUSY;
- goto RETURN_PATH;
- }
-
- /* Write to clear bit */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
-
- InstancePtr->IsBusy = FALSE;
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* Identify type of card using CMD0 + CMD1 sequence
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-******************************************************************************/
-s32 XSdPs_IdentifyCard(XSdPs *InstancePtr)
-{
- s32 Status;
-
- if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
- ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
- == XSDPS_CAPS_EMB_SLOT)) {
- InstancePtr->CardType = XSDPS_CHIP_EMMC;
- Status = XST_SUCCESS;
- goto RETURN_PATH;
- }
-
- /* 74 CLK delay after card is powered up, before the first command. */
- usleep(XSDPS_INIT_DELAY);
-
- /* CMD0 no response expected */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Host High Capacity support & High voltage window */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
- XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
- if (Status != XST_SUCCESS) {
- InstancePtr->CardType = XSDPS_CARD_SD;
- } else {
- InstancePtr->CardType = XSDPS_CARD_MMC;
- }
-
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
-
- Status = XSdPs_Reset(InstancePtr, XSDPS_SWRST_CMD_LINE_MASK);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* SD initialization is done in this function
-*
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because
-* a) SD is already initialized
-* b) There is no card inserted
-* c) One of the steps (commands) in the
- initialization cycle failed
-*
-* @note This function initializes the SD card by following its
-* initialization and identification state diagram.
-* CMD0 is sent to reset card.
-* CMD8 and ACDM41 are sent to identify voltage and
-* high capacity support
-* CMD2 and CMD3 are sent to obtain Card ID and
-* Relative card address respectively.
-* CMD9 is sent to read the card specific data.
-*
-******************************************************************************/
-s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr)
-{
- s32 Status;
-
-#ifndef UHS_MODE_ENABLE
- InstancePtr->Config.BusWidth = XSDPS_WIDTH_4;
-#endif
-
- Status = XSdPs_SdCardEnum(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XSdPs_SdModeInit(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* Mmc initialization is done in this function
-*
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because
-* a) MMC is already initialized
-* b) There is no card inserted
-* c) One of the steps (commands) in the initialization
-* cycle failed
-* @note This function initializes the SD card by following its
-* initialization and identification state diagram.
-* CMD0 is sent to reset card.
-* CMD1 sent to identify voltage and high capacity support
-* CMD2 and CMD3 are sent to obtain Card ID and
-* Relative card address respectively.
-* CMD9 is sent to read the card specific data.
-*
-******************************************************************************/
-s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr)
-{
- s32 Status;
-
- Status = XSdPs_MmcCardEnum(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if (((InstancePtr->CardType == XSDPS_CARD_MMC) &&
- (InstancePtr->Card_Version > CSD_SPEC_VER_3)) &&
- (InstancePtr->HC_Version == XSDPS_HC_SPEC_V2)) {
- Status = XSdPs_MmcModeInit(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } else if (InstancePtr->CardType == XSDPS_CHIP_EMMC) {
- Status = XSdPs_EmmcModeInit(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } else {
- Status = XST_FAILURE;
- goto RETURN_PATH;
-
- }
-
- if (InstancePtr->Mode != XSDPS_DDR52_MODE) {
- Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } else {
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_SIZE_OFFSET, XSDPS_BLK_SIZE_512_MASK);
- InstancePtr->BlkSize = XSDPS_BLK_SIZE_512_MASK;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function checks if the card is present or not.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_CheckCardDetect(XSdPs *InstancePtr)
-{
- u32 PresentStateReg;
- s32 Status;
-
- if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
- ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
- == XSDPS_CAPS_EMB_SLOT)) {
- Status = XST_SUCCESS;
- goto RETURN_PATH;
- }
-
- if(InstancePtr->Config.CardDetect != 0U) {
- /*
- * Check the present state register to make sure
- * card is inserted and detected by host controller
- */
- PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function sends CMD0 to reset the card.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_CardReset(XSdPs *InstancePtr)
-{
- s32 Status;
-
- /* CMD0 no response expected */
- Status = XSdPs_CmdTransfer(InstancePtr, (u32)CMD0, 0U, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function sends command to get the card interface details.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_CardIfCond(XSdPs *InstancePtr)
-{
- u32 RespOCR;
- s32 Status;
-
- /*
- * CMD8; response expected
- * 0x1AA - Supply Voltage 2.7 - 3.6V and AA is pattern
- */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD8,
- XSDPS_CMD8_VOL_PATTERN, 0U);
- if ((Status != XST_SUCCESS) && (Status != XSDPS_CT_ERROR)) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if (Status == XSDPS_CT_ERROR) {
- Status = XSdPs_Reset(InstancePtr, XSDPS_SWRST_CMD_LINE_MASK);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
- }
-
- RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET);
- if (RespOCR != XSDPS_CMD8_VOL_PATTERN) {
- InstancePtr->Card_Version = XSDPS_SD_VER_1_0;
- } else {
- InstancePtr->Card_Version = XSDPS_SD_VER_2_0;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function sends command to get the card operating condition.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_CardOpCond(XSdPs *InstancePtr)
-{
- u32 RespOCR;
- s32 Status;
- u32 Arg;
-
- /* Send ACMD41 while card is still busy with power up */
- do {
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
- Status = XSdPs_CmdTransfer(InstancePtr, CMD55, 0U, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U);
- if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
- (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) {
- Arg |= XSDPS_OCR_S18;
- }
-
- /* 0x40300000 - Host High Capacity support & 3.3V window */
- Status = XSdPs_CmdTransfer(InstancePtr, ACMD41,
- Arg, 0U);
- } else {
- /* Send CMD1 while card is still busy with power up */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
- XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
- }
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Response with card capacity */
- RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET);
- } while ((RespOCR & XSDPS_RESPOCR_READY) == 0U);
-
- /* Update HCS support flag based on card capacity response */
- if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) {
- InstancePtr->HCS = 1U;
- }
-
- if ((RespOCR & XSDPS_OCR_S18) != 0U) {
- InstancePtr->Switch1v8 = 1U;
- Status = XSdPs_Switch_Voltage(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to get the card ID.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_GetCardId(XSdPs *InstancePtr)
-{
- s32 Status;
-
- /* CMD2 for Card ID */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- InstancePtr->CardID[0] =
- XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET);
- InstancePtr->CardID[1] =
- XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP1_OFFSET);
- InstancePtr->CardID[2] =
- XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP2_OFFSET);
- InstancePtr->CardID[3] =
- XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP3_OFFSET);
-
- if(InstancePtr->CardType == XSDPS_CARD_SD) {
- do {
- Status = XSdPs_CmdTransfer(InstancePtr, CMD3, 0U, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /*
- * Relative card address is stored as the upper 16 bits
- * This is to avoid shifting when sending commands
- */
- InstancePtr->RelCardAddr =
- XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET) & 0xFFFF0000U;
- } while (InstancePtr->RelCardAddr == 0U);
- } else {
- /* Set relative card address */
- InstancePtr->RelCardAddr = 0x12340000U;
- Status = XSdPs_CmdTransfer(InstancePtr, CMD3, (InstancePtr->RelCardAddr), 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to get the CSD register from the card.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_GetCsd(XSdPs *InstancePtr)
-{
- s32 Status;
- u32 CSD[4];
- u32 BlkLen;
- u32 DeviceSize;
- u32 Mult;
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /*
- * Card specific data is read.
- * Currently not used for any operation.
- */
- CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET);
- CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP1_OFFSET);
- CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP2_OFFSET);
- CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP3_OFFSET);
-
- InstancePtr->CardSpecData[0] = CSD[0];
- InstancePtr->CardSpecData[1] = CSD[1];
- InstancePtr->CardSpecData[2] = CSD[2];
- InstancePtr->CardSpecData[3] = CSD[3];
-
- if (InstancePtr->CardType != XSDPS_CARD_SD) {
- InstancePtr->Card_Version = (u8)((u32)(CSD[3] & CSD_SPEC_VER_MASK) >>18U);
- Status = XST_SUCCESS;
- goto RETURN_PATH;
- }
-
- if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 0U) {
- BlkLen = 1U << ((u32)(CSD[2] & READ_BLK_LEN_MASK) >> 8U);
- Mult = 1U << ((u32)((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U);
- DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U;
- DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U;
- DeviceSize = (DeviceSize + 1U) * Mult;
- DeviceSize = DeviceSize * BlkLen;
- InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK);
- } else if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 1U) {
- InstancePtr->SectorCount = (((CSD[1] & CSD_V2_C_SIZE_MASK) >> 8U) +
- 1U) * 1024U;
- } else {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to set the card voltage to 1.8V.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_CardSetVoltage18(XSdPs *InstancePtr)
-{
- s32 Status;
- u16 CtrlReg;
- u16 ClockReg;
-
- /* Stop the clock */
- CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
- CtrlReg);
-
- /* Check for 1.8V signal enable bit is cleared by Host */
- Status = XSdPs_SetVoltage18(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- /* Enable the clock in the controller */
- Status = XSdPs_EnableClock(InstancePtr, ClockReg);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- /* Wait for 1mSec */
- (void)usleep(1000U);
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to do initial Reset Configuration.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_ResetConfig(XSdPs *InstancePtr)
-{
- s32 Status;
-
- XSdPs_DisableBusPower(InstancePtr);
-
-#ifdef versal
- if ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
- != XSDPS_CAPS_EMB_SLOT) {
- u32 Timeout = 200000U;
- u32 PresentStateReg;
-
- /* Check for SD Bus Lines low */
- do {
- PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- Timeout = Timeout - 1U;
- usleep(1);
- } while (((PresentStateReg & XSDPS_PSR_DAT30_SG_LVL_MASK) != 0U)
- && (Timeout != 0U));
- }
-#endif
-
- Status = XSdPs_Reset(InstancePtr, XSDPS_SWRST_ALL_MASK);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- XSdPs_EnableBusPower(InstancePtr);
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to do initial Host Configuration.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-void XSdPs_HostConfig(XSdPs *InstancePtr)
-{
- XSdPs_ConfigPower(InstancePtr);
-
- XSdPs_ConfigDma(InstancePtr);
-
- XSdPs_ConfigInterrupt(InstancePtr);
-
- /*
- * Transfer mode register - default value
- * DMA enabled, block count enabled, data direction card to host(read)
- */
- InstancePtr->TransferMode = XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK |
- XSDPS_TM_DAT_DIR_SEL_MASK;
-
- /* Set block size to 512 by default */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_SIZE_OFFSET, XSDPS_BLK_SIZE_512_MASK);
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function checks for Reset Done bits to be cleared after a reset assert.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Value is the bits to be checked to be cleared.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_CheckResetDone(XSdPs *InstancePtr, u8 Value)
-{
- u32 Timeout = 1000000U;
- u32 ReadReg;
- s32 Status;
-
- /* Proceed with initialization only after reset is complete */
- do {
- ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
- XSDPS_SW_RST_OFFSET);
- Timeout = Timeout - 1U;
- usleep(1);
- } while (((ReadReg & Value) != 0U)
- && (Timeout != 0U));
-
- if (Timeout == 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to setup the voltage switch.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_SetupVoltageSwitch(XSdPs *InstancePtr)
-{
- u32 Timeout = 10000;
- s32 Status;
- u32 ReadReg;
-
- /* Send switch voltage command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD11, 0U, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Wait for CMD and DATA line to go low */
- do {
- ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- Timeout = Timeout - 1;
- usleep(1);
- } while (((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK |
- XSDPS_PSR_DAT30_SG_LVL_MASK)) != 0U)
- && (Timeout != 0U));
-
- if (Timeout == 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to check if the Cmd and Dat buses are high.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_CheckBusHigh(XSdPs *InstancePtr)
-{
- u32 Timeout = 10000;
- s32 Status;
- u32 ReadReg;
-
- /* Wait for CMD and DATA line to go high */
- Timeout = MAX_TIMEOUT;
- do {
- ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- Timeout = Timeout - 1;
- usleep(1);
- } while (((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK))
- != (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK))
- && (Timeout != 0U));
-
- if (Timeout == 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to Identify the supported UHS mode. This API will assign the
-* corresponding tap delay API to the Config_TapDelay pointer based on the
-* supported bus speed.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param ReadBuff contains the response for CMD6
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff)
-{
- if (((ReadBuff[13] & UHS_SDR104_SUPPORT) != 0U) &&
- (InstancePtr->Config.InputClockHz >= XSDPS_SD_INPUT_MAX_CLK)) {
- InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR104;
- if (InstancePtr->Config.BankNumber == 2U) {
- InstancePtr->OTapDelay = SD_OTAPDLYSEL_HS200_B2;
- } else {
- InstancePtr->OTapDelay = SD_OTAPDLYSEL_HS200_B0;
- }
- } else if (((ReadBuff[13] & UHS_SDR50_SUPPORT) != 0U) &&
- (InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR50_MAX_CLK)) {
- InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR50;
- InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD50;
- } else if (((ReadBuff[13] & UHS_DDR50_SUPPORT) != 0U) &&
- (InstancePtr->Config.InputClockHz >= XSDPS_SD_DDR50_MAX_CLK)) {
- InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_DDR50;
- InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD_DDR50;
- InstancePtr->ITapDelay = SD_ITAPDLYSEL_SD_DDR50;
- } else if (((ReadBuff[13] & UHS_SDR25_SUPPORT) != 0U) &&
- (InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR25_MAX_CLK)) {
- InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR25;
- InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD_HSD;
- InstancePtr->ITapDelay = SD_ITAPDLYSEL_HSD;
- } else {
- InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR12;
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to set Tap Delay w.r.t speed modes
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-void XSdPs_SetTapDelay(XSdPs *InstancePtr)
-{
- if ((InstancePtr->Mode == XSDPS_DEFAULT_SPEED_MODE) ||
- (InstancePtr->Mode == XSDPS_UHS_SPEED_MODE_SDR12)) {
- return;
- }
-
-#ifndef versal
- /* Issue DLL Reset */
- XSdPs_DllRstCtrl(InstancePtr, 1U);
-#endif
-
- /* Configure the Tap Delay Registers */
- XSdPs_ConfigTapDelay(InstancePtr);
-
-#ifndef versal
- /* Release the DLL out of reset */
- XSdPs_DllRstCtrl(InstancePtr, 0U);
-#endif
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to change the SD Bus Speed.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_Change_SdBusSpeed(XSdPs *InstancePtr)
-{
- s32 Status;
- u32 Arg;
- u16 BlkCnt;
- u16 BlkSize;
- u16 CtrlReg;
- u8 ReadBuff[64] = {0U};
-
- Status = XSdPs_CalcBusSpeed(InstancePtr, &Arg);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
- BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
-
- XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, ReadBuff);
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, BlkCnt);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Check for transfer done */
- Status = XSdps_CheckTransferDone(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- if (InstancePtr->Switch1v8 != 0U) {
- /* Set UHS mode in controller */
- CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET);
- CtrlReg &= (u16)(~XSDPS_HC2_UHS_MODE_MASK);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET,
- CtrlReg | InstancePtr->Mode);
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to change the eMMC bus speed.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_Change_MmcBusSpeed(XSdPs *InstancePtr)
-{
- s32 Status;
- u32 Arg;
-
- Status = XSdPs_CalcBusSpeed(InstancePtr, &Arg);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Check for transfer done */
- Status = XSdps_CheckTransferDone(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to do the Auto tuning.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_AutoTuning(XSdPs *InstancePtr)
-{
- s32 Status;
- u16 BlkSize;
- u8 TuningCount;
-
- BlkSize = XSDPS_TUNING_CMD_BLKSIZE;
- if(InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH)
- {
- BlkSize = BlkSize*2U;
- }
- BlkSize &= XSDPS_BLK_SIZE_MASK;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
- BlkSize);
-
- InstancePtr->TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK;
-
- XSdPs_SetExecTuning(InstancePtr);
- /*
- * workaround which can work for 1.0/2.0 silicon for auto tuning.
- * This can be revisited for 3.0 silicon if necessary.
- */
- /* Wait for ~60 clock cycles to reset the tap values */
- (void)usleep(1U);
-
- for (TuningCount = 0U; TuningCount < MAX_TUNING_COUNT; TuningCount++) {
-
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
- Status = XSdPs_CmdTransfer(InstancePtr, CMD19, 0U, 1U);
- } else {
- Status = XSdPs_CmdTransfer(InstancePtr, CMD21, 0U, 1U);
- }
-
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_EXEC_TNG_MASK) == 0U) {
- break;
- }
- }
-
- if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_SAMP_CLK_SEL_MASK) == 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Wait for ~12 clock cycles to synchronize the new tap values */
- (void)usleep(1U);
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to setup ADMA2 descriptor table
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param BlkCnt - block count.
-* @param Buff pointer to data buffer.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
-{
- if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
- XSdPs_Setup64ADMA2DescTbl(InstancePtr, BlkCnt, Buff);
- } else {
- XSdPs_Setup32ADMA2DescTbl(InstancePtr, BlkCnt, Buff);
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to setup ADMA2 descriptor table for 64 Bit DMA
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param BlkCnt - block count.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-void XSdPs_SetupADMA2DescTbl64Bit(XSdPs *InstancePtr, u32 BlkCnt)
-{
-#ifdef __ICCARM__
-#pragma data_alignment = 32
- static XSdPs_Adma2Descriptor64 Adma2_DescrTbl[32];
-#else
- static XSdPs_Adma2Descriptor64 Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
-#endif
- u32 TotalDescLines;
- u64 DescNum;
- u32 BlkSize;
-
- /* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */
- BlkSize = (u32)XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_SIZE_OFFSET) &
- XSDPS_BLK_SIZE_MASK;
-
- if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) {
-
- TotalDescLines = 1U;
-
- } else {
-
- TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH);
- if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) {
- TotalDescLines += 1U;
- }
-
- }
-
- for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) {
- Adma2_DescrTbl[DescNum].Address =
- InstancePtr->Dma64BitAddr +
- (DescNum*XSDPS_DESC_MAX_LENGTH);
- Adma2_DescrTbl[DescNum].Attribute =
- XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
- Adma2_DescrTbl[DescNum].Length = 0U;
- }
-
- Adma2_DescrTbl[TotalDescLines-1].Address =
- InstancePtr->Dma64BitAddr +
- (DescNum*XSDPS_DESC_MAX_LENGTH);
-
- Adma2_DescrTbl[TotalDescLines-1].Attribute =
- XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
-
- Adma2_DescrTbl[TotalDescLines-1].Length =
- (u16)((BlkCnt*BlkSize) - (u32)(DescNum*XSDPS_DESC_MAX_LENGTH));
-
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
- (u32)((UINTPTR)&(Adma2_DescrTbl[0]) & (u32)~0x0));
-
- if (InstancePtr->Config.IsCacheCoherent == 0U) {
- Xil_DCacheFlushRange((INTPTR)&(Adma2_DescrTbl[0]),
- sizeof(XSdPs_Adma2Descriptor64) * 32U);
- }
-
- /* Clear the 64-Bit Address variable */
- InstancePtr->Dma64BitAddr = 0U;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to reset the DLL
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_DllReset(XSdPs *InstancePtr)
-{
- u32 ClockReg;
- s32 Status;
-
- /* Disable clock */
- ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- ClockReg &= ~XSDPS_CC_SD_CLK_EN_MASK;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET, (u16)ClockReg);
-
- /* Issue DLL Reset to load zero tap values */
- XSdPs_DllRstCtrl(InstancePtr, 1U);
-
- /* Wait for 2 micro seconds */
- (void)usleep(2U);
-
- XSdPs_DllRstCtrl(InstancePtr, 0U);
-
- ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- /* Enable the clock in the controller */
- Status = XSdPs_EnableClock(InstancePtr, ClockReg);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to identify the eMMC speed mode.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param ExtCsd is the extended CSD register from the card
-*
-* @return None
-*
-******************************************************************************/
-void XSdPs_IdentifyEmmcMode(XSdPs *InstancePtr, const u8 *ExtCsd)
-{
- if (InstancePtr->BusWidth < XSDPS_4_BIT_WIDTH) {
- InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
- } else {
- /* Check for card supported speed */
- if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
- (EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 |
- EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) {
- InstancePtr->Mode = XSDPS_HS200_MODE;
- if (InstancePtr->Config.BankNumber == 2U) {
- InstancePtr->OTapDelay = SD_OTAPDLYSEL_HS200_B2;
- } else {
- InstancePtr->OTapDelay = SD_OTAPDLYSEL_HS200_B0;
- }
- } else if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
- (EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED |
- EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED)) != 0U) {
- InstancePtr->Mode = XSDPS_DDR52_MODE;
- InstancePtr->OTapDelay = SD_OTAPDLYSEL_EMMC_DDR50;
- InstancePtr->ITapDelay = SD_ITAPDLYSEL_EMMC_DDR50;
- } else if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
- EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) {
- InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
- InstancePtr->OTapDelay = SD_OTAPDLYSEL_EMMC_HSD;
- InstancePtr->ITapDelay = SD_ITAPDLYSEL_HSD;
- } else {
- InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
- }
- }
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to check the eMMC timing.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param ExtCsd is the extended CSD register from the card
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_CheckEmmcTiming(XSdPs *InstancePtr, u8 *ExtCsd)
-{
- s32 Status;
-
- Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if (InstancePtr->Mode == XSDPS_HS200_MODE) {
- if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } else if ((InstancePtr->Mode == XSDPS_HIGH_SPEED_MODE) ||
- (InstancePtr->Mode == XSDPS_DDR52_MODE)) {
- if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } else {
- Status = XST_FAILURE;
- }
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to set the clock to the passed frequency.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param SelFreq is the selected frequency
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_SetClock(XSdPs *InstancePtr, u32 SelFreq)
-{
- u16 ClockReg;
- s32 Status;
-
- /* Disable clock */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET, 0U);
-
- /* If selected frequency is zero, return from here */
- if (SelFreq == 0U) {
- Status = XST_SUCCESS;
- goto RETURN_PATH ;
- }
-
- /* Calculate the clock */
- ClockReg = XSdPs_CalcClock(InstancePtr, SelFreq);
-
- /* Enable the clock in the controller */
- Status = XSdPs_EnableClock(InstancePtr, ClockReg);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function checks if the voltage is set to 1.8V or not.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if voltage is 1.8V
-* - XST_FAILURE if voltage is not 1.8V
-*
-******************************************************************************/
-s32 XSdPs_CheckVoltage18(XSdPs *InstancePtr)
-{
- u32 Status;
-
- if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_1V8_EN_MASK) == 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function initializes the command sequence.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Arg is the address passed by the user that is to be sent as
-* argument along with the command.
-* @param BlkCnt - Block count passed by the user.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_SetupCmd(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt)
-{
- s32 Status;
-
- /*
- * Check the command inhibit to make sure no other
- * command transfer is in progress
- */
- Status = XSdPs_CheckBusIdle(InstancePtr, XSDPS_PSR_INHIBIT_CMD_MASK);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- /* Write block count register */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_CNT_OFFSET, (u16)BlkCnt);
-
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_TIMEOUT_CTRL_OFFSET, 0xEU);
-
- /* Write argument register */
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress,
- XSDPS_ARGMT_OFFSET, Arg);
-
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function initiates the Cmd transfer to SD card.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Cmd is the command to be sent
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure
-*
-******************************************************************************/
-s32 XSdPs_SendCmd(XSdPs *InstancePtr, u32 Cmd)
-{
- u32 PresentStateReg;
- u32 CommandReg;
- s32 Status;
-
- /* Command register is set to trigger transfer of command */
- CommandReg = XSdPs_FrameCmd(InstancePtr, Cmd);
-
- /*
- * Mask to avoid writing to reserved bits 31-30
- * This is necessary because 0x8000 is used by this software to
- * distinguish between ACMD and CMD of same number
- */
- CommandReg = CommandReg & 0x3FFFU;
-
- /*
- * Check for data inhibit in case of command using DAT lines.
- * For Tuning Commands DAT lines check can be ignored.
- */
- if ((Cmd != CMD21) && (Cmd != CMD19)) {
- PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- if (((PresentStateReg & XSDPS_PSR_INHIBIT_DAT_MASK) != 0U) &&
- ((CommandReg & XSDPS_DAT_PRESENT_SEL_MASK) != 0U)) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET,
- (CommandReg << 16) | InstancePtr->TransferMode);
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-
-}
-
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/13/803474525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/13/803474525243001d18b399c1eb9b3628
deleted file mode 100644
index 39b5bda..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/13/803474525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,51 +0,0 @@
-########################################################################
-# This is file which used to generate QEMU(which emulates A9 core)
-# commandline(start_qemu.sh script) which used in Zynq HW-EMU.
-# This is a template file which is packaged in platform and it gets
-# processed by Vitis tool to generate meaningful file.
-#
-# This file contains flag and value pairs and they must be seperated
-# into two lines value followed by flag. Below are the common/mandated
-# flag and value pairs used for emulating Zynq. User can add more
-# commandline args to this file depends on requirements.
-#
-# For more details on the QEMU commandline, please refer to
-# the QEMU user guide UG1169.
-########################################################################
-#
-#
-# selects emulated machine
--M
-arm-generic-fdt-7series
-#
-#
-# redirect the serial port to specified char dev (i.e stdio, tcp port, file etc)
--serial
-/dev/null
--serial
-mon:stdio
-#
-#
-# Register writes to SLCR block, to set PLL and CLK_CTRL regs (required for linux)
--device
-loader,addr=0xf8000008,data=0xDF0D,data-len=4
--device
-loader,addr=0xf8000140,data=0x00500801,data-len=4
--device
-loader,addr=0xf800012c,data=0x1ed044d,data-len=4
--device
-loader,addr=0xf8000108,data=0x0001e008,data-len=4
--device
-loader,addr=0xF800025C,data=0x00000005,data-len=4
--device
-loader,addr=0xF8000240,data=0x00000000,data-len=4
-#
-#
-# Boot device selection
--boot
-mode=5
-#
-#
-# Guest software to load during boot up
--kernel
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/13/e02fe0585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/13/e02fe0585243001d18b399c1eb9b3628
deleted file mode 100644
index 9be0b25..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/13/e02fe0585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,176 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file asm_vectors.S
-*
-* This file contains the initial vector table for the Cortex A9 processor
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 1.00a ecm/sdm 10/20/09 Initial version
-* 3.05a sdm 02/02/12 Save lr when profiling is enabled
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-* 4.00a pkp 22/01/14 Modified return addresses for interrupt
-* handlers (DataAbortHandler and SVCHandler)
-* to fix CR#767251
-* 5.1 pkp 05/13/15 Saved the addresses of instruction causing data
-* abort and prefetch abort into DataAbortAddr and
-* PrefetchAbortAddr for further use to fix CR#854523
-* 5.4 pkp 12/03/15 Added handler for undefined exception
-* 6.8 mus 04/27/18 Removed __ARM_NEON__ flag definition. Now,
-* saving/restoring of of HW floating point register
-* would be done through newly introduced flag
-* FPU_HARD_FLOAT_ABI_ENABLED. This new flag will be
-* configured based on the -mfpu-abi option in extra
-* compiler flags.
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#include "xil_errata.h"
-#include "bspconfig.h"
-
-.org 0
-.text
-
-.globl _vector_table
-
-.section .vectors
-_vector_table:
- B _boot
- B Undefined
- B SVCHandler
- B PrefetchAbortHandler
- B DataAbortHandler
- NOP /* Placeholder for address exception vector*/
- B IRQHandler
- B FIQHandler
-
-
-IRQHandler: /* IRQ vector handler */
-
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/
-#if FPU_HARD_FLOAT_ABI_ENABLED
- vpush {d0-d7}
- vpush {d16-d31}
- vmrs r1, FPSCR
- push {r1}
- vmrs r1, FPEXC
- push {r1}
-#endif
-
-#ifdef PROFILING
- ldr r2, =prof_pc
- subs r3, lr, #0
- str r3, [r2]
-#endif
-
- bl IRQInterrupt /* IRQ vector */
-
-#if FPU_HARD_FLOAT_ABI_ENABLED
- pop {r1}
- vmsr FPEXC, r1
- pop {r1}
- vmsr FPSCR, r1
- vpop {d16-d31}
- vpop {d0-d7}
-#endif
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
-
- subs pc, lr, #4 /* adjust return */
-
-
-FIQHandler: /* FIQ vector handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
-#if FPU_HARD_FLOAT_ABI_ENABLED
- vpush {d0-d7}
- vpush {d16-d31}
- vmrs r1, FPSCR
- push {r1}
- vmrs r1, FPEXC
- push {r1}
-#endif
-
-FIQLoop:
- bl FIQInterrupt /* FIQ vector */
-
-#if FPU_HARD_FLOAT_ABI_ENABLED
- pop {r1}
- vmsr FPEXC, r1
- pop {r1}
- vmsr FPSCR, r1
- vpop {d16-d31}
- vpop {d0-d7}
-#endif
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
- subs pc, lr, #4 /* adjust return */
-
-
-Undefined: /* Undefined handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- ldr r0, =UndefinedExceptionAddr
- sub r1, lr, #4
- str r1, [r0] /* Store address of instruction causing undefined exception */
-
- bl UndefinedException /* UndefinedException: call C function here */
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
- movs pc, lr
-
-SVCHandler: /* SWI handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
-
- tst r0, #0x20 /* check the T bit */
- ldrneh r0, [lr,#-2] /* Thumb mode */
- bicne r0, r0, #0xff00 /* Thumb mode */
- ldreq r0, [lr,#-4] /* ARM mode */
- biceq r0, r0, #0xff000000 /* ARM mode */
-
- bl SWInterrupt /* SWInterrupt: call C function here */
-
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
- movs pc, lr /*return to the next instruction after the SWI instruction */
-
-
-DataAbortHandler: /* Data Abort handler */
-#ifdef CONFIG_ARM_ERRATA_775420
- dsb
-#endif
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- ldr r0, =DataAbortAddr
- sub r1, lr, #8
- str r1, [r0] /* Stores instruction causing data abort */
-
- bl DataAbortInterrupt /*DataAbortInterrupt :call C function here */
-
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
- subs pc, lr, #8 /* points to the instruction that caused the Data Abort exception */
-
-PrefetchAbortHandler: /* Prefetch Abort handler */
-#ifdef CONFIG_ARM_ERRATA_775420
- dsb
-#endif
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- ldr r0, =PrefetchAbortAddr
- sub r1, lr, #4
- str r1, [r0] /* Stores instruction causing prefetch abort */
-
- bl PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */
-
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
- subs pc, lr, #4 /* points to the instruction that caused the Prefetch Abort exception */
-
-.end
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/14/020a9a595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/14/020a9a595243001d18b399c1eb9b3628
deleted file mode 100644
index 75cd6f6..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/14/020a9a595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,105 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.h
-*
-* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions
-*
-* Cache functions provide access to cache related operations such as flush
-* and invalidate for instruction and data caches. It gives option to perform
-* the cache operations on a single cacheline, a range of memory and an entire
-* cache.
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 01/29/10 First release
-* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
-* APIs.
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00 hbm 07/28/09 Initial release
-* 6.2 ms 02/20/17 Fixed compilation warning. This is a fix for CR-969126.
-*
-*
-*
-******************************************************************************/
-
-#include "xil_types.h"
-#include "xil_exception.h"
-
-#include "microblaze_exceptions_g.h"
-#include "microblaze_interrupts_i.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *@cond nocomments
- */
-extern void microblaze_enable_exceptions(void);
-extern void microblaze_disable_exceptions(void);
-extern void microblaze_enable_interrupts(void);
-extern void microblaze_disable_interrupts(void);
-
-/**
-* Currently HAL is an augmented part of standalone BSP, so the old definition
-* of MB_ExceptionVectorTableEntry is used here.
-*/
-
-typedef struct {
- Xil_ExceptionHandler Handler;
- void *CallBackRef;
-} MB_ExceptionVectorTableEntry;
-
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * @endcond
- */
-
-/************************** Variable Definitions *****************************/
-extern MB_ExceptionVectorTableEntry MB_ExceptionVectorTable[XIL_EXCEPTION_ID_INT];
-extern MB_InterruptVectorTableEntry MB_InterruptVectorTable[MB_INTERRUPT_VECTOR_TABLE_ENTRIES];
-
-/****************************************************************************/
-/**
- * @brief This function is a stub handler that is the default handler that gets
- * called if the application has not setup a handler for a specific
- * exception. The function interface has to match the interface
- * specified for a handler even though none of the arguments are used.
- *
- * @param Data: unused by this function.
- *
- *****************************************************************************/
-static void Xil_ExceptionNullHandler(void *Data)
-{
- (void) Data;
-}
-
-/****************************************************************************/
-/**
-* @brief Initialize exception handling for the processor. The exception
-* vector table is setup with the stub handler for all exceptions.
-*
-*****************************************************************************/
-void Xil_ExceptionInit(void)
-{
- /*
- * there is no need to setup the exception table here
- */
-
-}
-
-/****************************************************************************/
-/**
-* @brief Enable Exceptions.
-*
-******************************************************************************/
-void Xil_ExceptionEnable(void)
-{
-#ifdef MICROBLAZE_EXCEPTIONS_ENABLED
- microblaze_enable_exceptions();
-#endif
- microblaze_enable_interrupts();
-}
-
-/****************************************************************************/
-/**
-* @brief Disable Exceptions.
-*
-******************************************************************************/
-void Xil_ExceptionDisable(void)
-{
-#ifdef MICROBLAZE_EXCEPTIONS_ENABLED
- microblaze_disable_exceptions();
-#endif
- microblaze_disable_interrupts();
-}
-
-/*****************************************************************************/
-/**
-*@brief Makes the connection between the Id of the exception source and the
-* associated handler that is to run when the exception is recognized.
-* The argument provided in this call as the DataPtr is used as the
-* argument for the handler when it is called.
-*
-* @param Id: contains the 32 bit ID of the exception source and should
-* be XIL_EXCEPTION_INT or be in the range of 0 to XIL_EXCEPTION_LAST.
-* See xil_mach_exception.h for further information.
-* @param Handler: handler function to be registered for exception
-* @param Data: a reference to data that will be passed to the handler
-* when it gets called.
-*
-****************************************************************************/
-void Xil_ExceptionRegisterHandler(u32 Id, Xil_ExceptionHandler Handler,
- void *Data)
-{
- if (Id == XIL_EXCEPTION_ID_INT) {
- MB_InterruptVectorTable[0].Handler = Handler;
- MB_InterruptVectorTable[0].CallBackRef = Data;
- }
- else {
-#ifdef MICROBLAZE_EXCEPTIONS_ENABLED
- MB_ExceptionVectorTable[Id].Handler = Handler;
- MB_ExceptionVectorTable[Id].CallBackRef = Data;
-#endif
- }
-}
-
-
-/*****************************************************************************/
-/**
-* @brief Removes the handler for a specific exception Id. The stub handler
-* is then registered for this exception Id.
-*
-* @param Id: contains the 32 bit ID of the exception source and should
-* be XIL_EXCEPTION_INT or in the range of 0 to XIL_EXCEPTION_LAST.
-* See xexception_l.h for further information.
-*
-****************************************************************************/
-void Xil_ExceptionRemoveHandler(u32 Id)
-{
- if (Id == XIL_EXCEPTION_ID_INT) {
- MB_InterruptVectorTable[0].Handler = Xil_ExceptionNullHandler;
- MB_InterruptVectorTable[0].CallBackRef = NULL;
- }
- else {
-
-#ifdef MICROBLAZE_EXCEPTIONS_ENABLED
- MB_ExceptionVectorTable[Id].Handler =
- Xil_ExceptionNullHandler;
- MB_ExceptionVectorTable[Id].CallBackRef = NULL;
-#endif
- }
-}
-/**
-* @} End of "addtogroup microblaze_exception_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/14/404821545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/14/404821545243001d18b399c1eb9b3628
deleted file mode 100644
index 3c23a5f..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/14/404821545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,25 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xcpu_cortexa9.h
-* @addtogroup cpu_cortexa9_v2_11
-* @{
-* @details
-*
-* dummy file
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------------
-* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID
-* parameter of cpu_cortexa9 in xparameters.h
-# 2.7 mus 07/03/18 Updated tcl to not to add default flags forcefully into
-# extra compiler flags. Now, user can remove default flags
-# from extra compiler flags. It fixes CR#998768.
-******************************************************************************/
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/14/a084a9575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/14/a084a9575243001d18b399c1eb9b3628
deleted file mode 100644
index 9d17f5c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/14/a084a9575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,86 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xtime_l.h
-* @addtogroup a9_time_apis Cortex A9 Time Functions
-*
-* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This
-* counter increases by one at every two processor cycles. These functions can
-* be used to get/set time in the global timer.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 1.00a rp/sdm 11/03/09 Initial release.
-* 3.06a sgd 05/15/12 Updated get/set time functions to make use Global Timer
-* 3.06a asa 06/17/12 Reverted back the changes to make use Global Timer.
-* 3.07a sgd 07/05/12 Updated get/set time functions to make use Global Timer
-* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep
-* implementation
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
-* displaying same warnings multiple times. It fixes CR#1090562.
-*
- *
- * The Spartan-3AF Embedded Peripheral Block contains a USB controller for
- * communication with serial peripherals or hosts. The USB controller supports
- * Host, Device and On the Go (OTG) applications.
- *
- *
USB Controller Features
- *
- * - Supports Low Speed USB 1.1 (1.5Mbps), Full Speed USB 1.1 (12Mbps), and
- * High Speed USB 2.0 (480Mbps) data speeds
- * - Supports Device, Host and OTG operational modes
- * - ULPI transceiver interface for USB 2.0 operation
- * - Integrated USB Full and Low speed serial transceiver interfaces for lowest
- * cost connections
- *
- *
Initialization & Configuration
- *
- * The configuration of the USB driver happens in multiple stages:
- *
- * - (a) Configuration of the basic parameters:
- * In this stage the basic parameters for the driver are configured,
- * including the base address and the controller ID.
- *
- * - (b) Configuration of the DEVICE endpoints (if applicable):
- * If DEVICE mode is desired, the endpoints of the controller need to be
- * configured using the XUsbPs_DeviceConfig data structure. Once the
- * endpoint configuration is set up in the data structure, The user then
- * needs to allocate the required amount of DMAable memory and
- * finalize the configuration of the XUsbPs_DeviceConfig data structure,
- * e.g. setting the DMAMemVirt and DMAMemPhys members.
- *
- * - (c) Configuration of the DEVICE modes:
- * In the second stage the parameters for DEVICE are configured.
- * The caller only needs to configure the modes that are
- * actually used. Configuration is done with the:
- * XUsbPs_ConfigureDevice()
- * Configuration parameters are defined and passed
- * into these functions using the:
- * XUsbPs_DeviceConfig data structures.
- *
- *
- *
USB Device Endpoints
- *
- * The USB core supports up to 4 endpoints. Each endpoint has two directions,
- * an OUT (RX) and an IN (TX) direction. Note that the direction is viewed from
- * the host's perspective. Endpoint 0 defaults to be the control endpoint and
- * does not need to be set up. Other endpoints need to be configured and set up
- * depending on the application. Only endpoints that are actuelly used by the
- * application need to be initialized.
- * See the example code (xusbps_intr_example.c) for more information.
- *
- *
- *
Interrupt Handling
- *
- * The USB core uses one interrupt line to report interrupts to the CPU.
- * Interrupts are handled by the driver's interrupt handler function
- * XUsbPs_IntrHandler().
- * It has to be registered with the OS's interrupt subsystem. The driver's
- * interrupt handler divides incoming interrupts into two categories:
- *
- * - General device interrupts
- * - Endopint related interrupts
- *
- * The user (typically the adapter layer) can register general interrupt
- * handler functions and endpoint specific interrupt handler functions with the
- * driver to receive those interrupts by calling the
- * XUsbPs_IntrSetHandler()
- * and
- * XUsbPs_EpSetHandler()
- * functions respectively. Calling these functions with a NULL pointer as the
- * argument for the function pointer will "clear" the handler function.
- *
- * The user can register one handler function for the generic interrupts and
- * two handler functions for each endpoint, one for the RX (OUT) and one for
- * the TX (IN) direction. For some applications it may be useful to register a
- * single endpoint handler function for muliple endpoints/directions.
- *
- * When a callback function is called by the driver, parameters identifying the
- * type of the interrupt will be passed into the handler functions. For general
- * interrupts the interrupt mask will be passed into the handler function. For
- * endpoint interrupts the parameters include the number of the endpoint, the
- * direction (OUT/IN) and the type of the interrupt.
- *
- *
- *
Data buffer handling
- *
- * Data buffers are sent to and received from endpoint using the
- * XUsbPs_EpBufferSend(), XUsbPs_EpBufferSendWithZLT()
- * and
- * XUsbPs_EpBufferReceive()
- * functions.
- *
- * User data buffer size is limited to 16 Kbytes. If the user wants to send a
- * data buffer that is bigger than this limit it needs to break down the data
- * buffer into multiple fragments and send the fragments individually.
- *
- * From the controller perspective Data buffers can be aligned at any boundary.
- * if the buffers are from cache region then the buffer and buffer size should
- * be aligned to cache line aligned
- *
- *
- *
Zero copy
- *
- * The driver uses a zero copy mechanism which imposes certain restrictions to
- * the way the user can handle the data buffers.
- *
- * One restriction is that the user needs to release a buffer after it is done
- * processing the data in the buffer.
- *
- * Similarly, when the user sends a data buffer it MUST not re-use the buffer
- * until it is notified by the driver that the buffer has been transmitted. The
- * driver will notify the user via the registered endpoint interrupt handling
- * function by sending a XUSBPS_EP_EVENT_DATA_TX event.
- *
- *
- *
DMA
- *
- * The driver uses DMA internally to move data from/to memory. This behaviour
- * is transparent to the user. Keeping the DMA handling hidden from the user
- * has the advantage that the same API can be used with USB cores that do not
- * support DMA.
- *
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- ----------------------------------------------------------
- * 1.00a wgr 10/10/10 First release
- * 1.02a wgr 05/16/12 Removed comments as they are showing up in SDK
- * Tabs for CR 657898
- * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet
- * handling.
- * 1.04a nm 10/23/12 Fixed CR# 679106.
- * 11/02/12 Fixed CR# 683931. Mult bits are set properly in dQH.
- * 2.00a kpc 04/03/14 Fixed CR#777763. Corrected the setup tripwire macro val.
- * 2.1 kpc 04/28/14 Removed unused function prototypes
- * 2.2 kpc 08/23/14 Exported XUsbPs_DeviceReset API as global for calling in
- * code coverage tests.
- * 2.3 kpc 02/19/14 Fixed CR#873972, CR#873974. Corrected the logic for proper
- * moving of dTD Head/Tail Pointers. Invalidate the cache
- * after buffer receive in Endpoint Buffer Handler.
- * 2.4 sg 04/26/16 Fixed CR#949693, Corrected the logic for EP flush
- * ms 03/17/17 Added readme.txt file in examples folder for doxygen
- * generation.
- * ms 04/10/17 Modified filename tag to include the file in doxygen
- * examples.
- * 2.5 pm 02/20/20 Added ISO support for usb 2.0 and ch9 common framework
- * calls.
- *
- *
- ******************************************************************************/
-
-#ifndef XUSBPS_H
-#define XUSBPS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xusbps_hw.h"
-#include "xil_types.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions *****************************/
-
-/**
- * @name System hang prevention Timeout counter value.
- *
- * This value is used throughout the code to initialize a Timeout counter that
- * is used when hard polling a register. The ides is to initialize the Timeout
- * counter to a value that is longer than any expected Timeout but short enough
- * so the system will continue to work and report an error while the user is
- * still paying attention. A reasonable Timeout time would be about 10 seconds.
- * The XUSBPS_TIMEOUT_COUNTER value should be chosen so a polling loop would
- * run about 10 seconds before a Timeout is detected. For example:
- *
- * int Timeout = XUSBPS_TIMEOUT_COUNTER;
- * while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- * XUSBPS_CMD_OFFSET) &
- * XUSBPS_CMD_RST_MASK) && --Timeout) {
- * ;
- * }
- * if (0 == Timeout) {
- * return XST_FAILURE;
- * }
- *
- */
-#define XUSBPS_TIMEOUT_COUNTER 1000000
-
-
-/**
- * @name Endpoint Direction (bitmask)
- * Definitions to be used with Endpoint related function that require a
- * 'Direction' parameter.
- *
- * NOTE:
- * The direction is always defined from the perspective of the HOST! This
- * means that an IN endpoint on the controller is used for sending data while
- * the OUT endpoint on the controller is used for receiving data.
- * @{
- */
-#define XUSBPS_EP_DIRECTION_IN 0x01 /**< Endpoint direction IN. */
-#define XUSBPS_EP_DIRECTION_OUT 0x02 /**< Endpoint direction OUT. */
-/* @} */
-
-
-/**
- * @name Endpoint Type
- * Definitions to be used with Endpoint related functions that require a 'Type'
- * parameter.
- * @{
- */
-#define XUSBPS_EP_TYPE_NONE 0 /**< Endpoint is not used. */
-#define XUSBPS_EP_TYPE_CONTROL 1 /**< Endpoint for Control Transfers */
-#define XUSBPS_EP_TYPE_ISOCHRONOUS 2 /**< Endpoint for isochronous data */
-#define XUSBPS_EP_TYPE_BULK 3 /**< Endpoint for BULK Transfers. */
-#define XUSBPS_EP_TYPE_INTERRUPT 4 /**< Endpoint for interrupt Transfers */
-/* @} */
-
-/**
- * Endpoint Max Packet Length in DeviceConfig is a coded value, ch9.6.6.
- *
- * @{
- */
-#define ENDPOINT_MAXP_LENGTH 0x400
-#define ENDPOINT_MAXP_MULT_MASK 0xC00
-#define ENDPOINT_MAXP_MULT_SHIFT 10
-/* @} */
-
-/**
- * @name Field names for status retrieval
- * Definitions for the XUsbPs_GetStatus() function call 'StatusType'
- * parameter.
- * @{
- */
-#define XUSBPS_EP_STS_ADDRESS 1 /**< Address of controller. */
-#define XUSBPS_EP_STS_CONTROLLER_STATE 2 /**< Current controller state. */
-/* @} */
-
- /*
- * Device Speeds
- */
- #define XUSBPS_SPEED_UNKNOWN 0U
- #define XUSBPS_SPEED_LOW 1U
- #define XUSBPS_SPEED_FULL 2U
- #define XUSBPS_SPEED_HIGH 3U
-
-/**
- * @name USB Default alternate setting
- *
- * @{
- */
-#define XUSBPS_DEFAULT_ALT_SETTING 0 /**< The default alternate setting is 0 */
-/* @} */
-
- /*
- * Device States
- */
- #define XUSBPS_STATE_ATTACHED 0U
- #define XUSBPS_STATE_POWERED 1U
- #define XUSBPS_STATE_DEFAULT 2U
- #define XUSBPS_STATE_ADDRESS 3U
- #define XUSBPS_STATE_CONFIGURED 4U
- #define XUSBPS_STATE_SUSPENDED 5U
-
-/**
- * @name Endpoint event types
- * Definitions that are used to identify events that occur on endpoints. Passed
- * to the endpoint event handler functions registered with
- * XUsbPs_EpSetHandler().
- * @{
- */
-#define XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED 0x01
- /**< Setup data has been received on the endpoint. */
-#define XUSBPS_EP_EVENT_DATA_RX 0x02
- /**< Data frame has been received on the endpoint. */
-#define XUSBPS_EP_EVENT_DATA_TX 0x03
- /**< Data frame has been sent on the endpoint. */
-/* @} */
-
-
-/*
- * Maximum packet size for endpoint, 1024
- * @{
- */
-#define XUSBPS_MAX_PACKET_SIZE 1024
- /**< Maximum value can be put into the queue head */
-/* @} */
-/**************************** Type Definitions *******************************/
-
-/******************************************************************************
- * This data type defines the callback function to be used for Endpoint
- * handlers.
- *
- * @param CallBackRef is the Callback reference passed in by the upper
- * layer when setting the handler, and is passed back to the upper
- * layer when the handler is called.
- * @param EpNum is the Number of the endpoint that caused the event.
- * @param EventType is the type of the event that occurred on the endpoint.
- * @param Data is a pointer to user data pointer specified when callback
- * was registered.
- */
-typedef void (*XUsbPs_EpHandlerFunc)(void *CallBackRef,
- u8 EpNum, u8 EventType, void *Data);
-
-/******************************************************************************
- * This data type defines the callback function to be used for Endpoint
- * handlers.
- *
- * @param CallBackRef is the Callback reference passed in by the upper
- * layer when setting the handler, and is passed back to the upper
- * layer when the handler is called.
- * @param RequestedBytes is the number of bytes requested to transfer.
- * @param BytesTxed is the actual number of bytes to be transfer.
- */
-typedef void (*XUsbPs_EpIsoHandlerFunc)(void *CallBackRef,
- u32 RequestedBytes, u32 BytesTxed);
-
-/******************************************************************************
- * This data type defines the callback function to be used for the general
- * interrupt handler.
- *
- * @param CallBackRef is the Callback reference passed in by the upper
- * layer when setting the handler, and is passed back to the upper
- * layer when the handler is called.
- * @param IrqMask is the Content of the interrupt status register. This
- * value can be used by the callback function to distinguish the
- * individual interrupt types.
- */
-typedef void (*XUsbPs_IntrHandlerFunc)(void *CallBackRef, u32 IrqMask);
-
-
-/******************************************************************************/
-
-/* The following type definitions are used for referencing Queue Heads and
- * Transfer Descriptors. The structures themselves are not used, however, the
- * types are used in the API to avoid using (void *) pointers.
- */
-typedef u8 XUsbPs_dQH[XUSBPS_dQH_ALIGN];
-typedef u8 XUsbPs_dTD[XUSBPS_dTD_ALIGN];
-
-
-/**
- * The following data structures are used internally by the L0/L1 driver.
- * Their contents MUST NOT be changed by the upper layers.
- */
-
-/**
- * The following data structure represents OUT endpoint.
- */
-typedef struct {
- XUsbPs_dQH *dQH;
- /**< Pointer to the Queue Head structure of the endpoint. */
-
- XUsbPs_dTD *dTDs;
- /**< Pointer to the first dTD of the dTD list for this
- * endpoint. */
-
- XUsbPs_dTD *dTDCurr;
- /**< Buffer to the currently processed descriptor. */
-
- u8 *dTDBufs;
- /**< Pointer to the first buffer of the buffer list for this
- * endpoint. */
-
- XUsbPs_EpHandlerFunc HandlerFunc;
- XUsbPs_EpIsoHandlerFunc HandlerIsoFunc;
- /**< Handler function for this endpoint. */
- void *HandlerRef;
- /**< User data reference for the handler. */
- u32 RequestedBytes; /**< RequestedBytes for transfer */
- u32 BytesTxed; /**< Actual Bytes transferred */
- u8 *BufferPtr; /**< Buffer location */
- u8 MemAlloted; /**< Mem alloted and data is not received */
- u32 Interval; /**< Data transfer service interval */
-} XUsbPs_EpOut;
-
-
-/**
- * The following data structure represents IN endpoint.
- */
-typedef struct {
- XUsbPs_dQH *dQH;
- /**< Pointer to the Queue Head structure of the endpoint. */
-
- XUsbPs_dTD *dTDs;
- /**< List of pointers to the Transfer Descriptors of the
- * endpoint. */
-
- XUsbPs_dTD *dTDHead;
- /**< Buffer to the next available descriptor in the list. */
-
- XUsbPs_dTD *dTDTail;
- /**< Buffer to the last unsent descriptor in the list*/
-
- XUsbPs_EpHandlerFunc HandlerFunc;
- XUsbPs_EpIsoHandlerFunc HandlerIsoFunc;
- /**< Handler function for this endpoint. */
- void *HandlerRef;
- /**< User data reference for the handler. */
- u32 RequestedBytes; /**< RequestedBytes for transfer */
- u32 BytesTxed; /**< Actual Bytes transferred */
- u8 *BufferPtr; /**< Buffer location */
- u32 Interval; /**< Data transfer service interval */
-} XUsbPs_EpIn;
-
-
-/**
- * The following data structure represents an endpoint used internally
- * by the L0/L1 driver.
- */
-typedef struct {
- /* Each endpoint has an OUT and an IN component.
- */
- XUsbPs_EpOut Out; /**< OUT endpoint structure */
- XUsbPs_EpIn In; /**< IN endpoint structure */
-} XUsbPs_Endpoint;
-
-
-
-/**
- * The following structure is used by the user to receive Setup Data from an
- * endpoint. Using this structure simplifies the process of interpreting the
- * setup data in the core's data fields.
- *
- * The naming scheme for the members of this structure is different from the
- * naming scheme found elsewhere in the code. The members of this structure are
- * defined in the Chapter 9 USB reference guide. Using this naming scheme makes
- * it easier for people familiar with the standard to read the code.
- */
-typedef struct {
- u8 bmRequestType; /**< bmRequestType in setup data */
- u8 bRequest; /**< bRequest in setup data */
- u16 wValue; /**< wValue in setup data */
- u16 wIndex; /**< wIndex in setup data */
- u16 wLength; /**< wLength in setup data */
-}
-XUsbPs_SetupData;
-
-
-/**
- * Data structures used to configure endpoints.
- */
-typedef struct {
- u32 Type;
- /**< Endpoint type:
- - XUSBPS_EP_TYPE_CONTROL
- - XUSBPS_EP_TYPE_ISOCHRONOUS
- - XUSBPS_EP_TYPE_BULK
- - XUSBPS_EP_TYPE_INTERRUPT */
-
- u32 NumBufs;
- /**< Number of buffers to be handled by this endpoint. */
- u32 BufSize;
- /**< Buffer size. Only relevant for OUT (receive) Endpoints. */
-
- u16 MaxPacketSize;
- /**< Maximum packet size for this endpoint. This number will
- * define the maximum number of bytes sent on the wire per
- * transaction. Range: 0..1024 */
-} XUsbPs_EpSetup;
-
-
-/**
- * Endpoint configuration structure.
- */
-typedef struct {
- XUsbPs_EpSetup Out; /**< OUT component of endpoint. */
- XUsbPs_EpSetup In; /**< IN component of endpoint. */
-} XUsbPs_EpConfig;
-
-
-/**
- * The XUsbPs_DeviceConfig structure contains the configuration information to
- * configure the USB controller for DEVICE mode. This data structure is used
- * with the XUsbPs_ConfigureDevice() function call.
- */
-typedef struct {
- u8 NumEndpoints; /**< Number of Endpoints for the controller.
- This number depends on the runtime
- configuration of driver. The driver may
- configure fewer endpoints than are available
- in the core. */
-
- XUsbPs_EpConfig EpCfg[XUSBPS_MAX_ENDPOINTS];
- /**< List of endpoint configurations. */
-
-
- u32 DMAMemPhys; /**< Physical base address of DMAable memory
- allocated for the driver. */
-
- /* The following members are used internally by the L0/L1 driver. They
- * MUST NOT be accesses and/or modified in any way by the upper layers.
- *
- * The reason for having these members is that we generally try to
- * avoid allocating memory in the L0/L1 driver as we want to be OS
- * independent. In order to avoid allocating memory for this data
- * structure wihin L0/L1 we put it into the XUsbPs_DeviceConfig
- * structure which is allocated by the caller.
- */
- XUsbPs_Endpoint Ep[XUSBPS_MAX_ENDPOINTS];
- /**< List of endpoint metadata structures. */
-
- u32 PhysAligned; /**< 64 byte aligned base address of the DMA
- memory block. Will be computed and set by
- the L0/L1 driver. */
-} XUsbPs_DeviceConfig;
-
-
-/**
- * The XUsbPs_Config structure contains configuration information for the USB
- * controller.
- *
- * This structure only contains the basic configuration for the controller. The
- * caller also needs to initialize the controller for the DEVICE mode
- * using the XUsbPs_DeviceConfig data structures with the
- * XUsbPs_ConfigureDevice() function call
- */
-typedef struct {
- u16 DeviceID; /**< Unique ID of controller. */
- u32 BaseAddress; /**< Core register base address. */
-} XUsbPs_Config;
-
-typedef XUsbPs_Config Usb_Config;
-
-struct Usb_DevData {
- u8 Speed;
- u8 State;
-
- void *PrivateData;
-};
-
-/**
- * The XUsbPs driver instance data. The user is required to allocate a
- * variable of this type for every USB controller in the system. A pointer to a
- * variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XUsbPs_SetupData SetupData;
- /**< Setup Packet buffer */
- XUsbPs_Config Config; /**< Configuration structure */
-
- int CurrentAltSetting; /**< Current alternative setting of interface */
-
- void *UserDataPtr; /**< Data pointer to be used by upper layers to
- store application dependent data structures.
- The upper layers are responsible to allocated
- and free the memory. The driver will not
- mofidy this data pointer. */
-
- /**
- * The following structures hold the configuration for DEVICE mode
- * of the controller. They are initialized using the
- * XUsbPs_ConfigureDevice() function call.
- */
- XUsbPs_DeviceConfig DeviceConfig;
- /**< Configuration for the DEVICE mode. */
-
- XUsbPs_IntrHandlerFunc HandlerFunc;
- /**< Handler function for the controller. */
- void *HandlerRef;
- /**< User data reference for the handler. */
- u32 HandlerMask;
- /**< User interrupt mask. Defines which interrupts will cause
- * the callback to be called. */
- struct Usb_DevData *AppData;
- u8 IsConfigDone;
- void *data_ptr; /* pointer for storing applications data */
-} XUsbPs;
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/******************************************************************************
- *
- * USB CONTROLLER RELATED MACROS
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
- * This macro returns the current frame number.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @return The current frame number.
- *
- * @note C-style signature:
- * u32 XUsbPs_GetFrameNum(const XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_GetFrameNum(InstancePtr) \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, XUSBPS_FRAME_OFFSET)
-
-
-/*****************************************************************************/
-/**
- * This macro starts the USB engine.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @note C-style signature:
- * void XUsbPs_Start(XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_Start(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
-
-
-/*****************************************************************************/
-/**
- * This macro stops the USB engine.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @note C-style signature:
- * void XUsbPs_Stop(XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_Stop(InstancePtr) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
-
-
-/*****************************************************************************/
-/**
- * This macro forces the USB engine to be in Full Speed (FS) mode.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @note C-style signature:
- * void XUsbPs_ForceFS(XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_ForceFS(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
- XUSBPS_PORTSCR_PFSC_MASK)
-
-
-/*****************************************************************************/
-/**
- * This macro starts the USB Timer 0, with repeat option for period of
- * one second.
- *
- * @param InstancePtr is a pointer to XUsbPs instance of the controller.
- * @param Interval is the interval for Timer0 to generate an interrupt
- *
- * @note C-style signature:
- * void XUsbPs_StartTimer0(XUsbPs *InstancePtr, u32 Interval)
- *
- ******************************************************************************/
-#define XUsbPs_StartTimer0(InstancePtr, Interval) \
-{ \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_TIMER0_LD_OFFSET, (Interval)); \
- XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
- XUSBPS_TIMER_RUN_MASK | \
- XUSBPS_TIMER_RESET_MASK | \
- XUSBPS_TIMER_REPEAT_MASK); \
-} \
-
-
-/*****************************************************************************/
-/**
-* This macro stops Timer 0.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_StopTimer0(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_StopTimer0(InstancePtr) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
- XUSBPS_TIMER_RUN_MASK)
-
-
-/*****************************************************************************/
-/**
-* This macro reads Timer 0.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_ReadTimer0(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_ReadTimer0(InstancePtr) \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_TIMER0_CTL_OFFSET) & \
- XUSBPS_TIMER_COUNTER_MASK
-
-
-/*****************************************************************************/
-/**
-* This macro force remote wakeup on host
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_RemoteWakeup(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_RemoteWakeup(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
- XUSBPS_PORTSCR_FPR_MASK)
-
-
-/******************************************************************************
- *
- * ENDPOINT RELATED MACROS
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
-* This macro enables the given endpoint for the given direction.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is number of the endpoint to enable.
-* @param Dir is direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpEnable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpEnable(InstancePtr, EpNum, Dir) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro disables the given endpoint for the given direction.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is the number of the endpoint to disable.
-* @param Dir is the direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpDisable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpDisable(InstancePtr, EpNum, Dir) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro stalls the given endpoint for the given direction, and flush
-* the buffers.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is number of the endpoint to stall.
-* @param Dir is the direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpStall(InstancePtr, EpNum, Dir) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro unstalls the given endpoint for the given direction.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is the Number of the endpoint to unstall.
-* @param Dir is the Direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpUnStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpUnStall(InstancePtr, EpNum, Dir) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro flush an endpoint upon interface disable
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is the number of the endpoint to flush.
-* @param Dir is the direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpFlush(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpFlush(InstancePtr, EpNum, Dir) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPFLUSH_OFFSET, \
- 1 << (EpNum + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? \
- XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT))) \
-
-/*****************************************************************************/
-/**
-* This macro enables the interrupts defined by the bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param IntrMask is the Bit mask of interrupts to be enabled.
-*
-* @note C-style signature:
-* void XUsbPs_IntrEnable(XUsbPs *InstancePtr, u32 IntrMask)
-*
-******************************************************************************/
-#define XUsbPs_IntrEnable(InstancePtr, IntrMask) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
-
-
-/*****************************************************************************/
-/**
-* This function disables the interrupts defined by the bit mask.
-*
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param IntrMask is a Bit mask of interrupts to be disabled.
-*
-* @note C-style signature:
-* void XUsbPs_IntrDisable(XUsbPs *InstancePtr, u32 IntrMask)
-*
-******************************************************************************/
-#define XUsbPs_IntrDisable(InstancePtr, IntrMask) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
-
-
-/*****************************************************************************/
-/**
-* This macro enables the endpoint NAK interrupts defined by the bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be
-* enabled.
-* @note C-style signature:
-* void XUsbPs_NakIntrEnable(XUsbPs *InstancePtr, u32 NakIntrMask)
-*
-******************************************************************************/
-#define XUsbPs_NakIntrEnable(InstancePtr, NakIntrMask) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
-
-
-/*****************************************************************************/
-/**
-* This macro disables the endpoint NAK interrupts defined by the bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param NakIntrMask is a Bit mask of endpoint NAK interrupts to be
-* disabled.
-*
-* @note
-* C-style signature:
-* void XUsbPs_NakIntrDisable(XUsbPs *InstancePtr, u32 NakIntrMask)
-*
-******************************************************************************/
-#define XUsbPs_NakIntrDisable(InstancePtr, NakIntrMask) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
-
-
-/*****************************************************************************/
-/**
-* This function clears the endpoint NAK interrupts status defined by the
-* bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be cleared.
-*
-* @note C-style signature:
-* void XUsbPs_NakIntrClear(XUsbPs *InstancePtr, u32 NakIntrMask)
-*
-******************************************************************************/
-#define XUsbPs_NakIntrClear(InstancePtr, NakIntrMask) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_EPNAKISR_OFFSET, NakIntrMask)
-
-
-
-/*****************************************************************************/
-/**
-* This macro sets the Interrupt Threshold value in the control register
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param Threshold is the Interrupt threshold to be set.
-* Allowed values:
-* - XUSBPS_CMD_ITHRESHOLD_0 - Immediate interrupt
-* - XUSBPS_CMD_ITHRESHOLD_1 - 1 Frame
-* - XUSBPS_CMD_ITHRESHOLD_2 - 2 Frames
-* - XUSBPS_CMD_ITHRESHOLD_4 - 4 Frames
-* - XUSBPS_CMD_ITHRESHOLD_8 - 8 Frames
-* - XUSBPS_CMD_ITHRESHOLD_16 - 16 Frames
-* - XUSBPS_CMD_ITHRESHOLD_32 - 32 Frames
-* - XUSBPS_CMD_ITHRESHOLD_64 - 64 Frames
-*
-* @note
-* C-style signature:
-* void XUsbPs_SetIntrThreshold(XUsbPs *InstancePtr, u8 Threshold)
-*
-******************************************************************************/
-#define XUsbPs_SetIntrThreshold(InstancePtr, Threshold) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_CMD_OFFSET, (Threshold))\
-
-
-/*****************************************************************************/
-/**
-* This macro sets the Tripwire bit in the USB command register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_SetTripwire(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_SetSetupTripwire(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, \
- XUSBPS_CMD_SUTW_MASK)
-
-
-/*****************************************************************************/
-/**
-* This macro clears the Tripwire bit in the USB command register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_ClrTripwire(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_ClrSetupTripwire(InstancePtr) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, \
- XUSBPS_CMD_SUTW_MASK)
-
-
-/*****************************************************************************/
-/**
-* This macro checks if the Tripwire bit in the USB command register is set.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @return
-* - TRUE: The tripwire bit is still set.
-* - FALSE: The tripwire bit has been cleared.
-*
-* @note C-style signature:
-* int XUsbPs_TripwireIsSet(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_SetupTripwireIsSet(InstancePtr) \
- (XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_CMD_OFFSET) & \
- XUSBPS_CMD_SUTW_MASK ? TRUE : FALSE)
-
-
-/******************************************************************************
-*
-* GENERAL REGISTER / BIT MANIPULATION MACROS
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-* This macro sets the given bit mask in the register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param RegOffset is the register offset to be written.
-* @param Bits is the Bits to be set in the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XUsbPs_SetBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
-*
-*****************************************************************************/
-#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- RegOffset) | (Bits));
-
-
-/****************************************************************************/
-/**
-*
-* This macro clears the given bits in the register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param RegOffset is the register offset to be written.
-* @param Bits are the bits to be cleared in the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XUsbPs_ClrBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
-*
-*****************************************************************************/
-#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- RegOffset) & ~(Bits));
-
-
-/************************** Function Prototypes ******************************/
-
-/**
- * Setup / Initialize functions.
- *
- * Implemented in file xusbps.c
- */
-int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
- const XUsbPs_Config *ConfigPtr, u32 BaseAddress);
-
-int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr,
- const XUsbPs_DeviceConfig *CfgPtr);
-
-/**
- * Common functions used for DEVICE/HOST mode.
- */
-int XUsbPs_Reset(XUsbPs *InstancePtr);
-
-void XUsbPs_DeviceReset(XUsbPs *InstancePtr);
-
-/**
- * DEVICE mode specific functions.
- */
-int XUsbPs_BusReset(XUsbPs *InstancePtr);
-int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address);
-
-
-/**
- * Handling Suspend and Resume.
- *
- * Implemented in xusbps.c
- */
-int XUsbPs_Suspend(const XUsbPs *InstancePtr);
-int XUsbPs_Resume(const XUsbPs *InstancePtr);
-int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr);
-
-
-/*
- * Functions for managing Endpoints / Transfers
- *
- * Implemented in file xusbps_endpoint.c
- */
-int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum,
- const u8 *BufferPtr, u32 BufferLen);
-int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum,
- const u8 *BufferPtr, u32 BufferLen);
-int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
- u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle);
-void XUsbPs_EpBufferRelease(u32 Handle);
-
-int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
- XUsbPs_EpHandlerFunc CallBackFunc,
- void *CallBackRef);
-s32 XUsbPs_EpSetIsoHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
- XUsbPs_EpIsoHandlerFunc CallBackFunc);
-int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum,
- XUsbPs_SetupData *SetupDataPtr);
-
-int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction);
-
-int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr,
- int EpNum, unsigned short NewDirection, int DirectionChanged);
-
-/*
- * Interrupt handling functions
- *
- * Implemented in file xusbps_intr.c
- */
-void XUsbPs_IntrHandler(void *InstancePtr);
-
-int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
- XUsbPs_IntrHandlerFunc CallBackFunc,
- void *CallBackRef, u32 Mask);
-void XUsbPs_EpGetData(XUsbPs *InstancePtr, u8 EpNum, u32 BufferLen);
-
-s32 XUsbPs_EpDataBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
- u8 *BufferPtr, u32 BufferLen);
-/*
- * Helper functions for static configuration.
- * Implemented in xusbps_sinit.c
- */
-XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceId);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XUSBPS_H */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/15/a01b82565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/15/a01b82565243001d18b399c1eb9b3628
deleted file mode 100644
index dcdb877..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/15/a01b82565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,459 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file mb_interface.h
-*
-* @addtogroup microblaze_pseudo_asm_macro Microblaze Pseudo-asm Macros and Interrupt Handling APIs
-*
-* Microblaze BSP includes macros to provide convenient access to various registers
-* in the MicroBlaze processor. Some of these macros are very useful within
-* exception handlers for retrieving information about the exception.Also,
-* the interrupt handling functions help manage interrupt handling on MicroBlaze
-* processor devices.To use these functions, include the header file
-* mb_interface.h in your source code
-*
-* @{
-*
-******************************************************************************/
-/**
- *@cond nocomments
- */
-
-#ifndef _MICROBLAZE_INTERFACE_H_
-#define _MICROBLAZE_INTERFACE_H_
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_exception.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-extern void microblaze_enable_interrupts(void); /* Enable Interrupts */
-extern void microblaze_disable_interrupts(void); /* Disable Interrupts */
-extern void microblaze_enable_icache(void); /* Enable Instruction Cache */
-extern void microblaze_disable_icache(void); /* Disable Instruction Cache */
-extern void microblaze_enable_dcache(void); /* Enable Instruction Cache */
-extern void microblaze_disable_dcache(void); /* Disable Instruction Cache */
-extern void microblaze_enable_exceptions(void); /* Enable hardware exceptions */
-extern void microblaze_disable_exceptions(void); /* Disable hardware exceptions */
-
-/**
- *@endcond
- */
-extern void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr); /* Register top level interrupt handler */
-extern void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr); /* Register exception handler */
-
-/**
- *@cond nocomments
- */
-extern void microblaze_invalidate_icache(void); /* Invalidate the entire icache */
-extern void microblaze_invalidate_dcache(void); /* Invalidate the entire dcache */
-extern void microblaze_flush_dcache(void); /* Flush the whole dcache */
-extern void microblaze_invalidate_icache_range(UINTPTR cacheaddr, u32 len); /* Invalidate a part of the icache */
-extern void microblaze_invalidate_dcache_range(UINTPTR cacheaddr, u32 len); /* Invalidate a part of the dcache */
-extern void microblaze_flush_dcache_range(UINTPTR cacheaddr, u32 len); /* Flush a part of the dcache */
-extern void microblaze_scrub(void); /* Scrub LMB and internal BRAM */
-extern void microblaze_invalidate_cache_ext(void); /* Invalidate cache ext */
-extern void microblaze_flush_cache_ext(void); /* Flush cache ext */
-extern void microblaze_flush_cache_ext_range(UINTPTR cacheaddr,
- u32 len); /* Flush cache ext range */
-extern void microblaze_invalidate_cache_ext_range(UINTPTR cacheaddr,
- u32 len); /* Invalidate cache ext range */
-
-/* Deprecated */
-extern void microblaze_update_icache (s32 , s32 , s32 ) __attribute__((deprecated));
-extern void microblaze_init_icache_range (s32 , s32 ) __attribute__((deprecated));
-extern void microblaze_update_dcache (s32 , s32 , s32 ) __attribute__((deprecated));
-extern void microblaze_init_dcache_range (s32 , s32 ) __attribute__((deprecated));
-
-/* necessary for pre-processor */
-#define stringify(s) tostring(s)
-#define tostring(s) #s
-
-/* FSL Access Macros */
-
-/* Blocking Data Read and Write to FSL no. id */
-#define getfsl(val, id) asm volatile ("get\t%0,rfsl" stringify(id) : "=d" (val))
-#define putfsl(val, id) asm volatile ("put\t%0,rfsl" stringify(id) :: "d" (val))
-
-/* Non-blocking Data Read and Write to FSL no. id */
-#define ngetfsl(val, id) asm volatile ("nget\t%0,rfsl" stringify(id) : "=d" (val))
-#define nputfsl(val, id) asm volatile ("nput\t%0,rfsl" stringify(id) :: "d" (val))
-
-/* Blocking Control Read and Write to FSL no. id */
-#define cgetfsl(val, id) asm volatile ("cget\t%0,rfsl" stringify(id) : "=d" (val))
-#define cputfsl(val, id) asm volatile ("cput\t%0,rfsl" stringify(id) :: "d" (val))
-
-/* Non-blocking Control Read and Write to FSL no. id */
-#define ncgetfsl(val, id) asm volatile ("ncget\t%0,rfsl" stringify(id) : "=d" (val))
-#define ncputfsl(val, id) asm volatile ("ncput\t%0,rfsl" stringify(id) :: "d" (val))
-
-/* Polling versions of FSL access macros. This makes the FSL access interruptible */
-#define getfsl_interruptible(val, id) asm volatile ("\n1:\n\tnget\t%0,rfsl" stringify(id) "\n\t" \
- "addic\tr18,r0,0\n\t" \
- "bnei\tr18,1b\n" \
- : "=d" (val) :: "r18")
-
-#define putfsl_interruptible(val, id) asm volatile ("\n1:\n\tnput\t%0,rfsl" stringify(id) "\n\t" \
- "addic\tr18,r0,0\n\t" \
- "bnei\tr18,1b\n" \
- :: "d" (val) : "r18")
-
-#define cgetfsl_interruptible(val, id) asm volatile ("\n1:\n\tncget\t%0,rfsl" stringify(id) "\n\t" \
- "addic\tr18,r0,0\n\t" \
- "bnei\tr18,1b\n" \
- : "=d" (val) :: "r18")
-
-#define cputfsl_interruptible(val, id) asm volatile ("\n1:\n\tncput\t%0,rfsl" stringify(id) "\n\t" \
- "addic\tr18,r0,0\n\t" \
- "bnei\tr18,1b\n" \
- :: "d" (val) : "r18")
-/* FSL valid and error check macros. */
-#define fsl_isinvalid(result) asm volatile ("addic\t%0,r0,0" : "=d" (result))
-#define fsl_iserror(error) asm volatile ("mfs\t%0,rmsr\n\t" \
- "andi\t%0,%0,0x10" : "=d" (error))
-
-/* Pseudo assembler instructions */
-#define clz(v) ({ u32 _rval = 0U; \
- __asm__ __volatile__ ( \
- "clz\t%0,%1\n" : "=d"(_rval): "d" (v) \
- ); \
- _rval; \
- })
-
-#define mbar(mask) ({ __asm__ __volatile__ ("mbar\t" stringify(mask) ); })
-#define mb_sleep() ({ __asm__ __volatile__ ("sleep\t"); })
-#define mb_hibernate() ({ __asm__ __volatile__ ("hibernate\t"); })
-#define mb_suspend() ({ __asm__ __volatile__ ("suspend\t"); })
-#define mb_swapb(v) ({ u32 _rval = 0U; \
- __asm__ __volatile__ ( \
- "swapb\t%0,%1\n" : "=d"(_rval) : "d" (v) \
- ); \
- _rval; \
- })
-
-#define mb_swaph(v) ({ u32 _rval = 0U; \
- __asm__ __volatile__ ( \
- "swaph\t%0,%1\n" : "=d"(_rval) : "d" (v) \
- ); \
- _rval; \
- })
-
-/** @name Microblaze pseudo-asm macros
- *
- * The following is a summary of the MicroBlaze processor pseudo-asm macros.
- * @{
- */
-
- /**
- Return value from the general purpose register (GPR) rn.
- @param rn General purpose register to be read.
-*/
-#define mfgpr(rn) ({ UINTPTR _rval = 0U; \
- __asm__ __volatile__ ( \
- "or\t%0,r0," stringify(rn) "\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
- /**
- Return the current value of the MSR.
-*/
-#define mfmsr() ({ UINTPTR _rval = 0U; \
- __asm__ __volatile__ ( \
- "mfs\t%0,rmsr\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
- /**
- Return the current value of the Exception Address Register (EAR).
-*/
-#define mfear() ({ UINTPTR _rval = 0U; \
- __asm__ __volatile__ ( \
- "mfs\t%0,rear\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mfeare() ({ UINTPTR _rval = 0U; \
- __asm__ __volatile__ ( \
- "mfse\t%0,rear\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
- /**
- Return the current value of the Exception Status Register (ESR).
-*/
-#define mfesr() ({ UINTPTR _rval = 0U; \
- __asm__ __volatile__ ( \
- "mfs\t%0,resr\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
- /**
- Return the current value of the Floating Point Status (FPS).
-*/
-#define mffsr() ({ UINTPTR _rval = 0U; \
- __asm__ __volatile__ ( \
- "mfs\t%0,rfsr\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-/*@}*/
-#define mfpvr(rn) ({ UINTPTR _rval = 0U; \
- __asm__ __volatile__ ( \
- "mfs\t%0,rpvr" stringify(rn) "\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mfpvre(rn) ({ UINTPTR _rval = 0U; \
- __asm__ __volatile__ ( \
- "mfse\t%0,rpvr" stringify(rn) "\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mfbtr() ({ UINTPTR _rval = 0U; \
- __asm__ __volatile__ ( \
- "mfs\t%0,rbtr\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mfedr() ({ UINTPTR _rval = 0U; \
- __asm__ __volatile__ ( \
- "mfs\t%0,redr\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mfpid() ({ UINTPTR _rval = 0U; \
- __asm__ __volatile__ ( \
- "mfs\t%0,rpid\n" : "=d"(_rval)\
- ); \
- _rval; \
- })
-
-#define mfzpr() ({ UINTPTR _rval = 0U; \
- __asm__ __volatile__ ( \
- "mfs\t%0,rzpr\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mftlbx() ({ UINTPTR _rval = 0U; \
- __asm__ __volatile__ ( \
- "mfs\t%0,rtlbx\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mftlblo() ({ UINTPTR _rval = 0U; \
- __asm__ __volatile__ ( \
- "mfs\t%0,rtlblo\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mftlbhi() ({ UINTPTR _rval = 0U; \
- __asm__ __volatile__ ( \
- "mfs\t%0,rtlbhi\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mfslr() ({ UINTPTR _rval = 0U; \
- __asm__ __volatile__ ( \
- "mfs\t%0,rslr\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mfshr() ({ UINTPTR _rval = 0U; \
- __asm__ __volatile__ ( \
- "mfs\t%0,rshr\n" : "=d"(_rval) \
- ); \
- _rval; \
- })
-
-#define mtgpr(rn, v) ({ __asm__ __volatile__ ( \
- "or\t" stringify(rn) ",r0,%0\n" :: "d" (v) \
- ); \
- })
-
-#define mtmsr(v) ({ __asm__ __volatile__ ( \
- "mts\trmsr,%0\n\tnop\n" :: "d" (v) \
- ); \
- })
-
-
-#define mtfsr(v) ({ __asm__ __volatile__ ( \
- "mts\trfsr,%0\n\tnop\n" :: "d" (v) \
- ); \
- })
-
-#define mtpid(v) ({ __asm__ __volatile__ ( \
- "mts\trpid,%0\n\tnop\n" :: "d" (v) \
- ); \
- })
-
-#define mtzpr(v) ({ __asm__ __volatile__ ( \
- "mts\trzpr,%0\n\tnop\n" :: "d" (v) \
- ); \
- })
-
-#define mttlbx(v) ({ __asm__ __volatile__ ( \
- "mts\trtlbx,%0\n\tnop\n" :: "d" (v) \
- ); \
- })
-
-#define mttlblo(v) ({ __asm__ __volatile__ ( \
- "mts\trtlblo,%0\n\tnop\n" :: "d" (v) \
- ); \
- })
-
-#define mttlbhi(v) ({ __asm__ __volatile__ ( \
- "mts\trtlbhi,%0\n\tnop\n" :: "d" (v) \
- ); \
- })
-
-#define mttlbsx(v) ({ __asm__ __volatile__ ( \
- "mts\trtlbsx,%0\n\tnop\n" :: "d" (v) \
- ); \
- })
-
-#define mtslr(v) ({ __asm__ __volatile__ ( \
- "mts\trslr,%0\n\tnop\n" :: "d" (v) \
- ); \
- })
-
-#define mtshr(v) ({ __asm__ __volatile__ ( \
- "mts\trshr,%0\n\tnop\n" :: "d" (v) \
- ); \
- })
-
-#define lwx(address) ({ u32 _rval = 0U; \
- __asm__ __volatile__ ( \
- "lwx\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
- ); \
- _rval; \
- })
-
-#define lwr(address) ({ u32 _rval = 0U; \
- __asm__ __volatile__ ( \
- "lwr\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
- ); \
- _rval; \
- })
-
-
-#define lwea(lladdr) ({ u32 _rval = 0U; \
- __asm__ __volatile__ ( \
- "lwea\t%0,%M1,%L1\n" : "=d"(_rval) : "d" (lladdr) \
- ); \
- _rval; \
- })
-
-#define lhur(address) ({ u32 _rval = 0U; \
- __asm__ __volatile__ ( \
- "lhur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
- ); \
- _rval; \
- })
-
-#define lhuea(lladdr) ({ u32 _rval = 0U; \
- __asm__ __volatile__ ( \
- "lhuea\t%0,%M1,%L1\n" : "=d"(_rval) : "d" (lladdr) \
- ); \
- _rval; \
- })
-
-#define lbur(address) ({ u32 _rval = 0U; \
- __asm__ __volatile__ ( \
- "lbur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
- ); \
- _rval; \
- })
-
-#define lbuea(lladdr) ({ u32 _rval = 0U; \
- __asm__ __volatile__ ( \
- "lbuea\t%0,%M1,%L1\n" : "=d"(_rval) : "d" (lladdr) \
- ); \
- _rval; \
- })
-
-#define swx(address, data) ({ __asm__ __volatile__ ( \
- "swx\t%0,%1,r0\n" :: "d" (data), "d" (address) \
- ); \
- })
-
-#define swr(address, data) ({ __asm__ __volatile__ ( \
- "swr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
- ); \
- })
-
-#define swea(lladdr, data) ({ __asm__ __volatile__ ( \
- "swea\t%0,%M1,%L1\n" :: "d" (data), "d" (lladdr) \
- ); \
- })
-
-#define shr(address, data) ({ __asm__ __volatile__ ( \
- "shr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
- ); \
- })
-
-#define shea(lladdr, data) ({ __asm__ __volatile__ ( \
- "shea\t%0,%M1,%L1\n" :: "d" (data), "d" (lladdr) \
- ); \
- })
-
-#define sbr(address, data) ({ __asm__ __volatile__ ( \
- "sbr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
- ); \
- })
-
-#define sbea(lladdr, data) ({ __asm__ __volatile__ ( \
- "sbea\t%0,%M1,%L1\n" :: "d" (data), "d" (lladdr) \
- ); \
- })
-
-#define microblaze_getfpex_operand_a() ({ \
- extern u32 mb_fpex_op_a; \
- mb_fpex_op_a; \
- })
-
-#define microblaze_getfpex_operand_b() ({ \
- extern u32 mb_fpex_op_b; \
- mb_fpex_op_b; \
- })
-
-/* Deprecated MicroBlaze FSL macros */
-#define microblaze_bread_datafsl(val, id) getfsl(val,id)
-#define microblaze_bwrite_datafsl(val, id) putfsl(val,id)
-#define microblaze_nbread_datafsl(val, id) ngetfsl(val,id)
-#define microblaze_nbwrite_datafsl(val, id) nputfsl(val,id)
-#define microblaze_bread_cntlfsl(val, id) cgetfsl(val,id)
-#define microblaze_bwrite_cntlfsl(val, id) cputfsl(val,id)
-#define microblaze_nbread_cntlfsl(val, id) ncgetfsl(val,id)
-#define microblaze_nbwrite_cntlfsl(val, id) ncputfsl(val,id)
-
-#ifdef __cplusplus
-}
-#endif
-#endif // _MICROBLAZE_INTERFACE_H_
-/**
- *@endcond
- */
-
-/**
-* @} End of "addtogroup microblaze_pseudo_asm_macro".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/16/81b3bb545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/16/81b3bb545243001d18b399c1eb9b3628
deleted file mode 100644
index 96afe7c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/16/81b3bb545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,779 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xgpiops_intr.c
-* @addtogroup gpiops_v3_9
-* @{
-*
-* This file contains functions related to GPIO interrupt handling.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sv 01/18/10 First Release
-* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
-* passed to API's. CR# 822636
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
-* 3.1 aru 07/13/18 Ressolved doxygen reported warnings. CR# 1006331.
-* 3.4 aru 08/09/18 Ressolved cppcheck warnings.
-* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
-* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
-* in safety mode and modified the code such as
-* Use of mixed mode arithmetic,Declared the pointer param
-* as Pointer to const,Casting operation to a pointer,
-* Literal value requires a U suffix.
-* 3.5 sne 03/14/19 Added Versal support.
-* 3.5 sne 03/20/19 Fixed multiple interrupts problem CR#1024556.
-* 3.6 sne 06/12/19 Fixed IAR compiler warning.
-* 3.6 sne 08/14/19 Added interrupt handler support on versal.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xgpiops.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-/****************************************************************************/
-/**
-*
-* This function enables the interrupts for the specified pins in the specified
-* bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param Mask is the bit mask of the pins for which interrupts are to
-* be enabled. Bit positions of 1 will be enabled. Bit positions
-* of 0 will keep the previous setting.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertVoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTEN_OFFSET, Mask);
-}
-
-/****************************************************************************/
-/**
-*
-* This function enables the interrupt for the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number for which the interrupt is to be enabled.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin)
-{
- u8 Bank;
- u8 PinNumber;
- u32 IntrReg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
-
- IntrReg = ((u32)1 << (u32)PinNumber);
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTEN_OFFSET, IntrReg);
-}
-
-/****************************************************************************/
-/**
-*
-* This function disables the interrupts for the specified pins in the specified
-* bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param Mask is the bit mask of the pins for which interrupts are
-* to be disabled. Bit positions of 1 will be disabled. Bit
-* positions of 0 will keep the previous setting.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertVoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTDIS_OFFSET, Mask);
-}
-
-/****************************************************************************/
-/**
-*
-* This function disables the interrupts for the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number for which the interrupt is to be disabled.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin)
-{
- u8 Bank;
- u8 PinNumber;
- u32 IntrReg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
-
- IntrReg = ((u32)1 << (u32)PinNumber);
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTDIS_OFFSET, IntrReg);
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the interrupt enable status for a bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-*
-* @return Enabled interrupt(s) in a 32-bit format. Bit positions with 1
-* indicate that the interrupt for that pin is enabled, bit
-* positions with 0 indicate that the interrupt for that pin is
-* disabled.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank)
-{
- u32 IntrMask;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertNonvoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- IntrMask = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTMASK_OFFSET);
- return (~IntrMask);
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns whether interrupts are enabled for the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number for which the interrupt enable status
-* is to be known.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*
-* @return
-* - TRUE if the interrupt is enabled.
-* - FALSE if the interrupt is disabled.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin)
-{
- u8 Bank;
- u8 PinNumber;
- u32 IntrReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
-
- IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTMASK_OFFSET);
-
- return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? (u32)FALSE : (u32)TRUE);
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns interrupt status read from Interrupt Status Register.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-*
-* @return The value read from Interrupt Status Register.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertNonvoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTSTS_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns interrupt enable status of the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number for which the interrupt enable status
-* is to be known.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*
-* @return
-* - TRUE if the interrupt has occurred.
-* - FALSE if the interrupt has not occurred.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin)
-{
- u8 Bank;
- u8 PinNumber;
- u32 IntrReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
-
- IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTSTS_OFFSET);
-
- return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? (u32)TRUE : (u32)FALSE);
-}
-
-/****************************************************************************/
-/**
-*
-* This function clears pending interrupt(s) with the provided mask. This
-* function should be called after the software has serviced the interrupts
-* that are pending.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param Mask is the mask of the interrupts to be cleared. Bit positions
-* of 1 will be cleared. Bit positions of 0 will not change the
-* previous interrupt status.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertVoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- /* Clear the currently pending interrupts. */
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTSTS_OFFSET, Mask);
-}
-
-/****************************************************************************/
-/**
-*
-* This function clears the specified pending interrupt. This function should be
-* called after the software has serviced the interrupts that are pending.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number for which the interrupt status is to be
-* cleared. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin)
-{
- u8 Bank;
- u8 PinNumber;
- u32 IntrReg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
-
- /* Clear the specified pending interrupts. */
- IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTSTS_OFFSET);
-
- IntrReg &= ((u32)1 << PinNumber);
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTSTS_OFFSET, IntrReg);
-}
-
-/****************************************************************************/
-/**
-*
-* This function is used for setting the Interrupt Type, Interrupt Polarity and
-* Interrupt On Any for the specified GPIO Bank pins.
-*
-* @param InstancePtr is a pointer to an XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param IntrType is the 32 bit mask of the interrupt type.
-* 0 means Level Sensitive and 1 means Edge Sensitive.
-* @param IntrPolarity is the 32 bit mask of the interrupt polarity.
-* 0 means Active Low or Falling Edge and 1 means Active High or
-* Rising Edge.
-* @param IntrOnAny is the 32 bit mask of the interrupt trigger for
-* edge triggered interrupts. 0 means trigger on single edge using
-* the configured interrupt polarity and 1 means trigger on both
-* edges.
-*
-* @return None.
-*
-* @note This function is used for setting the interrupt related
-* properties of all the pins in the specified bank. The previous
-* state of the pins is not maintained.
-* To change the Interrupt properties of a single GPIO pin, use the
-* function XGpioPs_SetPinIntrType().
-*
-*****************************************************************************/
-void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
- u32 IntrPolarity, u32 IntrOnAny)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertVoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTTYPE_OFFSET, IntrType);
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTPOL_OFFSET, IntrPolarity);
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTANY_OFFSET, IntrOnAny);
-}
-
-/****************************************************************************/
-/**
-*
-* This function is used for getting the Interrupt Type, Interrupt Polarity and
-* Interrupt On Any for the specified GPIO Bank pins.
-*
-* @param InstancePtr is a pointer to an XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param IntrType returns the 32 bit mask of the interrupt type.
-* 0 means Level Sensitive and 1 means Edge Sensitive.
-* @param IntrPolarity returns the 32 bit mask of the interrupt
-* polarity. 0 means Active Low or Falling Edge and 1 means
-* Active High or Rising Edge.
-* @param IntrOnAny returns the 32 bit mask of the interrupt trigger for
-* edge triggered interrupts. 0 means trigger on single edge using
-* the configured interrupt polarity and 1 means trigger on both
-* edges.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
- u32 *IntrPolarity, u32 *IntrOnAny)
-
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertVoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- *IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTTYPE_OFFSET);
-
- *IntrPolarity = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTPOL_OFFSET);
-
- *IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTANY_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* This function is used for setting the IRQ Type of a single GPIO pin.
-*
-* @param InstancePtr is a pointer to an XGpioPs instance.
-* @param Pin is the pin number whose IRQ type is to be set.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-* @param IrqType is the IRQ type for GPIO Pin. Use XGPIOPS_IRQ_TYPE_*
-* defined in xgpiops.h to specify the IRQ type.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType)
-{
- u32 IntrTypeReg;
- u32 IntrPolReg;
- u32 IntrOnAnyReg;
- u8 Bank;
- u8 PinNumber;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
- Xil_AssertVoid(IrqType <= XGPIOPS_IRQ_TYPE_LEVEL_LOW);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
-
- IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTTYPE_OFFSET);
-
- IntrPolReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTPOL_OFFSET);
-
- IntrOnAnyReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTANY_OFFSET);
-
- switch (IrqType) {
- case XGPIOPS_IRQ_TYPE_EDGE_RISING:
- IntrTypeReg |= ((u32)1 << (u32)PinNumber);
- IntrPolReg |= ((u32)1 << (u32)PinNumber);
- IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
- break;
- case XGPIOPS_IRQ_TYPE_EDGE_FALLING:
- IntrTypeReg |= ((u32)1 << (u32)PinNumber);
- IntrPolReg &= ~((u32)1 << (u32)PinNumber);
- IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
- break;
- case XGPIOPS_IRQ_TYPE_EDGE_BOTH:
- IntrTypeReg |= ((u32)1 << (u32)PinNumber);
- IntrOnAnyReg |= ((u32)1 << (u32)PinNumber);
- break;
- case XGPIOPS_IRQ_TYPE_LEVEL_HIGH:
- IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
- IntrPolReg |= ((u32)1 << (u32)PinNumber);
- break;
- case XGPIOPS_IRQ_TYPE_LEVEL_LOW:
- IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
- IntrPolReg &= ~((u32)1 << (u32)PinNumber);
- break;
- default:
- /**< Default statement is added for MISRA C compliance. */
- break;
- }
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTTYPE_OFFSET, IntrTypeReg);
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTPOL_OFFSET, IntrPolReg);
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTANY_OFFSET, IntrOnAnyReg);
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the IRQ Type of a given GPIO pin.
-*
-* @param InstancePtr is a pointer to an XGpioPs instance.
-* @param Pin is the pin number whose IRQ type is to be obtained.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*
-* @return None.
-*
-* @note Use XGPIOPS_IRQ_TYPE_* defined in xgpiops.h for the IRQ type
-* returned by this function.
-*
-*****************************************************************************/
-u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin)
-{
- u32 IntrType;
- u32 IntrPol;
- u32 IntrOnAny;
- u8 Bank;
- u8 PinNumber;
- u8 IrqType;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
-
- IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTTYPE_OFFSET) & ((u32)1 << PinNumber);
-
- if (IntrType == ((u32)1 << PinNumber)) {
-
- IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTANY_OFFSET) & ((u32)1 << PinNumber);
-
- IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
-
-
- if (IntrOnAny == ((u32)1 << PinNumber)) {
- IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH;
- } else if (IntrPol == ((u32)1 << PinNumber)) {
- IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING;
- } else {
- IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING;
- }
- } else {
-
- IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
-
- if (IntrPol == ((u32)1 << PinNumber)) {
- IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH;
- } else {
- IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW;
- }
- }
-
- return IrqType;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets the status callback function. The callback function is
-* called by the XGpioPs_IntrHandler when an interrupt occurs.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param CallBackRef is the upper layer callback reference passed back
-* when the callback function is invoked.
-* @param FuncPointer is the pointer to the callback function.
-*
-*
-* @return None.
-*
-* @note The handler is called within interrupt context, so it should do
-* its work quickly and queue potentially time-consuming work to a
-* task-level thread.
-*
-******************************************************************************/
-void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
- XGpioPs_Handler FuncPointer)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(FuncPointer != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- InstancePtr->Handler = FuncPointer;
- InstancePtr->CallBackRef = CallBackRef;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function is the interrupt handler for GPIO interrupts.It checks the
-* interrupt status registers of all the banks to determine the actual bank in
-* which an interrupt has been triggered. It then calls the upper layer callback
-* handler set by the function XGpioPs_SetBankHandler(). The callback is called
-* when an interrupt
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-*
-* @return None.
-*
-* @note This function does not save and restore the processor context
-* such that the user must provide this processing.
-*
-******************************************************************************/
-void XGpioPs_IntrHandler(const XGpioPs *InstancePtr)
-{
- u8 Bank;
- u32 IntrStatus;
- u32 IntrEnabled;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- for (Bank = 0U; Bank < InstancePtr->MaxBanks; Bank++) {
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- if(Bank == XGPIOPS_TWO) {
- continue;
- }
- } else {
- if((Bank == XGPIOPS_ONE) || (Bank == XGPIOPS_TWO)) {
- continue;
- }
- }
-#endif
- IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank);
- IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,Bank);
- if ((IntrStatus & IntrEnabled) != (u32)0) {
- XGpioPs_IntrClear(InstancePtr, Bank,
- (IntrStatus & IntrEnabled));
- InstancePtr->Handler(InstancePtr->
- CallBackRef, Bank,
- (IntrStatus & IntrEnabled));
- }
- }
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/16/d097fb535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/16/d097fb535243001d18b399c1eb9b3628
deleted file mode 100644
index 2d638da..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/16/d097fb535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,42 +0,0 @@
-
-
-
-phased_array_platform
-
-
-
- phased_array_platform
-
-
-
-
-
-
-
-
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/16/e08458545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/16/e08458545243001d18b399c1eb9b3628
deleted file mode 100644
index 2a4fff2..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/16/e08458545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,573 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xreg_cortexa9.h
-*
-* This header file contains definitions for using inline assembler code. It is
-* written specifically for the GNU, ARMCC compiler.
-*
-* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
-* with the positions of the bits within the registers.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm 10/20/09 First release
-*
-; MODIFICATION HISTORY:
-;
-; Ver Who Date Changes
-; ----- ------- -------- ---------------------------------------------------
-; 1.00a ecm/sdm 10/20/09 Initial version
-; 3.11a asa 9/17/13 Added support for neon.
-; 4.00 pkp 01/22/14 Modified return addresses for interrupt
-; handlers
-; 5.1 pkp 05/13/15 Saved the addresses of instruction causing data
-; abort and prefetch abort into DataAbortAddr and
-; PrefetchAbortAddr for further use to fix CR#854523
-; 5.4 pkp 12/03/15 Added handler for undefined exception
-;
-;
-; @note
-;
-; None.
-;
-;****************************************************************************
-
- EXPORT _vector_table
- EXPORT IRQHandler
-
- IMPORT _boot
- IMPORT _prestart
- IMPORT IRQInterrupt
- IMPORT FIQInterrupt
- IMPORT SWInterrupt
- IMPORT DataAbortInterrupt
- IMPORT PrefetchAbortInterrupt
- IMPORT UndefinedException
- IMPORT DataAbortAddr
- IMPORT PrefetchAbortAddr
- IMPORT UndefinedExceptionAddr
-
- AREA |.vectors|, CODE
- REQUIRE8 {TRUE}
- PRESERVE8 {TRUE}
- ENTRY ; define this as an entry point
-_vector_table
- B _boot
- B Undefined
- B SVCHandler
- B PrefetchAbortHandler
- B DataAbortHandler
- NOP ; Placeholder for address exception vector
- B IRQHandler
- B FIQHandler
-
-
-IRQHandler ; IRQ vector handler
-
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- vpush {d0-d7}
- vpush {d16-d31}
- vmrs r1, FPSCR
- push {r1}
- vmrs r1, FPEXC
- push {r1}
- bl IRQInterrupt ; IRQ vector
- pop {r1}
- vmsr FPEXC, r1
- pop {r1}
- vmsr FPSCR, r1
- vpop {d16-d31}
- vpop {d0-d7}
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- subs pc, lr, #4 ; adjust return
-
-
-FIQHandler ; FIQ vector handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- vpush {d0-d7}
- vpush {d16-d31}
- vmrs r1, FPSCR
- push {r1}
- vmrs r1, FPEXC
- push {r1}
-FIQLoop
- bl FIQInterrupt ; FIQ vector
- pop {r1}
- vmsr FPEXC, r1
- pop {r1}
- vmsr FPSCR, r1
- vpop {d16-d31}
- vpop {d0-d7}
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- subs pc, lr, #4 ; adjust return
-
-
-Undefined ; Undefined handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- ldr r0, =UndefinedExceptionAddr
- sub r1, lr,#4
- str r1, [r0] ; Address of instruction causing undefined exception
- bl UndefinedException ; UndefinedException: call C function here
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
-
- movs pc, lr
-
-
-SVCHandler ; SWI handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- tst r0, #0x20 ; check the T bit
- ldrneh r0, [lr,#-2] ; Thumb mode
- bicne r0, r0, #0xff00 ; Thumb mode
- ldreq r0, [lr,#-4] ; ARM mode
- biceq r0, r0, #0xff000000 ; ARM mode
- bl SWInterrupt ; SWInterrupt: call C function here
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- movs pc, lr ; adjust return
-
-DataAbortHandler ; Data Abort handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- ldr r0, =DataAbortAddr
- sub r1, lr,#8
- str r1, [r0] ;Address of instruction causing data abort
- bl DataAbortInterrupt ;DataAbortInterrupt :call C function here
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- subs pc, lr, #8 ; adjust return
-
-PrefetchAbortHandler ; Prefetch Abort handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- ldr r0, =PrefetchAbortAddr
- sub r1, lr,#4
- str r1, [r0] ;Address of instruction causing prefetch abort
- bl PrefetchAbortInterrupt ; PrefetchAbortInterrupt: call C function here
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- subs pc, lr, #4 ; adjust return
-
- END
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/17/007350585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/17/007350585243001d18b399c1eb9b3628
deleted file mode 100644
index 41c9c9c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/17/007350585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,53 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm.h
-*
-* @addtogroup a53_32_specific Cortex A53 32bit Processor Specific Include Files
-*
-* The xpseudo_asm.h includes xreg_cortexa53.h and xpseudo_asm_gcc.h.
-* The xreg_cortexa53.h file contains definitions for inline assembler code.
-* It provides inline definitions for Cortex A53 GPRs, SPRs, co-processor
-* registers and floating point registers.
-*
-* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
-* assembler instructions, available as macros. These can be very useful for
-* tasks such as setting or getting special purpose registers, synchronization,
-* or cache manipulation etc. These inline assembler instructions can be used
-* from drivers and user applications written in C.
-*
-* @{
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.2 pkp 28/05/15 First release
-*
-*
-******************************************************************************/
-#ifndef XPSEUDO_ASM_H
-#define XPSEUDO_ASM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xreg_cortexa53.h"
-#include "xpseudo_asm_gcc.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XPSEUDO_ASM_H */
-/**
-* @} End of "addtogroup a53_32_specific".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/17/901d7e595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/17/901d7e595243001d18b399c1eb9b3628
deleted file mode 100644
index 571acd9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/17/901d7e595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,112 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_exception.h
-*
-* @addtogroup microblaze_exception_apis Microblaze Exception APIs
-* @{
-*
-* The xil_exception.h file, available in the /src/microblaze folder,
-* contains Microblaze specific exception related APIs and macros. Application programs
-* can use these APIs for various exception related operations. For example, enable exception,
-* disable exception, register exception hander.
-*
-* @note To use exception related functions, xil_exception.h must be added in source code
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00 hbm 07/28/09 Initial release
-*
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
-#define XIL_EXCEPTION_H /* by using protection macros */
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/*
- * These constants are specific to Microblaze processor.
- */
-
-#define XIL_EXCEPTION_ID_FIRST 0U
-#define XIL_EXCEPTION_ID_FSL 0U
-#define XIL_EXCEPTION_ID_UNALIGNED_ACCESS 1U
-#define XIL_EXCEPTION_ID_ILLEGAL_OPCODE 2U
-#define XIL_EXCEPTION_ID_M_AXI_I_EXCEPTION 3U
-#define XIL_EXCEPTION_ID_IPLB_EXCEPTION 3U
-#define XIL_EXCEPTION_ID_M_AXI_D_EXCEPTION 4U
-#define XIL_EXCEPTION_ID_DPLB_EXCEPTION 4U
-#define XIL_EXCEPTION_ID_DIV_BY_ZERO 5U
-#define XIL_EXCEPTION_ID_FPU 6U
-#define XIL_EXCEPTION_ID_STACK_VIOLATION 7U
-#define XIL_EXCEPTION_ID_MMU 7U
-#define XIL_EXCEPTION_ID_LAST XIL_EXCEPTION_ID_MMU
-
-/*
- * XIL_EXCEPTION_ID_INT is defined for all processors, but with different value.
- */
-#define XIL_EXCEPTION_ID_INT 16U /**
- * exception ID for interrupt
- */
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef is the exception handler function.
- */
-typedef void (*Xil_ExceptionHandler)(void *Data);
-
-/**
- * This data type defines an interrupt handler for a device.
- * The argument points to the instance of the component
- */
-typedef void (*XInterruptHandler) (void *InstancePtr);
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-extern void Xil_ExceptionRegisterHandler(u32 Id,
- Xil_ExceptionHandler Handler,
- void *Data);
-
-extern void Xil_ExceptionRemoveHandler(u32 Id);
-
-extern void Xil_ExceptionInit(void);
-extern void Xil_ExceptionEnable(void);
-extern void Xil_ExceptionDisable(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-/**
- *@endcond
- */
-
-/**
-* @} End of "addtogroup microblaze_exception_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/17/e15889545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/17/e15889545243001d18b399c1eb9b3628
deleted file mode 100644
index b42d32b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/17/e15889545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,68 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xdevcfg_sinit.c
-* @addtogroup devcfg_v3_7
-* @{
-*
-* This file contains method for static initialization (compile-time) of the
-* driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 3.5 ms 08/07/17 Fixed compilation warnings.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xdevcfg.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-* Lookup the device configuration based on the unique device ID. The table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId is the unique device ID of the device being looked up.
-*
-* @return A pointer to the configuration table entry corresponding to the
-* given device ID, or NULL if no match is found.
-*
-* @note None.
-*
-******************************************************************************/
-XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId)
-{
- extern XDcfg_Config XDcfg_ConfigTable[];
- XDcfg_Config *CfgPtr = NULL;
- u32 Index;
-
- for (Index = 0U; Index < XPAR_XDCFG_NUM_INSTANCES; Index++) {
- if (XDcfg_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XDcfg_ConfigTable[Index];
- break;
- }
- }
-
- return (CfgPtr);
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/18/5007eb515243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/18/5007eb515243001d18b399c1eb9b3628
deleted file mode 100644
index 28aaa33..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/18/5007eb515243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,29 +0,0 @@
-
-
- phased_array_system
-
-
- phased_array
-
-
-
- org.eclipse.cdt.managedbuilder.core.genmakebuilder
-
-
-
-
- org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
- full,incremental,
-
-
-
-
-
- com.xilinx.sdx.system.core.embedded
- com.xilinx.sdx.system.systemprojectnature
- org.eclipse.cdt.core.cnature
- org.eclipse.cdt.managedbuilder.core.managedBuildNature
- org.eclipse.cdt.core.ccnature
- org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/18/50b01f565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/18/50b01f565243001d18b399c1eb9b3628
deleted file mode 100644
index 3438d96..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/18/50b01f565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1 +0,0 @@
-collect (PROJECT_LIB_HEADERS xparameters_ps.h)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/18/a00817575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/18/a00817575243001d18b399c1eb9b3628
deleted file mode 100644
index a22510e..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/18/a00817575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1649 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/******************************************************************************/
-/**
- * @file xusbps_endpoint.c
-* @addtogroup usbps_v2_7
-* @{
- *
- * Endpoint specific function implementations.
- *
- * @note None.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- --------------------------------------------------------
- * 1.00a jz 10/10/10 First release
- * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet
- * handling.
- * 1.04a nm 11/02/12 Fixed CR#683931. Mult bits are set properly in dQH.
- * 2.00a kpc 04/03/14 Fixed CR#777763. Updated the macro names
- * 2.1 kpc 04/28/14 Added XUsbPs_EpBufferSendWithZLT api and merged common
- * code to XUsbPs_EpQueueRequest.
- * 2.3 bss 01/19/16 Modified XUsbPs_EpQueueRequest function to fix CR#873972
- * (moving of dTD Head/Tail Pointers)and CR#873974(invalidate
- * Caches After Buffer Receive in Endpoint Buffer Handler...)
- * 2.5 pm 02/20/20 Added ISO endpoint support.
- *
- ******************************************************************************/
-
-/***************************** Include Files **********************************/
-
-#include /* for bzero() */
-#include
-
-#include "xusbps.h"
-#include "xusbps_endpoint.h"
-
-/************************** Constant Definitions ******************************/
-
-/**************************** Type Definitions ********************************/
-
-/************************** Variable Definitions ******************************/
-
-/************************** Function Prototypes ******************************/
-
-static void XUsbPs_EpListInit(XUsbPs_DeviceConfig *DevCfgPtr);
-static void XUsbPs_dQHInit(XUsbPs_DeviceConfig *DevCfgPtr);
-static int XUsbPs_dTDInit(XUsbPs_DeviceConfig *DevCfgPtr);
-static int XUsbPs_dTDAttachBuffer(XUsbPs_dTD *dTDPtr,
- const u8 *BufferPtr, u32 BufferLen);
-
-static void XUsbPs_dQHSetMaxPacketLenISO(XUsbPs_dQH *dQHPtr, u32 Len);
-
-/* Functions to reconfigure endpoint upon host's set alternate interface
- * request.
- */
-static void XUsbPs_dQHReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
- int EpNum, unsigned short NewDirection);
-static int XUsbPs_dTDReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
- int EpNum, unsigned short NewDirection);
-static int XUsbPs_EpQueueRequest(XUsbPs *InstancePtr, u8 EpNum,
- const u8 *BufferPtr, u32 BufferLen, u8 ReqZero);
-
-/******************************* Functions ************************************/
-
-/*****************************************************************************/
-/**
- *
- * This function configures the DEVICE side of the controller. The caller needs
- * to pass in the desired configuration (e.g. number of endpoints) and a
- * DMAable buffer that will hold the Queue Head List and the Transfer
- * Descriptors. The required size for this buffer can be obtained by the caller
- * using the: XUsbPs_DeviceMemRequired() macro.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- * @param CfgPtr is a pointer to the configuration structure that contains
- * the desired DEVICE side configuration.
- *
- * @return
- * - XST_SUCCESS: The operation completed successfully.
- * - XST_FAILURE: An error occurred.
- *
- * @note
- * The caller may configure the controller for both, DEVICE and
- * HOST side.
- *
- ******************************************************************************/
-int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr,
- const XUsbPs_DeviceConfig *CfgPtr)
-{
- int Status;
- u32 ModeValue = 0x0;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(CfgPtr != NULL);
-
- /* Copy the configuration data over into the local instance structure */
- InstancePtr->DeviceConfig = *CfgPtr;
-
-
- /* Align the buffer to a 2048 byte (XUSBPS_dQH_BASE_ALIGN) boundary.*/
- InstancePtr->DeviceConfig.PhysAligned =
- (InstancePtr->DeviceConfig.DMAMemPhys +
- XUSBPS_dQH_BASE_ALIGN) &
- ~(XUSBPS_dQH_BASE_ALIGN -1);
-
- /* Initialize the endpoint pointer list data structure. */
- XUsbPs_EpListInit(&InstancePtr->DeviceConfig);
-
-
- /* Initialize the Queue Head structures in DMA memory. */
- XUsbPs_dQHInit(&InstancePtr->DeviceConfig);
-
-
- /* Initialize the Transfer Descriptors in DMA memory.*/
- Status = XUsbPs_dTDInit(&InstancePtr->DeviceConfig);
- if (XST_SUCCESS != Status) {
- return XST_FAILURE;
- }
-
- /* Changing the DEVICE mode requires a controller RESET. */
- if (XST_SUCCESS != XUsbPs_Reset(InstancePtr)) {
- return XST_FAILURE;
- }
-
- /* Set the Queue Head List address. */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPLISTADDR_OFFSET,
- InstancePtr->DeviceConfig.PhysAligned);
-
- /* Set the USB mode register to configure DEVICE mode.
- *
- * XUSBPS_MODE_SLOM_MASK note:
- * Disable Setup Lockout. Setup Lockout is not required as we
- * will be using the tripwire mechanism when handling setup
- * packets.
- */
- ModeValue = XUSBPS_MODE_CM_DEVICE_MASK | XUSBPS_MODE_SLOM_MASK;
-
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_MODE_OFFSET, ModeValue);
-
- XUsbPs_SetBits(InstancePtr, XUSBPS_OTGCSR_OFFSET,
- XUSBPS_OTGSC_OT_MASK);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-* This function sends a given data buffer.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param EpNum is the number of the endpoint to receive data from.
-* @param BufferPtr is a pointer to the buffer to send.
-* @param BufferLen is the Buffer length.
-*
-* @return
-* - XST_SUCCESS: The operation completed successfully.
-* - XST_FAILURE: An error occurred.
-* - XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB).
-* - XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available.
-*
-******************************************************************************/
-int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum,
- const u8 *BufferPtr, u32 BufferLen)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
-
- return XUsbPs_EpQueueRequest(InstancePtr, EpNum, BufferPtr,
- BufferLen, FALSE);
-}
-
-/*****************************************************************************/
-/**
-* This function sends a given data buffer and also zero length packet if the
-* Bufferlen is in multiples of endpoint max packet size.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param EpNum is the number of the endpoint to receive data from.
-* @param BufferPtr is a pointer to the buffer to send.
-* @param BufferLen is the Buffer length.
-*
-* @return
-* - XST_SUCCESS: The operation completed successfully.
-* - XST_FAILURE: An error occurred.
-* - XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB).
-* - XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available.
-*
-******************************************************************************/
-int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum,
- const u8 *BufferPtr, u32 BufferLen)
-{
- u8 ReqZero = FALSE;
- XUsbPs_EpSetup *Ep;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
-
- Ep = &InstancePtr->DeviceConfig.EpCfg[EpNum].In;
-
- if ((BufferLen >= Ep->MaxPacketSize) &&
- (BufferLen % Ep->MaxPacketSize == 0)) {
- ReqZero = TRUE;
- }
-
- return XUsbPs_EpQueueRequest(InstancePtr, EpNum, BufferPtr,
- BufferLen, ReqZero);
-}
-
-/*****************************************************************************/
-/**
-* This function sends a given data buffer and also sends ZLT packet if it is
-* requested.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param EpNum is the number of the endpoint to receive data from.
-* @param BufferPtr is a pointer to the buffer to send.
-* @param BufferLen is the Buffer length.
-* @param ReqZero is the
-*
-* @return
-* - XST_SUCCESS: The operation completed successfully.
-* - XST_FAILURE: An error occurred.
-* - XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB).
-* - XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available.
-*
-******************************************************************************/
-static int XUsbPs_EpQueueRequest(XUsbPs *InstancePtr, u8 EpNum,
- const u8 *BufferPtr, u32 BufferLen, u8 ReqZero)
-{
- int Status;
- u32 Token;
- XUsbPs_EpIn *Ep;
- XUsbPs_dTD *DescPtr;
- u32 Length;
- u32 EpType;
- u32 Multo = 0;
- u32 PipeEmpty = 1;
- u32 Mask = 0x00010000;
- u32 BitMask = Mask << EpNum;
- u32 RegValue;
- u32 Temp;
- u32 exit = 1;
-
-
- /* Locate the next available buffer in the ring. A buffer is available
- * if its descriptor is not active.
- */
- Ep = &InstancePtr->DeviceConfig.Ep[EpNum].In;
- EpType = InstancePtr->DeviceConfig.EpCfg[EpNum].In.Type;
-
- Xil_DCacheFlushRange((unsigned int)BufferPtr, BufferLen);
-
- if(Ep->dTDTail != Ep->dTDHead) {
- PipeEmpty = 0;
- }
- XUsbPs_dTDInvalidateCache(Ep->dTDHead);
-
- /* Tell the caller if we do not have any descriptors available. */
- if (XUsbPs_dTDIsActive(Ep->dTDHead)) {
- return XST_USB_NO_DESC_AVAILABLE;
- }
-
- /* Remember the current head. */
- DescPtr = Ep->dTDHead;
-
- Ep->RequestedBytes = BufferLen;
- Ep->BytesTxed = 0;
- Ep->BufferPtr = (u8 *)BufferPtr;
-
- do {
-
- /* Tell the caller if we do not have any descriptors available. */
- if (XUsbPs_dTDIsActive(Ep->dTDHead)) {
- return XST_USB_NO_DESC_AVAILABLE;
- }
-
- Length = (BufferLen > XUSBPS_dTD_BUF_MAX_SIZE) ? XUSBPS_dTD_BUF_MAX_SIZE : BufferLen;
- /* Attach the provided buffer to the current descriptor.*/
- Status = XUsbPs_dTDAttachBuffer(Ep->dTDHead, BufferPtr, Length);
- if (XST_SUCCESS != Status) {
- return XST_FAILURE;
- }
- BufferLen -= Length;
- BufferPtr += Length;
- Ep->BytesTxed += Length;
-
- if (EpType == XUSBPS_EP_TYPE_ISOCHRONOUS) {
- Multo = BufferLen /
- InstancePtr->
- DeviceConfig.EpCfg[EpNum].Out.MaxPacketSize;
- if (BufferLen == 0 ||
- (BufferLen %
- InstancePtr->
- DeviceConfig.EpCfg[EpNum].
- Out.MaxPacketSize))
- Multo++;
-
- XUsbPs_dTDSetMultO(Ep->dTDHead, (Multo << 10));
- }
-
- XUsbPs_dTDSetActive(Ep->dTDHead);
- if (BufferLen == 0 && (ReqZero == FALSE)) {
- XUsbPs_dTDSetIOC(Ep->dTDHead);
- exit = 0;
- }
- XUsbPs_dTDClrTerminate(Ep->dTDHead);
- XUsbPs_dTDFlushCache(Ep->dTDHead);
-
- /* Advance the head descriptor pointer to the next descriptor. */
- Ep->dTDHead = XUsbPs_dTDGetNLP(Ep->dTDHead);
- /* Terminate the next descriptor and flush the cache.*/
- XUsbPs_dTDInvalidateCache(Ep->dTDHead);
-
- if (ReqZero && BufferLen == 0) {
- ReqZero = FALSE;
- }
-
- } while(BufferLen || exit);
-
- XUsbPs_dTDSetTerminate(Ep->dTDHead);
- XUsbPs_dTDFlushCache(Ep->dTDHead);
-
- if(!PipeEmpty) {
- /* Read the endpoint prime register. */
- RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_EPPRIME_OFFSET);
- if(RegValue & BitMask) {
- return XST_SUCCESS;
- }
-
- do {
- RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET);
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
- RegValue | XUSBPS_CMD_ATDTW_MASK);
- Temp = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_EPRDY_OFFSET)
- & BitMask;
- } while(!(XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET) &
- XUSBPS_CMD_ATDTW_MASK));
-
- RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET);
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
- RegValue & ~XUSBPS_CMD_ATDTW_MASK);
-
- if(Temp) {
- return XST_SUCCESS;
- }
- }
-
- /* Check, if the DMA engine is still running. If it is running, we do
- * not clear Queue Head fields.
- *
- * Same cache rule as for the Transfer Descriptor applies for the Queue
- * Head.
- */
- XUsbPs_dQHInvalidateCache(Ep->dQH);
- /* Add the dTD to the dQH */
- XUsbPs_WritedQH(Ep->dQH, XUSBPS_dQHdTDNLP, DescPtr);
- Token = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHdTDTOKEN);
- Token &= ~(XUSBPS_dTDTOKEN_ACTIVE_MASK | XUSBPS_dTDTOKEN_HALT_MASK);
- XUsbPs_WritedQH(Ep->dQH, XUSBPS_dQHdTDTOKEN, Token);
-
- XUsbPs_dQHFlushCache(Ep->dQH);
-
- Status = XUsbPs_EpPrime(InstancePtr, EpNum, XUSBPS_EP_DIRECTION_IN);
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
- * This function receives a data buffer from the endpoint of the given endpoint
- * number and pass it to the application.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- * @param EpNum is the number of the endpoint to receive data from.
- * @param BufferLen is holding the buffer length.
- *
- * @return None.
- *
- * @note None.
- *
- ******************************************************************************/
-void XUsbPs_EpGetData(XUsbPs *InstancePtr, u8 EpNum, u32 BufferLen)
-{
- XUsbPs_EpOut *Ep;
- XUsbPs_EpSetup *EpSetup;
- u8 *DataBuff;
- u32 Handle;
- u32 length = 0;
- u32 InavalidateLen = 0;
-
- /* The buffer is not active which means that it has been processed by
- * the DMA engine and contains valid data.
- */
- Ep = &InstancePtr->DeviceConfig.Ep[EpNum].Out;
- EpSetup = &InstancePtr->DeviceConfig.EpCfg[EpNum].Out;
-
- /* Use the buffer pointer stored in the "user data" field of the
- * Transfer Descriptor.
- */
-
- do {
- XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
-
- DataBuff = (u8 *) XUsbPs_ReaddTD(Ep->dTDCurr,
- XUSBPS_dTDUSERDATA);
-
- length = EpSetup->BufSize -
- XUsbPs_dTDGetTransferLen(Ep->dTDCurr);
-
- if (length > 0) {
- BufferLen = length;
- } else {
- BufferLen = 0;
- }
-
- /* Invalidate the Buffer Pointer */
- InavalidateLen = BufferLen;
- if (BufferLen % 32) {
- InavalidateLen = (BufferLen/32) * 32 + 32;
- }
-
- Xil_DCacheInvalidateRange((unsigned int)DataBuff,
- InavalidateLen);
-
- memcpy(Ep->BufferPtr, DataBuff, BufferLen);
-
- Ep->BytesTxed += BufferLen;
- Ep->BufferPtr += BufferLen;
-
- Handle = (u32) Ep->dTDCurr;
-
- /* Reset the descriptor's BufferPointer0 and Transfer Length
- * fields to their original value. Note that we can not yet
- * re-activate the descriptor as the caller will be using the
- * attached buffer. Once the caller releases the buffer by
- * calling XUsbPs_EpBufferRelease(),
- * we can re-activate the descriptor.
- */
- XUsbPs_WritedTD(Ep->dTDCurr, XUSBPS_dTDBPTR0, DataBuff);
- XUsbPs_dTDSetTransferLen(Ep->dTDCurr, EpSetup->BufSize);
-
- XUsbPs_dTDFlushCache(Ep->dTDCurr);
-
- XUsbPs_EpBufferRelease(Handle);
-
- Ep->dTDCurr = XUsbPs_dTDGetNLP(Ep->dTDCurr);
- XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
-
- /* Either Host sent exact requested length or more than that
- * or lesser data.
- */
- if ((Ep->RequestedBytes <= Ep->BytesTxed) ||
- (Ep->BytesTxed % EpSetup->MaxPacketSize)) {
- Ep->MemAlloted = 0;
- if (Ep->HandlerIsoFunc) {
- Ep->HandlerIsoFunc(Ep->HandlerRef,
- Ep->RequestedBytes,
- Ep->BytesTxed);
- }
-
- break;
- }
- } while (!XUsbPs_dTDIsActive(Ep->dTDCurr));
-
-}
-
-/*****************************************************************************/
-/**
- * This function receives a data buffer from the endpoint of the given endpoint
- * number.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- * @param EpNum is the number of the endpoint to receive data from.
- * @param BufferPtr (OUT param) is a pointer to the buffer pointer to hold
- * the reference of the data buffer.
- * @param BufferLenPtr (OUT param) is a pointer to the integer that will
- * hold the buffer length.
- * @param Handle is the opaque handle to be used when the buffer is
- * released.
- *
- * @return
- * - XST_SUCCESS: The operation completed successfully.
- * - XST_FAILURE: An error occurred.
- * - XST_USB_NO_BUF: No buffer available.
- *
- * @note
- * After handling the data in the buffer, the user MUST release
- * the buffer using the Handle by calling the
- * XUsbPs_EpBufferRelease() function.
- *
- ******************************************************************************/
-int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
- u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle)
-{
- XUsbPs_EpOut *Ep;
- XUsbPs_EpSetup *EpSetup;
- u32 length = 0;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(BufferPtr != NULL);
- Xil_AssertNonvoid(BufferLenPtr != NULL);
- Xil_AssertNonvoid(Handle != NULL);
- Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
-
- /* Locate the next available buffer in the ring. A buffer is available
- * if its descriptor is not active.
- */
- Ep = &InstancePtr->DeviceConfig.Ep[EpNum].Out;
-
- XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
-
- if (XUsbPs_dTDIsActive(Ep->dTDCurr)) {
- return XST_USB_NO_BUF;
- }
-
- /* The buffer is not active which means that it has been processed by
- * the DMA engine and contains valid data.
- */
- EpSetup = &InstancePtr->DeviceConfig.EpCfg[EpNum].Out;
-
-
- /* Use the buffer pointer stored in the "user data" field of the
- * Transfer Descriptor.
- */
- *BufferPtr = (u8 *) XUsbPs_ReaddTD(Ep->dTDCurr,
- XUSBPS_dTDUSERDATA);
-
- length = EpSetup->BufSize -
- XUsbPs_dTDGetTransferLen(Ep->dTDCurr);
-
- if(length > 0) {
- *BufferLenPtr = length;
- }else {
- *BufferLenPtr = 0;
- }
-
- *Handle = (u32) Ep->dTDCurr;
-
-
- /* Reset the descriptor's BufferPointer0 and Transfer Length fields to
- * their original value. Note that we can not yet re-activate the
- * descriptor as the caller will be using the attached buffer. Once the
- * caller releases the buffer by calling XUsbPs_EpBufferRelease(), we
- * can re-activate the descriptor.
- */
- XUsbPs_WritedTD(Ep->dTDCurr, XUSBPS_dTDBPTR0, *BufferPtr);
- XUsbPs_dTDSetTransferLen(Ep->dTDCurr, EpSetup->BufSize);
-
- XUsbPs_dTDFlushCache(Ep->dTDCurr);
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-* This function returns a previously received data buffer to the driver.
-*
-* @param Handle is a pointer to the buffer that is returned.
-*
-* @return None.
-*
-******************************************************************************/
-void XUsbPs_EpBufferRelease(u32 Handle)
-{
- XUsbPs_dTD *dTDPtr;
-
- /* Perform sanity check on Handle.*/
- Xil_AssertVoid((0 != Handle) && (0 == (Handle % XUSBPS_dTD_ALIGN)));
-
- /* Activate the descriptor and clear the Terminate bit. Make sure to do
- * the proper cache handling.
- */
- dTDPtr = (XUsbPs_dTD *) Handle;
-
- XUsbPs_dTDInvalidateCache(dTDPtr);
-
- XUsbPs_dTDClrTerminate(dTDPtr);
- XUsbPs_dTDSetActive(dTDPtr);
- XUsbPs_dTDSetIOC(dTDPtr);
-
- XUsbPs_dTDFlushCache(dTDPtr);
-
-}
-
-/*****************************************************************************/
-/**
- * This function receives a data buffer from the endpoint of the given endpoint
- * number.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- * @param EpNum is the number of the endpoint to receive data from.
- * @param BufferPtr (OUT param) is a pointer to the buffer pointer to hold
- * the reference of the data buffer.
- * @param BufferLen (OUT param) is a pointer to the integer that will
- * hold the buffer length.
- *
- * @return
- * - XST_SUCCESS: The operation completed successfully.
- * - XST_FAILURE: An error occurred.
- * - XST_USB_NO_BUF: No buffer available.
- *
- * @note
- *
- ******************************************************************************/
-s32 XUsbPs_EpDataBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
- u8 *BufferPtr, u32 BufferLen)
-{
- XUsbPs_EpOut *Ep;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(BufferPtr != NULL);
- Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
-
- Ep = &InstancePtr->DeviceConfig.Ep[EpNum].Out;
-
- Ep->RequestedBytes = BufferLen;
- Ep->BytesTxed = 0;
- Ep->BufferPtr = BufferPtr;
- Ep->MemAlloted = 1;
-
- XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
-
- /* Locate the next available buffer in the ring. A buffer is available
- * if its descriptor is not active.
- */
- if (XUsbPs_dTDIsActive(Ep->dTDCurr)) {
- return XST_USB_NO_BUF;
- }
- XUsbPs_EpGetData(InstancePtr, EpNum, BufferLen);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * This function sets the handler for endpoint events.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- * @param EpNum is the number of the endpoint to receive data from.
- * @param Direction is the direction of the endpoint (bitfield):
- * - XUSBPS_EP_DIRECTION_OUT
- * - XUSBPS_EP_DIRECTION_IN
- * @param CallBackFunc is the Handler callback function.
- * Can be NULL if the user wants to disable the handler entry.
- * @param CallBackRef is the user definable data pointer that will be
- * passed back if the handler is called. May be NULL.
- *
- * @return
- * - XST_SUCCESS: The operation completed successfully.
- * - XST_FAILURE: An error occurred.
- * - XST_INVALID_PARAM: Invalid parameter passed.
- *
- * @note
- * The user can disable a handler by setting the callback function
- * pointer to NULL.
- *
- ******************************************************************************/
-int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
- XUsbPs_EpHandlerFunc CallBackFunc,
- void *CallBackRef)
-{
- XUsbPs_Endpoint *Ep;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(CallBackFunc != NULL);
- Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
-
- Ep = &InstancePtr->DeviceConfig.Ep[EpNum];
-
- if(Direction & XUSBPS_EP_DIRECTION_OUT) {
- Ep->Out.HandlerFunc = CallBackFunc;
- Ep->Out.HandlerRef = CallBackRef;
- }
-
- if(Direction & XUSBPS_EP_DIRECTION_IN) {
- Ep->In.HandlerFunc = CallBackFunc;
- Ep->In.HandlerRef = CallBackRef;
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * This function sets the handler for ISO endpoint events.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- * @param EpNum is the number of the endpoint to receive data from.
- * @param Direction is the direction of the endpoint (bitfield):
- * - XUSBPS_EP_DIRECTION_OUT
- * - XUSBPS_EP_DIRECTION_IN
- * @param CallBackFunc is the Handler callback function.
- * Can be NULL if the user wants to disable the handler entry.
- *
- * @return
- * - XST_SUCCESS: The operation completed successfully.
- * - XST_FAILURE: An error occurred.
- * - XST_INVALID_PARAM: Invalid parameter passed.
- *
- * @note
- * The user can disable a handler by setting the callback function
- * pointer to NULL.
- *
- ******************************************************************************/
-s32 XUsbPs_EpSetIsoHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
- XUsbPs_EpIsoHandlerFunc CallBackFunc)
-{
- XUsbPs_Endpoint *Ep;
- void *CallBackRef = (void *) InstancePtr->AppData;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(CallBackFunc != NULL);
- Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
-
- Ep = &InstancePtr->DeviceConfig.Ep[EpNum];
-
- if (Direction & XUSBPS_EP_DIRECTION_OUT) {
- Ep->Out.HandlerIsoFunc = CallBackFunc;
- Ep->Out.HandlerRef = CallBackRef;
- }
-
- if (Direction & XUSBPS_EP_DIRECTION_IN) {
- Ep->In.HandlerIsoFunc = CallBackFunc;
- Ep->In.HandlerRef = CallBackRef;
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-* This function primes an endpoint.
-*
-* @param InstancePtr is pointer to the XUsbPs instance.
-* @param EpNum is the number of the endpoint to receive data from.
-* @param Direction is the direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @return
-* - XST_SUCCESS: The operation completed successfully.
-* - XST_FAILURE: An error occurred.
-* - XST_INVALID_PARAM: Invalid parameter passed.
-*
-* @note None.
-*
-******************************************************************************/
-int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction)
-{
- u32 Mask;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
-
- /* Get the right bit mask for the endpoint direction. */
- switch (Direction) {
-
- case XUSBPS_EP_DIRECTION_OUT:
- Mask = 0x00000001;
- break;
-
- case XUSBPS_EP_DIRECTION_IN:
- Mask = 0x00010000;
- break;
-
- default:
- return XST_INVALID_PARAM;
- }
-
- /* Write the endpoint prime register. */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPPRIME_OFFSET, Mask << EpNum);
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-* This function extracts the Setup Data from a given endpoint.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is the number of the endpoint to receive data from.
-* @param SetupDataPtr is a pointer to the setup data structure to be
-* filled.
-*
-* @return
-* - XST_SUCCESS: The operation completed successfully.
-* - XST_FAILURE: An error occurred.
-*
-* @note None.
-******************************************************************************/
-int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum,
- XUsbPs_SetupData *SetupDataPtr)
-{
- XUsbPs_EpOut *Ep;
-
- u32 Data[2];
- u8 *p;
-
- int Timeout;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(SetupDataPtr != NULL);
- Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
-
- Ep = &InstancePtr->DeviceConfig.Ep[EpNum].Out;
-
-
- /* Get the data from the Queue Heads Setup buffer into local variables
- * so we can extract the setup data values.
- */
- do {
- /* Arm the tripwire. The tripwire will tell us if a new setup
- * packet arrived (in which case the tripwire bit will be
- * cleared) while we were reading the buffer. If a new setup
- * packet arrived the buffer is corrupted and we continue
- * reading.
- */
- XUsbPs_SetSetupTripwire(InstancePtr);
-
- XUsbPs_dQHInvalidateCache(Ep->dQH);
-
- Data[0] = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHSUB0);
- Data[1] = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHSUB1);
- } while (FALSE == XUsbPs_SetupTripwireIsSet(InstancePtr));
-
- /* Clear the pending endpoint setup stat bit.
- */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPSTAT_OFFSET, 1 << EpNum);
-
- /* Clear the Tripwire bit and continue.
- */
- XUsbPs_ClrSetupTripwire(InstancePtr);
-
-
- /* Data in the setup buffer is being converted by the core to big
- * endian format. We have to take care of proper byte swapping when
- * reading the setup data values.
- *
- * Need to check if there is a smarter way to do this and take the
- * processor/memory-controller endianness into account?
- */
- p = (u8 *) Data;
-
- SetupDataPtr->bmRequestType = p[0];
- SetupDataPtr->bRequest = p[1];
- SetupDataPtr->wValue = (p[3] << 8) | p[2];
- SetupDataPtr->wIndex = (p[5] << 8) | p[4];
- SetupDataPtr->wLength = (p[7] << 8) | p[6];
-
- /* Before we leave we need to make sure that the endpoint setup bit has
- * cleared. It needs to be 0 before the endpoint can be re-primed.
- *
- * Note: According to the documentation this endpoint setup bit should
- * clear within 1-2us after it has been written above. This means that
- * we should never catch it being 1 here. However, we still need to
- * poll it to make sure. Just in case, we use a counter 'Timeout' so we
- * won't hang here if the bit is stuck for some reason.
- */
- Timeout = XUSBPS_TIMEOUT_COUNTER;
- while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPSTAT_OFFSET) &
- (1 << EpNum)) && --Timeout) {
- /* NOP */
- }
- if (0 == Timeout) {
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This function initializes the endpoint pointer data structure.
-*
-* The function sets up the local data structure with the aligned addresses for
-* the Queue Head and Transfer Descriptors.
-*
-* @param DevCfgPtr is pointer to the XUsbPs DEVICE configuration
-* structure.
-*
-* @return none
-*
-* @note
-* Endpoints of type XUSBPS_EP_TYPE_NONE are not used in the
-* system. Therefore no memory is reserved for them.
-*
-******************************************************************************/
-static void XUsbPs_EpListInit(XUsbPs_DeviceConfig *DevCfgPtr)
-{
- int EpNum;
- u8 *p;
-
- XUsbPs_Endpoint *Ep;
- XUsbPs_EpConfig *EpCfg;
-
- /* Set up the XUsbPs_Endpoint array. This array is used to define the
- * location of the Queue Head list and the Transfer Descriptors in the
- * block of DMA memory that has been passed into the driver.
- *
- * 'p' is used to set the pointers in the local data structure.
- * Initially 'p' is pointed to the beginning of the DMAable memory
- * block. As pointers are assigned, 'p' is incremented by the size of
- * the respective object.
- */
- Ep = DevCfgPtr->Ep;
- EpCfg = DevCfgPtr->EpCfg;
-
- /* Start off with 'p' pointing to the (aligned) beginning of the DMA
- * buffer.
- */
- p = (u8 *) DevCfgPtr->PhysAligned;
-
-
- /* Initialize the Queue Head pointer list.
- *
- * Each endpoint has two Queue Heads. One for the OUT direction and one
- * for the IN direction. An OUT Queue Head is always followed by an IN
- * Queue Head.
- *
- * Queue Head alignment is XUSBPS_dQH_ALIGN.
- *
- * Note that we have to reserve space here for unused endpoints.
- */
- for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
- /* OUT Queue Head */
- Ep[EpNum].Out.dQH = (XUsbPs_dQH *) p;
- p += XUSBPS_dQH_ALIGN;
-
- /* IN Queue Head */
- Ep[EpNum].In.dQH = (XUsbPs_dQH *) p;
- p += XUSBPS_dQH_ALIGN;
- }
-
-
- /* 'p' now points to the first address after the Queue Head list. The
- * Transfer Descriptors start here.
- *
- * Each endpoint has a variable number of Transfer Descriptors
- * depending on user configuration.
- *
- * Transfer Descriptor alignment is XUSBPS_dTD_ALIGN.
- */
- for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
- /* OUT Descriptors.
- */
- if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
- Ep[EpNum].Out.dTDs = (XUsbPs_dTD *) p;
- Ep[EpNum].Out.dTDCurr = (XUsbPs_dTD *) p;
- p += XUSBPS_dTD_ALIGN * EpCfg[EpNum].Out.NumBufs;
- }
-
- /* IN Descriptors.
- */
- if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) {
- Ep[EpNum].In.dTDs = (XUsbPs_dTD *) p;
- Ep[EpNum].In.dTDHead = (XUsbPs_dTD *) p;
- Ep[EpNum].In.dTDTail = (XUsbPs_dTD *) p;
- p += XUSBPS_dTD_ALIGN * EpCfg[EpNum].In.NumBufs;
- }
- }
-
-
- /* 'p' now points to the first address after the Transfer Descriptors.
- * The data buffers for the OUT Transfer Descriptors start here.
- *
- * Note that IN (TX) Transfer Descriptors are not assigned buffers at
- * this point. Buffers will be assigned when the user calls the send()
- * function.
- */
- for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
-
- if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
- /* If BufSize for this endpoint is set to 0 it means
- * that we do not need to attach a buffer to this
- * descriptor. We also initialize it's buffer pointer
- * to NULL.
- */
- if (0 == EpCfg[EpNum].Out.BufSize) {
- Ep[EpNum].Out.dTDBufs = NULL;
- continue;
- }
-
- Ep[EpNum].Out.dTDBufs = p;
- p += EpCfg[EpNum].Out.BufSize * EpCfg[EpNum].Out.NumBufs;
- }
- }
-
-
- /* Initialize the endpoint event handlers to NULL.
- */
- for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
- Ep[EpNum].Out.HandlerFunc = NULL;
- Ep[EpNum].In.HandlerFunc = NULL;
- Ep[EpNum].Out.HandlerIsoFunc = NULL;
- Ep[EpNum].In.HandlerIsoFunc = NULL;
- }
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This function initializes the Queue Head List in memory.
-*
-* @param DevCfgPtr is a pointer to the XUsbPs DEVICE configuration
-* structure.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-static void XUsbPs_dQHInit(XUsbPs_DeviceConfig *DevCfgPtr)
-{
- int EpNum;
-
- XUsbPs_Endpoint *Ep;
- XUsbPs_EpConfig *EpCfg;
-
- /* Setup pointers for simpler access. */
- Ep = DevCfgPtr->Ep;
- EpCfg = DevCfgPtr->EpCfg;
-
-
- /* Go through the list of Queue Head entries and:
- *
- * - Set Transfer Descriptor addresses
- * - Set Maximum Packet Size
- * - Disable Zero Length Termination (ZLT) for non-isochronous transfers
- * - Enable Interrupt On Setup (IOS)
- *
- */
- for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
-
- /* OUT Queue Heads.*/
- if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
- XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
- XUSBPS_dQHCPTR, Ep[EpNum].Out.dTDs);
-
- /* For isochronous, ep max packet size translates to different
- * values in queue head than other types.
- * Also enable ZLT for isochronous.
- */
- if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].Out.Type) {
- XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].Out.dQH,
- EpCfg[EpNum].Out.MaxPacketSize);
- XUsbPs_dQHEnableZLT(Ep[EpNum].Out.dQH);
- }else {
- XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].Out.dQH,
- EpCfg[EpNum].Out.MaxPacketSize);
- XUsbPs_dQHDisableZLT(Ep[EpNum].Out.dQH);
- }
-
- /* Only control OUT needs this */
- if(XUSBPS_EP_TYPE_CONTROL == EpCfg[EpNum].Out.Type) {
- XUsbPs_dQHSetIOS(Ep[EpNum].Out.dQH);
- }
-
- /* Set up the overlay next dTD pointer. */
- XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
- XUSBPS_dQHdTDNLP, Ep[EpNum].Out.dTDs);
-
- XUsbPs_dQHFlushCache(Ep[EpNum].Out.dQH);
- }
-
-
- /* IN Queue Heads. */
- if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) {
- XUsbPs_WritedQH(Ep[EpNum].In.dQH,
- XUSBPS_dQHCPTR, Ep[EpNum].In.dTDs);
-
-
- /* Isochronous ep packet size can be larger than 1024.*/
- if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].In.Type) {
- XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].In.dQH,
- EpCfg[EpNum].In.MaxPacketSize);
- XUsbPs_dQHEnableZLT(Ep[EpNum].In.dQH);
- }else {
- XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].In.dQH,
- EpCfg[EpNum].In.MaxPacketSize);
- XUsbPs_dQHDisableZLT(Ep[EpNum].In.dQH);
- }
-
- XUsbPs_dQHFlushCache(Ep[EpNum].In.dQH);
- }
- }
-}
-
-
-/*****************************************************************************/
-/**
- *
- * This function initializes the Transfer Descriptors lists in memory.
- *
- * @param DevCfgPtr is a pointer to the XUsbPs DEVICE configuration
- * structure.
- *
- * @return
- * - XST_SUCCESS: The operation completed successfully.
- * - XST_FAILURE: An error occurred.
- *
- ******************************************************************************/
-static int XUsbPs_dTDInit(XUsbPs_DeviceConfig *DevCfgPtr)
-{
- int EpNum;
-
- XUsbPs_Endpoint *Ep;
- XUsbPs_EpConfig *EpCfg;
-
- /* Setup pointers for simpler access. */
- Ep = DevCfgPtr->Ep;
- EpCfg = DevCfgPtr->EpCfg;
-
-
- /* Walk through the list of endpoints and initialize their Transfer
- * Descriptors.
- */
- for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
- int Td;
- int NumdTD;
-
- XUsbPs_EpOut *Out = &Ep[EpNum].Out;
- XUsbPs_EpIn *In = &Ep[EpNum].In;
-
-
- /* OUT Descriptors
- * ===============
- *
- * + Set the next link pointer
- * + Set the interrupt complete and the active bit
- * + Attach the buffer to the dTD
- */
- if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
- NumdTD = EpCfg[EpNum].Out.NumBufs;
- }
- else {
- NumdTD = 0;
- }
-
- for (Td = 0; Td < NumdTD; ++Td) {
- int Status;
-
- int NextTd = (Td + 1) % NumdTD;
-
- XUsbPs_dTDInvalidateCache(&Out->dTDs[Td]);
-
- /* Set NEXT link pointer. */
- XUsbPs_WritedTD(&Out->dTDs[Td], XUSBPS_dTDNLP,
- &Out->dTDs[NextTd]);
-
- /* Set the OUT descriptor ACTIVE and enable the
- * interrupt on complete.
- */
- XUsbPs_dTDSetActive(&Out->dTDs[Td]);
- XUsbPs_dTDSetIOC(&Out->dTDs[Td]);
-
-
- /* Set up the data buffer with the descriptor. If the
- * buffer pointer is NULL it means that we do not need
- * to attach a buffer to this descriptor.
- */
- if (NULL == Out->dTDBufs) {
- XUsbPs_dTDFlushCache(&Out->dTDs[Td]);
- continue;
- }
-
- Status = XUsbPs_dTDAttachBuffer(
- &Out->dTDs[Td],
- Out->dTDBufs +
- (Td * EpCfg[EpNum].Out.BufSize),
- EpCfg[EpNum].Out.BufSize);
- if (XST_SUCCESS != Status) {
- return XST_FAILURE;
- }
-
- XUsbPs_dTDFlushCache(&Out->dTDs[Td]);
- }
-
-
- /* IN Descriptors
- * ==============
- *
- * + Set the next link pointer
- * + Set the Terminate bit to mark it available
- */
- if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) {
- NumdTD = EpCfg[EpNum].In.NumBufs;
- }
- else {
- NumdTD = 0;
- }
-
- for (Td = 0; Td < NumdTD; ++Td) {
- int NextTd = (Td + 1) % NumdTD;
-
- XUsbPs_dTDInvalidateCache(&In->dTDs[Td]);
-
- /* Set NEXT link pointer. */
- XUsbPs_WritedTD(In->dTDs[Td], XUSBPS_dTDNLP,
- In->dTDs[NextTd]);
-
- /* Set the IN descriptor's TERMINATE bits. */
- XUsbPs_dTDSetTerminate(In->dTDs[Td]);
-
- XUsbPs_dTDFlushCache(&In->dTDs[Td]);
- }
- }
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
- *
- * This function associates a buffer with a Transfer Descriptor. The function
- * will take care of splitting the buffer into multiple 4kB aligned segments if
- * the buffer happens to span one or more 4kB pages.
- *
- * @param dTDIndex is a pointer to the Transfer Descriptor
- * @param BufferPtr is pointer to the buffer to link to the descriptor.
- * @param BufferLen is the length of the buffer.
- *
- * @return
- * - XST_SUCCESS: The operation completed successfully.
- * - XST_FAILURE: An error occurred.
- * - XST_USB_BUF_TOO_BIG: The provided buffer is bigger than tha
- * maximum allowed buffer size (16k).
- *
- * @note
- * Cache invalidation and flushing needs to be handler by the
- * caller of this function.
- *
- ******************************************************************************/
-static int XUsbPs_dTDAttachBuffer(XUsbPs_dTD *dTDPtr,
- const u8 *BufferPtr, u32 BufferLen)
-{
- u32 BufAddr;
- u32 BufEnd;
- u32 PtrNum;
-
- Xil_AssertNonvoid(dTDPtr != NULL);
-
- /* Check if the buffer is smaller than 16kB. */
- if (BufferLen > XUSBPS_dTD_BUF_MAX_SIZE) {
- return XST_USB_BUF_TOO_BIG;
- }
-
- /* Get a u32 of the buffer pointer to avoid casting in the following
- * logic operations.
- */
- BufAddr = (u32) BufferPtr;
-
-
- /* Set the buffer pointer 0. Buffer pointer 0 can point to any location
- * in memory. It does not need to be 4kB aligned. However, if the
- * provided buffer spans one or more 4kB boundaries, we need to set up
- * the subsequent buffer pointers which must be 4kB aligned.
- */
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDBPTR(0), BufAddr);
-
- /* Check if the buffer spans a 4kB boundary.
- *
- * Only do this check, if we are not sending a 0-length buffer.
- */
- if (BufferLen > 0) {
- BufEnd = BufAddr + BufferLen -1;
- PtrNum = 1;
-
- while ((BufAddr & 0xFFFFF000) != (BufEnd & 0xFFFFF000)) {
- /* The buffer spans at least one boundary, let's set
- * the next buffer pointer and repeat the procedure
- * until the end of the buffer and the pointer written
- * are in the same 4kB page.
- */
- BufAddr = (BufAddr + 0x1000) & 0xFFFFF000;
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDBPTR(PtrNum),
- BufAddr);
- PtrNum++;
- }
- }
-
- /* Set the length of the buffer. */
- XUsbPs_dTDSetTransferLen(dTDPtr, BufferLen);
-
-
- /* We remember the buffer pointer in the user data field (reserved
- * field in the dTD). This makes it easier to reset the buffer pointer
- * after a buffer has been received on the endpoint. The buffer pointer
- * needs to be reset because the DMA engine modifies the buffer pointer
- * while receiving.
- */
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDUSERDATA, BufferPtr);
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
- * This function set the Max PacketLen for the queue head for isochronous EP.
- *
- * If the max packet length is greater than XUSBPS_MAX_PACKET_SIZE, then
- * Mult bits are set to reflect that.
- *
- * @param dQHPtr is a pointer to the dQH element.
- * @param Len is the Length to be set.
- *
- ******************************************************************************/
-static void XUsbPs_dQHSetMaxPacketLenISO(XUsbPs_dQH *dQHPtr, u32 Len)
-{
- u32 Mult = (Len & ENDPOINT_MAXP_MULT_MASK) >> ENDPOINT_MAXP_MULT_SHIFT;
- u32 MaxPktSize = (Mult > 1) ? ENDPOINT_MAXP_LENGTH : Len;
-
- if (MaxPktSize > XUSBPS_MAX_PACKET_SIZE) {
- return;
- }
-
- if (Mult > 3) {
- return;
- }
-
- /* Set Max packet size */
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG,
- (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &
- ~XUSBPS_dQHCFG_MPL_MASK) |
- (MaxPktSize << XUSBPS_dQHCFG_MPL_SHIFT));
-
- /* Set Mult to tell hardware how many transactions in each microframe */
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG,
- (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &
- ~XUSBPS_dQHCFG_MULT_MASK) |
- (Mult << XUSBPS_dQHCFG_MULT_SHIFT));
-
-}
-
-/*****************************************************************************/
-/**
-* This function reconfigures one Ep corresponding to host's request of setting
-* alternate interface. The endpoint has been disabled before this call.
-*
-* Both QH and dTDs are updated for the new configuration.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param CfgPtr
-* Pointer to the updated XUsbPs DEVICE configuration structure.
-*
-* @param EpNum
-* The endpoint to be reconfigured.
-*
-* @param NewDirection
-* The new transfer direction the endpoint.
-*
-* @param DirectionChanged
-* A boolean value indicate whether the transfer direction has changed.
-*
-* @return
-* XST_SUCCESS upon success, XST_FAILURE otherwise.
-*
-******************************************************************************/
-int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr,
- int EpNum, unsigned short NewDirection,
- int DirectionChanged) {
-
- int Status = XST_SUCCESS;
- XUsbPs_Endpoint *Ep;
- XUsbPs_EpConfig *EpCfg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(CfgPtr != NULL);
-
- Ep = CfgPtr->Ep;
- EpCfg = CfgPtr->EpCfg;
-
- /* If transfer direction changes, dTDs has to be reset
- * Number of buffers are preset and should not to be changed.
- */
- if(DirectionChanged) {
- if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
- u8 *p;
-
- /* Swap the pointer to the dTDs.
- */
- Ep[EpNum].Out.dTDs = Ep[EpNum].In.dTDs;
- p = (u8 *)(Ep[EpNum].Out.dTDs + XUSBPS_dTD_ALIGN * EpCfg[EpNum].Out.NumBufs);
-
- /* Set the OUT buffer if buffer size is not zero
- */
- if(EpCfg[EpNum].Out.BufSize > 0) {
- Ep[EpNum].Out.dTDBufs = p;
- }
- } else if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
- Ep[EpNum].In.dTDs = Ep[EpNum].Out.dTDs;
- }
- }
-
- /* Reset dTD progress tracking pointers
- */
- if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
- Ep[EpNum].In.dTDHead = Ep[EpNum].In.dTDTail = Ep[EpNum].In.dTDs;
- } else if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
- Ep[EpNum].Out.dTDCurr = Ep[EpNum].Out.dTDs;
- }
-
- /* Reinitialize information in QH
- */
- XUsbPs_dQHReinitEp(CfgPtr, EpNum, NewDirection);
-
- /* Reinitialize the dTD linked list, and flush the cache
- */
- Status = XUsbPs_dTDReinitEp(CfgPtr, EpNum, NewDirection);
- if(Status != XST_SUCCESS) {
- return Status;
- }
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
- * This function re-initializes the Queue Head List in memory.
- * The endpoint 1 has been disabled before this call.
- *
- * @param DevCfgPtr
- * Pointer to the updated XUsbPs DEVICE configuration structure.
- *
- * @param EpNum
- * The endpoint to be reconfigured.
- *
- * @param NewDirection
- * The new transfer direction of endpoint 1
- *
- * @return none
- *
- ******************************************************************************/
-static void XUsbPs_dQHReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
-int EpNum, unsigned short NewDirection)
-{
- XUsbPs_Endpoint *Ep;
- XUsbPs_EpConfig *EpCfg;
-
- /* Setup pointers for simpler access.
- */
- Ep = DevCfgPtr->Ep;
- EpCfg = DevCfgPtr->EpCfg;
-
-
- /* Go through the list of Queue Head entries and:
- *
- * - Set Transfer Descriptor addresses
- * - Set Maximum Packet Size
- * - Disable Zero Length Termination (ZLT) for non-isochronous transfers
- * - Enable Interrupt On Setup (IOS)
- *
- */
- if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
- /* OUT Queue Heads.
- */
- XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
- XUSBPS_dQHCPTR, Ep[EpNum].Out.dTDs);
-
- /* For isochronous, ep max packet size translates to different
- * values in queue head than other types.
- * Also enable ZLT for isochronous.
- */
- if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].Out.Type) {
- XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].Out.dQH,
- EpCfg[EpNum].Out.MaxPacketSize);
- XUsbPs_dQHEnableZLT(Ep[EpNum].Out.dQH);
- }else {
- XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].Out.dQH,
- EpCfg[EpNum].Out.MaxPacketSize);
- XUsbPs_dQHDisableZLT(Ep[EpNum].Out.dQH);
- }
-
- XUsbPs_dQHSetIOS(Ep[EpNum].Out.dQH);
-
- /* Set up the overlay next dTD pointer.
- */
- XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
- XUSBPS_dQHdTDNLP, Ep[EpNum].Out.dTDs);
-
- XUsbPs_dQHFlushCache(Ep[EpNum].Out.dQH);
-
- } else if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
-
- /* IN Queue Heads.
- */
- XUsbPs_WritedQH(Ep[EpNum].In.dQH,
- XUSBPS_dQHCPTR, Ep[EpNum].In.dTDs);
-
- /* Isochronous ep packet size can be larger than 1024. */
- if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].In.Type) {
- XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].In.dQH,
- EpCfg[EpNum].In.MaxPacketSize);
- XUsbPs_dQHEnableZLT(Ep[EpNum].In.dQH);
- }else {
- XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].In.dQH,
- EpCfg[EpNum].In.MaxPacketSize);
- XUsbPs_dQHDisableZLT(Ep[EpNum].In.dQH);
- }
-
- XUsbPs_dQHSetIOS(Ep[EpNum].In.dQH);
-
- XUsbPs_dQHFlushCache(Ep[EpNum].In.dQH);
- }
-
-}
-
-/*****************************************************************************/
-/**
- *
- * This function re-initializes the Transfer Descriptors lists in memory.
- * The endpoint has been disabled before the call. The transfer descriptors
- * list pointer has been initialized too.
- *
- * @param DevCfgPtr
- * Pointer to the XUsbPs DEVICE configuration structure.
- *
- * @param EpNum
- * The endpoint to be reconfigured.
- *
- * @param NewDirection
- * The new transfer direction of endpoint 1
- *
- * @return
- * - XST_SUCCESS: The operation completed successfully.
- * - XST_FAILURE: An error occurred.
- *
- ******************************************************************************/
-static int XUsbPs_dTDReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
-int EpNum, unsigned short NewDirection)
-{
- XUsbPs_Endpoint *Ep;
- XUsbPs_EpConfig *EpCfg;
- int Td;
- int NumdTD;
-
-
- /* Setup pointers for simpler access.
- */
- Ep = DevCfgPtr->Ep;
- EpCfg = DevCfgPtr->EpCfg;
-
-
- if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
- XUsbPs_EpOut *Out = &Ep[EpNum].Out;
-
- /* OUT Descriptors
- * ===============
- *
- * + Set the next link pointer
- * + Set the interrupt complete and the active bit
- * + Attach the buffer to the dTD
- */
- NumdTD = EpCfg[EpNum].Out.NumBufs;
-
- for (Td = 0; Td < NumdTD; ++Td) {
- int Status;
-
- int NextTd = (Td + 1) % NumdTD;
-
- XUsbPs_dTDInvalidateCache(&Out->dTDs[Td]);
-
- /* Set NEXT link pointer.
- */
- XUsbPs_WritedTD(&Out->dTDs[Td], XUSBPS_dTDNLP,
- &Out->dTDs[NextTd]);
-
- /* Set the OUT descriptor ACTIVE and enable the
- * interrupt on complete.
- */
- XUsbPs_dTDSetActive(&Out->dTDs[Td]);
- XUsbPs_dTDSetIOC(&Out->dTDs[Td]);
-
- /* Set up the data buffer with the descriptor. If the
- * buffer pointer is NULL it means that we do not need
- * to attach a buffer to this descriptor.
- */
- if (Out->dTDBufs != NULL) {
-
- Status = XUsbPs_dTDAttachBuffer(
- &Out->dTDs[Td],
- Out->dTDBufs +
- (Td * EpCfg[EpNum].Out.BufSize),
- EpCfg[EpNum].Out.BufSize);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
- }
- XUsbPs_dTDFlushCache(&Out->dTDs[Td]);
- }
- } else if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
- XUsbPs_EpIn *In = &Ep[EpNum].In;
-
- /* IN Descriptors
- * ==============
- *
- * + Set the next link pointer
- * + Set the Terminate bit to mark it available
- */
- NumdTD = EpCfg[EpNum].In.NumBufs;
-
- for (Td = 0; Td < NumdTD; ++Td) {
- int NextTd = (Td + 1) % NumdTD;
-
- XUsbPs_dTDInvalidateCache(&In->dTDs[Td]);
-
- /* Set NEXT link pointer.
- */
- XUsbPs_WritedTD(&In->dTDs[Td], XUSBPS_dTDNLP,
- &In->dTDs[NextTd]);
-
- /* Set the IN descriptor's TERMINATE bits.
- */
- XUsbPs_dTDSetTerminate(&In->dTDs[Td]);
-
- XUsbPs_dTDFlushCache(&In->dTDs[Td]);
- }
- }
-
- return XST_SUCCESS;
-}
-
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/18/b0b384565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/18/b0b384565243001d18b399c1eb9b3628
deleted file mode 100644
index 42343dd..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/18/b0b384565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,59 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2008 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-* File : microblaze_disable_dcache.s
-* Date : 2002, March 20.
-* Company: Xilinx
-* Group : Emerging Software Technologies
-*
-* Summary:
-* Disable the L1 dcache on the microblaze.
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-#include "microblaze_instructions.h"
-
- .text
- .globl microblaze_disable_dcache
- .ent microblaze_disable_dcache
- .align 2
-microblaze_disable_dcache:
-#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
-
-#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
- ADDIK r1, r1, -8
- SI r15, r1, 0
- BRLID r15, microblaze_flush_dcache /* microblaze_flush_dcache does not use r1*/
- nop
- LI r15, r1, 0
- ADDIK r1, r1, 8
-#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
- rtsd r15, 8
- msrclr r0, 0x80
-
-#else /* XPAR_MICROBLAZE_USE_MSR_INSTR == 1 */
-
- ADDIK r1, r1, -8
-
-#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
- SI r15, r1, 0
- BRLID r15, microblaze_flush_dcache
- nop
-#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
- mfs r11, rmsr
- andi r11, r11, ~(0x80)
- mts rmsr, r11
-
-#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
- LI r15, r1, 0
-#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
-
- ADDIK r1, r1, 8
- rtsd r15, 8
- nop
-
-#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- .end microblaze_disable_dcache
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/19/006329585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/19/006329585243001d18b399c1eb9b3628
deleted file mode 100644
index 4b5c4cd..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/19/006329585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,105 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xscuwdt_selftest.c
-* @addtogroup scuwdt_v2_4
-* @{
-*
-* Contains diagnostic self-test functions for the XScuWdt driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xscuwdt.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/****************************************************************************/
-/**
-*
-* Run a self-test on the WDT. This test stops the watchdog, writes a value to
-* the watchdog load register, starts the watchdog and verifies that the value
-* read from the counter register is less that the value written to the load
-* register. It then restores the control register and the watchdog load
-* register.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return
-* - XST_SUCCESS if self-test was successful.
-* - XST_FAILURE if the WDT is not decrementing.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XScuWdt_SelfTest(XScuWdt *InstancePtr)
-{
- s32 SelfTestStatus;
- u32 Register;
- u32 CtrlOrig;
- u32 LoadOrig;
-
- /*
- * Assert to ensure the inputs are valid and the instance has been
- * initialized.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Stop the watchdog timer.
- */
- CtrlOrig = XScuWdt_GetControlReg(InstancePtr);
- XScuWdt_SetControlReg(InstancePtr,
- CtrlOrig & (~(u32)XSCUWDT_CONTROL_WD_ENABLE_MASK));
-
- LoadOrig = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,
- XSCUWDT_LOAD_OFFSET);
- XScuWdt_LoadWdt(InstancePtr, 0xFFFFFFFFU);
-
- /*
- * Start the watchdog timer and check if the watchdog counter is
- * decrementing.
- */
- XScuWdt_SetControlReg(InstancePtr,
- CtrlOrig | (u32)XSCUWDT_CONTROL_WD_ENABLE_MASK);
-
- Register = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,
- XSCUWDT_COUNTER_OFFSET);
-
- XScuWdt_LoadWdt(InstancePtr, LoadOrig);
- XScuWdt_SetControlReg(InstancePtr, CtrlOrig);
-
- if (Register == 0xFFFFFFFFU) {
- SelfTestStatus = (s32)XST_FAILURE;
- }
- else {
- SelfTestStatus = (s32)XST_SUCCESS;
- }
-
- return SelfTestStatus;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/19/6121ea555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/19/6121ea555243001d18b399c1eb9b3628
deleted file mode 100644
index 25fc262..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/19/6121ea555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,132 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xil-crt0.S
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 10/20/09 Initial version
-* 3.05a sdm 02/02/12 Added code for profiling
-* 3.06a sgd 05/16/12 Added global constructors and cleanup code
-* Uart initialization based on compiler flag
-* 3.07a sgd 07/05/12 Updated with reset and start Global Timer
-* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
-* 4.2 pkp 08/04/14 Removed PEEP board related code which contained
-* initialization of uart smc nor and sram
-* 5.3 pkp 10/07/15 Added support for OpenAMP by not initializing global
-* timer when USE_AMP flag is defined
-* 6.6 srm 10/18/17 Added timer configuration using XTime_StartTTCTimer API.
-* Now the TTC instance as specified by the user will be
-* started.
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#include "bspconfig.h"
-
- .file "xil-crt0.S"
- .section ".got2","aw"
- .align 2
-
- .text
-.Lsbss_start:
- .long __sbss_start
-
-.Lsbss_end:
- .long __sbss_end
-
-.Lbss_start:
- .long __bss_start
-
-.Lbss_end:
- .long __bss_end
-
-.Lstack:
- .long __stack
-
-
- .globl _start
-_start:
- bl __cpu_init /* Initialize the CPU first (BSP provides this) */
-
- mov r0, #0
-
- /* clear sbss */
- ldr r1,.Lsbss_start /* calculate beginning of the SBSS */
- ldr r2,.Lsbss_end /* calculate end of the SBSS */
-
-.Lloop_sbss:
- cmp r1,r2
- bge .Lenclsbss /* If no SBSS, no clearing required */
- str r0, [r1], #4
- b .Lloop_sbss
-
-.Lenclsbss:
- /* clear bss */
- ldr r1,.Lbss_start /* calculate beginning of the BSS */
- ldr r2,.Lbss_end /* calculate end of the BSS */
-
-.Lloop_bss:
- cmp r1,r2
- bge .Lenclbss /* If no BSS, no clearing required */
- str r0, [r1], #4
- b .Lloop_bss
-
-.Lenclbss:
-
- /* set stack pointer */
- ldr r13,.Lstack /* stack address */
-
- /* Reset and start Global Timer */
- mov r0, #0x0
- mov r1, #0x0
-
- /* Reset and start Triple Timer Counter */
- #if defined SLEEP_TIMER_BASEADDR
- bl XTime_StartTTCTimer
- #endif
-
-#if USE_AMP != 1
- bl XTime_SetTime
-#endif
-
-#ifdef PROFILING /* defined in Makefile */
- /* Setup profiling stuff */
- bl _profile_init
-#endif /* PROFILING */
-
- /* run global constructors */
- bl __libc_init_array
-
- /* make sure argc and argv are valid */
- mov r0, #0
- mov r1, #0
-
- /* Let her rip */
- bl main
-
- /* Cleanup global constructors */
- bl __libc_fini_array
-
-#ifdef PROFILING
- /* Cleanup profiling stuff */
- bl _profile_clean
-#endif /* PROFILING */
-
- /* All done */
- bl exit
-
-.Lexit: /* should never get here */
- b .Lexit
-
-.Lstart:
- .size _start,.Lstart-_start
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1a/308b39545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1a/308b39545243001d18b399c1eb9b3628
deleted file mode 100644
index e48c5f3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1a/308b39545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,111 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_errata.h
-*
-* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
-* @{
-* Various ARM errata are handled in the standalone BSP. The implementation for
-* errata handling follows ARM guidelines and is based on the open source Linux
-* support for these errata.
-*
-* @note The errata handling is enabled by default. To disable handling of all the
-* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
-* disable errata on a per-erratum basis, un-define relevant macros in
-* xil_errata.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a srt 04/18/13 First release
-* 6.6 mus 12/07/17 Removed errata 753970, It fixes CR#989132.
-*
-*
-******************************************************************************/
-#ifndef XIL_ERRATA_H
-#define XIL_ERRATA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *@cond nocomments
- */
-/**
- * @name errata_definitions
- *
- * The errata conditions handled in the standalone BSP are listed below
- * @{
- */
-
-#define ENABLE_ARM_ERRATA 1
-
-/**
- *@endcond
- */
-
-#ifdef ENABLE_ARM_ERRATA
-
-/**
- * Errata No: 742230
- * Description: DMB operation may be faulty
- */
-#define CONFIG_ARM_ERRATA_742230 1
-
-/**
- * Errata No: 743622
- * Description: Faulty hazard checking in the Store Buffer may lead
- * to data corruption.
- */
-#define CONFIG_ARM_ERRATA_743622 1
-
-/**
- * Errata No: 775420
- * Description: A data cache maintenance operation which aborts,
- * might lead to deadlock
- */
-#define CONFIG_ARM_ERRATA_775420 1
-
-/**
- * Errata No: 794073
- * Description: Speculative instruction fetches with MMU disabled
- * might not comply with architectural requirements
- */
-#define CONFIG_ARM_ERRATA_794073 1
-
-
-/** PL310 L2 Cache Errata */
-
-/**
- * Errata No: 588369
- * Description: Clean & Invalidate maintenance operations do not
- * invalidate clean lines
- */
-#define CONFIG_PL310_ERRATA_588369 1
-
-/**
- * Errata No: 727915
- * Description: Background Clean and Invalidate by Way operation
- * can cause data corruption
- */
-#define CONFIG_PL310_ERRATA_727915 1
-
-/*@}*/
-#endif /* ENABLE_ARM_ERRATA */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_ERRATA_H */
-/**
-* @} End of "addtogroup a9_errata".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1a/40a71a565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1a/40a71a565243001d18b399c1eb9b3628
deleted file mode 100644
index 801ef0b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1a/40a71a565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,135 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xil-crt0.S
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00 pkp 02/10/14 First release
-* 5.04 pkp 12/18/15 Initialized global constructor for C++ applications
-* 5.04 pkp 02/19/16 Added timer configuration using XTime_StartTimer API when
-* TTC3 is present
-* 6.4 asa 08/16/17 Added call to Xil_InitializeExistingMPURegConfig to
-* initialize the MPU configuration table with the MPU
-* configurations already set in Init_Mpu function.
-* 6.6 srm 10/18/17 Updated the timer configuration with XTime_StartTTCTimer.
-* Now the timer instance as specified by the user will be
-* started.
-* 7.2 mus 10/22/19 Defined RPU_TZ_MASK as #define instead of variable.
-* 7.2 sd 03/20/20 Add clocking support.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sv 01/15/10 First Release
-* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
-* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
-* relevant to Zynq device. The interrupts are disabled
-* for output pins on all banks during initialization.
-* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
-* 3.1 aru 07/13/18 Resolved doxygen reported warnings. CR# 1006331.
-* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
-* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
-* in safety mode and modified the code such as
-* Use of mixed mode arithmetic,Declared the pointer param
-* as Pointer to const,Casting operation to a pointer,
-* Literal value requires a U suffix.
-* 3.5 sne 03/13/19 Added Versal support.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xgpiops.h"
-
-/************************** Constant Definitions *****************************/
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-
-/************************** Function Prototypes ******************************/
-
-void StubHandler(void *CallBackRef, u32 Bank, u32 Status); /**< Stub handler */
-
-/*****************************************************************************/
-/**
-*
-* This function initializes a XGpioPs instance/driver.
-* All members of the XGpioPs instance structure are initialized and
-* StubHandlers are assigned to the Bank Status Handlers.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param ConfigPtr points to the XGpioPs device configuration structure.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. If the address translation is not used then the
-* physical address should be passed.
-* Unexpected errors may occur if the address mapping is changed
-* after this function is invoked.
-*
-* @return XST_SUCCESS always.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
- u32 EffectiveAddr)
-{
- s32 Status = (s32)0;
- u8 i;
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
- Xil_AssertNonvoid(EffectiveAddr != (u32)0);
- /*
- * Set some default values for instance data, don't indicate the device
- * is ready to use until everything has been initialized successfully.
- */
- InstancePtr->IsReady = 0U;
- InstancePtr->GpioConfig.BaseAddr = EffectiveAddr;
- InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId;
- InstancePtr->Handler = (XGpioPs_Handler)StubHandler;
- InstancePtr->Platform = XGetPlatform_Info();
-
- /* Initialize the Bank data based on platform */
- if (InstancePtr->Platform == (u32)XPLAT_ZYNQ_ULTRA_MP) {
- /*
- * Max pins in the ZynqMP GPIO device
- * 0 - 25, Bank 0
- * 26 - 51, Bank 1
- * 52 - 77, Bank 2
- * 78 - 109, Bank 3
- * 110 - 141, Bank 4
- * 142 - 173, Bank 5
- */
- InstancePtr->MaxPinNum = (u32)174;
- InstancePtr->MaxBanks = (u8)6;
- }
- else if (InstancePtr->Platform == (u32)XPLAT_VERSAL)
- {
- if(InstancePtr->PmcGpio == (u32)FALSE)
- {
- /* Max pins in the PS_GPIO devices
- * 0 -25, Bank 0
- * 26-57, Bank 3
- */
- InstancePtr->MaxPinNum = (u32)58;
- InstancePtr->MaxBanks = (u8)4;
- }
- else
- {
- /* Max pins in the PMC_GPIO devices
- * 0 - 25,Bank 0
- * 26 - 51,Bank 1
- * 52 - 83,Bank 3
- * 84 - 115, Bank 4
- */
- InstancePtr->MaxPinNum = (u32)116;
- InstancePtr->MaxBanks = (u8)5;
- }
- }
- else {
- /*
- * Max pins in the GPIO device
- * 0 - 31, Bank 0
- * 32 - 53, Bank 1
- * 54 - 85, Bank 2
- * 86 - 117, Bank 3
- */
- InstancePtr->MaxPinNum = (u32)118;
- InstancePtr->MaxBanks = (u8)4;
- }
-
- /*
- * By default, interrupts are not masked in GPIO. Disable
- * interrupts for all pins in all the 4 banks.
- */
- for (i=(u8)0U;iMaxBanks;i++) {
- if (InstancePtr->Platform == XPLAT_VERSAL){
- if(InstancePtr->PmcGpio == (u32)FALSE)
- {
- if((i== (u8)XGPIOPS_ONE)||(i== (u8)XGPIOPS_TWO))
- {
- continue;
- }
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
- }
- else
- {
- if(i==(u32)XGPIOPS_TWO)
- {
- continue;
- }
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
-
- }
- }
- else
- {
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
- }
- }
-
- /* Indicate the component is now ready to use. */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* Read the Data register of the specified GPIO bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-*
-* @return Current value of the Data register.
-*
-* @note This function is used for reading the state of all the GPIO pins
-* of specified bank.
-*
-*****************************************************************************/
-u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertNonvoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
- XGPIOPS_DATA_RO_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* Read Data from the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number for which the data has to be read.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-* See xgpiops.h for the mapping of the pin numbers in the banks.
-*
-* @return Current value of the Pin (0 or 1).
-*
-* @note This function is used for reading the state of the specified
-* GPIO pin.
-*
-*****************************************************************************/
-u32 XGpioPs_ReadPin(const XGpioPs *InstancePtr, u32 Pin)
-{
- u8 Bank;
- u8 PinNumber;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
- return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
- XGPIOPS_DATA_RO_OFFSET) >> (u32)PinNumber) & (u32)1;
-
-}
-
-/****************************************************************************/
-/**
-*
-* Write to the Data register of the specified GPIO bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param Data is the value to be written to the Data register.
-*
-* @return None.
-*
-* @note This function is used for writing to all the GPIO pins of
-* the bank. The previous state of the pins is not maintained.
-*
-*****************************************************************************/
-void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertVoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
- XGPIOPS_DATA_OFFSET, Data);
-}
-
-/****************************************************************************/
-/**
-*
-* Write data to the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number to which the Data is to be written.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-* @param Data is the data to be written to the specified pin (0 or 1).
-*
-* @return None.
-*
-* @note This function does a masked write to the specified pin of
-* the specified GPIO bank. The previous state of other pins
-* is maintained.
-*
-*****************************************************************************/
-void XGpioPs_WritePin(const XGpioPs *InstancePtr, u32 Pin, u32 Data)
-{
- u32 RegOffset;
- u32 Value;
- u8 Bank;
- u8 PinNumber;
- u32 DataVar = Data;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
-
- if (PinNumber > 15U) {
- /* There are only 16 data bits in bit maskable register. */
- PinNumber -= (u8)16;
- RegOffset = XGPIOPS_DATA_MSW_OFFSET;
- } else {
- RegOffset = XGPIOPS_DATA_LSW_OFFSET;
- }
-
- /*
- * Get the 32 bit value to be written to the Mask/Data register where
- * the upper 16 bits is the mask and lower 16 bits is the data.
- */
- DataVar &= (u32)0x01;
- Value = ~((u32)1 << (PinNumber + 16U)) & ((DataVar << PinNumber) | 0xFFFF0000U);
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_DATA_MASK_OFFSET) +
- RegOffset, Value);
-
-}
-
-
-
-/****************************************************************************/
-/**
-*
-* Set the Direction of the pins of the specified GPIO Bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param Direction is the 32 bit mask of the Pin direction to be set for
-* all the pins in the Bank. Bits with 0 are set to Input mode,
-* bits with 1 are set to Output Mode.
-*
-* @return None.
-*
-* @note This function is used for setting the direction of all the pins
-* in the specified bank. The previous state of the pins is
-* not maintained.
-*
-*****************************************************************************/
-void XGpioPs_SetDirection(const XGpioPs *InstancePtr, u8 Bank, u32 Direction)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertVoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_DIRM_OFFSET, Direction);
-}
-
-/****************************************************************************/
-/**
-*
-* Set the Direction of the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number to which the Data is to be written.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-* @param Direction is the direction to be set for the specified pin.
-* Valid values are 0 for Input Direction, 1 for Output Direction.
-*
-* @return None.
-*
-*****************************************************************************/
-void XGpioPs_SetDirectionPin(const XGpioPs *InstancePtr, u32 Pin, u32 Direction)
-{
- u8 Bank;
- u8 PinNumber;
- u32 DirModeReg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
- Xil_AssertVoid(Direction <= (u32)1);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
- DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_DIRM_OFFSET);
-
- if (Direction!=(u32)0) { /* Output Direction */
- DirModeReg |= ((u32)1 << (u32)PinNumber);
- } else { /* Input Direction */
- DirModeReg &= ~ ((u32)1 << (u32)PinNumber);
- }
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_DIRM_OFFSET, DirModeReg);
-}
-
-/****************************************************************************/
-/**
-*
-* Get the Direction of the pins of the specified GPIO Bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-*
-* @return Returns a 32 bit mask of the Direction register. Bits with 0 are
-* in Input mode, bits with 1 are in Output Mode.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertNonvoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_DIRM_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* Get the Direction of the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number for which the Direction is to be
-* retrieved.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*
-* @return Direction of the specified pin.
-* - 0 for Input Direction
-* - 1 for Output Direction
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpioPs_GetDirectionPin(const XGpioPs *InstancePtr, u32 Pin)
-{
- u8 Bank;
- u8 PinNumber;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
-
- return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_DIRM_OFFSET) >> (u32)PinNumber) & (u32)1;
-}
-
-/****************************************************************************/
-/**
-*
-* Set the Output Enable of the pins of the specified GPIO Bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param OpEnable is the 32 bit mask of the Output Enables to be set for
-* all the pins in the Bank. The Output Enable of bits with 0 are
-* disabled, the Output Enable of bits with 1 are enabled.
-*
-* @return None.
-*
-* @note This function is used for setting the Output Enables of all the
-* pins in the specified bank. The previous state of the Output
-* Enables is not maintained.
-*
-*****************************************************************************/
-void XGpioPs_SetOutputEnable(const XGpioPs *InstancePtr, u8 Bank, u32 OpEnable)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertVoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_OUTEN_OFFSET, OpEnable);
-}
-
-/****************************************************************************/
-/**
-*
-* Set the Output Enable of the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number to which the Data is to be written.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-* @param OpEnable specifies whether the Output Enable for the specified
-* pin should be enabled.
-* Valid values are 0 for Disabling Output Enable,
-* 1 for Enabling Output Enable.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnable)
-{
- u8 Bank;
- u8 PinNumber;
- u32 OpEnableReg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
- Xil_AssertVoid(OpEnable <= (u32)1);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
-
- OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_OUTEN_OFFSET);
-
- if (OpEnable != (u32)0) { /* Enable Output Enable */
- OpEnableReg |= ((u32)1 << (u32)PinNumber);
- } else { /* Disable Output Enable */
- OpEnableReg &= ~ ((u32)1 << (u32)PinNumber);
- }
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_OUTEN_OFFSET, OpEnableReg);
-}
-/****************************************************************************/
-/**
-*
-* Get the Output Enable status of the pins of the specified GPIO Bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-*
-* @return Returns a a 32 bit mask of the Output Enable register.
-* Bits with 0 are in Disabled state, bits with 1 are in
-* Enabled State.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertNonvoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_OUTEN_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* Get the Output Enable status of the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number for which the Output Enable status is to
-* be retrieved.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*
-* @return Output Enable of the specified pin.
-* - 0 if Output Enable is disabled for this pin
-* - 1 if Output Enable is enabled for this pin
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin)
-{
- u8 Bank;
- u8 PinNumber;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
-
- return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_OUTEN_OFFSET) >> (u32)PinNumber) & (u32)1;
-}
-
-/****************************************************************************/
-/**
-*
-* Get the Bank number and the Pin number in the Bank, for the given PinNumber
-* in the GPIO device.
-*
-* @param PinNumber is the Pin number in the GPIO device.
-* @param BankNumber returns the Bank in which this GPIO pin is present.
-* Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
-* @param PinNumberInBank returns the Pin Number within the Bank.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#ifdef versal
-void XGpioPs_GetBankPin(const XGpioPs *InstancePtr,u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
-#else
-void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
-#endif
-{
- u32 XGpioPsPinTable[6] = {0};
-#ifdef versal
- u8 i=(u8)0;
-#endif
- u32 Platform = XGetPlatform_Info();
-
- if (Platform == (u32)XPLAT_ZYNQ_ULTRA_MP) {
- /*
- * This structure defines the mapping of the pin numbers to the banks when
- * the driver APIs are used for working on the individual pins.
- */
-
- XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
- XGpioPsPinTable[1] = (u32)51; /* 26 - 51, Bank 1 */
- XGpioPsPinTable[2] = (u32)77; /* 52 - 77, Bank 2 */
- XGpioPsPinTable[3] = (u32)109; /* 78 - 109, Bank 3 */
- XGpioPsPinTable[4] = (u32)141; /* 110 - 141, Bank 4 */
- XGpioPsPinTable[5] = (u32)173; /* 142 - 173 Bank 5 */
-
- *BankNumber = 0U;
- while (*BankNumber < XGPIOPS_SIX) {
- if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
- break;
- }
- (*BankNumber)++;
- }
- }
-#ifdef versal
- else if(Platform == XPLAT_VERSAL)
- {
- if(InstancePtr->PmcGpio == (u32)(FALSE))
- {
- XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
- XGpioPsPinTable[1] = (u32)57; /* 26 - 57, Bank 3 */
- *BankNumber =0U;
- if(PinNumber <= XGpioPsPinTable[*BankNumber])
- {
- *BankNumber = (u8)XGPIOPS_ZERO;
- }
- else
- {
- *BankNumber = (u8)XGPIOPS_THREE;
- }
-
- }
- else
- {
- XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
- XGpioPsPinTable[1] = (u32)51; /* 26 - 51, Bank 1 */
- XGpioPsPinTable[2] = (u32)83; /* 52 - 83, Bank 3 */
- XGpioPsPinTable[3] = (u32)115; /*84 - 115, Bank 4 */
-
- *BankNumber =0U;
- while(i < XGPIOPS_FOUR)
- {
- if(i <= (u8)XGPIOPS_ONE)
- {
- if (PinNumber <= XGpioPsPinTable[i])
- {
- *BankNumber = (u8)i;
- break;
- }
- i++;
- }
- else
- {
- if (PinNumber <= XGpioPsPinTable[i])
- {
- *BankNumber = (u8)i+1U;
- break;
- }
- i++;
- }
-
- }
- }
-
- }
-#endif
- else {
- XGpioPsPinTable[0] = (u32)31; /* 0 - 31, Bank 0 */
- XGpioPsPinTable[1] = (u32)53; /* 32 - 53, Bank 1 */
- XGpioPsPinTable[2] = (u32)85; /* 54 - 85, Bank 2 */
- XGpioPsPinTable[3] = (u32)117; /* 86 - 117 Bank 3 */
-
- *BankNumber = 0U;
- while (*BankNumber < XGPIOPS_FOUR) {
- if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
- break;
- }
- (*BankNumber)++;
- }
- }
- if (*BankNumber == (u8)0) {
- *PinNumberInBank = PinNumber;
- }
-
-#ifdef versal
- else if(Platform == XPLAT_VERSAL)
- {
- if(InstancePtr->PmcGpio == (u32)(FALSE))
- {
- *PinNumberInBank = (u8)((u32)PinNumber - (XGpioPsPinTable[0] + (u32)1));
- }
- else {
- if((*BankNumber ==(u8)XGPIOPS_THREE) || (*BankNumber ==(u8)XGPIOPS_FOUR))
- {
- *PinNumberInBank = (u8)((u32)PinNumber %
- (XGpioPsPinTable[*BankNumber - (u8)XGPIOPS_TWO] + (u32)1));
- }
- else
- {
- *PinNumberInBank = (u8)((u32)PinNumber %
- (XGpioPsPinTable[*BankNumber - (u8)1] + (u32)1));
- }
- }
-
- }
-#endif
-
- else {
- *PinNumberInBank = (u8)((u32)PinNumber %
- (XGpioPsPinTable[*BankNumber - (u8)1] + (u32)1));
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* This is a stub for the status callback. The stub is here in case the upper
-* layers do not set the handler.
-*
-* @param CallBackRef is a pointer to the upper layer callback reference
-* @param Bank is the GPIO Bank in which an interrupt occurred.
-* @param Status is the Interrupt status of the GPIO bank.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void StubHandler(void *CallBackRef, u32 Bank, u32 Status)
-{
- (void) CallBackRef;
- (void) Bank;
- (void) Status;
-
- Xil_AssertVoidAlways();
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1a/914e73565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1a/914e73565243001d18b399c1eb9b3628
deleted file mode 100644
index 00b233a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1a/914e73565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,20 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include "xil_types.h"
-
-/*
- * fcntl -- Manipulate a file descriptor.
- * We don't have a filesystem, so we do nothing.
- */
-__attribute__((weak)) sint32 fcntl (sint32 fd, sint32 cmd, long arg)
-{
- (void)fd;
- (void)cmd;
- (void)arg;
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1a/b0f3598c4046001d13a480ec55035cc1 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1a/b0f3598c4046001d13a480ec55035cc1
deleted file mode 100644
index c63db8f..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1a/b0f3598c4046001d13a480ec55035cc1
+++ /dev/null
@@ -1,11 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1a/c00cdc545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1a/c00cdc545243001d18b399c1eb9b3628
deleted file mode 100644
index c466c85..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1a/c00cdc545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,260 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xscutimer.c
-* @addtogroup scutimer_v2_3
-* @{
-*
-* Contains the implementation of interface functions of the SCU Timer driver.
-* See xscutimer.h for a description of the driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm 03/10/10 First release
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xscutimer.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/****************************************************************************/
-/**
-*
-* Initialize a specific timer instance/driver. This function must be called
-* before other functions of the driver are called.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-* @param ConfigPtr points to the XScuTimer configuration structure.
-* @param EffectiveAddress is the base address for the device. It could be
-* a virtual address if address translation is supported in the
-* system, otherwise it is the physical address.
-*
-* @return
-* - XST_SUCCESS if initialization was successful.
-* - XST_DEVICE_IS_STARTED if the device has already been started.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
- XScuTimer_Config *ConfigPtr, u32 EffectiveAddress)
-{
- s32 Status;
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
-
- /*
- * If the device is started, disallow the initialize and return a
- * status indicating it is started. This allows the user to stop the
- * device and reinitialize, but prevents a user from inadvertently
- * initializing.
- */
- if (InstancePtr->IsStarted != XIL_COMPONENT_IS_STARTED) {
- /*
- * Copy configuration into the instance structure.
- */
- InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
-
- /*
- * Save the base address pointer such that the registers of the block
- * can be accessed and indicate it has not been started yet.
- */
- InstancePtr->Config.BaseAddr = EffectiveAddress;
-
- InstancePtr->IsStarted = (u32)0;
-
- /*
- * Indicate the instance is ready to use, successfully initialized.
- */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- Status =(s32)XST_SUCCESS;
- }
- else {
- Status = (s32)XST_DEVICE_IS_STARTED;
- }
- return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* Start the timer.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XScuTimer_Start(XScuTimer *InstancePtr)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the contents of the Control register.
- */
- Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
- XSCUTIMER_CONTROL_OFFSET);
-
- /*
- * Set the 'timer enable' bit in the register.
- */
- Register |= XSCUTIMER_CONTROL_ENABLE_MASK;
-
- /*
- * Update the Control register with the new value.
- */
- XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
- XSCUTIMER_CONTROL_OFFSET, Register);
-
- /*
- * Indicate that the device is started.
- */
- InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
-}
-
-/****************************************************************************/
-/**
-*
-* Stop the timer.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XScuTimer_Stop(XScuTimer *InstancePtr)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the contents of the Control register.
- */
- Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
- XSCUTIMER_CONTROL_OFFSET);
-
- /*
- * Clear the 'timer enable' bit in the register.
- */
- Register &= (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK);
-
- /*
- * Update the Control register with the new value.
- */
- XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
- XSCUTIMER_CONTROL_OFFSET, Register);
-
- /*
- * Indicate that the device is stopped.
- */
- InstancePtr->IsStarted = (u32)0;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets the prescaler bits in the timer control register.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-* @param PrescalerValue is a 8 bit value that sets the prescaler to use.
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue)
-{
- u32 ControlReg;
-
- /*
- * Assert to validate input arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- /*
- * Read the Timer control register.
- */
- ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
- XSCUTIMER_CONTROL_OFFSET);
-
- /*
- * Clear all of the prescaler control bits in the register.
- */
- ControlReg &= (u32)(~XSCUTIMER_CONTROL_PRESCALER_MASK);
-
- /*
- * Set the prescaler value.
- */
- ControlReg |= (((u32)PrescalerValue) << XSCUTIMER_CONTROL_PRESCALER_SHIFT);
-
- /*
- * Write the register with the new values.
- */
- XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
- XSCUTIMER_CONTROL_OFFSET, ControlReg);
-}
-
-/*****************************************************************************/
-/**
-*
-* This function returns the current prescaler value.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return The prescaler value.
-*
-* @note None.
-*
-****************************************************************************/
-u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr)
-{
- u32 ControlReg;
-
- /*
- * Assert to validate input arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Timer control register.
- */
- ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
- XSCUTIMER_CONTROL_OFFSET);
- ControlReg &= XSCUTIMER_CONTROL_PRESCALER_MASK;
-
- return (u8)(ControlReg >> XSCUTIMER_CONTROL_PRESCALER_SHIFT);
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1a/e043ad595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1a/e043ad595243001d18b399c1eb9b3628
deleted file mode 100644
index 60f4ba3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1a/e043ad595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,53 +0,0 @@
-/******************************************************************************
-* Copyright (c) 1995 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-*******************************************************************************/
- #ifndef XIL_PRINTF_H
- #define XIL_PRINTF_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include
-#include
-#include
-#include "xil_types.h"
-#include "xparameters.h"
-#include "bspconfig.h"
-#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
-#include "xen_console.h"
-#endif
-
-/*----------------------------------------------------*/
-/* Use the following parameter passing structure to */
-/* make xil_printf re-entrant. */
-/*----------------------------------------------------*/
-
-struct params_s;
-
-
-/*---------------------------------------------------*/
-/* The purpose of this routine is to output data the */
-/* same as the standard printf function without the */
-/* overhead most run-time libraries involve. Usually */
-/* the printf brings in many kilobytes of code and */
-/* that is unacceptable in most embedded systems. */
-/*---------------------------------------------------*/
-
-typedef char8* charptr;
-typedef s32 (*func_ptr)(int c);
-
-/* */
-
-void xil_printf( const char8 *ctrl1, ...);
-void xil_vprintf(const char8 *ctrl1, va_list argp);
-void print( const char8 *ptr);
-extern void outbyte (char8 c);
-extern char8 inbyte(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/033252565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/033252565243001d18b399c1eb9b3628
deleted file mode 100644
index b3dd7e9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/033252565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,126 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_assert.c
-* @addtogroup common_assert_apis Assert APIs and Macros
-* @{
-*
-* This file contains basic assert related functions for Xilinx software IP.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 Initial release
-* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/**
- * @brief This variable allows testing to be done easier with asserts. An assert
- * sets this variable such that a driver can evaluate this variable
- * to determine if an assert occurred.
- */
-u32 Xil_AssertStatus;
-
-/**
- * @brief This variable allows the assert functionality to be changed for testing
- * such that it does not wait infinitely. Use the debugger to disable the
- * waiting during testing of asserts.
- */
-s32 Xil_AssertWait = 1;
-
-/* The callback function to be invoked when an assert is taken */
-static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* @brief Implement assert. Currently, it calls a user-defined callback
-* function if one has been set. Then, it potentially enters an
-* infinite loop depending on the value of the Xil_AssertWait
-* variable.
-*
-* @param File: filename of the source
-* @param Line: linenumber within File
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void Xil_Assert(const char8 *File, s32 Line)
-{
- /* if the callback has been set then invoke it */
- if (Xil_AssertCallbackRoutine != 0) {
- (*Xil_AssertCallbackRoutine)(File, Line);
- }
-
- /* if specified, wait indefinitely such that the assert will show up
- * in testing
- */
- while (Xil_AssertWait != 0) {
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Set up a callback function to be invoked when an assert occurs.
-* If a callback is already installed, then it will be replaced.
-*
-* @param Routine: callback to be invoked when an assert is taken
-*
-* @return None.
-*
-* @note This function has no effect if NDEBUG is set
-*
-******************************************************************************/
-void Xil_AssertSetCallback(Xil_AssertCallback Routine)
-{
- Xil_AssertCallbackRoutine = Routine;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Null handler function. This follows the XInterruptHandler
-* signature for interrupt handlers. It can be used to assign a null
-* handler (a stub) to an interrupt controller vector table.
-*
-* @param NullParameter: arbitrary void pointer and not used.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XNullHandler(void *NullParameter)
-{
- (void) NullParameter;
-}
-/**
-* @} End of "addtogroup common_assert_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/10bf35585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/10bf35585243001d18b399c1eb9b3628
deleted file mode 100644
index 2de567a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/10bf35585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1410 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xsdps_hw.h
-* @addtogroup sdps_v3_13
-* @{
-*
-* This header file contains the identifiers and basic HW access driver
-* functions (or macros) that can be used to access the device. Other driver
-* functions are defined in xsdps.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a hk/sg 10/17/13 Initial release
-* 2.5 sg 07/09/15 Added SD 3.0 features
-* kvn 07/15/15 Modified the code according to MISRAC-2012.
-* 2.7 sk 12/10/15 Added support for MMC cards.
-* sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
-* 2.8 sk 04/20/16 Added new workaround for auto tuning.
-* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
-* sk 07/16/16 Added support for UHS modes.
-* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
-* operating modes.
-* 3.1 sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
-* 3.2 sk 03/20/17 Add support for EL1 non-secure mode.
-* 3.3 mn 08/22/17 Updated for Word Access System support
-* mn 09/06/17 Added support for ARMCC toolchain
-* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
-* 3.6 mn 07/06/18 Fix Doxygen warnings for sdps driver
-* 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
-* mn 05/21/19 Set correct tap delays for Versal
-* mn 05/21/19 Disable DLL Reset code for Versal
-* mn 07/03/19 Update Input Tap Delays for Versal
-* 3.9 mn 03/03/20 Restructured the code for more readability and modularity
-*
-*
-*
-******************************************************************************/
-
-#ifndef SD_HW_H_
-#define SD_HW_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets from the base address of an SD device.
- * @{
- */
-
-#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address
- Register */
-#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET
- /**< SDMA System Address
- Low Register */
-#define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */
-#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address
- High Register */
-#define XSDPS_ARGMT2_HI_OFFSET 0x02U /**< Argument2 High Register */
-
-#define XSDPS_BLK_SIZE_OFFSET 0x04U /**< Block Size Register */
-#define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */
-#define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */
-#define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET
- /**< Argument1 Register */
-#define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */
-
-#define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */
-#define XSDPS_CMD_OFFSET 0x0EU /**< Command Register */
-#define XSDPS_RESP0_OFFSET 0x10U /**< Response0 Register */
-#define XSDPS_RESP1_OFFSET 0x14U /**< Response1 Register */
-#define XSDPS_RESP2_OFFSET 0x18U /**< Response2 Register */
-#define XSDPS_RESP3_OFFSET 0x1CU /**< Response3 Register */
-#define XSDPS_BUF_DAT_PORT_OFFSET 0x20U /**< Buffer Data Port */
-#define XSDPS_PRES_STATE_OFFSET 0x24U /**< Present State */
-#define XSDPS_HOST_CTRL1_OFFSET 0x28U /**< Host Control 1 */
-#define XSDPS_POWER_CTRL_OFFSET 0x29U /**< Power Control */
-#define XSDPS_BLK_GAP_CTRL_OFFSET 0x2AU /**< Block Gap Control */
-#define XSDPS_WAKE_UP_CTRL_OFFSET 0x2BU /**< Wake Up Control */
-#define XSDPS_CLK_CTRL_OFFSET 0x2CU /**< Clock Control */
-#define XSDPS_TIMEOUT_CTRL_OFFSET 0x2EU /**< Timeout Control */
-#define XSDPS_SW_RST_OFFSET 0x2FU /**< Software Reset */
-#define XSDPS_NORM_INTR_STS_OFFSET 0x30U /**< Normal Interrupt
- Status Register */
-#define XSDPS_ERR_INTR_STS_OFFSET 0x32U /**< Error Interrupt
- Status Register */
-#define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34U /**< Normal Interrupt
- Status Enable Register */
-#define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36U /**< Error Interrupt
- Status Enable Register */
-#define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38U /**< Normal Interrupt
- Signal Enable Register */
-#define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3AU /**< Error Interrupt
- Signal Enable Register */
-
-#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3CU /**< Auto CMD12 Error Status
- Register */
-#define XSDPS_HOST_CTRL2_OFFSET 0x3EU /**< Host Control2 Register */
-#define XSDPS_CAPS_OFFSET 0x40U /**< Capabilities Register */
-#define XSDPS_CAPS_EXT_OFFSET 0x44U /**< Capabilities Extended */
-#define XSDPS_MAX_CURR_CAPS_OFFSET 0x48U /**< Maximum Current
- Capabilities Register */
-#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4CU /**< Maximum Current
- Capabilities Ext Register */
-#define XSDPS_FE_ERR_INT_STS_OFFSET 0x52U /**< Force Event for
- Error Interrupt Status */
-#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50U /**< Auto CM12 Error Interrupt
- Status Register */
-#define XSDPS_ADMA_ERR_STS_OFFSET 0x54U /**< ADMA Error Status
- Register */
-#define XSDPS_ADMA_SAR_OFFSET 0x58U /**< ADMA System Address
- Register */
-#define XSDPS_ADMA_SAR_EXT_OFFSET 0x5CU /**< ADMA System Address
- Extended Register */
-#define XSDPS_PRE_VAL_1_OFFSET 0x60U /**< Preset Value Register */
-#define XSDPS_PRE_VAL_2_OFFSET 0x64U /**< Preset Value Register */
-#define XSDPS_PRE_VAL_3_OFFSET 0x68U /**< Preset Value Register */
-#define XSDPS_PRE_VAL_4_OFFSET 0x6CU /**< Preset Value Register */
-#define XSDPS_BOOT_TOUT_CTRL_OFFSET 0x70U /**< Boot timeout control
- register */
-
-#define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0U /**< Shared Bus Control
- Register */
-#define XSDPS_SLOT_INTR_STS_OFFSET 0xFCU /**< Slot Interrupt Status
- Register */
-#define XSDPS_HOST_CTRL_VER_OFFSET 0xFEU /**< Host Controller Version
- Register */
-
-/** @} */
-
-/** @name Control Register - Host control, Power control,
- * Block Gap control and Wakeup control
- *
- * This register contains bits for various configuration options of
- * the SD host controller. Read/Write apart from the reserved bits.
- * @{
- */
-
-#define XSDPS_HC_LED_MASK 0x00000001U /**< LED Control */
-#define XSDPS_HC_WIDTH_MASK 0x00000002U /**< Bus width */
-#define XSDPS_HC_BUS_WIDTH_4 0x00000002U
-#define XSDPS_HC_SPEED_MASK 0x00000004U /**< High Speed */
-#define XSDPS_HC_DMA_MASK 0x00000018U /**< DMA Mode Select */
-#define XSDPS_HC_DMA_SDMA_MASK 0x00000000U /**< SDMA Mode */
-#define XSDPS_HC_DMA_ADMA1_MASK 0x00000008U /**< ADMA1 Mode */
-#define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010U /**< ADMA2 Mode - 32 bit */
-#define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018U /**< ADMA2 Mode - 64 bit */
-#define XSDPS_HC_EXT_BUS_WIDTH 0x00000020U /**< Bus width - 8 bit */
-#define XSDPS_HC_CARD_DET_TL_MASK 0x00000040U /**< Card Detect Tst Lvl */
-#define XSDPS_HC_CARD_DET_SD_MASK 0x00000080U /**< Card Detect Sig Det */
-
-#define XSDPS_PC_BUS_PWR_MASK 0x00000001U /**< Bus Power Control */
-#define XSDPS_PC_BUS_VSEL_MASK 0x0000000EU /**< Bus Voltage Select */
-#define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000EU /**< Bus Voltage 3.3V */
-#define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000CU /**< Bus Voltage 3.0V */
-#define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000AU /**< Bus Voltage 1.8V */
-#define XSDPS_PC_EMMC_HW_RST_MASK 0x00000010U /**< HW reset for eMMC */
-
-#define XSDPS_BGC_STP_REQ_MASK 0x00000001U /**< Block Gap Stop Req */
-#define XSDPS_BGC_CNT_REQ_MASK 0x00000002U /**< Block Gap Cont Req */
-#define XSDPS_BGC_RWC_MASK 0x00000004U /**< Block Gap Rd Wait */
-#define XSDPS_BGC_INTR_MASK 0x00000008U /**< Block Gap Intr */
-#define XSDPS_BGC_SPI_MODE_MASK 0x00000010U /**< Block Gap SPI Mode */
-#define XSDPS_BGC_BOOT_EN_MASK 0x00000020U /**< Block Gap Boot Enb */
-#define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040U /**< Block Gap Alt BootEn */
-#define XSDPS_BGC_BOOT_ACK_MASK 0x00000080U /**< Block Gap Boot Ack */
-
-#define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001U /**< Wakeup Card Intr */
-#define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002U /**< Wakeup Card Insert */
-#define XSDPS_WC_WUP_ON_REM_MASK 0x00000004U /**< Wakeup Card Removal */
-
-/** @} */
-
-/** @name Control Register - Clock control, Timeout control & Software reset
- *
- * This register contains bits for configuration options of clock, timeout and
- * software reset.
- * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
- * @{
- */
-
-#define XSDPS_CC_INT_CLK_EN_MASK 0x00000001U /**< INT clk enable */
-#define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002U /**< INT clk stable */
-#define XSDPS_CC_SD_CLK_EN_MASK 0x00000004U /**< SD clk enable */
-#define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020U /**< SD clk gen selection */
-#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x00000003U /**< SD clk freq sel upper */
-#define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x000000FFU /**< SD clk freq sel */
-#define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000U /**< Divider 256 */
-#define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000U /**< Divider 128 */
-#define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000U /**< Divider 64 */
-#define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000U /**< Divider 32 */
-#define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800U /**< Divider 16 */
-#define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400U /**< Divider 8 */
-#define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200U /**< Divider 4 */
-#define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100U /**< Divider 2 */
-#define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000U /**< Base clock */
-#define XSDPS_CC_MAX_DIV_CNT 256U /**< Max divider count */
-#define XSDPS_CC_EXT_MAX_DIV_CNT 2046U /**< Max extended divider count */
-#define XSDPS_CC_EXT_DIV_SHIFT 6U /**< Ext divider shift */
-
-#define XSDPS_TC_CNTR_VAL_MASK 0x0000000FU /**< Data timeout counter */
-
-#define XSDPS_SWRST_ALL_MASK 0x00000001U /**< Software Reset All */
-#define XSDPS_SWRST_CMD_LINE_MASK 0x00000002U /**< Software reset for CMD line */
-#define XSDPS_SWRST_DAT_LINE_MASK 0x00000004U /**< Software reset for DAT line */
-
-#define XSDPS_CC_MAX_NUM_OF_DIV 9U /**< Max number of Clock dividers */
-#define XSDPS_CC_DIV_SHIFT 8U /**< Clock Divider shift */
-
-/** @} */
-
-/** @name SD Interrupt Registers
- *
- * Normal and Error Interrupt Status Register
- * This register shows the normal and error interrupt status.
- * Status enable register affects reads of this register.
- * If Signal enable register is set and the corresponding status bit is set,
- * interrupt is generated.
- * Write to clear except
- * Error_interrupt and Card_Interrupt bits - Read only
- *
- * Normal and Error Interrupt Status Enable Register
- * Setting this register bits enables Interrupt status.
- * Read/Write except Fixed_to_0 bit (Read only)
- *
- * Normal and Error Interrupt Signal Enable Register
- * This register is used to select which interrupt status is
- * indicated to the Host System as the interrupt.
- * Read/Write except Fixed_to_0 bit (Read only)
- *
- * All three registers have same bit definitions
- * @{
- */
-
-#define XSDPS_INTR_CC_MASK 0x00000001U /**< Command Complete */
-#define XSDPS_INTR_TC_MASK 0x00000002U /**< Transfer Complete */
-#define XSDPS_INTR_BGE_MASK 0x00000004U /**< Block Gap Event */
-#define XSDPS_INTR_DMA_MASK 0x00000008U /**< DMA Interrupt */
-#define XSDPS_INTR_BWR_MASK 0x00000010U /**< Buffer Write Ready */
-#define XSDPS_INTR_BRR_MASK 0x00000020U /**< Buffer Read Ready */
-#define XSDPS_INTR_CARD_INSRT_MASK 0x00000040U /**< Card Insert */
-#define XSDPS_INTR_CARD_REM_MASK 0x00000080U /**< Card Remove */
-#define XSDPS_INTR_CARD_MASK 0x00000100U /**< Card Interrupt */
-#define XSDPS_INTR_INT_A_MASK 0x00000200U /**< INT A Interrupt */
-#define XSDPS_INTR_INT_B_MASK 0x00000400U /**< INT B Interrupt */
-#define XSDPS_INTR_INT_C_MASK 0x00000800U /**< INT C Interrupt */
-#define XSDPS_INTR_RE_TUNING_MASK 0x00001000U /**< Re-Tuning Interrupt */
-#define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00002000U /**< Boot Ack Recv
- Interrupt */
-#define XSDPS_INTR_BOOT_TERM_MASK 0x00004000U /**< Boot Terminate
- Interrupt */
-#define XSDPS_INTR_ERR_MASK 0x00008000U /**< Error Interrupt */
-#define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFFU
-
-#define XSDPS_INTR_ERR_CT_MASK 0x00000001U /**< Command Timeout
- Error */
-#define XSDPS_INTR_ERR_CCRC_MASK 0x00000002U /**< Command CRC Error */
-#define XSDPS_INTR_ERR_CEB_MASK 0x00000004U /**< Command End Bit
- Error */
-#define XSDPS_INTR_ERR_CI_MASK 0x00000008U /**< Command Index Error */
-#define XSDPS_INTR_ERR_DT_MASK 0x00000010U /**< Data Timeout Error */
-#define XSDPS_INTR_ERR_DCRC_MASK 0x00000020U /**< Data CRC Error */
-#define XSDPS_INTR_ERR_DEB_MASK 0x00000040U /**< Data End Bit Error */
-#define XSDPS_INTR_ERR_CUR_LMT_MASK 0x00000080U /**< Current Limit Error */
-#define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100U /**< Auto CMD12 Error */
-#define XSDPS_INTR_ERR_ADMA_MASK 0x00000200U /**< ADMA Error */
-#define XSDPS_INTR_ERR_TR_MASK 0x00001000U /**< Tuning Error */
-#define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000U /**< Vendor Specific
- Error */
-#define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FFU /**< Mask for error bits */
-/** @} */
-
-/** @name Block Size and Block Count Register
- *
- * This register contains the block count for current transfer,
- * block size and SDMA buffer size.
- * Read/Write except for reserved bits.
- * @{
- */
-
-#define XSDPS_BLK_SIZE_MASK 0x00000FFFU /**< Transfer Block Size */
-#define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000U /**< Host SDMA Buffer Size */
-#define XSDPS_BLK_SIZE_1024 0x400U
-#define XSDPS_BLK_SIZE_2048 0x800U
-#define XSDPS_BLK_CNT_MASK 0x0000FFFFU /**< Block Count for
- Current Transfer */
-
-/** @} */
-
-/** @name Transfer Mode and Command Register
- *
- * The Transfer Mode register is used to control the data transfers and
- * Command register is used for command generation
- * Read/Write except for reserved bits.
- * @{
- */
-
-#define XSDPS_TM_DMA_EN_MASK 0x00000001U /**< DMA Enable */
-#define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002U /**< Block Count Enable */
-#define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004U /**< Auto CMD12 Enable */
-#define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010U /**< Data Transfer
- Direction Select */
-#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020U /**< Multi/Single
- Block Select */
-
-#define XSDPS_CMD_RESP_SEL_MASK 0x00000003U /**< Response Type
- Select */
-#define XSDPS_CMD_RESP_NONE_MASK 0x00000000U /**< No Response */
-#define XSDPS_CMD_RESP_L136_MASK 0x00000001U /**< Response length 138 */
-#define XSDPS_CMD_RESP_L48_MASK 0x00000002U /**< Response length 48 */
-#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003U /**< Response length 48 &
- check busy after
- response */
-#define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008U /**< Command CRC Check
- Enable */
-#define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010U /**< Command Index Check
- Enable */
-#define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020U /**< Data Present Select */
-#define XSDPS_CMD_TYPE_MASK 0x000000C0U /**< Command Type */
-#define XSDPS_CMD_TYPE_NORM_MASK 0x00000000U /**< CMD Type - Normal */
-#define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040U /**< CMD Type - Suspend */
-#define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080U /**< CMD Type - Resume */
-#define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0U /**< CMD Type - Abort */
-#define XSDPS_CMD_MASK 0x00003F00U /**< Command Index Mask -
- Set to CMD0-63,
- AMCD0-63 */
-
-/** @} */
-
-/** @name Auto CMD Error Status Register
- *
- * This register is read only register which contains
- * information about the error status of Auto CMD 12 and 23.
- * Read Only
- * @{
- */
-#define XSDPS_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
- executed */
-#define XSDPS_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
- Error */
-#define XSDPS_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
-#define XSDPS_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
- Error */
-#define XSDPS_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
-#define XSDPS_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
- Auto CMD12 Error */
-/** @} */
-
-/** @name Host Control2 Register
- *
- * This register contains extended configuration bits.
- * Read Write
- * @{
- */
-#define XSDPS_HC2_UHS_MODE_MASK 0x0007U /**< UHS Mode select bits */
-#define XSDPS_HC2_UHS_MODE_SDR12_MASK 0x0000U /**< SDR12 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_SDR25_MASK 0x0001U /**< SDR25 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_SDR50_MASK 0x0002U /**< SDR50 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_SDR104_MASK 0x0003U /**< SDR104 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_DDR50_MASK 0x0004U /**< DDR50 UHS Mode */
-#define XSDPS_HC2_1V8_EN_MASK 0x0008U /**< 1.8V Signal Enable */
-#define XSDPS_HC2_DRV_STR_SEL_MASK 0x0030U /**< Driver Strength
- Selection */
-#define XSDPS_HC2_DRV_STR_B_MASK 0x0000U /**< Driver Strength B */
-#define XSDPS_HC2_DRV_STR_A_MASK 0x0010U /**< Driver Strength A */
-#define XSDPS_HC2_DRV_STR_C_MASK 0x0020U /**< Driver Strength C */
-#define XSDPS_HC2_DRV_STR_D_MASK 0x0030U /**< Driver Strength D */
-#define XSDPS_HC2_EXEC_TNG_MASK 0x0040U /**< Execute Tuning */
-#define XSDPS_HC2_SAMP_CLK_SEL_MASK 0x0080U /**< Sampling Clock
- Selection */
-#define XSDPS_HC2_ASYNC_INTR_EN_MASK 0x4000U /**< Asynchronous Interrupt
- Enable */
-#define XSDPS_HC2_PRE_VAL_EN_MASK 0x8000U /**< Preset Value Enable */
-
-/** @} */
-
-/** @name Capabilities Register
- *
- * Capabilities register is a read only register which contains
- * information about the host controller.
- * Sufficient if read once after power on.
- * Read Only
- * @{
- */
-#define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003FU /**< Timeout clock freq
- select */
-#define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080U /**< Timeout clock unit -
- MHz/KHz */
-#define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000U /**< Max block length */
-#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000U /**< Max block 512 bytes */
-#define XSDPS_CAP_MAX_BL_LN_1024_MASK 0x00010000U /**< Max block 1024 bytes */
-#define XSDPS_CAP_MAX_BL_LN_2048_MASK 0x00020000U /**< Max block 2048 bytes */
-#define XSDPS_CAP_MAX_BL_LN_4096_MASK 0x00030000U /**< Max block 4096 bytes */
-
-#define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000U /**< Extended media bus */
-#define XSDPS_CAP_ADMA2_MASK 0x00080000U /**< ADMA2 support */
-#define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000U /**< High speed support */
-#define XSDPS_CAP_SDMA_MASK 0x00400000U /**< SDMA support */
-#define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000U /**< Suspend/Resume
- support */
-#define XSDPS_CAP_VOLT_3V3_MASK 0x01000000U /**< 3.3V support */
-#define XSDPS_CAP_VOLT_3V0_MASK 0x02000000U /**< 3.0V support */
-#define XSDPS_CAP_VOLT_1V8_MASK 0x04000000U /**< 1.8V support */
-
-#define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000U /**< 64 bit system bus
- support */
-/* Spec 2.0 */
-#define XSDPS_CAP_INTR_MODE_MASK 0x08000000U /**< Interrupt mode
- support */
-#define XSDPS_CAP_SPI_MODE_MASK 0x20000000U /**< SPI mode */
-#define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x40000000U /**< SPI block mode */
-
-
-/* Spec 3.0 */
-#define XSDPS_CAPS_ASYNC_INTR_MASK 0x20000000U /**< Async Interrupt
- support */
-#define XSDPS_CAPS_SLOT_TYPE_MASK 0xC0000000U /**< Slot Type */
-#define XSDPS_CAPS_REM_CARD 0x00000000U /**< Removable Slot */
-#define XSDPS_CAPS_EMB_SLOT 0x40000000U /**< Embedded Slot */
-#define XSDPS_CAPS_SHR_BUS 0x80000000U /**< Shared Bus Slot */
-
-#define XSDPS_ECAPS_SDR50_MASK 0x00000001U /**< SDR50 Mode support */
-#define XSDPS_ECAPS_SDR104_MASK 0x00000002U /**< SDR104 Mode support */
-#define XSDPS_ECAPS_DDR50_MASK 0x00000004U /**< DDR50 Mode support */
-#define XSDPS_ECAPS_DRV_TYPE_A_MASK 0x00000010U /**< DriverType A support */
-#define XSDPS_ECAPS_DRV_TYPE_C_MASK 0x00000020U /**< DriverType C support */
-#define XSDPS_ECAPS_DRV_TYPE_D_MASK 0x00000040U /**< DriverType D support */
-#define XSDPS_ECAPS_TMR_CNT_MASK 0x00000F00U /**< Timer Count for
- Re-tuning */
-#define XSDPS_ECAPS_USE_TNG_SDR50_MASK 0x00002000U /**< SDR50 Mode needs
- tuning */
-#define XSDPS_ECAPS_RE_TNG_MODES_MASK 0x0000C000U /**< Re-tuning modes
- support */
-#define XSDPS_ECAPS_RE_TNG_MODE1_MASK 0x00000000U /**< Re-tuning mode 1 */
-#define XSDPS_ECAPS_RE_TNG_MODE2_MASK 0x00004000U /**< Re-tuning mode 2 */
-#define XSDPS_ECAPS_RE_TNG_MODE3_MASK 0x00008000U /**< Re-tuning mode 3 */
-#define XSDPS_ECAPS_CLK_MULT_MASK 0x00FF0000U /**< Clock Multiplier value
- for Programmable clock
- mode */
-#define XSDPS_ECAPS_SPI_MODE_MASK 0x01000000U /**< SPI mode */
-#define XSDPS_ECAPS_SPI_BLK_MODE_MASK 0x02000000U /**< SPI block mode */
-
-/** @} */
-
-/** @name Present State Register
- *
- * Gives the current status of the host controller
- * Read Only
- * @{
- */
-
-#define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001U /**< Command inhibit - CMD */
-#define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002U /**< Command Inhibit - DAT */
-#define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004U /**< DAT line active */
-#define XSDPS_PSR_RE_TUNING_REQ_MASK 0x00000008U /**< Re-tuning request */
-#define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100U /**< Write transfer active */
-#define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200U /**< Read transfer active */
-#define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400U /**< Buffer write enable */
-#define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800U /**< Buffer read enable */
-#define XSDPS_PSR_CARD_INSRT_MASK 0x00010000U /**< Card inserted */
-#define XSDPS_PSR_CARD_STABLE_MASK 0x00020000U /**< Card state stable */
-#define XSDPS_PSR_CARD_DPL_MASK 0x00040000U /**< Card detect pin level */
-#define XSDPS_PSR_WPS_PL_MASK 0x00080000U /**< Write protect switch
- pin level */
-#define XSDPS_PSR_DAT30_SG_LVL_MASK 0x00F00000U /**< Data 3:0 signal lvl */
-#define XSDPS_PSR_CMD_SG_LVL_MASK 0x01000000U /**< Cmd Line signal lvl */
-#define XSDPS_PSR_DAT74_SG_LVL_MASK 0x1E000000U /**< Data 7:4 signal lvl */
-
-/** @} */
-
-/** @name Maximum Current Capabilities Register
- *
- * This register is read only register which contains
- * information about current capabilities at each voltage levels.
- * Read Only
- * @{
- */
-#define XSDPS_MAX_CUR_CAPS_1V8_MASK 0x00000F00U /**< Maximum Current
- Capability at 1.8V */
-#define XSDPS_MAX_CUR_CAPS_3V0_MASK 0x000000F0U /**< Maximum Current
- Capability at 3.0V */
-#define XSDPS_MAX_CUR_CAPS_3V3_MASK 0x0000000FU /**< Maximum Current
- Capability at 3.3V */
-/** @} */
-
-
-/** @name Force Event for Auto CMD Error Status Register
- *
- * This register is write only register which contains
- * control bits to generate events for Auto CMD error status.
- * Write Only
- * @{
- */
-#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
- executed */
-#define XSDPS_FE_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
- Error */
-#define XSDPS_FE_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
-#define XSDPS_FE_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
- Error */
-#define XSDPS_FE_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
-#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
- Auto CMD12 Error */
-/** @} */
-
-
-
-/** @name Force Event for Error Interrupt Status Register
- *
- * This register is write only register which contains
- * control bits to generate events of error interrupt status register.
- * Write Only
- * @{
- */
-#define XSDPS_FE_INTR_ERR_CT_MASK 0x0001U /**< Command Timeout
- Error */
-#define XSDPS_FE_INTR_ERR_CCRC_MASK 0x0002U /**< Command CRC Error */
-#define XSDPS_FE_INTR_ERR_CEB_MASK 0x0004U /**< Command End Bit
- Error */
-#define XSDPS_FE_INTR_ERR_CI_MASK 0x0008U /**< Command Index Error */
-#define XSDPS_FE_INTR_ERR_DT_MASK 0x0010U /**< Data Timeout Error */
-#define XSDPS_FE_INTR_ERR_DCRC_MASK 0x0020U /**< Data CRC Error */
-#define XSDPS_FE_INTR_ERR_DEB_MASK 0x0040U /**< Data End Bit Error */
-#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK 0x0080U /**< Current Limit Error */
-#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK 0x0100U /**< Auto CMD Error */
-#define XSDPS_FE_INTR_ERR_ADMA_MASK 0x0200U /**< ADMA Error */
-#define XSDPS_FE_INTR_ERR_TR_MASK 0x1000U /**< Target Response */
-#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK 0xE000U /**< Vendor Specific
- Error */
-
-/** @} */
-
-/** @name ADMA Error Status Register
- *
- * This register is read only register which contains
- * status information about ADMA errors.
- * Read Only
- * @{
- */
-#define XSDPS_ADMA_ERR_MM_LEN_MASK 0x04U /**< ADMA Length Mismatch
- Error */
-#define XSDPS_ADMA_ERR_STATE_MASK 0x03U /**< ADMA Error State */
-#define XSDPS_ADMA_ERR_STATE_STOP_MASK 0x00U /**< ADMA Error State
- STOP */
-#define XSDPS_ADMA_ERR_STATE_FDS_MASK 0x01U /**< ADMA Error State
- FDS */
-#define XSDPS_ADMA_ERR_STATE_TFR_MASK 0x03U /**< ADMA Error State
- TFR */
-/** @} */
-
-/** @name Preset Values Register
- *
- * This register is read only register which contains
- * preset values for each of speed modes.
- * Read Only
- * @{
- */
-#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK 0x03FFU /**< SDCLK Frequency
- Select Value */
-#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK 0x0400U /**< Clock Generator
- Mode Select */
-#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK 0xC000U /**< Driver Strength
- Select Value */
-
-/** @} */
-
-/** @name Slot Interrupt Status Register
- *
- * This register is read only register which contains
- * interrupt slot signal for each slot.
- * Read Only
- * @{
- */
-#define XSDPS_SLOT_INTR_STS_INT_MASK 0x0007U /**< Interrupt Signal
- mask */
-
-/** @} */
-
-/** @name Host Controller Version Register
- *
- * This register is read only register which contains
- * Host Controller and Vendor Specific version.
- * Read Only
- * @{
- */
-#define XSDPS_HC_VENDOR_VER 0xFF00U /**< Vendor
- Specification
- version mask */
-#define XSDPS_HC_SPEC_VER_MASK 0x00FFU /**< Host
- Specification
- version mask */
-#define XSDPS_HC_SPEC_V3 0x0002U /**< HC spec version 3 */
-#define XSDPS_HC_SPEC_V2 0x0001U /**< HC spec version 2 */
-#define XSDPS_HC_SPEC_V1 0x0000U /**< HC spec version 1 */
-/** @} */
-
-/** @name Block size mask for 512 bytes
- *
- * Block size mask for 512 bytes - This is the default block size.
- * @{
- */
-
-#define XSDPS_BLK_SIZE_512_MASK 0x200U /**< Blk Size 512 */
-
-/** @} */
-
-/** @name Commands
- *
- * Constant definitions for commands and response related to SD
- * @{
- */
-/**
- * Command/Response related to SD/eMMC
- */
-
-#define XSDPS_APP_CMD_PREFIX 0x8000U
-#define CMD0 0x0000U
-#define CMD1 0x0100U
-#define CMD2 0x0200U
-#define CMD3 0x0300U
-#define CMD4 0x0400U
-#define CMD5 0x0500U
-#define CMD6 0x0600U
-#define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600U)
-#define CMD7 0x0700U
-#define CMD8 0x0800U
-#define CMD9 0x0900U
-#define CMD10 0x0A00U
-#define CMD11 0x0B00U
-#define CMD12 0x0C00U
-#define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00U)
-#define CMD16 0x1000U
-#define CMD17 0x1100U
-#define CMD18 0x1200U
-#define CMD19 0x1300U
-#define CMD21 0x1500U
-#define CMD23 0x1700U
-#define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700U)
-#define CMD24 0x1800U
-#define CMD25 0x1900U
-#define CMD41 0x2900U
-#define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900U)
-#define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00U)
-#define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300U)
-#define CMD52 0x3400U
-#define CMD55 0x3700U
-#define CMD58 0x3A00U
-
-#define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK
-#define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
- (u32)XSDPS_CMD_INX_CHK_EN_MASK
-
-#define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
- (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
-
-#define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
-#define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK
-
-#define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
- (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
-
-/** @} */
-
-/**
- * @name Card Interface
- * @{
- */
-/**
- * Card Interface Conditions Definitions
- */
-#define XSDPS_CIC_CHK_PATTERN 0xAAU
-#define XSDPS_CIC_VOLT_MASK (0xFU<<8)
-#define XSDPS_CIC_VOLT_2V7_3V6 (1U<<8)
-#define XSDPS_CIC_VOLT_LOW (1U<<9)
-/** @} */
-
-/**
- * @name OCR
- * @{
- */
-/**
- * Operation Conditions Register Definitions
- */
-#define XSDPS_OCR_PWRUP_STS (1U<<31)
-#define XSDPS_OCR_CC_STS (1U<<30)
-#define XSDPS_OCR_S18 (1U<<24)
-#define XSDPS_OCR_3V5_3V6 (1U<<23)
-#define XSDPS_OCR_3V4_3V5 (1U<<22)
-#define XSDPS_OCR_3V3_3V4 (1U<<21)
-#define XSDPS_OCR_3V2_3V3 (1U<<20)
-#define XSDPS_OCR_3V1_3V2 (1U<<19)
-#define XSDPS_OCR_3V0_3V1 (1U<<18)
-#define XSDPS_OCR_2V9_3V0 (1U<<17)
-#define XSDPS_OCR_2V8_2V9 (1U<<16)
-#define XSDPS_OCR_2V7_2V8 (1U<<15)
-#define XSDPS_OCR_1V7_1V95 (1U<<7)
-#define XSDPS_OCR_HIGH_VOL 0x00FF8000U
-#define XSDPS_OCR_LOW_VOL 0x00000080U
-/** @} */
-
-/**
- * @name Card Configuration
- * @{
- */
-/**
- * SD Card Configuration Register Definitions
- */
-#define XSDPS_SCR_REG_LEN 8U
-#define XSDPS_SCR_STRUCT_MASK (0xFU<<28)
-#define XSDPS_SCR_SPEC_MASK (0xFU<<24)
-#define XSDPS_SCR_SPEC_1V0 0U
-#define XSDPS_SCR_SPEC_1V1 (1U<<24)
-#define XSDPS_SCR_SPEC_2V0_3V0 (2U<<24)
-#define XSDPS_SCR_MEM_VAL_AF_ERASE (1U<<23)
-#define XSDPS_SCR_SEC_SUPP_MASK (7U<<20)
-#define XSDPS_SCR_SEC_SUPP_NONE 0U
-#define XSDPS_SCR_SEC_SUPP_1V1 (2U<<20)
-#define XSDPS_SCR_SEC_SUPP_2V0 (3U<<20)
-#define XSDPS_SCR_SEC_SUPP_3V0 (4U<<20)
-#define XSDPS_SCR_BUS_WIDTH_MASK (0xFU<<16)
-#define XSDPS_SCR_BUS_WIDTH_1 (1U<<16)
-#define XSDPS_SCR_BUS_WIDTH_4 (4U<<16)
-#define XSDPS_SCR_SPEC3_MASK (1U<<12)
-#define XSDPS_SCR_SPEC3_2V0 0U
-#define XSDPS_SCR_SPEC3_3V0 (1U<<12)
-#define XSDPS_SCR_CMD_SUPP_MASK 0x3U
-#define XSDPS_SCR_CMD23_SUPP (1U<<1)
-#define XSDPS_SCR_CMD20_SUPP (1U<<0)
-/** @} */
-
-/**
- * @name Card Status
- * @{
- */
-/**
- * Card Status Register Definitions
- */
-#define XSDPS_CD_STS_OUT_OF_RANGE (1U<<31)
-#define XSDPS_CD_STS_ADDR_ERR (1U<<30)
-#define XSDPS_CD_STS_BLK_LEN_ERR (1U<<29)
-#define XSDPS_CD_STS_ER_SEQ_ERR (1U<<28)
-#define XSDPS_CD_STS_ER_PRM_ERR (1U<<27)
-#define XSDPS_CD_STS_WP_VIO (1U<<26)
-#define XSDPS_CD_STS_IS_LOCKED (1U<<25)
-#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL (1U<<24)
-#define XSDPS_CD_STS_CMD_CRC_ERR (1U<<23)
-#define XSDPS_CD_STS_ILGL_CMD (1U<<22)
-#define XSDPS_CD_STS_CARD_ECC_FAIL (1U<<21)
-#define XSDPS_CD_STS_CC_ERR (1U<<20)
-#define XSDPS_CD_STS_ERR (1U<<19)
-#define XSDPS_CD_STS_CSD_OVRWR (1U<<16)
-#define XSDPS_CD_STS_WP_ER_SKIP (1U<<15)
-#define XSDPS_CD_STS_CARD_ECC_DIS (1U<<14)
-#define XSDPS_CD_STS_ER_RST (1U<<13)
-#define XSDPS_CD_STS_CUR_STATE (0xFU<<9)
-#define XSDPS_CD_STS_RDY_FOR_DATA (1U<<8)
-#define XSDPS_CD_STS_APP_CMD (1U<<5)
-#define XSDPS_CD_STS_AKE_SEQ_ERR (1U<<2)
-/** @} */
-
-/**
- * @name Switch function
- * @{
- */
-/**
- * Switch Function Definitions CMD6
- */
-#define XSDPS_SWITCH_SD_RESP_LEN 64U
-
-#define XSDPS_SWITCH_FUNC_SWITCH (1U<<31)
-#define XSDPS_SWITCH_FUNC_CHECK 0U
-/** @} */
-
-/**
- * @name Mode Function
- * @{
- */
-/**
- * Mode function groups definitions.
- */
-#define XSDPS_MODE_FUNC_GRP1 1U
-#define XSDPS_MODE_FUNC_GRP2 2U
-#define XSDPS_MODE_FUNC_GRP3 3U
-#define XSDPS_MODE_FUNC_GRP4 4U
-#define XSDPS_MODE_FUNC_GRP5 5U
-#define XSDPS_MODE_FUNC_GRP6 6U
-
-#define XSDPS_FUNC_GRP_DEF_VAL 0xFU
-#define XSDPS_FUNC_ALL_GRP_DEF_VAL 0xFFFFFFU
-/** @} */
-
-/**
- * @name Operating modes
- * @{
- */
-/**
- * SD operating modes in UHS.
- */
-#define XSDPS_ACC_MODE_DEF_SDR12 0U
-#define XSDPS_ACC_MODE_HS_SDR25 1U
-#define XSDPS_ACC_MODE_SDR50 2U
-#define XSDPS_ACC_MODE_SDR104 3U
-#define XSDPS_ACC_MODE_DDR50 4U
-/** @} */
-
-/**
- * @name General definitions
- * @{
- */
-/**
- * Definitions related to Driver strength, Current limit and
- * CSD specific data.
- */
-#define XSDPS_CMD_SYS_ARG_SHIFT 4U
-#define XSDPS_CMD_SYS_DEF 0U
-#define XSDPS_CMD_SYS_eC 1U
-#define XSDPS_CMD_SYS_OTP 3U
-#define XSDPS_CMD_SYS_ASSD 4U
-#define XSDPS_CMD_SYS_VEND 5U
-
-#define XSDPS_DRV_TYPE_ARG_SHIFT 8U
-#define XSDPS_DRV_TYPE_B 0U
-#define XSDPS_DRV_TYPE_A 1U
-#define XSDPS_DRV_TYPE_C 2U
-#define XSDPS_DRV_TYPE_D 3U
-
-#define XSDPS_CUR_LIM_ARG_SHIFT 12U
-#define XSDPS_CUR_LIM_200 0U
-#define XSDPS_CUR_LIM_400 1U
-#define XSDPS_CUR_LIM_600 2U
-#define XSDPS_CUR_LIM_800 3U
-
-#define CSD_SPEC_VER_MASK 0x3C0000U
-#define READ_BLK_LEN_MASK 0x00000F00U
-#define C_SIZE_MULT_MASK 0x00000380U
-#define C_SIZE_LOWER_MASK 0xFFC00000U
-#define C_SIZE_UPPER_MASK 0x00000003U
-#define CSD_STRUCT_MASK 0x00C00000U
-#define CSD_V2_C_SIZE_MASK 0x3FFFFF00U
-/** @} */
-
-/**
- * @name Extended Card Specific Data
- * @{
- */
-/**
- * EXT_CSD field definitions
- */
-#define XSDPS_EXT_CSD_SIZE 512U
-
-#define EXT_CSD_WR_REL_PARAM_EN (1U<<2)
-
-#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40U)
-#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10U)
-#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04U)
-#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01U)
-
-#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7U)
-#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1U)
-#define EXT_CSD_PART_CONFIG_ACC_BOOT1 (0x2U)
-#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U)
-#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U)
-#define EXT_CSD_PART_CONFIG_BYTE (179U)
-#define XSDPS_MMC_PART_CFG_0_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
- | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
- | ((u32)(0U) << 8U))
-
-#define XSDPS_MMC_PART_CFG_1_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
- | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
- | ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT0 << 8U))
-
-#define XSDPS_MMC_PART_CFG_2_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
- | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
- | ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT1 << 8U))
-
-#define EXT_CSD_PART_SUPPORT_PART_EN (0x1U)
-
-#define EXT_CSD_CMD_SET_NORMAL (1U<<0)
-#define EXT_CSD_CMD_SET_SECURE (1U<<1)
-#define EXT_CSD_CMD_SET_CPSECURE (1U<<2)
-
-#define EXT_CSD_CARD_TYPE_26 (1U<<0) /* Card can run at 26MHz */
-#define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */
-#define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */
-#define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */
- /* DDR mode @1.8V or 3V I/O */
-#define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */
- /* DDR mode @1.2V I/O */
-#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
- | EXT_CSD_CARD_TYPE_DDR_1_2V)
-#define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */
-#define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */
- /* SDR mode @1.2V I/O */
-#define EXT_CSD_BUS_WIDTH_BYTE 183U
-#define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */
-#define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */
-#define EXT_CSD_BUS_WIDTH_8_BIT 2U /* Card is in 8 bit mode */
-#define EXT_CSD_BUS_WIDTH_DDR_4_BIT 5U /* Card is in 4 bit DDR mode */
-#define EXT_CSD_BUS_WIDTH_DDR_8_BIT 6U /* Card is in 8 bit DDR mode */
-
-#define EXT_CSD_HS_TIMING_BYTE 185U
-#define EXT_CSD_HS_TIMING_DEF 0U
-#define EXT_CSD_HS_TIMING_HIGH 1U /* Card is in high speed mode */
-#define EXT_CSD_HS_TIMING_HS200 2U /* Card is in HS200 mode */
-
-#define EXT_CSD_RST_N_FUN_BYTE 162U
-#define EXT_CSD_RST_N_FUN_TEMP_DIS 0U /* RST_n signal is temporarily disabled */
-#define EXT_CSD_RST_N_FUN_PERM_EN 1U /* RST_n signal is permanently enabled */
-#define EXT_CSD_RST_N_FUN_PERM_DIS 2U /* RST_n signal is permanently disabled */
-
-#define XSDPS_EXT_CSD_CMD_SET 0U
-#define XSDPS_EXT_CSD_SET_BITS 1U
-#define XSDPS_EXT_CSD_CLR_BITS 2U
-#define XSDPS_EXT_CSD_WRITE_BYTE 3U
-/** @} */
-
-/**
- * @name SD/eMMC Bus Speed and Bus Width Arguments
- * @{
- */
-/**
- * SD/MMC Arguments for Bus Speed and Bus Width.
- */
-#define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
- | ((u32)EXT_CSD_HS_TIMING_DEF << 8))
-
-#define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
- | ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
-
-#define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
- | ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
-
-#define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8))
-
-#define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
-
-#define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
-
-#define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
-
-#define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
-
-#define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
- | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
-
-#define XSDPS_MMC_DELAY_FOR_SWITCH 1000U
-
-/** @} */
-
-/**
- * @name General Delay definitions
- * @{
- */
-/**
- * @400KHz, in usec
- */
-#define XSDPS_74CLK_DELAY 2960U
-#define XSDPS_100CLK_DELAY 4000U
-#define XSDPS_INIT_DELAY 10000U
-/** @} */
-
-#define XSDPS_DEF_VOLT_LVL XSDPS_PC_BUS_VSEL_3V0_MASK /**< Default voltage level */
-#define XSDPS_CARD_DEF_ADDR 0x1234U /**< Card Default address */
-
-#define XSDPS_CARD_SD 1U /**< SD card */
-#define XSDPS_CARD_MMC 2U /**< MMC card */
-#define XSDPS_CARD_SDIO 3U /**< SDIO card */
-#define XSDPS_CARD_SDCOMBO 4U /**< SDCOMBO card */
-#define XSDPS_CHIP_EMMC 5U /**< EMMC chip */
-
-
-/**
- *@name ADMA2 Descriptor related definitions
- * @{
- */
-/**
- * ADMA2 Descriptor related definitions
- */
-#define XSDPS_DESC_MAX_LENGTH 65536U
-
-#define XSDPS_DESC_VALID (0x1U << 0)
-#define XSDPS_DESC_END (0x1U << 1)
-#define XSDPS_DESC_INT (0x1U << 2)
-#define XSDPS_DESC_TRAN (0x2U << 4)
-
-/** @} */
-
-/* For changing clock frequencies */
-#define XSDPS_CLK_400_KHZ 400000U /**< 400 KHZ */
-#define XSDPS_CLK_50_MHZ 50000000U /**< 50 MHZ */
-#define XSDPS_CLK_52_MHZ 52000000U /**< 52 MHZ */
-#define XSDPS_SD_VER_1_0 0x1U /**< SD ver 1 */
-#define XSDPS_SD_VER_2_0 0x2U /**< SD ver 2 */
-#define XSDPS_SCR_BLKCNT 1U /**< SCR Block Count */
-#define XSDPS_SCR_BLKSIZE 8U /**< SCR Block Size */
-#define XSDPS_1_BIT_WIDTH 0x1U /**< Bus Width 1 */
-#define XSDPS_4_BIT_WIDTH 0x2U /**< Bus Width 4 */
-#define XSDPS_8_BIT_WIDTH 0x3U /**< Bus Width 8 */
-#define XSDPS_UHS_SPEED_MODE_SDR12 0x0U /**< SDR12 mode */
-#define XSDPS_UHS_SPEED_MODE_SDR25 0x1U /**< SDR25 mode */
-#define XSDPS_UHS_SPEED_MODE_SDR50 0x2U /**< SDR50 mode */
-#define XSDPS_UHS_SPEED_MODE_SDR104 0x3U /**< SDR104 mode */
-#define XSDPS_UHS_SPEED_MODE_DDR50 0x4U /**< DDR50 mode */
-#define XSDPS_HIGH_SPEED_MODE 0x5U /**< High Speed mode */
-#define XSDPS_DEFAULT_SPEED_MODE 0x6U /**< Default speed mode */
-#define XSDPS_HS200_MODE 0x7U /**< eMMC HS200 mode */
-#define XSDPS_DDR52_MODE 0x4U /**< eMMC DDR52 mode */
-#define XSDPS_SWITCH_CMD_BLKCNT 1U /**< Blk cnt for SWITCH cmd */
-#define XSDPS_SWITCH_CMD_BLKSIZE 64U /**< Blk sz for SWITCH cmd */
-#define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U /**< SWITCH cmd to Get HS */
-#define XSDPS_SWITCH_CMD_HS_SET 0x80FFFFF1U /**< SWITCH cmd to Set HS */
-#define XSDPS_SWITCH_CMD_SDR12_SET 0x80FFFFF0U /**< SWITCH cmd to Set SDR12 */
-#define XSDPS_SWITCH_CMD_SDR25_SET 0x80FFFFF1U /**< SWITCH cmd to Set SDR25 */
-#define XSDPS_SWITCH_CMD_SDR50_SET 0x80FFFFF2U /**< SWITCH cmd to Set SDR50 */
-#define XSDPS_SWITCH_CMD_SDR104_SET 0x80FFFFF3U /**< SWITCH cmd to Set SDR104 */
-#define XSDPS_SWITCH_CMD_DDR50_SET 0x80FFFFF4U /**< SWITCH cmd to Set DDR50 */
-#define XSDPS_EXT_CSD_CMD_BLKCNT 1U /**< Blk Cnt for EXT CSD */
-#define XSDPS_EXT_CSD_CMD_BLKSIZE 512U /**< Blk Sz for EXT CSD */
-#define XSDPS_TUNING_CMD_BLKCNT 1U /**< Blk Cnt for Tuning cmd */
-#define XSDPS_TUNING_CMD_BLKSIZE 64U /**< Blk Sz for Tuning cmd */
-#define XSDPS_SD_STATUS_BLKCNT 1U /**< Blk Cnt for SD status */
-#define XSDPS_SD_STATUS_BLKSIZE 64U /**< Blk Sz for SD status */
-
-#define XSDPS_HIGH_SPEED_MAX_CLK 50000000U /**< Max clk for HS mode */
-#define XSDPS_UHS_SDR104_MAX_CLK 208000000U /**< Max clk for SDR104 mode */
-#define XSDPS_UHS_SDR50_MAX_CLK 100000000U /**< Max clk for SDR50 mode */
-#define XSDPS_UHS_DDR50_MAX_CLK 50000000U /**< Max clk for DDR50 mode */
-#define XSDPS_UHS_SDR25_MAX_CLK 50000000U /**< Max clk for SDR25 mode */
-#define XSDPS_UHS_SDR12_MAX_CLK 25000000U /**< Max clk for SDR12 mode */
-
-#define SD_DRIVER_TYPE_B 0x01U /**< Driver Type B */
-#define SD_DRIVER_TYPE_A 0x02U /**< Driver Type A */
-#define SD_DRIVER_TYPE_C 0x04U /**< Driver Type C */
-#define SD_DRIVER_TYPE_D 0x08U /**< Driver Type D */
-#define SD_SET_CURRENT_LIMIT_200 0U /**< Current limit 200mA */
-#define SD_SET_CURRENT_LIMIT_400 1U /**< Current limit 400mA */
-#define SD_SET_CURRENT_LIMIT_600 2U /**< Current limit 600mA */
-#define SD_SET_CURRENT_LIMIT_800 3U /**< Current limit 800mA */
-
-#define SD_MAX_CURRENT_200 (1U << SD_SET_CURRENT_LIMIT_200) /**< Current limit 200mA Arg */
-#define SD_MAX_CURRENT_400 (1U << SD_SET_CURRENT_LIMIT_400) /**< Current limit 400mA Arg */
-#define SD_MAX_CURRENT_600 (1U << SD_SET_CURRENT_LIMIT_600) /**< Current limit 600mA Arg */
-#define SD_MAX_CURRENT_800 (1U << SD_SET_CURRENT_LIMIT_800) /**< Current limit 800mA Arg */
-
-#define XSDPS_SD_SDR12_MAX_CLK 25000000U /**< Max clk for SDR12 mode */
-#define XSDPS_SD_SDR25_MAX_CLK 50000000U /**< Max clk for SDR25 mode */
-#define XSDPS_SD_SDR50_MAX_CLK 100000000U /**< Max clk for SDR50 mode */
-#define XSDPS_SD_DDR50_MAX_CLK 50000000U /**< Max clk for DDR50 mode */
-#define XSDPS_SD_SDR104_MAX_CLK 208000000U /**< Max clk for SDR104 mode */
-/**
- * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller
- * than the clock value coming from the core. This value is kept to safely
- * switch to SDR104 mode if the SD card supports it.
- */
-#define XSDPS_SD_INPUT_MAX_CLK 175000000U
-
-#define XSDPS_MMC_HS200_MAX_CLK 200000000U /**< Max clk for MMC HS200 mode */
-#define XSDPS_MMC_HSD_MAX_CLK 52000000U /**< Max clk for MMC HSD mode */
-#define XSDPS_MMC_DDR_MAX_CLK 52000000U /**< Max clk for MMC DDR52 mode */
-
-/**
- * @name Card states
- * @{
- */
-/**
- * Definition for Card state.
- */
-#define XSDPS_CARD_STATE_IDLE 0U
-#define XSDPS_CARD_STATE_RDY 1U
-#define XSDPS_CARD_STATE_IDEN 2U
-#define XSDPS_CARD_STATE_STBY 3U
-#define XSDPS_CARD_STATE_TRAN 4U
-#define XSDPS_CARD_STATE_DATA 5U
-#define XSDPS_CARD_STATE_RCV 6U
-#define XSDPS_CARD_STATE_PROG 7U
-#define XSDPS_CARD_STATE_DIS 8U
-#define XSDPS_CARD_STATE_BTST 9U
-#define XSDPS_CARD_STATE_SLP 10U
-/** @} */
-
-#define XSDPS_SLOT_REM 0U /**< Removable slot */
-#define XSDPS_SLOT_EMB 1U /**< Embedded slot */
-
-#define XSDPS_WIDTH_8 8U /**< Bus width 8 */
-#define XSDPS_WIDTH_4 4U /**< Bus width 4 */
-
-/**
- * @name Tap delays
- * @{
- */
-/**
- * SD/eMMC ITAP and OTAP delays for different operating modes
- * for both Versal and ZynqMP platforms.
- */
-#ifdef versal
-#define SD_ITAPDLY_SEL_MASK 0x000000FFU
-#define SD_OTAPDLY_SEL_MASK 0x0000003FU
-#define SD_ITAPDLY 0x0000F0F8U
-#define SD_OTAPDLY 0x0000F0FCU
-#define SD0_DLL_CTRL 0x00000448U
-#define SD1_DLL_CTRL 0x000004C8U
-#define SD_DLL_RST 0x00000004U
-#define SD_ITAPCHGWIN 0x00000200U
-#define SD_ITAPDLYENA 0x00000100U
-#define SD_OTAPDLYENA 0x00000040U
-#define SD_OTAPDLYSEL_HS200_B0 0x00000002U
-#define SD_OTAPDLYSEL_HS200_B2 0x00000002U
-#define SD_ITAPDLYSEL_SD50 0x0000000EU
-#define SD_OTAPDLYSEL_SD50 0x00000003U
-#define SD_ITAPDLYSEL_SD_DDR50 0x00000036U
-#define SD_ITAPDLYSEL_EMMC_DDR50 0x0000001EU
-#define SD_OTAPDLYSEL_SD_DDR50 0x00000003U
-#define SD_OTAPDLYSEL_EMMC_DDR50 0x00000005U
-#define SD_ITAPDLYSEL_HSD 0x0000002CU
-#define SD_OTAPDLYSEL_SD_HSD 0x00000004U
-#define SD_OTAPDLYSEL_EMMC_HSD 0x00000005U
-#else
-#define SD0_ITAPDLY_SEL_MASK 0x000000FFU
-#define SD0_OTAPDLY_SEL_MASK 0x0000003FU
-#define SD1_ITAPDLY_SEL_MASK 0x00FF0000U
-#define SD1_OTAPDLY_SEL_MASK 0x003F0000U
-#define SD_DLL_CTRL 0x00000358U
-#define SD_ITAPDLY 0x00000314U
-#define SD_OTAPDLY 0x00000318U
-#define SD0_DLL_RST 0x00000004U
-#define SD1_DLL_RST 0x00040000U
-#define SD0_ITAPCHGWIN 0x00000200U
-#define SD0_ITAPDLYENA 0x00000100U
-#define SD0_OTAPDLYENA 0x00000040U
-#define SD1_ITAPCHGWIN 0x02000000U
-#define SD1_ITAPDLYENA 0x01000000U
-#define SD1_OTAPDLYENA 0x00400000U
-#define SD_OTAPDLYSEL_HS200_B0 0x00000003U
-#define SD_OTAPDLYSEL_HS200_B2 0x00000002U
-#define SD_ITAPDLYSEL_SD50 0x00000014U
-#define SD_OTAPDLYSEL_SD50 0x00000003U
-#define SD_ITAPDLYSEL_SD_DDR50 0x0000003DU
-#define SD_ITAPDLYSEL_EMMC_DDR50 0x00000012U
-#define SD_OTAPDLYSEL_SD_DDR50 0x00000004U
-#define SD_OTAPDLYSEL_EMMC_DDR50 0x00000006U
-#define SD_ITAPDLYSEL_HSD 0x00000015U
-#define SD_OTAPDLYSEL_SD_HSD 0x00000005U
-#define SD_OTAPDLYSEL_EMMC_HSD 0x00000006U
-#endif
-/** @} */
-
-#ifdef __MICROBLAZE__
-#define XPS_SYS_CTRL_BASEADDR 0xFF180000U /**< System controller Baseaddress */
-#endif
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#define XSdPs_In64 Xil_In64 /**< Low level 64-bit data read */
-#define XSdPs_Out64 Xil_Out64 /**< Low level 64-bit data write */
-
-#define XSdPs_In32 Xil_In32 /**< Low level 32-bit data read */
-#define XSdPs_Out32 Xil_Out32 /**< Low level 32-bit data write */
-
-#define XSdPs_In16 Xil_In16 /**< Low level 16-bit data read */
-#define XSdPs_Out16 Xil_Out16 /**< Low level 16-bit data write */
-
-#define XSdPs_In8 Xil_In8 /**< Low level 8-bit data read */
-#define XSdPs_Out8 Xil_Out8 /**< Low level 8-bit data write */
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param InstancePtr is the pointer to the sdps instance.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
-*
-******************************************************************************/
-#define XSdPs_ReadReg64(InstancePtr, RegOffset) \
- XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset)
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param InstancePtr is the pointer to the sdps instance.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
-* u64 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
- XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
- (RegisterValue))
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-#define XSdPs_ReadReg(BaseAddress, RegOffset) \
- XSdPs_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u32 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg >>= ((RegOffset & 0x3)*8);
- return (u16)Reg;
-#else
- return XSdPs_In16((BaseAddress) + (RegOffset));
-#endif
-}
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u16 RegisterValue)
-*
-******************************************************************************/
-
-static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg &= ~(0xFFFFU<<((RegOffset & 0x3)*8));
- Reg |= RegisterValue <<((RegOffset & 0x3)*8);
- XSdPs_Out32(BaseAddress, Reg);
-#else
- XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue));
-#endif
-}
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg >>= ((RegOffset & 0x3)*8);
- return (u8)Reg;
-#else
- return XSdPs_In8((BaseAddress) + (RegOffset));
-#endif
-}
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u8 RegisterValue)
-*
-******************************************************************************/
-static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg &= ~(0xFFU<<((RegOffset & 0x3)*8));
- Reg |= RegisterValue <<((RegOffset & 0x3)*8);
- XSdPs_Out32(BaseAddress, Reg);
-#else
- XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue));
-#endif
-}
-/***************************************************************************/
-/**
-* Macro to get present status register
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u8 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_GetPresentStatusReg(BaseAddress) \
- XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SD_HW_H_ */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/300c63545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/300c63545243001d18b399c1eb9b3628
deleted file mode 100644
index 4b6d75a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/300c63545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,261 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xscutimer_hw.h
-* @addtogroup scutimer_v2_3
-* @{
-*
-* This file contains the hardware interface to the Timer.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm 03/10/10 First release
-* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
-* and interrupt registers
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-#ifndef XSCUTIMER_HW_H /* prevent circular inclusions */
-#define XSCUTIMER_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- * Offsets of registers from the start of the device
- * @{
- */
-
-#define XSCUTIMER_LOAD_OFFSET 0x00U /**< Timer Load Register */
-#define XSCUTIMER_COUNTER_OFFSET 0x04U /**< Timer Counter Register */
-#define XSCUTIMER_CONTROL_OFFSET 0x08U /**< Timer Control Register */
-#define XSCUTIMER_ISR_OFFSET 0x0CU /**< Timer Interrupt
- Status Register */
-/* @} */
-
-/** @name Timer Control register
- * This register bits control the prescaler, Intr enable,
- * auto-reload and timer enable.
- * @{
- */
-
-#define XSCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
-#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8U
-#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004U /**< Intr enable */
-#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload */
-#define XSCUTIMER_CONTROL_ENABLE_MASK 0x00000001U /**< Timer enable */
-/* @} */
-
-/** @name Interrupt Status register
- * This register indicates the Timer counter register has reached zero.
- * @{
- */
-
-#define XSCUTIMER_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Write to the timer load register. This will also update the
-* timer counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetLoadReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer load register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer load register.
-*
-* @note C-style signature:
-* u32 XScuTimer_GetLoadReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetLoadReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the timer counter register.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the counter register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetCounterReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer counter register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer counter register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetCounterReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetCounterReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the timer load register. This will also update the
-* timer counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetControlReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer load register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer load register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetControlReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetControlReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the timer counter register.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the counter register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetIntrReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer counter register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer counter register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetIntrReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetIntrReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Read from the given Timer register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note C-style signature:
-* u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuTimer_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + (RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write to the given Timer register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + (RegOffset), (Data))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/407552555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/407552555243001d18b399c1eb9b3628
deleted file mode 100644
index 8abb888..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/407552555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,116 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xtime_l.c
-*
-* This file contains low level functions to get/set time from the Global Timer
-* register in the ARM Cortex A53 MP core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 5.00 pkp 05/29/14 First release
-* 5.05 pkp 04/13/16 Added XTime_StartTimer API to start the global timer
-* counter if it is disabled. Also XTime_GetTime calls
-* this API to ensure the global timer counter is enabled
-* 6.02 pkp 01/22/17 Added support for EL1 non-secure
-* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
-* displaying same warnings multiple times. It fixes CR#1090562.
-*
-*
-* @note None.
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "xtime_l.h"
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "bspconfig.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER)
-#pragma message ("For the sleep routines, Global timer is being used")
-#endif
-/****************************************************************************/
-/**
-* @brief Start the 64-bit physical timer counter.
-*
-* @return None.
-*
-* @note The timer is initialized only if it is disabled. If the timer is
-* already running this function does not perform any operation. This
-* API is effective only if BSP is built for EL3. For EL1 Non-secure,
-* it simply exits.
-*
-****************************************************************************/
-void XTime_StartTimer(void)
-{
- if (EL3 == 1){
- /* Enable the global timer counter only if it is disabled */
- if(((Xil_In32(XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET))
- & XIOU_SCNTRS_CNT_CNTRL_REG_EN_MASK) !=
- XIOU_SCNTRS_CNT_CNTRL_REG_EN){
- /*write frequency to System Time Stamp Generator Register*/
- Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_FREQ_REG_OFFSET),
- XIOU_SCNTRS_FREQ);
- /*Enable the timer/counter*/
- Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET)
- ,XIOU_SCNTRS_CNT_CNTRL_REG_EN);
- }
- }
-}
-/****************************************************************************/
-/**
-* @brief Timer of A53 runs continuously and the time can not be set as
-* desired. This API doesn't contain anything. It is defined to have
-* uniformity across platforms.
-*
-* @param Xtime_Global: 64bit value to be written to the physical timer
-* counter register. Since API does not do anything, the value is
-* not utilized.
-*
-* @return None.
-*
-****************************************************************************/
-void XTime_SetTime(XTime Xtime_Global)
-{
- (void) Xtime_Global;
-/*As the generic timer of A53 runs constantly time can not be set as desired
-so the API is left unimplemented*/
-}
-
-/****************************************************************************/
-/**
-* @brief Get the time from the physical timer counter register.
-*
-* @param Xtime_Global: Pointer to the 64-bit location to be updated with the
-* current value of physical timer counter register.
-*
-* @return None.
-*
-****************************************************************************/
-void XTime_GetTime(XTime *Xtime_Global)
-{
- if (EL3 == 1)
- /* Start global timer counter, it will only be enabled if it is disabled */
- XTime_StartTimer();
-
- *Xtime_Global = mfcp(CNTPCT_EL0);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/512c23595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/512c23595243001d18b399c1eb9b3628
deleted file mode 100644
index f25c28a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/512c23595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,427 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xreg_cortexr5.h
-*
-* This header file contains definitions for using inline assembler code. It is
-* written specifically for the GNU, IAR, ARMCC compiler.
-*
-* All of the ARM Cortex R5 GPRs, SPRs, and Debug Registers are defined along
-* with the positions of the bits within the registers.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 02/10/14 Initial version
-*
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- ----------------------------------------------------------
- * 1.00a jz 10/10/10 First release
- * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet
- * handling.
- * 2.3 bss 01/19/16 Modified XUsbPs_EpQueueRequest function to fix CR#873972
- * (moving of dTD Head/Tail Pointers properly).
- * 2.5 pm 02/20/20 Added ISO endpoint support.
- *
- ******************************************************************************/
-
-/***************************** Include Files **********************************/
-
-#include "xusbps.h"
-#include "xusbps_endpoint.h"
-
-/************************** Constant Definitions ******************************/
-
-/**************************** Type Definitions ********************************/
-
-/***************** Macros (Inline Functions) Definitions **********************/
-
-/************************** Variable Definitions ******************************/
-
-/************************** Function Prototypes *******************************/
-
-static void XUsbPs_IntrHandleTX(XUsbPs *InstancePtr, u32 EpCompl);
-static void XUsbPs_IntrHandleRX(XUsbPs *InstancePtr, u32 EpCompl);
-static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts);
-static void XUsbPs_IntrHandleEp0Setup(XUsbPs *InstancePtr);
-
-/*****************************************************************************/
-/**
-* This function is the first-level interrupt handler for the USB core. All USB
-* interrupts will be handled here. Depending on the type of the interrupt,
-* second level interrupt handler may be called. Second level interrupt
-* handlers will be registered by the user using the:
-* XUsbPs_IntrSetHandler()
-* and/or
-* XUsbPs_EpSetHandler()
-* functions.
-*
-*
-* @param HandlerRef is a Reference passed to the interrupt register
-* function. In our case this will be a pointer to the XUsbPs
-* instance.
-*
-* @return None
-*
-* @note None
-*
-******************************************************************************/
-void XUsbPs_IntrHandler(void *HandlerRef)
-{
- XUsbPs *InstancePtr;
-
- u32 IrqSts;
-
- Xil_AssertVoid(HandlerRef != NULL);
-
- InstancePtr = (XUsbPs *) HandlerRef;
-
- /* Handle controller (non-endpoint) related interrupts. */
- IrqSts = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_ISR_OFFSET);
-
- /* Clear the interrupt status register. */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_ISR_OFFSET, IrqSts);
-
- /* Nak interrupt, used to respond to host's IN request */
- if(IrqSts & XUSBPS_IXR_NAK_MASK) {
- /* Ack the hardware */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPNAKISR_OFFSET,
- XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPNAKISR_OFFSET));
- }
-
-
- /***************************************************************
- *
- * Handle general interrupts. Endpoint interrupts will be handler
- * later.
- *
- */
-
- /* RESET interrupt.*/
- if (IrqSts & XUSBPS_IXR_UR_MASK) {
- XUsbPs_IntrHandleReset(InstancePtr, IrqSts);
- return;
- }
-
- /* Check if we have a user handler that needs to be called. Note that
- * this is the handler for general interrupts. Endpoint interrupts will
- * be handled below.
- */
- if ((IrqSts & InstancePtr->HandlerMask) && InstancePtr->HandlerFunc) {
- (InstancePtr->HandlerFunc)(InstancePtr->HandlerRef, IrqSts);
- }
-
-
- /***************************************************************
- *
- * Handle Endpoint interrupts.
- *
- */
- if (IrqSts & XUSBPS_IXR_UI_MASK) {
- u32 EpStat;
- u32 EpCompl;
-
- /* ENDPOINT 0 SETUP PACKET HANDLING
- *
- * Check if we got a setup packet on endpoint 0. Currently we
- * only check for setup packets on endpoint 0 as we would not
- * expect setup packets on any other endpoint (even though it
- * is possible to send setup packets on other endpoints).
- */
- EpStat = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPSTAT_OFFSET);
- if (EpStat & 0x0001) {
- /* Handle the setup packet */
- XUsbPs_IntrHandleEp0Setup(InstancePtr);
-
- /* Re-Prime the endpoint.
- * Endpoint is de-primed if a setup packet comes in.
- */
- XUsbPs_EpPrime(InstancePtr, 0, XUSBPS_EP_DIRECTION_OUT);
- }
-
- /* Check for RX and TX complete interrupts. */
- EpCompl = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPCOMPL_OFFSET);
-
-
- /* ACK the complete interrupts. */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPCOMPL_OFFSET, EpCompl);
-
- /* Check OUT (RX) endpoints. */
- if (EpCompl & XUSBPS_EP_OUT_MASK) {
- XUsbPs_IntrHandleRX(InstancePtr, EpCompl);
- }
-
- /* Check IN (TX) endpoints. */
- if (EpCompl & XUSBPS_EP_IN_MASK) {
- XUsbPs_IntrHandleTX(InstancePtr, EpCompl);
- }
- }
-}
-
-
-/*****************************************************************************/
-/**
-* This function registers the user callback handler for controller
-* (non-endpoint) interrupts.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param CallBackFunc is the Callback function to register.
-* CallBackFunc may be NULL to clear the entry.
-* @param CallBackRef is the user data reference passed to the
-* callback function. CallBackRef may be NULL.
-* @param Mask is the User interrupt mask. Defines which interrupts
-* will cause the callback to be called.
-*
-* @return
-* - XST_SUCCESS: Callback registered successfully.
-* - XST_FAILURE: Callback could not be registered.
-*
-* @note None.
-*
-******************************************************************************/
-int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
- XUsbPs_IntrHandlerFunc CallBackFunc,
- void *CallBackRef, u32 Mask)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- InstancePtr->HandlerFunc = CallBackFunc;
- InstancePtr->HandlerRef = CallBackRef;
- InstancePtr->HandlerMask = Mask;
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-* This function handles TX buffer interrupts. It is called by the interrupt
-* when a transmit complete interrupt occurs. It returns buffers of completed
-* descriptors to the caller.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpCompl is the Bit mask of endpoints that caused a transmit
-* complete interrupt.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-static void XUsbPs_IntrHandleTX(XUsbPs *InstancePtr, u32 EpCompl)
-{
- int Index;
- u32 Mask;
- int NumEp;
-
- /* Check all endpoints for TX complete bits.
- */
- Mask = 0x00010000;
- NumEp = InstancePtr->DeviceConfig.NumEndpoints;
-
- /* Check for every endpoint if its TX complete bit is
- * set.
- */
- for (Index = 0; Index < NumEp; Index++, Mask <<= 1) {
- XUsbPs_EpIn *Ep;
-
- if (!(EpCompl & Mask)) {
- continue;
- }
- /* The TX complete bit for this endpoint is
- * set. Walk the list of descriptors to see
- * which ones are completed.
- */
- Ep = &InstancePtr->DeviceConfig.Ep[Index].In;
- do {
-
- XUsbPs_dTDInvalidateCache(Ep->dTDTail);
-
- /* If the descriptor is not active then the buffer has
- * not been sent yet.
- */
- if (XUsbPs_dTDIsActive(Ep->dTDTail)) {
- break;
- }
-
-
- if (InstancePtr->DeviceConfig.EpCfg[Index].In.Type ==
- XUSBPS_EP_TYPE_ISOCHRONOUS) {
- if (Ep->HandlerIsoFunc) {
- Ep->HandlerIsoFunc(Ep->HandlerRef,
- Ep->RequestedBytes,
- Ep->BytesTxed);
- }
- } else {
- if (Ep->HandlerFunc) {
- void *BufPtr;
-
- BufPtr = (void *) XUsbPs_ReaddTD(Ep->dTDTail,
- XUSBPS_dTDUSERDATA);
-
- Ep->HandlerFunc(Ep->HandlerRef, Index,
- XUSBPS_EP_EVENT_DATA_TX,
- BufPtr);
- }
- }
-
- Ep->dTDTail = XUsbPs_dTDGetNLP(Ep->dTDTail);
- } while(Ep->dTDTail != Ep->dTDHead);
- }
-}
-
-
-/*****************************************************************************/
-/**
- * This function handles RX buffer interrupts. It is called by the interrupt
- * when a receive complete interrupt occurs. It notifies the callback functions
- * that have been registered with the individual endpoints that data has been
- * received.
- *
- * @param InstancePtr
- * Pointer to the XUsbPs instance of the controller.
- *
- * @param EpCompl
- * Bit mask of endpoints that caused a receive complete interrupt.
- * @return
- * none
- *
- ******************************************************************************/
-static void XUsbPs_IntrHandleRX(XUsbPs *InstancePtr, u32 EpCompl)
-{
- XUsbPs_EpOut *Ep;
- int Index;
- u32 Mask;
- int NumEp;
-
- /* Check all endpoints for RX complete bits. */
- Mask = 0x00000001;
- NumEp = InstancePtr->DeviceConfig.NumEndpoints;
-
-
- /* Check for every endpoint if its RX complete bit is set.*/
- for (Index = 0; Index < NumEp; Index++, Mask <<= 1) {
- int numP = 0;
-
- if (!(EpCompl & Mask)) {
- continue;
- }
- Ep = &InstancePtr->DeviceConfig.Ep[Index].Out;
-
- XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
-
- /* Handle all finished dTDs */
- while (!XUsbPs_dTDIsActive(Ep->dTDCurr)) {
- numP += 1;
- /* We get data RX events for 0 length packets on
- * endpoint 0. We receive and immediately release
- * them again here, but there's no action to be
- * taken.
- */
- if (InstancePtr->DeviceConfig.EpCfg[Index].Out.Type ==
- XUSBPS_EP_TYPE_ISOCHRONOUS){
- if (Index == 0) {
- u8 BufferPtr[64] = {0};
-
- /* Get the data buffer. */
- XUsbPs_EpDataBufferReceive(InstancePtr,
- 0, &BufferPtr[0], 64);
- Ep->MemAlloted = 0;
- }
-
- if (Ep->MemAlloted == 1) {
- XUsbPs_EpGetData(InstancePtr, Index,
- Ep->RequestedBytes);
- } else
- break;
- } else {
- if (Ep->HandlerFunc) {
- Ep->HandlerFunc(Ep->HandlerRef, Index,
- XUSBPS_EP_EVENT_DATA_RX, NULL);
- }
-
- Ep->dTDCurr = XUsbPs_dTDGetNLP(Ep->dTDCurr);
- XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
- }
- }
- /* Re-Prime the endpoint.*/
- XUsbPs_EpPrime(InstancePtr, Index, XUSBPS_EP_DIRECTION_OUT);
- }
-}
-
-
-/*****************************************************************************/
-/**
-* This function handles a RESET interrupt. It will notify the interrupt
-* handler callback of the RESET condition.
-*
-* @param InstancePtr is pointer to the XUsbPs instance of the controller
-* @param IrqSts is the Interrupt status register content.
-* To be passed on to the user.
-*
-* @return None
-*
-* @Note None.
-*
-******************************************************************************/
-static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts)
-{
- u32 Timeout;
- u8 Index;
-
- if (InstancePtr->AppData != NULL)
- InstancePtr->AppData->State = XUSBPS_STATE_DEFAULT;
-
- for (Index = 0; Index < InstancePtr->DeviceConfig.NumEndpoints;
- Index++) {
- InstancePtr->DeviceConfig.Ep[Index].Out.MemAlloted = 0;
- InstancePtr->DeviceConfig.Ep[Index].Out.BufferPtr = NULL;
- InstancePtr->DeviceConfig.Ep[Index].Out.BytesTxed = 0;
- InstancePtr->DeviceConfig.Ep[Index].Out.RequestedBytes = 0;
- InstancePtr->DeviceConfig.Ep[Index].In.BufferPtr = NULL;
- InstancePtr->DeviceConfig.Ep[Index].In.BytesTxed = 0;
- InstancePtr->DeviceConfig.Ep[Index].In.RequestedBytes = 0;
- }
-
- /* Clear all setup token semaphores by reading the
- * XUSBPS_EPSTAT_OFFSET register and writing its value back to
- * itself.
- */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPSTAT_OFFSET,
- XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPSTAT_OFFSET));
-
- /* Clear all the endpoint complete status bits by reading the
- * XUSBPS_EPCOMPL_OFFSET register and writings its value back
- * to itself.
- */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPCOMPL_OFFSET,
- XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPCOMPL_OFFSET));
-
- /* Cancel all endpoint prime status by waiting until all bits
- * in XUSBPS_EPPRIME_OFFSET are 0 and then writing 0xFFFFFFFF
- * to XUSBPS_EPFLUSH_OFFSET.
- *
- * Avoid hanging here by using a Timeout counter...
- */
- Timeout = XUSBPS_TIMEOUT_COUNTER;
- while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPPRIME_OFFSET) &
- XUSBPS_EP_ALL_MASK) && --Timeout) {
- /* NOP */
- }
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF);
-
- /* Make sure that the reset bit in XUSBPS_PORTSCR1_OFFSET is
- * still set at this point. If the code gets to this point and
- * the reset bit has already been cleared we are in trouble and
- * hardware reset is necessary.
- */
- if (!(XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_PORTSCR1_OFFSET) &
- XUSBPS_PORTSCR_PR_MASK)) {
- /* Send a notification to the user that a hardware
- * RESET is required. At this point we can only hope
- * that the user registered an interrupt handler and
- * will issue a hardware RESET.
- */
- if (InstancePtr->HandlerFunc) {
- (InstancePtr->HandlerFunc)(InstancePtr->HandlerRef,
- IrqSts);
- }
- else {
- for (;;);
- }
-
- /* If we get here there is nothing more to do. The user
- * should have reset the core.
- */
- return;
- }
-
- /* Check if we have a user handler that needs to be called.
- */
- if (InstancePtr->HandlerFunc) {
- (InstancePtr->HandlerFunc)(InstancePtr->HandlerRef, IrqSts);
- }
-
- /* We are done. After RESET we don't proceed in the interrupt
- * handler.
- */
-}
-
-
-/*****************************************************************************/
-/**
-* This function handles a Setup Packet interrupt. It will notify the interrupt
-* handler callback of the RESET condition.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-*
-* @return None
-*
-* @Note None
-*
-******************************************************************************/
-static void XUsbPs_IntrHandleEp0Setup(XUsbPs *InstancePtr)
-{
-
- XUsbPs_EpOut *Ep;
-
- /* Notify the user. */
- Ep = &InstancePtr->DeviceConfig.Ep[0].Out;
-
- if (Ep->HandlerFunc) {
- Ep->HandlerFunc(Ep->HandlerRef, 0,
- XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED, NULL);
- }
-}
-
-
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/c1eb9c555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/c1eb9c555243001d18b399c1eb9b3628
deleted file mode 100644
index 1f20eea..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/c1eb9c555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,78 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/* read.c -- read bytes from a input device.
- */
-#ifndef UNDEFINE_FILE_OPS
-#include "xil_printf.h"
-#include "xparameters.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes);
-}
-#endif
-
-/*
- * read -- read bytes from the serial port. Ignore fd, since
- * we only have stdin.
- */
-__attribute__((weak)) s32
-read (s32 fd, char8* buf, s32 nbytes)
-{
-#ifdef STDIN_BASEADDRESS
- s32 i;
- s32 numbytes = 0;
- char8* LocalBuf = buf;
-
- (void)fd;
- if(LocalBuf != NULL) {
- for (i = 0; i < nbytes; i++) {
- numbytes++;
- *(LocalBuf + i) = inbyte();
- if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
- break;
- }
- }
- }
-
- return numbytes;
-#else
- (void)fd;
- (void)buf;
- (void)nbytes;
- return 0;
-#endif
-}
-
-__attribute__((weak)) s32
-_read (s32 fd, char8* buf, s32 nbytes)
-{
-#ifdef STDIN_BASEADDRESS
- s32 i;
- s32 numbytes = 0;
- char8* LocalBuf = buf;
-
- (void)fd;
- if(LocalBuf != NULL) {
- for (i = 0; i < nbytes; i++) {
- numbytes++;
- *(LocalBuf + i) = inbyte();
- if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
- break;
- }
- }
- }
-
- return numbytes;
-#else
- (void)fd;
- (void)buf;
- (void)nbytes;
- return 0;
-#endif
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/d0532a555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/d0532a555243001d18b399c1eb9b3628
deleted file mode 100644
index 166f2bb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/d0532a555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,454 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file boot.S
-*
-* @addtogroup a53_64_boot_code Cortex A53 64bit Processor Boot Code
-* @{
-*
boot.S
-*
-* The boot code performs minimum configuration which is required for an
-* application. Cortex-A53 starts by checking current exception level. If the
-* current exception level is EL3 and BSP is built for EL3, it will do
-* initialization required for application execution at EL3. Below is a
-* sequence illustrating what all configuration is performed before control
-* reaches to main function for EL3 execution.
-*
-* 1. Program vector table base for exception handling
-* 2. Set reset vector table base address
-* 3. Program stack pointer for EL3
-* 4. Routing of interrupts to EL3
-* 5. Enable ECC protection
-* 6. Program generic counter frequency
-* 7. Invalidate instruction cache, data cache and TLBs
-* 8. Configure MMU registers and program base address of translation table
-* 9. Transfer control to _start which clears BSS sections and runs global
-* constructor before jumping to main application
-*
-* If the current exception level is EL1 and BSP is also built for EL1_NONSECURE
-* it will perform initialization required for application execution at EL1
-* non-secure. For all other combination, the execution will go into infinite
-* loop. Below is a sequence illustrating what all configuration is performed
-* before control reaches to main function for EL1 execution.
-*
-* 1. Program vector table base for exception handling
-* 2. Program stack pointer for EL1
-* 3. Invalidate instruction cache, data cache and TLBs
-* 4. Configure MMU registers and program base address of translation table
-* 5. Transfer control to _start which clears BSS sections and runs global
-* constructor before jumping to main application
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 5.00 pkp 05/21/14 Initial version
-* 6.00 pkp 07/25/16 Program the counter frequency
-* 6.02 pkp 01/22/17 Added support for EL1 non-secure
-* 6.02 pkp 01/24/17 Clearing status of FPUStatus variable to ensure it
-* holds correct value.
-* 6.3 mus 04/20/17 CPU Cache protection bit in the L2CTLR_EL1 will be in
-* set state on reset. So, setting that bit through boot
-* code is redundant, hence removed the code which sets
-* CPU cache protection bit.
-* 6.4 mus 08/11/17 Implemented ARM erratum 855873.It fixes
-* CR#982209.
-* 6.6 mus 01/19/18 Added isb after writing to the cpacr_el1/cptr_el3,
-* to ensure floating-point unit is disabled, before
-* any subsequent instruction.
-* 7.0 mus 03/26/18 Updated TCR_EL3/TCR_EL1 as per versal address map
-* 7.3 mus 04/24/20 Corrected CPACR_EL1 handling at EL1 NS
-*
-*
-*
-******************************************************************************/
-
-#include "xparameters.h"
-#include "bspconfig.h"
-#include "xil_errata.h"
-
-.globl MMUTableL0
-.globl MMUTableL1
-.globl MMUTableL2
-.global _prestart
-.global _boot
-
-.global __el3_stack
-.global __el2_stack
-.global __el1_stack
-.global __el0_stack
-.global _vector_table
-
-.set EL3_stack, __el3_stack
-.set EL2_stack, __el2_stack
-.set EL1_stack, __el1_stack
-.set EL0_stack, __el0_stack
-
-.set TT_S1_FAULT, 0x0
-.set TT_S1_TABLE, 0x3
-
-.set L0Table, MMUTableL0
-.set L1Table, MMUTableL1
-.set L2Table, MMUTableL2
-.set vector_base, _vector_table
-.set rvbar_base, 0xFD5C0040
-
-#if defined (versal)
-.set counterfreq, XPAR_CPU_CORTEXA72_0_TIMESTAMP_CLK_FREQ
-#else
-.set counterfreq, XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ
-#endif
-
-.set MODE_EL1, 0x5
-.set DAIF_BIT, 0x1C0
-
-.section .boot,"ax"
-
-
-/* this initializes the various processor modes */
-
-_prestart:
-_boot:
- mov x0, #0
- mov x1, #0
- mov x2, #0
- mov x3, #0
- mov x4, #0
- mov x5, #0
- mov x6, #0
- mov x7, #0
- mov x8, #0
- mov x9, #0
- mov x10, #0
- mov x11, #0
- mov x12, #0
- mov x13, #0
- mov x14, #0
- mov x15, #0
- mov x16, #0
- mov x17, #0
- mov x18, #0
- mov x19, #0
- mov x20, #0
- mov x21, #0
- mov x22, #0
- mov x23, #0
- mov x24, #0
- mov x25, #0
- mov x26, #0
- mov x27, #0
- mov x28, #0
- mov x29, #0
- mov x30, #0
-#if 0 //don't put other a53 cpus in wfi
- //Which core am I
- // ----------------
- mrs x0, MPIDR_EL1
- and x0, x0, #0xFF //Mask off to leave Aff0
- cbz x0, OKToRun //If core 0, run the primary init code
-EndlessLoop0:
- wfi
- b EndlessLoop0
-#endif
-OKToRun:
-
- mrs x0, currentEL
- cmp x0, #0xC
- beq InitEL3
-
- cmp x0, #0x4
- beq InitEL1
-
- b error // go to error if current exception level is neither EL3 nor EL1
-InitEL3:
-.if (EL3 == 1)
- /*Set vector table base address*/
- ldr x1, =vector_base
- msr VBAR_EL3,x1
-
- /* Set reset vector address */
- /* Get the cpu ID */
- mrs x0, MPIDR_EL1
- and x0, x0, #0xFF
- mov w0, w0
- ldr w2, =rvbar_base
- /* calculate the rvbar base address for particular CPU core */
- mov w3, #0x8
- mul w0, w0, w3
- add w2, w2, w0
- /* store vector base address to RVBAR */
- str x1, [x2]
-
- /*Define stack pointer for current exception level*/
- ldr x2,=EL3_stack
- mov sp,x2
-
- /* Enable Trapping of SIMD/FPU register for standalone BSP */
- mov x0, #0
-#ifndef FREERTOS_BSP
- orr x0, x0, #(0x1 << 10)
-#endif
- msr CPTR_EL3, x0
- isb
-
- /*
- * Clear FPUStatus variable to make sure that it contains current
- * status of FPU i.e. disabled. In case of a warm restart execution
- * when bss sections are not cleared, it may contain previously updated
- * value which does not hold true now.
- */
-#ifndef FREERTOS_BSP
- ldr x0,=FPUStatus
- str xzr, [x0]
-#endif
- /* Configure SCR_EL3 */
- mov w1, #0 //; Initial value of register is unknown
- orr w1, w1, #(1 << 11) //; Set ST bit (Secure EL1 can access CNTPS_TVAL_EL1, CNTPS_CTL_EL1 & CNTPS_CVAL_EL1)
- orr w1, w1, #(1 << 10) //; Set RW bit (EL1 is AArch64, as this is the Secure world)
- orr w1, w1, #(1 << 3) //; Set EA bit (SError routed to EL3)
- orr w1, w1, #(1 << 2) //; Set FIQ bit (FIQs routed to EL3)
- orr w1, w1, #(1 << 1) //; Set IRQ bit (IRQs routed to EL3)
- msr SCR_EL3, x1
-
- /*configure cpu auxiliary control register EL1 */
- ldr x0,=0x80CA000 // L1 Data prefetch control - 5, Enable device split throttle, 2 independent data prefetch streams
-#if CONFIG_ARM_ERRATA_855873
- /*
- * Set ENDCCASCI bit in CPUACTLR_EL1 register, to execute data
- * cache clean operations as data cache clean and invalidate
- *
- */
- orr x0, x0, #(1 << 44) //; Set ENDCCASCI bit
-#endif
- msr S3_1_C15_C2_0, x0 //CPUACTLR_EL1
-
- /* program the counter frequency */
- ldr x0,=counterfreq
- msr CNTFRQ_EL0, x0
-
- /*Enable hardware coherency between cores*/
- mrs x0, S3_1_c15_c2_1 //Read EL1 CPU Extended Control Register
- orr x0, x0, #(1 << 6) //Set the SMPEN bit
- msr S3_1_c15_c2_1, x0 //Write EL1 CPU Extended Control Register
- isb
-
- tlbi ALLE3
- ic IALLU //; Invalidate I cache to PoU
- bl invalidate_dcaches
- dsb sy
- isb
-
- ldr x1, =L0Table //; Get address of level 0 for TTBR0_EL3
- msr TTBR0_EL3, x1 //; Set TTBR0_EL3
-
- /**********************************************
- * Set up memory attributes
- * This equates to:
- * 0 = b01000100 = Normal, Inner/Outer Non-Cacheable
- * 1 = b11111111 = Normal, Inner/Outer WB/WA/RA
- * 2 = b00000000 = Device-nGnRnE
- * 3 = b00000100 = Device-nGnRE
- * 4 = b10111011 = Normal, Inner/Outer WT/WA/RA
- **********************************************/
- ldr x1, =0x000000BB0400FF44
- msr MAIR_EL3, x1
-
-#if defined (versal)
- /**********************************************
- * Set up TCR_EL3
- * Physical Address Size PS = 100 -> 44bits 16 TB
- * Granual Size TG0 = 00 -> 4KB
- * size offset of the memory region T0SZ = 20 -> (region size 2^(64-20) = 2^44)
- ***************************************************/
- ldr x1,=0x80843514
-#else
- /**********************************************
- * Set up TCR_EL3
- * Physical Address Size PS = 010 -> 40bits 1TB
- * Granual Size TG0 = 00 -> 4KB
- * size offset of the memory region T0SZ = 24 -> (region size 2^(64-24) = 2^40)
- ***************************************************/
- ldr x1,=0x80823518
-#endif
- msr TCR_EL3, x1
- isb
-
- /* Enable SError Exception for asynchronous abort */
- mrs x1,DAIF
- bic x1,x1,#(0x1<<8)
- msr DAIF,x1
-
- /* Configure SCTLR_EL3 */
- mov x1, #0 //Most of the SCTLR_EL3 bits are unknown at reset
- orr x1, x1, #(1 << 12) //Enable I cache
- orr x1, x1, #(1 << 3) //Enable SP alignment check
- orr x1, x1, #(1 << 2) //Enable caches
- orr x1, x1, #(1 << 0) //Enable MMU
- msr SCTLR_EL3, x1
- dsb sy
- isb
-
- b _startup //jump to start
-.else
- b error // present exception level and selected exception level mismatch
-.endif
-
-InitEL1:
-.if (EL1_NONSECURE == 1)
- /*Set vector table base address*/
- ldr x1, =vector_base
- msr VBAR_EL1,x1
-
- /* Trap floating point access only in case of standalone BSP */
-#ifdef FREERTOS_BSP
- mrs x0, CPACR_EL1
- orr x0, x0, #(0x3 << 20)
- msr CPACR_EL1, x0
-#else
- mrs x0, CPACR_EL1
- bic x0, x0, #(0x3 << 20)
- msr CPACR_EL1, x0
-#endif
- isb
-
- /*
- * Clear FPUStatus variable to make sure that it contains current
- * status of FPU i.e. disabled. In case of a warm restart execution
- * when bss sections are not cleared, it may contain previously updated
- * value which does not hold true now.
- */
-#ifndef FREERTOS_BSP
- ldr x0,=FPUStatus
- str xzr, [x0]
-#endif
- /*Define stack pointer for current exception level*/
- ldr x2,=EL1_stack
- mov sp,x2
-
- /* Disable MMU first */
- mov x1,#0x0
- msr SCTLR_EL1, x1
- isb
-
- TLBI VMALLE1
-
- ic IALLU //; Invalidate I cache to PoU
- bl invalidate_dcaches
- dsb sy
- isb
-
- ldr x1, =L0Table //; Get address of level 0 for TTBR0_EL1
- msr TTBR0_EL1, x1 //; Set TTBR0_EL1
-
- /**********************************************
- * Set up memory attributes
- * This equates to:
- * 0 = b01000100 = Normal, Inner/Outer Non-Cacheable
- * 1 = b11111111 = Normal, Inner/Outer WB/WA/RA
- * 2 = b00000000 = Device-nGnRnE
- * 3 = b00000100 = Device-nGnRE
- * 4 = b10111011 = Normal, Inner/Outer WT/WA/RA
- **********************************************/
- ldr x1, =0x000000BB0400FF44
- msr MAIR_EL1, x1
-
- #if defined (versal)
- /**********************************************
- * Set up TCR_EL1
- * Physical Address Size PS = 100 -> 44bits 16TB
- * Granual Size TG0 = 00 -> 4KB
- * size offset of the memory region T0SZ = 20 -> (region size 2^(64-20) = 2^44)
- ***************************************************/
- ldr x1,=0x485800514
- #else
- /**********************************************
- * Set up TCR_EL1
- * Physical Address Size PS = 010 -> 44bits 16TB
- * Granual Size TG0 = 00 -> 4KB
- * size offset of the memory region T0SZ = 24 -> (region size 2^(64-24) = 2^40)
- ***************************************************/
- ldr x1,=0x285800518
- #endif
- msr TCR_EL1, x1
- isb
- /* Enable SError Exception for asynchronous abort */
- mrs x1,DAIF
- bic x1,x1,#(0x1<<8)
- msr DAIF,x1
-
- //; Enable MMU
- mov x1,#0x0
- orr x1, x1, #(1 << 18) // ; Set WFE non trapping
- orr x1, x1, #(1 << 17) // ; Set WFI non trapping
- orr x1, x1, #(1 << 5) // ; Set CP15 barrier enabled
- orr x1, x1, #(1 << 12) // ; Set I bit
- orr x1, x1, #(1 << 2) // ; Set C bit
- orr x1, x1, #(1 << 0) // ; Set M bit
- msr SCTLR_EL1, x1
- isb
-
- bl _startup //jump to start
-.else
- b error // present exception level and selected exception level mismatch
-.endif
-
-error: b error
-
-
-invalidate_dcaches:
-
- dmb ISH
- mrs x0, CLIDR_EL1 //; x0 = CLIDR
- ubfx w2, w0, #24, #3 //; w2 = CLIDR.LoC
- cmp w2, #0 //; LoC is 0?
- b.eq invalidateCaches_end //; No cleaning required and enable MMU
- mov w1, #0 //; w1 = level iterator
-
-invalidateCaches_flush_level:
- add w3, w1, w1, lsl #1 //; w3 = w1 * 3 (right-shift for cache type)
- lsr w3, w0, w3 //; w3 = w0 >> w3
- ubfx w3, w3, #0, #3 //; w3 = cache type of this level
- cmp w3, #2 //; No cache at this level?
- b.lt invalidateCaches_next_level
-
- lsl w4, w1, #1
- msr CSSELR_EL1, x4 //; Select current cache level in CSSELR
- isb //; ISB required to reflect new CSIDR
- mrs x4, CCSIDR_EL1 //; w4 = CSIDR
-
- ubfx w3, w4, #0, #3
- add w3, w3, #2 //; w3 = log2(line size)
- ubfx w5, w4, #13, #15
- ubfx w4, w4, #3, #10 //; w4 = Way number
- clz w6, w4 //; w6 = 32 - log2(number of ways)
-
-invalidateCaches_flush_set:
- mov w8, w4 //; w8 = Way number
-invalidateCaches_flush_way:
- lsl w7, w1, #1 //; Fill level field
- lsl w9, w5, w3
- orr w7, w7, w9 //; Fill index field
- lsl w9, w8, w6
- orr w7, w7, w9 //; Fill way field
- dc CISW, x7 //; Invalidate by set/way to point of coherency
- subs w8, w8, #1 //; Decrement way
- b.ge invalidateCaches_flush_way
- subs w5, w5, #1 //; Descrement set
- b.ge invalidateCaches_flush_set
-
-invalidateCaches_next_level:
- add w1, w1, #1 //; Next level
- cmp w2, w1
- b.gt invalidateCaches_flush_level
-
-invalidateCaches_end:
- ret
-
-.end
-/**
-* @} End of "addtogroup a53_64_boot_code".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/e025b2595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/e025b2595243001d18b399c1eb9b3628
deleted file mode 100644
index fa58233..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1b/e025b2595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,78 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_spinlock.h
-*
-* This header file contains function prototypes to be used while using Xilinx
-* spinlocking mechanism.
-* Please refer to file header contents of xil_spinlock.c to understand in
-* detail the spinlocking mechanism.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 7.5 asa 02/16/21 First release
-* 7.6 sk 08/05/21 Add Boolean check and braces for Xil_IsSpinLockEnabled
-* if condition to fix misrac violations.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.4 mmd 04/21/19 First release.
-* 7.2 nava 08/01/20 Updated Xil_WaitForEvent() and Xil_WaitForEvents(()
-* API to use microsecond timeout instead of a free
-* counter.
-* 7.3 kal 06/30/20 Converted Xil_Ceil macro to API.
-* rpo 08/19/20 Added function for read,modify,write
-* kal 09/22/20 Changed the param type from const char to const char*
-* to avoid copying key onto stack
-* td 10/16/20 Added Xil_Strcpy, Xil_Strcat, Xil_SecureMemCpy and
-* Xil_MemCmp functions
-* 7.4 am 11/26/20 Added Xil_StrCpyRange function
-* 7.6 kpt 07/15/21 Added Xil_SecureZeroize function
-*
-*
-*
-*****************************************************************************/
-
-/****************************** Include Files *********************************/
-#include "xil_util.h"
-#include "sleep.h"
-
-/************************** Constant Definitions ****************************/
-#define MAX_NIBBLES 8U
-
-/************************** Function Prototypes *****************************/
-
-/******************************************************************************/
-/**
-* This API ceils the provided float value.
-*
-* @param Value is a float variable which has to ceiled to nearest
-* integer.
-*
-* @return Returns ceiled value.
-*
-*******************************************************************************/
-int Xil_Ceil(float Value)
-{
- int Result = Value;
-
- if (Value > Result) {
- Result = Result + 1;
- }
-
- return Result;
-}
-
-/****************************************************************************/
-/**
- * Converts the char into the equivalent nibble.
- * Ex: 'a' -> 0xa, 'A' -> 0xa, '9'->0x9
- *
- * @param InChar - Input character to be converted to nibble.
- * Valid characters are between 0-9, a-f, A-F
- * @param Num - Memory location where nibble is to be stored
- *
- * @return
- * XST_SUCCESS - Character converted to nibble
- * XST_FAILURE - Invalid input character
- *
- * @note None.
- *
- *****************************************************************************/
-
-u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num)
-{
- u32 Status;
-
- /* Convert the char to nibble */
- if ((InChar >= (u8)'0') && (InChar <= (u8)'9')) {
- *Num = InChar - (u8)'0';
- Status = XST_SUCCESS;
- }
- else if ((InChar >= (u8)'a') && (InChar <= (u8)'f')) {
- *Num = InChar - (u8)'a' + 10U;
- Status = XST_SUCCESS;
- }
- else if ((InChar >= (u8)'A') && (InChar <= (u8)'F')) {
- *Num = InChar - (u8)'A' + 10U;
- Status = XST_SUCCESS;
- }
- else {
- Status = XST_FAILURE;
- }
-
- return Status;
-}
-
-/****************************************************************************/
-/*
- * Converts the string into the equivalent Hex buffer.
- * Ex: "abc123" -> {0xab, 0xc1, 0x23}
- *
- * @param Str - Pointer to string to be converted to Hex.
- * Accepted characters in string are between 0-9, a-f and A-F
- * @param Buf - Pointer to memory location where converted hex values are to
- * be stored.
- * @param Len - Length of input string
- *
- * @return
- * XST_SUCCESS - Input string is converted to hex
- * XST_FAILURE - Invalid character in inpit string
- *
- * @note None.
- *
- *****************************************************************************/
-u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len)
-{
- u32 Status = XST_FAILURE;
- u8 ConvertedLen = 0U, index = 0U;
- u8 Nibble[MAX_NIBBLES] = {0U};
- u8 i;
-
- while (ConvertedLen < Len) {
- for (i = 0U; i < MAX_NIBBLES; i++) {
- Status = Xil_ConvertCharToNibble(Str[ConvertedLen],
- &Nibble[i]);
- ConvertedLen = ConvertedLen +1U;
- if (Status != XST_SUCCESS) {
- /* Error converting char to nibble */
- goto END;
- }
- }
-
- buf[index] = ((Nibble[0] << (u8)28U) | (Nibble[1] << (u8)24U) |
- (Nibble[2] << (u8)20U) | (Nibble[3] << (u8)16U) |
- (Nibble[4] << (u8)12U) | (Nibble[5] << (u8)8U) |
- (Nibble[6] << (u8)4U) | (u32)Nibble[7]);
- index++;
- }
-END:
- return Status;
-}
-
-/****************************************************************************/
-/*
- * Waits for the event
- *
- * @param RegAddr - Address of register to be checked for event(s) occurrence
- * @param EventMask - Mask indicating event(s) to be checked
- * @param Event - Specific event(s) value to be checked
- * @param Timeout - Max number of microseconds to wait for an event(s).
- *
- * @return
- * XST_SUCCESS - On occurrence of the event(s).
- * XST_FAILURE - Event did not occur before counter reaches 0
- *
- * @note None.
- *
- *****************************************************************************/
-u32 Xil_WaitForEvent(u32 RegAddr, u32 EventMask, u32 Event, u32 Timeout)
-{
- u32 EventStatus;
- u32 PollCount = Timeout;
- u32 Status = XST_FAILURE;
-
- while(PollCount > 0) {
- EventStatus = Xil_In32(RegAddr) & EventMask;
- if (EventStatus == Event) {
- Status = XST_SUCCESS;
- break;
- }
- PollCount--;
- usleep(1U);
- }
-
- return Status;
-}
-
-
-/******************************************************************************/
-/**
- * Waits for the events. Returns on occurrence of first event / timeout.
- *
- * @param EventsRegAddr - Address of register to be checked for event(s)
- * occurrence
- * @param EventsMask - Mask indicating event(s) to be checked
- * @param WaitEvents - Specific event(s) to be checked
- * @param Timeout - Max number of microseconds to wait for an event(s).
- * @param Events - Mask of Events occurred returned in memory pointed by
- * this variable
- *
- * @return
- * XST_SUCCESS - On occurrence of the event(s).
- * XST_FAILURE - Event did not occur before counter reaches 0
- *
- ******************************************************************************/
-u32 Xil_WaitForEvents(u32 EventsRegAddr, u32 EventsMask, u32 WaitEvents,
- u32 Timeout, u32* Events)
-{
- u32 EventStatus;
- u32 PollCount = Timeout;
- u32 Status = XST_TIMEOUT;
-
- *Events = 0x00;
- do {
- EventStatus = Xil_In32(EventsRegAddr);
- EventStatus &= EventsMask;
- if(EventStatus & WaitEvents) {
- Status = XST_SUCCESS;
- *Events = EventStatus;
- break;
- }
- PollCount--;
- usleep(1U);
- }
- while(PollCount > 0);
-
- return Status;
-}
-
-/******************************************************************************/
-/**
- * Checks whether the passed character is a valid hex digit
- *
- * @param Ch - Pointer to the input character
- *
- * @return
- * XST_SUCCESS - on valid hex digit
- * XST_FAILURE - on invalid hex digit
- *
- * @note None.
- *
- ******************************************************************************/
-u32 Xil_IsValidHexChar(const char *Ch)
-{
- u32 Status = XST_FAILURE;
-
- if(NULL == Ch) {
- goto END;
- }
- if ((*Ch >= '0' && *Ch <='9')||
- (*Ch >= 'a' && *Ch <='f')||
- (*Ch >= 'A' && *Ch <='F')) {
-
- Status = XST_SUCCESS;
- }
-END:
- return Status;
-}
-
-/******************************************************************************/
-/**
- * Validate the input string contains only hexadecimal characters
- *
- * @param HexStr - Pointer to string to be validated
- *
- * @return
- * XST_SUCCESS - On valid input hex string
- * XST_INVALID_PARAM - On invalid length of the input string
- * XST_FAILURE - On non hexadecimal character in string
- *
- * @note None
- *
- ******************************************************************************/
-u32 Xil_ValidateHexStr(const char *HexStr)
-{
- u32 Idx;
- u32 Len;
- u32 Status = XST_INVALID_PARAM;
-
- if(NULL == HexStr) {
- goto END;
- }
-
- Len = Xil_Strnlen(HexStr, XIL_MAX_HEX_STR_LEN + 1U);
- if (Len > XIL_MAX_HEX_STR_LEN) {
- goto END;
- }
-
- for (Idx = 0U; Idx < Len; Idx++) {
- Status = Xil_IsValidHexChar(&HexStr[Idx]);
- if (Status != XST_SUCCESS) {
- break;
- }
- }
-
-END:
- return Status;
-}
-
-/****************************************************************************/
-/**
- * Converts the string into the equivalent Hex buffer.
- * Ex: "abc123" -> {0xab, 0xc1, 0x23}
- *
- * @param Str is a Input String. Will support the lower and upper case values.
- * Value should be between 0-9, a-f and A-F
- * @param Buf is Output buffer.
- * @param Len of the input string. Should have even values
- *
- * @return
- * - XST_SUCCESS no errors occurred.
- * - XST_FAILURE an error when input parameters are not valid
- * - an error when input buffer has invalid values
- *
- * TDD Test Cases:
- * ---Initialization---
- * Len is odd
- * Len is zero
- * Str is NULL
- * Buf is NULL
- * ---Functionality---
- * Str input with only numbers
- * Str input with All values in A-F
- * Str input with All values in a-f
- * Str input with values in a-f, 0-9, A-F
- * Str input with values in a-z, 0-9, A-Z
- * Boundary Cases
- * Memory Bounds of buffer checking
- * ****************************************************************************/
-u32 Xil_ConvertStringToHexBE(const char *Str, u8 *Buf, u32 Len)
-{
- u32 ConvertedLen;
- u8 LowerNibble = 0U;
- u8 UpperNibble = 0U;
- u32 Status = (u32)XST_FAILURE;
-
- if ((Str == NULL) || (Buf == NULL)) {
- Status = (u32)XST_INVALID_PARAM;
- goto END;
- }
-
- if ((Len == 0U) || ((Len % XIL_SIZE_OF_BYTE_IN_BITS) != 0U)) {
- Status = (u32)XST_INVALID_PARAM;
- goto END;
- }
-
- if(Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) {
- Status = (u32)XST_INVALID_PARAM;
- goto END;
- }
-
- ConvertedLen = 0U;
- while (ConvertedLen < (Len / XIL_SIZE_OF_NIBBLE_IN_BITS)) {
- if (Xil_ConvertCharToNibble(Str[ConvertedLen],&UpperNibble)
- == (u32)XST_SUCCESS) {
- if (Xil_ConvertCharToNibble(Str[ConvertedLen+1],
- &LowerNibble) == (u32)XST_SUCCESS) {
- Buf[ConvertedLen/2] =
- (UpperNibble << XIL_SIZE_OF_NIBBLE_IN_BITS) |
- LowerNibble;
- }
- else {
- Status = (u32)XST_INVALID_PARAM;
- goto END;
- }
- }
- else {
- Status = (u32)XST_INVALID_PARAM;
- goto END;
- }
- ConvertedLen += 2U;
- }
- Status = (u32)XST_SUCCESS;
-END:
- return Status;
-}
-
-/******************************************************************************/
-/**
- * Converts the string into the equivalent Hex buffer.
- * Ex: "abc123" -> {0x23, 0xc1, 0xab}
- *
- * @param Str - Input String to be converted to hex number in little
- * endian format. Valid characters of input strin are between
- * 0-9, a-f and A-F
- * @param Buf - Pointer to memory location where converted hex numbers are to
- * be stored.
- * @param Len - Expected number of output bits
- *
- * @return
- * XST_SUCCESS - Input string is converted to hex number(s)
- * XST_FAILURE - Invalid input character detected in input string
- *
- * @note
- *
- ******************************************************************************/
-u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len)
-{
- u32 ConvertedLen;
- u8 LowerNibble = 0U;
- u8 UpperNibble = 0U;
- u32 StrIndex;
- u32 Status = XST_FAILURE;
-
- if ((NULL == Str) || (NULL == Buf)) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- if ((Len == 0U) || ((Len % XIL_SIZE_OF_BYTE_IN_BITS) != 0U)) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- if(Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- StrIndex = (Len / XIL_SIZE_OF_BYTE_IN_BITS) - 1U;
- ConvertedLen = 0U;
- while (ConvertedLen < (Len / XIL_SIZE_OF_NIBBLE_IN_BITS)) {
- Status = Xil_ConvertCharToNibble(Str[ConvertedLen],
- &UpperNibble);
- if (XST_SUCCESS == Status) {
- Status = Xil_ConvertCharToNibble(Str[ConvertedLen + 1],
- &LowerNibble);
- if (XST_SUCCESS == Status) {
- Buf[StrIndex] =
- (UpperNibble << XIL_SIZE_OF_NIBBLE_IN_BITS) |
- LowerNibble;
- StrIndex = StrIndex - 1U;
- }
- else {
- Status = XST_INVALID_PARAM;
- goto END;
- }
- }
- else {
- Status = XST_INVALID_PARAM;
- goto END;
- }
- ConvertedLen += 2U;
- }
-
- Status = XST_SUCCESS;
-END:
- return Status;
-}
-
-/******************************************************************************/
-/**
- * Returns the length of input string.
- *
- * @param Str - Input string
- * @param MaxLen - Maximum expected length of the input string
- *
- * @return
- * Returns length of the input string if length is less than MaxLen.
- * Returns MaxLen if the length of the input string is >= MaxLen.
- *
- * @note
- *
- ******************************************************************************/
-u32 Xil_Strnlen(const char *Str, u32 MaxLen)
-{
- const char *InStr = Str;
- u32 StrLen = 0U;
-
- if (NULL == Str) {
- goto END;
- }
-
- while(StrLen < MaxLen) {
- if ('\0' == *InStr) {
- break;
- }
- StrLen++;
- InStr++;
- }
-
-END:
- return StrLen;
-}
-
-/*****************************************************************************/
-/**
- * @brief This function will Read, Modify and Write to an address.
- *
- * @param Addr denotes Address
- * @param Mask denotes the bits to be modified
- * @param Value is the value to be written to the address
- *
- * @return None
- *
- *****************************************************************************/
-void Xil_UtilRMW32(u32 Addr, u32 Mask, u32 Value)
-{
- u32 Val;
-
- Val = Xil_In32(Addr);
- Val = (Val & (~Mask)) | (Mask & Value);
- Xil_Out32(Addr, Val);
-}
-
-/*****************************************************************************/
-/**
- * @brief This functions copies source string to destination string. This
- * function is a safe version of strcpy
- *
- * @param DestPtr is pointer to destination string
- * @param SrcPtr is pointer to source string
- * @param Size is the maximum number of bytes of the source string
- * to be copied
- *
- * @return XST_SUCCESS on success and error code on failure
- *
- ******************************************************************************/
-int Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size)
-{
- int Status = XST_FAILURE;
- u32 Count;
-
- if ((SrcPtr == NULL) || (DestPtr == NULL) || (Size == 0U)) {
- goto END;
- }
-
- for (Count = 0U; (SrcPtr[Count] != '\0') && (Count < Size); ++Count) {
- DestPtr[Count] = SrcPtr[Count];
- }
- if (Count == Size) {
- DestPtr[0U] = '\0';
- goto END;
- }
- DestPtr[Count] = '\0';
- Status = XST_SUCCESS;
-
-END:
- return Status;
-}
-
-/****************************************************************************/
-/**
- * @brief Copies specified range from source string to destination string
- *
- * @param Src is a pointer to source string
- * @param Dst is a pointer to destination string
- * @param From is 0 based index from where string copy starts
- * @param To is 0 based index till which string is copied
- * @param MaxSrcLen is the maximum length of source string
- * @param MaxDstLen is the maximum length of destination string
- *
- * @return XST_SUCCESS on success
- * XST_FAILURE on failure
- *
- * @note None
- *
- ****************************************************************************/
-int Xil_StrCpyRange(const u8 *Src, u8 *Dst, u32 From, u32 To, u32 MaxSrcLen,
- u32 MaxDstLen)
-{
- int Status = XST_FAILURE;
- u32 SrcLength;
- u32 Index;
-
- if ((Src == NULL) || (Dst == NULL)) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- if ((To >= MaxSrcLen) || (To < From)) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- if ((To - From + 1U) >= MaxDstLen) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- SrcLength = Xil_Strnlen((const char *)Src, MaxSrcLen);
- if (To >= SrcLength) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- for (Index = From; Index <= To && Src[Index]!= '\0'; Index++) {
- Dst[Index - From] = Src[Index];
- }
-
- Dst[Index - From] = '\0';
- Status = XST_SUCCESS;
-
-END:
- return Status;
-}
-
-/*****************************************************************************/
-/**
- * @brief This function appends string2 to string1. This function is a safe
- * version of strcat
- *
- * @param Str1Ptr is pointer to string1
- * @param Str2Ptr is pointer to string2
- * @param Size is the maximum number of bytes Str1 can hold
- *
- * @return XST_SUCCESS on success and error code on failure
- *
- ******************************************************************************/
-int Xil_Strcat(char* Str1Ptr, const char* Str2Ptr, const u32 Size)
-{
- int Status = XST_FAILURE;
- u32 Count = 0U;
- u32 CountTmp = 0U;
-
- if ((Str1Ptr == NULL) || (Str2Ptr == NULL) || (Size == 0U)) {
- goto END;
- }
-
- while ((Count < Size) && (Str1Ptr[Count] != '\0')) {
- Count++;
- }
-
- while ((Str2Ptr[CountTmp] != '\0') && (Count < Size)) {
- Str1Ptr[Count++] = Str2Ptr[CountTmp++];
- }
- if (Count == Size) {
- Str1Ptr[0U] = '\0';
- goto END;
- }
- Str1Ptr[Count] = '\0';
- Status = XST_SUCCESS;
-
-END:
- return Status;
-}
-
-/*****************************************************************************/
-/**
- * @brief This function copies Len bytes from source memory to destination
- * memory. If Len is greater than DestPtrLen, then DestPtr is also
- * filled with 0s till DestPtrLen bytes and is considered as a failure.
- * This function is a secure implementation of memcpy
- *
- * @param DestPtr is pointer to destination address
- * @param DestPtrLen is the memory alloted to the destination buffer
- * @param SrcPtr is pointer to source address
- * @param Len is number of bytes to be copied
- *
- * @return XST_SUCCESS on success and error code on failure
- *
- ******************************************************************************/
-int Xil_SecureMemCpy(void * DestPtr, u32 DestPtrLen, const void * SrcPtr, u32 Len)
-{
- int Status = XST_FAILURE;
- u8 *Dest = (u8 *)DestPtr;
- const u8 *Src = (const u8 *)SrcPtr;
-
- if ((DestPtr == NULL) || (SrcPtr == NULL)) {
- goto END;
- }
-
- if (Len > DestPtrLen) {
- while (DestPtrLen != 0U) {
- *Dest = 0U;
- Dest++;
- DestPtrLen--;
- }
- goto END;
- }
-
- /* Loop and copy. */
- while (Len != 0U) {
- *Dest = *Src;
- Dest++;
- Src++;
- Len--;
- }
- Status = XST_SUCCESS;
-
-END:
- return Status;
-}
-
-/*****************************************************************************/
-/**
- * @brief This function compares Len bytes from memory1 and memory2. This
- * function is a secure implementation of memcmp
- *
- * @param Buf1Ptr is pointer to memory1
- * @param Buf2Ptr is pointer to memory2
- * @param Len is number of byets to be compared
- *
- * @return 0 if contents of both the memory regions are same,
- * -1 if first non-matching character has lower value in Buf1Ptr
- * 1 if first non-matching character is greater value in Buf1Ptr
- *
- ******************************************************************************/
-int Xil_MemCmp(const void * Buf1Ptr, const void * Buf2Ptr, u32 Len)
-{
- volatile int RetVal = 1;
- const u8 *Buf1 = Buf1Ptr;
- const u8 *Buf2 = Buf2Ptr;
- u32 Size = Len;
-
- /* Assert validates the input arguments */
- if ((Buf1 == NULL) || (Buf2 == NULL) || (Len == 0x0U)) {
- goto END;
- }
-
- /* Loop and compare */
- while (Size != 0U) {
- if (*Buf1 > *Buf2) {
- RetVal = 1;
- goto END;
- } else if (*Buf1 < *Buf2) {
- RetVal = -1;
- goto END;
- } else {
- Buf1++;
- Buf2++;
- Size--;
- }
- }
-
- /* Make sure size is zero to know the whole of data is compared */
- if (Size == 0U) {
- RetVal = 0;
- }
-
-END:
- return RetVal;
-}
-
-/*****************************************************************************/
-/**
- * @brief This function is used to zeroize the memory
- *
- * @param DataPtr Pointer to the memory which need to be zeroized.
- * @param Length Length of the data in bytes.
- *
- * @return
- * - XST_SUCCESS: If Zeroization is successful.
- * - XST_FAILURE: If Zeroization is not successful.
- ********************************************************************************/
-int Xil_SecureZeroize(u8 *DataPtr, const u32 Length)
-{
- u32 Index;
- int Status = XST_FAILURE;
-
- /* Clear the data */
- (void)memset(DataPtr, 0, Length);
-
- /* Read it back to verify */
- for (Index = 0U; Index < Length; Index++) {
- if (DataPtr[Index] != 0x00U) {
- goto END;
- }
- }
- if (Index == Length) {
- Status = XST_SUCCESS;
- }
-
-END:
- return Status;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1c/b1c7e0545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1c/b1c7e0545243001d18b399c1eb9b3628
deleted file mode 100644
index eb496ea..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1c/b1c7e0545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,39 +0,0 @@
-DRIVER_LIB_VERSION = 1.0
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I$(INCLUDEDIR)
-
-SRCFILES:=$(wildcard *.c)
-
-OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
-
-libs: $(OBJECTS)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf ${DEPFILES}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1c/e0868d595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1c/e0868d595243001d18b399c1eb9b3628
deleted file mode 100644
index 20f0886..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1c/e0868d595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,42 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
- .globl _mcount
- .text
- .align 2
- .ent _mcount
-
- #ifndef PROFILE_NO_GRAPH
-
-_mcount:
- addi r1, r1, -48
- swi r11, r1, 44
- swi r12, r1, 40
- swi r5, r1, 36
- swi r6, r1, 32
- swi r7, r1, 28
- swi r8, r1, 24
- swi r9, r1, 20
- swi r10, r1, 16
- swi r15, r1, 12
- add r5, r0, r15
- brlid r15, mcount
- add r6, r0, r16
-
- lwi r11, r1, 44
- lwi r12, r1, 40
- lwi r5, r1, 36
- lwi r6, r1, 32
- lwi r7, r1, 28
- lwi r8, r1, 24
- lwi r9, r1, 20
- lwi r10, r1, 16
- lwi r15, r1, 12
- rtsd r15, 4
- addi r1, r1, 48
-
- #endif /* PROFILE_NO_GRAPH */
-
- .end _mcount
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1c/f0f08b545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1c/f0f08b545243001d18b399c1eb9b3628
deleted file mode 100644
index be5fccb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1c/f0f08b545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,41 +0,0 @@
-DRIVER_LIB_VERSION = 1.0
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I$(INCLUDEDIR)
-
-INCLUDEFILES:=*.h
-
-SRCFILES:=$(wildcard *.c)
-
-OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
-
-libs: $(OBJECTS)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf $(DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1d/01cea3595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1d/01cea3595243001d18b399c1eb9b3628
deleted file mode 100644
index 1f57654..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1d/01cea3595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,64 +0,0 @@
-/******************************************************************************/
-/**
-* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-* @file xil_mem.c
-*
-* This file contains xil mem copy function to use in case of word aligned
-* data copies.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.1 nsk 11/07/16 First release.
-*
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-
-/***************** Inline Functions Definitions ********************/
-/*****************************************************************************/
-/**
-* @brief This function copies memory from once location to other.
-*
-* @param dst: pointer pointing to destination memory
-*
-* @param src: pointer pointing to source memory
-*
-* @param cnt: 32 bit length of bytes to be copied
-*
-*****************************************************************************/
-void Xil_MemCpy(void* dst, const void* src, u32 cnt)
-{
- char *d = (char*)(void *)dst;
- const char *s = src;
-
- while (cnt >= sizeof (int)) {
- *(int*)d = *(int*)s;
- d += sizeof (int);
- s += sizeof (int);
- cnt -= sizeof (int);
- }
- while (cnt >= sizeof (u16)) {
- *(u16*)d = *(u16*)s;
- d += sizeof (u16);
- s += sizeof (u16);
- cnt -= sizeof (u16);
- }
- while ((cnt) > 0U){
- *d = *s;
- d += 1U;
- s += 1U;
- cnt -= 1U;
- }
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1d/739134595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1d/739134595243001d18b399c1eb9b3628
deleted file mode 100644
index 853ef6b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1d/739134595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,412 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_io.h
-*
-* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
-*
-* The xil_io.h file contains the interface for the general I/O component, which
-* encapsulates the Input/Output functions for the processors that do not
-* require any special I/O handling.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/29/14 First release
-* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
-* ARM processors
-* 7.20 har 01/03/20 Added Xil_SecureOut32 for avoiding blindwrite for
-* CR-1049218
-* 7.30 kpt 09/21/20 Moved Xil_EndianSwap16 and Xil_EndianSwap32 to
-* xil_io.h and made them as static inline
-* am 10/13/20 Changed the return type of Xil_SecureOut32 function
-* from u32 to int
-* 7.50 dp 02/12/21 Fix compilation error in Xil_EndianSwap32() that occur
-* when -Werror=conversion compiler flag is enabled
-* 7.5 mus 05/17/21 Update the functions with comments. It fixes CR#1067739.
-*
-*
-******************************************************************************/
-
-#ifndef XIL_IO_H /* prevent circular inclusions */
-#define XIL_IO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_printf.h"
-#include "xstatus.h"
-
-#if defined (__MICROBLAZE__)
-#include "mb_interface.h"
-#else
-#include "xpseudo_asm.h"
-#endif
-
-/************************** Function Prototypes ******************************/
-#ifdef ENABLE_SAFETY
-extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
-#endif
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#if defined __GNUC__
-#if defined (__MICROBLAZE__)
-# define INST_SYNC mbar(0)
-# define DATA_SYNC mbar(1)
-# else
-# define SYNCHRONIZE_IO dmb()
-# define INST_SYNC isb()
-# define DATA_SYNC dsb()
-# endif
-#else
-# define SYNCHRONIZE_IO
-# define INST_SYNC
-# define DATA_SYNC
-# define INST_SYNC
-# define DATA_SYNC
-#endif
-
-#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
-#define INLINE inline
-#else
-#define INLINE __inline
-#endif
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading
-* from the specified address and returning the 8 bit Value read from
-* that address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 8 bit Value read from the specified input address.
-
-*
-******************************************************************************/
-static INLINE u8 Xil_In8(UINTPTR Addr)
-{
- return *(volatile u8 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading from
-* the specified address and returning the 16 bit Value read from that
-* address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 16 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u16 Xil_In16(UINTPTR Addr)
-{
- return *(volatile u16 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by
-* reading from the specified address and returning the 32 bit Value
-* read from that address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 32 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u32 Xil_In32(UINTPTR Addr)
-{
- return *(volatile u32 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading the
-* 64 bit Value read from that address.
-*
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 64 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u64 Xil_In64(UINTPTR Addr)
-{
- return *(volatile u64 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for an memory location by
-* writing the 8 bit Value to the the specified address.
-*
-* @param Addr: contains the address to perform the output operation
-* @param Value: contains the 8 bit Value to be written at the specified
-* address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
-{
- /* write 8 bit value to specified address */
- volatile u8 *LocalAddr = (volatile u8 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 16 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains the Value to be written at the specified address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
-{
- /* write 16 bit value to specified address */
- volatile u16 *LocalAddr = (volatile u16 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 32 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains the 32 bit Value to be written at the specified
-* address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
-{
- /* write 32 bit value to specified address */
-#ifndef ENABLE_SAFETY
- volatile u32 *LocalAddr = (volatile u32 *)Addr;
- *LocalAddr = Value;
-#else
- XStl_RegUpdate(Addr, Value);
-#endif
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 64 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains 64 bit Value to be written at the specified address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
-{
- /* write 64 bit value to specified address */
- volatile u64 *LocalAddr = (volatile u64 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
- *
- * @brief Performs an output operation for a memory location by writing the
- * 32 bit Value to the the specified address and then reading it
- * back to verify the value written in the register.
- *
- * @param Addr contains the address to perform the output operation
- * @param Value contains 32 bit Value to be written at the specified address
- *
- * @return Returns Status
- * - XST_SUCCESS on success
- * - XST_FAILURE on failure
- *
- *****************************************************************************/
-static INLINE int Xil_SecureOut32(UINTPTR Addr, u32 Value)
-{
- int Status = XST_FAILURE;
- u32 ReadReg;
- u32 ReadRegTemp;
-
- /* writing 32 bit value to specified address */
- Xil_Out32(Addr, Value);
-
- /* verify value written to specified address with multiple reads */
- ReadReg = Xil_In32(Addr);
- ReadRegTemp = Xil_In32(Addr);
-
- if( (ReadReg == Value) && (ReadRegTemp == Value) ) {
- Status = XST_SUCCESS;
- }
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a 16-bit endian conversion.
-*
-* @param Data: 16 bit value to be converted
-*
-* @return 16 bit Data with converted endianness
-*
-******************************************************************************/
-static INLINE __attribute__((always_inline)) u16 Xil_EndianSwap16(u16 Data)
-{
- return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a 32-bit endian conversion.
-*
-* @param Data: 32 bit value to be converted
-*
-* @return 32 bit data with converted endianness
-*
-******************************************************************************/
-static INLINE __attribute__((always_inline)) u32 Xil_EndianSwap32(u32 Data)
-{
- u16 LoWord;
- u16 HiWord;
-
- /* get each of the half words from the 32 bit word */
-
- LoWord = (u16) (Data & 0x0000FFFFU);
- HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
-
- /* byte swap each of the 16 bit half words */
-
- LoWord = (u16)(((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
- HiWord = (u16)(((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
-
- /* swap the half words before returning the value */
-
- return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-# define Xil_In16LE Xil_In16
-# define Xil_In32LE Xil_In32
-# define Xil_Out16LE Xil_Out16
-# define Xil_Out32LE Xil_Out32
-# define Xil_Htons Xil_EndianSwap16
-# define Xil_Htonl Xil_EndianSwap32
-# define Xil_Ntohs Xil_EndianSwap16
-# define Xil_Ntohl Xil_EndianSwap32
-# else
-# define Xil_In16BE Xil_In16
-# define Xil_In32BE Xil_In32
-# define Xil_Out16BE Xil_Out16
-# define Xil_Out32BE Xil_Out32
-# define Xil_Htons(Data) (Data)
-# define Xil_Htonl(Data) (Data)
-# define Xil_Ntohs(Data) (Data)
-# define Xil_Ntohl(Data) (Data)
-#endif
-#else
-# define Xil_In16LE Xil_In16
-# define Xil_In32LE Xil_In32
-# define Xil_Out16LE Xil_Out16
-# define Xil_Out32LE Xil_Out32
-# define Xil_Htons Xil_EndianSwap16
-# define Xil_Htonl Xil_EndianSwap32
-# define Xil_Ntohs Xil_EndianSwap16
-# define Xil_Ntohl Xil_EndianSwap32
-#endif
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE u16 Xil_In16BE(UINTPTR Addr)
-#else
-static INLINE u16 Xil_In16LE(UINTPTR Addr)
-#endif
-#else
-static INLINE u16 Xil_In16BE(UINTPTR Addr)
-#endif
-{
- u16 value = Xil_In16(Addr);
- return Xil_EndianSwap16(value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE u32 Xil_In32BE(UINTPTR Addr)
-#else
-static INLINE u32 Xil_In32LE(UINTPTR Addr)
-#endif
-#else
-static INLINE u32 Xil_In32BE(UINTPTR Addr)
-#endif
-{
- u32 value = Xil_In32(Addr);
- return Xil_EndianSwap32(value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
-#else
-static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
-#endif
-#else
-static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
-#endif
-{
- Value = Xil_EndianSwap16(Value);
- Xil_Out16(Addr, Value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
-#else
-static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
-#endif
-#else
-static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
-#endif
-{
- Value = Xil_EndianSwap32(Value);
- Xil_Out32(Addr, Value);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_io_interfacing_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1d/80a6ba585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1d/80a6ba585243001d18b399c1eb9b3628
deleted file mode 100644
index b8b9f7a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1d/80a6ba585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,34 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/*
- *
- * This is a template implementation of the "__lseek" function used by
- * the standard library. Replace it with a system-specific
- * implementation.
- *
- * The "__lseek" function makes the next file operation (__read or
- * __write) act on a new location. The parameter "whence" specifies
- * how the "offset" parameter should be interpreted according to the
- * following table:
- *
- * 0 (=SEEK_SET) - Goto location "offset".
- * 1 (=SEEK_CUR) - Go "offset" bytes from the current location.
- * 2 (=SEEK_END) - Go to "offset" bytes from the end.
- *
- * This function should return the current file position, or -1 on
- * failure.
- */
-
-#include
-#include
-#include "xil_types.h"
-LONG __lseek(sint32 handle, LONG offset, sint32 whence);
-
-LONG __lseek(sint32 handle, LONG offset, sint32 whence)
-{
- return (-1);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1d/d14ff5565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1d/d14ff5565243001d18b399c1eb9b3628
deleted file mode 100644
index 14446f4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1d/d14ff5565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,143 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xplatform_info.c
-* @addtogroup common_platform_info Hardware Platform Information
-* @{
-* This file contains information about hardware for which the code is built
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 5.00 pkp 12/15/14 Initial release
-* 5.04 pkp 01/12/16 Added platform information support for Cortex-A53 32bit
-* mode
-* 6.00 mus 17/08/16 Removed unused variable from XGetPlatform_Info
-* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
-* function for PMUFW.
-* ms 06/13/17 Added PSU_PMU macro to provide support of
-* XGetPlatform_Info function for PMUFW.
-* mus 08/17/17 Add EL1 NS mode support for
-* XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info
-* APIs.
-* 7.0 aru 03/15/19 Check for versal before aarch64 and armr5
-* in XGetPlatform_Info()
-* 7.2 adk 08/01/20 Added versal support for the XGetPSVersion_Info function.
-* 7.6 mus 08/23/21 Updated prototypes for functions which are not taking any
-* arguments with void keyword. This has been done to fix
-* compilation warnings with "-Wstrict-prototypes" flag.
-* It fixes CR#1108601.
-* 7.6 mus 08/30/21 Updated flag checking to fix compilation warnings
-* reported with "-Wundef" flag. It fixes CR#1108601.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xplatform_info.h"
-#if defined (__aarch64__)
-#include "bspconfig.h"
-#include "xil_smc.h"
-#endif
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* @brief This API is used to provide information about platform
-*
-* @return The information about platform defined in xplatform_info.h
-*
-******************************************************************************/
-u32 XGetPlatform_Info(void)
-{
-#if defined (versal)
- return XPLAT_VERSAL;
-#elif defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU)
- return XPLAT_ZYNQ_ULTRA_MP;
-#elif defined (__microblaze__)
- return XPLAT_MICROBLAZE;
-#else
- return XPLAT_ZYNQ;
-#endif
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief This API is used to provide information about zynq ultrascale MP platform
-*
-* @return The information about zynq ultrascale MP platform defined in
-* xplatform_info.h
-*
-******************************************************************************/
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
-u32 XGet_Zynq_UltraMp_Platform_info(void)
-{
-#if EL1_NONSECURE
- XSmc_OutVar reg;
- /*
- * This SMC call will return,
- * idcode - upper 32 bits of reg.Arg0
- * version - lower 32 bits of reg.Arg1
- */
- reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
- return (u32)((reg.Arg1 >> XPLAT_INFO_SHIFT) & XPLAT_INFO_MASK);
-#else
- u32 reg;
- reg = ((Xil_In32(XPLAT_PS_VERSION_ADDRESS) >> XPLAT_INFO_SHIFT )
- & XPLAT_INFO_MASK);
- return reg;
-#endif
-}
-#endif
-
-/*****************************************************************************/
-/**
-*
-* @brief This API is used to provide information about PS Silicon version
-*
-* @return The information about PS Silicon version.
-*
-******************************************************************************/
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU) || defined (versal)
-u32 XGetPSVersion_Info(void)
-{
-#if EL1_NONSECURE
- /*
- * This SMC call will return,
- * idcode - upper 32 bits of reg.Arg0
- * version - lower 32 bits of reg.Arg1
- */
- XSmc_OutVar reg;
- reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
- return (u32)((reg.Arg1 & XPS_VERSION_INFO_MASK) >>
- XPS_VERSION_INFO_SHIFT);
-#else
- u32 reg;
- reg = (Xil_In32(XPLAT_PS_VERSION_ADDRESS)
- & XPS_VERSION_INFO_MASK);
- return (reg >> XPS_VERSION_INFO_SHIFT);
-#endif
-}
-#endif
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1d/e023ee565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1d/e023ee565243001d18b399c1eb9b3628
deleted file mode 100644
index aa666d1..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1d/e023ee565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1568 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_testmem.c
-* @addtogroup common_test_utils
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 08/25/09 First release
-* 7.5 mus 03/10/21 Added new set of Xil_TestMem32, Xil_TestMem16 and
-* Xil_TestMem8 APIs to support memory test for memory
-* regions mapped at extended addresses
-* (addresses > 4 GB). These new set of APIs would be
-* compiled only for 32 bit Microblaze processor, if
-* XPAR_MICROBLAZE_ADDR_SIZE is greater than 32.
-* It fixes CR#1089129.
-* 7.6 mus 07/29/21 Updated Xil_TestMem8 to fix issues reported by static
-* analysis tool. It fixes CR#1105956.
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xil_testmem.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions ****************************/
-/************************** Function Prototypes *****************************/
-
-static u32 RotateLeft(u32 Input, u8 Width);
-
-/* define ROTATE_RIGHT to give access to this functionality */
-/* #define ROTATE_RIGHT */
-#ifdef ROTATE_RIGHT
-static u32 RotateRight(u32 Input, u8 Width);
-#endif /* ROTATE_RIGHT */
-
-#if defined(__MICROBLAZE__) && !defined(__arch64__) && (XPAR_MICROBLAZE_ADDR_SIZE > 32)
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 8-bit wide memory test.
-*
-* @param Addrlow: lower 32 bit address of memory to be tested.
-* @param Addrhigh: upper 32 bit address of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: type of test selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u8 Val;
- u8 WordMem8;
- s32 Status = 0;
- u64 Addr = (Addrlow + ((u64)Addrhigh << 32));
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * select the proper Subtest(s)
- */
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from XIL_TESTMEM_INIT_VALUE
- */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- sbea(Addr+I, Val);
- Val++;
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = XIL_TESTMEM_INIT_VALUE;
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference
- * Val
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = lbuea(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val++;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking ones test
- */
-
- for (j = 0U; j < NUM_OF_BITS_IN_BYTE; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
- Val = (u8)((u32)1 << j);
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
- for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) {
- /* write memory location */
- sbea(Addr+I, Val);
- Val = (u8)RotateLeft(Val, 8U);
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u8)((u32)1 << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) {
- /* read memory location */
- WordMem8 = lbuea(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = (u8)RotateLeft(Val, NUM_OF_BITS_IN_BYTE);
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible initial test
- * Patterns for walking zeros test
- */
-
- for (j = 0U; j < NUM_OF_BITS_IN_BYTE; j++) {
- /*
- * Generate an initial value for walking ones test to test
- * for bad data bits
- */
- Val = (u8) (~(1U << j));
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
- for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) {
- /* write memory location */
- sbea(Addr+I, Val);
- Val = ~((u8)RotateLeft(~Val, NUM_OF_BITS_IN_BYTE));
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u8) (~(1U << j));
- /* Read the values from each location that was written */
- for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) {
- /* read memory location */
- WordMem8 = lbuea(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val = ~((u8)RotateLeft(~Val, NUM_OF_BITS_IN_BYTE));
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- Val = (u8) (~((INTPTR) (Addr + I)));
- sbea(Addr+I, Val);
- }
-
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = lbuea(Addr+I);
- Val = (u8) (~((INTPTR) (Addr+I)));
- if ((WordMem8 ^ Val) != 0x00U) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
-
- if (Pattern == (u8)0) {
- Val = 0xA5U;
- }
- else {
- Val = Pattern;
- }
- /*
- * Fill the memory with fixed Pattern
- */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- sbea(Addr+I, Val);
- }
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed Pattern
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = lbuea(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
-End_Label:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 16-bit wide memory test.
-*
-* @param Addrlow: lower 32 bit address of memory to be tested.
-* @param Addrhigh: upper 32 bit address of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant Pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: type of test selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u16 Val;
- u16 WordMem16;
- s32 Status = 0;
- u64 Addr = (Addrlow + ((u64)Addrhigh << 32));
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * selectthe proper Subtest(s)
- */
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from 'XIL_TESTMEM_INIT_VALUE'
- */
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) {
- /* write memory location */
- shea(Addr+I, Val);
- Val++;
- I = I + NUM_OF_BYTES_IN_HW;
- }
-
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference val
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) {
- /* read memory location */
- WordMem16 = lhuea(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val++;
- I = I + NUM_OF_BYTES_IN_HW;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial test
- * Patterns for walking ones test
- */
-
- for (j = 0U; j < NUM_OF_BITS_IN_HW; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = (u16)((u32)1 << j);
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) {
- /* write memory location */
- shea(Addr+I,Val);
- Val = (u16)RotateLeft(Val, 16U);
- I = I + NUM_OF_BYTES_IN_HW;
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u16)((u32)1 << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) {
- /* read memory location */
- WordMem16 = lhuea(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = (u16)RotateLeft(Val, NUM_OF_BITS_IN_HW);
- I = I + NUM_OF_BYTES_IN_HW;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking zeros test
- */
-
- for (j = 0U; j < NUM_OF_BITS_IN_HW; j++) {
- /*
- * Generate an initial value for walking ones
- * test to test for bad
- * data bits
- */
-
- Val = ~(1U << j);
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW);) {
- shea(Addr+I, Val);
- Val = ~((u16)RotateLeft(~Val, 16U));
- I = I + NUM_OF_BYTES_IN_HW;
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = ~(1U << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) {
- WordMem16= lhuea(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = ~((u16)RotateLeft(~Val, NUM_OF_BITS_IN_HW));
- I = I + NUM_OF_BYTES_IN_HW;
- }
-
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) {
- /* write memory location */
- Val = (u16) (~((INTPTR)((Addr+I))));
- shea(Addr+I, Val);
- I = I + NUM_OF_BYTES_IN_HW;
- }
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW*Words); ) {
- /* read memory location */
- //WordMem16 = *(Addr+I);
- WordMem16 = lhuea(Addr+I);
- Val = (u16) (~((INTPTR) ((Addr+I))));
- if ((WordMem16 ^ Val) != 0x0000U) {
- Status = -1;
- goto End_Label;
- }
- I = I + NUM_OF_BYTES_IN_HW;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
- if (Pattern == (u16)0) {
- Val = 0xDEADU;
- }
- else {
- Val = Pattern;
- }
-
- /*
- * Fill the memory with fixed pattern
- */
-
- for (I = 0U; I < (2*Words);) {
- /* write memory location */
- shea(Addr+I, Val);
- I = I + NUM_OF_BYTES_IN_HW;
- }
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed pattern
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) {
- /* read memory location */
- WordMem16=lhuea(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- I = I + NUM_OF_BYTES_IN_HW;
- }
- }
-End_Label:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 32-bit wide memory test.
-*
-* @param Addrlow: lower 32 bit address of memory to be tested.
-* @param Addrhigh: upper 32 bit address of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: test type selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-* - 0 is returned for a pass
-* - 1 is returned for a failure
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u32 Val;
- u32 WordMem32;
- s32 Status = 0;
- u64 Addr = (Addrlow + ((u64)Addrhigh << 32));
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
-
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from 'XIL_TESTMEM_INIT_VALUE'
- */
- for (I = 0U; I <(NUM_OF_BYTES_IN_WORD * Words);) {
- swea(Addr+I, Val);
- Val++;
- I = I + NUM_OF_BYTES_IN_WORD;
- }
-
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference
- * Val
- */
-
- for (I = 0U; I < ( NUM_OF_BYTES_IN_WORD * Words);) {
- WordMem32 = lwea(Addr+I);
-
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val++;
- I = I + NUM_OF_BYTES_IN_WORD;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking ones test
- */
-
- for (j = 0U; j < NUM_OF_BITS_IN_WORD; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = (1U << j);
-
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * NUM_OF_BITS_IN_WORD);) {
- /* write memory location */
- swea(Addr+I, Val);
- Val = (u32) RotateLeft(Val, NUM_OF_BITS_IN_WORD);
- I = I + NUM_OF_BYTES_IN_WORD;
- }
-
- /*
- * Restore the reference 'val' to the
- * initial value
- */
- Val = 1U << j;
-
- /* Read the values from each location that was
- * written */
- for (I = 0U; I < ((u32)32 * NUM_OF_BYTES_IN_WORD);) {
- /* read memory location */
-
- WordMem32 = lwea(Addr+I);
-
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val = (u32)RotateLeft(Val, NUM_OF_BITS_IN_WORD);
- I = I + NUM_OF_BYTES_IN_WORD;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible
- * initial test Patterns for walking zeros test
- */
-
- for (j = 0U; j < NUM_OF_BITS_IN_WORD; j++) {
-
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = ~(1U << j);
-
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (NUM_OF_BITS_IN_WORD * NUM_OF_BYTES_IN_WORD);) {
- /* write memory location */
- swea(Addr+I, Val);
- Val = ~((u32)RotateLeft(~Val, NUM_OF_BITS_IN_WORD));
- I = I + NUM_OF_BYTES_IN_WORD;
- }
-
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
-
- Val = ~(1U << j);
-
- /* Read the values from each location that was
- * written */
- for (I = 0U; I < (NUM_OF_BITS_IN_WORD * NUM_OF_BYTES_IN_WORD);) {
- /* read memory location */
- WordMem32 = lwea(Addr+I);
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = ~((u32)RotateLeft(~Val, NUM_OF_BITS_IN_WORD));
- I = I + NUM_OF_BYTES_IN_WORD;
- }
-
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) {
- /* write memory location */
- Val = (u32) (~((INTPTR) (Addr+I)));
- swea(Addr+I, Val);
- I = I + NUM_OF_BYTES_IN_WORD;
- }
-
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) {
- /* Read the location */
- WordMem32 = lwea(Addr+I);
- Val = (u32) (~((INTPTR) (Addr+I)));
-
- if ((WordMem32 ^ Val) != 0x00000000U) {
- Status = -1;
- goto End_Label;
- }
- I = I + NUM_OF_BYTES_IN_WORD;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
-
- if (Pattern == (u32)0) {
- Val = 0xDEADBEEFU;
- }
- else {
- Val = Pattern;
- }
-
- /*
- * Fill the memory with fixed Pattern
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) {
- /* write memory location */
- swea(Addr+I, Val);
- I = I + NUM_OF_BYTES_IN_WORD;
- }
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed Pattern
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) {
-
- /* read memory location */
-
- WordMem32 = lwea(Addr+I);
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
- I = I + NUM_OF_BYTES_IN_WORD;
- }
- }
-
-End_Label:
- return Status;
-}
-
-#else
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 32-bit wide memory test.
-*
-* @param Addr: pointer to the region of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: test type selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-* - 0 is returned for a pass
-* - 1 is returned for a failure
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u32 Val;
- u32 FirtVal;
- u32 WordMem32;
- s32 Status = 0;
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
- FirtVal = XIL_TESTMEM_INIT_VALUE;
-
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from 'FirtVal'
- */
- for (I = 0U; I < Words; I++) {
- *(Addr+I) = Val;
- Val++;
- }
-
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = FirtVal;
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference
- * Val
- */
-
- for (I = 0U; I < Words; I++) {
- WordMem32 = *(Addr+I);
-
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val++;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking ones test
- */
-
- for (j = 0U; j < (u32)32; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = (1U << j);
-
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (u32)32; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = (u32) RotateLeft(Val, 32U);
- }
-
- /*
- * Restore the reference 'val' to the
- * initial value
- */
- Val = 1U << j;
-
- /* Read the values from each location that was
- * written */
- for (I = 0U; I < (u32)32; I++) {
- /* read memory location */
-
- WordMem32 = *(Addr+I);
-
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val = (u32)RotateLeft(Val, 32U);
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible
- * initial test Patterns for walking zeros test
- */
-
- for (j = 0U; j < (u32)32; j++) {
-
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = ~(1U << j);
-
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (u32)32; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = ~((u32)RotateLeft(~Val, 32U));
- }
-
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
-
- Val = ~(1U << j);
-
- /* Read the values from each location that was
- * written */
- for (I = 0U; I < (u32)32; I++) {
- /* read memory location */
- WordMem32 = *(Addr+I);
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = ~((u32)RotateLeft(~Val, 32U));
- }
-
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- Val = (u32) (~((INTPTR) (&Addr[I])));
- *(Addr+I) = Val;
- }
-
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < Words; I++) {
- /* Read the location */
- WordMem32 = *(Addr+I);
- Val = (u32) (~((INTPTR) (&Addr[I])));
-
- if ((WordMem32 ^ Val) != 0x00000000U) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
-
- if (Pattern == (u32)0) {
- Val = 0xDEADBEEFU;
- }
- else {
- Val = Pattern;
- }
-
- /*
- * Fill the memory with fixed Pattern
- */
-
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- }
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed Pattern
- */
-
- for (I = 0U; I < Words; I++) {
-
- /* read memory location */
-
- WordMem32 = *(Addr+I);
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
-End_Label:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 16-bit wide memory test.
-*
-* @param Addr: pointer to the region of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant Pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: type of test selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-* @note Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u16 Val;
- u16 FirtVal;
- u16 WordMem16;
- s32 Status = 0;
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
- FirtVal = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * selectthe proper Subtest(s)
- */
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from 'FirtVal'
- */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val++;
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = FirtVal;
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference val
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val++;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial test
- * Patterns for walking ones test
- */
-
- for (j = 0U; j < (u32)16; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = (u16)((u32)1 << j);
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (u32)16; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = (u16)RotateLeft(Val, 16U);
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u16)((u32)1 << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < (u32)16; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = (u16)RotateLeft(Val, 16U);
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking zeros test
- */
-
- for (j = 0U; j < (u32)16; j++) {
- /*
- * Generate an initial value for walking ones
- * test to test for bad
- * data bits
- */
-
- Val = ~(1U << j);
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (u32)16; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = ~((u16)RotateLeft(~Val, 16U));
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = ~(1U << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < (u32)16; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = ~((u16)RotateLeft(~Val, 16U));
- }
-
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- Val = (u16) (~((INTPTR)(&Addr[I])));
- *(Addr+I) = Val;
- }
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- Val = (u16) (~((INTPTR) (&Addr[I])));
- if ((WordMem16 ^ Val) != 0x0000U) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
- if (Pattern == (u16)0) {
- Val = 0xDEADU;
- }
- else {
- Val = Pattern;
- }
-
- /*
- * Fill the memory with fixed pattern
- */
-
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- }
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed pattern
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
-End_Label:
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 8-bit wide memory test.
-*
-* @param Addr: pointer to the region of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: type of test selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u8 Val;
- u8 FirtVal;
- u8 WordMem8;
- s32 Status = 0;
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
- FirtVal = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * select the proper Subtest(s)
- */
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from 'FirtVal'
- */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val++;
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = FirtVal;
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference
- * Val
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val++;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking ones test
- */
-
- for (j = 0U; j < (u32)8; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
- Val = (u8)((u32)1 << j);
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
- for (I = 0U; I < (u32)8; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = (u8)RotateLeft(Val, 8U);
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u8)((u32)1 << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < (u32)8; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = (u8)RotateLeft(Val, 8U);
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible initial test
- * Patterns for walking zeros test
- */
-
- for (j = 0U; j < (u32)8; j++) {
- /*
- * Generate an initial value for walking ones test to test
- * for bad data bits
- */
- Val = (u8) (~(1U << j));
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
- for (I = 0U; I < (u32)8; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = ~((u8)RotateLeft(~Val, 8U));
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u8) (~(1U << j));
- /* Read the values from each location that was written */
- for (I = 0U; I < (u32)8; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val = ~((u8)RotateLeft(~Val, 8U));
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- Val = (u8) (~((INTPTR) (&Addr[I])));
- *(Addr+I) = Val;
- }
-
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- Val = (u8) (~((INTPTR) (&Addr[I])));
- if ((WordMem8 ^ Val) != 0x00U) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
-
- if (Pattern == (u8)0) {
- Val = 0xA5U;
- }
- else {
- Val = Pattern;
- }
- /*
- * Fill the memory with fixed Pattern
- */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- }
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed Pattern
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
-End_Label:
- return Status;
-}
-#endif
-
-/*****************************************************************************/
-/**
-*
-* @brief Rotates the provided value to the left one bit position
-*
-* @param Input is value to be rotated to the left
-* @param Width is the number of bits in the input data
-*
-* @return The resulting unsigned long value of the rotate left
-*
-*
-*****************************************************************************/
-static u32 RotateLeft(u32 Input, u8 Width)
-{
- u32 Msb;
- u32 ReturnVal;
- u32 WidthMask;
- u32 MsbMask;
- u32 LocalInput = Input;
-
- /*
- * set up the WidthMask and the MsbMask
- */
-
- MsbMask = 1U << (Width - 1U);
-
- WidthMask = (MsbMask << (u32)1) - (u32)1;
-
- /*
- * set the Width of the Input to the correct width
- */
-
- LocalInput = LocalInput & WidthMask;
-
- Msb = LocalInput & MsbMask;
-
- ReturnVal = LocalInput << 1U;
-
- if (Msb != 0x00000000U) {
- ReturnVal = ReturnVal | (u32)0x00000001;
- }
-
- ReturnVal = ReturnVal & WidthMask;
-
- return ReturnVal;
-
-}
-
-#ifdef ROTATE_RIGHT
-/*****************************************************************************/
-/**
-*
-* @brief Rotates the provided value to the right one bit position
-*
-* @param Input: value to be rotated to the right
-* @param Width: number of bits in the input data
-*
-* @return
-* The resulting u32 value of the rotate right
-*
-*****************************************************************************/
-static u32 RotateRight(u32 Input, u8 Width)
-{
- u32 Lsb;
- u32 ReturnVal;
- u32 WidthMask;
- u32 MsbMask;
- u32 LocalInput = Input;
- /*
- * set up the WidthMask and the MsbMask
- */
-
- MsbMask = 1U << (Width - 1U);
-
- WidthMask = (MsbMask << 1U) - 1U;
-
- /*
- * set the width of the input to the correct width
- */
-
- LocalInput = LocalInput & WidthMask;
-
- ReturnVal = LocalInput >> 1U;
-
- Lsb = LocalInput & 0x00000001U;
-
- if (Lsb != 0x00000000U) {
- ReturnVal = ReturnVal | MsbMask;
- }
-
- ReturnVal = ReturnVal & WidthMask;
-
- return ReturnVal;
-
-}
-#endif /* ROTATE_RIGHT */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1d/f037a1525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1d/f037a1525243001d18b399c1eb9b3628
deleted file mode 100644
index d8aef59..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1d/f037a1525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,169 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xenv.h
-*
-* Defines common services that are typically found in a host operating.
-* environment. This include file simply includes an OS specific file based
-* on the compile-time constant BUILD_ENV_*, where * is the name of the target
-* environment.
-*
-* All services are defined as macros.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b ch 10/24/02 Added XENV_LINUX
-* 1.00a rmm 04/17/02 First release
-*
-* The translation_table.S contains a static page table required by MMU for
-* cortex-A53. This translation table is flat mapped (input address = output
-* address) with default memory attributes defined for zynq ultrascale+
-* architecture. It utilizes short descriptor translation table format with each
-* section defining 1MB of memory.
-*
-* For DDR in region 0x00000000 - 0x7FFFFFFF, a system where DDR is less than
-* 2GB, region after DDR and before PL is marked as undefined/reserved in
-* translation table. In region 0xFFC00000 - 0xFFDFFFFF, it contains CSU
-* and PMU memory which are marked as Device since it is less than 1MB and
-* falls in a region with device memory.
-*
-* The overview of translation table memory attributes is described below.
-*
-*| | Memory Range | Definition in Translation Table |
-*|-----------------|-------------------------|---------------------------------|
-*| DDR | 0x00000000 - 0x7FFFFFFF | Normal write-back Cacheable |
-*| PL | 0x80000000 - 0xBFFFFFFF | Strongly Ordered |
-*| QSPI, lower PCIe| 0xC0000000 - 0xEFFFFFFF | Device Memory |
-*| Reserved | 0xF0000000 - 0xF7FFFFFF | Unassigned |
-*| STM Coresight | 0xF8000000 - 0xF8FFFFFF | Device Memory |
-*| GIC | 0xF9000000 - 0xF90FFFFF | Device memory |
-*| Reserved | 0xF9100000 - 0xFCFFFFFF | Unassigned |
-*| FPS, LPS slaves | 0xFD000000 - 0xFFBFFFFF | Device memory |
-*| CSU, PMU | 0xFFC00000 - 0xFFDFFFFF | Device Memory |
-*| TCM, OCM | 0xFFE00000 - 0xFFFFFFFF | Normal write-back cacheable |
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 5.4 pkp 18/12/15 Updated the address map according to proper address map
-* 6.0 mus 20/07/16 Added warning for ddrless HW design CR-954977
-*
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- --------------------------------------------------------
- * 1.00a jz 10/10/10 First release
- * 2.1 kpc 04/28/14 Removed unused functions
- * 2.5 pm 02/20/20 Added usb state interface.
- *
- ******************************************************************************/
-
-/***************************** Include Files **********************************/
-#include
-#include "xusbps.h"
-
-/************************** Constant Definitions ******************************/
-
-/**************************** Type Definitions ********************************/
-
-/***************** Macros (Inline Functions) Definitions **********************/
-
-/************************** Variable Definitions ******************************/
-
-/************************** Function Prototypes *******************************/
-
-/*****************************************************************************/
-/**
-*
-* This function initializes a XUsbPs instance/driver.
-*
-* The initialization entails:
-* - Initialize all members of the XUsbPs structure.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param ConfigPtr is a pointer to a XUsbPs_Config configuration
-* structure. This structure will contain the requested
-* configuration for the device. Typically, this is a local
-* structure and the content of which will be copied into the
-* configuration structure within XUsbPs.
-* @param VirtBaseAddress is the base address of the device. For systems
-* with virtual memory, this address must be the virtual address
-* of the device.
-* For systems that do not support virtual memory this address
-* should be the physical address of the device. For backwards
-* compatibility NULL may be passed in systems that do not support
-* virtual memory (deprecated).
-*
-* @return
-* - XST_SUCCESS no errors occurred.
-* - XST_FAILURE an error occurred during initialization.
-*
-* @note
-* After calling XUsbPs_CfgInitialize() the controller
-* IS NOT READY for use. Before the controller can be used its
-* DEVICE parameters must be configured. See xusbps.h
-* for details.
-*
-******************************************************************************/
-int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
- const XUsbPs_Config *ConfigPtr, u32 VirtBaseAddress)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
-
- /* Copy the config structure. */
- InstancePtr->Config = *ConfigPtr;
-
- /* Check if the user provided a non-NULL base address. If so, we have
- * to overwrite the base address in the configuration structure.
- */
- if (0 != VirtBaseAddress) {
- InstancePtr->Config.BaseAddress = VirtBaseAddress;
- }
-
- /* Initialize the XUsbPs structure to default values. */
- InstancePtr->CurrentAltSetting = XUSBPS_DEFAULT_ALT_SETTING;
-
- InstancePtr->HandlerFunc = NULL;
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function performs device reset, device is stopped at the end.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XUsbPs_DeviceReset(XUsbPs *InstancePtr)
-{
- int Timeout;
-
- /* Clear all setup token semaphores by reading the
- * XUSBPS_EPSTAT_OFFSET register and writing its value back to
- * itself.
- */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPSTAT_OFFSET,
- XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPSTAT_OFFSET));
-
- /* Clear all the endpoint complete status bits by reading the
- * XUSBPS_EPCOMPL_OFFSET register and writings its value back
- * to itself.
- */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPCOMPL_OFFSET,
- XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPCOMPL_OFFSET));
-
- /* Cancel all endpoint prime status by waiting until all bits
- * in XUSBPS_EPPRIME_OFFSET are 0 and then writing 0xFFFFFFFF
- * to XUSBPS_EPFLUSH_OFFSET.
- *
- * Avoid hanging here by using a Timeout counter...
- */
- Timeout = XUSBPS_TIMEOUT_COUNTER;
- while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPPRIME_OFFSET) &
- XUSBPS_EP_ALL_MASK) && --Timeout) {
- /* NOP */
- }
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF);
-
- XUsbPs_Stop(InstancePtr);
-
- /* Write to CR register for controller reset */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
- XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_CMD_OFFSET) | XUSBPS_CMD_RST_MASK);
-
- /* Wait for reset to finish, hardware clears the reset bit once done */
- Timeout = 1000000;
- while((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_CMD_OFFSET) &
- XUSBPS_CMD_RST_MASK) && --Timeout) {
- /* NOP */
- }
-}
-/*****************************************************************************/
-/**
-*
-* This function resets the USB device. All the configuration registers are
-* reset to their default values. The function waits until the reset operation
-* is complete or for a certain duration within which the reset operation is
-* expected to be completed.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @return
-* - XST_SUCCESS Reset operation completed successfully.
-* - XST_FAILURE Reset operation timed out.
-*
-* @note None.
-*
-******************************************************************************/
-int XUsbPs_Reset(XUsbPs *InstancePtr)
-{
- int Timeout;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /* Write a 1 to the RESET bit. The RESET bit is cleared by HW once the
- * RESET is complete.
- *
- * We are going to wait for the RESET bit to clear before we return
- * from this function. Unfortunately we do not have timers available at
- * this point to determine when we should report a Timeout.
- *
- * However, by using a large number for the poll loop we can assume
- * that the polling operation will take longer than the expected time
- * the HW needs to RESET. If the poll loop expires we can assume a
- * Timeout. The drawback is that on a slow system (and even on a fast
- * system) this can lead to _very_ long Timeout periods.
- */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_CMD_OFFSET, XUSBPS_CMD_RST_MASK);
-
-
- /* Wait for the RESET bit to be cleared by HW. */
- Timeout = XUSBPS_TIMEOUT_COUNTER;
- while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_CMD_OFFSET) &
- XUSBPS_CMD_RST_MASK) && --Timeout) {
- /* NOP */
- }
-
- if (0 == Timeout) {
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * USB Suspend
- *
- * In order to conserve power, USB devices automatically enter the suspended
- * state when the device has observed no bus traffic for a specified period.
- * When suspended, the USB device maintains any internal status, including its
- * address and configuration. Attached devices must be prepared to suspend at
- * any time they are powered, regardless of if they have been assigned a
- * non-default address, are configured, or neither. Bus activity may cease due
- * to the host entering a suspend mode of its own. In addition, a USB device
- * shall also enter the suspended state when the hub port it is attached to is
- * disabled.
- *
- * A USB device exits suspend mode when there is bus activity. A USB device may
- * also request the host to exit suspend mode or selective suspend by using
- * electrical signaling to indicate remote wakeup. The ability of a device to
- * signal remote wakeup is optional. If the USB device is capable of remote
- * wakeup signaling, the device must support the ability of the host to enable
- * and disable this capability. When the device is reset, remote wakeup
- * signaling must be disabled.
- *
- * @param InstancePtr is a pointer to XUsbPs instance of the controller.
- *
- * @return
- * - XST_SUCCESS if the USB device has entered Suspend mode
- * successfully
- * - XST_FAILURE on any error
- *
- * @note None.
- *
- ******************************************************************************/
-int XUsbPs_Suspend(const XUsbPs *InstancePtr)
-{
- (void) InstancePtr;
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-* USB Resume
-*
- If the USB controller is suspended, its operation is resumed when any
-* non-idle signaling is received on its upstream facing port.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @return
-* - XST_SUCCESS if the USB device has Resumed successfully
-* - XST_FAILURE on any error
-*
-* @note None.
-*
-******************************************************************************/
-int XUsbPs_Resume(const XUsbPs *InstancePtr)
-{
- (void) InstancePtr;
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-* USB Assert Resume
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @return
-* - XST_SUCCESS if the USB device has Resumed successfully
-* - XST_FAILURE on any error
-*
-* @note None.
-*
-******************************************************************************/
-
-int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr)
-{
- (void) InstancePtr;
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-* This functions sets the controller's DEVICE address. It also sets the
-* advance bit so the controller will wait for the next IN-ACK before the new
-* address takes effect.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param Address is the Address of the device.
-*
-* @return
-* - XST_SUCCESS: Address set successfully.
-* - XST_FAILURE: An error occurred.
-* - XST_INVALID_PARAM: Invalid parameter passed, e.g. address
-* value too big.
-*
-* @note None.
-*
-*****************************************************************************/
-int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- if ((InstancePtr->AppData != NULL) &&
- (InstancePtr->AppData->State ==
- XUSBPS_STATE_CONFIGURED)) {
- return XST_FAILURE;
- }
-
- /* Check address range validity. */
- if (Address > XUSBPS_DEVICEADDR_MAX) {
- return XST_INVALID_PARAM;
- }
-
- /* Set the address register with the Address value provided. Also set
- * the Address Advance Bit. This will cause the address to be set only
- * after an IN occurred and has been ACKed on the endpoint.
- */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_DEVICEADDR_OFFSET,
- (Address << XUSBPS_DEVICEADDR_ADDR_SHIFT) |
- XUSBPS_DEVICEADDR_DEVICEAADV_MASK);
-
- if (InstancePtr->AppData != NULL) {
- if (Address)
- InstancePtr->AppData->State = XUSBPS_STATE_ADDRESS;
- else
- InstancePtr->AppData->State = XUSBPS_STATE_DEFAULT;
- }
- return XST_SUCCESS;
-}
-
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1f/a0217b575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1f/a0217b575243001d18b399c1eb9b3628
deleted file mode 100644
index 2e5cbd5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1f/a0217b575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,146 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xgpiops_hw.h
-* @addtogroup gpiops_v3_9
-* @{
-*
-* This header file contains the identifiers and basic driver functions (or
-* macros) that can be used to access the device. Other driver functions
-* are defined in xgpiops.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------
-* 1.00a sv 01/15/10 First Release
-* 1.02a hk 08/22/13 Added low level reset API function prototype and
-* related constant definitions
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/13/15 Corrected reset values of banks.
-* 3.5 sne 03/14/19 Added versal support.
-*
-*
-******************************************************************************/
-#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
-#define XGPIOPS_HW_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register offsets for the GPIO. Each register is 32 bits.
- * @{
- */
-#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /**< Mask and Data Register LSW, WO */
-#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /**< Mask and Data Register MSW, WO */
-#define XGPIOPS_DATA_OFFSET 0x00000040U /**< Data Register, RW */
-#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /**< Data Register - Input, RO */
-#define XGPIOPS_DIRM_OFFSET 0x00000204U /**< Direction Mode Register, RW */
-#define XGPIOPS_OUTEN_OFFSET 0x00000208U /**< Output Enable Register, RW */
-#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /**< Interrupt Mask Register, RO */
-#define XGPIOPS_INTEN_OFFSET 0x00000210U /**< Interrupt Enable Register, WO */
-#define XGPIOPS_INTDIS_OFFSET 0x00000214U /**< Interrupt Disable Register, WO*/
-#define XGPIOPS_INTSTS_OFFSET 0x00000218U /**< Interrupt Status Register, RO */
-#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /**< Interrupt Type Register, RW */
-#define XGPIOPS_INTPOL_OFFSET 0x00000220U /**< Interrupt Polarity Register, RW */
-#define XGPIOPS_INTANY_OFFSET 0x00000224U /**< Interrupt On Any Register, RW */
-/** @} */
-
-/** @name Register offsets for each Bank.
- * @{
- */
-#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /**< Data/Mask Registers offset */
-#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /**< Data Registers offset */
-#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /**< Registers offset */
-/** @} */
-
-/* For backwards compatibility */
-#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40 /**< Mask for backward support */
-
-/** @name Interrupt type reset values for each bank
- * @{
- */
-#ifdef XPAR_PSU_GPIO_0_BASEADDR
-#define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-#define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-#define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-#else
-#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /**< Resets specific to Zynq */
-#define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU /**< Resets specific to Zynq */
-#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU /**< Resets specific to Zynq */
-#endif
-
-#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /**< Reset common to both platforms */
-#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-/** @} */
-#define XGPIOPS_PS_GPIO_BASEADDR 0xFF0B0000U /**< Flag for Base Address for PS_GPIO in Versal */
-#define XGPIOPS_ZERO 0U /**< Flag for 0 Value */
-#define XGPIOPS_ONE 1U /**< Flag for 1 Value */
-#define XGPIOPS_TWO 2U /**< Flag for 2 Value */
-#define XGPIOPS_THREE 3U /**< Flag for 3 Value */
-#define XGPIOPS_FOUR 4U /**< Flag for 4 Value */
-#define XGPIOPS_SIX 6U /**< Flag for 6 Value */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* This macro reads the given register.
-*
-* @param BaseAddr is the base address of the device.
-* @param RegOffset is the register offset to be read.
-*
-* @return The 32-bit value of the register
-*
-* @note None.
-*
-*****************************************************************************/
-#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + (u32)(RegOffset))
-
-/****************************************************************************/
-/**
-*
-* This macro writes to the given register.
-*
-* @param BaseAddr is the base address of the device.
-* @param RegOffset is the offset of the register to be written.
-* @param Data is the 32-bit value to write to the register.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
-
-/************************** Function Prototypes ******************************/
-
-void XGpioPs_ResetHw(UINTPTR BaseAddress);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XGPIOPS_HW_H */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1f/b09498575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1f/b09498575243001d18b399c1eb9b3628
deleted file mode 100644
index 2a4fff2..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1f/b09498575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,573 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xreg_cortexa9.h
-*
-* This header file contains definitions for using inline assembler code. It is
-* written specifically for the GNU, ARMCC compiler.
-*
-* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
-* with the positions of the bits within the registers.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm 10/20/09 First release
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 First release
-* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
-* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
-* changed to volatile.
-*
-*
-*
-******************************************************************************/
-
-#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */
-#define XEMACPS_BDRING_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/**************************** Type Definitions *******************************/
-
-/** This is an internal structure used to maintain the DMA list */
-typedef struct {
- UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
- UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */
- UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */
- u32 Length; /**< Total size of ring in bytes */
- u32 RunState; /**< Flag to indicate DMA is started */
- u32 Separation; /**< Number of bytes between the starting address
- of adjacent BDs */
- XEmacPs_Bd *FreeHead;
- /**< First BD in the free group */
- XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
- XEmacPs_Bd *HwHead; /**< First BD in the work group */
- XEmacPs_Bd *HwTail; /**< Last BD in the work group */
- XEmacPs_Bd *PostHead;
- /**< First BD in the post-work group */
- XEmacPs_Bd *BdaRestart;
- /**< BDA to load when channel is started */
-
- volatile u32 HwCnt; /**< Number of BDs in work group */
- u32 PreCnt; /**< Number of BDs in pre-work group */
- u32 FreeCnt; /**< Number of allocatable BDs in the free group */
- u32 PostCnt; /**< Number of BDs in post-work group */
- u32 AllCnt; /**< Total Number of BDs for channel */
-} XEmacPs_BdRing;
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
-* Use this macro at initialization time to determine how many BDs will fit
-* in a BD list within the given memory constraints.
-*
-* The results of this macro can be provided to XEmacPs_BdRingCreate().
-*
-* @param Alignment specifies what byte alignment the BDs must fall on and
-* must be a power of 2 to get an accurate calculation (32, 64, 128,...)
-* @param Bytes is the number of bytes to be used to store BDs.
-*
-* @return Number of BDs that can fit in the given memory area
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
-*
-******************************************************************************/
-#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \
- (u32)((Bytes) / (sizeof(XEmacPs_Bd)))
-
-/*****************************************************************************/
-/**
-* Use this macro at initialization time to determine how many bytes of memory
-* is required to contain a given number of BDs at a given alignment.
-*
-* @param Alignment specifies what byte alignment the BDs must fall on. This
-* parameter must be a power of 2 to get an accurate calculation (32, 64,
-* 128,...)
-* @param NumBd is the number of BDs to calculate memory size requirements for
-*
-* @return The number of bytes of memory required to create a BD list with the
-* given memory constraints.
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
-*
-******************************************************************************/
-#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \
- (u32)(sizeof(XEmacPs_Bd) * (NumBd))
-
-/****************************************************************************/
-/**
-* Return the total number of BDs allocated by this channel with
-* XEmacPs_BdRingCreate().
-*
-* @param RingPtr is the DMA channel to operate on.
-*
-* @return The total number of BDs allocated for this channel.
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
-
-/****************************************************************************/
-/**
-* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
-* processing.
-*
-* @param RingPtr is the DMA channel to operate on.
-*
-* @return The number of BDs currently allocatable.
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt)
-
-/****************************************************************************/
-/**
-* Return the next BD from BdPtr in a list.
-*
-* @param RingPtr is the DMA channel to operate on.
-* @param BdPtr is the BD to operate on.
-*
-* @return The next BD in the list relative to the BdPtr parameter.
-*
-* @note
-* C-style signature:
-* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
-* XEmacPs_Bd *BdPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingNext(RingPtr, BdPtr) \
- (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ? \
- (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) : \
- (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
-
-/****************************************************************************/
-/**
-* Return the previous BD from BdPtr in the list.
-*
-* @param RingPtr is the DMA channel to operate on.
-* @param BdPtr is the BD to operate on
-*
-* @return The previous BD in the list relative to the BdPtr parameter.
-*
-* @note
-* C-style signature:
-* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
-* XEmacPs_Bd *BdPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \
- (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \
- (XEmacPs_Bd*)(RingPtr)->HighBdAddr : \
- (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Scatter gather DMA related functions in xemacps_bdring.c
- */
-LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
- UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
-LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
- u8 Direction);
-LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd ** BdSetPtr);
-LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr);
-LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr);
-LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr);
-u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
- XEmacPs_Bd ** BdSetPtr);
-u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
- XEmacPs_Bd ** BdSetPtr);
-LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
-
-void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* end of protection macros */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1f/e207b7595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1f/e207b7595243001d18b399c1eb9b3628
deleted file mode 100644
index d1c27df..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/1f/e207b7595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,765 +0,0 @@
-/******************************************************************************/
-/**
-* Copyright (c) 2019 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-* @file xil_util.c
-*
-* This file contains xil utility functions
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.4 mmd 04/21/19 First release.
-* 7.2 nava 08/01/20 Updated Xil_WaitForEvent() and Xil_WaitForEvents(()
-* API to use microsecond timeout instead of a free
-* counter.
-* 7.3 kal 06/30/20 Converted Xil_Ceil macro to API.
-* rpo 08/19/20 Added function for read,modify,write
-* kal 09/22/20 Changed the param type from const char to const char*
-* to avoid copying key onto stack
-* td 10/16/20 Added Xil_Strcpy, Xil_Strcat, Xil_SecureMemCpy and
-* Xil_MemCmp functions
-* 7.4 am 11/26/20 Added Xil_StrCpyRange function
-* 7.6 kpt 07/15/21 Added Xil_SecureZeroize function
-*
-*
-*
-*****************************************************************************/
-
-/****************************** Include Files *********************************/
-#include "xil_util.h"
-#include "sleep.h"
-
-/************************** Constant Definitions ****************************/
-#define MAX_NIBBLES 8U
-
-/************************** Function Prototypes *****************************/
-
-/******************************************************************************/
-/**
-* This API ceils the provided float value.
-*
-* @param Value is a float variable which has to ceiled to nearest
-* integer.
-*
-* @return Returns ceiled value.
-*
-*******************************************************************************/
-int Xil_Ceil(float Value)
-{
- int Result = Value;
-
- if (Value > Result) {
- Result = Result + 1;
- }
-
- return Result;
-}
-
-/****************************************************************************/
-/**
- * Converts the char into the equivalent nibble.
- * Ex: 'a' -> 0xa, 'A' -> 0xa, '9'->0x9
- *
- * @param InChar - Input character to be converted to nibble.
- * Valid characters are between 0-9, a-f, A-F
- * @param Num - Memory location where nibble is to be stored
- *
- * @return
- * XST_SUCCESS - Character converted to nibble
- * XST_FAILURE - Invalid input character
- *
- * @note None.
- *
- *****************************************************************************/
-
-u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num)
-{
- u32 Status;
-
- /* Convert the char to nibble */
- if ((InChar >= (u8)'0') && (InChar <= (u8)'9')) {
- *Num = InChar - (u8)'0';
- Status = XST_SUCCESS;
- }
- else if ((InChar >= (u8)'a') && (InChar <= (u8)'f')) {
- *Num = InChar - (u8)'a' + 10U;
- Status = XST_SUCCESS;
- }
- else if ((InChar >= (u8)'A') && (InChar <= (u8)'F')) {
- *Num = InChar - (u8)'A' + 10U;
- Status = XST_SUCCESS;
- }
- else {
- Status = XST_FAILURE;
- }
-
- return Status;
-}
-
-/****************************************************************************/
-/*
- * Converts the string into the equivalent Hex buffer.
- * Ex: "abc123" -> {0xab, 0xc1, 0x23}
- *
- * @param Str - Pointer to string to be converted to Hex.
- * Accepted characters in string are between 0-9, a-f and A-F
- * @param Buf - Pointer to memory location where converted hex values are to
- * be stored.
- * @param Len - Length of input string
- *
- * @return
- * XST_SUCCESS - Input string is converted to hex
- * XST_FAILURE - Invalid character in inpit string
- *
- * @note None.
- *
- *****************************************************************************/
-u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len)
-{
- u32 Status = XST_FAILURE;
- u8 ConvertedLen = 0U, index = 0U;
- u8 Nibble[MAX_NIBBLES] = {0U};
- u8 i;
-
- while (ConvertedLen < Len) {
- for (i = 0U; i < MAX_NIBBLES; i++) {
- Status = Xil_ConvertCharToNibble(Str[ConvertedLen],
- &Nibble[i]);
- ConvertedLen = ConvertedLen +1U;
- if (Status != XST_SUCCESS) {
- /* Error converting char to nibble */
- goto END;
- }
- }
-
- buf[index] = ((Nibble[0] << (u8)28U) | (Nibble[1] << (u8)24U) |
- (Nibble[2] << (u8)20U) | (Nibble[3] << (u8)16U) |
- (Nibble[4] << (u8)12U) | (Nibble[5] << (u8)8U) |
- (Nibble[6] << (u8)4U) | (u32)Nibble[7]);
- index++;
- }
-END:
- return Status;
-}
-
-/****************************************************************************/
-/*
- * Waits for the event
- *
- * @param RegAddr - Address of register to be checked for event(s) occurrence
- * @param EventMask - Mask indicating event(s) to be checked
- * @param Event - Specific event(s) value to be checked
- * @param Timeout - Max number of microseconds to wait for an event(s).
- *
- * @return
- * XST_SUCCESS - On occurrence of the event(s).
- * XST_FAILURE - Event did not occur before counter reaches 0
- *
- * @note None.
- *
- *****************************************************************************/
-u32 Xil_WaitForEvent(u32 RegAddr, u32 EventMask, u32 Event, u32 Timeout)
-{
- u32 EventStatus;
- u32 PollCount = Timeout;
- u32 Status = XST_FAILURE;
-
- while(PollCount > 0) {
- EventStatus = Xil_In32(RegAddr) & EventMask;
- if (EventStatus == Event) {
- Status = XST_SUCCESS;
- break;
- }
- PollCount--;
- usleep(1U);
- }
-
- return Status;
-}
-
-
-/******************************************************************************/
-/**
- * Waits for the events. Returns on occurrence of first event / timeout.
- *
- * @param EventsRegAddr - Address of register to be checked for event(s)
- * occurrence
- * @param EventsMask - Mask indicating event(s) to be checked
- * @param WaitEvents - Specific event(s) to be checked
- * @param Timeout - Max number of microseconds to wait for an event(s).
- * @param Events - Mask of Events occurred returned in memory pointed by
- * this variable
- *
- * @return
- * XST_SUCCESS - On occurrence of the event(s).
- * XST_FAILURE - Event did not occur before counter reaches 0
- *
- ******************************************************************************/
-u32 Xil_WaitForEvents(u32 EventsRegAddr, u32 EventsMask, u32 WaitEvents,
- u32 Timeout, u32* Events)
-{
- u32 EventStatus;
- u32 PollCount = Timeout;
- u32 Status = XST_TIMEOUT;
-
- *Events = 0x00;
- do {
- EventStatus = Xil_In32(EventsRegAddr);
- EventStatus &= EventsMask;
- if(EventStatus & WaitEvents) {
- Status = XST_SUCCESS;
- *Events = EventStatus;
- break;
- }
- PollCount--;
- usleep(1U);
- }
- while(PollCount > 0);
-
- return Status;
-}
-
-/******************************************************************************/
-/**
- * Checks whether the passed character is a valid hex digit
- *
- * @param Ch - Pointer to the input character
- *
- * @return
- * XST_SUCCESS - on valid hex digit
- * XST_FAILURE - on invalid hex digit
- *
- * @note None.
- *
- ******************************************************************************/
-u32 Xil_IsValidHexChar(const char *Ch)
-{
- u32 Status = XST_FAILURE;
-
- if(NULL == Ch) {
- goto END;
- }
- if ((*Ch >= '0' && *Ch <='9')||
- (*Ch >= 'a' && *Ch <='f')||
- (*Ch >= 'A' && *Ch <='F')) {
-
- Status = XST_SUCCESS;
- }
-END:
- return Status;
-}
-
-/******************************************************************************/
-/**
- * Validate the input string contains only hexadecimal characters
- *
- * @param HexStr - Pointer to string to be validated
- *
- * @return
- * XST_SUCCESS - On valid input hex string
- * XST_INVALID_PARAM - On invalid length of the input string
- * XST_FAILURE - On non hexadecimal character in string
- *
- * @note None
- *
- ******************************************************************************/
-u32 Xil_ValidateHexStr(const char *HexStr)
-{
- u32 Idx;
- u32 Len;
- u32 Status = XST_INVALID_PARAM;
-
- if(NULL == HexStr) {
- goto END;
- }
-
- Len = Xil_Strnlen(HexStr, XIL_MAX_HEX_STR_LEN + 1U);
- if (Len > XIL_MAX_HEX_STR_LEN) {
- goto END;
- }
-
- for (Idx = 0U; Idx < Len; Idx++) {
- Status = Xil_IsValidHexChar(&HexStr[Idx]);
- if (Status != XST_SUCCESS) {
- break;
- }
- }
-
-END:
- return Status;
-}
-
-/****************************************************************************/
-/**
- * Converts the string into the equivalent Hex buffer.
- * Ex: "abc123" -> {0xab, 0xc1, 0x23}
- *
- * @param Str is a Input String. Will support the lower and upper case values.
- * Value should be between 0-9, a-f and A-F
- * @param Buf is Output buffer.
- * @param Len of the input string. Should have even values
- *
- * @return
- * - XST_SUCCESS no errors occurred.
- * - XST_FAILURE an error when input parameters are not valid
- * - an error when input buffer has invalid values
- *
- * TDD Test Cases:
- * ---Initialization---
- * Len is odd
- * Len is zero
- * Str is NULL
- * Buf is NULL
- * ---Functionality---
- * Str input with only numbers
- * Str input with All values in A-F
- * Str input with All values in a-f
- * Str input with values in a-f, 0-9, A-F
- * Str input with values in a-z, 0-9, A-Z
- * Boundary Cases
- * Memory Bounds of buffer checking
- * ****************************************************************************/
-u32 Xil_ConvertStringToHexBE(const char *Str, u8 *Buf, u32 Len)
-{
- u32 ConvertedLen;
- u8 LowerNibble = 0U;
- u8 UpperNibble = 0U;
- u32 Status = (u32)XST_FAILURE;
-
- if ((Str == NULL) || (Buf == NULL)) {
- Status = (u32)XST_INVALID_PARAM;
- goto END;
- }
-
- if ((Len == 0U) || ((Len % XIL_SIZE_OF_BYTE_IN_BITS) != 0U)) {
- Status = (u32)XST_INVALID_PARAM;
- goto END;
- }
-
- if(Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) {
- Status = (u32)XST_INVALID_PARAM;
- goto END;
- }
-
- ConvertedLen = 0U;
- while (ConvertedLen < (Len / XIL_SIZE_OF_NIBBLE_IN_BITS)) {
- if (Xil_ConvertCharToNibble(Str[ConvertedLen],&UpperNibble)
- == (u32)XST_SUCCESS) {
- if (Xil_ConvertCharToNibble(Str[ConvertedLen+1],
- &LowerNibble) == (u32)XST_SUCCESS) {
- Buf[ConvertedLen/2] =
- (UpperNibble << XIL_SIZE_OF_NIBBLE_IN_BITS) |
- LowerNibble;
- }
- else {
- Status = (u32)XST_INVALID_PARAM;
- goto END;
- }
- }
- else {
- Status = (u32)XST_INVALID_PARAM;
- goto END;
- }
- ConvertedLen += 2U;
- }
- Status = (u32)XST_SUCCESS;
-END:
- return Status;
-}
-
-/******************************************************************************/
-/**
- * Converts the string into the equivalent Hex buffer.
- * Ex: "abc123" -> {0x23, 0xc1, 0xab}
- *
- * @param Str - Input String to be converted to hex number in little
- * endian format. Valid characters of input strin are between
- * 0-9, a-f and A-F
- * @param Buf - Pointer to memory location where converted hex numbers are to
- * be stored.
- * @param Len - Expected number of output bits
- *
- * @return
- * XST_SUCCESS - Input string is converted to hex number(s)
- * XST_FAILURE - Invalid input character detected in input string
- *
- * @note
- *
- ******************************************************************************/
-u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len)
-{
- u32 ConvertedLen;
- u8 LowerNibble = 0U;
- u8 UpperNibble = 0U;
- u32 StrIndex;
- u32 Status = XST_FAILURE;
-
- if ((NULL == Str) || (NULL == Buf)) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- if ((Len == 0U) || ((Len % XIL_SIZE_OF_BYTE_IN_BITS) != 0U)) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- if(Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- StrIndex = (Len / XIL_SIZE_OF_BYTE_IN_BITS) - 1U;
- ConvertedLen = 0U;
- while (ConvertedLen < (Len / XIL_SIZE_OF_NIBBLE_IN_BITS)) {
- Status = Xil_ConvertCharToNibble(Str[ConvertedLen],
- &UpperNibble);
- if (XST_SUCCESS == Status) {
- Status = Xil_ConvertCharToNibble(Str[ConvertedLen + 1],
- &LowerNibble);
- if (XST_SUCCESS == Status) {
- Buf[StrIndex] =
- (UpperNibble << XIL_SIZE_OF_NIBBLE_IN_BITS) |
- LowerNibble;
- StrIndex = StrIndex - 1U;
- }
- else {
- Status = XST_INVALID_PARAM;
- goto END;
- }
- }
- else {
- Status = XST_INVALID_PARAM;
- goto END;
- }
- ConvertedLen += 2U;
- }
-
- Status = XST_SUCCESS;
-END:
- return Status;
-}
-
-/******************************************************************************/
-/**
- * Returns the length of input string.
- *
- * @param Str - Input string
- * @param MaxLen - Maximum expected length of the input string
- *
- * @return
- * Returns length of the input string if length is less than MaxLen.
- * Returns MaxLen if the length of the input string is >= MaxLen.
- *
- * @note
- *
- ******************************************************************************/
-u32 Xil_Strnlen(const char *Str, u32 MaxLen)
-{
- const char *InStr = Str;
- u32 StrLen = 0U;
-
- if (NULL == Str) {
- goto END;
- }
-
- while(StrLen < MaxLen) {
- if ('\0' == *InStr) {
- break;
- }
- StrLen++;
- InStr++;
- }
-
-END:
- return StrLen;
-}
-
-/*****************************************************************************/
-/**
- * @brief This function will Read, Modify and Write to an address.
- *
- * @param Addr denotes Address
- * @param Mask denotes the bits to be modified
- * @param Value is the value to be written to the address
- *
- * @return None
- *
- *****************************************************************************/
-void Xil_UtilRMW32(u32 Addr, u32 Mask, u32 Value)
-{
- u32 Val;
-
- Val = Xil_In32(Addr);
- Val = (Val & (~Mask)) | (Mask & Value);
- Xil_Out32(Addr, Val);
-}
-
-/*****************************************************************************/
-/**
- * @brief This functions copies source string to destination string. This
- * function is a safe version of strcpy
- *
- * @param DestPtr is pointer to destination string
- * @param SrcPtr is pointer to source string
- * @param Size is the maximum number of bytes of the source string
- * to be copied
- *
- * @return XST_SUCCESS on success and error code on failure
- *
- ******************************************************************************/
-int Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size)
-{
- int Status = XST_FAILURE;
- u32 Count;
-
- if ((SrcPtr == NULL) || (DestPtr == NULL) || (Size == 0U)) {
- goto END;
- }
-
- for (Count = 0U; (SrcPtr[Count] != '\0') && (Count < Size); ++Count) {
- DestPtr[Count] = SrcPtr[Count];
- }
- if (Count == Size) {
- DestPtr[0U] = '\0';
- goto END;
- }
- DestPtr[Count] = '\0';
- Status = XST_SUCCESS;
-
-END:
- return Status;
-}
-
-/****************************************************************************/
-/**
- * @brief Copies specified range from source string to destination string
- *
- * @param Src is a pointer to source string
- * @param Dst is a pointer to destination string
- * @param From is 0 based index from where string copy starts
- * @param To is 0 based index till which string is copied
- * @param MaxSrcLen is the maximum length of source string
- * @param MaxDstLen is the maximum length of destination string
- *
- * @return XST_SUCCESS on success
- * XST_FAILURE on failure
- *
- * @note None
- *
- ****************************************************************************/
-int Xil_StrCpyRange(const u8 *Src, u8 *Dst, u32 From, u32 To, u32 MaxSrcLen,
- u32 MaxDstLen)
-{
- int Status = XST_FAILURE;
- u32 SrcLength;
- u32 Index;
-
- if ((Src == NULL) || (Dst == NULL)) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- if ((To >= MaxSrcLen) || (To < From)) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- if ((To - From + 1U) >= MaxDstLen) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- SrcLength = Xil_Strnlen((const char *)Src, MaxSrcLen);
- if (To >= SrcLength) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- for (Index = From; Index <= To && Src[Index]!= '\0'; Index++) {
- Dst[Index - From] = Src[Index];
- }
-
- Dst[Index - From] = '\0';
- Status = XST_SUCCESS;
-
-END:
- return Status;
-}
-
-/*****************************************************************************/
-/**
- * @brief This function appends string2 to string1. This function is a safe
- * version of strcat
- *
- * @param Str1Ptr is pointer to string1
- * @param Str2Ptr is pointer to string2
- * @param Size is the maximum number of bytes Str1 can hold
- *
- * @return XST_SUCCESS on success and error code on failure
- *
- ******************************************************************************/
-int Xil_Strcat(char* Str1Ptr, const char* Str2Ptr, const u32 Size)
-{
- int Status = XST_FAILURE;
- u32 Count = 0U;
- u32 CountTmp = 0U;
-
- if ((Str1Ptr == NULL) || (Str2Ptr == NULL) || (Size == 0U)) {
- goto END;
- }
-
- while ((Count < Size) && (Str1Ptr[Count] != '\0')) {
- Count++;
- }
-
- while ((Str2Ptr[CountTmp] != '\0') && (Count < Size)) {
- Str1Ptr[Count++] = Str2Ptr[CountTmp++];
- }
- if (Count == Size) {
- Str1Ptr[0U] = '\0';
- goto END;
- }
- Str1Ptr[Count] = '\0';
- Status = XST_SUCCESS;
-
-END:
- return Status;
-}
-
-/*****************************************************************************/
-/**
- * @brief This function copies Len bytes from source memory to destination
- * memory. If Len is greater than DestPtrLen, then DestPtr is also
- * filled with 0s till DestPtrLen bytes and is considered as a failure.
- * This function is a secure implementation of memcpy
- *
- * @param DestPtr is pointer to destination address
- * @param DestPtrLen is the memory alloted to the destination buffer
- * @param SrcPtr is pointer to source address
- * @param Len is number of bytes to be copied
- *
- * @return XST_SUCCESS on success and error code on failure
- *
- ******************************************************************************/
-int Xil_SecureMemCpy(void * DestPtr, u32 DestPtrLen, const void * SrcPtr, u32 Len)
-{
- int Status = XST_FAILURE;
- u8 *Dest = (u8 *)DestPtr;
- const u8 *Src = (const u8 *)SrcPtr;
-
- if ((DestPtr == NULL) || (SrcPtr == NULL)) {
- goto END;
- }
-
- if (Len > DestPtrLen) {
- while (DestPtrLen != 0U) {
- *Dest = 0U;
- Dest++;
- DestPtrLen--;
- }
- goto END;
- }
-
- /* Loop and copy. */
- while (Len != 0U) {
- *Dest = *Src;
- Dest++;
- Src++;
- Len--;
- }
- Status = XST_SUCCESS;
-
-END:
- return Status;
-}
-
-/*****************************************************************************/
-/**
- * @brief This function compares Len bytes from memory1 and memory2. This
- * function is a secure implementation of memcmp
- *
- * @param Buf1Ptr is pointer to memory1
- * @param Buf2Ptr is pointer to memory2
- * @param Len is number of byets to be compared
- *
- * @return 0 if contents of both the memory regions are same,
- * -1 if first non-matching character has lower value in Buf1Ptr
- * 1 if first non-matching character is greater value in Buf1Ptr
- *
- ******************************************************************************/
-int Xil_MemCmp(const void * Buf1Ptr, const void * Buf2Ptr, u32 Len)
-{
- volatile int RetVal = 1;
- const u8 *Buf1 = Buf1Ptr;
- const u8 *Buf2 = Buf2Ptr;
- u32 Size = Len;
-
- /* Assert validates the input arguments */
- if ((Buf1 == NULL) || (Buf2 == NULL) || (Len == 0x0U)) {
- goto END;
- }
-
- /* Loop and compare */
- while (Size != 0U) {
- if (*Buf1 > *Buf2) {
- RetVal = 1;
- goto END;
- } else if (*Buf1 < *Buf2) {
- RetVal = -1;
- goto END;
- } else {
- Buf1++;
- Buf2++;
- Size--;
- }
- }
-
- /* Make sure size is zero to know the whole of data is compared */
- if (Size == 0U) {
- RetVal = 0;
- }
-
-END:
- return RetVal;
-}
-
-/*****************************************************************************/
-/**
- * @brief This function is used to zeroize the memory
- *
- * @param DataPtr Pointer to the memory which need to be zeroized.
- * @param Length Length of the data in bytes.
- *
- * @return
- * - XST_SUCCESS: If Zeroization is successful.
- * - XST_FAILURE: If Zeroization is not successful.
- ********************************************************************************/
-int Xil_SecureZeroize(u8 *DataPtr, const u32 Length)
-{
- u32 Index;
- int Status = XST_FAILURE;
-
- /* Clear the data */
- (void)memset(DataPtr, 0, Length);
-
- /* Read it back to verify */
- for (Index = 0U; Index < Length; Index++) {
- if (DataPtr[Index] != 0x00U) {
- goto END;
- }
- }
- if (Index == Length) {
- Status = XST_SUCCESS;
- }
-
-END:
- return Status;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2/10df83585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2/10df83585243001d18b399c1eb9b3628
deleted file mode 100644
index cb26e19..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2/10df83585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,175 +0,0 @@
-/*******************************************************************************
-* Copyright (c) 2018 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-*******************************************************************************/
-
-
-#ifndef __XPMC_XIOU_SECURE_SLCR_H__
-#define __XPMC_XIOU_SECURE_SLCR_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *@cond nocomments
- */
-
-/**
- * XpmcXiouSecureSlcr Base Address
- */
-#define XPMC_XIOU_SECURE_SLCR_BASEADDR 0xF1070000UL
-
-/**
- * Register: XpmcXiouSecureSlcrAxiWprtcnSd0
- */
-#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD0 ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000000UL )
-#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD0_RSTVAL 0x00000000UL
-
-#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD0_AWPROT_SHIFT 0UL
-#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD0_AWPROT_WIDTH 3UL
-#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD0_AWPROT_MASK 0x00000007UL
-#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD0_AWPROT_DEFVAL 0x0UL
-
-/**
- * Register: XpmcXiouSecureSlcrAxiRprtcnSd0
- */
-#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD0 ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000004UL )
-#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD0_RSTVAL 0x00000000UL
-
-#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD0_ARPROT_SHIFT 0UL
-#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD0_ARPROT_WIDTH 3UL
-#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD0_ARPROT_MASK 0x00000007UL
-#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD0_ARPROT_DEFVAL 0x0UL
-
-/**
- * Register: XpmcXiouSecureSlcrAxiWprtcnSd1
- */
-#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD1 ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000010UL )
-#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD1_RSTVAL 0x00000000UL
-
-#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD1_AWPROT_SHIFT 0UL
-#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD1_AWPROT_WIDTH 3UL
-#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD1_AWPROT_MASK 0x00000007UL
-#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD1_AWPROT_DEFVAL 0x0UL
-
-/**
- * Register: XpmcXiouSecureSlcrAxiRprtcnSd1
- */
-#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD1 ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000014UL )
-#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD1_RSTVAL 0x00000000UL
-
-#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD1_ARPROT_SHIFT 0UL
-#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD1_ARPROT_WIDTH 3UL
-#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD1_ARPROT_MASK 0x00000007UL
-#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD1_ARPROT_DEFVAL 0x0UL
-
-/**
- * Register: XpmcXiouSecureSlcrAxiWprtcnQspi
- */
-#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_QSPI ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000020UL )
-#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_QSPI_RSTVAL 0x00000000UL
-
-#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_QSPI_XQSPIPSAXI_AWPROT_SHIFT 0UL
-#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_QSPI_XQSPIPSAXI_AWPROT_WIDTH 3UL
-#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_QSPI_XQSPIPSAXI_AWPROT_MASK 0x00000007UL
-#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_QSPI_XQSPIPSAXI_AWPROT_DEFVAL 0x0UL
-
-/**
- * Register: XpmcXiouSecureSlcrAxiWprtcnOspi
- */
-#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_OSPI ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000030UL )
-#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_OSPI_RSTVAL 0x00000000UL
-
-#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_OSPI_AWPROT_SHIFT 0UL
-#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_OSPI_AWPROT_WIDTH 3UL
-#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_OSPI_AWPROT_MASK 0x00000007UL
-#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_OSPI_AWPROT_DEFVAL 0x0UL
-
-/**
- * Register: XpmcXiouSecureSlcrCtrl
- */
-#define XPMC_XIOU_SECURE_SLCR_CTRL ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000040UL )
-#define XPMC_XIOU_SECURE_SLCR_CTRL_RSTVAL 0x00000000UL
-
-#define XPMC_XIOU_SECURE_SLCR_CTRL_SLVERR_EN_SHIFT 0UL
-#define XPMC_XIOU_SECURE_SLCR_CTRL_SLVERR_EN_WIDTH 1UL
-#define XPMC_XIOU_SECURE_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL
-#define XPMC_XIOU_SECURE_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL
-
-/**
- * Register: XpmcXiouSecureSlcrIsr
- */
-#define XPMC_XIOU_SECURE_SLCR_ISR ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000044UL )
-#define XPMC_XIOU_SECURE_SLCR_ISR_RSTVAL 0x00000000UL
-
-#define XPMC_XIOU_SECURE_SLCR_ISR_ADDR_DECODE_ERR_SHIFT 0UL
-#define XPMC_XIOU_SECURE_SLCR_ISR_ADDR_DECODE_ERR_WIDTH 1UL
-#define XPMC_XIOU_SECURE_SLCR_ISR_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XPMC_XIOU_SECURE_SLCR_ISR_ADDR_DECODE_ERR_DEFVAL 0x0UL
-
-/**
- * Register: XpmcXiouSecureSlcrImr
- */
-#define XPMC_XIOU_SECURE_SLCR_IMR ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000048UL )
-#define XPMC_XIOU_SECURE_SLCR_IMR_RSTVAL 0x00000001UL
-
-#define XPMC_XIOU_SECURE_SLCR_IMR_ADDR_DECODE_ERR_SHIFT 0UL
-#define XPMC_XIOU_SECURE_SLCR_IMR_ADDR_DECODE_ERR_WIDTH 1UL
-#define XPMC_XIOU_SECURE_SLCR_IMR_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XPMC_XIOU_SECURE_SLCR_IMR_ADDR_DECODE_ERR_DEFVAL 0x1UL
-
-/**
- * Register: XpmcXiouSecureSlcrIer
- */
-#define XPMC_XIOU_SECURE_SLCR_IER ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x0000004CUL )
-#define XPMC_XIOU_SECURE_SLCR_IER_RSTVAL 0x00000000UL
-
-#define XPMC_XIOU_SECURE_SLCR_IER_ADDR_DECODE_ERR_SHIFT 0UL
-#define XPMC_XIOU_SECURE_SLCR_IER_ADDR_DECODE_ERR_WIDTH 1UL
-#define XPMC_XIOU_SECURE_SLCR_IER_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XPMC_XIOU_SECURE_SLCR_IER_ADDR_DECODE_ERR_DEFVAL 0x0UL
-
-/**
- * Register: XpmcXiouSecureSlcrIdr
- */
-#define XPMC_XIOU_SECURE_SLCR_IDR ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000050UL )
-#define XPMC_XIOU_SECURE_SLCR_IDR_RSTVAL 0x00000000UL
-
-#define XPMC_XIOU_SECURE_SLCR_IDR_ADDR_DECODE_ERR_SHIFT 0UL
-#define XPMC_XIOU_SECURE_SLCR_IDR_ADDR_DECODE_ERR_WIDTH 1UL
-#define XPMC_XIOU_SECURE_SLCR_IDR_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XPMC_XIOU_SECURE_SLCR_IDR_ADDR_DECODE_ERR_DEFVAL 0x0UL
-
-/**
- * Register: XpmcXiouSecureSlcrItr
- */
-#define XPMC_XIOU_SECURE_SLCR_ITR ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000054UL )
-#define XPMC_XIOU_SECURE_SLCR_ITR_RSTVAL 0x00000000UL
-
-#define XPMC_XIOU_SECURE_SLCR_ITR_ADDR_DECODE_ERR_SHIFT 0UL
-#define XPMC_XIOU_SECURE_SLCR_ITR_ADDR_DECODE_ERR_WIDTH 1UL
-#define XPMC_XIOU_SECURE_SLCR_ITR_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XPMC_XIOU_SECURE_SLCR_ITR_ADDR_DECODE_ERR_DEFVAL 0x0UL
-
-/**
- * Register: XpmcXiouSecureSlcrTzprot
- */
-#define XPMC_XIOU_SECURE_SLCR_TZPROT ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x0000006CUL )
-#define XPMC_XIOU_SECURE_SLCR_TZPROT_RSTVAL 0x00000000UL
-
-#define XPMC_XIOU_SECURE_SLCR_TZPROT_ACT_SHIFT 0UL
-#define XPMC_XIOU_SECURE_SLCR_TZPROT_ACT_WIDTH 1UL
-#define XPMC_XIOU_SECURE_SLCR_TZPROT_ACT_MASK 0x00000001UL
-#define XPMC_XIOU_SECURE_SLCR_TZPROT_ACT_DEFVAL 0x0UL
-
-/**
- *@endcond
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XPMC_XIOU_SECURE_SLCR_H__ */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2/10f623565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2/10f623565243001d18b399c1eb9b3628
deleted file mode 100644
index 3438d96..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2/10f623565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1 +0,0 @@
-collect (PROJECT_LIB_HEADERS xparameters_ps.h)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2/4076b4565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2/4076b4565243001d18b399c1eb9b3628
deleted file mode 100644
index 369a4a1..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2/4076b4565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,435 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_misc_reset.c
-*
-* This file contains the implementation of the reset sequence for various
-* zynq ps devices like DDR,OCM,Slcr,Ethernet,Usb.. controllers. The reset
-* sequence provided to the interfaces is based on the provision in
-* slcr reset functional block.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00b kpc 03/07/13 First release
-* 5.4 pkp 16/11/15 Change the description for XOcm_Remap function
-*
-*
-******************************************************************************/
-
-
-/***************************** Include Files *********************************/
-#include "xil_misc_psreset_api.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for ddr reset.
-*
-* @return N/A.
-*
-******************************************************************************/
-void XDdr_ResetHw(void)
-{
- u32 RegVal;
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert and deassert the ddr softreset bit */
- RegVal = Xil_In32(XDDRC_CTRL_BASEADDR);
- RegVal &= (u32)(~XDDRPS_CTRL_RESET_MASK);
- Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
- RegVal |= XDDRPS_CTRL_RESET_MASK;
- Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
-
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for remapping the ocm memory region
-* to postbootrom state.
-*
-* @return N/A.
-*
-******************************************************************************/
-void XOcm_Remap(void)
-{
- u32 RegVal;
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Map the ocm region to postbootrom state */
- RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR);
- RegVal = (RegVal & (u32)(~XSLCR_OCM_CFG_HIADDR_MASK)) | (u32)XSLCR_OCM_CFG_RESETVAL;
- Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for SMC reset sequence
-*
-* @param BaseAddress of the interface
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSmc_ResetHw(u32 BaseAddress)
-{
- u32 RegVal;
-
- /* Clear the interuupts */
- RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET);
- RegVal |= XSMC_MEMC_CLR_CONFIG_MASK;
- Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal);
- /* Clear the idle counter registers */
- Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0U);
- Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0U);
- /* Update the ecc registers with reset values */
- Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET,
- XSMC_ECC_MEMCFG1_RESET_VAL);
- Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD1_OFFSET,
- XSMC_ECC_MEMCMD1_RESET_VAL);
- Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD2_OFFSET,
- XSMC_ECC_MEMCMD2_RESET_VAL);
-
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for updating the slcr mio registers
-* with reset values
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_MioWriteResetValues(void)
-{
- u32 i;
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Update all the MIO registers with reset values */
- for (i=0U; i<=1U;i++)
- {
- Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
- XSLCR_MIO_PIN_00_RESET_VAL);
- }
- for (; i<=8U;i++)
- {
- Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
- XSLCR_MIO_PIN_02_RESET_VAL);
- }
- for (; i<=53U ;i++)
- {
- Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
- XSLCR_MIO_PIN_00_RESET_VAL);
- }
-
-
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for updating the slcr pll registers
-* with reset values
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_PllWriteResetValues(void)
-{
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
-
- /* update the pll control registers with reset values */
- Xil_Out32(XSLCR_IO_PLL_CTRL_ADDR, XSLCR_IO_PLL_CTRL_RESET_VAL);
- Xil_Out32(XSLCR_ARM_PLL_CTRL_ADDR, XSLCR_ARM_PLL_CTRL_RESET_VAL);
- Xil_Out32(XSLCR_DDR_PLL_CTRL_ADDR, XSLCR_DDR_PLL_CTRL_RESET_VAL);
- /* update the pll config registers with reset values */
- Xil_Out32(XSLCR_IO_PLL_CFG_ADDR, XSLCR_IO_PLL_CFG_RESET_VAL);
- Xil_Out32(XSLCR_ARM_PLL_CFG_ADDR, XSLCR_ARM_PLL_CFG_RESET_VAL);
- Xil_Out32(XSLCR_DDR_PLL_CFG_ADDR, XSLCR_DDR_PLL_CFG_RESET_VAL);
- /* update the clock control registers with reset values */
- Xil_Out32(XSLCR_ARM_CLK_CTRL_ADDR, XSLCR_ARM_CLK_CTRL_RESET_VAL);
- Xil_Out32(XSLCR_DDR_CLK_CTRL_ADDR, XSLCR_DDR_CLK_CTRL_RESET_VAL);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for disabling the level shifters
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_DisableLevelShifters(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Disable the level shifters */
- RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_LVL_SHFTR_EN_MASK);
- Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal);
-
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for OCM software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_OcmReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
- RegVal |= XSLCR_OCM_RST_CTRL_VAL;
- Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_OCM_RST_CTRL_VAL);
- Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for Ethernet software reset from
-* the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_EmacPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
- RegVal |= XSLCR_GEM_RST_CTRL_VAL;
- Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
- RegVal &= (u32)(~XSLCR_GEM_RST_CTRL_VAL);
- Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for USB software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_UsbPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
- RegVal |= XSLCR_USB_RST_CTRL_VAL;
- Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_USB_RST_CTRL_VAL);
- Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for QSPI software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_QspiPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
- RegVal |= XSLCR_QSPI_RST_CTRL_VAL;
- Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_QSPI_RST_CTRL_VAL);
- Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for SPI software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_SpiPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
- RegVal |= XSLCR_SPI_RST_CTRL_VAL;
- Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_SPI_RST_CTRL_VAL);
- Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for i2c software reset from the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_I2cPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
- RegVal |= XSLCR_I2C_RST_CTRL_VAL;
- Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_I2C_RST_CTRL_VAL);
- Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for UART software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_UartPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
- RegVal |= XSLCR_UART_RST_CTRL_VAL;
- Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_UART_RST_CTRL_VAL);
- Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for CAN software reset from slcr
-* registers
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_CanPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
- RegVal |= XSLCR_CAN_RST_CTRL_VAL;
- Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_CAN_RST_CTRL_VAL);
- Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for SMC software reset from the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_SmcPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
- RegVal |= XSLCR_SMC_RST_CTRL_VAL;
- Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_SMC_RST_CTRL_VAL);
- Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for DMA controller software reset
-* from the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_DmaPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
- RegVal |= XSLCR_DMAC_RST_CTRL_VAL;
- Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_DMAC_RST_CTRL_VAL);
- Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for Gpio AMBA software reset from
-* the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_GpioPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
- RegVal |= XSLCR_GPIO_RST_CTRL_VAL;
- Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_GPIO_RST_CTRL_VAL);
- Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2/408eb6555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2/408eb6555243001d18b399c1eb9b3628
deleted file mode 100644
index 315387a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2/408eb6555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,105 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/*
- * The "__write" function should output "size" number of bytes from
- * "buffer" in some application-specific way. It should return the
- * number of characters written, or _LLIO_ERROR on failure.
- *
- * If "buffer" is zero then __write should perform flushing of
- * internal buffers, if any. In this case "handle" can be -1 to
- * indicate that all handles should be flushed.
- *
- * The template implementation below assumes that the application
- * provides the function "MyLowLevelPutchar". It should return the
- * character written, or -1 on failure.
- *
- */
-
-#include
-#include "xil_types.h"
-
-
-#if 0
-/*
- * If the __write implementation uses internal buffering, uncomment
- * the following line to ensure that we are called with "buffer" as 0
- * (i.e. flush) when the application terminates.
- */
-
-size_t __write(sint32 handle, const u8 * buffer, size_t size)
-{
- u32 volatile *uart_base = (u32 *)0xE0001000U;
- s32 i;
-
- for (i =0; i < size;i++) {
- /* wait if TNFUL */
- while (*(uart_base + 11U) & (1U << 14U)) ;
- *(uart_base + 12U) = buffer[i];
- }
- return 0;
-}
-
-#endif
-
-#include "xparameters.h"
-#include "xil_printf.h"
-
-#ifdef __cplusplus
-extern "C" {
- sint32 _write (sint32 fd, char8* buf, sint32 nbytes);
-}
-#endif
-
-/*
- * write -- write bytes to the serial port. Ignore fd, since
- * stdout and stderr are the same. Since we have no filesystem,
- * open will only return an error.
- */
-sint32
-write (sint32 fd, char8* buf, sint32 nbytes)
-
-{
-#ifdef STDOUT_BASEADDRESS
- s32 i;
-
- (void)fd;
- for (i = 0; i < nbytes; i++) {
- if (*(buf + i) == '\n') {
- outbyte ('\r');
- }
- outbyte (*(buf + i));
- }
- return (nbytes);
-#else
- (void)fd;
- (void)buf;
- (void)nbytes;
- return 0;
-#endif
-}
-
-size_t
-__write (sint32 fd, const u8* buf, size_t nbytes)
-{
-#ifdef STDOUT_BASEADDRESS
- s32 i;
-
- (void)fd;
- for (i = 0; i < nbytes; i++) {
- if (*(buf + i) == '\n') {
- outbyte ('\r');
- }
- outbyte (*(buf + i));
- }
- return (nbytes);
-#else
- (void)fd;
- (void)buf;
- (void)nbytes;
- return 0;
-#endif
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2/c02957585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2/c02957585243001d18b399c1eb9b3628
deleted file mode 100644
index 74feb77..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2/c02957585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,314 +0,0 @@
-;/******************************************************************************
-;* Copyright (c) 2019 - 2021 Xilinx, Inc. All rights reserved.
-;* SPDX-License-Identifier: MIT
-;******************************************************************************/
-;/*****************************************************************************/
-;/**
-;* @file asm_vectors.S
-;*
-;* This file contains the initial vector table for the Cortex A53 processor
-;*
-;*
-;* MODIFICATION HISTORY:
-;*
-;* Ver Who Date Changes
-;* ----- ------- -------- ---------------------------------------------------
-;* 7.0 cjp 02/26/19 First release
-;*
-;*
-;* @note
-;*
-;* None.
-;*
-;******************************************************************************/
-
-#include "bspconfig.h"
-
- EXPORT _vector_table
- EXPORT FPUStatus
-
- IMPORT _boot
- IMPORT FIQInterrupt
- IMPORT IRQInterrupt
- IMPORT SErrorInterrupt
- IMPORT SynchronousInterrupt
-
-;
-; FPUContextSize is the size of the array where floating point registers are
-; stored when required. The default size corresponds to the case when there is
-; no nested interrupt. If there are nested interrupts in application which are
-; using floating point operation, the size of FPUContextSize need to be
-; increased as per requirement
-;
-FPUContextSize EQU 528
-
- MACRO
- saveregister
- stp X0, X1, [sp,#-0x10]!
- stp X2, X3, [sp,#-0x10]!
- stp X4, X5, [sp,#-0x10]!
- stp X6, X7, [sp,#-0x10]!
- stp X8, X9, [sp,#-0x10]!
- stp X10, X11, [sp,#-0x10]!
- stp X12, X13, [sp,#-0x10]!
- stp X14, X15, [sp,#-0x10]!
- stp X16, X17, [sp,#-0x10]!
- stp X18, X19, [sp,#-0x10]!
- stp X29, X30, [sp,#-0x10]!
- MEND
-
- MACRO
- restoreregister
- ldp X29, X30, [sp], #0x10
- ldp X18, X19, [sp], #0x10
- ldp X16, X17, [sp], #0x10
- ldp X14, X15, [sp], #0x10
- ldp X12, X13, [sp], #0x10
- ldp X10, X11, [sp], #0x10
- ldp X8, X9, [sp], #0x10
- ldp X6, X7, [sp], #0x10
- ldp X4, X5, [sp], #0x10
- ldp X2, X3, [sp], #0x10
- ldp X0, X1, [sp], #0x10
- MEND
-
- MACRO
- savefloatregister
- ldr x1, =FPUContextBase ; Load the floating point context array address from FPUContextBase
- ldr x0, [x1]
- stp q0, q1, [x0], #0x20 ; Save all the floating point register to the array
- stp q2, q3, [x0], #0x20
- stp q4, q5, [x0], #0x20
- stp q6, q7, [x0], #0x20
- stp q8, q9, [x0], #0x20
- stp q10, q11, [x0], #0x20
- stp q12, q13, [x0], #0x20
- stp q14, q15, [x0], #0x20
- stp q16, q17, [x0], #0x20
- stp q18, q19, [x0], #0x20
- stp q20, q21, [x0], #0x20
- stp q22, q23, [x0], #0x20
- stp q24, q25, [x0], #0x20
- stp q26, q27, [x0], #0x20
- stp q28, q29, [x0], #0x20
- stp q30, q31, [x0], #0x20
- mrs x2, FPCR
- mrs x3, FPSR
- stp x2, x3, [x0], #0x10
- str x0, [x1] ; Save current address of floating point context array to FPUContextBase
- MEND
-
- MACRO
- restorefloatregister
- ldr x1, =FPUContextBase ; Restore the address of floating point context array from FPUContextBase
- ldr x0, [x1]
- ldp x2, x3, [x0,#-0x10]! ; Restore all the floating point register from the array
- msr FPCR, x2
- msr FPSR, x3
- ldp q30, q31, [x0,#-0x20]!
- ldp q28, q29, [x0,#-0x20]!
- ldp q26, q27, [x0,#-0x20]!
- ldp q24, q25, [x0,#-0x20]!
- ldp q22, q23, [x0,#-0x20]!
- ldp q20, q21, [x0,#-0x20]!
- ldp q18, q19, [x0,#-0x20]!
- ldp q16, q17, [x0,#-0x20]!
- ldp q14, q15, [x0,#-0x20]!
- ldp q12, q13, [x0,#-0x20]!
- ldp q10, q11, [x0,#-0x20]!
- ldp q8, q9, [x0,#-0x20]!
- ldp q6, q7, [x0,#-0x20]!
- ldp q4, q5, [x0,#-0x20]!
- ldp q2, q3, [x0,#-0x20]!
- ldp q0, q1, [x0,#-0x20]!
- str x0, [x1] ; Save current address of floating point context array to FPUContextBase
- MEND
-
- AREA |.vectors|, CODE
- REQUIRE8 {TRUE}
- PRESERVE8 {TRUE}
- ENTRY ; Define this as an entry point
-
-_vector_table
-
-;
-; If application is built for XEN GUEST as EL1 Non-secure following image
-; header is required by XEN.
-;
-#if (HYP_GUEST == 1)
- ldr x16, =_boot ; Valid Image header
- br x16 ; HW reset vector
- DCD 0 ; Text offset
- DCD 0 ; Image size
- DCD 8 ; Flags
- DCD 0 ; RES0
- DCD 0
- DCD 0
- DCD 0x644d5241 ; Magic
- DCD 0 ; RES0
-#endif
-
- B _boot
- ALIGN 512
- B SynchronousInterruptHandler
- ALIGN 128
- B IRQInterruptHandler
- ALIGN 128
- B FIQInterruptHandler
- ALIGN 128
- B SErrorInterruptHandler
-
-SynchronousInterruptHandler
- saveregister
-
-; Check if the Synchronous abort is occurred due to floating point access
-#if (EL3 == 1)
- mrs x0, ESR_EL3
-#else
- mrs x0, ESR_EL1
-#endif
- and x0, x0, #(0x3F << 26)
- mov x1, #(0x7 << 26)
- cmp x0, x1
-
-;
-; If exception is not due to floating point access go to synchronous
-; handler
-;
- bne synchronoushandler
-
-;
-; If exception occurred due to floating point access, Enable the floating point
-; access i.e. do not trap floating point instruction
-;
-#if (EL3 == 1)
- mrs x1, CPTR_EL3
- mov x2, #(0x1<<10)
- bic x1, x1, x2
- msr CPTR_EL3, x1
-#else
- mrs x1, CPACR_EL1
- orr x1, x1, #(0x1<<20)
- msr CPACR_EL1, x1
-#endif
- isb
-
-;
-; If the floating point access was previously enabled, store FPU context
-; registers(storefloat)
-;
- ldr x0, =FPUStatus
- ldrb w1, [x0]
- cbnz w1, storefloat
-
-;
-; If the floating point access was not enabled previously, save the status of
-; floating point accessibility i.e. enabled and store floating point context
-; array address(FPUContext) to FPUContextBase
-;
- mov w1, #0x1
- strb w1, [x0]
- ldr x0, =FPUContext
- ldr x1, =FPUContextBase
- str x0, [x1]
- b restorecontext
-
-storefloat
- savefloatregister
- b restorecontext
-
-synchronoushandler
- bl SynchronousInterrupt
-
-restorecontext
- restoreregister
- eret
-
-IRQInterruptHandler
- saveregister
-
-; Save the status of SPSR, ELR and CPTR to stack
-#if (EL3 == 1)
- mrs x0, CPTR_EL3
- mrs x1, ELR_EL3
- mrs x2, SPSR_EL3
-#else
- mrs x0, CPACR_EL1
- mrs x1, ELR_EL1
- mrs x2, SPSR_EL1
-#endif
- stp x0, x1, [sp,#-0x10]!
- str x2, [sp,#-0x10]!
-
-
-; Trap floating point access
-#if (EL3 == 1)
- mrs x1, CPTR_EL3
- orr x1, x1, #(0x1<<10)
- msr CPTR_EL3, x1
-#else
- mrs x1, CPACR_EL1
- mov x2, #(0x1<<20)
- bic x1, x1, x2
- msr CPACR_EL1, x1
-#endif
- isb
- bl IRQInterrupt
-;
-; If floating point access is enabled during interrupt handling, restore
-; floating point registers
-;
-#if (EL3 == 1)
- mrs x0, CPTR_EL3
- ands x0, x0, #(0x1<<10)
- bne RestorePrevState
-#else
- mrs x0, CPACR_EL1
- ands x0, x0, #(0x1<<20)
- beq RestorePrevState
-#endif
- restorefloatregister
-
-
-; Restore the status of SPSR, ELR and CPTR from stack
-RestorePrevState
- ldr x2, [sp], #0x10
- ldp x0, x1, [sp],#0x10
-#if (EL3 == 1)
- msr CPTR_EL3, x0
- msr ELR_EL3, x1
- msr SPSR_EL3, x2
-#else
- msr CPACR_EL1, x0
- msr ELR_EL1, x1
- msr SPSR_EL1, x2
-#endif
- restoreregister
- eret
-
-FIQInterruptHandler
- saveregister
- bl FIQInterrupt
- restoreregister
- eret
-
-SErrorInterruptHandler
- saveregister
- bl SErrorInterrupt
- restoreregister
- eret
-
- ALIGN 8
-
-; Array to store floating point registers
-FPUContext
- SPACE FPUContextSize
-
-; Stores address for floating point context array
-FPUContextBase
- SPACE 8
-
-FPUStatus
- SPACE 4
-
- END
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2/d0c2bb595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2/d0c2bb595243001d18b399c1eb9b3628
deleted file mode 100644
index ea3a08c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2/d0c2bb595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,133 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xl2cc_counter.c
-*
-* This file contains APIs for configuring and controlling the event counters
-* in PL310 L2 cache controller. For more information about the event counters,
-* see xl2cc_counter.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
-* inside the APIs
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include
-#include "xparameters_ps.h"
-#include "xl2cc_counter.h"
-#include "xl2cc.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void XL2cc_EventCtrReset(void);
-
-/******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @brief This function initializes the event counters in L2 Cache controller
-* with a set of event codes specified by the user.
-*
-* @param Event0: Event code for counter 0.
-* @param Event1: Event code for counter 1.
-*
-* @return None.
-*
-* @note The definitions for event codes XL2CC_* can be found in
-* xl2cc_counter.h.
-*
-*****************************************************************************/
-void XL2cc_EventCtrInit(s32 Event0, s32 Event1)
-{
-
- /* Write event code into cnt1 cfg reg */
- *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_CTRL_OFFSET)) = (((u32)Event1) << 2);
-
- /* Write event code into cnt0 cfg reg */
- *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_CTRL_OFFSET)) = (((u32)Event0) << 2);
-
- /* Reset counters */
- XL2cc_EventCtrReset();
-}
-
-
-/****************************************************************************/
-/**
-*
-* @brief This function starts the event counters in L2 Cache controller.
-*
-* @return None.
-*
-*****************************************************************************/
-void XL2cc_EventCtrStart(void)
-{
- u32 *LocalPtr;
- LocalPtr = (u32 *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET);
- XL2cc_EventCtrReset();
-
- /* Enable counter */
- /* *((volatile u32*)((void *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET))) = 1 */
- *LocalPtr = (u32)1;
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function disables the event counters in L2 Cache controller,
-* saves the counter values and resets the counters.
-*
-* @param EveCtr0: Output parameter which is used to return the value
-* in event counter 0.
-* @param EveCtr1: Output parameter which is used to return the value
-* in event counter 1.
-*
-* @return None.
-*
-*****************************************************************************/
-void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1)
-{
- /* Disable counter */
- *((volatile u32*) (XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0U;
-
- /* Save counter values */
- *EveCtr1 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_VAL_OFFSET));
- *EveCtr0 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_VAL_OFFSET));
-
- XL2cc_EventCtrReset();
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function resets the event counters in L2 Cache controller.
-*
-* @return None.
-*
-*****************************************************************************/
-void XL2cc_EventCtrReset(void)
-{
- *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0x6U;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2/f15aa4545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2/f15aa4545243001d18b399c1eb9b3628
deleted file mode 100644
index 1a0f044..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2/f15aa4545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,242 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xemacps_intr.c
-* @addtogroup emacps_v3_15
-* @{
-*
-* Functions in this file implement general purpose interrupt processing related
-* functionality. See xemacps.h for a detailed description of the driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 First release
-* 1.03a asa 01/24/13 Fix for CR #692702 which updates error handling for
-* Rx errors. Under heavy Rx traffic, there will be a large
-* number of errors related to receive buffer not available.
-* Because of a HW bug (SI #692601), under such heavy errors,
-* the Rx data path can become unresponsive. To reduce the
-* probabilities for hitting this HW bug, the SW writes to
-* bit 18 to flush a packet from Rx DPRAM immediately. The
-* changes for it are done in the function
-* XEmacPs_IntrHandler.
-* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification
-* and 64-bit changes.
-* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 hk 07/27/15 Do not call error handler with '0' error code when
-* there is no error. CR# 869403
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xemacps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
- * Install an asynchronous handler function for the given HandlerType:
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param HandlerType indicates what interrupt handler type is.
- * XEMACPS_HANDLER_DMASEND, XEMACPS_HANDLER_DMARECV and
- * XEMACPS_HANDLER_ERROR.
- * @param FuncPointer is the pointer to the callback function
- * @param CallBackRef is the upper layer callback reference passed back when
- * when the callback function is invoked.
- *
- * @return
- *
- * None.
- *
- * @note
- * There is no assert on the CallBackRef since the driver doesn't know what
- * it is.
- *
- *****************************************************************************/
-LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
- void *FuncPointer, void *CallBackRef)
-{
- LONG Status;
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(FuncPointer != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- switch (HandlerType) {
- case XEMACPS_HANDLER_DMASEND:
- Status = (LONG)(XST_SUCCESS);
- InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
- InstancePtr->SendRef = CallBackRef;
- break;
- case XEMACPS_HANDLER_DMARECV:
- Status = (LONG)(XST_SUCCESS);
- InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
- InstancePtr->RecvRef = CallBackRef;
- break;
- case XEMACPS_HANDLER_ERROR:
- Status = (LONG)(XST_SUCCESS);
- InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
- InstancePtr->ErrorRef = CallBackRef;
- break;
- default:
- Status = (LONG)(XST_INVALID_PARAM);
- break;
- }
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* Master interrupt handler for EMAC driver. This routine will query the
-* status of the device, bump statistics, and invoke user callbacks.
-*
-* This routine must be connected to an interrupt controller using OS/BSP
-* specific methods.
-*
-* @param XEmacPsPtr is a pointer to the XEMACPS instance that has caused the
-* interrupt.
-*
-******************************************************************************/
-void XEmacPs_IntrHandler(void *XEmacPsPtr)
-{
- u32 RegISR;
- u32 RegSR;
- u32 RegCtrl;
- u32 RegQ1ISR = 0U;
- XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- /* This ISR will try to handle as many interrupts as it can in a single
- * call. However, in most of the places where the user's error handler
- * is called, this ISR exits because it is expected that the user will
- * reset the device in nearly all instances.
- */
- RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_ISR_OFFSET);
-
- /* Read Transmit Q1 ISR */
-
- if (InstancePtr->Version > 2)
- RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_INTQ1_STS_OFFSET);
-
- /* Clear the interrupt status register */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
- RegISR);
-
- /* Receive complete interrupt */
- if ((RegISR & XEMACPS_IXR_FRAMERX_MASK) != 0x00000000U) {
- /* Clear RX status register RX complete indication but preserve
- * error bits if there is any */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_RXSR_OFFSET,
- ((u32)XEMACPS_RXSR_FRAMERX_MASK |
- (u32)XEMACPS_RXSR_BUFFNA_MASK));
- InstancePtr->RecvHandler(InstancePtr->RecvRef);
- }
-
- /* Transmit Q1 complete interrupt */
- if ((InstancePtr->Version > 2) &&
- ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
- /* Clear TX status register TX complete indication but preserve
- * error bits if there is any */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_INTQ1_STS_OFFSET,
- XEMACPS_INTQ1SR_TXCOMPL_MASK);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_TXSR_OFFSET,
- ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
- (u32)XEMACPS_TXSR_USEDREAD_MASK));
- InstancePtr->SendHandler(InstancePtr->SendRef);
- }
-
- /* Transmit complete interrupt */
- if ((RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U) {
- /* Clear TX status register TX complete indication but preserve
- * error bits if there is any */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_TXSR_OFFSET,
- ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
- (u32)XEMACPS_TXSR_USEDREAD_MASK));
- InstancePtr->SendHandler(InstancePtr->SendRef);
- }
-
- /* Receive error conditions interrupt */
- if ((RegISR & XEMACPS_IXR_RX_ERR_MASK) != 0x00000000U) {
- /* Clear RX status register */
- RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_RXSR_OFFSET);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_RXSR_OFFSET, RegSR);
-
- /* Fix for CR # 692702. Write to bit 18 of net_ctrl
- * register to flush a packet out of Rx SRAM upon
- * an error for receive buffer not available. */
- if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
- RegCtrl =
- XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET);
- RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET, RegCtrl);
- }
-
- if(RegSR != 0) {
- InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
- XEMACPS_RECV, RegSR);
- }
- }
-
- /* When XEMACPS_IXR_TXCOMPL_MASK is flagged, XEMACPS_IXR_TXUSED_MASK
- * will be asserted the same time.
- * Have to distinguish this bit to handle the real error condition.
- */
- /* Transmit Q1 error conditions interrupt */
- if ((InstancePtr->Version > 2) &&
- ((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
- ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
- /* Clear Interrupt Q1 status register */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_INTQ1_STS_OFFSET, RegQ1ISR);
- InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
- RegQ1ISR);
- }
-
- /* Transmit error conditions interrupt */
- if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
- (!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
- /* Clear TX status register */
- RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_TXSR_OFFSET);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_TXSR_OFFSET, RegSR);
- InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
- RegSR);
- }
-
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/20/01d3c9565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/20/01d3c9565243001d18b399c1eb9b3628
deleted file mode 100644
index bbf3bb8..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/20/01d3c9565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,35 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include "xil_types.h"
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) char8 *sbrk (s32 nbytes);
-}
-#endif
-
-extern u8 _heap_start[];
-extern u8 _heap_end[];
-extern char8 HeapBase[];
-extern char8 HeapLimit[];
-
-
-
-__attribute__((weak)) char8 *sbrk (s32 nbytes)
-{
- char8 *base;
- static char8 *heap_ptr = HeapBase;
-
- base = heap_ptr;
- if((heap_ptr != NULL) && (heap_ptr + nbytes <= (char8 *)&HeapLimit + 1)) {
- heap_ptr += nbytes;
- return base;
- } else {
- errno = ENOMEM;
- return ((char8 *)-1);
- }
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/20/106c2e585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/20/106c2e585243001d18b399c1eb9b3628
deleted file mode 100644
index 2782826..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/20/106c2e585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,342 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xsdps.h
-* @addtogroup sdps_v3_13
-* @{
-* @details
-*
-* This file contains the implementation of XSdPs driver.
-* This driver is used initialize read from and write to the SD card.
-* Features such as switching bus width to 4-bit and switching to high speed,
-* changing clock frequency, block size etc. are supported.
-* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
-* is done using 1-bit bus width and 400KHz clock frequency.
-* SD commands are classified as broadcast and addressed. Commands can be
-* those with response only (using only command line) or
-* response + data (using command and data lines).
-* Only one command can be sent at a time. During a data transfer however,
-* when dsta lines are in use, certain commands (which use only the command
-* line) can be sent, most often to obtain status.
-* This driver does not support multi card slots at present.
-*
-* Initialization:
-* This includes initialization on the host controller side to select
-* clock frequency, bus power and default transfer related parameters.
-* The default voltage is 3.3V.
-* On the SD card side, the initialization and identification state diagram is
-* implemented. This resets the card, gives it a unique address/ID and
-* identifies key card related specifications.
-*
-* Data transfer:
-* The SD card is put in transfer state to read from or write to it.
-* The default block size is 512 bytes and if supported,
-* default bus width is 4-bit and bus speed is High speed.
-* The read and write functions are implemented in polled mode using ADMA2.
-*
-* At any point, when key parameters such as block size or
-* clock/speed or bus width are modified, this driver takes care of
-* maintaining the same selection on host and card.
-* All error bits in host controller are monitored by the driver and in the
-* event one of them is set, driver will clear the interrupt status and
-* communicate failure to the upper layer.
-*
-* File system use:
-* This driver can be used with xilffs library to read and write files to SD.
-* (Please refer to procedure in diskio.c). The file system read/write example
-* in polled mode can used for reference.
-*
-* There is no example for using SD driver without file system at present.
-* However, the driver can be used without the file system. The glue layer
-* in filesystem can be used as reference for the same. The block count
-* passed to the read/write function in one call is limited by the ADMA2
-* descriptor table and hence care will have to be taken to call read/write
-* API's in a loop for large file sizes.
-*
-* Interrupt mode is not supported because it offers no improvement when used
-* with file system.
-*
-* eMMC support:
-* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
-* The features of eMMC supported by the driver will depend on those supported
-* by the host controller. The current driver supports read/write on eMMC card
-* using 4-bit and high speed mode currently.
-*
-* Features not supported include - card write protect, password setting,
-* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
-* 64-bit addressed ADMA2, erase/pre-erase commands.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a hk/sg 10/17/13 Initial release
-* 2.0 hk 03/07/14 Version number revised.
-* 2.1 hk 04/18/14 Increase sleep for eMMC switch command.
-* Add sleep for microblaze designs. CR# 781117.
-* 2.2 hk 07/28/14 Make changes to enable use of data cache.
-* 2.3 sk 09/23/14 Send command for relative card address
-* when re-initialization is done.CR# 819614.
-* Use XSdPs_Change_ClkFreq API whenever changing
-* clock.CR# 816586.
-* 2.4 sk 12/04/14 Added support for micro SD without
-* WP/CD. CR# 810655.
-* Checked for DAT Inhibit mask instead of CMD
-* Inhibit mask in Cmd Transfer API.
-* Added Support for SD Card v1.0
-* 2.5 sg 07/09/15 Added SD 3.0 features
-* kvn 07/15/15 Modified the code according to MISRAC-2012.
-* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
-* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
-* sk 12/10/15 Added support for MMC cards.
-* 01/08/16 Added workaround for issue in auto tuning mode
-* of SDR50, SDR104 and HS200.
-* sk 02/16/16 Corrected the Tuning logic.
-* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
-* 2.8 sk 04/20/16 Added new workaround for auto tuning.
-* 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
-* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
-* sk 07/16/16 Added support for UHS modes.
-* sk 07/07/16 Used usleep API for both arm and microblaze.
-* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
-* operating modes.
-* sk 08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
-* CR#956899.
-* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
-* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
-* sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
-* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
-* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value.
-* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
-* sk 02/01/17 Added HSD and DDR mode support for eMMC.
-* sk 02/01/17 Consider bus width parameter from design for switching
-* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
-* sk 03/20/17 Add support for EL1 non-secure mode.
-* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
-* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
-* mn 08/17/17 Enabled CCI support for A53 by adding cache coherency
-* information.
-* mn 09/06/17 Resolved compilation errors with IAR toolchain
-* 3.6 mn 08/01/18 Add support for using 64Bit DMA with 32-Bit Processor
-* 3.7 mn 02/01/19 Add support for idling of SDIO
-* 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
-* mn 09/17/19 Modified ADMA handling API for 32bit and 64bit addresses
-* 3.9 mn 03/03/20 Restructured the code for more readability and modularity
-* mn 03/16/20 Move XSdPs_Select_Card API to User APIs
-* 3.10 mn 06/05/20 Check Transfer completion separately from XSdPs_Read and
-* XSdPs_Write APIs
-* mn 06/05/20 Modified code for SD Non-Blocking Read support
-* 3.11 sk 12/01/20 Tap programming sequence updates like disable OTAPEN
-* always, write zero to tap register for zero tap value.
-* sk 12/07/20 Fix eMMC DDR52 mode write/read issue.
-* sk 12/17/20 Removed checking platform specific SD macros and used
-* Baseaddress instead.
-* 3.12 sk 01/28/21 Added support for non-blocking write.
-* sk 02/12/21 Fix the issue in reading CID and CSD.
-* sk 04/08/21 Fixed doxygen warnings in all source files.
-* sk 05/25/21 Fix the compilation issue in Cortex-A72 + EL1_NS by
-* removing the DLL reset logic (Dead code for Versal).
-* 3.13 sk 08/10/21 Limit the SD operating frequency to 19MHz for Versal.
-*
-*
-*
-******************************************************************************/
-
-
-#ifndef SDPS_H_
-#define SDPS_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xil_printf.h"
-#include "xil_cache.h"
-#include "xstatus.h"
-#include "xsdps_hw.h"
-#include "xplatform_info.h"
-#include "sleep.h"
-#include
-#if defined (XCLOCKING)
-#include "xil_clocking.h"
-#endif
-
-/************************** Constant Definitions *****************************/
-
-#define XSDPS_CT_ERROR 0x2L /**< Command timeout flag */
-#define MAX_TUNING_COUNT 40U /**< Maximum Tuning count */
-#define MAX_TIMEOUT 0x1FFFFFFFU /**< Maximum Timeout */
-#define XSDPS_CMD8_VOL_PATTERN 0x1AAU /**< CMD8 voltage pattern */
-#define XSDPS_RESPOCR_READY 0x80000000U /**< Ready response */
-#define XSDPS_ACMD41_HCS 0x40000000U /**< High Capacity Support */
-#define XSDPS_ACMD41_3V3 0x00300000U /**< 3.3 voltage support */
-#define XSDPS_CMD1_HIGH_VOL 0x00FF8000U /**< CMD1 for High voltage */
-#define XSDPS_CMD1_DUAL_VOL 0x00FF8010U /**< CMD1 for Dual voltage */
-#define HIGH_SPEED_SUPPORT 0x2U /**< High Speed support */
-#define UHS_SDR12_SUPPORT 0x1U /**< SDR12 support */
-#define UHS_SDR25_SUPPORT 0x2U /**< SDR25 support */
-#define UHS_SDR50_SUPPORT 0x4U /**< SDR50 support */
-#define UHS_SDR104_SUPPORT 0x8U /**< SDR104 support */
-#define UHS_DDR50_SUPPORT 0x10U /**< DDR50 support */
-#define WIDTH_4_BIT_SUPPORT 0x4U /**< 4-bit width support */
-#define SD_CLK_25_MHZ 25000000U /**< 25MHz clock */
-#define SD_CLK_19_MHZ 19000000U /**< 19MHz clock */
-#define SD_CLK_26_MHZ 26000000U /**< 26MHz clock */
-#define EXT_CSD_DEVICE_TYPE_BYTE 196U /**< CSD Device Type byte number */
-#define EXT_CSD_SEC_COUNT_BYTE1 212U /**< CSD Sector count byte 1 */
-#define EXT_CSD_SEC_COUNT_BYTE2 213U /**< CSD Sector count byte 2 */
-#define EXT_CSD_SEC_COUNT_BYTE3 214U /**< CSD Sector count byte 3 */
-#define EXT_CSD_SEC_COUNT_BYTE4 215U /**< CSD Sector count byte 4 */
-#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED 0x2U /**< CSD Device type HS */
-#define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED 0x4U /**< CSD Dev type DDR 1.8v speed */
-#define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED 0x8U /**< CSD Dev type DDR 1.2v speed */
-#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 0x10U /**< CSD SDR 1.8v HS200 */
-#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200 0x20U /**< CSD SDR 1.2v HS200 */
-#define CSD_SPEC_VER_3 0x3U /**< CSD card spec ver 3 */
-#define SCR_SPEC_VER_3 0x80U /**< SCR spec ver 3 */
-#define ADDRESS_BEYOND_32BIT 0x100000000U /**< Macro used for beyond 32-bit addr */
-
-#define XSDPS_ZYNQMP_SD0_BASE 0xFF160000U /**< ZynqMP SD0 Baseaddress */
-#define XSDPS_ZYNQMP_SD1_BASE 0xFF170000U /**< ZynqMP SD1 Baseaddress */
-#define XSDPS_VERSAL_SD0_BASE 0xF1040000U /**< Versal SD0 Baseaddress */
-#define XSDPS_VERSAL_SD1_BASE 0xF1050000U /**< Versal SD1 Baseaddress */
-
-/**************************** Type Definitions *******************************/
-
-/**
- * Function pointer for configuring the Tap delays.
- */
-typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of the device */
- u32 InputClockHz; /**< Input clock frequency */
- u32 CardDetect; /**< Card Detect */
- u32 WriteProtect; /**< Write Protect */
- u32 BusWidth; /**< Bus Width */
- u32 BankNumber; /**< MIO Bank selection for SD */
- u32 HasEMIO; /**< If SD is connected to EMIO */
- u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */
-#if defined (XCLOCKING)
- u32 RefClk; /**< Input clocks */
-#endif
-} XSdPs_Config;
-
-/**
- * ADMA2 32-Bit descriptor table
- */
-typedef struct {
- u16 Attribute; /**< Attributes of descriptor */
- u16 Length; /**< Length of current dma transfer */
- u32 Address; /**< Address of current dma transfer */
-#ifdef __ICCARM__
-#pragma data_alignment = 32
-} XSdPs_Adma2Descriptor32;
-#else
-} __attribute__((__packed__))XSdPs_Adma2Descriptor32;
-#endif
-
-/**
- * ADMA2 64-Bit descriptor table
- */
-typedef struct {
- u16 Attribute; /**< Attributes of descriptor */
- u16 Length; /**< Length of current dma transfer */
- u64 Address; /**< Address of current dma transfer */
-#ifdef __ICCARM__
-#pragma data_alignment = 32
-} XSdPs_Adma2Descriptor64;
-#else
-} __attribute__((__packed__))XSdPs_Adma2Descriptor64;
-#endif
-
-/**
- * The XSdPs driver instance data. The user is required to allocate a
- * variable of this type for every SD device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XSdPs_Config Config; /**< Configuration structure */
- u32 IsReady; /**< Device is initialized and ready */
- u32 Host_Caps; /**< Capabilities of host controller */
- u32 Host_CapsExt; /**< Extended Capabilities */
- u32 HCS; /**< High capacity support in card */
- u8 CardType; /**< Type of card - SD/MMC/eMMC */
- u8 Card_Version; /**< Card version */
- u8 HC_Version; /**< Host controller version */
- u8 BusWidth; /**< Current operating bus width */
- u32 BusSpeed; /**< Current operating bus speed */
- u8 Switch1v8; /**< 1.8V Switch support */
- u32 CardID[4]; /**< Card ID Register */
- u32 RelCardAddr; /**< Relative Card Address */
- u32 CardSpecData[4]; /**< Card Specific Data Register */
- u32 SectorCount; /**< Sector Count */
- u32 SdCardConfig; /**< Sd Card Configuration Register */
- u32 Mode; /**< Bus Speed Mode */
- u32 OTapDelay; /**< Output Tap Delay */
- u32 ITapDelay; /**< Input Tap Delay */
- u64 Dma64BitAddr; /**< 64 Bit DMA Address */
- u16 TransferMode; /**< Transfer Mode */
- u32 SlcrBaseAddr; /**< SLCR base address*/
- u8 IsBusy; /**< Busy Flag*/
- u32 BlkSize; /**< Block Size*/
-} XSdPs;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-/**
- * @name SD High Speed mode configuration options
- * @{
- */
-/**
- * User configuration option to enable or disable SD HS mode.
- * By default SD HS mode is disabled for Versal and enabled for
- * other platforms.
- */
-#ifdef versal
-#define SD_HS_MODE_ENABLE 0
-#else
-#define SD_HS_MODE_ENABLE 1
-#endif
-/** @} */
-
-/************************** Function Prototypes ******************************/
-XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
-s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
- u32 EffectiveAddr);
-s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
-s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
-s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
-s32 XSdPs_Idle(XSdPs *InstancePtr);
-
-s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr);
-s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq);
-s32 XSdPs_Pullup(XSdPs *InstancePtr);
-s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *ReadBuff);
-s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr);
-s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff);
-s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
-s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg);
-s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize);
-s32 XSdPs_Get_Status(XSdPs *InstancePtr, u8 *SdStatReg);
-s32 XSdPs_Select_Card(XSdPs *InstancePtr);
-s32 XSdPs_StartReadTransfer(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
-s32 XSdPs_CheckReadTransfer(XSdPs *InstancePtr);
-s32 XSdPs_StartWriteTransfer(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
-s32 XSdPs_CheckWriteTransfer(XSdPs *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SD_H_ */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/20/52cbd6565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/20/52cbd6565243001d18b399c1eb9b3628
deleted file mode 100644
index 77e1f3d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/20/52cbd6565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,74 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache_vxworks.h
-*
-* Contains the cache related functions for VxWorks that is wrapped by
-* xil_cache.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 12/11/09 Initial release
-*
-*
-*
-* @note
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_CACHE_VXWORKS_H
-#define XIL_CACHE_VXWORKS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "vxWorks.h"
-#include "vxLib.h"
-#include "sysLibExtra.h"
-#include "cacheLib.h"
-
-#if (CPU_FAMILY==PPC)
-
-#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
-
-#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
-
-#define Xil_DCacheInvalidateRange(Addr, Len) \
- cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
-
-#define Xil_DCacheFlushRange(Addr, Len) \
- cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
-
-#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
-
-#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
-
-#define Xil_ICacheInvalidateRange(Addr, Len) \
- cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
-
-
-#else
-#error "Unknown processor / architecture. Must be PPC for VxWorks."
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
- *@endcond
- */
\ No newline at end of file
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/20/702b6f525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/20/702b6f525243001d18b399c1eb9b3628
deleted file mode 100644
index 47bef93..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/20/702b6f525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,8 +0,0 @@
--= SD card boot image =-
-
-Platform:
-Application:
-
-1. Copy the contents of this directory to an SD card
-2. Set boot mode to SD
-3. Insert SD card and turn board on
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/20/b13fcd545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/20/b13fcd545243001d18b399c1eb9b3628
deleted file mode 100644
index 0e77af1..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/20/b13fcd545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1305 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xscugic.c
-* @addtogroup scugic_v4_6
-* @{
-*
-* Contains required functions for the XScuGic driver for the Interrupt
-* Controller. See xscugic.h for a detailed description of the driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- --------------------------------------------------------
-* 1.00a drg 01/19/10 First release
-* 1.01a sdm 11/09/11 Changes are made in function XScuGic_CfgInitialize
-* Since entry is now made as pointer in the XScuGic
-* structure, necessary changes are made.
-* The HandlerTable can now be populated through the low
-* level routine XScuGic_RegisterHandler added in this
-* release. Hence necessary checks are added not to
-* overwrite the HandlerTable entries in function
-* XScuGic_CfgInitialize.
-* 1.03a srt 02/27/13 Added APIs
-* -XScuGic_SetPriTrigTypeByDistAddr()
-* -XScuGic_GetPriTrigTypeByDistAddr()
-* Removed Offset calculation macros, defined in _hw.h
-* (CR 702687)
-* added support to direct interrupts to the appropriate
-* CPU Earlier interrupts were directed to CPU1
-* (hard coded).Now depending upon the CPU selected by the
-* user(xparameters.h), interrupts will be directed to
-* the relevant CPU. This fixes CR 699688.
-*
-* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
-* XScuGic_CfgInitialize. Fix for CR#704400 to remove
-* warnings.
-* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
-* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
-* This is fix for CR#705621.
-* 1.06a asa 16/11/13 Fix for CR#749178. Assignment for EffectiveAddr
-* in function XScuGic_CfgInitialize is removed as it was
-* a bug.
-* 3.00 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
-* 3.01 pkp 06/19/15 Added XScuGic_InterruptMaptoCpu API for an interrupt
-* target CPU mapping
-* 3.02 pkp 11/09/15 Modified DistributorInit function for AMP case to add
-* the current cpu to interrupt processor targets registers
-* 3.2 asa 02/29/16 Modified DistributorInit function for Zynq AMP case. The
-* distributor is left uninitialized for Zynq AMP. It is
-* assumed that the distributor will be initialized by
-* Linux master. However for CortexR5 case, the earlier code
-* is left unchanged where the interrupt processor target
-* registers in the distributor is initialized with the
-* corresponding CPU ID on which the application built over
-* the scugic driver runs. These changes fix CR#937243.
-* 3.3 pkp 05/12/16 Modified XScuGic_InterruptMaptoCpu to write proper value
-* to interrupt target register to fix CR#951848
-*
-* 3.4 asa 04/07/16 Created a new static function DoDistributorInit to
-* simplify the flow and avoid code duplication. Changes are
-* made for USE_AMP use case for R5. In a scenario
-* (in R5 split mode) when one R5 is operating with A53 in
-* open amp config and other R5 running baremetal app, the
-* existing code had the potential to stop the whole AMP
-* solution to work (if for some reason the R5 running the
-* baremetal app tasked to initialize the Distributor hangs
-* or crashes before initializing).Changes are made so that
-* the R5 under AMP first checks if the distributor is
-* enabled or not and if not, it does the standard
-* Distributor initialization.This fixes the CR#952962.
-* 3.4 mus 09/08/16 Added assert to avoid invalid access of GIC from CPUID 1
-* for single core zynq-7000s
-* 3.5 mus 10/05/16 Modified DistributorInit function to avoid
-* re-initialization of distributor, If it is already
-* initialized by other CPU.
-* 3.5 pkp 10/17/16 Modified XScuGic_InterruptMaptoCpu to correct the CPU Id
-* value and properly mask interrupt target processor value
-* to modify interrupt target processor register for a given
-* interrupt ID and cpu ID
-* 3.6 pkp 20/01/17 Added new API XScuGic_Stop to Disable distributor and
-* interrupts in case they are being used only by current
-* cpu. It also removes current cpu from interrupt target
-* registers for all interrupts.
-* kvn 02/17/17 Add support for changing GIC CPU master at run time.
-* kvn 02/28/17 Make the CpuId as static variable and Added new
-* XScugiC_GetCpuId to access CpuId.
-* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
-* XScuGic_InterruptUnmapFromCpu, These API's can be used
-* by applications to unmap specific/all interrupts from
-* target CPU. It fixes CR#992490.
-* 3.10 mus 07/17/18 Updated file to fix the various coding style issues
-* reported by checkpatch. It fixes CR#1006344.
-* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
-* It fixes CR#1007753.
-* 3.10 mus 09/19/18 Fix cppcheck warnings
-* 4.0 mus 11/22/18 Fixed bugs in software interrupt generation through
-* XScuGic_SoftwareIntr API
-* 4.1 asa 03/30/19 Made changes not to direct each interrupt to all
-* available CPUs by default. This was breaking AMP
-* behavior. Instead every time an interrupt enable
-* request is received, the interrupt was mapped to
-* the respective CPU. There were several other changes
-* made to implement this. This set of changes was to
-* fix CR-1024716.
-* 4.1 mus 06/19/19 Added API's XScuGic_MarkCoreAsleep and
-* XScuGic_MarkCoreAwake to mark processor core as
-* asleep or awake. Fix for CR#1027220.
-* 4.3 mus 10/14/20 Updated XScuGic_Stop for scenarios where USE_AMP flag
-* is set to 1. Now, XScuGic_Stop would not disable
-* distributor for USE_AMP=1, even when SPI interrupts
-* are not being used by other CPU. This update is needed
-* to support scenarios, where master CPU is using only
-* SGI/PPI interrupts. It fixes CR#1079241.
-* 4.5 asa 03/07/21 Added spinlock protection for critical sections in the
-* code. The sections are critical when applications
-* running on separate CPUs (R5s or A9s) try to update
-* the same register. The spinlock mechanism used here
-* used exclusive load and store instructions. To ensure
-* that legacy behavior is not broken, unless someone
-* enables spinlocks explicitely in their applications
-* the existing flow will remain unchanged. On how to
-* enable spinlocks, please refer to the documentations
-* at: lib/bsp/standalone/src/arm/common/gcc/xil_spinlock.c
-* 4.6 sk 08/05/21 Fix scugic Misra-c violations.
-* 4.7 sk 09/14/21 Fix gcc compiler warnings for A72 processor.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xscugic.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-static u32 CpuId = XPAR_CPU_ID; /**< CPU Core identifier */
-
-/************************** Function Prototypes ******************************/
-
-static void StubHandler(void *CallBackRef);
-
-/*****************************************************************************/
-/**
-*
-* DoDistributorInit initializes the distributor of the GIC. The
-* initialization entails:
-*
-* - Write the trigger mode, priority
-* - All interrupt sources are disabled
-* - Enable the distributor
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-static void DoDistributorInit(const XScuGic *InstancePtr)
-{
- u32 Int_Id;
-
-#if defined (GICv3)
- u32 Temp;
-
- Temp = XScuGic_DistReadReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET);
- Temp = (XSCUGIC500_DCTLR_ARE_NS_ENABLE | XSCUGIC500_DCTLR_ARE_S_ENABLE);
- Temp &= ~(XSCUGIC_EN_INT_MASK);
- XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, Temp);
-#else
- XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U);
-#endif
-
- /*
- * Set the security domains in the int_security registers for
- * non-secure interrupts
- * All are secure, so leave at the default. Set to 1 for non-secure
- * interrupts.
- */
-
- /*
- * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
- */
-
- /*
- * 1. The trigger mode in the int_config register
- * Only write to the SPI interrupts, so start at 32
- */
- for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
- Int_Id = Int_Id+16U) {
- /*
- * Each INT_ID uses two bits, or 16 INT_ID per register
- * Set them all to be level sensitive, active HIGH.
- */
- XScuGic_DistWriteReg(InstancePtr,
- XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
- 0U);
- }
-
-
-#define DEFAULT_PRIORITY 0xa0a0a0a0U
- for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
- Int_Id = Int_Id+4U) {
- /*
- * 2. The priority using int the priority_level register
- * The priority_level and spi_target registers use one byte per
- * INT_ID.
- * Write a default value that can be changed elsewhere.
- */
- XScuGic_DistWriteReg(InstancePtr,
- XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
- DEFAULT_PRIORITY);
- }
-
-#if defined (GICv3)
- for (Int_Id = 0U; Int_IdBaseAddress for this parameters, passing the physical
-* address instead.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-*
-* @note None.
-*
-******************************************************************************/
-s32 XScuGic_CfgInitialize(XScuGic *InstancePtr,
- XScuGic_Config *ConfigPtr,
- u32 EffectiveAddr)
-{
- u32 Int_Id;
- (void) EffectiveAddr;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
- /*
- * Check Zynq-7000 base silicon configuration.
- * If it is single CPU configuration then invoke assert for CPU ID 1.
- */
-#ifdef ARMA9
- if (XPAR_CPU_ID == 0x01) {
- Xil_AssertNonvoid((Xil_In32(XPS_EFUSE_BASEADDR
- + EFUSE_STATUS_OFFSET) & EFUSE_STATUS_CPU_MASK) == 0);
- }
-#endif
-
- if(InstancePtr->IsReady != XIL_COMPONENT_IS_READY) {
-
- InstancePtr->IsReady = 0U;
- InstancePtr->Config = ConfigPtr;
-
-
- for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
- Int_Id++) {
- /*
- * Initialize the handler to point to a stub to handle an
- * interrupt which has not been connected to a handler
- * Only initialize it if the handler is 0 which means it
- * was not initialized statically by the tools/user. Set
- * the callback reference to this instance so that
- * unhandled interrupts can be tracked.
- */
- if ((InstancePtr->Config->HandlerTable[Int_Id].Handler
- == (Xil_InterruptHandler)NULL)) {
- InstancePtr->Config->HandlerTable[Int_Id].Handler
- = (Xil_InterruptHandler)StubHandler;
- }
- InstancePtr->Config->HandlerTable[Int_Id].CallBackRef =
- InstancePtr;
- }
-#if defined (GICv3)
- u32 Waker_State;
- Waker_State = XScuGic_ReDistReadReg(InstancePtr,XSCUGIC_RDIST_WAKER_OFFSET);
- XScuGic_ReDistWriteReg(InstancePtr,XSCUGIC_RDIST_WAKER_OFFSET,
- Waker_State & (~ XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK));
- /* Enable system reg interface through ICC_SRE_EL1 */
- #if EL3
- XScuGic_Enable_SystemReg_CPU_Interface_EL3();
- #endif
- XScuGic_Enable_SystemReg_CPU_Interface_EL1();
- isb();
-#endif
- XScuGic_Stop(InstancePtr);
- DistributorInit(InstancePtr);
-#if defined (GICv3)
- XScuGic_set_priority_filter(0xff);
-#else
- CPUInitialize(InstancePtr);
-#endif
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Makes the connection between the Int_Id of the interrupt source and the
-* associated handler that is to run when the interrupt is recognized. The
-* argument provided in this call as the Callbackref is used as the argument
-* for the handler when it is called.
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-* @param Int_Id contains the ID of the interrupt source and should be
-* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-* @param Handler to the handler for that interrupt.
-* @param CallBackRef is the callback reference, usually the instance
-* pointer of the connecting driver.
-*
-* @return
-*
-* - XST_SUCCESS if the handler was connected correctly.
-*
-* @note
-*
-* WARNING: The handler provided as an argument will overwrite any handler
-* that was previously connected.
-*
-****************************************************************************/
-s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
- Xil_InterruptHandler Handler, void *CallBackRef)
-{
- /*
- * Assert the arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
- Xil_AssertNonvoid(Handler != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * The Int_Id is used as an index into the table to select the proper
- * handler
- */
- InstancePtr->Config->HandlerTable[Int_Id].Handler = (Xil_InterruptHandler)Handler;
- InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = CallBackRef;
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Updates the interrupt table with the Null Handler and NULL arguments at the
-* location pointed at by the Int_Id. This effectively disconnects that interrupt
-* source from any handler. The interrupt is disabled also.
-*
-* @param InstancePtr is a pointer to the XScuGic instance to be worked on.
-* @param Int_Id contains the ID of the interrupt source and should
-* be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id)
-{
- u32 Mask;
-
- /*
- * Assert the arguments
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
-
- /*
- * The Int_Id is used to create the appropriate mask for the
- * desired bit position. Int_Id currently limited to 0 - 31
- */
- Mask = (u32)0x00000001U << (Int_Id % 32U);
-
- /*
- * Disable the interrupt such that it won't occur while disconnecting
- * the handler, only disable the specified interrupt id without
- * modifying the other interrupt ids
- */
- XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
- ((Int_Id / 32U) * 4U), Mask);
-
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
- /*
- * Disconnect the handler and connect a stub, the callback reference
- * must be set to this instance to allow unhandled interrupts to be
- * tracked
- */
- InstancePtr->Config->HandlerTable[Int_Id].Handler = (Xil_InterruptHandler)StubHandler;
- InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = InstancePtr;
-}
-
-/*****************************************************************************/
-/**
-*
-* Enables the interrupt source provided as the argument Int_Id. Any pending
-* interrupt condition for the specified Int_Id will occur after this function is
-* called.
-* This API also maps the interrupt to the requesting CPU.
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-* @param Int_Id contains the ID of the interrupt source and should be
-* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id)
-{
- u32 Mask;
- u8 Cpu_Identifier = (u8)CpuId;
-
-#if defined (GICv3)
- u32 Temp;
-#endif
- /*
- * Assert the arguments
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-#if defined (GICv3)
- if (Int_Id < XSCUGIC_SPI_INT_ID_START) {
- XScuGic_InterruptMaptoCpu(InstancePtr, Cpu_Identifier, Int_Id);
-
- Int_Id &= 0x1f;
- Int_Id = 1 << Int_Id;
-
- Temp = XScuGic_ReDistSGIPPIReadReg(InstancePtr,XSCUGIC_RDIST_ISENABLE_OFFSET);
- Temp |= Int_Id;
- XScuGic_ReDistSGIPPIWriteReg(InstancePtr,XSCUGIC_RDIST_ISENABLE_OFFSET,Temp);
- }
-#endif
- XScuGic_InterruptMaptoCpu(InstancePtr, Cpu_Identifier, Int_Id);
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
- /*
- * The Int_Id is used to create the appropriate mask for the
- * desired bit position.
- */
- Mask = (u32)0x00000001U << (Int_Id % 32U);
- /*
- * Enable the selected interrupt source by setting the
- * corresponding bit in the Enable Set register.
- */
- XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_ENABLE_SET_OFFSET +
- ((Int_Id / 32U) * 4U), Mask);
-
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-}
-
-/*****************************************************************************/
-/**
-*
-* Disables the interrupt source provided as the argument Int_Id such that the
-* interrupt controller will not cause interrupts for the specified Int_Id. The
-* interrupt controller will continue to hold an interrupt condition for the
-* Int_Id, but will not cause an interrupt.
-* This API also unmaps the interrupt for the requesting CPU.
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-* @param Int_Id contains the ID of the interrupt source and should be
-* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id)
-{
- u32 Mask;
- u8 Cpu_Identifier = (u8)CpuId;
-#if defined (GICv3)
- u32 Temp;
-#endif
-
- /*
- * Assert the arguments
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-#if defined (GICv3)
- if (Int_Id < XSCUGIC_SPI_INT_ID_START) {
-
- XScuGic_InterruptUnmapFromCpu(InstancePtr, Cpu_Identifier, Int_Id);
-
- Int_Id &= 0x1f;
- Int_Id = 1 << Int_Id;
-
- Temp = XScuGic_ReDistSGIPPIReadReg(InstancePtr,XSCUGIC_RDIST_ISENABLE_OFFSET);
- Temp &= ~Int_Id;
- XScuGic_ReDistSGIPPIWriteReg(InstancePtr,XSCUGIC_RDIST_ISENABLE_OFFSET,Temp);
- }
-#endif
- XScuGic_InterruptUnmapFromCpu(InstancePtr, Cpu_Identifier, Int_Id);
-
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
- /*
- * The Int_Id is used to create the appropriate mask for the
- * desired bit position. Int_Id currently limited to 0 - 31
- */
- Mask = (u32)0x00000001U << (Int_Id % 32U);
-
- /*
- * Disable the selected interrupt source by setting the
- * corresponding bit in the IDR.
- */
- XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
- ((Int_Id / 32U) * 4U), Mask);
-
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-}
-
-/*****************************************************************************/
-/**
-*
-* Allows software to simulate an interrupt in the interrupt controller. This
-* function will only be successful when the interrupt controller has been
-* started in simulation mode. A simulated interrupt allows the interrupt
-* controller to be tested without any device to drive an interrupt input
-* signal into it.
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-* @param Int_Id is the software interrupt ID to simulate an interrupt.
-* @param Cpu_Identifier is the list of CPUs to send the interrupt.
-*
-* @return
-*
-* XST_SUCCESS if successful, or XST_FAILURE if the interrupt could not be
-* simulated
-*
-* @note None.
-*
-******************************************************************************/
-s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Identifier)
-{
- u32 Mask;
-
- /*
- * Assert the arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Int_Id <= 15U);
- Xil_AssertNonvoid(Cpu_Identifier <= 255U);
-
-#if defined (GICv3)
- Mask = (Cpu_Identifier | (Int_Id << XSCUGIC_SGIR_EL1_INITID_SHIFT));
-#if EL3
- XScuGic_WriteICC_SGI0R_EL1(Mask);
-#else
- XScuGic_WriteICC_SGI1R_EL1(Mask);
-#endif
-#else
-
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
-
- /*
- * The Int_Id is used to create the appropriate mask for the
- * desired interrupt. Int_Id currently limited to 0 - 15
- * Use the target list for the Cpu ID.
- */
- Mask = ((Cpu_Identifier << 16U) | Int_Id) &
- (XSCUGIC_SFI_TRIG_CPU_MASK | XSCUGIC_SFI_TRIG_INTID_MASK);
-
- /*
- * Write to the Software interrupt trigger register. Use the appropriate
- * CPU Int_Id.
- */
- XScuGic_DistWriteReg(InstancePtr, XSCUGIC_SFI_TRIG_OFFSET, Mask);
-
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-
- /* Indicate the interrupt was successfully simulated */
-#endif
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* A stub for the asynchronous callback. The stub is here in case the upper
-* layers forget to set the handler.
-*
-* @param CallBackRef is a pointer to the upper layer callback reference
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-static void StubHandler(void *CallBackRef)
-{
- /*
- * verify that the inputs are valid
- */
- Xil_AssertVoid(CallBackRef != NULL);
-
- /*
- * Indicate another unhandled interrupt for stats
- */
- ((XScuGic *)((void *)CallBackRef))->UnhandledInterrupts++;
-}
-
-/****************************************************************************/
-/**
-* Sets the interrupt priority and trigger type for the specificd IRQ source.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Int_Id is the IRQ source number to modify
-* @param Priority is the new priority for the IRQ source. 0 is highest
-* priority, 0xF8(248) is lowest. There are 32 priority levels
-* supported with a step of 8. Hence the supported priorities are
-* 0, 8, 16, 32, 40 ..., 248.
-* @param Trigger is the new trigger type for the IRQ source.
-* Each bit pair describes the configuration for an INT_ID.
-* SFI Read Only b10 always
-* PPI Read Only depending on how the PPIs are configured.
-* b01 Active HIGH level sensitive
-* b11 Rising edge sensitive
-* SPI LSB is read only.
-* b01 Active HIGH level sensitive
-* b11 Rising edge sensitive/
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
- u8 Priority, u8 Trigger)
-{
- u32 RegValue;
-#if defined (GICv3)
- u32 Temp;
- u32 Index;
-#endif
- u8 LocalPriority;
- LocalPriority = Priority;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(Trigger <= (u8)XSCUGIC_INT_CFG_MASK);
- Xil_AssertVoid(LocalPriority <= (u8)XSCUGIC_MAX_INTR_PRIO_VAL);
-#if defined (GICv3)
- if (Int_Id < XSCUGIC_SPI_INT_ID_START )
- {
- XScuGic_ReDistSGIPPIWriteReg(InstancePtr,XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(Int_Id),Priority);
- Temp = XScuGic_ReDistSGIPPIReadReg(InstancePtr,XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(Int_Id));
- Index = XScuGic_Get_Rdist_Int_Trigger_Index(Int_Id);
- Temp |= (Trigger << Index);
- XScuGic_ReDistSGIPPIWriteReg(InstancePtr,XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(Int_Id),Temp);
- return;
- }
-#endif
-
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
- /*
- * Determine the register to write to using the Int_Id.
- */
- RegValue = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
-
- /*
- * The priority bits are Bits 7 to 3 in GIC Priority Register. This
- * means the number of priority levels supported are 32 and they are
- * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
- * The lower order 3 bits are masked before putting it in the register.
- */
- LocalPriority = LocalPriority & (u8)XSCUGIC_INTR_PRIO_MASK;
- /*
- * Shift and Mask the correct bits for the priority and trigger in the
- * register
- */
- RegValue &= ~((u32)XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
- RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
-
- /*
- * Write the value back to the register.
- */
- XScuGic_DistWriteReg(InstancePtr, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
- RegValue);
-
- /*
- * Determine the register to write to using the Int_Id.
- */
- RegValue = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id));
-
- /*
- * Shift and Mask the correct bits for the priority and trigger in the
- * register
- */
- RegValue &= ~((u32)XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
- RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
-
- /*
- * Write the value back to the register.
- */
- XScuGic_DistWriteReg(InstancePtr, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
- RegValue);
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-}
-
-/****************************************************************************/
-/**
-* Gets the interrupt priority and trigger type for the specificd IRQ source.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Int_Id is the IRQ source number to modify
-* @param Priority is a pointer to the value of the priority of the IRQ
-* source. This is a return value.
-* @param Trigger is pointer to the value of the trigger of the IRQ
-* source. This is a return value.
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
- u8 *Priority, u8 *Trigger)
-{
- u32 RegValue;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(Priority != NULL);
- Xil_AssertVoid(Trigger != NULL);
-
- /*
- * Determine the register to read to using the Int_Id.
- */
- RegValue = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
-
- /*
- * Shift and Mask the correct bits for the priority and trigger in the
- * register
- */
- RegValue = RegValue >> ((Int_Id%4U)*8U);
- *Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
-
- /*
- * Determine the register to read to using the Int_Id.
- */
- RegValue = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id));
-
- /*
- * Shift and Mask the correct bits for the priority and trigger in the
- * register
- */
- RegValue = RegValue >> ((Int_Id%16U)*2U);
-
- *Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
-}
-/****************************************************************************/
-/**
-* Sets the target CPU for the interrupt of a peripheral
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Cpu_Identifier is a CPU number for which the interrupt has to be targeted
-* @param Int_Id is the IRQ source number to modify
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Identifier, u32 Int_Id)
-{
- u32 RegValue;
-
-#if defined (GICv3)
- u32 Temp;
- Xil_AssertVoid(InstancePtr != NULL);
- if (Int_Id >= 32) {
- Temp = Int_Id - 32;
- RegValue = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_IROUTER_OFFSET_CALC(Temp));
- RegValue |= Cpu_Identifier;
- XScuGic_DistWriteReg(InstancePtr, XSCUGIC_IROUTER_OFFSET_CALC(Temp),
- (Cpu_Identifier-1));
- }
-#else
- u8 Cpu_CoreId;
- u32 Offset;
- Xil_AssertVoid(InstancePtr != NULL);
-
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
-
- RegValue = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
-
- Offset = (Int_Id & 0x3U);
- Cpu_CoreId = (0x1U << Cpu_Identifier);
-
- RegValue |= (u32)(Cpu_CoreId) << (Offset*8U);
- XScuGic_DistWriteReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
- RegValue);
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-#endif
-}
-/****************************************************************************/
-/**
-* Unmaps specific SPI interrupt from the target CPU
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Cpu_Identifier is a CPU number from which the interrupt has to be
-* unmapped
-* @param Int_Id is the IRQ source number to modify
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Identifier, u32 Int_Id)
-{
- u32 RegValue;
-
-#if defined (GICv3)
- u32 Temp;
- Xil_AssertVoid(InstancePtr != NULL);
- if (Int_Id >= 32) {
- Temp = Int_Id - 32;
- RegValue = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_IROUTER_OFFSET_CALC(Temp));
- RegValue &= ~Cpu_Identifier;
- XScuGic_DistWriteReg(InstancePtr, XSCUGIC_IROUTER_OFFSET_CALC(Temp),
- (Cpu_Identifier-1));
- }
-#else
- u32 Cpu_CoreId;
- u32 Offset;
- Xil_AssertVoid(InstancePtr != NULL);
-
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
-
- RegValue = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
-
- Offset = (Int_Id & 0x3U);
- Cpu_CoreId = ((u32)0x1U << Cpu_Identifier);
-
- RegValue &= ~(Cpu_CoreId << (Offset*8U));
- XScuGic_DistWriteReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
- RegValue);
-
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-#endif
-}
-/****************************************************************************/
-/**
-* Unmaps all SPI interrupts from the target CPU
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Cpu_Identifier is a CPU number from which the interrupts has to be
-* unmapped
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Identifier)
-{
- u32 Int_Id;
- u32 Target_Cpu;
- u32 LocalCpuID = ((u32)1U << Cpu_Identifier);
-
- Xil_AssertVoid(InstancePtr != NULL);
-
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
-
- LocalCpuID |= LocalCpuID << 8U;
- LocalCpuID |= LocalCpuID << 16U;
-
- for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
- Int_Id = Int_Id+4U) {
-
- Target_Cpu = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
- /* Remove LocalCpuID from interrupt target register */
- Target_Cpu &= (~LocalCpuID);
- XScuGic_DistWriteReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu);
-
- }
-
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-}
-/****************************************************************************/
-/**
-* It checks if the interrupt target register contains all interrupts to be
-* targeted for current CPU. If they are programmed to be forwarded to current
-* cpu, this API disable all interrupts and disable GIC distributor.
-* This API also removes current CPU from interrupt target registers for all
-* interrupt.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_Stop(XScuGic *InstancePtr)
-{
- u32 Int_Id;
- u32 RegValue;
- u32 Target_Cpu;
- #if (defined (USE_AMP) && (USE_AMP==1))
- u32 DistDisable = 0; /* Do not disable distributor */
- #else
- u32 DistDisable = 1; /* Track distributor status*/
- #endif
- u32 LocalCpuID = ((u32)0x1 << CpuId);
-
- Xil_AssertVoid(InstancePtr != NULL);
-
- /* If distributor is already disabled, no need to do anything */
- RegValue = XScuGic_DistReadReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET);
- if ((RegValue & XSCUGIC_EN_INT_MASK) == 0U) {
- return;
- }
-
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
-
- LocalCpuID |= LocalCpuID << 8U;
- LocalCpuID |= LocalCpuID << 16U;
-
- /*
- * Check if the interrupt are targeted to current cpu only or not.
- * Also remove current cpu from interrupt target register for all
- * interrupts.
- */
- for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
- Int_Id = Int_Id+4U) {
-
- Target_Cpu = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
- if ((Target_Cpu != LocalCpuID) && (Target_Cpu != (u32)0)) {
- /*
- * If any other CPU is also programmed to target
- * register, GIC distributor can not be disabled.
- */
- DistDisable = 0;
- }
-
- /* Remove current CPU from interrupt target register */
- Target_Cpu &= (~LocalCpuID);
- XScuGic_DistWriteReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu);
-
- }
-
- /*
- * If GIC distributor is safe to be disabled, disable all the interrupt
- * and then disable distributor.
- */
- if (DistDisable == (u32)1) {
- for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
- Int_Id = Int_Id+32U) {
- /*
- * Disable all the interrupts
- */
- XScuGic_DistWriteReg(InstancePtr,
- XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET,
- Int_Id),
- 0xFFFFFFFFU);
- }
- XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U);
- }
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-}
-
-/****************************************************************************/
-/**
-* This updates the CpuId global variable.
-*
-* @param CpuCoreId is the CPU core number.
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_SetCpuID(u32 CpuCoreId)
-{
- Xil_AssertVoid(CpuCoreId <= 1U);
-
- CpuId = CpuCoreId;
-}
-
-/****************************************************************************/
-/**
-* This function returns the CpuId variable.
-*
-* @return The CPU core number.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XScuGic_GetCpuID(void)
-{
- return CpuId;
-}
-
-#if defined (GICv3)
-/****************************************************************************/
-/**
-* It marks processor core which calls this API as asleep
-*
-* @return None.
-*
-* @note It should be called before suspending processor core. Once this
-* API is invoked, pending interrupts for processor core asserts
-* WakeRequest, to indicate that the PE is to have its power
-* restored In case of Versal SoC, WakeRequest will be consumed by
-* psv_psm processor and psmfw will wake up APU processor core.
-*
-*****************************************************************************/
-void XScuGic_MarkCoreAsleep(XScuGic *InstancePtr)
-{
- u32 Waker_State;
-
- Waker_State = XScuGic_ReDistReadReg(InstancePtr,XSCUGIC_RDIST_WAKER_OFFSET);
- XScuGic_ReDistWriteReg(InstancePtr,XSCUGIC_RDIST_WAKER_OFFSET,
- Waker_State |
- XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK);
-}
-
-/****************************************************************************/
-/**
-* It marks processor core which calls this API as awake
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_MarkCoreAwake(XScuGic *InstancePtr)
-{
- u32 Waker_State;
-
- Waker_State = XScuGic_ReDistReadReg(InstancePtr,
- XSCUGIC_RDIST_WAKER_OFFSET);
- XScuGic_ReDistWriteReg(InstancePtr,XSCUGIC_RDIST_WAKER_OFFSET,
- Waker_State &
- (~ XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK));
-}
-#endif
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/20/f06c005a5243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/20/f06c005a5243001d18b399c1eb9b3628
deleted file mode 100644
index acef5d8..0000000
Binary files a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/20/f06c005a5243001d18b399c1eb9b3628 and /dev/null differ
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/21/114e33585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/21/114e33585243001d18b399c1eb9b3628
deleted file mode 100644
index 8f62bbb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/21/114e33585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1711 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xsdps_host.c
-* @addtogroup sdps_v3_13
-* @{
-*
-* Contains the interface functions of the XSdPs driver.
-* See xsdps.h for a detailed description of the device and driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 3.9 mn 03/03/20 Restructured the code for more readability and modularity
-* mn 03/16/20 Add code to get card ID for MMC/eMMC
-* 3.10 mn 07/09/20 Modified code to prevent removing pull up on D3 line
-* mn 07/30/20 Read 16Bit value for Block Size Register
-* 3.11 sk 12/01/20 Tap programming sequence updates like disable OTAPEN
-* always, write zero to tap register for zero tap value.
-* sk 12/17/20 Removed checking platform specific SD macros and used
-* Baseaddress instead.
-* 3.13 sk 08/10/21 Limit the SD operating frequency to 19MHz for Versal.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xsdps_core.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-#if EL1_NONSECURE && defined (__aarch64__)
-void XSdps_Smc(XSdPs *InstancePtr, u32 RegOffset, u32 Mask, u32 Val)
-{
- (void)Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(InstancePtr->SlcrBaseAddr +
- RegOffset) | ((u64)Mask << 32),
- (u64)Val, 0, 0, 0, 0, 0);
-}
-#endif
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* Switches the SD card voltage from 3v3 to 1v8
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-******************************************************************************/
-s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr)
-{
- s32 Status;
-
- /* Setup the voltage switching sequence */
- Status = XSdPs_SetupVoltageSwitch(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Set the card voltage to 1.8V */
- Status = XSdPs_CardSetVoltage18(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Check if the bus is high */
- Status = XSdPs_CheckBusHigh(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function initiates the transfer to or from SD card.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure
-*
-******************************************************************************/
-s32 XSdPs_SetupTransfer(XSdPs *InstancePtr)
-{
- u32 PresentStateReg;
- s32 Status;
-
- if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
- ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
- != XSDPS_CAPS_EMB_SLOT)) {
- if(InstancePtr->Config.CardDetect != 0U) {
- /* Check status to ensure card is initialized */
- PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
- }
-
- /* Set block size to 512 if not already set */
- if(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
- Status = XSdPs_SetBlkSize(InstancePtr,
- XSDPS_BLK_SIZE_512_MASK);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function resets the SD card.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Value is the type of reset
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure
-*
-******************************************************************************/
-s32 XSdPs_Reset(XSdPs *InstancePtr, u8 Value)
-{
- s32 Status;
-
- /* "Software reset for all" is initiated */
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
- Value);
-
- Status = XSdPs_CheckResetDone(InstancePtr, Value);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function sets bit to start execution of tuning.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-void XSdPs_SetExecTuning(XSdPs *InstancePtr)
-{
- u16 CtrlReg;
-
- CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET);
- CtrlReg |= XSDPS_HC2_EXEC_TNG_MASK;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET, CtrlReg);
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function does SD mode initialization.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if initialization is successful
-* - XST_FAILURE if failure
-*
-******************************************************************************/
-s32 XSdPs_SdModeInit(XSdPs *InstancePtr)
-{
- s32 Status;
-#ifdef __ICCARM__
-#pragma data_alignment = 32
- static u8 SCR[8] = { 0U };
-#else
- static u8 SCR[8] __attribute__ ((aligned(32))) = { 0U };
-#endif
-#if SD_HS_MODE_ENABLE
- u8 ReadBuff[64] = { 0U };
-#endif
-
- Status = XSdPs_Get_BusWidth(InstancePtr, SCR);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if ((SCR[1] & WIDTH_4_BIT_SUPPORT) != 0U) {
- InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
- Status = XSdPs_Change_BusWidth(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
-#if SD_HS_MODE_ENABLE
- /* Get speed supported by device */
- Status = XSdPs_Get_BusSpeed(InstancePtr, ReadBuff);
- if (Status != XST_SUCCESS) {
- goto RETURN_PATH;
- }
-
- if (((SCR[2] & SCR_SPEC_VER_3) != 0U) &&
- (ReadBuff[13] >= UHS_SDR50_SUPPORT) &&
- (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8) &&
- (InstancePtr->Switch1v8 == 0U)) {
-
- InstancePtr->Switch1v8 = 1U;
-
- Status = XSdPs_CardSetVoltage18(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- if (InstancePtr->Switch1v8 != 0U) {
-
- /* Identify the UHS mode supported by card */
- XSdPs_Identify_UhsMode(InstancePtr, ReadBuff);
-
- Status = XSdPs_Change_BusSpeed(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } else {
- /*
- * card supports CMD6 when SD_SPEC field in SCR register
- * indicates that the Physical Layer Specification Version
- * is 1.10 or later. So for SD v1.0 cmd6 is not supported.
- */
- if (SCR[0] != 0U) {
- /* Check for high speed support */
- if (((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) &&
- (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
- InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
- InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD_HSD;
- InstancePtr->ITapDelay = SD_ITAPDLYSEL_HSD;
- Status = XSdPs_Change_BusSpeed(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
- }
- }
-#endif
-
- Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function does MMC mode initialization.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if initialization is successful
-* - XST_FAILURE if failure
-*
-******************************************************************************/
-s32 XSdPs_MmcModeInit(XSdPs *InstancePtr)
-{
- s32 Status;
-#ifdef __ICCARM__
-#pragma data_alignment = 32
- static u8 ExtCsd[512];
-#else
- static u8 ExtCsd[512] __attribute__ ((aligned(32)));
-#endif
-
- InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
- Status = XSdPs_Change_BusWidth(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24;
- InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16;
- InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8;
- InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1];
-
- if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
- EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) &&
- (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
- InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
- Status = XSdPs_Change_BusSpeed(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function does eMMC mode initialization.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if initialization is successful
-* - XST_FAILURE if failure
-*
-******************************************************************************/
-s32 XSdPs_EmmcModeInit(XSdPs *InstancePtr)
-{
- s32 Status;
-
-#ifdef __ICCARM__
-#pragma data_alignment = 32
- static u8 ExtCsd[512];
-#else
- static u8 ExtCsd[512] __attribute__ ((aligned(32)));
-#endif
-
- if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
- (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) {
- /* in case of eMMC data width 8-bit */
- InstancePtr->BusWidth = XSDPS_8_BIT_WIDTH;
- } else if (InstancePtr->Config.BusWidth == XSDPS_WIDTH_4) {
- /* in case of eMMC data width 4-bit */
- InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
- } else {
- /* in case of eMMC data width 1-bit */
- InstancePtr->BusWidth = XSDPS_1_BIT_WIDTH;
- }
-
- Status = XSdPs_Change_BusWidth(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Get Extended CSD */
- Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24;
- InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16;
- InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8;
- InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1];
-
- XSdPs_IdentifyEmmcMode(InstancePtr, ExtCsd);
-
- if (InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) {
- Status = XSdPs_Change_BusSpeed(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XSdPs_CheckEmmcTiming(InstancePtr, ExtCsd);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
- Status = XSdPs_Change_BusWidth(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
- }
-
- /* Enable Rst_n_Fun bit if it is disabled */
- if(ExtCsd[EXT_CSD_RST_N_FUN_BYTE] == EXT_CSD_RST_N_FUN_TEMP_DIS) {
- Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, XSDPS_MMC_RST_FUN_EN_ARG);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function disables the bus power.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-void XSdPs_DisableBusPower(XSdPs *InstancePtr)
-{
- /* Disable SD bus power and issue eMMC HW reset */
- if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_POWER_CTRL_OFFSET, XSDPS_PC_EMMC_HW_RST_MASK);
- } else {
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_POWER_CTRL_OFFSET, 0x0);
- }
-
- /* 1ms delay to poweroff card */
- (void)usleep(1000U);
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function enables the bus power.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-void XSdPs_EnableBusPower(XSdPs *InstancePtr)
-{
- /* Select voltage and enable bus power. */
- if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_POWER_CTRL_OFFSET,
- (XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK) &
- ~XSDPS_PC_EMMC_HW_RST_MASK);
- } else {
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_POWER_CTRL_OFFSET,
- XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK);
- }
-
- /* 0.2ms Delay after bus power on*/
- usleep(200);
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function enumerates the SD card.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_SdCardEnum(XSdPs *InstancePtr)
-{
- s32 Status;
-
- /* Check if the card is present */
- Status = XSdPs_CheckCardDetect(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Reset the SD card */
- Status = XSdPs_CardReset(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Get the card interface condition */
- Status = XSdPs_CardIfCond(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Get the card operating condition */
- Status = XSdPs_CardOpCond(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Get the card ID */
- Status = XSdPs_GetCardId(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Get the CSD register */
- Status = XSdPs_GetCsd(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Change clock to default clock 25MHz */
- /*
- * SD default speed mode timing should be closed at 19 MHz.
- * The reason for this is SD requires a voltage level shifter.
- * This limitation applies to ZynqMPSoC.
- */
- if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
- InstancePtr->BusSpeed = SD_CLK_19_MHZ;
- } else {
- InstancePtr->BusSpeed = SD_CLK_25_MHZ;
- }
- Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Select the card to transition to transfer state */
- Status = XSdPs_Select_Card(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function enumerates the MMC card.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_MmcCardEnum(XSdPs *InstancePtr)
-{
- s32 Status;
-
- /* Check if the card is preset */
- Status = XSdPs_CheckCardDetect(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Reset the card */
- Status = XSdPs_CardReset(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Get the card operating condition */
- Status = XSdPs_CardOpCond(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Get the card ID */
- Status = XSdPs_GetCardId(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Get the CSD register */
- Status = XSdPs_GetCsd(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Change clock to default clock 26MHz */
- InstancePtr->BusSpeed = SD_CLK_26_MHZ;
- Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Send select card command to transition to transfer state */
- Status = XSdPs_Select_Card(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function performs SD tuning.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
-{
- s32 Status;
-
-#ifndef versal
- /* Issue DLL Reset to load new SDHC tuned tap values */
- Status = XSdPs_DllReset(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
-#endif
-
- /* Perform the auto tuning */
- Status = XSdPs_AutoTuning(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
-#ifndef versal
- /* Issue DLL Reset to load new SDHC tuned tap values */
- Status = XSdPs_DllReset(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
-#endif
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to enable the clock.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param ClockReg is the clock value to be set.
-*
-* @return
-* - XST_SUCCESS if success
-* - XST_FAILURE if failure
-*
-******************************************************************************/
-s32 XSdPs_EnableClock(XSdPs *InstancePtr, u16 ClockReg)
-{
- u32 Timeout = 150000U;
- s32 Status;
- u16 ReadReg;
-
- ClockReg |= (u16)XSDPS_CC_INT_CLK_EN_MASK;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET, ClockReg);
-
- /* Wait for 150ms for internal clock to stabilize */
- do {
- ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- Timeout = Timeout - 1U;
- usleep(1);
- } while (((ReadReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U)
- && (Timeout != 0U));
-
- if (Timeout == 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- /* Enable SD clock */
- ClockReg |= XSDPS_CC_SD_CLK_EN_MASK;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET, ClockReg);
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to calculate the bus speed.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Arg is the argument to be sent along with the command.
-* This could be address or any other information
-*
-* @return
-* - XST_SUCCESS if success
-* - XST_FAILURE if failure
-*
-******************************************************************************/
-s32 XSdPs_CalcBusSpeed(XSdPs *InstancePtr, u32 *Arg)
-{
- s32 Status = XST_SUCCESS;
-
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
- switch (InstancePtr->Mode) {
- case XSDPS_UHS_SPEED_MODE_SDR12:
- *Arg = XSDPS_SWITCH_CMD_SDR12_SET;
- InstancePtr->BusSpeed = XSDPS_SD_SDR12_MAX_CLK;
- break;
- case XSDPS_UHS_SPEED_MODE_SDR25:
- *Arg = XSDPS_SWITCH_CMD_SDR25_SET;
- InstancePtr->BusSpeed = XSDPS_SD_SDR25_MAX_CLK;
- break;
- case XSDPS_UHS_SPEED_MODE_SDR50:
- *Arg = XSDPS_SWITCH_CMD_SDR50_SET;
- InstancePtr->BusSpeed = XSDPS_SD_SDR50_MAX_CLK;
- break;
- case XSDPS_UHS_SPEED_MODE_SDR104:
- *Arg = XSDPS_SWITCH_CMD_SDR104_SET;
- InstancePtr->BusSpeed = XSDPS_SD_SDR104_MAX_CLK;
- break;
- case XSDPS_UHS_SPEED_MODE_DDR50:
- *Arg = XSDPS_SWITCH_CMD_DDR50_SET;
- InstancePtr->BusSpeed = XSDPS_SD_DDR50_MAX_CLK;
- break;
- case XSDPS_HIGH_SPEED_MODE:
- *Arg = XSDPS_SWITCH_CMD_HS_SET;
- InstancePtr->BusSpeed = XSDPS_CLK_50_MHZ;
- break;
- default:
- Status = XST_FAILURE;
- break;
- }
- } else {
- switch (InstancePtr->Mode) {
- case XSDPS_HS200_MODE:
- *Arg = XSDPS_MMC_HS200_ARG;
- InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK;
- break;
- case XSDPS_DDR52_MODE:
- *Arg = XSDPS_MMC_HIGH_SPEED_ARG;
- InstancePtr->BusSpeed = XSDPS_MMC_DDR_MAX_CLK;
- break;
- case XSDPS_HIGH_SPEED_MODE:
- *Arg = XSDPS_MMC_HIGH_SPEED_ARG;
- InstancePtr->BusSpeed = XSDPS_MMC_HSD_MAX_CLK;
- break;
- default:
- Status = XST_FAILURE;
- break;
- }
- }
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to do the DMA transfer to or from SD card.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param BlkCnt - Block count passed by the user.
-* @param BlkSize - Block size passed by the user.
-* @param Buff - Pointer to the data buffer for a DMA transfer.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because another transfer
-* is in progress or command or data inhibit is set
-*
-******************************************************************************/
-void XSdPs_SetupReadDma(XSdPs *InstancePtr, u16 BlkCnt, u16 BlkSize, u8 *Buff)
-{
- BlkSize &= XSDPS_BLK_SIZE_MASK;
-
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_SIZE_OFFSET, BlkSize);
-
- if (InstancePtr->Dma64BitAddr >= ADDRESS_BEYOND_32BIT) {
- XSdPs_SetupADMA2DescTbl64Bit(InstancePtr, BlkCnt);
- } else {
- XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
- if (InstancePtr->Config.IsCacheCoherent == 0U) {
- Xil_DCacheInvalidateRange((INTPTR)Buff,
- (INTPTR)BlkCnt * BlkSize);
- }
- }
-
- if (BlkCnt == 1U) {
- InstancePtr->TransferMode = XSDPS_TM_BLK_CNT_EN_MASK |
- XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
- } else {
- InstancePtr->TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK |
- XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK |
- XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK;
- }
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to do the DMA transfer to or from SD card.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param BlkCnt - Block count passed by the user.
-* @param BlkSize - Block size passed by the user.
-* @param Buff - Pointer to the data buffer for a DMA transfer.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because another transfer
-* is in progress or command or data inhibit is set
-*
-******************************************************************************/
-void XSdPs_SetupWriteDma(XSdPs *InstancePtr, u16 BlkCnt, u16 BlkSize, const u8 *Buff)
-{
- BlkSize &= XSDPS_BLK_SIZE_MASK;
-
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_SIZE_OFFSET, BlkSize);
-
- if (InstancePtr->Dma64BitAddr >= ADDRESS_BEYOND_32BIT) {
- XSdPs_SetupADMA2DescTbl64Bit(InstancePtr, BlkCnt);
- } else {
- XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
- if (InstancePtr->Config.IsCacheCoherent == 0U) {
- Xil_DCacheFlushRange((INTPTR)Buff,
- (INTPTR)BlkCnt * BlkSize);
- }
- }
-
- if (BlkCnt == 1U) {
- InstancePtr->TransferMode = XSDPS_TM_BLK_CNT_EN_MASK |
- XSDPS_TM_DMA_EN_MASK;
- } else {
- InstancePtr->TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK |
- XSDPS_TM_BLK_CNT_EN_MASK |
- XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to setup ADMA2 descriptor table for 32-bit DMA
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param BlkCnt - block count.
-* @param Buff pointer to data buffer.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-void XSdPs_Setup32ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
-{
-#ifdef __ICCARM__
-#pragma data_alignment = 32
- static XSdPs_Adma2Descriptor32 Adma2_DescrTbl[32];
-#else
- static XSdPs_Adma2Descriptor32 Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
-#endif
- u32 TotalDescLines;
- u64 DescNum;
- u32 BlkSize;
-
- /* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */
- BlkSize = (u32)XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_SIZE_OFFSET) &
- XSDPS_BLK_SIZE_MASK;
-
- if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) {
- TotalDescLines = 1U;
- } else {
- TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH);
- if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) {
- TotalDescLines += 1U;
- }
- }
-
- for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) {
- Adma2_DescrTbl[DescNum].Address =
- (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
- Adma2_DescrTbl[DescNum].Attribute =
- XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
- Adma2_DescrTbl[DescNum].Length = 0U;
- }
-
- Adma2_DescrTbl[TotalDescLines-1].Address =
- (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
-
- Adma2_DescrTbl[TotalDescLines-1].Attribute =
- XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
-
- Adma2_DescrTbl[TotalDescLines-1].Length =
- (u16)((BlkCnt*BlkSize) - (u32)(DescNum*XSDPS_DESC_MAX_LENGTH));
-
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
- (u32)((UINTPTR)&(Adma2_DescrTbl[0]) & (u32)~0x0));
-
- if (InstancePtr->Config.IsCacheCoherent == 0U) {
- Xil_DCacheFlushRange((INTPTR)&(Adma2_DescrTbl[0]),
- sizeof(XSdPs_Adma2Descriptor32) * 32U);
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to setup ADMA2 descriptor table for 64-bit DMA
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param BlkCnt - block count.
-* @param Buff pointer to data buffer.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-void XSdPs_Setup64ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
-{
-#ifdef __ICCARM__
-#pragma data_alignment = 32
- static XSdPs_Adma2Descriptor64 Adma2_DescrTbl[32];
-#else
- static XSdPs_Adma2Descriptor64 Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
-#endif
- u32 TotalDescLines;
- u64 DescNum;
- u32 BlkSize;
-
- /* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */
- BlkSize = (u32)XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_SIZE_OFFSET) &
- XSDPS_BLK_SIZE_MASK;
-
- if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) {
- TotalDescLines = 1U;
- } else {
- TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH);
- if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) {
- TotalDescLines += 1U;
- }
- }
-
- for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) {
- Adma2_DescrTbl[DescNum].Address =
- ((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
- Adma2_DescrTbl[DescNum].Attribute =
- XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
- Adma2_DescrTbl[DescNum].Length = 0U;
- }
-
- Adma2_DescrTbl[TotalDescLines-1].Address =
- (u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
-
- Adma2_DescrTbl[TotalDescLines-1].Attribute =
- XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
-
- Adma2_DescrTbl[TotalDescLines-1].Length =
- (u16)((BlkCnt*BlkSize) - (u32)(DescNum*XSDPS_DESC_MAX_LENGTH));
-
-#if defined(__aarch64__) || defined(__arch64__)
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_EXT_OFFSET,
- (u32)((UINTPTR)(Adma2_DescrTbl)>>32U));
-#endif
-
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
- (u32)((UINTPTR)&(Adma2_DescrTbl[0]) & (u32)~0x0));
-
- if (InstancePtr->Config.IsCacheCoherent == 0U) {
- Xil_DCacheFlushRange((INTPTR)&(Adma2_DescrTbl[0]),
- sizeof(XSdPs_Adma2Descriptor64) * 32U);
- }
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used calculate the clock divisor value.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param SelFreq is the selected frequency
-*
-* @return Clock divisor value
-*
-******************************************************************************/
-u32 XSdPs_CalcClock(XSdPs *InstancePtr, u32 SelFreq)
-{
- u16 ClockVal = 0U;
- u16 DivCnt;
- u16 Divisor = 0U;
-
- if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
- /* Calculate divisor */
- for (DivCnt = 0x1U; DivCnt <= XSDPS_CC_EXT_MAX_DIV_CNT; DivCnt++) {
- if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
- Divisor = DivCnt >> 1;
- break;
- }
- }
- } else {
- /* Calculate divisor */
- for (DivCnt = 0x1U; DivCnt <= XSDPS_CC_MAX_DIV_CNT; DivCnt <<= 1U) {
- if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
- Divisor = DivCnt / 2U;
- break;
- }
- }
- }
-
- ClockVal |= (Divisor & XSDPS_CC_SDCLK_FREQ_SEL_MASK) << XSDPS_CC_DIV_SHIFT;
- ClockVal |= ((Divisor >> 8U) & XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK) << XSDPS_CC_EXT_DIV_SHIFT;
-
- return ClockVal;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to Set or Reset the DLL
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param EnRst is a flag indicating whether to Assert or De-assert Reset.
-*
-* @return None
-*
-* @note This API is specific to ZynqMP platform.
-*
-******************************************************************************/
-void XSdPs_DllRstCtrl(XSdPs *InstancePtr, u8 EnRst)
-{
-#ifndef versal
- u32 BaseAddress;
- u32 DllCtrl;
-
- BaseAddress = InstancePtr->Config.BaseAddress;
- if (BaseAddress == XSDPS_ZYNQMP_SD0_BASE) {
-#if EL1_NONSECURE && defined (__aarch64__)
- (void)DllCtrl;
-
- XSdps_Smc(InstancePtr, SD_DLL_CTRL, SD0_DLL_RST, (EnRst == 1U) ? SD0_DLL_RST : 0U);
-#else
- DllCtrl = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_DLL_CTRL);
- if (EnRst == 1U) {
- DllCtrl |= SD0_DLL_RST;
- } else {
- DllCtrl &= ~SD0_DLL_RST;
- }
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_DLL_CTRL, DllCtrl);
-#endif
- } else {
-#if EL1_NONSECURE && defined (__aarch64__)
- (void)DllCtrl;
-
- XSdps_Smc(InstancePtr, SD_DLL_CTRL, SD1_DLL_RST, (EnRst == 1U) ? SD1_DLL_RST : 0U);
-#else
- DllCtrl = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_DLL_CTRL);
- if (EnRst == 1U) {
- DllCtrl |= SD1_DLL_RST;
- } else {
- DllCtrl &= ~SD1_DLL_RST;
- }
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_DLL_CTRL, DllCtrl);
-#endif
- }
-#else
- (void)InstancePtr;
- (void)EnRst;
-#endif
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* Function to configure the Tap Delays.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-void XSdPs_ConfigTapDelay(XSdPs *InstancePtr)
-{
- u32 BaseAddress;
- u32 TapDelay;
- u32 ITapDelay;
- u32 OTapDelay;
-
- BaseAddress = InstancePtr->Config.BaseAddress;
- TapDelay = 0U;
- ITapDelay = InstancePtr->ITapDelay;
- OTapDelay = InstancePtr->OTapDelay;
-
-#ifdef versal
- (void) BaseAddress;
- if (ITapDelay) {
- TapDelay = SD_ITAPCHGWIN;
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_ITAPDLY, TapDelay);
- /* Program the ITAPDLY */
- TapDelay |= SD_ITAPDLYENA;
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_ITAPDLY, TapDelay);
- TapDelay |= ITapDelay;
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_ITAPDLY, TapDelay);
- TapDelay &= ~SD_ITAPCHGWIN;
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_ITAPDLY, TapDelay);
- } else {
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_ITAPDLY, 0x0);
- }
-
- /* Program the OTAPDLY */
- if (OTapDelay) {
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_OTAPDLY, OTapDelay);
- } else {
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_OTAPDLY, 0x0);
- }
-#else
- if (BaseAddress == XSDPS_ZYNQMP_SD0_BASE) {
-#if EL1_NONSECURE && defined (__aarch64__)
- (void)TapDelay;
- if (ITapDelay) {
- XSdps_Smc(InstancePtr, SD_ITAPDLY, SD0_ITAPCHGWIN, SD0_ITAPCHGWIN);
- XSdps_Smc(InstancePtr, SD_ITAPDLY, SD0_ITAPDLYENA, SD0_ITAPDLYENA);
- XSdps_Smc(InstancePtr, SD_ITAPDLY, SD0_ITAPDLY_SEL_MASK, ITapDelay);
- XSdps_Smc(InstancePtr, SD_ITAPDLY, SD0_ITAPCHGWIN, 0U);
- } else {
- XSdps_Smc(InstancePtr, SD_ITAPDLY, (SD0_ITAPDLY_SEL_MASK |
- SD0_ITAPCHGWIN | SD0_ITAPDLYENA), 0x0);
- }
- if (OTapDelay) {
- XSdps_Smc(InstancePtr, SD_OTAPDLY, SD0_OTAPDLY_SEL_MASK, OTapDelay);
- } else {
- XSdps_Smc(InstancePtr, SD_OTAPDLY, SD0_OTAPDLY_SEL_MASK, 0x0);
- }
-#else
- if (ITapDelay) {
- TapDelay = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY);
- TapDelay |= SD0_ITAPCHGWIN;
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay);
- /* Program the ITAPDLY */
- TapDelay |= SD0_ITAPDLYENA;
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay);
- TapDelay &= ~SD0_ITAPDLY_SEL_MASK;
- TapDelay |= ITapDelay;
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay);
- TapDelay &= ~SD0_ITAPCHGWIN;
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay);
- } else {
- TapDelay = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY);
- TapDelay &= ~(u32)(SD0_ITAPDLY_SEL_MASK | SD0_ITAPCHGWIN | SD0_ITAPDLYENA);
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay);
- }
- if (OTapDelay) {
- /* Program the OTAPDLY */
- TapDelay = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_OTAPDLY);
- TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
- TapDelay |= OTapDelay;
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_OTAPDLY, TapDelay);
- } else {
- TapDelay = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_OTAPDLY);
- TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_OTAPDLY, TapDelay);
- }
-#endif
- } else {
- ITapDelay = ITapDelay << 16U;
- OTapDelay = OTapDelay << 16U;
-#if EL1_NONSECURE && defined (__aarch64__)
- (void)TapDelay;
- if (ITapDelay) {
- XSdps_Smc(InstancePtr, SD_ITAPDLY, SD1_ITAPCHGWIN, SD1_ITAPCHGWIN);
- XSdps_Smc(InstancePtr, SD_ITAPDLY, SD1_ITAPDLYENA, SD1_ITAPDLYENA);
- XSdps_Smc(InstancePtr, SD_ITAPDLY, SD1_ITAPDLY_SEL_MASK, ITapDelay);
- XSdps_Smc(InstancePtr, SD_ITAPDLY, SD1_ITAPCHGWIN, 0U);
- } else {
- XSdps_Smc(InstancePtr, SD_ITAPDLY, (SD1_ITAPDLY_SEL_MASK |
- SD1_ITAPCHGWIN | SD1_ITAPDLYENA), 0x0);
- }
- if (OTapDelay) {
- XSdps_Smc(InstancePtr, SD_OTAPDLY, SD1_OTAPDLY_SEL_MASK, OTapDelay);
- } else {
- XSdps_Smc(InstancePtr, SD_OTAPDLY, SD1_OTAPDLY_SEL_MASK, 0x0);
- }
-#else
- if (ITapDelay) {
- TapDelay = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY);
- TapDelay |= SD1_ITAPCHGWIN;
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay);
- /* Program the ITAPDLY */
- TapDelay |= SD1_ITAPDLYENA;
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay);
- TapDelay &= ~SD1_ITAPDLY_SEL_MASK;
- TapDelay |= ITapDelay;
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay);
- TapDelay &= ~SD1_ITAPCHGWIN;
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay);
- } else {
- TapDelay = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY);
- TapDelay &= ~(u32)(SD1_ITAPDLY_SEL_MASK | SD1_ITAPCHGWIN | SD1_ITAPDLYENA);
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay);
- }
- if (OTapDelay) {
- /* Program the OTAPDLY */
- TapDelay = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_OTAPDLY);
- TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
- TapDelay |= OTapDelay;
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_OTAPDLY, TapDelay);
- } else {
- TapDelay = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_OTAPDLY);
- TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_OTAPDLY, TapDelay);
- }
-#endif
- }
-#endif /* versal */
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to set voltage to 1.8V.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if successful
-* - XST_FAILURE if failure
-*
-******************************************************************************/
-s32 XSdPs_SetVoltage18(XSdPs *InstancePtr)
-{
- s32 Status;
- u16 CtrlReg;
-
- /* Enabling 1.8V in controller */
- CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET);
- CtrlReg |= XSDPS_HC2_1V8_EN_MASK;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET,
- CtrlReg);
-
- /* Wait minimum 5mSec */
- (void)usleep(5000U);
-
- /* Check for 1.8V signal enable bit is cleared by Host */
- Status = XSdPs_CheckVoltage18(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used configure the Power Level.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-void XSdPs_ConfigPower(XSdPs *InstancePtr)
-{
- u8 PowerLevel;
-
- if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V3_MASK) != 0U) {
- PowerLevel = XSDPS_PC_BUS_VSEL_3V3_MASK;
- } else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V0_MASK) != 0U) {
- PowerLevel = XSDPS_PC_BUS_VSEL_3V0_MASK;
- } else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_1V8_MASK) != 0U) {
- PowerLevel = XSDPS_PC_BUS_VSEL_1V8_MASK;
- } else {
- PowerLevel = 0U;
- }
-
- /* Select voltage based on capability and enable bus power. */
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_POWER_CTRL_OFFSET,
- PowerLevel | XSDPS_PC_BUS_PWR_MASK);
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used configure the DMA.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-void XSdPs_ConfigDma(XSdPs *InstancePtr)
-{
- if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
- /* Enable ADMA2 in 64bit mode. */
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL1_OFFSET,
- XSDPS_HC_DMA_ADMA2_64_MASK);
- } else {
- /* Enable ADMA2 in 32bit mode. */
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL1_OFFSET,
- XSDPS_HC_DMA_ADMA2_32_MASK);
- }
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used configure the Interrupts.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-void XSdPs_ConfigInterrupt(XSdPs *InstancePtr)
-{
- /* Enable all interrupt status except card interrupt initially */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_EN_OFFSET,
- XSDPS_NORM_INTR_ALL_MASK & (~XSDPS_INTR_CARD_MASK));
-
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_EN_OFFSET,
- XSDPS_ERROR_INTR_ALL_MASK);
-
- /* Disable all interrupt signals by default. */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_SIG_EN_OFFSET, 0x0U);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_SIG_EN_OFFSET, 0x0U);
-
-}
-
-/*****************************************************************************/
-/**
-* This function does SD command generation.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Cmd is the command to be sent.
-* @param Arg is the argument to be sent along with the command.
-* This could be address or any other information
-* @param BlkCnt - Block count passed by the user.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because another transfer
-* is in progress or command or data inhibit is set
-*
-******************************************************************************/
-s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt)
-{
- u32 Timeout = 10000000U;
- u32 StatusReg;
- s32 Status;
-
- Status = XSdPs_SetupCmd(InstancePtr, Arg, BlkCnt);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XSdPs_SendCmd(InstancePtr, Cmd);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Polling for response for now */
- do {
- StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET);
- if ((Cmd == CMD21) || (Cmd == CMD19)) {
- if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET) & XSDPS_INTR_BRR_MASK) != 0U){
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_BRR_MASK);
- break;
- }
- }
-
- if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
- Status = (s32)XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET);
- if (((u32)Status & ~XSDPS_INTR_ERR_CT_MASK) == 0U) {
- Status = XSDPS_CT_ERROR;
- }
- /* Write to clear error bits */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET,
- XSDPS_ERROR_INTR_ALL_MASK);
- goto RETURN_PATH;
- }
- Timeout = Timeout - 1U;
- } while (((StatusReg & XSDPS_INTR_CC_MASK) == 0U)
- && (Timeout != 0U));
- /* Write to clear bit */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET,
- XSDPS_INTR_CC_MASK);
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-* This function is used to check if the transfer is completed successfully.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdps_CheckTransferDone(XSdPs *InstancePtr)
-{
- u32 Timeout = 5000000U;
- u16 StatusReg;
- s32 Status;
-
- /*
- * Check for transfer complete
- * Polling for response for now
- */
- do {
- StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET);
- if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
- /* Write to clear error bits */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET,
- XSDPS_ERROR_INTR_ALL_MASK);
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- Timeout = Timeout - 1U;
- usleep(1);
- } while (((StatusReg & XSDPS_INTR_TC_MASK) == 0U)
- && (Timeout != 0U));
-
- if (Timeout == 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- /* Write to clear bit */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to check if the CMD/DATA bus is idle or not.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Value is to selct Cmd bus or Dat bus
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_CheckBusIdle(XSdPs *InstancePtr, u32 Value)
-{
- u32 Timeout = 10000000U;
- u32 PresentStateReg;
- u32 StatusReg;
- s32 Status;
-
- PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- /* Check for Card Present */
- if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) != 0U) {
- /* Check for SD idle */
- do {
- StatusReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- Timeout = Timeout - 1;
- usleep(1);
- } while (((StatusReg & Value) != 0U)
- && (Timeout != 0U));
- }
-
- if (Timeout == 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function frames the Command register for a particular command.
-* Note that this generates only the command register value i.e.
-* the upper 16 bits of the transfer mode and command register.
-* This value is already shifted to be upper 16 bits and can be directly
-* OR'ed with transfer mode register value.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Cmd is the Command to be sent.
-*
-* @return Command register value complete with response type and
-* data, CRC and index related flags.
-*
-******************************************************************************/
-u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd)
-{
- u32 RetVal;
-
- RetVal = Cmd;
-
- switch(Cmd) {
- case CMD0:
- RetVal |= RESP_NONE;
- break;
- case CMD1:
- RetVal |= RESP_R3;
- break;
- case CMD2:
- RetVal |= RESP_R2;
- break;
- case CMD3:
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
- RetVal |= RESP_R6;
- } else {
- RetVal |= RESP_R1;
- }
- break;
- case CMD4:
- RetVal |= RESP_NONE;
- break;
- case CMD5:
- RetVal |= RESP_R1B;
- break;
- case CMD6:
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
- RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
- } else {
- RetVal |= RESP_R1B;
- }
- break;
- case ACMD6:
- RetVal |= RESP_R1;
- break;
- case CMD7:
- RetVal |= RESP_R1;
- break;
- case CMD8:
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
- RetVal |= RESP_R1;
- } else {
- RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
- }
- break;
- case CMD9:
- RetVal |= RESP_R2;
- break;
- case CMD11:
- case CMD10:
- case CMD12:
- RetVal |= RESP_R1;
- break;
- case ACMD13:
- RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
- break;
- case CMD16:
- RetVal |= RESP_R1;
- break;
- case CMD17:
- case CMD18:
- case CMD19:
- case CMD21:
- RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
- break;
- case CMD23:
- case ACMD23:
- case CMD24:
- case CMD25:
- RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
- break;
- case ACMD41:
- RetVal |= RESP_R3;
- break;
- case ACMD42:
- RetVal |= RESP_R1;
- break;
- case ACMD51:
- RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
- break;
- case CMD52:
- case CMD55:
- RetVal |= RESP_R1;
- break;
- case CMD58:
- break;
- default :
- RetVal |= Cmd;
- break;
- }
-
- return RetVal;
-}
-
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/21/115a43555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/21/115a43555243001d18b399c1eb9b3628
deleted file mode 100644
index 348ec47..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/21/115a43555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
-Copyright DornerWorks 2016
-
-Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-following conditions are met:
-1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
-following disclaimer.
-
-THIS SOFTWARE IS PROVIDED BY DORNERWORKS FOR USE ON THE CONTRACTED PROJECT, AND ANY EXPRESS OR IMPLIED WARRANTY
-IS LIMITED TO THIS USE. FOR ALL OTHER USES THIS SOFTWARE IS PROVIDED ''AS IS'' AND ANY EXPRESS OR IMPLIED
-WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL DORNERWORKS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-#ifndef _ARM64_OPS_H_
-#define _ARM64_OPS_H_
-#include
-
-#define BUG() while(1){asm volatile (".word 0xe7f000f0\n");} /* Undefined instruction; will call our fault handler. */
-#define ASSERT(x) \
-do { \
- if (!(x)) { \
- printk("ASSERTION FAILED: %s at %s:%d.\n", \
- # x , \
- __FILE__, \
- __LINE__); \
- BUG(); \
- } \
-} while(0)
-
-#define BUG_ON(x) ASSERT(!(x))
-
-#define smp_processor_id() 0
-
-#define barrier() __asm__ __volatile__("": : :"memory")
-
-// disable interrupts
-static inline void local_irq_disable(void) {
- __asm__ __volatile__("cpsid i":::"memory");
-}
-
-// enable interrupts
-static inline void local_irq_enable(void) {
- __asm__ __volatile__("cpsie i":::"memory");
-}
-
-#define local_irq_save(x) { \
- __asm__ __volatile__("mrs %0, cpsr;cpsid i":"=r"(x)::"memory"); \
-}
-
-#define local_irq_restore(x) { \
- __asm__ __volatile__("msr cpsr_c, %0"::"r"(x):"memory"); \
-}
-
-#define local_save_flags(x) { \
- __asm__ __volatile__("mrs %0, cpsr":"=r"(x)::"memory"); \
-}
-
-static inline int irqs_disabled(void) {
- int x;
- local_save_flags(x);
- return x & 0x80;
-}
-
-#define dsb(scope) asm volatile("dsb " #scope : : : "memory")
-
-/* We probably only need "dmb" here, but we'll start by being paranoid. */
-#define mb() dsb(sy)
-#define rmb() dsb(ld)
-#define wmb() dsb(st)
-
-#define xchg(ptr,v) __atomic_exchange_n(ptr, v, __ATOMIC_SEQ_CST)
-
-/**
- * test_and_clear_bit - Clear a bit and return its old value
- * @nr: Bit to clear
- * @addr: Address to count from
- *
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- *
- * This operation is atomic.
- * If you need a memory barrier, use synch_test_and_clear_bit instead.
- */
-static __inline__ int test_and_clear_bit(int nr, volatile void * addr)
-{
- uint8_t *byte = ((uint8_t *)addr) + (nr >> 3);
- uint8_t bit = 1 << (nr & 7);
- uint8_t orig;
-
- orig = __atomic_fetch_and(byte, ~bit, __ATOMIC_RELAXED);
-
- return (orig & bit) != 0;
-}
-
-/**
- * Atomically set a bit and return the old value.
- * Similar to test_and_clear_bit.
- */
-static __inline__ int test_and_set_bit(int nr, volatile void *base)
-{
- uint8_t *byte = ((uint8_t *)base) + (nr >> 3);
- uint8_t bit = 1 << (nr & 7);
- uint8_t orig;
-
- orig = __atomic_fetch_or(byte, bit, __ATOMIC_RELAXED);
-
- return (orig & bit) != 0;
-}
-
-/**
- * Test whether a bit is set. */
-static __inline__ int test_bit(int nr, const volatile unsigned long *addr)
-{
- const uint8_t *ptr = (const uint8_t *) addr;
- return ((1 << (nr & 7)) & (ptr[nr >> 3])) != 0;
-}
-
-/**
- * Atomically set a bit in memory (like test_and_set_bit but discards result).
- */
-static __inline__ void set_bit(int nr, volatile unsigned long *addr)
-{
- test_and_set_bit(nr, addr);
-}
-
-/**
- * Atomically clear a bit in memory (like test_and_clear_bit but discards result).
- */
-static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
-{
- test_and_clear_bit(nr, addr);
-}
-
-/**
- * __ffs - find first (lowest) set bit in word.
- * @word: The word to search
- *
- * Undefined if no bit exists, so code should check against 0 first.
- */
-static __inline__ unsigned long __ffs(unsigned long word)
-{
- return __builtin_ctzl(word);
-}
-
-
-
-/********************* common arm32 and arm64 ****************************/
-
-/* If *ptr == old, then store new there (and return new).
- * Otherwise, return the old value.
- * Atomic. */
-#define synch_cmpxchg(ptr, old, new) \
-({ __typeof__(*ptr) stored = old; \
- __atomic_compare_exchange_n(ptr, &stored, new, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST) ? new : old; \
-})
-
-/* As test_and_clear_bit, but using __ATOMIC_SEQ_CST */
-static __inline__ int synch_test_and_clear_bit(int nr, volatile void *addr)
-{
- uint8_t *byte = ((uint8_t *)addr) + (nr >> 3);
- uint8_t bit = 1 << (nr & 7);
- uint8_t orig;
-
- orig = __atomic_fetch_and(byte, ~bit, __ATOMIC_SEQ_CST);
-
- return (orig & bit) != 0;
-}
-
-/* As test_and_set_bit, but using __ATOMIC_SEQ_CST */
-static __inline__ int synch_test_and_set_bit(int nr, volatile void *base)
-{
- uint8_t *byte = ((uint8_t *)base) + (nr >> 3);
- uint8_t bit = 1 << (nr & 7);
- uint8_t orig;
-
- orig = __atomic_fetch_or(byte, bit, __ATOMIC_SEQ_CST);
-
- return (orig & bit) != 0;
-}
-
-/* As set_bit, but using __ATOMIC_SEQ_CST */
-static __inline__ void synch_set_bit(int nr, volatile void *addr)
-{
- synch_test_and_set_bit(nr, addr);
-}
-
-/* As clear_bit, but using __ATOMIC_SEQ_CST */
-static __inline__ void synch_clear_bit(int nr, volatile void *addr)
-{
- synch_test_and_clear_bit(nr, addr);
-}
-
-/* As test_bit, but with a following memory barrier. */
-static __inline__ int synch_test_bit(int nr, volatile void *addr)
-{
- int result;
- result = test_bit(nr, addr);
- barrier();
- return result;
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/21/311098525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/21/311098525243001d18b399c1eb9b3628
deleted file mode 100644
index d039278..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/21/311098525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,267 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xdmaps_hw.h
-* @addtogroup dmaps_v2_8
-* @{
-*
-* This header file contains the hardware interface of an XDmaPs device.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ----------------------------------------------
-* 1.00a hbm 08/18/10 First Release
-* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
-* the maximum number of channels.
-* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
-* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
-* 1.02a sg 05/16/12 Made changes for doxygen
-* 1.06a kpc 07/10/13 Added function prototype
-*
-*
-******************************************************************************/
-
-#ifndef XDMAPS_HW_H /* prevent circular inclusions */
-#define XDMAPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets for the DMAC.
- * @{
- */
-
-#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */
-#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */
-#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */
-#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */
-#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register
- */
-#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */
-#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager
- * Register
- */
-#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register
- */
-#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */
-
-#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */
-/*
- * The offset for the rest of the FTC registers is calculated as
- * FTC0 + dev_chan_num * 4
- */
-#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4)
-
-#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */
-/*
- * The offset for the rest of the CS registers is calculated as
- * CS0 + * dev_chan_num * 0x08
- */
-#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8)
-
-#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA
- * Channel 0
- */
-/*
- * The offset for the rest of the CPC registers is calculated as
- * CPC0 + dev_chan_num * 0x08
- */
-#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8)
-
-#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA
- * Channel 0
- */
-/* The offset for the rest of the SA registers is calculated as
- * SA_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for
- * DMA Channel 0
- */
-/* The offset for the rest of the DA registers is calculated as
- * DA_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for
- * DMA Channel 0
- */
-/*
- * The offset for the rest of the CC registers is calculated as
- * CC_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */
-/*
- * The offset for the rest of the LC0 registers is calculated as
- * LC_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20)
-#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */
-/*
- * The offset for the rest of the LC1 registers is calculated as
- * LC_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */
-#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */
-#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */
-#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */
-
-#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */
-#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */
-#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */
-#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */
-#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */
-#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */
-
-#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification
- * Register 0
- */
-#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification
- * Register 1
- */
-#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification
- * Register 2
- */
-#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification
- * Register 3
- */
-#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification
- * Register 0
- */
-#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification
- * Register 1
- */
-#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification
- * Register 2
- */
-#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification
- * Register 3
- */
-
-/*
- * Some useful register masks
- */
-#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */
-#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */
-
-#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */
-
-#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask,
- * llast 3 bits of CS register
- */
-
-#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */
-
-
-/*
- * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register.
- * @b1: Instruction byte 1
- * @b0: Instruction byte 0
- * @ch: Channel number
- * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel
- */
-#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \
- (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1)))
-
-/* @} */
-
-/** @name Control Register
- *
- * The Control register (CR) controls the major functions of the device.
- *
- * Control Register Bit Definition
- */
-
-/* @}*/
-
-
-#define XDMAPS_CHANNELS_PER_DEV 8
-
-
-/** @name Mode Register
- *
- * The mode register (MR) defines the mode of transfer as well as the data
- * format. If this register is modified during transmission or reception,
- * data validity cannot be guaranteed.
- *
- * Mode Register Bit Definition
- * @{
- */
-
-/* @} */
-
-
-/** @name Interrupt Registers
- *
- * Interrupt control logic uses the interrupt enable register (IER) and the
- * interrupt disable register (IDR) to set the value of the bits in the
- * interrupt mask register (IMR). The IMR determines whether to pass an
- * interrupt to the interrupt status register (ISR).
- * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
- * interrupt. IMR and ISR are read only, and IER and IDR are write only.
- * Reading either IER or IDR returns 0x00.
- *
- * All four registers have the same bit definitions.
- *
- * @{
- */
-
-/* @} */
-#define XDMAPS_INTCLR_ALL_MASK 0xFF
-
-#define XDmaPs_ReadReg(BaseAddress, RegOffset) \
- Xil_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write a DMAC register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the base address of the device.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note
-* C-Style signature:
-* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u32 RegisterValue)
-******************************************************************************/
-#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes *****************************/
-/*
- * Perform reset operation to the dmaps interface
- */
-void XDmaPs_ResetHw(u32 BaseAddr);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/21/602b18555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/21/602b18555243001d18b399c1eb9b3628
deleted file mode 100644
index 3eee8cc..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/21/602b18555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,41 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache_l.h
-*
-* Contains L1 and L2 specific functions for the ARM cache functionality
-* used by xcache.c. This functionality is being made available here for
-* more sophisticated users.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 01/24/10 First release
-*
-*
-******************************************************************************/
-#ifndef XIL_CACHE_MACH_H
-#define XIL_CACHE_MACH_H
-
-#include "xil_types.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Function Prototypes ******************************/
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/21/606ac3565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/21/606ac3565243001d18b399c1eb9b3628
deleted file mode 100644
index 27b3df1..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/21/606ac3565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,105 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#ifndef PROFILE_H
-#define PROFILE_H 1
-
-#include
-#include "xil_types.h"
-#include "profile_config.h"
-
-#ifdef PROC_MICROBLAZE
-#include "mblaze_nt_types.h"
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void _system_init( void ) ;
-void _system_clean( void ) ;
-void mcount(u32 frompc, u32 selfpc);
-void profile_intr_handler( void ) ;
-void _profile_init( void );
-
-
-
-/****************************************************************************
- * Profiling on hardware - Hash table maintained on hardware and data sent
- * to xmd for gmon.out generation.
- ****************************************************************************/
-/*
- * histogram counters are unsigned shorts (according to the kernel).
- */
-#define HISTCOUNTER u16
-
-struct tostruct {
- u32 selfpc;
- s32 count;
- s16 link;
- u16 pad;
-};
-
-struct fromstruct {
- u32 frompc ;
- s16 link ;
- u16 pad ;
-} ;
-
-/*
- * general rounding functions.
- */
-#define ROUNDDOWN(x,y) (((x)/(y))*(y))
-#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y))
-
-/*
- * The profiling data structures are housed in this structure.
- */
-struct gmonparam {
- s32 state;
-
- /* Histogram Information */
- u16 *kcount; /* No. of bins in histogram */
- u32 kcountsize; /* Histogram samples */
-
- /* Call-graph Information */
- struct fromstruct *froms;
- u32 fromssize;
- struct tostruct *tos;
- u32 tossize;
-
- /* Initialization I/Ps */
- u32 lowpc;
- u32 highpc;
- u32 textsize;
- /* u32 cg_froms, */
- /* u32 cg_tos, */
-};
-extern struct gmonparam *_gmonparam;
-extern s32 n_gmon_sections;
-
-/*
- * Possible states of profiling.
- */
-#define GMON_PROF_ON 0
-#define GMON_PROF_BUSY 1
-#define GMON_PROF_ERROR 2
-#define GMON_PROF_OFF 3
-
-/*
- * Sysctl definitions for extracting profiling information from the kernel.
- */
-#define GPROF_STATE 0 /* int: profiling enabling variable */
-#define GPROF_COUNT 1 /* struct: profile tick count buffer */
-#define GPROF_FROMS 2 /* struct: from location hash bucket */
-#define GPROF_TOS 3 /* struct: destination/count structure */
-#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PROFILE_H */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/21/b0341f595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/21/b0341f595243001d18b399c1eb9b3628
deleted file mode 100644
index 7754298..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/21/b0341f595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,54 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_mmu.h
-* This file only includes xil_mpu.h which contains Xil_SetTlbAttributes API
-* defined for MPU in R5. R5 does not have mmu and for usage of similar API
-* the file has been created.
-*
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.0 pkp 2/12/15 Initial version
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#ifndef XIL_MMU_H
-#define XIL_MMU_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/***************************** Include Files *********************************/
-
-#include "xil_mpu.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_MMU_H */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/21/c0fc25575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/21/c0fc25575243001d18b399c1eb9b3628
deleted file mode 100644
index 980f394..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/21/c0fc25575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,571 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xadcps.h
-* @addtogroup xadcps_v2_6
-* @{
-* @details
-*
-* The XAdcPs driver supports the Xilinx XADC/ADC device.
-*
-* The XADC/ADC device has the following features:
-* - 10-bit, 200-KSPS (kilo samples per second)
-* Analog-to-Digital Converter (ADC)
-* - Monitoring of on-chip supply voltages and temperature
-* - 1 dedicated differential analog-input pair and
-* 16 auxiliary differential analog-input pairs
-* - Automatic alarms based on user defined limits for the on-chip
-* supply voltages and temperature
-* - Automatic Channel Sequencer, programmable averaging, programmable
-* acquisition time for the external inputs, unipolar or differential
-* input selection for the external inputs
-* - Inbuilt Calibration
-* - Optional interrupt request generation
-*
-*
-* The user should refer to the hardware device specification for detailed
-* information about the device.
-*
-* This header file contains the prototypes of driver functions that can
-* be used to access the XADC/ADC device.
-*
-*
-* XADC Channel Sequencer Modes
-*
-* The XADC Channel Sequencer supports the following operating modes:
-*
-* - Default : This is the default mode after power up.
-* In this mode of operation the XADC operates in
-* a sequence mode, monitoring the on chip sensors:
-* Temperature, VCCINT, and VCCAUX.
-* - One pass through sequence : In this mode the XADC
-* converts the channels enabled in the Sequencer Channel Enable
-* registers for a single pass and then stops.
-* - Continuous cycling of sequence : In this mode the XADC
-* converts the channels enabled in the Sequencer Channel Enable
-* registers continuously.
-* - Single channel mode: In this mode the XADC Channel
-* Sequencer is disabled and the XADC operates in a
-* Single Channel Mode.
-* The XADC can operate either in a Continuous or Event
-* driven sampling mode in the single channel mode.
-* - Simultaneous Sampling Mode: In this mode the XADC Channel
-* Sequencer will automatically sequence through eight fixed pairs
-* of auxiliary analog input channels for simulataneous conversion.
-* - Independent ADC mode: In this mode the first ADC (A) is used to
-* is used to implement a fixed monitoring mode similar to the
-* default mode but the alarm fucntions ar eenabled.
-* The second ADC (B) is available to be used with external analog
-* input channels only.
-*
-* Read the XADC spec for more information about the sequencer modes.
-*
-* Initialization and Configuration
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate to the XADC/ADC device.
-*
-* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC
-* device. The user needs to first call the XAdcPs_LookupConfig() API which
-* returns the Configuration structure pointer which is passed as a parameter to
-* the XAdcPs_CfgInitialize() API.
-*
-*
-* Interrupts
-*
-* The XADC/ADC device supports interrupt driven mode and the default
-* operation mode is polling mode.
-*
-* The interrupt mode is available only if hardware is configured to support
-* interrupts.
-*
-* This driver does not provide a Interrupt Service Routine (ISR) for the device.
-* It is the responsibility of the application to provide one if needed. Refer to
-* the interrupt example provided with this driver for details on using the
-* device in interrupt mode.
-*
-*
-* Virtual Memory
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-*
-* Threads
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-*
-* Asserts
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-*
-* Building the driver
-*
-* The XAdcPs driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-* Limitations of the driver
-*
-* XADC/ADC device can be accessed through the JTAG port and the PLB
-* interface. The driver implementation does not support the simultaneous access
-* of the device by both these interfaces. The user has to care of this situation
-* in the user application code.
-*
-*
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
-* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
-* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
-* in xadcps.c to fix CR #693371
-* 1.03a bss 11/01/13 Modified xadcps_hw.h to use correct Register offsets
-* CR#749687
-* 2.1 bss 08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
-* XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
-* XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
-* functions.
-* Modified Assert for XAdcPs_SetSingleChParams in
-* xadcps.c to fix CR #807563.
-* 2.2 bss 04/27/14 Modified to use correct Device Config base address in
-* xadcps.c (CR#854437).
-* ms 01/23/17 Added xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/05/17 Modified Comment lines in functions of xadcps
-* examples to recognize it as documentation block
-* for doxygen generation.
-* 2.3 mn 07/09/18 Fix Doxygen warning
-* 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors.
-* aad 12/17/20 Added missing function declarations and removed
-* functions with no definitions.
-*
-*
-*
-*****************************************************************************/
-#ifndef XADCPS_H /* Prevent circular inclusions */
-#define XADCPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xadcps_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**
- * @name Indexes for the different channels.
- * @{
- */
-#define XADCPS_CH_TEMP 0x0U /**< On Chip Temperature */
-#define XADCPS_CH_VCCINT 0x1U /**< VCCINT */
-#define XADCPS_CH_VCCAUX 0x2U /**< VCCAUX */
-#define XADCPS_CH_VPVN 0x3U /**< VP/VN Dedicated analog inputs */
-#define XADCPS_CH_VREFP 0x4U /**< VREFP */
-#define XADCPS_CH_VREFN 0x5U /**< VREFN */
-#define XADCPS_CH_VBRAM 0x6U /**< On-chip VBRAM Data Reg, 7 series */
-#define XADCPS_CH_SUPPLY_CALIB 0x07U /**< Supply Calib Data Reg */
-#define XADCPS_CH_ADC_CALIB 0x08U /**< ADC Offset Channel Reg */
-#define XADCPS_CH_GAINERR_CALIB 0x09U /**< Gain Error Channel Reg */
-#define XADCPS_CH_VCCPINT 0x0DU /**< On-chip PS VCCPINT Channel , Zynq */
-#define XADCPS_CH_VCCPAUX 0x0EU /**< On-chip PS VCCPAUX Channel , Zynq */
-#define XADCPS_CH_VCCPDRO 0x0FU /**< On-chip PS VCCPDRO Channel , Zynq */
-#define XADCPS_CH_AUX_MIN 16U /**< Channel number for 1st Aux Channel */
-#define XADCPS_CH_AUX_MAX 31U /**< Channel number for Last Aux channel */
-
-/*@}*/
-
-
-/**
- * @name Indexes for reading the Calibration Coefficient Data.
- * @{
- */
-#define XADCPS_CALIB_SUPPLY_COEFF 0U /**< Supply Offset Calib Coefficient */
-#define XADCPS_CALIB_ADC_COEFF 1U /**< ADC Offset Calib Coefficient */
-#define XADCPS_CALIB_GAIN_ERROR_COEFF 2U /**< Gain Error Calib Coefficient*/
-/*@}*/
-
-
-/**
- * @name Indexes for reading the Minimum/Maximum Measurement Data.
- * @{
- */
-#define XADCPS_MAX_TEMP 0U /**< Maximum Temperature Data */
-#define XADCPS_MAX_VCCINT 1U /**< Maximum VCCINT Data */
-#define XADCPS_MAX_VCCAUX 2U /**< Maximum VCCAUX Data */
-#define XADCPS_MAX_VBRAM 3U /**< Maximum VBRAM Data */
-#define XADCPS_MIN_TEMP 4U /**< Minimum Temperature Data */
-#define XADCPS_MIN_VCCINT 5U /**< Minimum VCCINT Data */
-#define XADCPS_MIN_VCCAUX 6U /**< Minimum VCCAUX Data */
-#define XADCPS_MIN_VBRAM 7U /**< Minimum VBRAM Data */
-#define XADCPS_MAX_VCCPINT 8U /**< Maximum VCCPINT Register , Zynq */
-#define XADCPS_MAX_VCCPAUX 9U /**< Maximum VCCPAUX Register , Zynq */
-#define XADCPS_MAX_VCCPDRO 0xAU /**< Maximum VCCPDRO Register , Zynq */
-#define XADCPS_MIN_VCCPINT 0xCU /**< Minimum VCCPINT Register , Zynq */
-#define XADCPS_MIN_VCCPAUX 0xDU /**< Minimum VCCPAUX Register , Zynq */
-#define XADCPS_MIN_VCCPDRO 0xEU /**< Minimum VCCPDRO Register , Zynq */
-
-/*@}*/
-
-
-/**
- * @name Alarm Threshold(Limit) Register (ATR) indexes.
- * @{
- */
-#define XADCPS_ATR_TEMP_UPPER 0U /**< High user Temperature */
-#define XADCPS_ATR_VCCINT_UPPER 1U /**< VCCINT high voltage limit register */
-#define XADCPS_ATR_VCCAUX_UPPER 2U /**< VCCAUX high voltage limit register */
-#define XADCPS_ATR_OT_UPPER 3U /**< VCCAUX high voltage limit register */
-#define XADCPS_ATR_TEMP_LOWER 4U /**< Upper Over Temperature limit Reg */
-#define XADCPS_ATR_VCCINT_LOWER 5U /**< VCCINT high voltage limit register */
-#define XADCPS_ATR_VCCAUX_LOWER 6U /**< VCCAUX low voltage limit register */
-#define XADCPS_ATR_OT_LOWER 7U /**< Lower Over Temperature limit */
-#define XADCPS_ATR_VBRAM_UPPER_ 8U /**< VRBAM Upper Alarm Reg, 7 Series */
-#define XADCPS_ATR_VCCPINT_UPPER 9U /**< VCCPINT Upper Alarm Reg, Zynq */
-#define XADCPS_ATR_VCCPAUX_UPPER 0xAU /**< VCCPAUX Upper Alarm Reg, Zynq */
-#define XADCPS_ATR_VCCPDRO_UPPER 0xBU /**< VCCPDRO Upper Alarm Reg, Zynq */
-#define XADCPS_ATR_VBRAM_LOWER 0xCU /**< VRBAM Lower Alarm Reg, 7 Series */
-#define XADCPS_ATR_VCCPINT_LOWER 0xDU /**< VCCPINT Lower Alarm Reg , Zynq */
-#define XADCPS_ATR_VCCPAUX_LOWER 0xEU /**< VCCPAUX Lower Alarm Reg , Zynq */
-#define XADCPS_ATR_VCCPDRO_LOWER 0xFU /**< VCCPDRO Lower Alarm Reg , Zynq */
-
-/*@}*/
-
-
-/**
- * @name Averaging to be done for the channels.
- * @{
- */
-#define XADCPS_AVG_0_SAMPLES 0U /**< No Averaging */
-#define XADCPS_AVG_16_SAMPLES 1U /**< Average 16 samples */
-#define XADCPS_AVG_64_SAMPLES 2U /**< Average 64 samples */
-#define XADCPS_AVG_256_SAMPLES 3U /**< Average 256 samples */
-
-/*@}*/
-
-
-/**
- * @name Channel Sequencer Modes of operation
- * @{
- */
-#define XADCPS_SEQ_MODE_SAFE 0U /**< Default Safe Mode */
-#define XADCPS_SEQ_MODE_ONEPASS 1U /**< Onepass through Sequencer */
-#define XADCPS_SEQ_MODE_CONTINPASS 2U /**< Continuous Cycling Sequencer */
-#define XADCPS_SEQ_MODE_SINGCHAN 3U /**< Single channel -No Sequencing */
-#define XADCPS_SEQ_MODE_SIMUL_SAMPLING 4U /**< Simultaneous sampling */
-#define XADCPS_SEQ_MODE_INDEPENDENT 8U /**< Independent mode */
-
-/*@}*/
-
-
-
-/**
- * @name Power Down Modes
- * @{
- */
-#define XADCPS_PD_MODE_NONE 0U /**< No Power Down */
-#define XADCPS_PD_MODE_ADCB 1U /**< Power Down ADC B */
-#define XADCPS_PD_MODE_XADC 2U /**< Power Down ADC A and ADC B */
-/*@}*/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the XADC/ADC
- * device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Device base address */
-} XAdcPs_Config;
-
-
-/**
- * The driver's instance data. The user is required to allocate a variable
- * of this type for every XADC/ADC device in the system. A pointer to
- * a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XAdcPs_Config Config; /**< XAdcPs_Config of current device */
- u32 IsReady; /**< Device is initialized and ready */
-
-} XAdcPs;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-*
-* This macro checks if the XADC device is in Event Sampling mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return
-* - TRUE if the device is in Event Sampling Mode.
-* - FALSE if the device is in Continuous Sampling Mode.
-*
-* @note C-Style signature:
-* int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);
-*
-*****************************************************************************/
-#define XAdcPs_IsEventSamplingModeSet(InstancePtr) \
- (((XAdcPs_ReadInternalReg(InstancePtr, \
- XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ? \
- TRUE : FALSE))
-
-
-/****************************************************************************/
-/**
-*
-* This macro checks if the XADC device is in External Mux mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return
-* - TRUE if the device is in External Mux Mode.
-* - FALSE if the device is NOT in External Mux Mode.
-*
-* @note C-Style signature:
-* int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);
-*
-*****************************************************************************/
-#define XAdcPs_IsExternalMuxModeSet(InstancePtr) \
- (((XAdcPs_ReadInternalReg(InstancePtr, \
- XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ? \
- TRUE : FALSE))
-
-/****************************************************************************/
-/**
-*
-* This macro converts XADC Raw Data to Temperature(centigrades).
-*
-* @param AdcData is the Raw ADC Data from XADC.
-*
-* @return The Temperature in centigrades.
-*
-* @note C-Style signature:
-* float XAdcPs_RawToTemperature(u32 AdcData);
-*
-*****************************************************************************/
-#define XAdcPs_RawToTemperature(AdcData) \
- ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
-
-/****************************************************************************/
-/**
-*
-* This macro converts XADC/ADC Raw Data to Voltage(volts).
-*
-* @param AdcData is the XADC/ADC Raw Data.
-*
-* @return The Voltage in volts.
-*
-* @note C-Style signature:
-* float XAdcPs_RawToVoltage(u32 AdcData);
-*
-*****************************************************************************/
-#define XAdcPs_RawToVoltage(AdcData) \
- ((((float)(AdcData))* (3.0f))/65536.0f)
-
-/****************************************************************************/
-/**
-*
-* This macro converts Temperature in centigrades to XADC/ADC Raw Data.
-*
-* @param Temperature is the Temperature in centigrades to be
-* converted to XADC/ADC Raw Data.
-*
-* @return The XADC/ADC Raw Data.
-*
-* @note C-Style signature:
-* int XAdcPs_TemperatureToRaw(float Temperature);
-*
-*****************************************************************************/
-#define XAdcPs_TemperatureToRaw(Temperature) \
- ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
-
-/****************************************************************************/
-/**
-*
-* This macro converts Voltage in Volts to XADC/ADC Raw Data.
-*
-* @param Voltage is the Voltage in volts to be converted to
-* XADC/ADC Raw Data.
-*
-* @return The XADC/ADC Raw Data.
-*
-* @note C-Style signature:
-* int XAdcPs_VoltageToRaw(float Voltage);
-*
-*****************************************************************************/
-#define XAdcPs_VoltageToRaw(Voltage) \
- ((int)((Voltage)*65536.0f/3.0f))
-
-
-/****************************************************************************/
-/**
-*
-* This macro is used for writing to the XADC Registers using the
-* command FIFO.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Data is the value to be written to XADC register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);
-*
-*****************************************************************************/
-#define XAdcPs_WriteFifo(InstancePtr, Data) \
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XADCPS_CMDFIFO_OFFSET, Data);
-
-
-/****************************************************************************/
-/**
-*
-* This macro is used for reading from the XADC Registers using the
-* data FIFO.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return Data read from the FIFO
-*
-* @note C-Style signature:
-* u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);
-*
-*****************************************************************************/
-#define XAdcPs_ReadFifo(InstancePtr) \
- XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XADCPS_RDFIFO_OFFSET);
-
-
-/************************** Function Prototypes *****************************/
-
-
-
-/**
- * Functions in xadcps_sinit.c
- */
-XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
-
-/**
- * Functions in xadcps.c
- */
-int XAdcPs_CfgInitialize(XAdcPs *InstancePtr,
- XAdcPs_Config *ConfigPtr,
- u32 EffectiveAddr);
-
-void XAdcPs_SetConfigRegister(XAdcPs *InstancePtr, u32 Data);
-u32 XAdcPs_GetConfigRegister(XAdcPs *InstancePtr);
-
-u32 XAdcPs_GetMiscStatus(XAdcPs *InstancePtr);
-
-void XAdcPs_SetMiscCtrlRegister(XAdcPs *InstancePtr, u32 Data);
-u32 XAdcPs_GetMiscCtrlRegister(XAdcPs *InstancePtr);
-
-void XAdcPs_Reset(XAdcPs *InstancePtr);
-
-u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel);
-
-u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType);
-
-u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType);
-
-void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average);
-u8 XAdcPs_GetAvg(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
- u8 Channel,
- int IncreaseAcqCycles,
- int IsEventMode,
- int IsDifferentialMode);
-
-
-void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask);
-u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr);
-
-void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration);
-u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr);
-
-void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode);
-u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr);
-
-void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor);
-u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask);
-u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask);
-u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask);
-u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask);
-u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr);
-
-void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value);
-u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg);
-
-void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr);
-void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr);
-
-void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode);
-
-int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr);
-
-void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel);
-
-void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode);
-
-u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr);
-
-/**
- * Functions in xadcps_selftest.c
- */
-int XAdcPs_SelfTest(XAdcPs *InstancePtr);
-
-/**
- * Functions in xadcps_intr.c
- */
-void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask);
-void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask);
-u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr);
-
-u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr);
-void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* End of protection macro. */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/22/7124d8595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/22/7124d8595243001d18b399c1eb9b3628
deleted file mode 100644
index f06656a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/22/7124d8595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,96 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
- *
- * @file xusbps_hw.c
-* @addtogroup usbps_v2_7
-* @{
- *
- * The implementation of the XUsbPs interface reset functionality
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.05a kpc 10/10/10 first version
- *
- *
- *****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xstatus.h"
-#include "xusbps.h"
-#include "xparameters.h"
-
-
-/************************** Constant Definitions ****************************/
-#define XUSBPS_RESET_TIMEOUT 0xFFFFF
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-
-/************************** Function Prototypes *****************************/
-
-
-/*****************************************************************************/
-/**
-* This function perform the reset sequence to the given usbps interface by
-* configuring the appropriate control bits in the usbps specific registers.
-* the usbps reset sequence involves the below steps
-* Disable the interrupts
-* Clear the status registers
-* Apply the reset command and wait for reset complete status
-* Update the relevant control registers with reset values
-* @param BaseAddress of the interface
-*
-* @return N/A.
-*
-* @note None.
-*
-******************************************************************************/
-void XUsbPs_ResetHw(u32 BaseAddress)
-{
- u32 RegVal;
- u32 Timeout = 0;
-
- /* Host and device mode */
- /* Disable the interrupts */
- XUsbPs_WriteReg(BaseAddress,XUSBPS_IER_OFFSET,0x0);
- /* Clear the interuupt status */
- RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_ISR_OFFSET);
- XUsbPs_WriteReg(BaseAddress,XUSBPS_ISR_OFFSET,RegVal);
-
- /* Perform the reset operation using USB CMD register */
- RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET);
- RegVal = RegVal | XUSBPS_CMD_RST_MASK;
- XUsbPs_WriteReg(BaseAddress,XUSBPS_CMD_OFFSET,RegVal);
- RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET);
- /* Wait till the reset operation returns success */
- /*
- * FIX ME: right now no indication to the caller or user about
- * timeout overflow
- */
- while ((RegVal & XUSBPS_CMD_RST_MASK) && (Timeout < XUSBPS_RESET_TIMEOUT))
- {
- RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET);
- Timeout++;
- }
- /* Update periodic list base address register with reset value */
- XUsbPs_WriteReg(BaseAddress,XUSBPS_LISTBASE_OFFSET,0x0);
- /* Update async/endpoint list base address register with reset value */
- XUsbPs_WriteReg(BaseAddress,XUSBPS_ASYNCLISTADDR_OFFSET,0x0);
-
-}
-
-
-
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/22/9034ad545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/22/9034ad545243001d18b399c1eb9b3628
deleted file mode 100644
index 9d33a6c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/22/9034ad545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,193 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xgpio.h
-* @addtogroup gpio_v4_8
-* @{
-* @details
-*
-* This file contains the software API definition of the Xilinx General Purpose
-* I/O (XGpio) device driver.
-*
-* The Xilinx GPIO controller is a soft IP core designed for Xilinx FPGAs and
-* contains the following general features:
-* - Support for up to 32 I/O discretes for each channel (64 bits total).
-* - Each of the discretes can be configured for input or output.
-* - Configurable support for dual channels and interrupt generation.
-*
-* The driver provides interrupt management functions. Implementation of
-* interrupt handlers is left to the user. Refer to the provided interrupt
-* example in the examples directory for details.
-*
-* This driver is intended to be RTOS and processor independent. Any needs for
-* dynamic memory management, threads or thread mutual exclusion, virtual
-* memory, or cache control must be satisfied by the layer above this driver.
-*
-* Initialization & Configuration
-*
-* The XGpio_Config structure is used by the driver to configure itself. This
-* configuration structure is typically created by the tool-chain based on HW
-* build properties.
-*
-* To support multiple runtime loading and initialization strategies employed
-* by various operating systems, the driver instance can be initialized in one
-* of the following ways:
-*
-* - XGpio_Initialize(InstancePtr, DeviceId) - The driver looks up its own
-* configuration structure created by the tool-chain based on an ID provided
-* by the tool-chain.
-*
-* - XGpio_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-* configuration structure provided by the caller. If running in a system
-* with address translation, the provided virtual memory base address
-* replaces the physical address present in the configuration structure.
-*
-* @note
-*
-* This API utilizes 32 bit I/O to the GPIO registers. With less than 32 bits,
-* the unused bits from registers are read as zero and written as don't cares.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 03/13/02 First release
-* 2.00a jhl 11/26/03 Added support for dual channels and interrupts
-* 2.01a jvb 12/14/05 I separated dependency on the static config table and
-* xparameters.h from the driver initialization by moving
-* _Initialize and _LookupConfig to _sinit.c. I also added
-* the new _CfgInitialize routine.
-* 2.11a mta 03/21/07 Updated to new coding style, added GetDataDirection
-* 2.12a sv 11/21/07 Updated driver to support access through DCR bus
-* 2.12a sv 06/05/08 Updated driver to fix the XGpio_InterruptDisable function
-* to properly update the Interrupt Enable register
-* 2.13a sdm 08/22/08 Removed support for static interrupt handlers from the MDD
-* file
-* 3.00a sv 11/21/09 Updated to use HAL Processor APIs.
-* Renamed the macros XGpio_mWriteReg to XGpio_WriteReg and
-* XGpio_mReadReg to XGpio_ReadReg. Removed the macros
-* XGpio_mSetDataDirection, XGpio_mGetDataReg and
-* XGpio_mSetDataReg. Users should use XGpio_WriteReg and
-* XGpio_ReadReg to achieve the same functionality.
-* 3.01a bss 04/18/13 Updated driver tcl to generate Canonical params in
-* xparameters.h. CR#698589
-* 4.0 adk 19/12/13 Updated as per the New Tcl API's
-* 4.1 lks 11/18/15 Updated to use canonical xparameters in examples and
-* clean up of the comments, removed support for DCR bridge
-* and removed xgpio_intr_example for CR 900381
-* 4.2 sk 08/16/16 Used UINTPTR instead of u32 for Baseaddress as part of
-* adding 64 bit support. CR# 867425.
-* Changed the prototype of XGpio_CfgInitialize API.
-* 4.3 sk 09/29/16 Modified the example to make it work when LED_bits are
-* configured as an output. CR# 958644
-* ms 01/23/17 Added xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 4.4 sne 04/25/19 Updated Makefile for IAR compier (CR-1029421).
-* 4.5 sne 06/14/19 Fixed IAR compiler warnings on example files.
-* 4.6 sne 08/11/19 Fixed compilation error of armcc compiler.
-* 4.7 sne 08/28/20 Modify Makefile to support parallel make execution.
-* 4.8 sne 02/10/21 Fixed doxygen warnings.
-*
-*
-*****************************************************************************/
-
-#ifndef XGPIO_H /* prevent circular inclusions */
-#define XGPIO_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xgpio_l.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- UINTPTR BaseAddress; /**< Device base address */
- int InterruptPresent; /**< Are interrupts supported in h/w */
- int IsDual; /**< Are 2 channels supported in h/w */
-} XGpio_Config;
-
-/**
- * The XGpio driver instance data. The user is required to allocate a
- * variable of this type for every GPIO device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- UINTPTR BaseAddress; /**< Device base address */
- u32 IsReady; /**< Device is initialized and ready */
- int InterruptPresent; /**< Are interrupts supported in h/w */
- int IsDual; /**< Are 2 channels supported in h/w */
-} XGpio;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Function Prototypes *****************************/
-
-/*
- * Initialization functions in xgpio_sinit.c
- */
-int XGpio_Initialize(XGpio *InstancePtr, u16 DeviceId);
-XGpio_Config *XGpio_LookupConfig(u16 DeviceId);
-
-/*
- * API Basic functions implemented in xgpio.c
- */
-int XGpio_CfgInitialize(XGpio *InstancePtr, XGpio_Config * Config,
- UINTPTR EffectiveAddr);
-void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
- u32 DirectionMask);
-u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel);
-u32 XGpio_DiscreteRead(XGpio *InstancePtr, unsigned Channel);
-void XGpio_DiscreteWrite(XGpio *InstancePtr, unsigned Channel, u32 Mask);
-
-
-/*
- * API Functions implemented in xgpio_extra.c
- */
-void XGpio_DiscreteSet(XGpio *InstancePtr, unsigned Channel, u32 Mask);
-void XGpio_DiscreteClear(XGpio *InstancePtr, unsigned Channel, u32 Mask);
-
-/*
- * API Functions implemented in xgpio_selftest.c
- */
-int XGpio_SelfTest(XGpio *InstancePtr);
-
-/*
- * API Functions implemented in xgpio_intr.c
- */
-void XGpio_InterruptGlobalEnable(XGpio *InstancePtr);
-void XGpio_InterruptGlobalDisable(XGpio *InstancePtr);
-void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask);
-void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask);
-void XGpio_InterruptClear(XGpio *InstancePtr, u32 Mask);
-u32 XGpio_InterruptGetEnabled(XGpio *InstancePtr);
-u32 XGpio_InterruptGetStatus(XGpio *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/22/915cb8585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/22/915cb8585243001d18b399c1eb9b3628
deleted file mode 100644
index 76a4904..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/22/915cb8585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,16 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include
-#include "xil_types.h"
-
-void exit(sint32 arg)
-{
- while(1) {
- ;
- }
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/22/c1ca5d565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/22/c1ca5d565243001d18b399c1eb9b3628
deleted file mode 100644
index c52d476..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/22/c1ca5d565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,447 +0,0 @@
-/******************************************************************************
-* Copyright (c) 1995 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-*******************************************************************************/
-/*---------------------------------------------------*/
-/* Modified from : */
-/* Public Domain version of printf */
-/* Rud Merriam, Compsult, Inc. Houston, Tx. */
-/* For Embedded Systems Programming, 1991 */
-/* */
-/*---------------------------------------------------*/
-#include "xil_printf.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include
-#include
-#include
-
-static void padding( const s32 l_flag,const struct params_s *par);
-static void outs(const charptr lp, struct params_s *par);
-static s32 getnum( charptr* linep);
-
-typedef struct params_s {
- s32 len;
- s32 num1;
- s32 num2;
- char8 pad_character;
- s32 do_padding;
- s32 left_flag;
- s32 unsigned_flag;
-} params_t;
-
-
-/*---------------------------------------------------*/
-/* The purpose of this routine is to output data the */
-/* same as the standard printf function without the */
-/* overhead most run-time libraries involve. Usually */
-/* the printf brings in many kilobytes of code and */
-/* that is unacceptable in most embedded systems. */
-/*---------------------------------------------------*/
-
-
-/*---------------------------------------------------*/
-/* */
-/* This routine puts pad characters into the output */
-/* buffer. */
-/* */
-static void padding( const s32 l_flag, const struct params_s *par)
-{
- s32 i;
-
- if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) {
- i=(par->len);
- for (; i<(par->num1); i++) {
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( par->pad_character);
-#endif
- }
- }
-}
-
-/*---------------------------------------------------*/
-/* */
-/* This routine moves a string to the output buffer */
-/* as directed by the padding and positioning flags. */
-/* */
-static void outs(const charptr lp, struct params_s *par)
-{
- charptr LocalPtr;
- LocalPtr = lp;
- /* pad on left if needed */
- if(LocalPtr != NULL) {
- par->len = (s32)strlen( LocalPtr);
- padding( !(par->left_flag), par);
- /* Move string to the buffer */
- while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) {
- (par->num2)--;
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte(*LocalPtr);
-#endif
- LocalPtr += 1;
- }
-}
-
- /* Pad on right if needed */
- /* CR 439175 - elided next stmt. Seemed bogus. */
- /* par->len = strlen( lp) */
- padding( par->left_flag, par);
-}
-
-/*---------------------------------------------------*/
-/* */
-/* This routine moves a number to the output buffer */
-/* as directed by the padding and positioning flags. */
-/* */
-
-static void outnum( const s32 n, const s32 base, struct params_s *par)
-{
- s32 negative;
- s32 i;
- char8 outbuf[32];
- const char8 digits[] = "0123456789ABCDEF";
- u32 num;
- for(i = 0; i<32; i++) {
- outbuf[i] = '0';
- }
-
- /* Check if number is negative */
- if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
- negative = 1;
- num =(-(n));
- }
- else{
- num = n;
- negative = 0;
- }
-
- /* Build number (backwards) in outbuf */
- i = 0;
- do {
- outbuf[i] = digits[(num % base)];
- i++;
- num /= base;
- } while (num > 0);
-
- if (negative != 0) {
- outbuf[i] = '-';
- i++;
- }
-
- outbuf[i] = '\0';
- i--;
-
- /* Move the converted number to the buffer and */
- /* add in the padding where needed. */
- par->len = (s32)strlen(outbuf);
- padding( !(par->left_flag), par);
- while (&outbuf[i] >= outbuf) {
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( outbuf[i] );
-#endif
- i--;
-}
- padding( par->left_flag, par);
-}
-/*---------------------------------------------------*/
-/* */
-/* This routine moves a 64-bit number to the output */
-/* buffer as directed by the padding and positioning */
-/* flags. */
-/* */
-#if defined (__aarch64__) || defined (__arch64__)
-static void outnum1( const s64 n, const s32 base, params_t *par)
-{
- s32 negative;
- s32 i;
- char8 outbuf[64];
- const char8 digits[] = "0123456789ABCDEF";
- u64 num;
- for(i = 0; i<64; i++) {
- outbuf[i] = '0';
- }
-
- /* Check if number is negative */
- if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
- negative = 1;
- num =(-(n));
- }
- else{
- num = (n);
- negative = 0;
- }
-
- /* Build number (backwards) in outbuf */
- i = 0;
- do {
- outbuf[i] = digits[(num % base)];
- i++;
- num /= base;
- } while (num > 0);
-
- if (negative != 0) {
- outbuf[i] = '-';
- i++;
- }
-
- outbuf[i] = '\0';
- i--;
-
- /* Move the converted number to the buffer and */
- /* add in the padding where needed. */
- par->len = (s32)strlen(outbuf);
- padding( !(par->left_flag), par);
- while (&outbuf[i] >= outbuf) {
- outbyte( outbuf[i] );
- i--;
-}
- padding( par->left_flag, par);
-}
-#endif
-/*---------------------------------------------------*/
-/* */
-/* This routine gets a number from the format */
-/* string. */
-/* */
-static s32 getnum(charptr* linep)
-{
- s32 n = 0;
- s32 ResultIsDigit = 0;
- charptr cptr = *linep;
-
- while (cptr != NULL) {
- ResultIsDigit = isdigit(((s32)*cptr));
- if (ResultIsDigit == 0)
- break;
- n = ((n*10) + (((s32)*cptr) - (s32)'0'));
- cptr += 1;
- }
-
- *linep = ((charptr)(cptr));
- return(n);
-}
-
-/*---------------------------------------------------*/
-/* */
-/* This routine operates just like a printf/sprintf */
-/* routine. It outputs a set of data under the */
-/* control of a formatting string. Not all of the */
-/* standard C format control are supported. The ones */
-/* provided are primarily those needed for embedded */
-/* systems work. Primarily the floating point */
-/* routines are omitted. Other formats could be */
-/* added easily by following the examples shown for */
-/* the supported formats. */
-/* */
-
-/* void esp_printf( const func_ptr f_ptr,
- const charptr ctrl1, ...) */
-#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
-void xil_printf( const char8 *ctrl1, ...){
- XPVXenConsole_Printf(ctrl1);
-}
-#else
-void xil_printf( const char8 *ctrl1, ...)
-{
- va_list argp;
-
- va_start(argp, ctrl1);
-
- xil_vprintf(ctrl1, argp);
-
- va_end(argp);
-}
-#endif
-
-/* This routine is equivalent to vprintf routine */
-void xil_vprintf(const char8 *ctrl1, va_list argp)
-{
- s32 Check;
-#if defined (__aarch64__) || defined (__arch64__)
- s32 long_flag;
-#endif
- s32 dot_flag;
-
- params_t par;
-
- char8 ch;
- char8 *ctrl = (char8 *)ctrl1;
-
- while ((ctrl != NULL) && (*ctrl != (char8)0)) {
-
- /* move format string chars to buffer until a */
- /* format control is found. */
- if (*ctrl != '%') {
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte(*ctrl);
-#endif
- ctrl += 1;
- continue;
- }
-
- /* initialize all the flags for this format. */
- dot_flag = 0;
-#if defined (__aarch64__) || defined (__arch64__)
- long_flag = 0;
-#endif
- par.unsigned_flag = 0;
- par.left_flag = 0;
- par.do_padding = 0;
- par.pad_character = ' ';
- par.num2=32767;
- par.num1=0;
- par.len=0;
-
- try_next:
- if(ctrl != NULL) {
- ctrl += 1;
- }
- if(ctrl != NULL) {
- ch = *ctrl;
- } else {
- break;
- }
-
- if (isdigit((s32)ch) != 0) {
- if (dot_flag != 0) {
- par.num2 = getnum(&ctrl);
- }
- else {
- if (ch == '0') {
- par.pad_character = '0';
- }
- if(ctrl != NULL) {
- par.num1 = getnum(&ctrl);
- }
- par.do_padding = 1;
- }
- if(ctrl != NULL) {
- ctrl -= 1;
- }
- goto try_next;
- }
-
- switch (tolower((s32)ch)) {
- case '%':
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( '%');
-#endif
- Check = 1;
- break;
-
- case '-':
- par.left_flag = 1;
- Check = 0;
- break;
-
- case '.':
- dot_flag = 1;
- Check = 0;
- break;
-
- case 'l':
- #if defined (__aarch64__) || defined (__arch64__)
- long_flag = 1;
- #endif
- Check = 0;
- break;
-
- case 'u':
- par.unsigned_flag = 1;
- /* fall through */
- case 'i':
- case 'd':
- #if defined (__aarch64__) || defined (__arch64__)
- if (long_flag != 0){
- outnum1((s64)va_arg(argp, s64), 10L, &par);
- }
- else {
- outnum( va_arg(argp, s32), 10L, &par);
- }
- #else
- outnum( va_arg(argp, s32), 10L, &par);
- #endif
- Check = 1;
- break;
- case 'p':
- #if defined (__aarch64__) || defined (__arch64__)
- par.unsigned_flag = 1;
- outnum1((s64)va_arg(argp, s64), 16L, &par);
- Check = 1;
- break;
- #endif
- case 'X':
- case 'x':
- par.unsigned_flag = 1;
- #if defined (__aarch64__) || defined (__arch64__)
- if (long_flag != 0) {
- outnum1((s64)va_arg(argp, s64), 16L, &par);
- }
- else {
- outnum((s32)va_arg(argp, s32), 16L, &par);
- }
- #else
- outnum((s32)va_arg(argp, s32), 16L, &par);
- #endif
- Check = 1;
- break;
-
- case 's':
- outs( va_arg( argp, char *), &par);
- Check = 1;
- break;
-
- case 'c':
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( va_arg( argp, s32));
-#endif
- Check = 1;
- break;
-
- case '\\':
- switch (*ctrl) {
- case 'a':
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( ((char8)0x07));
-#endif
- break;
- case 'h':
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( ((char8)0x08));
-#endif
- break;
- case 'r':
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( ((char8)0x0D));
-#endif
- break;
- case 'n':
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( ((char8)0x0D));
- outbyte( ((char8)0x0A));
-#endif
- break;
- default:
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( *ctrl);
-#endif
- break;
- }
- ctrl += 1;
- Check = 0;
- break;
-
- default:
- Check = 1;
- break;
- }
- if(Check == 1) {
- if(ctrl != NULL) {
- ctrl += 1;
- }
- continue;
- }
- goto try_next;
- }
-}
-/*---------------------------------------------------*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/22/f0a5d0555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/22/f0a5d0555243001d18b399c1eb9b3628
deleted file mode 100644
index 3972482..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/22/f0a5d0555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,15 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#include "xil_types.h"
-/* Stub for iserror() function */
-__weak s32 _sys_iserror(s32 status)
-{
- if(status<0) {
- return 1;
- }
-
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/22/f1c8d3575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/22/f1c8d3575243001d18b399c1eb9b3628
deleted file mode 100644
index 33822bf..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/22/f1c8d3575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,843 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
- *
- * @file xemacps.h
-* @addtogroup emacps_v3_15
-* @{
-* @details
- *
- * The Xilinx Embedded Processor Block Ethernet driver.
- *
- * For a full description of XEMACPS features, please see the hardware spec.
- * This driver supports the following features:
- * - Memory mapped access to host interface registers
- * - Statistics counter registers for RMON/MIB
- * - API for interrupt driven frame transfers for hardware configured DMA
- * - Virtual memory support
- * - Unicast, broadcast, and multicast receive address filtering
- * - Full and half duplex operation
- * - Automatic PAD & FCS insertion and stripping
- * - Flow control
- * - Support up to four 48bit addresses
- * - Address checking for four specific 48bit addresses
- * - VLAN frame support
- * - Pause frame support
- * - Large frame support up to 1536 bytes
- * - Checksum offload
- *
- * Driver Description
- *
- * The device driver enables higher layer software (e.g., an application) to
- * communicate to the XEmacPs. The driver handles transmission and reception
- * of Ethernet frames, as well as configuration and control. No pre or post
- * processing of frame data is performed. The driver does not validate the
- * contents of an incoming frame in addition to what has already occurred in
- * hardware.
- * A single device driver can support multiple devices even when those devices
- * have significantly different configurations.
- *
- * Initialization & Configuration
- *
- * The XEmacPs_Config structure is used by the driver to configure itself.
- * This configuration structure is typically created by the tool-chain based
- * on hardware build properties.
- *
- * The driver instance can be initialized in
- *
- * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a
- * configuration structure provided by the caller. If running in a system
- * with address translation, the provided virtual memory base address
- * replaces the physical address present in the configuration structure.
- *
- * The device supports DMA only as current development plan. No FIFO mode is
- * supported. The driver expects to start the DMA channels and expects that
- * the user has set up the buffer descriptor lists.
- *
- * Interrupts and Asynchronous Callbacks
- *
- * The driver has no dependencies on the interrupt controller. When an
- * interrupt occurs, the handler will perform a small amount of
- * housekeeping work, determine the source of the interrupt, and call the
- * appropriate callback function. All callbacks are registered by the user
- * level application.
- *
- * Virtual Memory
- *
- * All virtual to physical memory mappings must occur prior to accessing the
- * driver API.
- *
- * For DMA transactions, user buffers supplied to the driver must be in terms
- * of their physical address.
- *
- * DMA
- *
- * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
- * These BDs are typically chained together into a list the hardware follows
- * when transferring data in and out of the packet buffers. Each BD describes
- * a memory region containing either a full or partial Ethernet packet.
- *
- * Interrupt coalescing is not supported from this built-in DMA engine.
- *
- * This API requires the user to understand how the DMA operates. The
- * following paragraphs provide some explanation, but the user is encouraged
- * to read documentation in xemacps_bdring.h as well as study example code
- * that accompanies this driver.
- *
- * The API is designed to get BDs to and from the DMA engine in the most
- * efficient means possible. The first step is to establish a memory region
- * to contain all BDs for a specific channel. This is done with
- * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
- * follow as BDs are processed. The ring will consist of a user defined number
- * of BDs which will all be partially initialized. For example on the transmit
- * channel, the driver will initialize all BDs' so that they are configured
- * for transmit. The more fields that can be permanently setup at
- * initialization, then the fewer accesses will be needed to each BD while
- * the DMA engine is in operation resulting in better throughput and CPU
- * utilization. The best case initialization would require the user to set
- * only a frame buffer address and length prior to submitting the BD to the
- * engine.
- *
- * BDs move through the engine with the help of functions
- * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
- * and XEmacPs_BdRingFree().
- * All these functions handle BDs that are in place. That is, there are no
- * copies of BDs kept anywhere and any BD the user interacts with is an actual
- * BD from the same ring hardware accesses.
- *
- * BDs in the ring go through a series of states as follows:
- * 1. Idle. The driver controls BDs in this state.
- * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
- * reserve BD(s). Once allocated, the user may setup the BD(s) with
- * frame buffer address, length, and other attributes. The user controls
- * BDs in this state.
- * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
- * in this state are either waiting to be processed by hardware, are in
- * process, or have been processed. The DMA engine controls BDs in this
- * state.
- * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
- * user. Once retrieved, the user can examine each BD for the outcome of
- * the DMA transfer. The user controls BDs in this state. After examining
- * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
- * into state 1.
- *
- * Each of the four BD accessor functions operate on a set of BDs. A set is
- * defined as a segment of the BD ring consisting of one or more BDs. The user
- * views the set as a pointer to the first BD along with the number of BDs for
- * that set. The set can be navigated by using macros XEmacPs_BdNext(). The
- * user must exercise extreme caution when changing BDs in a set as there is
- * nothing to prevent doing a mBdNext past the end of the set and modifying a
- * BD out of bounds.
- *
- * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
- * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
- * tandem. The same BD set retrieved with BdRingAlloc should be the same one
- * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
- * BdRIngFree.
- *
- * Alignment & Data Cache Restrictions
- *
- * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
- * aligned. Please reference xemacps_bd.h for cache related macros.
- *
- * DMA Tx:
- *
- * - If frame buffers exist in cached memory, then they must be flushed
- * prior to committing them to hardware.
- *
- * DMA Rx:
- *
- * - If frame buffers exist in cached memory, then the cache must be
- * invalidated for the memory region containing the frame prior to data
- * access
- *
- * Both cache invalidate/flush are taken care of in driver code.
- *
- * Buffer Copying
- *
- * The driver is designed for a zero-copy buffer scheme. That is, the driver
- * will not copy buffers. This avoids potential throughput bottlenecks within
- * the driver. If byte copying is required, then the transfer will take longer
- * to complete.
- *
- * Checksum Offloading
- *
- * The Embedded Processor Block Ethernet can be configured to perform IP, TCP
- * and UDP checksum offloading in both receive and transmit directions.
- *
- * IP packets contain a 16-bit checksum field, which is the 16-bit 1s
- * complement of the 1s complement sum of all 16-bit words in the header.
- * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
- * 1s complement of the 1s complement sum of all 16-bit words in the header,
- * the data and a conceptual pseudo header.
- *
- * To calculate these checksums in software requires each byte of the packet
- * to be read. For TCP and UDP this can use a large amount of processing power.
- * Offloading the checksum calculation to hardware can result in significant
- * performance improvements.
- *
- * The transmit checksum offload is only available to use DMA in packet buffer
- * mode. This is because the complete frame to be transmitted must be read
- * into the packet buffer memory before the checksum can be calculated and
- * written to the header at the beginning of the frame.
- *
- * For IP, TCP or UDP receive checksum offload to be useful, the operating
- * system containing the protocol stack must be aware that this offload is
- * available so that it can make use of the fact that the hardware has verified
- * the checksum.
- *
- * When receive checksum offloading is enabled in the hardware, the IP header
- * checksum is checked, where the packet meets the following criteria:
- *
- * 1. If present, the VLAN header must be four octets long and the CFI bit
- * must not be set.
- * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
- * encoding.
- * 3. IP v4 packet.
- * 4. IP header is of a valid length.
- * 5. Good IP header checksum.
- * 6. No IP fragmentation.
- * 7. TCP or UDP packet.
- *
- * When an IP, TCP or UDP frame is received, the receive buffer descriptor
- * gives an indication if the hardware was able to verify the checksums.
- * There is also an indication if the frame had SNAP encapsulation. These
- * indication bits will replace the type ID match indication bits when the
- * receive checksum offload is enabled.
- *
- * If any of the checksums are verified incorrect by the hardware, the packet
- * is discarded and the appropriate statistics counter incremented.
- *
- * PHY Interfaces
- *
- * RGMII 1.3 is the only interface supported.
- *
- * Asserts
- *
- * Asserts are used within all Xilinx drivers to enforce constraints on
- * parameters. Asserts can be turned off on a system-wide basis by defining,
- * at compile time, the NDEBUG identifier. By default, asserts are turned on
- * and it is recommended that users leave asserts on during development. For
- * deployment use -DNDEBUG compiler switch to remove assert code.
- *
- * @note
- *
- * Xilinx drivers are typically composed of two parts, one is the driver
- * and the other is the adapter. The driver is independent of OS and processor
- * and is intended to be highly portable. The adapter is OS-specific and
- * facilitates communication between the driver and an OS.
- * This driver is intended to be RTOS and processor independent. Any needs for
- * dynamic memory management, threads or thread mutual exclusion, or cache
- * control must be satisfied bythe layer above this driver.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -------------------------------------------------------
- * 1.00a wsy 01/10/10 First release
- * 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file
- * xemacps_bdring.c is modified. Earlier it was checking for
- * "BdLimit"(passed argument) number of BDs for finding out
- * which BDs are successfully processed. Now one more check
- * is added. It looks for BDs till the current BD pointer
- * reaches HwTail. By doing this processing time is saved.
- * 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
- * xemacps_bdring.c is modified. Now start of packet is
- * searched for returning the number of BDs processed.
- * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
- * registers. Added a new API to set the bust length.
- * Added some new hash-defines.
- * 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for
- * Rx errors. Under heavy Rx traffic, there will be a large
- * number of errors related to receive buffer not available.
- * Because of a HW bug (SI #692601), under such heavy errors,
- * the Rx data path can become unresponsive. To reduce the
- * probabilities for hitting this HW bug, the SW writes to
- * bit 18 to flush a packet from Rx DPRAM immediately. The
- * changes for it are done in the function
- * XEmacPs_IntrHandler.
- * 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
- * removed. It is expected that all BDs are allocated in
- * from uncached area.
- * 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
- * to 0x1fff. This fixes the CR#744902.
- * Made changes in example file xemacps_example.h to fix compilation
- * issues with iarcc compiler.
- * 2.0 adk 10/12/13 Updated as per the New Tcl API's
- * 2.1 adk 11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
- * 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy
- * address in xparameters.h when GMII to RGMII converter
- * is present in hw.
- * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
- * changes.
- * 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
- * 1000BASE-X mode export proper values to the xparameters.h
- * file. Changes are made in the driver tcl file.
- * 3.0 adk 08/1/15 Don't include gem in peripheral test when gem is
- * configured with PCS/PMA Core. Changes are made in the
- * test app tcl(CR:827686).
- * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
- * 3.0 hk 03/18/15 Added support for jumbo frames. Increase AHB burst.
- * Disable extended mode. Perform all 64 bit changes under
- * check for arch64.
- * Remove "used bit set" from TX error interrupt masks.
- * 3.1 hk 07/27/15 Do not call error handler with '0' error code when
- * there is no error. CR# 869403
- * 08/10/15 Update upper 32 bit tx and rx queue ptr registers.
- * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
- * 3.4 ms 01/23/17 Modified xil_printf statement in main function for all
- * examples to ensure that "Successfully ran" and "Failed"
- * strings are available in all examples. This is a fix
- * for CR-965028.
- * ms 03/17/17 Modified text file in examples folder for doxygen
- * generation.
- * ms 04/05/17 Added tabspace for return statements in functions of
- * xemacps_ieee1588_example.c for proper documentation
- * while generating doxygen.
- * 3.5 hk 08/14/17 Update cache coherency information of the interface in
- * its config structure.
- * 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
- * changed to volatile.
- * Add API XEmacPs_BdRingPtrReset() to reset pointers
- * 3.8 hk 07/19/18 Fixed CPP, GCC and doxygen warnings - CR-1006327
- * hk 09/17/18 Fix PTP interrupt masks and cleanup comments.
- * 3.9 hk 01/23/19 Add RX watermark support
- * 3.11 sd 02/14/20 Add clock support
- * 3.13 nsk 12/14/20 Updated the tcl to not to use the instance names.
- *
- *
- *
- ****************************************************************************/
-
-#ifndef XEMACPS_H /* prevent circular inclusions */
-#define XEMACPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xemacps_hw.h"
-#include "xemacps_bd.h"
-#include "xemacps_bdring.h"
-#if defined (XCLOCKING)
-#include "xil_clocking.h"
-#endif
-
-/************************** Constant Definitions ****************************/
-
-/*
- * Device information
- */
-#define XEMACPS_DEVICE_NAME "xemacps"
-#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC"
-
-
-/** @name Configuration options
- *
- * Device configuration options. See the XEmacPs_SetOptions(),
- * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
- * use options.
- *
- * The default state of the options are noted and are what the device and
- * driver will be set to after calling XEmacPs_Reset() or
- * XEmacPs_Initialize().
- *
- * @{
- */
-
-#define XEMACPS_PROMISC_OPTION 0x00000001U
-/**< Accept all incoming packets.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_FRAME1536_OPTION 0x00000002U
-/**< Frame larger than 1516 support for Tx & Rx.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_VLAN_OPTION 0x00000004U
-/**< VLAN Rx & Tx frame support.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U
-/**< Enable recognition of flow control frames on Rx
- * This option defaults to enabled (set) */
-
-#define XEMACPS_FCS_STRIP_OPTION 0x00000020U
-/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
- * stripped.
- * This option defaults to enabled (set) */
-
-#define XEMACPS_FCS_INSERT_OPTION 0x00000040U
-/**< Generate FCS field and add PAD automatically for outgoing frames.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U
-/**< Enable Length/Type error checking for incoming frames. When this option is
- * set, the MAC will filter frames that have a mismatched type/length field
- * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
- * types of frames are encountered. When this option is cleared, the MAC will
- * allow these types of frames to be received.
- *
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U
-/**< Enable the transmitter.
- * This option defaults to enabled (set) */
-
-#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U
-/**< Enable the receiver
- * This option defaults to enabled (set) */
-
-#define XEMACPS_BROADCAST_OPTION 0x00000400U
-/**< Allow reception of the broadcast address
- * This option defaults to enabled (set) */
-
-#define XEMACPS_MULTICAST_OPTION 0x00000800U
-/**< Allows reception of multicast addresses programmed into hash
- * This option defaults to disabled (clear) */
-
-#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U
-/**< Enable the RX checksum offload
- * This option defaults to enabled (set) */
-
-#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U
-/**< Enable the TX checksum offload
- * This option defaults to enabled (set) */
-
-#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U
-#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U
-
-#define XEMACPS_DEFAULT_OPTIONS \
- ((u32)XEMACPS_FLOW_CONTROL_OPTION | \
- (u32)XEMACPS_FCS_INSERT_OPTION | \
- (u32)XEMACPS_FCS_STRIP_OPTION | \
- (u32)XEMACPS_BROADCAST_OPTION | \
- (u32)XEMACPS_LENTYPE_ERR_OPTION | \
- (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
- (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
- (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
- (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
-
-/**< Default options set when device is initialized or reset */
-/*@}*/
-
-/** @name Callback identifiers
- *
- * These constants are used as parameters to XEmacPs_SetHandler()
- * @{
- */
-#define XEMACPS_HANDLER_DMASEND 1U
-#define XEMACPS_HANDLER_DMARECV 2U
-#define XEMACPS_HANDLER_ERROR 3U
-/*@}*/
-
-/* Constants to determine the configuration of the hardware device. They are
- * used to allow the driver to verify it can operate with the hardware.
- */
-#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */
-
-/* The next few constants help upper layers determine the size of memory
- * pools used for Ethernet buffers and descriptor lists.
- */
-#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */
-
-#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */
-#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */
-#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */
-#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
-#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
-#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
- XEMACPS_TRL_SIZE)
-#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
- XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
-#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
- XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
-
-/* DMACR Bust length hash defines */
-
-#define XEMACPS_SINGLE_BURST 0x00000001
-#define XEMACPS_4BYTE_BURST 0x00000004
-#define XEMACPS_8BYTE_BURST 0x00000008
-#define XEMACPS_16BYTE_BURST 0x00000010
-
-
-/**************************** Type Definitions ******************************/
-/** @name Typedefs for callback functions
- *
- * These callbacks are invoked in interrupt context.
- * @{
- */
-/**
- * Callback invoked when frame(s) have been sent or received in interrupt
- * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
- *
- * @param CallBackRef is user data assigned when the callback was set.
- *
- * @note
- * See xemacps_hw.h for bitmasks definitions and the device hardware spec for
- * further information on their meaning.
- *
- */
-typedef void (*XEmacPs_Handler) (void *CallBackRef);
-
-/**
- * Callback when an asynchronous error occurs. To set this callback, invoke
- * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
- * parameter.
- *
- * @param CallBackRef is user data assigned when the callback was set.
- * @param Direction defines either receive or transmit error(s) has occurred.
- * @param ErrorWord definition varies with Direction
- *
- */
-typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
- u32 ErrorWord);
-
-/*@}*/
-
-/**
- * This typedef contains configuration information for a device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
- u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
- * describes whether Cache Coherent or not */
-#if defined (XCLOCKING)
- u32 RefClk; /**< Input clock */
-#endif
- u16 S1GDiv0; /**< 1Gbps Clock Divider 0 */
- u8 S1GDiv1; /**< 1Gbps Clock Divider 1 */
- u16 S100MDiv0; /**< 100Mbps Clock Divider 0 */
- u8 S100MDiv1; /**< 100Mbps Clock Divider 1 */
- u16 S10MDiv0; /**< 10Mbps Clock Divider 0 */
- u8 S10MDiv1; /**< 10Mbps Clock Divider 1 */
-} XEmacPs_Config;
-
-
-/**
- * The XEmacPs driver instance data. The user is required to allocate a
- * structure of this type for every XEmacPs device in the system. A pointer
- * to a structure of this type is then passed to the driver API functions.
- */
-typedef struct XEmacPs_Instance {
- XEmacPs_Config Config; /* Hardware configuration */
- u32 IsStarted; /* Device is currently started */
- u32 IsReady; /* Device is initialized and ready */
- u32 Options; /* Current options word */
-
- XEmacPs_BdRing TxBdRing; /* Transmit BD ring */
- XEmacPs_BdRing RxBdRing; /* Receive BD ring */
-
- XEmacPs_Handler SendHandler;
- XEmacPs_Handler RecvHandler;
- void *SendRef;
- void *RecvRef;
-
- XEmacPs_ErrHandler ErrorHandler;
- void *ErrorRef;
- u32 Version;
- u32 RxBufMask;
- u32 MaxMtuSize;
- u32 MaxFrameSize;
- u32 MaxVlanFrameSize;
-
-} XEmacPs;
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* Retrieve the Tx ring object. This object can be used in the various Ring
-* API functions.
-*
-* @param InstancePtr is the DMA channel to operate on.
-*
-* @return TxBdRing attribute
-*
-* @note
-* C-style signature:
-* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
-
-/****************************************************************************/
-/**
-* Retrieve the Rx ring object. This object can be used in the various Ring
-* API functions.
-*
-* @param InstancePtr is the DMA channel to operate on.
-*
-* @return RxBdRing attribute
-*
-* @note
-* C-style signature:
-* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
-
-/****************************************************************************/
-/**
-*
-* Enable interrupts specified in Mask. The corresponding interrupt for
-* each bit set to 1 in Mask, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to enable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntEnable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_IER_OFFSET, \
- ((Mask) & XEMACPS_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Disable interrupts specified in Mask. The corresponding interrupt for
-* each bit set to 1 in Mask, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to disable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntDisable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_IDR_OFFSET, \
- ((Mask) & XEMACPS_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Enable interrupts specified in Mask. The corresponding interrupt for
-* each bit set to 1 in Mask, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to enable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_INTQ1_IER_OFFSET, \
- ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Disable interrupts specified in Mask. The corresponding interrupt for
-* each bit set to 1 in Mask, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to disable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_INTQ1_IDR_OFFSET, \
- ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* This macro triggers trasmit circuit to send data currently in TX buffer(s).
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return
-*
-* @note
-*
-* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_Transmit(InstancePtr) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_NWCTRL_OFFSET, \
- (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
-
-/****************************************************************************/
-/**
-*
-* This macro determines if the device is configured with checksum offloading
-* on the receive channel
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return
-*
-* Boolean TRUE if the device is configured with checksum offloading, or
-* FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_IsRxCsum(InstancePtr) \
- ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
- ? TRUE : FALSE)
-
-/****************************************************************************/
-/**
-*
-* This macro determines if the device is configured with checksum offloading
-* on the transmit channel
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return
-*
-* Boolean TRUE if the device is configured with checksum offloading, or
-* FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_IsTxCsum(InstancePtr) \
- ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
- ? TRUE : FALSE)
-
-/************************** Function Prototypes *****************************/
-
-/****************************************************************************/
-/**
-*
-* This macro sets RX watermark register.
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-* @param High is the non-zero RX high watermark value. When SRAM fill level
-* is above this, a pause frame will be sent.
-* @param Low is the non-zero RX low watermark value. When SRAM fill level
-* is below this, a zero length pause frame will be sent IF the last
-* pause frame sent was non-zero.
-*
-* @return None
-*
-* @note
-*
-* Signature: void XEmacPs_SetRXWatermark(XEmacPs *InstancePtr, u16 High,
-* u16 Low)
-*
-*****************************************************************************/
-#define XEmacPs_SetRXWatermark(InstancePtr, High, Low) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_RXWATERMARK_OFFSET, \
- (High & XEMACPS_RXWM_HIGH_MASK) | \
- ((Low << XEMACPS_RXWM_LOW_SHFT_MSK) & XEMACPS_RXWM_LOW_MASK) |)
-
-/****************************************************************************/
-/**
-*
-* This macro gets RX watermark register.
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return RX watermark register value
-*
-* @note
-*
-* Signature: void XEmacPs_GetRXWatermark(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_GetRXWatermark(InstancePtr) \
- XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_RXWATERMARK_OFFSET)
-/*
- * Initialization functions in xemacps.c
- */
-LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
- UINTPTR EffectiveAddress);
-void XEmacPs_Start(XEmacPs *InstancePtr);
-void XEmacPs_Stop(XEmacPs *InstancePtr);
-void XEmacPs_Reset(XEmacPs *InstancePtr);
-void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
- u16 Direction);
-
-/*
- * Lookup configuration in xemacps_sinit.c
- */
-XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
-
-/*
- * Interrupt-related functions in xemacps_intr.c
- * DMA only and FIFO is not supported. This DMA does not support coalescing.
- */
-LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
- void *FuncPointer, void *CallBackRef);
-void XEmacPs_IntrHandler(void *XEmacPsPtr);
-
-/*
- * MAC configuration/control functions in XEmacPs_control.c
- */
-LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
-LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
-u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
-
-LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
-LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
-void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
-
-LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
-void XEmacPs_ClearHash(XEmacPs *InstancePtr);
-void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
-
-void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
- XEmacPs_MdcDiv Divisor);
-void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
-u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
-LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
- u32 RegisterNum, u16 *PhyDataPtr);
-LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
- u32 RegisterNum, u16 PhyData);
-LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
-
-LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
-void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/23/20e3f1585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/23/20e3f1585243001d18b399c1eb9b3628
deleted file mode 100644
index e48c5f3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/23/20e3f1585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,111 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_errata.h
-*
-* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
-* @{
-* Various ARM errata are handled in the standalone BSP. The implementation for
-* errata handling follows ARM guidelines and is based on the open source Linux
-* support for these errata.
-*
-* @note The errata handling is enabled by default. To disable handling of all the
-* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
-* disable errata on a per-erratum basis, un-define relevant macros in
-* xil_errata.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a srt 04/18/13 First release
-* 6.6 mus 12/07/17 Removed errata 753970, It fixes CR#989132.
-*
-*
-******************************************************************************/
-#ifndef XIL_ERRATA_H
-#define XIL_ERRATA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *@cond nocomments
- */
-/**
- * @name errata_definitions
- *
- * The errata conditions handled in the standalone BSP are listed below
- * @{
- */
-
-#define ENABLE_ARM_ERRATA 1
-
-/**
- *@endcond
- */
-
-#ifdef ENABLE_ARM_ERRATA
-
-/**
- * Errata No: 742230
- * Description: DMB operation may be faulty
- */
-#define CONFIG_ARM_ERRATA_742230 1
-
-/**
- * Errata No: 743622
- * Description: Faulty hazard checking in the Store Buffer may lead
- * to data corruption.
- */
-#define CONFIG_ARM_ERRATA_743622 1
-
-/**
- * Errata No: 775420
- * Description: A data cache maintenance operation which aborts,
- * might lead to deadlock
- */
-#define CONFIG_ARM_ERRATA_775420 1
-
-/**
- * Errata No: 794073
- * Description: Speculative instruction fetches with MMU disabled
- * might not comply with architectural requirements
- */
-#define CONFIG_ARM_ERRATA_794073 1
-
-
-/** PL310 L2 Cache Errata */
-
-/**
- * Errata No: 588369
- * Description: Clean & Invalidate maintenance operations do not
- * invalidate clean lines
- */
-#define CONFIG_PL310_ERRATA_588369 1
-
-/**
- * Errata No: 727915
- * Description: Background Clean and Invalidate by Way operation
- * can cause data corruption
- */
-#define CONFIG_PL310_ERRATA_727915 1
-
-/*@}*/
-#endif /* ENABLE_ARM_ERRATA */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_ERRATA_H */
-/**
-* @} End of "addtogroup a9_errata".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/23/31a934545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/23/31a934545243001d18b399c1eb9b3628
deleted file mode 100644
index 75cd6f6..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/23/31a934545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,105 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.h
-*
-* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions
-*
-* Cache functions provide access to cache related operations such as flush
-* and invalidate for instruction and data caches. It gives option to perform
-* the cache operations on a single cacheline, a range of memory and an entire
-* cache.
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 01/29/10 First release
-* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
-* APIs.
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-*
-******************************************************************************/
-
-/**
-*@cond nocomments
-*/
-
-#ifndef XIL_CACHE_H
-#define XIL_CACHE_H
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef __GNUC__
-
-#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
- XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
-
-#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
- XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
-
-#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
- XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
-
-#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
- XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
-
-#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
- XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
-
-#elif defined (__ICCARM__)
-
-#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
- XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
-
-#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
- XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
-
-#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \
- XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
-
-#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \
- XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
-
-#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \
- XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
-
-#endif
-
-/**
-*@endcond
-*/
-
-void Xil_DCacheEnable(void);
-void Xil_DCacheDisable(void);
-void Xil_DCacheInvalidate(void);
-void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
-void Xil_DCacheFlush(void);
-void Xil_DCacheFlushRange(INTPTR adr, u32 len);
-
-void Xil_ICacheEnable(void);
-void Xil_ICacheDisable(void);
-void Xil_ICacheInvalidate(void);
-void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-* @} End of "addtogroup a9_cache_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/23/828a30545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/23/828a30545243001d18b399c1eb9b3628
deleted file mode 100644
index fd7f472..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/23/828a30545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,273 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xgpiops.h
-* @addtogroup gpiops_v3_9
-* @{
-* @details
-*
-* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
-* Controller.
-*
-* The GPIO Controller supports the following features:
-* - 4 banks
-* - Masked writes (There are no masked reads)
-* - Bypass mode
-* - Configurable Interrupts (Level/Edge)
-*
-* This driver is intended to be RTOS and processor independent. Any needs for
-* dynamic memory management, threads or thread mutual exclusion, virtual
-* memory, or cache control must be satisfied by the layer above this driver.
-
-* This driver supports all the features listed above, if applicable.
-*
-* Driver Description
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate to the GPIO.
-*
-* Interrupts
-*
-* The driver provides interrupt management functions and an interrupt handler.
-* Users of this driver need to provide callback functions. An interrupt handler
-* example is available with the driver.
-*
-* Threads
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* Asserts
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* Building the driver
-*
-* The XGpioPs driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sv 01/15/10 First Release
-* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
-* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
-* relevant to Zynq device.The interrupts are disabled
-* for output pins on all banks during initialization.
-* 1.02a hk 08/22/13 Added low level reset API
-* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
-* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
-* passed to APIs. CR# 822636
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/05/17 Added tabspace for return statements in functions of
-* gpiops examples for proper documentation while
-* generating doxygen.
-* 3.3 ms 04/17/17 Added notes about gpio input and output pin description
-* for zcu102 and zc702 boards in polled and interrupt
-* example, configured Interrupt pin to input pin for
-* proper functioning of interrupt example.
-* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
-* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
-* in safety mode and modified the code such as
-* Use of mixed mode arithmetic,Declared the pointer param
-* as Pointer to const,Casting operation to a pointer,
-* Literal value requires a U suffix.
-* 3.5 sne 03/14/19 Added Versal support.
-* 3.6 mus 04/05/19 Replaced XPLAT_versal macro with XPLAT_VERSAL, to be in
-* sync with standalone BSP
-* 3.6 sne 06/12/19 Fixed IAR compiler warning.
-* 3.6 sne 08/14/19 Added interrupt handler support on versal.
-* 3.7 sne 12/04/19 Reverted versal examples support.
-* 3.8 sne 08/28/20 Modify Makefile to support parallel make execution.
-* 3.8 sne 09/17/20 Added description for Versal PS and PMC GPIO pins.
-* 3.9 sne 03/15/21 Fixed MISRA-C violations.
-*
-*
-*
-******************************************************************************/
-#ifndef XGPIOPS_H /* prevent circular inclusions */
-#define XGPIOPS_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xgpiops_hw.h"
-#include "xplatform_info.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Interrupt types
- * @{
- * The following constants define the interrupt types that can be set for each
- * GPIO pin.
- */
-#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */
-#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */
-#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */
-#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */
-#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
-/** @}*/
-
-#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
-#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
-#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
-#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
-#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
-
-#ifdef XPAR_PSU_GPIO_0_BASEADDR
-#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */
-#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */
-#endif
-
-#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a
- * Zynq Ultrascale+ MP GPIO device
- */
-#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
-
-#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
- * Zynq Ultrascale+ MP GPIO device
- * 0 - 25, Bank 0
- * 26 - 51, Bank 1
- * 52 - 77, Bank 2
- * 78 - 109, Bank 3
- * 110 - 141, Bank 4
- * 142 - 173, Bank 5
- */
-#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device
- * 0 - 31, Bank 0
- * 32 - 53, Bank 1
- * 54 - 85, Bank 2
- * 86 - 117, Bank 3
- */
-
-/**************************** Type Definitions *******************************/
-
-/****************************************************************************/
-/**
- * This handler data type allows the user to define a callback function to
- * handle the interrupts for the GPIO device. The application using this
- * driver is expected to define a handler of this type, to support interrupt
- * driven mode. The handler executes in an interrupt context such that minimal
- * processing should be performed.
- *
- * @param CallBackRef is a callback reference passed in by the upper layer
- * when setting the callback functions for a GPIO bank. It is
- * passed back to the upper layer when the callback is invoked. Its
- * type is not important to the driver component, so it is a void
- * pointer.
- * @param Bank is the bank for which the interrupt status has changed.
- * @param Status is the Interrupt status of the GPIO bank.
- *
- *****************************************************************************/
-typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
-
-/**
- * This typedef contains configuration information for a device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- UINTPTR BaseAddr; /**< Register base address */
-} XGpioPs_Config;
-
-/**
- * The XGpioPs driver instance data. The user is required to allocate a
- * variable of this type for the GPIO device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XGpioPs_Config GpioConfig; /**< Device configuration */
- u32 IsReady; /**< Device is initialized and ready */
- XGpioPs_Handler Handler; /**< Status handlers for all banks */
- void *CallBackRef; /**< Callback ref for bank handlers */
- u32 Platform; /**< Platform data */
- u32 MaxPinNum; /**< Max pins in the GPIO device */
- u8 MaxBanks; /**< Max banks in a GPIO device */
- u32 PmcGpio; /**< Flag for accessing PS GPIO for versal*/
-} XGpioPs;
-
-/************************** Variable Definitions *****************************/
-extern XGpioPs_Config XGpioPs_ConfigTable[];
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/* Functions in xgpiops.c */
-s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
- u32 EffectiveAddr);
-
-/* Bank APIs in xgpiops.c */
-u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data);
-void XGpioPs_SetDirection(const XGpioPs *InstancePtr, u8 Bank, u32 Direction);
-u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_SetOutputEnable(const XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
-u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank);
-#ifdef versal
-void XGpioPs_GetBankPin(const XGpioPs *InstancePtr,u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank);
-#else
-void XGpioPs_GetBankPin(u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank);
-#endif
-
-/* Pin APIs in xgpiops.c */
-u32 XGpioPs_ReadPin(const XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_WritePin(const XGpioPs *InstancePtr, u32 Pin, u32 Data);
-void XGpioPs_SetDirectionPin(const XGpioPs *InstancePtr, u32 Pin, u32 Direction);
-u32 XGpioPs_GetDirectionPin(const XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
-u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin);
-
-/* Diagnostic functions in xgpiops_selftest.c */
-s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr);
-
-/* Functions in xgpiops_intr.c */
-/* Bank APIs in xgpiops_intr.c */
-void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
-void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
-u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank);
-u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
-void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
- u32 IntrPolarity, u32 IntrOnAny);
-void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
- u32 *IntrPolarity, u32 *IntrOnAny);
-void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
- XGpioPs_Handler FuncPointer);
-void XGpioPs_IntrHandler(const XGpioPs *InstancePtr);
-
-/* Pin APIs in xgpiops_intr.c */
-void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
-u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin);
-
-void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin);
-u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin);
-u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin);
-
-/* Functions in xgpiops_sinit.c */
-XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/23/f08ebf555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/23/f08ebf555243001d18b399c1eb9b3628
deleted file mode 100644
index 6719ab0..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/23/f08ebf555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,62 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file vectors.h
-*
-* This file contains the C level vector prototypes for the ARM Cortex A9 core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 10/20/10 Initial version, moved over from bsp area
-* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#ifndef _VECTORS_H_
-#define _VECTORS_H_
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void FIQInterrupt(void);
-void IRQInterrupt(void);
-#if !defined (__aarch64__)
-void SWInterrupt(void);
-void DataAbortInterrupt(void);
-void PrefetchAbortInterrupt(void);
-void UndefinedException(void);
-#else
-void SynchronousInterrupt(void);
-void SErrorInterrupt(void);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* protection macro */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/24/107a02585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/24/107a02585243001d18b399c1eb9b3628
deleted file mode 100644
index a3d5ae4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/24/107a02585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,399 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xqspips_hw.h
-* @addtogroup qspips_v3_9
-* @{
-*
-* This header file contains the identifiers and basic HW access driver
-* functions (or macros) that can be used to access the device. Other driver
-* functions are defined in xqspips.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00 sdm 11/25/10 First release
-* 2.00a ka 07/25/12 Added a few register defines for CR 670297
-* and removed some defines of reserved fields for
-* CR 671468
-* Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
-* bit in Configuration register.
-* 2.01a sg 02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
-* which need write to clear. Removed Read zeros mask from
-* LQSPI Config register.
-* 2.03a hk 08/22/13 Added prototypes of API's for QSPI reset and
-* linear mode initialization for boot. Added related
-* constant definitions.
-* 3.1 hk 08/13/14 Changed definition of CR reset value masks to set/reset
-* required bits leaving reserved bits untouched. CR# 796813.
-* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
-* controller does not update FIFO status flags as expected
-* when thresholds are used.
-* 3.6 akm 03/28/19 Fixed memory leak issue while reading from qspi.(CR#1016357)
-*
-*
-*
-******************************************************************************/
-#ifndef XQSPIPS_HW_H /* prevent circular inclusions */
-#define XQSPIPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets from the base address of an QSPI device.
- * @{
- */
-#define XQSPIPS_CR_OFFSET 0x00 /**< Configuration Register */
-#define XQSPIPS_SR_OFFSET 0x04 /**< Interrupt Status */
-#define XQSPIPS_IER_OFFSET 0x08 /**< Interrupt Enable */
-#define XQSPIPS_IDR_OFFSET 0x0c /**< Interrupt Disable */
-#define XQSPIPS_IMR_OFFSET 0x10 /**< Interrupt Enabled Mask */
-#define XQSPIPS_ER_OFFSET 0x14 /**< Enable/Disable Register */
-#define XQSPIPS_DR_OFFSET 0x18 /**< Delay Register */
-#define XQSPIPS_TXD_00_OFFSET 0x1C /**< Transmit 4-byte inst/data */
-#define XQSPIPS_RXD_OFFSET 0x20 /**< Data Receive Register */
-#define XQSPIPS_SICR_OFFSET 0x24 /**< Slave Idle Count */
-#define XQSPIPS_TXWR_OFFSET 0x28 /**< Transmit FIFO Watermark */
-#define XQSPIPS_RXWR_OFFSET 0x2C /**< Receive FIFO Watermark */
-#define XQSPIPS_GPIO_OFFSET 0x30 /**< GPIO Register */
-#define XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38 /**< Loopback Delay Adjust Reg */
-#define XQSPIPS_TXD_01_OFFSET 0x80 /**< Transmit 1-byte inst */
-#define XQSPIPS_TXD_10_OFFSET 0x84 /**< Transmit 2-byte inst */
-#define XQSPIPS_TXD_11_OFFSET 0x88 /**< Transmit 3-byte inst */
-#define XQSPIPS_LQSPI_CR_OFFSET 0xA0 /**< Linear QSPI config register */
-#define XQSPIPS_LQSPI_SR_OFFSET 0xA4 /**< Linear QSPI status register */
-#define XQSPIPS_MOD_ID_OFFSET 0xFC /**< Module ID register */
-
-/* @} */
-
-/** @name Configuration Register
- *
- * This register contains various control bits that
- * affect the operation of the QSPI device. Read/Write.
- * @{
- */
-
-#define XQSPIPS_CR_IFMODE_MASK 0x80000000 /**< Flash mem interface mode */
-#define XQSPIPS_CR_ENDIAN_MASK 0x04000000 /**< Tx/Rx FIFO endianness */
-#define XQSPIPS_CR_MANSTRT_MASK 0x00010000 /**< Manual Transmission Start */
-#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start
- Enable */
-#define XQSPIPS_CR_SSFORCE_MASK 0x00004000 /**< Force Slave Select */
-#define XQSPIPS_CR_SSCTRL_MASK 0x00000400 /**< Slave Select Decode */
-#define XQSPIPS_CR_SSCTRL_SHIFT 10 /**< Slave Select Decode shift */
-#define XQSPIPS_CR_DATA_SZ_MASK 0x000000C0 /**< Size of word to be
- transferred */
-#define XQSPIPS_CR_PRESC_MASK 0x00000038 /**< Prescaler Setting */
-#define XQSPIPS_CR_PRESC_SHIFT 3 /**< Prescaler shift */
-#define XQSPIPS_CR_PRESC_MAXIMUM 0x07 /**< Prescaler maximum value */
-
-#define XQSPIPS_CR_CPHA_MASK 0x00000004 /**< Phase Configuration */
-#define XQSPIPS_CR_CPOL_MASK 0x00000002 /**< Polarity Configuration */
-
-#define XQSPIPS_CR_MSTREN_MASK 0x00000001 /**< Master Mode Enable */
-
-#define XQSPIPS_CR_HOLD_B_MASK 0x00080000 /**< HOLD_B Pin Drive Enable */
-
-#define XQSPIPS_CR_REF_CLK_MASK 0x00000100 /**< Ref clk bit - should be 0 */
-
-/* Deselect the Slave select line and set the transfer size to 32 at reset */
-#define XQSPIPS_CR_RESET_MASK_SET XQSPIPS_CR_IFMODE_MASK | \
- XQSPIPS_CR_SSCTRL_MASK | \
- XQSPIPS_CR_DATA_SZ_MASK | \
- XQSPIPS_CR_MSTREN_MASK | \
- XQSPIPS_CR_SSFORCE_MASK | \
- XQSPIPS_CR_HOLD_B_MASK
-#define XQSPIPS_CR_RESET_MASK_CLR XQSPIPS_CR_CPOL_MASK | \
- XQSPIPS_CR_CPHA_MASK | \
- XQSPIPS_CR_PRESC_MASK | \
- XQSPIPS_CR_MANSTRTEN_MASK | \
- XQSPIPS_CR_MANSTRT_MASK | \
- XQSPIPS_CR_ENDIAN_MASK | \
- XQSPIPS_CR_REF_CLK_MASK
-/* @} */
-
-
-/** @name QSPI Interrupt Registers
- *
- * QSPI Status Register
- *
- * This register holds the interrupt status flags for an QSPI device. Some
- * of the flags are level triggered, which means that they are set as long
- * as the interrupt condition exists. Other flags are edge triggered,
- * which means they are set once the interrupt condition occurs and remain
- * set until they are cleared by software. The interrupts are cleared by
- * writing a '1' to the interrupt bit position in the Status Register.
- * Read/Write.
- *
- * QSPI Interrupt Enable Register
- *
- * This register is used to enable chosen interrupts for an QSPI device.
- * Writing a '1' to a bit in this register sets the corresponding bit in the
- * QSPI Interrupt Mask register. Write only.
- *
- * QSPI Interrupt Disable Register
- *
- * This register is used to disable chosen interrupts for an QSPI device.
- * Writing a '1' to a bit in this register clears the corresponding bit in the
- * QSPI Interrupt Mask register. Write only.
- *
- * QSPI Interrupt Mask Register
- *
- * This register shows the enabled/disabled interrupts of an QSPI device.
- * Read only.
- *
- * All four registers have the same bit definitions. They are only defined once
- * for each of the Interrupt Enable Register, Interrupt Disable Register,
- * Interrupt Mask Register, and Channel Interrupt Status Register
- * @{
- */
-
-#define XQSPIPS_IXR_TXUF_MASK 0x00000040 /**< QSPI Tx FIFO Underflow */
-#define XQSPIPS_IXR_RXFULL_MASK 0x00000020 /**< QSPI Rx FIFO Full */
-#define XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010 /**< QSPI Rx FIFO Not Empty */
-#define XQSPIPS_IXR_TXFULL_MASK 0x00000008 /**< QSPI Tx FIFO Full */
-#define XQSPIPS_IXR_TXOW_MASK 0x00000004 /**< QSPI Tx FIFO Overwater */
-#define XQSPIPS_IXR_RXOVR_MASK 0x00000001 /**< QSPI Rx FIFO Overrun */
-#define XQSPIPS_IXR_DFLT_MASK 0x00000025 /**< QSPI default interrupts
- mask */
-#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041 /**< Interrupts which
- need write to clear */
-#define XQSPIPS_ISR_RESET_STATE 0x00000004 /**< Default to tx/rx empty */
-#define XQSPIPS_IXR_DISABLE_ALL 0x0000007D /**< Disable all interrupts */
-/* @} */
-
-
-/** @name Enable Register
- *
- * This register is used to enable or disable an QSPI device.
- * Read/Write
- * @{
- */
-#define XQSPIPS_ER_ENABLE_MASK 0x00000001 /**< QSPI Enable Bit Mask */
-/* @} */
-
-
-/** @name Delay Register
- *
- * This register is used to program timing delays in
- * slave mode. Read/Write
- * @{
- */
-#define XQSPIPS_DR_NSS_MASK 0xFF000000 /**< Delay to de-assert slave select
- between two words mask */
-#define XQSPIPS_DR_NSS_SHIFT 24 /**< Delay to de-assert slave select
- between two words shift */
-#define XQSPIPS_DR_BTWN_MASK 0x00FF0000 /**< Delay Between Transfers
- mask */
-#define XQSPIPS_DR_BTWN_SHIFT 16 /**< Delay Between Transfers shift */
-#define XQSPIPS_DR_AFTER_MASK 0x0000FF00 /**< Delay After Transfers mask */
-#define XQSPIPS_DR_AFTER_SHIFT 8 /**< Delay After Transfers shift */
-#define XQSPIPS_DR_INIT_MASK 0x000000FF /**< Delay Initially mask */
-/* @} */
-
-/** @name Slave Idle Count Registers
- *
- * This register defines the number of pclk cycles the slave waits for a the
- * QSPI clock to become stable in quiescent state before it can detect the start
- * of the next transfer in CPHA = 1 mode.
- * Read/Write
- *
- * @{
- */
-#define XQSPIPS_SICR_MASK 0x000000FF /**< Slave Idle Count Mask */
-/* @} */
-
-
-/** @name Transmit FIFO Watermark Register
- *
- * This register defines the watermark setting for the Transmit FIFO.
- *
- * @{
- */
-#define XQSPIPS_TXWR_MASK 0x0000003F /**< Transmit Watermark Mask */
-#define XQSPIPS_TXWR_RESET_VALUE 0x00000001 /**< Transmit Watermark
- * register reset value */
-
-/* @} */
-
-/** @name Receive FIFO Watermark Register
- *
- * This register defines the watermark setting for the Receive FIFO.
- *
- * @{
- */
-#define XQSPIPS_RXWR_MASK 0x0000003F /**< Receive Watermark Mask */
-#define XQSPIPS_RXWR_RESET_VALUE 0x00000001 /**< Receive Watermark
- * register reset value */
-
-/* @} */
-
-/** @name FIFO Depth
- *
- * This macro provides the depth of transmit FIFO and receive FIFO.
- *
- * @{
- */
-#define XQSPIPS_FIFO_DEPTH 63 /**< FIFO depth (words) */
-/* @} */
-
-
-/** @name Linear QSPI Configuration Register
- *
- * This register contains various control bits that
- * affect the operation of the Linear QSPI controller. Read/Write.
- *
- * @{
- */
-#define XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */
-#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */
-#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Separate memory bus */
-#define XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */
-#define XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */
-#define XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */
-#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O
- or quad I/O */
-#define XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700 /**< Number of dummy bytes
- between addr and return
- read data */
-#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */
-#define XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B /**< Default CR value */
-/* @} */
-
-/** @name Linear QSPI Status Register
- *
- * This register contains various status bits of the Linear QSPI controller.
- * Read/Write.
- *
- * @{
- */
-#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004 /**< AXI Data FSM Error
- received */
-#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002 /**< AXI write command
- received */
-/* @} */
-
-
-/** @name Loopback Delay Adjust Register
- *
- * This register contains various bit masks of Loopback Delay Adjust Register.
- *
- * @{
- */
-
-#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */
-
-/* @} */
-
-
-/** @name SLCR Register
- *
- * Register offsets from SLCR base address.
- *
- * @{
- */
-
-#define SLCR_LOCK 0x00000004 /**< SLCR Write Protection Lock */
-#define SLCR_UNLOCK 0x00000008 /**< SLCR Write Protection Unlock */
-#define LQSPI_RST_CTRL 0x00000230 /**< Quad SPI Software Reset Control */
-#define SLCR_LOCKSTA 0x0000000C /**< SLCR Write Protection status */
-
-/* @} */
-
-
-/** @name SLCR Register
- *
- * Bit Masks of above SLCR Registers .
- *
- * @{
- */
-
-#ifndef XPAR_XSLCR_0_BASEADDR
-#define XPAR_XSLCR_0_BASEADDR 0xF8000000
-#endif
-#define SLCR_LOCK_MASK 0x767B /**< Write Protection Lock mask*/
-#define SLCR_UNLOCK_MASK 0xDF0D /**< SLCR Write Protection Unlock */
-#define LQSPI_RST_CTRL_MASK 0x3 /**< Quad SPI Software Reset Control */
-
-/* @} */
-
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XQspiPs_In32 Xil_In32
-#define XQspiPs_Out32 Xil_Out32
-#define XQSPIPS_DUMMY_TX_DATA 0xFFFFFFFF
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-#define XQspiPs_ReadReg(BaseAddress, RegOffset) \
- XQspiPs_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u32 RegisterValue)
-*
-******************************************************************************/
-#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Functions implemented in xqspips_hw.c
- */
-void XQspiPs_ResetHw(u32 BaseAddress);
-void XQspiPs_LinearInit(u32 BaseAddress);
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/24/80b3bb545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/24/80b3bb545243001d18b399c1eb9b3628
deleted file mode 100644
index 2e5cbd5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/24/80b3bb545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,146 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xgpiops_hw.h
-* @addtogroup gpiops_v3_9
-* @{
-*
-* This header file contains the identifiers and basic driver functions (or
-* macros) that can be used to access the device. Other driver functions
-* are defined in xgpiops.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------
-* 1.00a sv 01/15/10 First Release
-* 1.02a hk 08/22/13 Added low level reset API function prototype and
-* related constant definitions
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/13/15 Corrected reset values of banks.
-* 3.5 sne 03/14/19 Added versal support.
-*
-*
-******************************************************************************/
-#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
-#define XGPIOPS_HW_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register offsets for the GPIO. Each register is 32 bits.
- * @{
- */
-#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /**< Mask and Data Register LSW, WO */
-#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /**< Mask and Data Register MSW, WO */
-#define XGPIOPS_DATA_OFFSET 0x00000040U /**< Data Register, RW */
-#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /**< Data Register - Input, RO */
-#define XGPIOPS_DIRM_OFFSET 0x00000204U /**< Direction Mode Register, RW */
-#define XGPIOPS_OUTEN_OFFSET 0x00000208U /**< Output Enable Register, RW */
-#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /**< Interrupt Mask Register, RO */
-#define XGPIOPS_INTEN_OFFSET 0x00000210U /**< Interrupt Enable Register, WO */
-#define XGPIOPS_INTDIS_OFFSET 0x00000214U /**< Interrupt Disable Register, WO*/
-#define XGPIOPS_INTSTS_OFFSET 0x00000218U /**< Interrupt Status Register, RO */
-#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /**< Interrupt Type Register, RW */
-#define XGPIOPS_INTPOL_OFFSET 0x00000220U /**< Interrupt Polarity Register, RW */
-#define XGPIOPS_INTANY_OFFSET 0x00000224U /**< Interrupt On Any Register, RW */
-/** @} */
-
-/** @name Register offsets for each Bank.
- * @{
- */
-#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /**< Data/Mask Registers offset */
-#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /**< Data Registers offset */
-#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /**< Registers offset */
-/** @} */
-
-/* For backwards compatibility */
-#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40 /**< Mask for backward support */
-
-/** @name Interrupt type reset values for each bank
- * @{
- */
-#ifdef XPAR_PSU_GPIO_0_BASEADDR
-#define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-#define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-#define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-#else
-#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /**< Resets specific to Zynq */
-#define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU /**< Resets specific to Zynq */
-#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU /**< Resets specific to Zynq */
-#endif
-
-#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /**< Reset common to both platforms */
-#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-/** @} */
-#define XGPIOPS_PS_GPIO_BASEADDR 0xFF0B0000U /**< Flag for Base Address for PS_GPIO in Versal */
-#define XGPIOPS_ZERO 0U /**< Flag for 0 Value */
-#define XGPIOPS_ONE 1U /**< Flag for 1 Value */
-#define XGPIOPS_TWO 2U /**< Flag for 2 Value */
-#define XGPIOPS_THREE 3U /**< Flag for 3 Value */
-#define XGPIOPS_FOUR 4U /**< Flag for 4 Value */
-#define XGPIOPS_SIX 6U /**< Flag for 6 Value */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* This macro reads the given register.
-*
-* @param BaseAddr is the base address of the device.
-* @param RegOffset is the register offset to be read.
-*
-* @return The 32-bit value of the register
-*
-* @note None.
-*
-*****************************************************************************/
-#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + (u32)(RegOffset))
-
-/****************************************************************************/
-/**
-*
-* This macro writes to the given register.
-*
-* @param BaseAddr is the base address of the device.
-* @param RegOffset is the offset of the register to be written.
-* @param Data is the 32-bit value to write to the register.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
-
-/************************** Function Prototypes ******************************/
-
-void XGpioPs_ResetHw(UINTPTR BaseAddress);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XGPIOPS_HW_H */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/24/a1ba17595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/24/a1ba17595243001d18b399c1eb9b3628
deleted file mode 100644
index 3dc57c3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/24/a1ba17595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,325 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2018 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xparameters_ps.h
-*
-* @addtogroup r5_peripheral_definitions Cortex R5 peripheral definitions
-*
-* The xparameters_ps.h file contains the canonical definitions and constant
-* declarations for peripherals within hardblock, attached to the ARM Cortex R5
-* core. These definitions can be used by drivers or applications to access the
-* peripherals.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 7.00 mus 01/25/18 Initial version
-* mn 03/26/18 Change Interrupt IDs for versal
-* mn 03/26/18 Update SLCR base address
-* pm 02/04/20 Add Interrupt IDs for usb-versal
-* sne 03/26/20 Add Interrupt ID's for WWDT
-* pm 03/24/20 Add wakeup Interrupt IDs for usb-versal
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 10/20/09 Initial version, moved over from bsp area
-* 6.0 mus 27/07/16 Consolidated vectors for a53,a9 and r5 processor
-* and added UndefinedException for a53 32 bit and r5
-* processor
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "xil_exception.h"
-#include "vectors.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-typedef struct {
- Xil_ExceptionHandler Handler;
- void *Data;
-} XExc_VectorTableEntry;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-extern XExc_VectorTableEntry XExc_VectorTable[];
-
-/************************** Function Prototypes ******************************/
-
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the FIQ interrupt called from the vectors.s
-* file.
-*
-* @return None.
-*
-******************************************************************************/
-void FIQInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[
- XIL_EXCEPTION_ID_FIQ_INT].Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the IRQ interrupt called from the vectors.s
-* file.
-*
-* @return None.
-*
-******************************************************************************/
-void IRQInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[
- XIL_EXCEPTION_ID_IRQ_INT].Data);
-}
-
-#if !defined (__aarch64__)
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the Undefined exception called from the
-* vectors.s file.
-*
-* @return None.
-*
-******************************************************************************/
-void UndefinedException(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_UNDEFINED_INT].Handler(XExc_VectorTable[
- XIL_EXCEPTION_ID_UNDEFINED_INT].Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the SW Interrupt called from the vectors.s
-* file.
-*
-* @return None.
-*
-******************************************************************************/
-void SWInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_SWI_INT].Handler(XExc_VectorTable[
- XIL_EXCEPTION_ID_SWI_INT].Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the DataAbort Interrupt called from the
-* vectors.s file.
-*
-* @return None.
-*
-******************************************************************************/
-void DataAbortInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Handler(
- XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the PrefetchAbort Interrupt called from the
-* vectors.s file.
-*
-* @return None.
-*
-******************************************************************************/
-void PrefetchAbortInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler(
- XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data);
-}
-#else
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the Synchronous Interrupt called from the vectors.s
-* file.
-*
-* @return None.
-*
-******************************************************************************/
-void SynchronousInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_SYNC_INT].Handler(XExc_VectorTable[
- XIL_EXCEPTION_ID_SYNC_INT].Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the SError Interrupt called from the
-* vectors.s file.
-*
-* @return None.
-*
-******************************************************************************/
-void SErrorInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Handler(
- XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Data);
-}
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/25/6494b0585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/25/6494b0585243001d18b399c1eb9b3628
deleted file mode 100644
index f673ff3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/25/6494b0585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,34 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#include
-#include
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) int _kill(pid_t pid, int sig);
-}
-#endif
-
-/*
- * kill -- go out via exit...
- */
-
-__attribute__((weak)) int kill(pid_t pid, int sig)
-{
- if(pid == 1) {
- _exit(sig);
- }
- return 0;
-}
-
-__attribute__((weak)) int _kill(pid_t pid, int sig)
-{
- if(pid == 1) {
- _exit(sig);
- }
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/25/a0a2a4575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/25/a0a2a4575243001d18b399c1eb9b3628
deleted file mode 100644
index 0cdfc1e..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/25/a0a2a4575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,156 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xscuwdt_hw.h
-* @addtogroup scuwdt_v2_4
-* @{
-*
-* This file contains the hardware interface to the Xilinx SCU private Watch Dog
-* Timer (XSCUWDT).
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
-* of 0x20 as the base address obtained from the tools
-* starts at 0x20.
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-#ifndef XSCUWDT_HW_H /**< prevent circular inclusions */
-#define XSCUWDT_HW_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- * Offsets of registers from the start of the device. The WDT registers start at
- * an offset 0x20
- * @{
- */
-
-#define XSCUWDT_LOAD_OFFSET 0x00U /**< Watchdog Load Register */
-#define XSCUWDT_COUNTER_OFFSET 0x04U /**< Watchdog Counter Register */
-#define XSCUWDT_CONTROL_OFFSET 0x08U /**< Watchdog Control Register */
-#define XSCUWDT_ISR_OFFSET 0x0CU /**< Watchdog Interrupt Status Register */
-#define XSCUWDT_RST_STS_OFFSET 0x10U /**< Watchdog Reset Status Register */
-#define XSCUWDT_DISABLE_OFFSET 0x14U /**< Watchdog Disable Register */
-/* @} */
-
-/** @name Watchdog Control register
- * This register bits control the prescaler, WD/Timer mode, Intr enable,
- * auto-reload, watchdog enable.
- * @{
- */
-
-#define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
-#define XSCUWDT_CONTROL_PRESCALER_SHIFT 8U
-#define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008U /**< Watchdog/Timer mode */
-#define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004U /**< Intr enable (in
- timer mode) */
-#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload (in
- timer mode) */
-#define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001U /**< Watchdog enable */
-/* @} */
-
-/** @name Interrupt Status register
- * This register indicates the Counter register has reached zero in Counter
- * mode.
- * @{
- */
-
-#define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
-/*@}*/
-
-/** @name Reset Status register
- * This register indicates the Counter register has reached zero in Watchdog
- * mode and a reset request is sent.
- * @{
- */
-
-#define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001U /**< Time out occurred */
-/*@}*/
-
-/** @name Disable register
- * This register is used to switch from watchdog mode to timer mode.
- * The software must write 0x12345678 and 0x87654321 successively to the
- * Watchdog Disable Register so that the watchdog mode bit in the Watchdog
- * Control Register is set to zero.
- * @{
- */
-#define XSCUWDT_DISABLE_VALUE1 0x12345678U /**< Watchdog mode disable
- value 1 */
-#define XSCUWDT_DISABLE_VALUE2 0x87654321U /**< Watchdog mode disable
- value 2 */
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note C-style signature:
-* u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuWdt_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + ((u32)RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/25/f009f0545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/25/f009f0545243001d18b399c1eb9b3628
deleted file mode 100644
index 5feeb49..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/25/f009f0545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,39 +0,0 @@
-DRIVER_LIB_VERSION = 1.0
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I$(INCLUDEDIR)
-
-SRCFILES:=$(wildcard *.c)
-
-OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
-
-libs: $(OBJECTS)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf $(DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/26/21e3f1585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/26/21e3f1585243001d18b399c1eb9b3628
deleted file mode 100644
index 10366fb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/26/21e3f1585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,436 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_misc_psreset_api.c
-*
-* This file contains the implementation of the reset sequence for various
-* zynq ps devices like DDR,OCM,Slcr,Ethernet,Usb.. controllers. The reset
-* sequence provided to the interfaces is based on the provision in
-* slcr reset functional block.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00b kpc 03/07/13 First release
-* 5.4 pkp 09/11/15 Change the description for XOcm_Remap function
-*
-*
-******************************************************************************/
-
-
-/***************************** Include Files *********************************/
-#include "xil_misc_psreset_api.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for ddr reset.
-*
-*
-* @return N/A.
-*
-******************************************************************************/
-void XDdr_ResetHw(void)
-{
- u32 RegVal;
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert and deassert the ddr softreset bit */
- RegVal = Xil_In32(XDDRC_CTRL_BASEADDR);
- RegVal &= (u32)(~XDDRPS_CTRL_RESET_MASK);
- Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
- RegVal |= ((u32)XDDRPS_CTRL_RESET_MASK);
- Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
-
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for remapping the ocm memory region
-* to postbootrom state.
-*
-* @return N/A.
-*
-******************************************************************************/
-void XOcm_Remap(void)
-{
- u32 RegVal;
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Map the ocm region to postbootrom state */
- RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR);
- RegVal = (RegVal & (u32)(~XSLCR_OCM_CFG_HIADDR_MASK)) | (u32)XSLCR_OCM_CFG_RESETVAL;
- Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for SMC reset sequence
-*
-* @param BaseAddress of the interface
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSmc_ResetHw(u32 BaseAddress)
-{
- u32 RegVal;
-
- /* Clear the interuupts */
- RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET);
- RegVal = RegVal | (u32)XSMC_MEMC_CLR_CONFIG_MASK;
- Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal);
- /* Clear the idle counter registers */
- Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0U);
- Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0U);
- /* Update the ecc registers with reset values */
- Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET,
- XSMC_ECC_MEMCFG1_RESET_VAL);
- Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD1_OFFSET,
- XSMC_ECC_MEMCMD1_RESET_VAL);
- Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD2_OFFSET,
- XSMC_ECC_MEMCMD2_RESET_VAL);
-
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for updating the slcr mio registers
-* with reset values
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_MioWriteResetValues(void)
-{
- u32 i;
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Update all the MIO registers with reset values */
- for (i=0U; i<=1U;i++)
- {
- Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
- XSLCR_MIO_PIN_00_RESET_VAL);
- }
- for (; i<=8U;i++)
- {
- Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
- XSLCR_MIO_PIN_02_RESET_VAL);
- }
- for (; i<=53U ;i++)
- {
- Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
- XSLCR_MIO_PIN_00_RESET_VAL);
- }
-
-
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for updating the slcr pll registers
-* with reset values
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_PllWriteResetValues(void)
-{
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
-
- /* update the pll control registers with reset values */
- Xil_Out32(XSLCR_IO_PLL_CTRL_ADDR, XSLCR_IO_PLL_CTRL_RESET_VAL);
- Xil_Out32(XSLCR_ARM_PLL_CTRL_ADDR, XSLCR_ARM_PLL_CTRL_RESET_VAL);
- Xil_Out32(XSLCR_DDR_PLL_CTRL_ADDR, XSLCR_DDR_PLL_CTRL_RESET_VAL);
- /* update the pll config registers with reset values */
- Xil_Out32(XSLCR_IO_PLL_CFG_ADDR, XSLCR_IO_PLL_CFG_RESET_VAL);
- Xil_Out32(XSLCR_ARM_PLL_CFG_ADDR, XSLCR_ARM_PLL_CFG_RESET_VAL);
- Xil_Out32(XSLCR_DDR_PLL_CFG_ADDR, XSLCR_DDR_PLL_CFG_RESET_VAL);
- /* update the clock control registers with reset values */
- Xil_Out32(XSLCR_ARM_CLK_CTRL_ADDR, XSLCR_ARM_CLK_CTRL_RESET_VAL);
- Xil_Out32(XSLCR_DDR_CLK_CTRL_ADDR, XSLCR_DDR_CLK_CTRL_RESET_VAL);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for disabling the level shifters
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_DisableLevelShifters(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Disable the level shifters */
- RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_LVL_SHFTR_EN_MASK);
- Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal);
-
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for OCM software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_OcmReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_OCM_RST_CTRL_VAL);
- Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_OCM_RST_CTRL_VAL);
- Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for Ethernet software reset from
-* the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_EmacPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_GEM_RST_CTRL_VAL);
- Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_GEM_RST_CTRL_VAL);
- Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for USB software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_UsbPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_USB_RST_CTRL_VAL);
- Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_USB_RST_CTRL_VAL);
- Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for QSPI software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_QspiPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_QSPI_RST_CTRL_VAL);
- Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_QSPI_RST_CTRL_VAL);
- Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for SPI software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_SpiPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_SPI_RST_CTRL_VAL);
- Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_SPI_RST_CTRL_VAL);
- Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for i2c software reset from the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_I2cPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_I2C_RST_CTRL_VAL);
- Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_I2C_RST_CTRL_VAL);
- Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for UART software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_UartPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_UART_RST_CTRL_VAL);
- Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_UART_RST_CTRL_VAL);
- Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for CAN software reset from slcr
-* registers
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_CanPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_CAN_RST_CTRL_VAL);
- Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_CAN_RST_CTRL_VAL);
- Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for SMC software reset from the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_SmcPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_SMC_RST_CTRL_VAL);
- Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_SMC_RST_CTRL_VAL);
- Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for DMA controller software reset
-* from the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_DmaPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_DMAC_RST_CTRL_VAL);
- Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_DMAC_RST_CTRL_VAL);
- Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for Gpio AMBA software reset from
-* the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_GpioPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_GPIO_RST_CTRL_VAL);
- Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_GPIO_RST_CTRL_VAL);
- Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/26/c1b945575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/26/c1b945575243001d18b399c1eb9b3628
deleted file mode 100644
index 0cec19b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/26/c1b945575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,61 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file nor.h
-*
-* This file contains the interface for the NOR FLASH functionality
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 01/10/10 Initial release
-* 10.00a kc 08/04/14 Fix for CR#809336 - Removed smc.h
-*
-*
-*
-* @note
-*
-******************************************************************************/
-#ifndef ___NOR_H___
-#define ___NOR_H___
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-/************************** Constant Definitions *****************************/
-
-#define XPS_NOR_BASEADDR XPS_PARPORT0_BASEADDR
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-
-void InitNor(void);
-
-u32 NorAccess( u32 SourceAddress,
- u32 DestinationAddress,
- u32 LengthBytes);
-
-/************************** Variable Definitions *****************************/
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* ___NOR_H___ */
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/27/02d3c9565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/27/02d3c9565243001d18b399c1eb9b3628
deleted file mode 100644
index efa60da..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/27/02d3c9565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,66 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************
-*
-* @file sleep.c
-*
-* This function provides a second delay using the Global Timer register in
-* the ARM Cortex A9 MP core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm 11/11/09 First release
-* 3.07a sgd 07/05/12 Updated sleep function to make use Global
-* 6.0 asa 08/15/16 Updated the sleep signature. Fix for CR#956899.
-* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
-* implementation. Now sleep routines will use Timer
-* specified by the user (i.e. Global timer/TTC timer)
-*
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "sleep.h"
-#include "xtime_l.h"
-#include "xparameters.h"
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#include "xil_sleeptimer.h"
-#endif
-
-/*****************************************************************************/
-/*
-*
-* This API is used to provide delays in seconds
-*
-* @param seconds requested
-*
-* @return 0 always
-*
-* @note None.
-*
-****************************************************************************/
-unsigned sleep_A9(unsigned int seconds)
-{
-#if defined (SLEEP_TIMER_BASEADDR)
- Xil_SleepTTCCommon(seconds, COUNTS_PER_SECOND);
-#else
- XTime tEnd, tCur;
-
- XTime_GetTime(&tCur);
- tEnd = tCur + (((XTime) seconds) * COUNTS_PER_SECOND);
- do
- {
- XTime_GetTime(&tCur);
- } while (tCur < tEnd);
-#endif
-
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/27/119ef6585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/27/119ef6585243001d18b399c1eb9b3628
deleted file mode 100644
index 379023c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/27/119ef6585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,154 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xl2cc.h
-*
-* This file contains the address definitions for the PL310 Level-2 Cache
-* Controller.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 02/01/10 Initial version
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef _XL2CC_H_
-#define _XL2CC_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-/* L2CC Register Offsets */
-#define XPS_L2CC_ID_OFFSET 0x0000U
-#define XPS_L2CC_TYPE_OFFSET 0x0004U
-#define XPS_L2CC_CNTRL_OFFSET 0x0100U
-#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104U
-#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108U
-#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010CU
-
-#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200U
-#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204U
-#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208U
-#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020CU
-#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210U
-
-#define XPS_L2CC_IER_OFFSET 0x0214U /* Interrupt Mask */
-#define XPS_L2CC_IPR_OFFSET 0x0218U /* Masked interrupt status */
-#define XPS_L2CC_ISR_OFFSET 0x021CU /* Raw Interrupt Status */
-#define XPS_L2CC_IAR_OFFSET 0x0220U /* Interrupt Clear */
-
-#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730U /* Cache Sync */
-#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740U /* Dummy Register for Cache Sync */
-#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770U /* Cache Invalid by PA */
-#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077CU /* Cache Invalid by Way */
-#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0U /* Cache Clean by PA */
-#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8U /* Cache Clean by Index */
-#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BCU /* Cache Clean by Way */
-#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0U /* Cache Invalidate and Clean by PA */
-#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8U /* Cache Invalidate and Clean by Index */
-#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FCU /* Cache Invalidate and Clean by Way */
-
-#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900U /* Cache Data Lockdown 0 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904U /* Cache Instruction Lockdown 0 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908U /* Cache Data Lockdown 1 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090CU /* Cache Instruction Lockdown 1 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910U /* Cache Data Lockdown 2 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914U /* Cache Instruction Lockdown 2 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918U /* Cache Data Lockdown 3 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091CU /* Cache Instruction Lockdown 3 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920U /* Cache Data Lockdown 4 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924U /* Cache Instruction Lockdown 4 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928U /* Cache Data Lockdown 5 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092CU /* Cache Instruction Lockdown 5 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930U /* Cache Data Lockdown 6 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934U /* Cache Instruction Lockdown 6 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938U /* Cache Data Lockdown 7 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093CU /* Cache Instruction Lockdown 7 by Way */
-
-#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U /* Cache Lockdown Line Enable */
-#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954U /* Cache Unlock All Lines by Way */
-
-#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00U /* Start of address filtering */
-#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04U /* Start of address filtering */
-
-#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40U /* Debug Control Register */
-
-/* XPS_L2CC_CNTRL_OFFSET bit masks */
-#define XPS_L2CC_ENABLE_MASK 0x00000001U /* enables the L2CC */
-
-/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */
-#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000U /* Early BRESP Enable */
-#define XPS_L2CC_AUX_IPFE_MASK 0x20000000U /* Instruction Prefetch Enable */
-#define XPS_L2CC_AUX_DPFE_MASK 0x10000000U /* Data Prefetch Enable */
-#define XPS_L2CC_AUX_NSIC_MASK 0x08000000U /* Non-secure interrupt access control */
-#define XPS_L2CC_AUX_NSLE_MASK 0x04000000U /* Non-secure lockdown enable */
-#define XPS_L2CC_AUX_CRP_MASK 0x02000000U /* Cache replacement policy */
-#define XPS_L2CC_AUX_FWE_MASK 0x01800000U /* Force write allocate */
-#define XPS_L2CC_AUX_SAOE_MASK 0x00400000U /* Shared attribute override enable */
-#define XPS_L2CC_AUX_PE_MASK 0x00200000U /* Parity enable */
-#define XPS_L2CC_AUX_EMBE_MASK 0x00100000U /* Event monitor bus enable */
-#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000U /* Way-size */
-#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000U /* Associativity */
-#define XPS_L2CC_AUX_SAIE_MASK 0x00002000U /* Shared attribute invalidate enable */
-#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000U /* Exclusive cache configuration */
-#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800U /* Store buffer device limitation Enable */
-#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400U /* High Priority for SO and Dev Reads Enable */
-#define XPS_L2CC_AUX_FLZE_MASK 0x00000001U /* Full line of zero enable */
-
-#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000U /* Enable all prefetching, */
- /* Cache replacement policy, Parity enable, */
- /* Event monitor bus enable and Way Size (64 KB) */
-#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFFU /* */
-
-#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111U /* latency for TAG RAM */
-#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121U /* latency for DATA RAM */
-
-/* Interrupt bit masks */
-#define XPS_L2CC_IXR_DECERR_MASK 0x00000100U /* DECERR from L3 */
-#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080U /* SLVERR from L3 */
-#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040U /* Error on L2 data RAM (Read) */
-#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020U /* Error on L2 tag RAM (Read) */
-#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010U /* Error on L2 data RAM (Write) */
-#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008U /* Error on L2 tag RAM (Write) */
-#define XPS_L2CC_IXR_PARRD_MASK 0x00000004U /* Parity Error on L2 data RAM (Read) */
-#define XPS_L2CC_IXR_PARRT_MASK 0x00000002U /* Parity Error on L2 tag RAM (Read) */
-#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001U /* Event Counter1/0 Overflow Increment */
-
-/* Address filtering mask and enable bit */
-#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000U /* Address filtering valid bits*/
-#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U /* Address filtering enable bit*/
-
-/* Debug control bits */
-#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004U /* Debug SPIDEN bit */
-#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002U /* Debug DWB bit, forces write through */
-#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002U /* Debug DCL bit, disables cache line fill */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* protection macro */
-
-/**
- *@endcond
- */
\ No newline at end of file
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/27/31afbc525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/27/31afbc525243001d18b399c1eb9b3628
deleted file mode 100644
index d21e13a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/27/31afbc525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,92 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2012 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_mmu.h
-*
-* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions
-*
-* MMU functions equip users to enable MMU, disable MMU and modify default
-* memory attributes of MMU table as per the need.
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 01/12/12 Initial version
-* 4.2 pkp 07/21/14 Included xil_types.h file which contains definition for
-* u32 which resolves issue of CR#805869
-* 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-*
-*
-******************************************************************************/
-
-/**
-*@cond nocomments
-*/
-
-#ifndef XIL_MMU_H
-#define XIL_MMU_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/* Memory type */
-#define NORM_NONCACHE 0x11DE2 /* Normal Non-cacheable */
-#define STRONG_ORDERED 0xC02 /* Strongly ordered */
-#define DEVICE_MEMORY 0xC06 /* Device memory */
-#define RESERVED 0x0 /* reserved memory */
-
-/* Normal write-through cacheable shareable */
-#define NORM_WT_CACHE 0x16DEA
-
-/* Normal write back cacheable shareable */
-#define NORM_WB_CACHE 0x15DE6
-
-/* shareability attribute */
-#define SHAREABLE (0x1 << 16)
-#define NON_SHAREABLE (~(0x1 << 16))
-
-/* Execution type */
-#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0))
-
-/**
-*@endcond
-*/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
-void Xil_EnableMMU(void);
-void Xil_DisableMMU(void);
-void* Xil_MemMap(UINTPTR PhysAddr, size_t size, u32 flags);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_MMU_H */
-/**
-* @} End of "addtogroup a9_mmu_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/27/817a7a565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/27/817a7a565243001d18b399c1eb9b3628
deleted file mode 100644
index 5f39620..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/27/817a7a565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,20 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#include
-#include "xil_types.h"
-sint32 fcntl (sint32 fd, sint32 cmd, sint32 arg);
-
-/*
- * fcntl -- Manipulate a file descriptor.
- * We don't have a filesystem, so we do nothing.
- */
-sint32 fcntl (sint32 fd, sint32 cmd, sint32 arg)
-{
- (void) fd;
- (void) cmd;
- (void) arg;
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/27/e19f0f555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/27/e19f0f555243001d18b399c1eb9b3628
deleted file mode 100644
index 3438d96..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/27/e19f0f555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1 +0,0 @@
-collect (PROJECT_LIB_HEADERS xparameters_ps.h)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/27/f05aa4545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/27/f05aa4545243001d18b399c1eb9b3628
deleted file mode 100644
index ee6ac60..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/27/f05aa4545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,646 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xemacps_hw.h
-* @addtogroup emacps_v3_15
-* @{
-*
-* This header file contains identifiers and low-level driver functions (or
-* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
-* High-level driver functions are defined in xemacps.h.
-*
-* @note
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 First release.
-* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration.
-* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype
-* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
-* to 0x1fff. This fixes the CR#744902.
-* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
-* 3.0 kvn 12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
-* XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
-* 3.0 kpc 1/23/15 Corrected the extended descriptor macro values.
-* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.0 hk 03/18/15 Added support for jumbo frames.
-* Remove "used bit set" from TX error interrupt masks.
-* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
-* 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
-* 3.8 hk 09/17/18 Fix PTP interrupt masks.
-* 3.9 hk 01/23/19 Add RX watermark support
-* 3.10 hk 05/16/19 Clear status registers properly in reset
-*
-*
-******************************************************************************/
-
-#ifndef XEMACPS_HW_H /* prevent circular inclusions */
-#define XEMACPS_HW_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address
- supported */
-#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */
-
-#ifdef __aarch64__
-#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment
- on the local bus */
-#else
-
-#define XEMACPS_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment
- on the local bus */
-#endif
-#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using
- options that impose alignment
- restrictions on the buffer data on
- the local bus */
-
-/** @name Direction identifiers
- *
- * These are used by several functions and callbacks that need
- * to specify whether an operation specifies a send or receive channel.
- * @{
- */
-#define XEMACPS_SEND 1U /**< send direction */
-#define XEMACPS_RECV 2U /**< receive direction */
-/*@}*/
-
-/** @name MDC clock division
- * currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
- * @{
- */
-typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
- MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
-} XEmacPs_MdcDiv;
-
-/*@}*/
-
-#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
- bytes, 64, 128, ... 10240 */
-#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
-
-#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a
- unit, this is HW setup */
-
-#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */
-#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */
-
-#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
-
-/* Register offset definitions. Unless otherwise noted, register access is
- * 32 bit. Names are self explained here.
- */
-
-#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */
-#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */
-#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */
-
-#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */
-#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */
-#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */
-#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */
-#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */
-
-#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */
-#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */
-#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */
-#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */
-
-#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */
-#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */
-#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */
-
-#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */
-
-#define XEMACPS_RXWATERMARK_OFFSET 0x0000007CU /**< RX watermark reg */
-
-#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */
-#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */
-
-#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */
-#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */
-#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */
-#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */
-#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */
-#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */
-#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */
-#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */
-
-#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */
-#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */
-#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */
-#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */
-
-#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */
-
-#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low
- reg */
-#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High
- reg */
-
-#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes
- transmitted counter */
-#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast
- Frames counter*/
-#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast
- Frame counter */
-#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted
- Counter */
-#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames
- Transmitted counter */
-#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte
- Frames Transmitted
- counter */
-#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte
- Frames Transmitted
- counter*/
-#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte
- Frames transmitted
- counter */
-#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte
- Frames transmitted
- counter */
-#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte
- Frames transmitted
- counter */
-#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than
- 1519 byte Frames
- transmitted counter */
-#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error
- counter */
-
-#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame
- Counter */
-#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame
- Counter */
-#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
- Counter */
-#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame
- Counter */
-#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission
- Frame Counter */
-#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense
- Error Counter */
-
-#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register
- Low */
-#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register
- High */
-
-#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames
- Received Counter */
-#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast
- Frames Received Counter */
-#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast
- Frames Received Counter */
-#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames
- Received Counter */
-#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames
- Received Counter */
-#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte
- Frames Received Counter */
-#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte
- Frames Received Counter */
-#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte
- Frames Received Counter */
-#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte
- Frames Received Counter */
-#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte
- Frames Received Counter */
-#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte
- Frames Received Counter */
-#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received
- Counter */
-#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received
- Counter */
-#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received
- Counter */
-#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence
- Error Counter */
-#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error
- Counter */
-#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */
-#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */
-#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error
- Counter */
-#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */
-#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error
- Counter */
-#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error
- Counter */
-#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error
- Counter */
-#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter
- offset, for clearing */
-
-#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */
-#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */
-#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond
- adjustment counter */
-#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond
- increment counter */
-#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second
- counter */
-#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
- nanosecond counter */
-#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second
- counter */
-#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
- nanosecond counter */
-#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit
- second counter */
-#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
- nanosecond counter */
-#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive
- second counter */
-#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
- nanosecond counter */
-
-#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status
- reg */
-#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address
- reg */
-#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address
- reg */
-#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base
- reg */
-#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base
- reg */
-#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable
- reg */
-#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable
- reg */
-#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask
- reg */
-
-/* Define some bit positions for registers. */
-
-/** @name network control register bit definitions
- * @{
- */
-#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from
- Rx SRAM */
-#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
- pause frame */
-#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */
-#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission
- after current frame */
-#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */
-
-#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to
- stat counters */
-#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic
- registers */
-#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic
- registers */
-#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */
-#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */
-#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */
-#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */
-/*@}*/
-
-/** @name network configuration register bit definitions
- * @{
- */
-#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
- non-standard preamble */
-#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */
-#define XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U /**< SGMII Enable */
-#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of
- FCS error */
-#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */
-#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum
- offload */
-#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
- Frames to memory */
-#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */
-#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */
-#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */
-#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from
- received frames */
-#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
-/**< RX length error discard */
-#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */
-#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */
-#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
-#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
-/**< External address match enable */
-#define XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U /**< PCS Select */
-#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */
-#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte
- frames reception */
-#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
- frames */
-#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
- frames */
-#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive
- broadcast frames */
-#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */
-#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */
-#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN
- frames */
-#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */
-#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */
-#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */
-/*@}*/
-
-/** @name network status register bit definitaions
- * @{
- */
-#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */
-#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */
-/*@}*/
-
-
-/** @name MAC address register word 1 mask
- * @{
- */
-#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32]
- bit[31:0] are in BOTTOM */
-/*@}*/
-
-
-/** @name DMA control register bit definitions
- * @{
- */
-#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */
-#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */
-#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */
-#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer
- size */
-#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer
- size */
-#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX
- checksum offload */
-#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */
-#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */
-#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */
-#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */
-#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */
-#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */
-#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */
-#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */
-/*@}*/
-
-/** @name transmit status register bit definitions
- * @{
- */
-#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */
-#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */
-#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */
-#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted
- mid frame */
-#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */
-#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */
-#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */
-#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */
-
-#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
- (u32)XEMACPS_TXSR_URUN_MASK | \
- (u32)XEMACPS_TXSR_BUFEXH_MASK | \
- (u32)XEMACPS_TXSR_RXOVR_MASK | \
- (u32)XEMACPS_TXSR_FRAMERX_MASK | \
- (u32)XEMACPS_TXSR_USEDREAD_MASK)
-/*@}*/
-
-/**
- * @name receive status register bit definitions
- * @{
- */
-#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */
-#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */
-#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */
-#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */
-
-#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
- (u32)XEMACPS_RXSR_RXOVR_MASK | \
- (u32)XEMACPS_RXSR_BUFFNA_MASK)
-
-#define XEMACPS_SR_ALL_MASK 0xFFFFFFFFU /**< Mask for full register */
-
-/*@}*/
-
-/**
- * @name Interrupt Q1 status register bit definitions
- * @{
- */
-#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */
-#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */
-
-#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
- (u32)XEMACPS_INTQ1SR_TXERR_MASK)
-
-/*@}*/
-
-/**
- * @name interrupts bit definitions
- * Bits definitions are same in XEMACPS_ISR_OFFSET,
- * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
- * @{
- */
-#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Pdelay_resp TXed */
-#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req TXed */
-#define XEMACPS_IXR_PTPPSRX_MASK 0x00800000U /**< PTP Pdelay_resp RXed */
-#define XEMACPS_IXR_PTPPDRRX_MASK 0x00400000U /**< PTP Pdelay_req RXed */
-
-#define XEMACPS_IXR_PTPSTX_MASK 0x00200000U /**< PTP Sync TXed */
-#define XEMACPS_IXR_PTPDRTX_MASK 0x00100000U /**< PTP Delay_req TXed */
-#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync RXed */
-#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req RXed */
-
-#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */
-#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached
- zero */
-#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
-#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */
-#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */
-#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */
-#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or
- no buffers*/
-#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */
-#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */
-#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */
-#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */
-#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */
-#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */
-#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */
-
-#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \
- (u32)XEMACPS_IXR_RETRY_MASK | \
- (u32)XEMACPS_IXR_URUN_MASK)
-
-
-#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \
- (u32)XEMACPS_IXR_RXUSED_MASK | \
- (u32)XEMACPS_IXR_RXOVR_MASK)
-
-/*@}*/
-
-/** @name PHY Maintenance bit definitions
- * @{
- */
-#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */
-#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */
-#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */
-#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */
-#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */
-#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */
-#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */
-#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */
-/*@}*/
-
-/** @name RX watermark bit definitions
- * @{
- */
-#define XEMACPS_RXWM_HIGH_MASK 0x0000FFFFU /**< RXWM high mask */
-#define XEMACPS_RXWM_LOW_MASK 0xFFFF0000U /**< RXWM low mask */
-#define XEMACPS_RXWM_LOW_SHFT_MSK 16U /**< Shift for RXWM low */
-/*@}*/
-
-/* Transmit buffer descriptor status words offset
- * @{
- */
-#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */
-#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */
-#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */
-
-/*
- * @}
- */
-
-/* Transmit buffer descriptor status words bit positions.
- * Transmit buffer descriptor consists of two 32-bit registers,
- * the first - word0 contains a 32-bit address pointing to the location of
- * the transmit data.
- * The following register - word1, consists of various information to control
- * the XEmacPs transmit process. After transmit, this is updated with status
- * information, whether the frame was transmitted OK or why it had failed.
- * @{
- */
-#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */
-#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */
-#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
-#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */
-#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */
-#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */
-#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
-#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */
-#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */
-/*
- * @}
- */
-
-/* Receive buffer descriptor status words bit positions.
- * Receive buffer descriptor consists of two 32-bit registers,
- * the first - word0 contains a 32-bit word aligned address pointing to the
- * address of the buffer. The lower two bits make up the wrap bit indicating
- * the last descriptor and the ownership bit to indicate it has been used by
- * the XEmacPs.
- * The following register - word1, contains status information regarding why
- * the frame was received (the filter match condition) as well as other
- * useful info.
- * @{
- */
-#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */
-#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
-#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */
-#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */
-#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address
- matched */
-#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */
-#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */
-#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */
-#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */
-#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */
-#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */
-#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */
-#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */
-#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */
-#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
-
-#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */
-#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */
-#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */
-/*
- * @}
- */
-
-/*
- * Define appropriate I/O access method to memory mapped I/O or other
- * interface if necessary.
- */
-
-#define XEmacPs_In32 Xil_In32
-#define XEmacPs_Out32 Xil_Out32
-
-
-/****************************************************************************/
-/**
-*
-* Read the given register.
-*
-* @param BaseAddress is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
- XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
-
-
-/****************************************************************************/
-/**
-*
-* Write the given register.
-*
-* @param BaseAddress is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
-* u32 Data)
-*
-*****************************************************************************/
-#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
- XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
-
-/************************** Function Prototypes *****************************/
-/*
- * Perform reset operation to the emacps interface
- */
-void XEmacPs_ResetHw(u32 BaseAddr);
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/28/112cb0525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/28/112cb0525243001d18b399c1eb9b3628
deleted file mode 100644
index fd80a0d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/28/112cb0525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,62 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_clocking.h
-*
-* The xil_clocking.h file contains clocking related functions and macros.
-* certain conditions.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 7.2 sd 12/11/19 First release
-* 7.2 sd 03/20/20 Added checking for isolation case
-*
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.00a wgr 10/10/10 First release
- *
- *
- *****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xstatus.h"
-#include "xusbps.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-extern XUsbPs_Config XUsbPs_ConfigTable[];
-
-/************************** Function Prototypes *****************************/
-
-/****************************************************************************/
-/**
-*
-* Looks up the controller configuration based on the unique controller ID. A
-* table contains the configuration info for each controller in the system.
-*
-* @param DeviceID is the ID of the controller to look up the
-* configuration for.
-*
-* @return
-* A pointer to the configuration found or NULL if the specified
-* controller ID was not found.
-*
-******************************************************************************/
-XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceID)
-{
- XUsbPs_Config *CfgPtr = NULL;
-
- int Index;
-
- for (Index = 0; Index < XPAR_XUSBPS_NUM_INSTANCES; Index++) {
- if (XUsbPs_ConfigTable[Index].DeviceID == DeviceID) {
- CfgPtr = &XUsbPs_ConfigTable[Index];
- break;
- }
- }
-
- return CfgPtr;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/29/c0c65fb75243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/29/c0c65fb75243001d18b399c1eb9b3628
deleted file mode 100644
index c63db8f..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/29/c0c65fb75243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,11 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/29/c17dde545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/29/c17dde545243001d18b399c1eb9b3628
deleted file mode 100644
index 4b6d75a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/29/c17dde545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,261 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xscutimer_hw.h
-* @addtogroup scutimer_v2_3
-* @{
-*
-* This file contains the hardware interface to the Timer.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm 03/10/10 First release
-* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
-* and interrupt registers
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-#ifndef XSCUTIMER_HW_H /* prevent circular inclusions */
-#define XSCUTIMER_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- * Offsets of registers from the start of the device
- * @{
- */
-
-#define XSCUTIMER_LOAD_OFFSET 0x00U /**< Timer Load Register */
-#define XSCUTIMER_COUNTER_OFFSET 0x04U /**< Timer Counter Register */
-#define XSCUTIMER_CONTROL_OFFSET 0x08U /**< Timer Control Register */
-#define XSCUTIMER_ISR_OFFSET 0x0CU /**< Timer Interrupt
- Status Register */
-/* @} */
-
-/** @name Timer Control register
- * This register bits control the prescaler, Intr enable,
- * auto-reload and timer enable.
- * @{
- */
-
-#define XSCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
-#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8U
-#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004U /**< Intr enable */
-#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload */
-#define XSCUTIMER_CONTROL_ENABLE_MASK 0x00000001U /**< Timer enable */
-/* @} */
-
-/** @name Interrupt Status register
- * This register indicates the Timer counter register has reached zero.
- * @{
- */
-
-#define XSCUTIMER_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Write to the timer load register. This will also update the
-* timer counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetLoadReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer load register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer load register.
-*
-* @note C-style signature:
-* u32 XScuTimer_GetLoadReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetLoadReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the timer counter register.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the counter register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetCounterReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer counter register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer counter register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetCounterReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetCounterReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the timer load register. This will also update the
-* timer counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetControlReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer load register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer load register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetControlReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetControlReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the timer counter register.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the counter register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetIntrReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer counter register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer counter register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetIntrReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetIntrReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Read from the given Timer register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note C-style signature:
-* u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuTimer_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + (RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write to the given Timer register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + (RegOffset), (Data))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/29/e105f3565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/29/e105f3565243001d18b399c1eb9b3628
deleted file mode 100644
index ea3a08c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/29/e105f3565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,133 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xl2cc_counter.c
-*
-* This file contains APIs for configuring and controlling the event counters
-* in PL310 L2 cache controller. For more information about the event counters,
-* see xl2cc_counter.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
-* inside the APIs
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include
-#include "xparameters_ps.h"
-#include "xl2cc_counter.h"
-#include "xl2cc.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void XL2cc_EventCtrReset(void);
-
-/******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @brief This function initializes the event counters in L2 Cache controller
-* with a set of event codes specified by the user.
-*
-* @param Event0: Event code for counter 0.
-* @param Event1: Event code for counter 1.
-*
-* @return None.
-*
-* @note The definitions for event codes XL2CC_* can be found in
-* xl2cc_counter.h.
-*
-*****************************************************************************/
-void XL2cc_EventCtrInit(s32 Event0, s32 Event1)
-{
-
- /* Write event code into cnt1 cfg reg */
- *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_CTRL_OFFSET)) = (((u32)Event1) << 2);
-
- /* Write event code into cnt0 cfg reg */
- *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_CTRL_OFFSET)) = (((u32)Event0) << 2);
-
- /* Reset counters */
- XL2cc_EventCtrReset();
-}
-
-
-/****************************************************************************/
-/**
-*
-* @brief This function starts the event counters in L2 Cache controller.
-*
-* @return None.
-*
-*****************************************************************************/
-void XL2cc_EventCtrStart(void)
-{
- u32 *LocalPtr;
- LocalPtr = (u32 *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET);
- XL2cc_EventCtrReset();
-
- /* Enable counter */
- /* *((volatile u32*)((void *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET))) = 1 */
- *LocalPtr = (u32)1;
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function disables the event counters in L2 Cache controller,
-* saves the counter values and resets the counters.
-*
-* @param EveCtr0: Output parameter which is used to return the value
-* in event counter 0.
-* @param EveCtr1: Output parameter which is used to return the value
-* in event counter 1.
-*
-* @return None.
-*
-*****************************************************************************/
-void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1)
-{
- /* Disable counter */
- *((volatile u32*) (XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0U;
-
- /* Save counter values */
- *EveCtr1 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_VAL_OFFSET));
- *EveCtr0 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_VAL_OFFSET));
-
- XL2cc_EventCtrReset();
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function resets the event counters in L2 Cache controller.
-*
-* @return None.
-*
-*****************************************************************************/
-void XL2cc_EventCtrReset(void)
-{
- *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0x6U;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2a/4091fa545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2a/4091fa545243001d18b399c1eb9b3628
deleted file mode 100644
index 2de567a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2a/4091fa545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1410 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xsdps_hw.h
-* @addtogroup sdps_v3_13
-* @{
-*
-* This header file contains the identifiers and basic HW access driver
-* functions (or macros) that can be used to access the device. Other driver
-* functions are defined in xsdps.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a hk/sg 10/17/13 Initial release
-* 2.5 sg 07/09/15 Added SD 3.0 features
-* kvn 07/15/15 Modified the code according to MISRAC-2012.
-* 2.7 sk 12/10/15 Added support for MMC cards.
-* sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
-* 2.8 sk 04/20/16 Added new workaround for auto tuning.
-* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
-* sk 07/16/16 Added support for UHS modes.
-* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
-* operating modes.
-* 3.1 sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
-* 3.2 sk 03/20/17 Add support for EL1 non-secure mode.
-* 3.3 mn 08/22/17 Updated for Word Access System support
-* mn 09/06/17 Added support for ARMCC toolchain
-* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
-* 3.6 mn 07/06/18 Fix Doxygen warnings for sdps driver
-* 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
-* mn 05/21/19 Set correct tap delays for Versal
-* mn 05/21/19 Disable DLL Reset code for Versal
-* mn 07/03/19 Update Input Tap Delays for Versal
-* 3.9 mn 03/03/20 Restructured the code for more readability and modularity
-*
-*
-*
-******************************************************************************/
-
-#ifndef SD_HW_H_
-#define SD_HW_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets from the base address of an SD device.
- * @{
- */
-
-#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address
- Register */
-#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET
- /**< SDMA System Address
- Low Register */
-#define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */
-#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address
- High Register */
-#define XSDPS_ARGMT2_HI_OFFSET 0x02U /**< Argument2 High Register */
-
-#define XSDPS_BLK_SIZE_OFFSET 0x04U /**< Block Size Register */
-#define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */
-#define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */
-#define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET
- /**< Argument1 Register */
-#define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */
-
-#define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */
-#define XSDPS_CMD_OFFSET 0x0EU /**< Command Register */
-#define XSDPS_RESP0_OFFSET 0x10U /**< Response0 Register */
-#define XSDPS_RESP1_OFFSET 0x14U /**< Response1 Register */
-#define XSDPS_RESP2_OFFSET 0x18U /**< Response2 Register */
-#define XSDPS_RESP3_OFFSET 0x1CU /**< Response3 Register */
-#define XSDPS_BUF_DAT_PORT_OFFSET 0x20U /**< Buffer Data Port */
-#define XSDPS_PRES_STATE_OFFSET 0x24U /**< Present State */
-#define XSDPS_HOST_CTRL1_OFFSET 0x28U /**< Host Control 1 */
-#define XSDPS_POWER_CTRL_OFFSET 0x29U /**< Power Control */
-#define XSDPS_BLK_GAP_CTRL_OFFSET 0x2AU /**< Block Gap Control */
-#define XSDPS_WAKE_UP_CTRL_OFFSET 0x2BU /**< Wake Up Control */
-#define XSDPS_CLK_CTRL_OFFSET 0x2CU /**< Clock Control */
-#define XSDPS_TIMEOUT_CTRL_OFFSET 0x2EU /**< Timeout Control */
-#define XSDPS_SW_RST_OFFSET 0x2FU /**< Software Reset */
-#define XSDPS_NORM_INTR_STS_OFFSET 0x30U /**< Normal Interrupt
- Status Register */
-#define XSDPS_ERR_INTR_STS_OFFSET 0x32U /**< Error Interrupt
- Status Register */
-#define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34U /**< Normal Interrupt
- Status Enable Register */
-#define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36U /**< Error Interrupt
- Status Enable Register */
-#define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38U /**< Normal Interrupt
- Signal Enable Register */
-#define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3AU /**< Error Interrupt
- Signal Enable Register */
-
-#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3CU /**< Auto CMD12 Error Status
- Register */
-#define XSDPS_HOST_CTRL2_OFFSET 0x3EU /**< Host Control2 Register */
-#define XSDPS_CAPS_OFFSET 0x40U /**< Capabilities Register */
-#define XSDPS_CAPS_EXT_OFFSET 0x44U /**< Capabilities Extended */
-#define XSDPS_MAX_CURR_CAPS_OFFSET 0x48U /**< Maximum Current
- Capabilities Register */
-#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4CU /**< Maximum Current
- Capabilities Ext Register */
-#define XSDPS_FE_ERR_INT_STS_OFFSET 0x52U /**< Force Event for
- Error Interrupt Status */
-#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50U /**< Auto CM12 Error Interrupt
- Status Register */
-#define XSDPS_ADMA_ERR_STS_OFFSET 0x54U /**< ADMA Error Status
- Register */
-#define XSDPS_ADMA_SAR_OFFSET 0x58U /**< ADMA System Address
- Register */
-#define XSDPS_ADMA_SAR_EXT_OFFSET 0x5CU /**< ADMA System Address
- Extended Register */
-#define XSDPS_PRE_VAL_1_OFFSET 0x60U /**< Preset Value Register */
-#define XSDPS_PRE_VAL_2_OFFSET 0x64U /**< Preset Value Register */
-#define XSDPS_PRE_VAL_3_OFFSET 0x68U /**< Preset Value Register */
-#define XSDPS_PRE_VAL_4_OFFSET 0x6CU /**< Preset Value Register */
-#define XSDPS_BOOT_TOUT_CTRL_OFFSET 0x70U /**< Boot timeout control
- register */
-
-#define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0U /**< Shared Bus Control
- Register */
-#define XSDPS_SLOT_INTR_STS_OFFSET 0xFCU /**< Slot Interrupt Status
- Register */
-#define XSDPS_HOST_CTRL_VER_OFFSET 0xFEU /**< Host Controller Version
- Register */
-
-/** @} */
-
-/** @name Control Register - Host control, Power control,
- * Block Gap control and Wakeup control
- *
- * This register contains bits for various configuration options of
- * the SD host controller. Read/Write apart from the reserved bits.
- * @{
- */
-
-#define XSDPS_HC_LED_MASK 0x00000001U /**< LED Control */
-#define XSDPS_HC_WIDTH_MASK 0x00000002U /**< Bus width */
-#define XSDPS_HC_BUS_WIDTH_4 0x00000002U
-#define XSDPS_HC_SPEED_MASK 0x00000004U /**< High Speed */
-#define XSDPS_HC_DMA_MASK 0x00000018U /**< DMA Mode Select */
-#define XSDPS_HC_DMA_SDMA_MASK 0x00000000U /**< SDMA Mode */
-#define XSDPS_HC_DMA_ADMA1_MASK 0x00000008U /**< ADMA1 Mode */
-#define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010U /**< ADMA2 Mode - 32 bit */
-#define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018U /**< ADMA2 Mode - 64 bit */
-#define XSDPS_HC_EXT_BUS_WIDTH 0x00000020U /**< Bus width - 8 bit */
-#define XSDPS_HC_CARD_DET_TL_MASK 0x00000040U /**< Card Detect Tst Lvl */
-#define XSDPS_HC_CARD_DET_SD_MASK 0x00000080U /**< Card Detect Sig Det */
-
-#define XSDPS_PC_BUS_PWR_MASK 0x00000001U /**< Bus Power Control */
-#define XSDPS_PC_BUS_VSEL_MASK 0x0000000EU /**< Bus Voltage Select */
-#define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000EU /**< Bus Voltage 3.3V */
-#define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000CU /**< Bus Voltage 3.0V */
-#define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000AU /**< Bus Voltage 1.8V */
-#define XSDPS_PC_EMMC_HW_RST_MASK 0x00000010U /**< HW reset for eMMC */
-
-#define XSDPS_BGC_STP_REQ_MASK 0x00000001U /**< Block Gap Stop Req */
-#define XSDPS_BGC_CNT_REQ_MASK 0x00000002U /**< Block Gap Cont Req */
-#define XSDPS_BGC_RWC_MASK 0x00000004U /**< Block Gap Rd Wait */
-#define XSDPS_BGC_INTR_MASK 0x00000008U /**< Block Gap Intr */
-#define XSDPS_BGC_SPI_MODE_MASK 0x00000010U /**< Block Gap SPI Mode */
-#define XSDPS_BGC_BOOT_EN_MASK 0x00000020U /**< Block Gap Boot Enb */
-#define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040U /**< Block Gap Alt BootEn */
-#define XSDPS_BGC_BOOT_ACK_MASK 0x00000080U /**< Block Gap Boot Ack */
-
-#define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001U /**< Wakeup Card Intr */
-#define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002U /**< Wakeup Card Insert */
-#define XSDPS_WC_WUP_ON_REM_MASK 0x00000004U /**< Wakeup Card Removal */
-
-/** @} */
-
-/** @name Control Register - Clock control, Timeout control & Software reset
- *
- * This register contains bits for configuration options of clock, timeout and
- * software reset.
- * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
- * @{
- */
-
-#define XSDPS_CC_INT_CLK_EN_MASK 0x00000001U /**< INT clk enable */
-#define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002U /**< INT clk stable */
-#define XSDPS_CC_SD_CLK_EN_MASK 0x00000004U /**< SD clk enable */
-#define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020U /**< SD clk gen selection */
-#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x00000003U /**< SD clk freq sel upper */
-#define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x000000FFU /**< SD clk freq sel */
-#define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000U /**< Divider 256 */
-#define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000U /**< Divider 128 */
-#define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000U /**< Divider 64 */
-#define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000U /**< Divider 32 */
-#define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800U /**< Divider 16 */
-#define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400U /**< Divider 8 */
-#define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200U /**< Divider 4 */
-#define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100U /**< Divider 2 */
-#define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000U /**< Base clock */
-#define XSDPS_CC_MAX_DIV_CNT 256U /**< Max divider count */
-#define XSDPS_CC_EXT_MAX_DIV_CNT 2046U /**< Max extended divider count */
-#define XSDPS_CC_EXT_DIV_SHIFT 6U /**< Ext divider shift */
-
-#define XSDPS_TC_CNTR_VAL_MASK 0x0000000FU /**< Data timeout counter */
-
-#define XSDPS_SWRST_ALL_MASK 0x00000001U /**< Software Reset All */
-#define XSDPS_SWRST_CMD_LINE_MASK 0x00000002U /**< Software reset for CMD line */
-#define XSDPS_SWRST_DAT_LINE_MASK 0x00000004U /**< Software reset for DAT line */
-
-#define XSDPS_CC_MAX_NUM_OF_DIV 9U /**< Max number of Clock dividers */
-#define XSDPS_CC_DIV_SHIFT 8U /**< Clock Divider shift */
-
-/** @} */
-
-/** @name SD Interrupt Registers
- *
- * Normal and Error Interrupt Status Register
- * This register shows the normal and error interrupt status.
- * Status enable register affects reads of this register.
- * If Signal enable register is set and the corresponding status bit is set,
- * interrupt is generated.
- * Write to clear except
- * Error_interrupt and Card_Interrupt bits - Read only
- *
- * Normal and Error Interrupt Status Enable Register
- * Setting this register bits enables Interrupt status.
- * Read/Write except Fixed_to_0 bit (Read only)
- *
- * Normal and Error Interrupt Signal Enable Register
- * This register is used to select which interrupt status is
- * indicated to the Host System as the interrupt.
- * Read/Write except Fixed_to_0 bit (Read only)
- *
- * All three registers have same bit definitions
- * @{
- */
-
-#define XSDPS_INTR_CC_MASK 0x00000001U /**< Command Complete */
-#define XSDPS_INTR_TC_MASK 0x00000002U /**< Transfer Complete */
-#define XSDPS_INTR_BGE_MASK 0x00000004U /**< Block Gap Event */
-#define XSDPS_INTR_DMA_MASK 0x00000008U /**< DMA Interrupt */
-#define XSDPS_INTR_BWR_MASK 0x00000010U /**< Buffer Write Ready */
-#define XSDPS_INTR_BRR_MASK 0x00000020U /**< Buffer Read Ready */
-#define XSDPS_INTR_CARD_INSRT_MASK 0x00000040U /**< Card Insert */
-#define XSDPS_INTR_CARD_REM_MASK 0x00000080U /**< Card Remove */
-#define XSDPS_INTR_CARD_MASK 0x00000100U /**< Card Interrupt */
-#define XSDPS_INTR_INT_A_MASK 0x00000200U /**< INT A Interrupt */
-#define XSDPS_INTR_INT_B_MASK 0x00000400U /**< INT B Interrupt */
-#define XSDPS_INTR_INT_C_MASK 0x00000800U /**< INT C Interrupt */
-#define XSDPS_INTR_RE_TUNING_MASK 0x00001000U /**< Re-Tuning Interrupt */
-#define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00002000U /**< Boot Ack Recv
- Interrupt */
-#define XSDPS_INTR_BOOT_TERM_MASK 0x00004000U /**< Boot Terminate
- Interrupt */
-#define XSDPS_INTR_ERR_MASK 0x00008000U /**< Error Interrupt */
-#define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFFU
-
-#define XSDPS_INTR_ERR_CT_MASK 0x00000001U /**< Command Timeout
- Error */
-#define XSDPS_INTR_ERR_CCRC_MASK 0x00000002U /**< Command CRC Error */
-#define XSDPS_INTR_ERR_CEB_MASK 0x00000004U /**< Command End Bit
- Error */
-#define XSDPS_INTR_ERR_CI_MASK 0x00000008U /**< Command Index Error */
-#define XSDPS_INTR_ERR_DT_MASK 0x00000010U /**< Data Timeout Error */
-#define XSDPS_INTR_ERR_DCRC_MASK 0x00000020U /**< Data CRC Error */
-#define XSDPS_INTR_ERR_DEB_MASK 0x00000040U /**< Data End Bit Error */
-#define XSDPS_INTR_ERR_CUR_LMT_MASK 0x00000080U /**< Current Limit Error */
-#define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100U /**< Auto CMD12 Error */
-#define XSDPS_INTR_ERR_ADMA_MASK 0x00000200U /**< ADMA Error */
-#define XSDPS_INTR_ERR_TR_MASK 0x00001000U /**< Tuning Error */
-#define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000U /**< Vendor Specific
- Error */
-#define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FFU /**< Mask for error bits */
-/** @} */
-
-/** @name Block Size and Block Count Register
- *
- * This register contains the block count for current transfer,
- * block size and SDMA buffer size.
- * Read/Write except for reserved bits.
- * @{
- */
-
-#define XSDPS_BLK_SIZE_MASK 0x00000FFFU /**< Transfer Block Size */
-#define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000U /**< Host SDMA Buffer Size */
-#define XSDPS_BLK_SIZE_1024 0x400U
-#define XSDPS_BLK_SIZE_2048 0x800U
-#define XSDPS_BLK_CNT_MASK 0x0000FFFFU /**< Block Count for
- Current Transfer */
-
-/** @} */
-
-/** @name Transfer Mode and Command Register
- *
- * The Transfer Mode register is used to control the data transfers and
- * Command register is used for command generation
- * Read/Write except for reserved bits.
- * @{
- */
-
-#define XSDPS_TM_DMA_EN_MASK 0x00000001U /**< DMA Enable */
-#define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002U /**< Block Count Enable */
-#define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004U /**< Auto CMD12 Enable */
-#define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010U /**< Data Transfer
- Direction Select */
-#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020U /**< Multi/Single
- Block Select */
-
-#define XSDPS_CMD_RESP_SEL_MASK 0x00000003U /**< Response Type
- Select */
-#define XSDPS_CMD_RESP_NONE_MASK 0x00000000U /**< No Response */
-#define XSDPS_CMD_RESP_L136_MASK 0x00000001U /**< Response length 138 */
-#define XSDPS_CMD_RESP_L48_MASK 0x00000002U /**< Response length 48 */
-#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003U /**< Response length 48 &
- check busy after
- response */
-#define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008U /**< Command CRC Check
- Enable */
-#define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010U /**< Command Index Check
- Enable */
-#define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020U /**< Data Present Select */
-#define XSDPS_CMD_TYPE_MASK 0x000000C0U /**< Command Type */
-#define XSDPS_CMD_TYPE_NORM_MASK 0x00000000U /**< CMD Type - Normal */
-#define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040U /**< CMD Type - Suspend */
-#define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080U /**< CMD Type - Resume */
-#define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0U /**< CMD Type - Abort */
-#define XSDPS_CMD_MASK 0x00003F00U /**< Command Index Mask -
- Set to CMD0-63,
- AMCD0-63 */
-
-/** @} */
-
-/** @name Auto CMD Error Status Register
- *
- * This register is read only register which contains
- * information about the error status of Auto CMD 12 and 23.
- * Read Only
- * @{
- */
-#define XSDPS_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
- executed */
-#define XSDPS_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
- Error */
-#define XSDPS_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
-#define XSDPS_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
- Error */
-#define XSDPS_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
-#define XSDPS_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
- Auto CMD12 Error */
-/** @} */
-
-/** @name Host Control2 Register
- *
- * This register contains extended configuration bits.
- * Read Write
- * @{
- */
-#define XSDPS_HC2_UHS_MODE_MASK 0x0007U /**< UHS Mode select bits */
-#define XSDPS_HC2_UHS_MODE_SDR12_MASK 0x0000U /**< SDR12 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_SDR25_MASK 0x0001U /**< SDR25 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_SDR50_MASK 0x0002U /**< SDR50 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_SDR104_MASK 0x0003U /**< SDR104 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_DDR50_MASK 0x0004U /**< DDR50 UHS Mode */
-#define XSDPS_HC2_1V8_EN_MASK 0x0008U /**< 1.8V Signal Enable */
-#define XSDPS_HC2_DRV_STR_SEL_MASK 0x0030U /**< Driver Strength
- Selection */
-#define XSDPS_HC2_DRV_STR_B_MASK 0x0000U /**< Driver Strength B */
-#define XSDPS_HC2_DRV_STR_A_MASK 0x0010U /**< Driver Strength A */
-#define XSDPS_HC2_DRV_STR_C_MASK 0x0020U /**< Driver Strength C */
-#define XSDPS_HC2_DRV_STR_D_MASK 0x0030U /**< Driver Strength D */
-#define XSDPS_HC2_EXEC_TNG_MASK 0x0040U /**< Execute Tuning */
-#define XSDPS_HC2_SAMP_CLK_SEL_MASK 0x0080U /**< Sampling Clock
- Selection */
-#define XSDPS_HC2_ASYNC_INTR_EN_MASK 0x4000U /**< Asynchronous Interrupt
- Enable */
-#define XSDPS_HC2_PRE_VAL_EN_MASK 0x8000U /**< Preset Value Enable */
-
-/** @} */
-
-/** @name Capabilities Register
- *
- * Capabilities register is a read only register which contains
- * information about the host controller.
- * Sufficient if read once after power on.
- * Read Only
- * @{
- */
-#define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003FU /**< Timeout clock freq
- select */
-#define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080U /**< Timeout clock unit -
- MHz/KHz */
-#define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000U /**< Max block length */
-#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000U /**< Max block 512 bytes */
-#define XSDPS_CAP_MAX_BL_LN_1024_MASK 0x00010000U /**< Max block 1024 bytes */
-#define XSDPS_CAP_MAX_BL_LN_2048_MASK 0x00020000U /**< Max block 2048 bytes */
-#define XSDPS_CAP_MAX_BL_LN_4096_MASK 0x00030000U /**< Max block 4096 bytes */
-
-#define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000U /**< Extended media bus */
-#define XSDPS_CAP_ADMA2_MASK 0x00080000U /**< ADMA2 support */
-#define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000U /**< High speed support */
-#define XSDPS_CAP_SDMA_MASK 0x00400000U /**< SDMA support */
-#define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000U /**< Suspend/Resume
- support */
-#define XSDPS_CAP_VOLT_3V3_MASK 0x01000000U /**< 3.3V support */
-#define XSDPS_CAP_VOLT_3V0_MASK 0x02000000U /**< 3.0V support */
-#define XSDPS_CAP_VOLT_1V8_MASK 0x04000000U /**< 1.8V support */
-
-#define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000U /**< 64 bit system bus
- support */
-/* Spec 2.0 */
-#define XSDPS_CAP_INTR_MODE_MASK 0x08000000U /**< Interrupt mode
- support */
-#define XSDPS_CAP_SPI_MODE_MASK 0x20000000U /**< SPI mode */
-#define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x40000000U /**< SPI block mode */
-
-
-/* Spec 3.0 */
-#define XSDPS_CAPS_ASYNC_INTR_MASK 0x20000000U /**< Async Interrupt
- support */
-#define XSDPS_CAPS_SLOT_TYPE_MASK 0xC0000000U /**< Slot Type */
-#define XSDPS_CAPS_REM_CARD 0x00000000U /**< Removable Slot */
-#define XSDPS_CAPS_EMB_SLOT 0x40000000U /**< Embedded Slot */
-#define XSDPS_CAPS_SHR_BUS 0x80000000U /**< Shared Bus Slot */
-
-#define XSDPS_ECAPS_SDR50_MASK 0x00000001U /**< SDR50 Mode support */
-#define XSDPS_ECAPS_SDR104_MASK 0x00000002U /**< SDR104 Mode support */
-#define XSDPS_ECAPS_DDR50_MASK 0x00000004U /**< DDR50 Mode support */
-#define XSDPS_ECAPS_DRV_TYPE_A_MASK 0x00000010U /**< DriverType A support */
-#define XSDPS_ECAPS_DRV_TYPE_C_MASK 0x00000020U /**< DriverType C support */
-#define XSDPS_ECAPS_DRV_TYPE_D_MASK 0x00000040U /**< DriverType D support */
-#define XSDPS_ECAPS_TMR_CNT_MASK 0x00000F00U /**< Timer Count for
- Re-tuning */
-#define XSDPS_ECAPS_USE_TNG_SDR50_MASK 0x00002000U /**< SDR50 Mode needs
- tuning */
-#define XSDPS_ECAPS_RE_TNG_MODES_MASK 0x0000C000U /**< Re-tuning modes
- support */
-#define XSDPS_ECAPS_RE_TNG_MODE1_MASK 0x00000000U /**< Re-tuning mode 1 */
-#define XSDPS_ECAPS_RE_TNG_MODE2_MASK 0x00004000U /**< Re-tuning mode 2 */
-#define XSDPS_ECAPS_RE_TNG_MODE3_MASK 0x00008000U /**< Re-tuning mode 3 */
-#define XSDPS_ECAPS_CLK_MULT_MASK 0x00FF0000U /**< Clock Multiplier value
- for Programmable clock
- mode */
-#define XSDPS_ECAPS_SPI_MODE_MASK 0x01000000U /**< SPI mode */
-#define XSDPS_ECAPS_SPI_BLK_MODE_MASK 0x02000000U /**< SPI block mode */
-
-/** @} */
-
-/** @name Present State Register
- *
- * Gives the current status of the host controller
- * Read Only
- * @{
- */
-
-#define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001U /**< Command inhibit - CMD */
-#define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002U /**< Command Inhibit - DAT */
-#define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004U /**< DAT line active */
-#define XSDPS_PSR_RE_TUNING_REQ_MASK 0x00000008U /**< Re-tuning request */
-#define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100U /**< Write transfer active */
-#define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200U /**< Read transfer active */
-#define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400U /**< Buffer write enable */
-#define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800U /**< Buffer read enable */
-#define XSDPS_PSR_CARD_INSRT_MASK 0x00010000U /**< Card inserted */
-#define XSDPS_PSR_CARD_STABLE_MASK 0x00020000U /**< Card state stable */
-#define XSDPS_PSR_CARD_DPL_MASK 0x00040000U /**< Card detect pin level */
-#define XSDPS_PSR_WPS_PL_MASK 0x00080000U /**< Write protect switch
- pin level */
-#define XSDPS_PSR_DAT30_SG_LVL_MASK 0x00F00000U /**< Data 3:0 signal lvl */
-#define XSDPS_PSR_CMD_SG_LVL_MASK 0x01000000U /**< Cmd Line signal lvl */
-#define XSDPS_PSR_DAT74_SG_LVL_MASK 0x1E000000U /**< Data 7:4 signal lvl */
-
-/** @} */
-
-/** @name Maximum Current Capabilities Register
- *
- * This register is read only register which contains
- * information about current capabilities at each voltage levels.
- * Read Only
- * @{
- */
-#define XSDPS_MAX_CUR_CAPS_1V8_MASK 0x00000F00U /**< Maximum Current
- Capability at 1.8V */
-#define XSDPS_MAX_CUR_CAPS_3V0_MASK 0x000000F0U /**< Maximum Current
- Capability at 3.0V */
-#define XSDPS_MAX_CUR_CAPS_3V3_MASK 0x0000000FU /**< Maximum Current
- Capability at 3.3V */
-/** @} */
-
-
-/** @name Force Event for Auto CMD Error Status Register
- *
- * This register is write only register which contains
- * control bits to generate events for Auto CMD error status.
- * Write Only
- * @{
- */
-#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
- executed */
-#define XSDPS_FE_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
- Error */
-#define XSDPS_FE_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
-#define XSDPS_FE_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
- Error */
-#define XSDPS_FE_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
-#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
- Auto CMD12 Error */
-/** @} */
-
-
-
-/** @name Force Event for Error Interrupt Status Register
- *
- * This register is write only register which contains
- * control bits to generate events of error interrupt status register.
- * Write Only
- * @{
- */
-#define XSDPS_FE_INTR_ERR_CT_MASK 0x0001U /**< Command Timeout
- Error */
-#define XSDPS_FE_INTR_ERR_CCRC_MASK 0x0002U /**< Command CRC Error */
-#define XSDPS_FE_INTR_ERR_CEB_MASK 0x0004U /**< Command End Bit
- Error */
-#define XSDPS_FE_INTR_ERR_CI_MASK 0x0008U /**< Command Index Error */
-#define XSDPS_FE_INTR_ERR_DT_MASK 0x0010U /**< Data Timeout Error */
-#define XSDPS_FE_INTR_ERR_DCRC_MASK 0x0020U /**< Data CRC Error */
-#define XSDPS_FE_INTR_ERR_DEB_MASK 0x0040U /**< Data End Bit Error */
-#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK 0x0080U /**< Current Limit Error */
-#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK 0x0100U /**< Auto CMD Error */
-#define XSDPS_FE_INTR_ERR_ADMA_MASK 0x0200U /**< ADMA Error */
-#define XSDPS_FE_INTR_ERR_TR_MASK 0x1000U /**< Target Response */
-#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK 0xE000U /**< Vendor Specific
- Error */
-
-/** @} */
-
-/** @name ADMA Error Status Register
- *
- * This register is read only register which contains
- * status information about ADMA errors.
- * Read Only
- * @{
- */
-#define XSDPS_ADMA_ERR_MM_LEN_MASK 0x04U /**< ADMA Length Mismatch
- Error */
-#define XSDPS_ADMA_ERR_STATE_MASK 0x03U /**< ADMA Error State */
-#define XSDPS_ADMA_ERR_STATE_STOP_MASK 0x00U /**< ADMA Error State
- STOP */
-#define XSDPS_ADMA_ERR_STATE_FDS_MASK 0x01U /**< ADMA Error State
- FDS */
-#define XSDPS_ADMA_ERR_STATE_TFR_MASK 0x03U /**< ADMA Error State
- TFR */
-/** @} */
-
-/** @name Preset Values Register
- *
- * This register is read only register which contains
- * preset values for each of speed modes.
- * Read Only
- * @{
- */
-#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK 0x03FFU /**< SDCLK Frequency
- Select Value */
-#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK 0x0400U /**< Clock Generator
- Mode Select */
-#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK 0xC000U /**< Driver Strength
- Select Value */
-
-/** @} */
-
-/** @name Slot Interrupt Status Register
- *
- * This register is read only register which contains
- * interrupt slot signal for each slot.
- * Read Only
- * @{
- */
-#define XSDPS_SLOT_INTR_STS_INT_MASK 0x0007U /**< Interrupt Signal
- mask */
-
-/** @} */
-
-/** @name Host Controller Version Register
- *
- * This register is read only register which contains
- * Host Controller and Vendor Specific version.
- * Read Only
- * @{
- */
-#define XSDPS_HC_VENDOR_VER 0xFF00U /**< Vendor
- Specification
- version mask */
-#define XSDPS_HC_SPEC_VER_MASK 0x00FFU /**< Host
- Specification
- version mask */
-#define XSDPS_HC_SPEC_V3 0x0002U /**< HC spec version 3 */
-#define XSDPS_HC_SPEC_V2 0x0001U /**< HC spec version 2 */
-#define XSDPS_HC_SPEC_V1 0x0000U /**< HC spec version 1 */
-/** @} */
-
-/** @name Block size mask for 512 bytes
- *
- * Block size mask for 512 bytes - This is the default block size.
- * @{
- */
-
-#define XSDPS_BLK_SIZE_512_MASK 0x200U /**< Blk Size 512 */
-
-/** @} */
-
-/** @name Commands
- *
- * Constant definitions for commands and response related to SD
- * @{
- */
-/**
- * Command/Response related to SD/eMMC
- */
-
-#define XSDPS_APP_CMD_PREFIX 0x8000U
-#define CMD0 0x0000U
-#define CMD1 0x0100U
-#define CMD2 0x0200U
-#define CMD3 0x0300U
-#define CMD4 0x0400U
-#define CMD5 0x0500U
-#define CMD6 0x0600U
-#define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600U)
-#define CMD7 0x0700U
-#define CMD8 0x0800U
-#define CMD9 0x0900U
-#define CMD10 0x0A00U
-#define CMD11 0x0B00U
-#define CMD12 0x0C00U
-#define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00U)
-#define CMD16 0x1000U
-#define CMD17 0x1100U
-#define CMD18 0x1200U
-#define CMD19 0x1300U
-#define CMD21 0x1500U
-#define CMD23 0x1700U
-#define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700U)
-#define CMD24 0x1800U
-#define CMD25 0x1900U
-#define CMD41 0x2900U
-#define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900U)
-#define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00U)
-#define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300U)
-#define CMD52 0x3400U
-#define CMD55 0x3700U
-#define CMD58 0x3A00U
-
-#define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK
-#define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
- (u32)XSDPS_CMD_INX_CHK_EN_MASK
-
-#define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
- (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
-
-#define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
-#define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK
-
-#define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
- (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
-
-/** @} */
-
-/**
- * @name Card Interface
- * @{
- */
-/**
- * Card Interface Conditions Definitions
- */
-#define XSDPS_CIC_CHK_PATTERN 0xAAU
-#define XSDPS_CIC_VOLT_MASK (0xFU<<8)
-#define XSDPS_CIC_VOLT_2V7_3V6 (1U<<8)
-#define XSDPS_CIC_VOLT_LOW (1U<<9)
-/** @} */
-
-/**
- * @name OCR
- * @{
- */
-/**
- * Operation Conditions Register Definitions
- */
-#define XSDPS_OCR_PWRUP_STS (1U<<31)
-#define XSDPS_OCR_CC_STS (1U<<30)
-#define XSDPS_OCR_S18 (1U<<24)
-#define XSDPS_OCR_3V5_3V6 (1U<<23)
-#define XSDPS_OCR_3V4_3V5 (1U<<22)
-#define XSDPS_OCR_3V3_3V4 (1U<<21)
-#define XSDPS_OCR_3V2_3V3 (1U<<20)
-#define XSDPS_OCR_3V1_3V2 (1U<<19)
-#define XSDPS_OCR_3V0_3V1 (1U<<18)
-#define XSDPS_OCR_2V9_3V0 (1U<<17)
-#define XSDPS_OCR_2V8_2V9 (1U<<16)
-#define XSDPS_OCR_2V7_2V8 (1U<<15)
-#define XSDPS_OCR_1V7_1V95 (1U<<7)
-#define XSDPS_OCR_HIGH_VOL 0x00FF8000U
-#define XSDPS_OCR_LOW_VOL 0x00000080U
-/** @} */
-
-/**
- * @name Card Configuration
- * @{
- */
-/**
- * SD Card Configuration Register Definitions
- */
-#define XSDPS_SCR_REG_LEN 8U
-#define XSDPS_SCR_STRUCT_MASK (0xFU<<28)
-#define XSDPS_SCR_SPEC_MASK (0xFU<<24)
-#define XSDPS_SCR_SPEC_1V0 0U
-#define XSDPS_SCR_SPEC_1V1 (1U<<24)
-#define XSDPS_SCR_SPEC_2V0_3V0 (2U<<24)
-#define XSDPS_SCR_MEM_VAL_AF_ERASE (1U<<23)
-#define XSDPS_SCR_SEC_SUPP_MASK (7U<<20)
-#define XSDPS_SCR_SEC_SUPP_NONE 0U
-#define XSDPS_SCR_SEC_SUPP_1V1 (2U<<20)
-#define XSDPS_SCR_SEC_SUPP_2V0 (3U<<20)
-#define XSDPS_SCR_SEC_SUPP_3V0 (4U<<20)
-#define XSDPS_SCR_BUS_WIDTH_MASK (0xFU<<16)
-#define XSDPS_SCR_BUS_WIDTH_1 (1U<<16)
-#define XSDPS_SCR_BUS_WIDTH_4 (4U<<16)
-#define XSDPS_SCR_SPEC3_MASK (1U<<12)
-#define XSDPS_SCR_SPEC3_2V0 0U
-#define XSDPS_SCR_SPEC3_3V0 (1U<<12)
-#define XSDPS_SCR_CMD_SUPP_MASK 0x3U
-#define XSDPS_SCR_CMD23_SUPP (1U<<1)
-#define XSDPS_SCR_CMD20_SUPP (1U<<0)
-/** @} */
-
-/**
- * @name Card Status
- * @{
- */
-/**
- * Card Status Register Definitions
- */
-#define XSDPS_CD_STS_OUT_OF_RANGE (1U<<31)
-#define XSDPS_CD_STS_ADDR_ERR (1U<<30)
-#define XSDPS_CD_STS_BLK_LEN_ERR (1U<<29)
-#define XSDPS_CD_STS_ER_SEQ_ERR (1U<<28)
-#define XSDPS_CD_STS_ER_PRM_ERR (1U<<27)
-#define XSDPS_CD_STS_WP_VIO (1U<<26)
-#define XSDPS_CD_STS_IS_LOCKED (1U<<25)
-#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL (1U<<24)
-#define XSDPS_CD_STS_CMD_CRC_ERR (1U<<23)
-#define XSDPS_CD_STS_ILGL_CMD (1U<<22)
-#define XSDPS_CD_STS_CARD_ECC_FAIL (1U<<21)
-#define XSDPS_CD_STS_CC_ERR (1U<<20)
-#define XSDPS_CD_STS_ERR (1U<<19)
-#define XSDPS_CD_STS_CSD_OVRWR (1U<<16)
-#define XSDPS_CD_STS_WP_ER_SKIP (1U<<15)
-#define XSDPS_CD_STS_CARD_ECC_DIS (1U<<14)
-#define XSDPS_CD_STS_ER_RST (1U<<13)
-#define XSDPS_CD_STS_CUR_STATE (0xFU<<9)
-#define XSDPS_CD_STS_RDY_FOR_DATA (1U<<8)
-#define XSDPS_CD_STS_APP_CMD (1U<<5)
-#define XSDPS_CD_STS_AKE_SEQ_ERR (1U<<2)
-/** @} */
-
-/**
- * @name Switch function
- * @{
- */
-/**
- * Switch Function Definitions CMD6
- */
-#define XSDPS_SWITCH_SD_RESP_LEN 64U
-
-#define XSDPS_SWITCH_FUNC_SWITCH (1U<<31)
-#define XSDPS_SWITCH_FUNC_CHECK 0U
-/** @} */
-
-/**
- * @name Mode Function
- * @{
- */
-/**
- * Mode function groups definitions.
- */
-#define XSDPS_MODE_FUNC_GRP1 1U
-#define XSDPS_MODE_FUNC_GRP2 2U
-#define XSDPS_MODE_FUNC_GRP3 3U
-#define XSDPS_MODE_FUNC_GRP4 4U
-#define XSDPS_MODE_FUNC_GRP5 5U
-#define XSDPS_MODE_FUNC_GRP6 6U
-
-#define XSDPS_FUNC_GRP_DEF_VAL 0xFU
-#define XSDPS_FUNC_ALL_GRP_DEF_VAL 0xFFFFFFU
-/** @} */
-
-/**
- * @name Operating modes
- * @{
- */
-/**
- * SD operating modes in UHS.
- */
-#define XSDPS_ACC_MODE_DEF_SDR12 0U
-#define XSDPS_ACC_MODE_HS_SDR25 1U
-#define XSDPS_ACC_MODE_SDR50 2U
-#define XSDPS_ACC_MODE_SDR104 3U
-#define XSDPS_ACC_MODE_DDR50 4U
-/** @} */
-
-/**
- * @name General definitions
- * @{
- */
-/**
- * Definitions related to Driver strength, Current limit and
- * CSD specific data.
- */
-#define XSDPS_CMD_SYS_ARG_SHIFT 4U
-#define XSDPS_CMD_SYS_DEF 0U
-#define XSDPS_CMD_SYS_eC 1U
-#define XSDPS_CMD_SYS_OTP 3U
-#define XSDPS_CMD_SYS_ASSD 4U
-#define XSDPS_CMD_SYS_VEND 5U
-
-#define XSDPS_DRV_TYPE_ARG_SHIFT 8U
-#define XSDPS_DRV_TYPE_B 0U
-#define XSDPS_DRV_TYPE_A 1U
-#define XSDPS_DRV_TYPE_C 2U
-#define XSDPS_DRV_TYPE_D 3U
-
-#define XSDPS_CUR_LIM_ARG_SHIFT 12U
-#define XSDPS_CUR_LIM_200 0U
-#define XSDPS_CUR_LIM_400 1U
-#define XSDPS_CUR_LIM_600 2U
-#define XSDPS_CUR_LIM_800 3U
-
-#define CSD_SPEC_VER_MASK 0x3C0000U
-#define READ_BLK_LEN_MASK 0x00000F00U
-#define C_SIZE_MULT_MASK 0x00000380U
-#define C_SIZE_LOWER_MASK 0xFFC00000U
-#define C_SIZE_UPPER_MASK 0x00000003U
-#define CSD_STRUCT_MASK 0x00C00000U
-#define CSD_V2_C_SIZE_MASK 0x3FFFFF00U
-/** @} */
-
-/**
- * @name Extended Card Specific Data
- * @{
- */
-/**
- * EXT_CSD field definitions
- */
-#define XSDPS_EXT_CSD_SIZE 512U
-
-#define EXT_CSD_WR_REL_PARAM_EN (1U<<2)
-
-#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40U)
-#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10U)
-#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04U)
-#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01U)
-
-#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7U)
-#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1U)
-#define EXT_CSD_PART_CONFIG_ACC_BOOT1 (0x2U)
-#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U)
-#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U)
-#define EXT_CSD_PART_CONFIG_BYTE (179U)
-#define XSDPS_MMC_PART_CFG_0_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
- | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
- | ((u32)(0U) << 8U))
-
-#define XSDPS_MMC_PART_CFG_1_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
- | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
- | ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT0 << 8U))
-
-#define XSDPS_MMC_PART_CFG_2_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
- | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
- | ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT1 << 8U))
-
-#define EXT_CSD_PART_SUPPORT_PART_EN (0x1U)
-
-#define EXT_CSD_CMD_SET_NORMAL (1U<<0)
-#define EXT_CSD_CMD_SET_SECURE (1U<<1)
-#define EXT_CSD_CMD_SET_CPSECURE (1U<<2)
-
-#define EXT_CSD_CARD_TYPE_26 (1U<<0) /* Card can run at 26MHz */
-#define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */
-#define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */
-#define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */
- /* DDR mode @1.8V or 3V I/O */
-#define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */
- /* DDR mode @1.2V I/O */
-#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
- | EXT_CSD_CARD_TYPE_DDR_1_2V)
-#define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */
-#define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */
- /* SDR mode @1.2V I/O */
-#define EXT_CSD_BUS_WIDTH_BYTE 183U
-#define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */
-#define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */
-#define EXT_CSD_BUS_WIDTH_8_BIT 2U /* Card is in 8 bit mode */
-#define EXT_CSD_BUS_WIDTH_DDR_4_BIT 5U /* Card is in 4 bit DDR mode */
-#define EXT_CSD_BUS_WIDTH_DDR_8_BIT 6U /* Card is in 8 bit DDR mode */
-
-#define EXT_CSD_HS_TIMING_BYTE 185U
-#define EXT_CSD_HS_TIMING_DEF 0U
-#define EXT_CSD_HS_TIMING_HIGH 1U /* Card is in high speed mode */
-#define EXT_CSD_HS_TIMING_HS200 2U /* Card is in HS200 mode */
-
-#define EXT_CSD_RST_N_FUN_BYTE 162U
-#define EXT_CSD_RST_N_FUN_TEMP_DIS 0U /* RST_n signal is temporarily disabled */
-#define EXT_CSD_RST_N_FUN_PERM_EN 1U /* RST_n signal is permanently enabled */
-#define EXT_CSD_RST_N_FUN_PERM_DIS 2U /* RST_n signal is permanently disabled */
-
-#define XSDPS_EXT_CSD_CMD_SET 0U
-#define XSDPS_EXT_CSD_SET_BITS 1U
-#define XSDPS_EXT_CSD_CLR_BITS 2U
-#define XSDPS_EXT_CSD_WRITE_BYTE 3U
-/** @} */
-
-/**
- * @name SD/eMMC Bus Speed and Bus Width Arguments
- * @{
- */
-/**
- * SD/MMC Arguments for Bus Speed and Bus Width.
- */
-#define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
- | ((u32)EXT_CSD_HS_TIMING_DEF << 8))
-
-#define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
- | ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
-
-#define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
- | ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
-
-#define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8))
-
-#define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
-
-#define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
-
-#define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
-
-#define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
-
-#define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
- | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
-
-#define XSDPS_MMC_DELAY_FOR_SWITCH 1000U
-
-/** @} */
-
-/**
- * @name General Delay definitions
- * @{
- */
-/**
- * @400KHz, in usec
- */
-#define XSDPS_74CLK_DELAY 2960U
-#define XSDPS_100CLK_DELAY 4000U
-#define XSDPS_INIT_DELAY 10000U
-/** @} */
-
-#define XSDPS_DEF_VOLT_LVL XSDPS_PC_BUS_VSEL_3V0_MASK /**< Default voltage level */
-#define XSDPS_CARD_DEF_ADDR 0x1234U /**< Card Default address */
-
-#define XSDPS_CARD_SD 1U /**< SD card */
-#define XSDPS_CARD_MMC 2U /**< MMC card */
-#define XSDPS_CARD_SDIO 3U /**< SDIO card */
-#define XSDPS_CARD_SDCOMBO 4U /**< SDCOMBO card */
-#define XSDPS_CHIP_EMMC 5U /**< EMMC chip */
-
-
-/**
- *@name ADMA2 Descriptor related definitions
- * @{
- */
-/**
- * ADMA2 Descriptor related definitions
- */
-#define XSDPS_DESC_MAX_LENGTH 65536U
-
-#define XSDPS_DESC_VALID (0x1U << 0)
-#define XSDPS_DESC_END (0x1U << 1)
-#define XSDPS_DESC_INT (0x1U << 2)
-#define XSDPS_DESC_TRAN (0x2U << 4)
-
-/** @} */
-
-/* For changing clock frequencies */
-#define XSDPS_CLK_400_KHZ 400000U /**< 400 KHZ */
-#define XSDPS_CLK_50_MHZ 50000000U /**< 50 MHZ */
-#define XSDPS_CLK_52_MHZ 52000000U /**< 52 MHZ */
-#define XSDPS_SD_VER_1_0 0x1U /**< SD ver 1 */
-#define XSDPS_SD_VER_2_0 0x2U /**< SD ver 2 */
-#define XSDPS_SCR_BLKCNT 1U /**< SCR Block Count */
-#define XSDPS_SCR_BLKSIZE 8U /**< SCR Block Size */
-#define XSDPS_1_BIT_WIDTH 0x1U /**< Bus Width 1 */
-#define XSDPS_4_BIT_WIDTH 0x2U /**< Bus Width 4 */
-#define XSDPS_8_BIT_WIDTH 0x3U /**< Bus Width 8 */
-#define XSDPS_UHS_SPEED_MODE_SDR12 0x0U /**< SDR12 mode */
-#define XSDPS_UHS_SPEED_MODE_SDR25 0x1U /**< SDR25 mode */
-#define XSDPS_UHS_SPEED_MODE_SDR50 0x2U /**< SDR50 mode */
-#define XSDPS_UHS_SPEED_MODE_SDR104 0x3U /**< SDR104 mode */
-#define XSDPS_UHS_SPEED_MODE_DDR50 0x4U /**< DDR50 mode */
-#define XSDPS_HIGH_SPEED_MODE 0x5U /**< High Speed mode */
-#define XSDPS_DEFAULT_SPEED_MODE 0x6U /**< Default speed mode */
-#define XSDPS_HS200_MODE 0x7U /**< eMMC HS200 mode */
-#define XSDPS_DDR52_MODE 0x4U /**< eMMC DDR52 mode */
-#define XSDPS_SWITCH_CMD_BLKCNT 1U /**< Blk cnt for SWITCH cmd */
-#define XSDPS_SWITCH_CMD_BLKSIZE 64U /**< Blk sz for SWITCH cmd */
-#define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U /**< SWITCH cmd to Get HS */
-#define XSDPS_SWITCH_CMD_HS_SET 0x80FFFFF1U /**< SWITCH cmd to Set HS */
-#define XSDPS_SWITCH_CMD_SDR12_SET 0x80FFFFF0U /**< SWITCH cmd to Set SDR12 */
-#define XSDPS_SWITCH_CMD_SDR25_SET 0x80FFFFF1U /**< SWITCH cmd to Set SDR25 */
-#define XSDPS_SWITCH_CMD_SDR50_SET 0x80FFFFF2U /**< SWITCH cmd to Set SDR50 */
-#define XSDPS_SWITCH_CMD_SDR104_SET 0x80FFFFF3U /**< SWITCH cmd to Set SDR104 */
-#define XSDPS_SWITCH_CMD_DDR50_SET 0x80FFFFF4U /**< SWITCH cmd to Set DDR50 */
-#define XSDPS_EXT_CSD_CMD_BLKCNT 1U /**< Blk Cnt for EXT CSD */
-#define XSDPS_EXT_CSD_CMD_BLKSIZE 512U /**< Blk Sz for EXT CSD */
-#define XSDPS_TUNING_CMD_BLKCNT 1U /**< Blk Cnt for Tuning cmd */
-#define XSDPS_TUNING_CMD_BLKSIZE 64U /**< Blk Sz for Tuning cmd */
-#define XSDPS_SD_STATUS_BLKCNT 1U /**< Blk Cnt for SD status */
-#define XSDPS_SD_STATUS_BLKSIZE 64U /**< Blk Sz for SD status */
-
-#define XSDPS_HIGH_SPEED_MAX_CLK 50000000U /**< Max clk for HS mode */
-#define XSDPS_UHS_SDR104_MAX_CLK 208000000U /**< Max clk for SDR104 mode */
-#define XSDPS_UHS_SDR50_MAX_CLK 100000000U /**< Max clk for SDR50 mode */
-#define XSDPS_UHS_DDR50_MAX_CLK 50000000U /**< Max clk for DDR50 mode */
-#define XSDPS_UHS_SDR25_MAX_CLK 50000000U /**< Max clk for SDR25 mode */
-#define XSDPS_UHS_SDR12_MAX_CLK 25000000U /**< Max clk for SDR12 mode */
-
-#define SD_DRIVER_TYPE_B 0x01U /**< Driver Type B */
-#define SD_DRIVER_TYPE_A 0x02U /**< Driver Type A */
-#define SD_DRIVER_TYPE_C 0x04U /**< Driver Type C */
-#define SD_DRIVER_TYPE_D 0x08U /**< Driver Type D */
-#define SD_SET_CURRENT_LIMIT_200 0U /**< Current limit 200mA */
-#define SD_SET_CURRENT_LIMIT_400 1U /**< Current limit 400mA */
-#define SD_SET_CURRENT_LIMIT_600 2U /**< Current limit 600mA */
-#define SD_SET_CURRENT_LIMIT_800 3U /**< Current limit 800mA */
-
-#define SD_MAX_CURRENT_200 (1U << SD_SET_CURRENT_LIMIT_200) /**< Current limit 200mA Arg */
-#define SD_MAX_CURRENT_400 (1U << SD_SET_CURRENT_LIMIT_400) /**< Current limit 400mA Arg */
-#define SD_MAX_CURRENT_600 (1U << SD_SET_CURRENT_LIMIT_600) /**< Current limit 600mA Arg */
-#define SD_MAX_CURRENT_800 (1U << SD_SET_CURRENT_LIMIT_800) /**< Current limit 800mA Arg */
-
-#define XSDPS_SD_SDR12_MAX_CLK 25000000U /**< Max clk for SDR12 mode */
-#define XSDPS_SD_SDR25_MAX_CLK 50000000U /**< Max clk for SDR25 mode */
-#define XSDPS_SD_SDR50_MAX_CLK 100000000U /**< Max clk for SDR50 mode */
-#define XSDPS_SD_DDR50_MAX_CLK 50000000U /**< Max clk for DDR50 mode */
-#define XSDPS_SD_SDR104_MAX_CLK 208000000U /**< Max clk for SDR104 mode */
-/**
- * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller
- * than the clock value coming from the core. This value is kept to safely
- * switch to SDR104 mode if the SD card supports it.
- */
-#define XSDPS_SD_INPUT_MAX_CLK 175000000U
-
-#define XSDPS_MMC_HS200_MAX_CLK 200000000U /**< Max clk for MMC HS200 mode */
-#define XSDPS_MMC_HSD_MAX_CLK 52000000U /**< Max clk for MMC HSD mode */
-#define XSDPS_MMC_DDR_MAX_CLK 52000000U /**< Max clk for MMC DDR52 mode */
-
-/**
- * @name Card states
- * @{
- */
-/**
- * Definition for Card state.
- */
-#define XSDPS_CARD_STATE_IDLE 0U
-#define XSDPS_CARD_STATE_RDY 1U
-#define XSDPS_CARD_STATE_IDEN 2U
-#define XSDPS_CARD_STATE_STBY 3U
-#define XSDPS_CARD_STATE_TRAN 4U
-#define XSDPS_CARD_STATE_DATA 5U
-#define XSDPS_CARD_STATE_RCV 6U
-#define XSDPS_CARD_STATE_PROG 7U
-#define XSDPS_CARD_STATE_DIS 8U
-#define XSDPS_CARD_STATE_BTST 9U
-#define XSDPS_CARD_STATE_SLP 10U
-/** @} */
-
-#define XSDPS_SLOT_REM 0U /**< Removable slot */
-#define XSDPS_SLOT_EMB 1U /**< Embedded slot */
-
-#define XSDPS_WIDTH_8 8U /**< Bus width 8 */
-#define XSDPS_WIDTH_4 4U /**< Bus width 4 */
-
-/**
- * @name Tap delays
- * @{
- */
-/**
- * SD/eMMC ITAP and OTAP delays for different operating modes
- * for both Versal and ZynqMP platforms.
- */
-#ifdef versal
-#define SD_ITAPDLY_SEL_MASK 0x000000FFU
-#define SD_OTAPDLY_SEL_MASK 0x0000003FU
-#define SD_ITAPDLY 0x0000F0F8U
-#define SD_OTAPDLY 0x0000F0FCU
-#define SD0_DLL_CTRL 0x00000448U
-#define SD1_DLL_CTRL 0x000004C8U
-#define SD_DLL_RST 0x00000004U
-#define SD_ITAPCHGWIN 0x00000200U
-#define SD_ITAPDLYENA 0x00000100U
-#define SD_OTAPDLYENA 0x00000040U
-#define SD_OTAPDLYSEL_HS200_B0 0x00000002U
-#define SD_OTAPDLYSEL_HS200_B2 0x00000002U
-#define SD_ITAPDLYSEL_SD50 0x0000000EU
-#define SD_OTAPDLYSEL_SD50 0x00000003U
-#define SD_ITAPDLYSEL_SD_DDR50 0x00000036U
-#define SD_ITAPDLYSEL_EMMC_DDR50 0x0000001EU
-#define SD_OTAPDLYSEL_SD_DDR50 0x00000003U
-#define SD_OTAPDLYSEL_EMMC_DDR50 0x00000005U
-#define SD_ITAPDLYSEL_HSD 0x0000002CU
-#define SD_OTAPDLYSEL_SD_HSD 0x00000004U
-#define SD_OTAPDLYSEL_EMMC_HSD 0x00000005U
-#else
-#define SD0_ITAPDLY_SEL_MASK 0x000000FFU
-#define SD0_OTAPDLY_SEL_MASK 0x0000003FU
-#define SD1_ITAPDLY_SEL_MASK 0x00FF0000U
-#define SD1_OTAPDLY_SEL_MASK 0x003F0000U
-#define SD_DLL_CTRL 0x00000358U
-#define SD_ITAPDLY 0x00000314U
-#define SD_OTAPDLY 0x00000318U
-#define SD0_DLL_RST 0x00000004U
-#define SD1_DLL_RST 0x00040000U
-#define SD0_ITAPCHGWIN 0x00000200U
-#define SD0_ITAPDLYENA 0x00000100U
-#define SD0_OTAPDLYENA 0x00000040U
-#define SD1_ITAPCHGWIN 0x02000000U
-#define SD1_ITAPDLYENA 0x01000000U
-#define SD1_OTAPDLYENA 0x00400000U
-#define SD_OTAPDLYSEL_HS200_B0 0x00000003U
-#define SD_OTAPDLYSEL_HS200_B2 0x00000002U
-#define SD_ITAPDLYSEL_SD50 0x00000014U
-#define SD_OTAPDLYSEL_SD50 0x00000003U
-#define SD_ITAPDLYSEL_SD_DDR50 0x0000003DU
-#define SD_ITAPDLYSEL_EMMC_DDR50 0x00000012U
-#define SD_OTAPDLYSEL_SD_DDR50 0x00000004U
-#define SD_OTAPDLYSEL_EMMC_DDR50 0x00000006U
-#define SD_ITAPDLYSEL_HSD 0x00000015U
-#define SD_OTAPDLYSEL_SD_HSD 0x00000005U
-#define SD_OTAPDLYSEL_EMMC_HSD 0x00000006U
-#endif
-/** @} */
-
-#ifdef __MICROBLAZE__
-#define XPS_SYS_CTRL_BASEADDR 0xFF180000U /**< System controller Baseaddress */
-#endif
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#define XSdPs_In64 Xil_In64 /**< Low level 64-bit data read */
-#define XSdPs_Out64 Xil_Out64 /**< Low level 64-bit data write */
-
-#define XSdPs_In32 Xil_In32 /**< Low level 32-bit data read */
-#define XSdPs_Out32 Xil_Out32 /**< Low level 32-bit data write */
-
-#define XSdPs_In16 Xil_In16 /**< Low level 16-bit data read */
-#define XSdPs_Out16 Xil_Out16 /**< Low level 16-bit data write */
-
-#define XSdPs_In8 Xil_In8 /**< Low level 8-bit data read */
-#define XSdPs_Out8 Xil_Out8 /**< Low level 8-bit data write */
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param InstancePtr is the pointer to the sdps instance.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
-*
-******************************************************************************/
-#define XSdPs_ReadReg64(InstancePtr, RegOffset) \
- XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset)
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param InstancePtr is the pointer to the sdps instance.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
-* u64 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
- XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
- (RegisterValue))
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-#define XSdPs_ReadReg(BaseAddress, RegOffset) \
- XSdPs_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u32 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg >>= ((RegOffset & 0x3)*8);
- return (u16)Reg;
-#else
- return XSdPs_In16((BaseAddress) + (RegOffset));
-#endif
-}
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u16 RegisterValue)
-*
-******************************************************************************/
-
-static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg &= ~(0xFFFFU<<((RegOffset & 0x3)*8));
- Reg |= RegisterValue <<((RegOffset & 0x3)*8);
- XSdPs_Out32(BaseAddress, Reg);
-#else
- XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue));
-#endif
-}
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg >>= ((RegOffset & 0x3)*8);
- return (u8)Reg;
-#else
- return XSdPs_In8((BaseAddress) + (RegOffset));
-#endif
-}
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u8 RegisterValue)
-*
-******************************************************************************/
-static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg &= ~(0xFFU<<((RegOffset & 0x3)*8));
- Reg |= RegisterValue <<((RegOffset & 0x3)*8);
- XSdPs_Out32(BaseAddress, Reg);
-#else
- XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue));
-#endif
-}
-/***************************************************************************/
-/**
-* Macro to get present status register
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u8 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_GetPresentStatusReg(BaseAddress) \
- XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SD_HW_H_ */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2a/711622555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2a/711622555243001d18b399c1eb9b3628
deleted file mode 100644
index 2c4d446..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2a/711622555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,92 +0,0 @@
-###############################################################################
-# Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
-# SPDX-License-Identifier: MIT
-###############################################################################
-DRIVER_LIB_VERSION = v1.0
-
-include config.make
-
-AS=$(ASSEMBLER)
-COMPILER=$(COMPILER)
-ARCHIVER=$(ARCHIVER)
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-INCLUDEFILES=*.h
-
-SRCFILES:=$(wildcard *.c)
-ASSEMBLY_SRCFILES:=$(wildcard *.S)
-
-COBJS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(wildcard *.c))))
-AOBJS1 = $(RELEASEDIR)/asm_vectors.o
-AOBJS2 = $(RELEASEDIR)/translation_table.o
-AOBJS3 = $(RELEASEDIR)/boot.o
-OBJS = $(COBJS) $(AOBJS1) $(AOBJS2) $(AOBJS3)
-
-ASOURCES1 = asm_vectors.S
-ASOURCES2 = translation_table.S
-ASOURCES3 = boot.S
-
-OBJECTS = $(OBJS)
-
-libs: standalone_libs
-standalone_libs: ${OBJECTS}
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-ASSEMBLY_DEPFILES := $(ASSEMBLY_SRCFILES:%.S=$(RELEASEDIR)%.d)
-
-include $(wildcard $(ASSEMBLY_DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(AOBJS1): $(ASOURCES1)
-ifeq ($(findstring asm_vectors.S,$(wildcard *.S)),asm_vectors.S)
- ${COMPILER} $(INCLUDES) --target=aarch64-arm-none-eabi -E -o asm_vectors_post.s asm_vectors.S
-endif
- ${AS} --cpu=8-A.64 --fpu=fp-armv8 -o $*.o asm_vectors_post.s --depend=$*.d
-
-$(AOBJS2): $(ASOURCES2)
-ifeq ($(findstring translation_table.S,$(wildcard *.S)),translation_table.S)
- ${COMPILER} $(INCLUDES) --target=aarch64-arm-none-eabi -E -o translation_table_post.s translation_table.S
-endif
- ${AS} --cpu=8-A.64 --fpu=fp-armv8 -o $*.o translation_table_post.s --depend=$*.d
-
-$(AOBJS3): $(ASOURCES3)
-ifeq ($(findstring boot.S,$(wildcard *.S)),boot.S)
- ${COMPILER} $(INCLUDES) --target=aarch64-arm-none-eabi -E -o boot_post.s boot.S
-endif
- ${AS} --cpu=8-A.64 --fpu=fp-armv8 -o $*.o boot_post.s --depend=$*.d
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} -c $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $<
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h)) $(addprefix $(INCLUDEDIR), $(subst includes_ps/,,$(wildcard includes_ps/*.h)))
-
-
-
-$(INCLUDEDIR)%.h: includes_ps/%.h
- $(CP) $< $@
-
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf $(DEPFILES)
- rm -rf $(ASSEMBLY_DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2a/a08e66545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2a/a08e66545243001d18b399c1eb9b3628
deleted file mode 100644
index 0cdfc1e..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2a/a08e66545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,156 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xscuwdt_hw.h
-* @addtogroup scuwdt_v2_4
-* @{
-*
-* This file contains the hardware interface to the Xilinx SCU private Watch Dog
-* Timer (XSCUWDT).
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
-* of 0x20 as the base address obtained from the tools
-* starts at 0x20.
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-#ifndef XSCUWDT_HW_H /**< prevent circular inclusions */
-#define XSCUWDT_HW_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- * Offsets of registers from the start of the device. The WDT registers start at
- * an offset 0x20
- * @{
- */
-
-#define XSCUWDT_LOAD_OFFSET 0x00U /**< Watchdog Load Register */
-#define XSCUWDT_COUNTER_OFFSET 0x04U /**< Watchdog Counter Register */
-#define XSCUWDT_CONTROL_OFFSET 0x08U /**< Watchdog Control Register */
-#define XSCUWDT_ISR_OFFSET 0x0CU /**< Watchdog Interrupt Status Register */
-#define XSCUWDT_RST_STS_OFFSET 0x10U /**< Watchdog Reset Status Register */
-#define XSCUWDT_DISABLE_OFFSET 0x14U /**< Watchdog Disable Register */
-/* @} */
-
-/** @name Watchdog Control register
- * This register bits control the prescaler, WD/Timer mode, Intr enable,
- * auto-reload, watchdog enable.
- * @{
- */
-
-#define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
-#define XSCUWDT_CONTROL_PRESCALER_SHIFT 8U
-#define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008U /**< Watchdog/Timer mode */
-#define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004U /**< Intr enable (in
- timer mode) */
-#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload (in
- timer mode) */
-#define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001U /**< Watchdog enable */
-/* @} */
-
-/** @name Interrupt Status register
- * This register indicates the Counter register has reached zero in Counter
- * mode.
- * @{
- */
-
-#define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
-/*@}*/
-
-/** @name Reset Status register
- * This register indicates the Counter register has reached zero in Watchdog
- * mode and a reset request is sent.
- * @{
- */
-
-#define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001U /**< Time out occurred */
-/*@}*/
-
-/** @name Disable register
- * This register is used to switch from watchdog mode to timer mode.
- * The software must write 0x12345678 and 0x87654321 successively to the
- * Watchdog Disable Register so that the watchdog mode bit in the Watchdog
- * Control Register is set to zero.
- * @{
- */
-#define XSCUWDT_DISABLE_VALUE1 0x12345678U /**< Watchdog mode disable
- value 1 */
-#define XSCUWDT_DISABLE_VALUE2 0x87654321U /**< Watchdog mode disable
- value 2 */
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note C-style signature:
-* u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuWdt_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + ((u32)RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2a/b3341f595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2a/b3341f595243001d18b399c1eb9b3628
deleted file mode 100644
index fc90230..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2a/b3341f595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,470 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpm_counter.c
-*
-* This file contains APIs for configuring and controlling the Cortex-R5
-* Performance Monitor Events. For more information about the event counters,
-* see xpm_counter.h.
-* The file contains APIs to setup an event, return the event counter value,
-* disable event(s), enable events, reset event counters.
-* It also provides a helper function: Xpm_SleepPerfCounter that is used to
-* implement sleep routines in non-OS environment.
-* It also contains two APIs which are being deprecated. Users are advised
-* not to use them.
-* On usage of these APIs, please refer to xpm_conter_example.c file which can
-* be found at standalone example folder.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.00 pkp 02/10/14 Initial version
-* 6.2 mus 01/27/17 Updated to support IAR compiler
-* 7.1 aru 04/15/19 Updated the events correctly
-* 7.2 mus 01/29/20 Added helper function Xpm_SleepPerfCounter for sleep
-* routines. It would be consumed by sleep routines for
-* delay generation through CortexR5 PMU cycle counter,if
-* TTC2 as well as TTC3 is not present in HW design. User
-* can add compiler flag "DONT_USE_PMU_FOR_SLEEP_ROUTINES"
-* in BSP compiler flags to avoid using PMU cycle counter
-* for sleep routines.
-* 7.2 asa 03/18/20 Add implementation for new APIs that simplifies the
-* existing event handling mechanism.
-* Older APIs are being deprecated.
-* 7.6 mus 09/16/21 PmcrEventCfg32 is declared with deprecate attribute and
-* being used in one of the deprecated function,
-* that is always resulting into complialation
-* warning. Removed deprecate attribute from PmcrEventCfg32
-* to fix un-necessary warning CR#1110990.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xpm_counter.h"
-#include "xil_sleeptimer.h"
-#include "xtime_l.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-typedef const u32 PmcrEventCfg32[XPM_CTRCOUNT];
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions *****************************/
-
-
-/******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @brief This function disables the Cortex R5 event counters.
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_DisableEventCounters(void)
-{
- u32 RegVal;
- /* Disable the event counters */
-#ifdef __GNUC__
- RegVal = mfcp(XREG_CP15_COUNT_ENABLE_CLR);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_COUNT_ENABLE_CLR, RegVal);
-#else
- { register u32 C15Reg __asm(XREG_CP15_COUNT_ENABLE_CLR);
- RegVal = C15Reg; }
-#endif
- RegVal |= XPM_EVENT_CNTRS_MASK;
- mtcp(XREG_CP15_COUNT_ENABLE_CLR, RegVal);
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function enables the Cortex R5 event counters.
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_EnableEventCounters(void)
-{
- u32 RegVal;
- /* Enable the event counters */
-#ifdef __GNUC__
- RegVal = mfcp(XREG_CP15_COUNT_ENABLE_SET);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_COUNT_ENABLE_SET, RegVal);
-#else
- { register u32 C15Reg __asm(XREG_CP15_COUNT_ENABLE_SET);
- RegVal = C15Reg; }
-#endif
- RegVal |= XPM_EVENT_CNTRS_MASK;
- mtcp(XREG_CP15_COUNT_ENABLE_SET, RegVal);
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function resets the Cortex R5 event counters.
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_ResetEventCounters(void)
-{
- u32 Reg;
-
-#ifdef __GNUC__
- Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
-#else
- { register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL);
- Reg = C15Reg; }
-#endif
- Reg |= (1U << 2U); /* reset event counters */
- mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
-}
-
-/*****************************************************************************/
-/**
- *
- * Disables the requested event counter.
- *
- *
- * @param EventCntrId: Event Counter ID. The counter ID is the same that
- * was earlier returned through a call to Xpm_SetUpAnEvent.
- * Cortex-R5 supports only 3 counters. The valid values are 0, 1,
- * or 2.
- *
- * @return
- * - XST_SUCCESS if successful.
- * - XST_FAILURE if the passed Counter ID is invalid
- * (i.e. greater than 2).
- *
- ******************************************************************************/
-u32 Xpm_DisableEvent(u32 EventCntrId)
-{
- u32 Counters;
- u32 CntrMask = 0x1U;
-
- if (EventCntrId > XPM_MAX_EVENTHANDLER_ID) {
- xil_printf("Invalid EventHandlerID\r\n");
- return XST_FAILURE;
- } else {
- CntrMask = CntrMask << EventCntrId;
-#ifdef __GNUC__
- Counters = mfcp(XREG_CP15_COUNT_ENABLE_CLR);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_COUNT_ENABLE_CLR, Counters);
-#else
- { register u32 C15Reg __asm(XREG_CP15_COUNT_ENABLE_CLR);
- Counters = C15Reg; }
-#endif
- Counters &= ~CntrMask;
- mtcp(XREG_CP15_COUNT_ENABLE_CLR, Counters);
- return XST_SUCCESS;
- }
-}
-
-/*****************************************************************************/
-/**
- *
- * Sets up one of the event counters to count events based on the Event ID
- * passed. For supported Event IDs please refer xpm_counter.h.
- * Upon invoked, the API searches for an available counter. After finding
- * one, it sets up the counter to count events for the requested event.
- *
- *
- * @param EventID: For valid values, please refer xpm_counter.h.
- *
- * @return
- * - Counter Number if successful. For Cortex-R5, valid return values are
- * 0, 1, or 2.
- * - XPM_NO_COUNTERS_AVAILABLE (0xFF) if all counters are being used
- *
- ******************************************************************************/
-u32 Xpm_SetUpAnEvent(u32 EventID)
-{
- u32 Counters;
- u32 OriginalCounters;
- u32 Index;
-
-#ifdef __GNUC__
- OriginalCounters = mfcp(XREG_CP15_COUNT_ENABLE_SET);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_COUNT_ENABLE_SET, OriginalCounters);
-#else
- { register u32 C15Reg __asm(XREG_CP15_COUNT_ENABLE_SET);
- OriginalCounters = C15Reg; }
-#endif
- OriginalCounters &= XPM_EVENT_CNTRS_BIT_MASK;
- Counters = OriginalCounters;
- if (Counters == XPM_ALL_EVENT_CNTRS_IN_USE) {
- xil_printf("No counters available\r\n");
- return XPM_NO_COUNTERS_AVAILABLE;
- } else {
- for(Index = 0U; Index < XPM_CTRCOUNT; Index++) {
- if ((Counters & 0x1U) == 0x0) {
- break;
- } else {
- Counters = Counters >> 0x1U;
- continue;
- }
- }
- }
-
- /* Select event counter */
- mtcp(XREG_CP15_EVENT_CNTR_SEL, Index);
- /* Set the event */
- mtcp(XREG_CP15_EVENT_TYPE_SEL, EventID);
- /* Enable event counter */
- mtcp(XREG_CP15_COUNT_ENABLE_SET, OriginalCounters | (1U << Index));
- return Index;
-}
-
-/*****************************************************************************/
-/**
- *
- * Reads the counter value for the requested counter ID. This is used to read
- * the number of events that has been counted for the requsted event ID.
- * This can only be called after a call to Xpm_SetUpAnEvent.
- *
- *
- * @param EventCntrId: The counter ID is the same that was earlier
- * returned through a call to Xpm_SetUpAnEvent.
- * Cortex-R5 supports only 3 counters. The valid values are 0, 1,
- * or 2.
- * @param CntVal: Pointer to a 32 bit unsigned int type. This is used to return
- * the event counter value.
- *
- * @return
- * - XST_SUCCESS if successful.
- * - XST_FAILURE if the passed Counter ID is invalid
- * (i.e. greater than 2).
- *
- ******************************************************************************/
-u32 Xpm_GetEventCounter(u32 EventCntrId, u32 *CntVal)
-{
- if (EventCntrId > XPM_MAX_EVENTHANDLER_ID) {
- xil_printf("Invalid Event Handler ID\r\n");
- return XST_FAILURE;
- } else {
- mtcp(XREG_CP15_EVENT_CNTR_SEL, EventCntrId);
-#ifdef __GNUC__
- *CntVal = mfcp(XREG_CP15_PERF_MONITOR_COUNT);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_PERF_MONITOR_COUNT, (*CntVal));
-#else
- { register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT);
- *CntVal = C15Reg; }
-#endif
- return XST_SUCCESS;
- }
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This is helper function used by sleep/usleep APIs to generate
-* delay in sec/usec
-*
-* @param delay - delay time in sec/usec
-* @param frequency - Number of countes in second/micro second
-*
-* @return None.
-*
-*****************************************************************************/
-
-void Xpm_SleepPerfCounter(u32 delay, u64 frequency)
-{
- u64 tEnd = 0U;
- u64 tCur = 0U;
- XCntrVal TimeHighVal = 0U;
- XCntrVal TimeLowVal1 = 0U;
- XCntrVal TimeLowVal2 = 0U;
-
-#if defined (__GNUC__)
- TimeLowVal1 = Xpm_ReadCycleCounterVal();
-#elif defined (__ICCARM__)
- Xpm_ReadCycleCounterVal(TimeLowVal1);
-#endif
- tEnd = (u64)TimeLowVal1 + ((u64)(delay) * frequency);
- do {
-#if defined (__GNUC__)
- TimeLowVal2 = Xpm_ReadCycleCounterVal();
-#elif defined (__ICCARM__)
- Xpm_ReadCycleCounterVal(TimeLowVal2);
-#endif
- if (TimeLowVal2 < TimeLowVal1) {
- TimeHighVal++;
- }
- TimeLowVal1 = TimeLowVal2;
- tCur = (((u64) TimeHighVal) << XSLEEP_TIMER_REG_SHIFT) |
- (u64)TimeLowVal2;
- }while (tCur < tEnd);
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function configures the Cortex R5 event counters controller,
-* with the event codes, in a configuration selected by the user and
-* enables the counters.
-*
-* @param PmcrCfg: Configuration value based on which the event counters
-* are configured.XPM_CNTRCFG* values defined in xpm_counter.h can
-* be utilized for setting configuration
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_SetEvents(s32 PmcrCfg)
-{
- u32 Counter;
- static PmcrEventCfg32 PmcrEvents[] = {
-
- {
- XPM_EVENT_SOFTINCR,
- XPM_EVENT_INSTRCACHEMISS,
- XPM_EVENT_DATACACHEMISS
- },
- {
- XPM_EVENT_DATACACHEACCESS,
- XPM_EVENT_DATAREAD,
- XPM_EVENT_DATAWRITE
- },
- {
- XPM_EVENT_INSTR,
- XPM_EVENT_DUALINSTR,
- XPM_EVENT_EXCEPTION
- },
- {
- XPM_EVENT_EXCEPTIONRET,
- XPM_EVENT_CHANGETOCONTEXID,
- XPM_EVENT_SWCHANGE
- },
- {
- XPM_EVENT_IMMEDIATEINSTR,
- XPM_EVENT_PROCEDURERET,
- XPM_EVENT_UNALIGNACCESS
- },
- {
- XPM_EVENT_BRANCHMISPREDICT,
- XPM_EVENT_CLOCKCYCLES,
- XPM_EVENT_BRANCHPREDICT
- },
- {
- XPM_EVENT_INSTRSTALL,
- XPM_EVENT_DATASTALL,
- XPM_EVENT_DATACACHEWRITE
- },
- {
- XPM_EVENT_EXTERNALMEMREQ,
- XPM_EVENT_LSUSTALL,
- XPM_EVENT_FORCEDRAINSTORE
- },
- {
- XPM_EVENT_INSTRTAGPARITY,
- XPM_EVENT_INSTRDATAPARITY,
- XPM_EVENT_DATATAGPARITY
- },
- {
- XPM_EVENT_DATADATAPARITY,
- XPM_EVENT_TCMERRORPREFETCH,
- XPM_EVENT_TCMERRORSTORE
- },
- {
- XPM_EVENT_INSTRCACHEACCESS,
- XPM_EVENT_DUALISSUEA,
- XPM_EVENT_DUALISSUEB
- },
- {
- XPM_EVENT_DUALISSUEOTHER,
- XPM_EVENT_FPA,
- XPM_EVENT_DATACACHEDATAERROR
- },
- {
- XPM_EVENT_DATACACHETAGERROR,
- XPM_EVENT_PROCESSORLIVELOCK,
- XPM_EVENT_ATCMMULTIBITERROR
- },
- {
- XPM_EVENT_B0TCMMULTIBITERROR,
- XPM_EVENT_B1TCMMULTIBITERROR,
- XPM_EVENT_ATCMSINGLEBITERROR
- },
- {
- XPM_EVENT_B0TCMSINGLEBITERROR,
- XPM_EVENT_B1TCMSINGLEBITERROR,
- XPM_EVENT_TCMERRORLSU
- },
- {
- XPM_EVENT_TCMERRORPFU,
- XPM_EVENT_TCMFATALERRORAXI,
- XPM_EVENT_TCMERRORAXI
- },
-
- };
- const u32 *ptr = PmcrEvents[PmcrCfg];
-
- Xpm_DisableEventCounters();
-
- for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
-
- /* Select event counter */
- mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
-
- /* Set the event */
- mtcp(XREG_CP15_EVENT_TYPE_SEL, ptr[Counter]);
- }
-
- Xpm_ResetEventCounters();
- Xpm_EnableEventCounters();
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function disables the event counters and returns the counter
-* values.
-*
-* @param PmCtrValue: Pointer to an array of type u32 PmCtrValue[6].
-* It is an output parameter which is used to return the PM
-* counter values.
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_GetEventCounters(u32 *PmCtrValue)
-{
- u32 Counter;
-
- Xpm_DisableEventCounters();
-
- for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
-
- mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
-#ifdef __GNUC__
- PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_PERF_MONITOR_COUNT, PmCtrValue[Counter]);
-#else
- { register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT);
- PmCtrValue[Counter] = Cp15Reg; }
-#endif
- }
-}
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2a/c1caec535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2a/c1caec535243001d18b399c1eb9b3628
deleted file mode 100644
index 27a10ad..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2a/c1caec535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,425 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xuartps_hw.h
-* @addtogroup uartps_v3_11
-* @{
-*
-* This header file contains the hardware interface of an XUartPs device.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00 drg/jz 01/12/10 First Release
-* 1.03a sg 09/04/12 Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
-* and XUARTPS_IXR_TTRIG.
-* Modified the names of these defines
-* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
-* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
-* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
-* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
-* 1.05a hk 08/22/13 Added prototype for uart reset and related
-* constant definitions.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
-* 3.6 ms 02/16/18 Updates flow control mode offset value in
-* modem control register.
-*
-*
-*
-******************************************************************************/
-#ifndef XUARTPS_HW_H /* prevent circular inclusions */
-#define XUARTPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets for the UART.
- * @{
- */
-#define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */
-#define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */
-#define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */
-#define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */
-#define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */
-#define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/
-#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */
-#define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */
-#define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */
-#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */
-#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */
-#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */
-#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */
-#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */
-#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */
-#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */
-#define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */
-/* @} */
-
-/** @name Control Register
- *
- * The Control register (CR) controls the major functions of the device.
- *
- * Control Register Bit Definition
- */
-
-#define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */
-#define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */
-#define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */
-#define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */
-#define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */
-#define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */
-#define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */
-#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */
-#define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */
-#define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */
-/* @}*/
-
-
-/** @name Mode Register
- *
- * The mode register (MR) defines the mode of transfer as well as the data
- * format. If this register is modified during transmission or reception,
- * data validity cannot be guaranteed.
- *
- * Mode Register Bit Definition
- * @{
- */
-#define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */
-#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */
-#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */
-#define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */
-#define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */
-#define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */
-#define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */
-#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */
-#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */
-#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */
-#define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */
-#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */
-#define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */
-#define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */
-#define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */
-#define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */
-#define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */
-#define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */
-#define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */
-#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */
-#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */
-#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */
-#define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */
-#define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */
-#define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */
-/* @} */
-
-
-/** @name Interrupt Registers
- *
- * Interrupt control logic uses the interrupt enable register (IER) and the
- * interrupt disable register (IDR) to set the value of the bits in the
- * interrupt mask register (IMR). The IMR determines whether to pass an
- * interrupt to the interrupt status register (ISR).
- * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
- * interrupt. IMR and ISR are read only, and IER and IDR are write only.
- * Reading either IER or IDR returns 0x00.
- *
- * All four registers have the same bit definitions.
- *
- * @{
- */
-#define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */
-#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */
-#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */
-#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */
-#define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */
-#define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */
-#define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */
-#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */
-#define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */
-#define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */
-#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */
-#define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */
-#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */
-#define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */
-#define XUARTPS_IXR_MASK 0x00003FFFU /**< Valid bit mask */
-/* @} */
-
-
-/** @name Baud Rate Generator Register
- *
- * The baud rate generator control register (BRGR) is a 16 bit register that
- * controls the receiver bit sample clock and baud rate.
- * Valid values are 1 - 65535.
- *
- * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
- * in the MR register.
- * @{
- */
-#define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */
-#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */
-#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */
-
-/** @name Baud Divisor Rate register
- *
- * The baud rate divider register (BDIV) controls how much the bit sample
- * rate is divided by. It sets the baud rate.
- * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
- *
- * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
- * the MR_CCLK bit in the MR register.
- * @{
- */
-#define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */
-#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */
-/* @} */
-
-
-/** @name Receiver Timeout Register
- *
- * Use the receiver timeout register (RTR) to detect an idle condition on
- * the receiver data line.
- *
- * @{
- */
-#define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */
-#define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */
-
-/** @name Receiver FIFO Trigger Level Register
- *
- * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
- * which the RX FIFO triggers an interrupt event.
- * @{
- */
-
-#define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */
-#define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */
-#define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */
-/* @} */
-
-/** @name Transmit FIFO Trigger Level Register
- *
- * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
- * which the TX FIFO triggers an interrupt event.
- * @{
- */
-
-#define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */
-#define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */
-/* @} */
-
-/** @name Modem Control Register
- *
- * This register (MODEMCR) controls the interface with the modem or data set,
- * or a peripheral device emulating a modem.
- *
- * @{
- */
-#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */
-#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */
-#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */
-/* @} */
-
-/** @name Modem Status Register
- *
- * This register (MODEMSR) indicates the current state of the control lines
- * from a modem, or another peripheral device, to the CPU. In addition, four
- * bits of the modem status register provide change information. These bits
- * are set to a logic 1 whenever a control input from the modem changes state.
- *
- * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
- * status interrupt is generated and this is reflected in the modem status
- * register.
- *
- * @{
- */
-#define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */
-#define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */
-#define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */
-#define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */
-#define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */
-#define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */
-#define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */
-#define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */
-#define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */
-/* @} */
-
-/** @name Channel Status Register
- *
- * The channel status register (CSR) is provided to enable the control logic
- * to monitor the status of bits in the channel interrupt status register,
- * even if these are masked out by the interrupt mask register.
- *
- * @{
- */
-#define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */
-#define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */
-#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */
-#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */
-#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */
-#define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */
-#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */
-#define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */
-#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */
-#define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */
-/* @} */
-
-/** @name Flow Delay Register
- *
- * Operation of the flow delay register (FLOWDEL) is very similar to the
- * receive FIFO trigger register. An internal trigger signal activates when the
- * FIFO is filled to the level set by this register. This trigger will not
- * cause an interrupt, although it can be read through the channel status
- * register. In hardware flow control mode, RTS is deactivated when the trigger
- * becomes active. RTS only resets when the FIFO level is four less than the
- * level of the flow delay trigger and the flow delay trigger is not activated.
- * A value less than 4 disables the flow delay.
- * @{
- */
-#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */
-/* @} */
-
-/** @name Receiver FIFO Byte Status Register
- *
- * The Receiver FIFO Status register is used to have a continuous
- * monitoring of the raw unmasked byte status information. The register
- * contains frame, parity and break status information for the top
- * four bytes in the RX FIFO.
- *
- * Receiver FIFO Byte Status Register Bit Definition
- * @{
- */
-#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /**< Byte3 Break Error */
-#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /**< Byte3 Frame Error */
-#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /**< Byte3 Parity Error */
-#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /**< Byte2 Break Error */
-#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /**< Byte2 Frame Error */
-#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /**< Byte2 Parity Error */
-#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /**< Byte1 Break Error */
-#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /**< Byte1 Frame Error */
-#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /**< Byte1 Parity Error */
-#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /**< Byte0 Break Error */
-#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /**< Byte0 Frame Error */
-#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /**< Byte0 Parity Error */
-#define XUARTPS_RXBS_MASK 0x00000007U /**< 3 bit RX byte status mask */
-/* @} */
-
-
-/*
- * Defines for backwards compatibility, will be removed
- * in the next version of the driver
- */
-#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD
-#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI
-#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR
-#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS
-
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-* Read a UART register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the base address of the
-* device.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
-*
-******************************************************************************/
-#define XUartPs_ReadReg(BaseAddress, RegOffset) \
- Xil_In32((BaseAddress) + (u32)(RegOffset))
-
-/***************************************************************************/
-/**
-* Write a UART register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the base address of the
-* device.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u16 RegisterValue)
-*
-******************************************************************************/
-#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
-
-/****************************************************************************/
-/**
-* Determine if there is receive data in the receiver and/or FIFO.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return TRUE if there is receive data, FALSE otherwise.
-*
-* @note C-Style signature:
-* u32 XUartPs_IsReceiveData(u32 BaseAddress)
-*
-******************************************************************************/
-#define XUartPs_IsReceiveData(BaseAddress) \
- !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
- (u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
-
-/****************************************************************************/
-/**
-* Determine if a byte of data can be sent with the transmitter.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the
-* FIFO.
-*
-* @note C-Style signature:
-* u32 XUartPs_IsTransmitFull(u32 BaseAddress)
-*
-******************************************************************************/
-#define XUartPs_IsTransmitFull(BaseAddress) \
- ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
- (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
-
-/************************** Function Prototypes ******************************/
-
-void XUartPs_SendByte(u32 BaseAddress, u8 Data);
-
-u8 XUartPs_RecvByte(u32 BaseAddress);
-
-void XUartPs_ResetHw(u32 BaseAddress);
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2a/d1ba6f585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2a/d1ba6f585243001d18b399c1eb9b3628
deleted file mode 100644
index fd281c5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2a/d1ba6f585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,131 +0,0 @@
-/******************************************************************************
- * xen.h
- *
- * Guest OS interface to Xen.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Copyright (c) 2004, K A Fraser
- */
-/*
-Copyright DornerWorks 2016
-
-Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-following conditions are met:
-1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
-following disclaimer.
-
-THIS SOFTWARE IS PROVIDED BY DORNERWORKS FOR USE ON THE CONTRACTED PROJECT, AND ANY EXPRESS OR IMPLIED WARRANTY
-IS LIMITED TO THIS USE. FOR ALL OTHER USES THIS SOFTWARE IS PROVIDED ''AS IS'' AND ANY EXPRESS OR IMPLIED
-WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL DORNERWORKS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#ifndef __XEN_H_
-#define __XEN_H_
-
-/*
- * HYPERCALLS
- */
-
-/* `incontents 100 hcalls List of hypercalls
- * ` enum hypercall_num { // __HYPERVISOR_* => HYPERVISOR_*()
- */
-
-#define __HYPERVISOR_set_trap_table 0
-#define __HYPERVISOR_mmu_update 1
-#define __HYPERVISOR_set_gdt 2
-#define __HYPERVISOR_stack_switch 3
-#define __HYPERVISOR_set_callbacks 4
-#define __HYPERVISOR_fpu_taskswitch 5
-#define __HYPERVISOR_sched_op_compat 6 /* compat since 0x00030101 */
-#define __HYPERVISOR_platform_op 7
-#define __HYPERVISOR_set_debugreg 8
-#define __HYPERVISOR_get_debugreg 9
-#define __HYPERVISOR_update_descriptor 10
-#define __HYPERVISOR_memory_op 12
-#define __HYPERVISOR_multicall 13
-#define __HYPERVISOR_update_va_mapping 14
-#define __HYPERVISOR_set_timer_op 15
-#define __HYPERVISOR_event_channel_op_compat 16 /* compat since 0x00030202 */
-#define __HYPERVISOR_xen_version 17
-#define __HYPERVISOR_console_io 18
-#define __HYPERVISOR_physdev_op_compat 19 /* compat since 0x00030202 */
-#define __HYPERVISOR_grant_table_op 20
-#define __HYPERVISOR_vm_assist 21
-#define __HYPERVISOR_update_va_mapping_otherdomain 22
-#define __HYPERVISOR_iret 23 /* x86 only */
-#define __HYPERVISOR_vcpu_op 24
-#define __HYPERVISOR_set_segment_base 25 /* x86/64 only */
-#define __HYPERVISOR_mmuext_op 26
-#define __HYPERVISOR_xsm_op 27
-#define __HYPERVISOR_nmi_op 28
-#define __HYPERVISOR_sched_op 29
-#define __HYPERVISOR_callback_op 30
-#define __HYPERVISOR_xenoprof_op 31
-#define __HYPERVISOR_event_channel_op 32
-#define __HYPERVISOR_physdev_op 33
-#define __HYPERVISOR_hvm_op 34
-#define __HYPERVISOR_sysctl 35
-#define __HYPERVISOR_domctl 36
-#define __HYPERVISOR_kexec_op 37
-#define __HYPERVISOR_tmem_op 38
-#define __HYPERVISOR_xc_reserved_op 39 /* reserved for XenClient */
-
-/* Architecture-specific hypercall definitions. */
-#define __HYPERVISOR_arch_0 48
-#define __HYPERVISOR_arch_1 49
-#define __HYPERVISOR_arch_2 50
-#define __HYPERVISOR_arch_3 51
-#define __HYPERVISOR_arch_4 52
-#define __HYPERVISOR_arch_5 53
-#define __HYPERVISOR_arch_6 54
-#define __HYPERVISOR_arch_7 55
-
-/* ` } */
-
-/*
- * Commands to HYPERVISOR_console_io().
- */
-#define CONSOLEIO_write 0
-#define CONSOLEIO_read 1
-
-/*
- * Commands to HYPERVISOR_hvm_op
- */
-#define HVMOP_set_param 0
-#define HVMOP_get_param 1
-
-/* DOMID_SELF is used in certain contexts to refer to oneself. */
-#define DOMID_SELF (0x7FF0U)
-
-
-#define XENMEM_add_to_physmap 7
-
-
-/* Console debug shared memory ring and event channel */
-#define HVM_PARAM_CONSOLE_PFN 17
-#define HVM_PARAM_CONSOLE_EVTCHN 18
-
-
-#endif /* __XEN_PUBLIC_XEN_H__ */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2b/3036df535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2b/3036df535243001d18b399c1eb9b3628
deleted file mode 100644
index 8d11ff8..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2b/3036df535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,365 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xscuwdt.h
-* @addtogroup scuwdt_v2_4
-* @{
-* @details
-*
-* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private
-* watchdog timer hardware.
-*
-* The XScuWdt driver supports the following features:
-* - Watchdog mode
-* - Timer mode
-* - Auto reload (timer mode only)
-*
-* The watchdog counter register is a down counter and starts decrementing when
-* the watchdog is started.
-* In watchdog mode, when the counter reaches 0, the Reset flag is set in the
-* Reset status register and the WDRESETREQ pin is asserted, causing a system
-* reset. The Reset flag is not reset by normal processor reset and is cleared
-* when written with a value of 1. This enables the user to differentiate a
-* normal reset and a reset caused by watchdog time-out. The user needs to call
-* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out.
-*
-* The IsWdtExpired function can be used to check if the watchdog was the cause
-* of the last reset. In this situation, call Initialize then call IsWdtExpired.
-* If the result is true, watchdog timeout caused the last system reset. The
-* application then needs to clear the Reset flag.
-*
-* In timer mode, when the counter reaches 0, the Event flag is set in the
-* Interrupt status register and if interrupts are enabled, interrupt ID 30 is
-* set as pending in the interrupt distributor. The IsTimerExpired function
-* is used to check if the watchdog counter has decremented to 0 in timer mode.
-* If auto-reload mode is enabled, the Counter register is automatically reloaded
-* from the Load register.
-*
-* Initialization and Configuration
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate with the Watchdog Timer.
-*
-* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The
-* user needs to first call the XScuWdt_LookupConfig() API which returns
-* the Configuration structure pointer which is passed as a parameter to
-* the XScuWdt_CfgInitialize() API.
-*
-* Interrupts
-*
-* The SCU Watchdog Timer supports interrupts in Timer mode.
-*
-* This driver does not provide a Interrupt Service Routine (ISR) for the device.
-* It is the responsibility of the application to provide one if needed. Refer to
-* the interrupt example provided with this driver for details on using the
-* Timer in interrupt mode.
-*
-* Virtual Memory
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-* Threads
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* Asserts
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* Building the driver
-*
-* The XScuWdt driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-*
-*
-* NOTE:
-* The watchdog timer is not a part of the snoop control unit as indicated
-* by the prefix "scu" in the name of the driver.
-* It is an independent module in APU.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 2.3 mus 08/31/20 Updated makefile to support parallel make and
-* incremental builds. It would help to reduce compilaton
-* time.
-* 2.3 sne 09/16/20 Fixed MISRA-C violations.
-* 2.4 sne 02/04/21 Fixed Doxygen warnings.
-*
-*
-******************************************************************************/
-#ifndef XSCUWDT_H /**< prevent circular inclusions */
-#define XSCUWDT_H /**< by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xscuwdt_hw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddr; /**< Base address of the device */
-} XScuWdt_Config;
-
-/**
- * The XScuWdt driver instance data. The user is required to allocate a
- * variable of this type for every watchdog/timer device in the system.
- * A pointer to a variable of this type is then passed to the driver API
- * functions.
- */
-typedef struct {
- XScuWdt_Config Config;/**< Hardware Configuration */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStarted; /**< Device watchdog timer is running */
-} XScuWdt;
-
-/************************** Variable Definitions *****************************/
-extern XScuWdt_Config XScuWdt_ConfigTable[];
-
-/***************** Macros (Inline Functions) Definitions *********************/
-/****************************************************************************/
-/**
-*
-* This function is used to check if the watchdog has timed-out and the last
-* reset was caused by the watchdog reset.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return
-* - TRUE if the watchdog has expired.
-* - FALSE if the watchdog has not expired.
-*
-* @note C-style signature:
-* int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_IsWdtExpired(InstancePtr) \
- ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_RST_STS_OFFSET) & \
- XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
-
-/****************************************************************************/
-/**
-*
-* This function is used to check if the watchdog counter has reached 0 in timer
-* mode.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return
-* - TRUE if the watchdog has expired.
-* - FALSE if the watchdog has not expired.
-*
-* @note C-style signature:
-* int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_IsTimerExpired(InstancePtr) \
- ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_ISR_OFFSET) & \
- XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
-
-/****************************************************************************/
-/**
-*
-* Re-start the watchdog timer. This macro will read the watchdog load register
-* and write the same value to load register to update the counter register.
-* An application needs to call this function periodically to keep the watchdog
-* from asserting the WDRESETREQ reset request output pin.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_RestartWdt(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_RestartWdt(InstancePtr) \
- XScuWdt_LoadWdt((InstancePtr), \
- (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_LOAD_OFFSET)))
-
-/****************************************************************************/
-/**
-*
-* Write to the watchdog timer load register. This will also update the
-* watchdog counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-* @param Value is the value to be written to the Watchdog Load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value)
-*
-******************************************************************************/
-#define XScuWdt_LoadWdt(InstancePtr, Value) \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_LOAD_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the
-* Watchdog control register.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_SetWdMode(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_SetWdMode(InstancePtr) \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET, \
- (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET) | \
- (XSCUWDT_CONTROL_WD_MODE_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321
-* successively to the Watchdog Disable Register.
-* The software must write 0x12345678 and 0x87654321 successively to the
-* Watchdog Disable Register so that the watchdog mode bit in the Watchdog
-* Control Register is set to zero.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_SetTimerMode(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_SetTimerMode(InstancePtr) \
-{ \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_DISABLE_OFFSET, \
- XSCUWDT_DISABLE_VALUE1); \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_DISABLE_OFFSET, \
- XSCUWDT_DISABLE_VALUE2); \
-}
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the watchdog control register.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return Contents of the watchdog control register.
-*
-* @note C-style signature:
- u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_GetControlReg(InstancePtr) \
- XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the watchdog control register.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-* @param ControlReg is the value to be written to the watchdog control
-* register.
-*
-* @return None.
-*
-* @note C-style signature:
- void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg)
-*
-******************************************************************************/
-#define XScuWdt_SetControlReg(InstancePtr, ControlReg) \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET, (ControlReg))
-
-/****************************************************************************/
-/**
-*
-* Enable auto-reload mode.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_EnableAutoReload(InstancePtr) \
- XScuWdt_SetControlReg((InstancePtr), \
- (XScuWdt_GetControlReg(InstancePtr) | \
- XSCUWDT_CONTROL_AUTO_RELOAD_MASK))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Lookup configuration in xscuwdt_sinit.c.
- */
-XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId);
-
-/*
- * Selftest function in xscuwdt_selftest.c
- */
-s32 XScuWdt_SelfTest(XScuWdt *InstancePtr);
-
-/*
- * Interface functions in xscuwdt.c
- */
-s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
- XScuWdt_Config *ConfigPtr, u32 EffectiveAddress);
-
-void XScuWdt_Start(XScuWdt *InstancePtr);
-
-void XScuWdt_Stop(XScuWdt *InstancePtr);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2b/308dfd565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2b/308dfd565243001d18b399c1eb9b3628
deleted file mode 100644
index 1e9e6fb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2b/308dfd565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,522 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xstatus.h
-*
-* @addtogroup common_status_codes Xilinx software status codes
-*
-* The xstatus.h file contains the Xilinx software status codes.These codes are
-* used throughout the Xilinx device drivers.
-*
-* @{
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XSTATUS_H /* prevent circular inclusions */
-#define XSTATUS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/*********************** Common statuses 0 - 500 *****************************/
-/**
-@name Common Status Codes for All Device Drivers
-@{
-*/
-#define XST_SUCCESS 0L
-#define XST_FAILURE 1L
-#define XST_DEVICE_NOT_FOUND 2L
-#define XST_DEVICE_BLOCK_NOT_FOUND 3L
-#define XST_INVALID_VERSION 4L
-#define XST_DEVICE_IS_STARTED 5L
-#define XST_DEVICE_IS_STOPPED 6L
-#define XST_FIFO_ERROR 7L /*!< An error occurred during an
- operation with a FIFO such as
- an underrun or overrun, this
- error requires the device to
- be reset */
-#define XST_RESET_ERROR 8L /*!< An error occurred which requires
- the device to be reset */
-#define XST_DMA_ERROR 9L /*!< A DMA error occurred, this error
- typically requires the device
- using the DMA to be reset */
-#define XST_NOT_POLLED 10L /*!< The device is not configured for
- polled mode operation */
-#define XST_FIFO_NO_ROOM 11L /*!< A FIFO did not have room to put
- the specified data into */
-#define XST_BUFFER_TOO_SMALL 12L /*!< The buffer is not large enough
- to hold the expected data */
-#define XST_NO_DATA 13L /*!< There was no data available */
-#define XST_REGISTER_ERROR 14L /*!< A register did not contain the
- expected value */
-#define XST_INVALID_PARAM 15L /*!< An invalid parameter was passed
- into the function */
-#define XST_NOT_SGDMA 16L /*!< The device is not configured for
- scatter-gather DMA operation */
-#define XST_LOOPBACK_ERROR 17L /*!< A loopback test failed */
-#define XST_NO_CALLBACK 18L /*!< A callback has not yet been
- registered */
-#define XST_NO_FEATURE 19L /*!< Device is not configured with
- the requested feature */
-#define XST_NOT_INTERRUPT 20L /*!< Device is not configured for
- interrupt mode operation */
-#define XST_DEVICE_BUSY 21L /*!< Device is busy */
-#define XST_ERROR_COUNT_MAX 22L /*!< The error counters of a device
- have maxed out */
-#define XST_IS_STARTED 23L /*!< Used when part of device is
- already started i.e.
- sub channel */
-#define XST_IS_STOPPED 24L /*!< Used when part of device is
- already stopped i.e.
- sub channel */
-#define XST_DATA_LOST 26L /*!< Driver defined error */
-#define XST_RECV_ERROR 27L /*!< Generic receive error */
-#define XST_SEND_ERROR 28L /*!< Generic transmit error */
-#define XST_NOT_ENABLED 29L /*!< A requested service is not
- available because it has not
- been enabled */
-#define XST_NO_ACCESS 30L /* Generic access error */
-#define XST_TIMEOUT 31L /*!< Event timeout occurred */
-
-/** @} */
-/***************** Utility Component statuses 401 - 500 *********************/
-/**
-@name Utility Component Status Codes 401 - 500
-@{
-*/
-#define XST_MEMTEST_FAILED 401L /*!< Memory test failed */
-
-/** @} */
-/***************** Common Components statuses 501 - 1000 *********************/
-/**
-@name Packet Fifo Status Codes 501 - 510
-@{
-*/
-/********************* Packet Fifo statuses 501 - 510 ************************/
-
-#define XST_PFIFO_LACK_OF_DATA 501L /*!< Not enough data in FIFO */
-#define XST_PFIFO_NO_ROOM 502L /*!< Not enough room in FIFO */
-#define XST_PFIFO_BAD_REG_VALUE 503L /*!< Self test, a register value
- was invalid after reset */
-#define XST_PFIFO_ERROR 504L /*!< Generic packet FIFO error */
-#define XST_PFIFO_DEADLOCK 505L /*!< Packet FIFO is reporting
- * empty and full simultaneously
- */
-/** @} */
-/**
-@name DMA Status Codes 511 - 530
-@{
-*/
-/************************** DMA statuses 511 - 530 ***************************/
-
-#define XST_DMA_TRANSFER_ERROR 511L /*!< Self test, DMA transfer
- failed */
-#define XST_DMA_RESET_REGISTER_ERROR 512L /*!< Self test, a register value
- was invalid after reset */
-#define XST_DMA_SG_LIST_EMPTY 513L /*!< Scatter gather list contains
- no buffer descriptors ready
- to be processed */
-#define XST_DMA_SG_IS_STARTED 514L /*!< Scatter gather not stopped */
-#define XST_DMA_SG_IS_STOPPED 515L /*!< Scatter gather not running */
-#define XST_DMA_SG_LIST_FULL 517L /*!< All the buffer descriptors of
- the scatter gather list are
- being used */
-#define XST_DMA_SG_BD_LOCKED 518L /*!< The scatter gather buffer
- descriptor which is to be
- copied over in the scatter
- list is locked */
-#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /*!< No buffer descriptors have been
- put into the scatter gather
- list to be committed */
-#define XST_DMA_SG_COUNT_EXCEEDED 521L /*!< The packet count threshold
- specified was larger than the
- total # of buffer descriptors
- in the scatter gather list */
-#define XST_DMA_SG_LIST_EXISTS 522L /*!< The scatter gather list has
- already been created */
-#define XST_DMA_SG_NO_LIST 523L /*!< No scatter gather list has
- been created */
-#define XST_DMA_SG_BD_NOT_COMMITTED 524L /*!< The buffer descriptor which was
- being started was not committed
- to the list */
-#define XST_DMA_SG_NO_DATA 525L /*!< The buffer descriptor to start
- has already been used by the
- hardware so it can't be reused
- */
-#define XST_DMA_SG_LIST_ERROR 526L /*!< General purpose list access
- error */
-#define XST_DMA_BD_ERROR 527L /*!< General buffer descriptor
- error */
-/** @} */
-/**
-@name IPIF Status Codes Codes 531 - 550
-@{
-*/
-/************************** IPIF statuses 531 - 550 ***************************/
-
-#define XST_IPIF_REG_WIDTH_ERROR 531L /*!< An invalid register width
- was passed into the function */
-#define XST_IPIF_RESET_REGISTER_ERROR 532L /*!< The value of a register at
- reset was not valid */
-#define XST_IPIF_DEVICE_STATUS_ERROR 533L /*!< A write to the device interrupt
- status register did not read
- back correctly */
-#define XST_IPIF_DEVICE_ACK_ERROR 534L /*!< The device interrupt status
- register did not reset when
- acked */
-#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /*!< The device interrupt enable
- register was not updated when
- other registers changed */
-#define XST_IPIF_IP_STATUS_ERROR 536L /*!< A write to the IP interrupt
- status register did not read
- back correctly */
-#define XST_IPIF_IP_ACK_ERROR 537L /*!< The IP interrupt status register
- did not reset when acked */
-#define XST_IPIF_IP_ENABLE_ERROR 538L /*!< IP interrupt enable register was
- not updated correctly when other
- registers changed */
-#define XST_IPIF_DEVICE_PENDING_ERROR 539L /*!< The device interrupt pending
- register did not indicate the
- expected value */
-#define XST_IPIF_DEVICE_ID_ERROR 540L /*!< The device interrupt ID register
- did not indicate the expected
- value */
-#define XST_IPIF_ERROR 541L /*!< Generic ipif error */
-/** @} */
-
-/****************** Device specific statuses 1001 - 4095 *********************/
-/**
-@name Ethernet Status Codes 1001 - 1050
-@{
-*/
-/********************* Ethernet statuses 1001 - 1050 *************************/
-
-#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /*!< Memory space is not big enough
- * to hold the minimum number of
- * buffers or descriptors */
-#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /*!< Memory allocation failed */
-#define XST_EMAC_MII_READ_ERROR 1003L /*!< MII read error */
-#define XST_EMAC_MII_BUSY 1004L /*!< An MII operation is in progress */
-#define XST_EMAC_OUT_OF_BUFFERS 1005L /*!< Driver is out of buffers */
-#define XST_EMAC_PARSE_ERROR 1006L /*!< Invalid driver init string */
-#define XST_EMAC_COLLISION_ERROR 1007L /*!< Excess deferral or late
- * collision on polled send */
-/** @} */
-/**
-@name UART Status Codes 1051 - 1075
-@{
-*/
-/*********************** UART statuses 1051 - 1075 ***************************/
-#define XST_UART
-
-#define XST_UART_INIT_ERROR 1051L
-#define XST_UART_START_ERROR 1052L
-#define XST_UART_CONFIG_ERROR 1053L
-#define XST_UART_TEST_FAIL 1054L
-#define XST_UART_BAUD_ERROR 1055L
-#define XST_UART_BAUD_RANGE 1056L
-
-/** @} */
-/**
-@name IIC Status Codes 1076 - 1100
-@{
-*/
-/************************ IIC statuses 1076 - 1100 ***************************/
-
-#define XST_IIC_SELFTEST_FAILED 1076 /*!< self test failed */
-#define XST_IIC_BUS_BUSY 1077 /*!< bus found busy */
-#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /*!< mastersend attempted with */
- /* general call address */
-#define XST_IIC_STAND_REG_RESET_ERROR 1079 /*!< A non parameterizable reg */
- /* value after reset not valid */
-#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /*!< Tx fifo included in design */
- /* value after reset not valid */
-#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /*!< Rx fifo included in design */
- /* value after reset not valid */
-#define XST_IIC_TBA_REG_RESET_ERROR 1082 /*!< 10 bit addr incl in design */
- /* value after reset not valid */
-#define XST_IIC_CR_READBACK_ERROR 1083 /*!< Read of the control register */
- /* didn't return value written */
-#define XST_IIC_DTR_READBACK_ERROR 1084 /*!< Read of the data Tx reg */
- /* didn't return value written */
-#define XST_IIC_DRR_READBACK_ERROR 1085 /*!< Read of the data Receive reg */
- /* didn't return value written */
-#define XST_IIC_ADR_READBACK_ERROR 1086 /*!< Read of the data Tx reg */
- /* didn't return value written */
-#define XST_IIC_TBA_READBACK_ERROR 1087 /*!< Read of the 10 bit addr reg */
- /* didn't return written value */
-#define XST_IIC_NOT_SLAVE 1088 /*!< The device isn't a slave */
-#define XST_IIC_ARB_LOST 1089 /*!< Arbitration lost for master */
-/** @} */
-/**
-@name ATMC Status Codes 1101 - 1125
-@{
-*/
-/*********************** ATMC statuses 1101 - 1125 ***************************/
-
-#define XST_ATMC_ERROR_COUNT_MAX 1101L /*!< the error counters in the ATM
- controller hit the max value
- which requires the statistics
- to be cleared */
-/** @} */
-/**
-@name Flash Status Codes 1126 - 1150
-@{
-*/
-/*********************** Flash statuses 1126 - 1150 **************************/
-
-#define XST_FLASH_BUSY 1126L /*!< Flash is erasing or programming
- */
-#define XST_FLASH_READY 1127L /*!< Flash is ready for commands */
-#define XST_FLASH_ERROR 1128L /*!< Flash had detected an internal
- error. Use XFlash_DeviceControl
- to retrieve device specific codes
- */
-#define XST_FLASH_ERASE_SUSPENDED 1129L /*!< Flash is in suspended erase state
- */
-#define XST_FLASH_WRITE_SUSPENDED 1130L /*!< Flash is in suspended write state
- */
-#define XST_FLASH_PART_NOT_SUPPORTED 1131L /*!< Flash type not supported by
- driver */
-#define XST_FLASH_NOT_SUPPORTED 1132L /*!< Operation not supported */
-#define XST_FLASH_TOO_MANY_REGIONS 1133L /*!< Too many erase regions */
-#define XST_FLASH_TIMEOUT_ERROR 1134L /*!< Programming or erase operation
- aborted due to a timeout */
-#define XST_FLASH_ADDRESS_ERROR 1135L /*!< Accessed flash outside its
- addressible range */
-#define XST_FLASH_ALIGNMENT_ERROR 1136L /*!< Write alignment error */
-#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /*!< Couldn't return immediately from
- write/erase function with
- XFL_NON_BLOCKING_WRITE/ERASE
- option cleared */
-#define XST_FLASH_CFI_QUERY_ERROR 1138L /*!< Failed to query the device */
-/** @} */
-/**
-@name SPI Status Codes 1151 - 1175
-@{
-*/
-/*********************** SPI statuses 1151 - 1175 ****************************/
-
-#define XST_SPI_MODE_FAULT 1151 /*!< master was selected as slave */
-#define XST_SPI_TRANSFER_DONE 1152 /*!< data transfer is complete */
-#define XST_SPI_TRANSMIT_UNDERRUN 1153 /*!< slave underruns transmit register */
-#define XST_SPI_RECEIVE_OVERRUN 1154 /*!< device overruns receive register */
-#define XST_SPI_NO_SLAVE 1155 /*!< no slave has been selected yet */
-#define XST_SPI_TOO_MANY_SLAVES 1156 /*!< more than one slave is being
- * selected */
-#define XST_SPI_NOT_MASTER 1157 /*!< operation is valid only as master */
-#define XST_SPI_SLAVE_ONLY 1158 /*!< device is configured as slave-only
- */
-#define XST_SPI_SLAVE_MODE_FAULT 1159 /*!< slave was selected while disabled */
-#define XST_SPI_SLAVE_MODE 1160 /*!< device has been addressed as slave */
-#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /*!< device received data in slave mode */
-
-#define XST_SPI_COMMAND_ERROR 1162 /*!< unrecognised command - qspi only */
-#define XST_SPI_POLL_DONE 1163 /*!< controller completed polling the
- device for status */
-/** @} */
-/**
-@name OPB Arbiter Status Codes 1176 - 1200
-@{
-*/
-/********************** OPB Arbiter statuses 1176 - 1200 *********************/
-
-#define XST_OPBARB_INVALID_PRIORITY 1176 /*!< the priority registers have either
- * one master assigned to two or more
- * priorities, or one master not
- * assigned to any priority
- */
-#define XST_OPBARB_NOT_SUSPENDED 1177 /*!< an attempt was made to modify the
- * priority levels without first
- * suspending the use of priority
- * levels
- */
-#define XST_OPBARB_PARK_NOT_ENABLED 1178 /*!< bus parking by id was enabled but
- * bus parking was not enabled
- */
-#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /*!< the arbiter must be in fixed
- * priority mode to allow the
- * priorities to be changed
- */
-/** @} */
-/**
-@name INTC Status Codes 1201 - 1225
-@{
-*/
-/************************ Intc statuses 1201 - 1225 **************************/
-
-#define XST_INTC_FAIL_SELFTEST 1201 /*!< self test failed */
-#define XST_INTC_CONNECT_ERROR 1202 /*!< interrupt already in use */
-/** @} */
-/**
-@name TmrCtr Status Codes 1226 - 1250
-@{
-*/
-/********************** TmrCtr statuses 1226 - 1250 **************************/
-
-#define XST_TMRCTR_TIMER_FAILED 1226 /*!< self test failed */
-/** @} */
-/**
-@name WdtTb Status Codes 1251 - 1275
-@{
-*/
-/********************** WdtTb statuses 1251 - 1275 ***************************/
-
-#define XST_WDTTB_TIMER_FAILED 1251L
-/** @} */
-/**
-@name PlbArb status Codes 1276 - 1300
-@{
-*/
-/********************** PlbArb statuses 1276 - 1300 **************************/
-
-#define XST_PLBARB_FAIL_SELFTEST 1276L
-/** @} */
-/**
-@name Plb2Opb Status Codes 1301 - 1325
-@{
-*/
-/********************** Plb2Opb statuses 1301 - 1325 *************************/
-
-#define XST_PLB2OPB_FAIL_SELFTEST 1301L
-/** @} */
-/**
-@name Opb2Plb Status 1326 - 1350
-@{
-*/
-/********************** Opb2Plb statuses 1326 - 1350 *************************/
-
-#define XST_OPB2PLB_FAIL_SELFTEST 1326L
-/** @} */
-/**
-@name SysAce Status Codes 1351 - 1360
-@{
-*/
-/********************** SysAce statuses 1351 - 1360 **************************/
-
-#define XST_SYSACE_NO_LOCK 1351L /*!< No MPU lock has been granted */
-/** @} */
-/**
-@name PCI Bridge Status Codes 1361 - 1375
-@{
-*/
-/********************** PCI Bridge statuses 1361 - 1375 **********************/
-
-#define XST_PCI_INVALID_ADDRESS 1361L
-/** @} */
-/**
-@name FlexRay Constants 1400 - 1409
-@{
-*/
-/********************** FlexRay constants 1400 - 1409 *************************/
-
-#define XST_FR_TX_ERROR 1400
-#define XST_FR_TX_BUSY 1401
-#define XST_FR_BUF_LOCKED 1402
-#define XST_FR_NO_BUF 1403
-/** @} */
-/**
-@name USB constants 1410 - 1420
-@{
-*/
-/****************** USB constants 1410 - 1420 *******************************/
-
-#define XST_USB_ALREADY_CONFIGURED 1410
-#define XST_USB_BUF_ALIGN_ERROR 1411
-#define XST_USB_NO_DESC_AVAILABLE 1412
-#define XST_USB_BUF_TOO_BIG 1413
-#define XST_USB_NO_BUF 1414
-/** @} */
-/**
-@name HWICAP constants 1421 - 1429
-@{
-*/
-/****************** HWICAP constants 1421 - 1429 *****************************/
-
-#define XST_HWICAP_WRITE_DONE 1421
-
-/** @} */
-/**
-@name AXI VDMA constants 1430 - 1440
-@{
-*/
-/****************** AXI VDMA constants 1430 - 1440 *****************************/
-
-#define XST_VDMA_MISMATCH_ERROR 1430
-/** @} */
-/**
-@name NAND Flash Status Codes 1441 - 1459
-@{
-*/
-/*********************** NAND Flash statuses 1441 - 1459 *********************/
-
-#define XST_NAND_BUSY 1441L /*!< Flash is erasing or
- * programming
- */
-#define XST_NAND_READY 1442L /*!< Flash is ready for commands
- */
-#define XST_NAND_ERROR 1443L /*!< Flash had detected an
- * internal error.
- */
-#define XST_NAND_PART_NOT_SUPPORTED 1444L /*!< Flash type not supported by
- * driver
- */
-#define XST_NAND_OPT_NOT_SUPPORTED 1445L /*!< Operation not supported
- */
-#define XST_NAND_TIMEOUT_ERROR 1446L /*!< Programming or erase
- * operation aborted due to a
- * timeout
- */
-#define XST_NAND_ADDRESS_ERROR 1447L /*!< Accessed flash outside its
- * addressible range
- */
-#define XST_NAND_ALIGNMENT_ERROR 1448L /*!< Write alignment error
- */
-#define XST_NAND_PARAM_PAGE_ERROR 1449L /*!< Failed to read parameter
- * page of the device
- */
-#define XST_NAND_CACHE_ERROR 1450L /*!< Flash page buffer error
- */
-
-#define XST_NAND_WRITE_PROTECTED 1451L /*!< Flash is write protected
- */
-/** @} */
-
-/**************************** Type Definitions *******************************/
-
-typedef s32 XStatus;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
-
-/**
-* @} End of "addtogroup common_status_codes".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2b/40b55f585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2b/40b55f585243001d18b399c1eb9b3628
deleted file mode 100644
index 939d0ef..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2b/40b55f585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,246 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file translation_table.s
-*
-* @addtogroup a53_64_boot_code
-* @{
-*
translation_table.S
-* translation_table.S contains a static page table required by MMU for
-* cortex-A53. This translation table is flat mapped (input address = output
-* address) with default memory attributes defined for zynq ultrascale+
-* architecture. It utilizes translation granual size of 4KB with 2MB section
-* size for initial 4GB memory and 1GB section size for memory after 4GB.
-* The overview of translation table memory attributes is described below.
-*
-*| | Memory Range | Definition in Translation Table |
-*|-----------------------|-----------------------------|-----------------------------------|
-*| DDR | 0x0000000000 - 0x007FFFFFFF | Normal write-back Cacheable |
-*| PL | 0x0080000000 - 0x00BFFFFFFF | Strongly Ordered |
-*| QSPI, lower PCIe | 0x00C0000000 - 0x00EFFFFFFF | Strongly Ordere |
-*| Reserved | 0x00F0000000 - 0x00F7FFFFFF | Unassigned |
-*| STM Coresight | 0x00F8000000 - 0x00F8FFFFFF | Strongly Ordered |
-*| GIC | 0x00F9000000 - 0x00F91FFFFF | Strongly Ordered |
-*| Reserved | 0x00F9200000 - 0x00FCFFFFFF | Unassigned |
-*| FPS, LPS slaves | 0x00FD000000 - 0x00FFBFFFFF | Strongly Ordered |
-*| CSU, PMU | 0x00FFC00000 - 0x00FFDFFFFF | Strongly Ordered |
-*| TCM, OCM | 0x00FFE00000 - 0x00FFFFFFFF | Normal inner write-back cacheable |
-*| Reserved | 0x0100000000 - 0x03FFFFFFFF | Unassigned |
-*| PL, PCIe | 0x0400000000 - 0x07FFFFFFFF | Strongly Ordered |
-*| DDR | 0x0800000000 - 0x0FFFFFFFFF | Normal inner write-back cacheable |
-*| PL, PCIe | 0x1000000000 - 0xBFFFFFFFFF | Strongly Ordered |
-*| Reserved | 0xC000000000 - 0xFFFFFFFFFF | Unassigned |
-*
-* @note
-*
-* For DDR region 0x0000000000 - 0x007FFFFFFF, a system where DDR is less than
-* 2GB, region after DDR and before PL is marked as undefined/reserved in
-* translation table. Region 0xF9100000 - 0xF91FFFFF is reserved memory in
-* 0x00F9000000 - 0x00F91FFFFF range, but it is marked as strongly ordered
-* because minimum section size in translation table section is 2MB. Region
-* 0x00FFC00000 - 0x00FFDFFFFF contains CSU and PMU memory which are marked as
-* Device since it is less than 1MB and falls in a region with device memory.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00 pkp 05/21/14 Initial version
-* 5.04 pkp 12/18/15 Updated the address map according to proper address map
-* 6.0 mus 07/20/16 Added warning for ddrless HW design CR-954977
-* 6.2 pkp 12/14/16 DDR memory in 0x800000000 - 0xFFFFFFFFF range is marked
-* as normal writeback for the size defined in hdf and rest
-* of the memory in that 32GB range is marked as reserved.
-* 6.4 mus 08/10/17 Marked memory as a outer shareable for EL1 NS execution,
-* to support CCI enabled IP's.
-*
-*
-******************************************************************************/
-#include "xparameters.h"
-#include "bspconfig.h"
-
- .globl MMUTableL0
- .globl MMUTableL1
- .globl MMUTableL2
-
- .set reserved, 0x0 /* Fault*/
- #if EL1_NONSECURE
- .set Memory, 0x405 | (2 << 8) | (0x0) /* normal writeback write allocate outer shared read write */
- #else
- .set Memory, 0x405 | (3 << 8) | (0x0) /* normal writeback write allocate inner shared read write */
- #endif
- .set Device, 0x409 | (1 << 53)| (1 << 54) |(0x0) /* strongly ordered read write non executable*/
- .section .mmu_tbl0,"a"
-
-MMUTableL0:
-
-.set SECT, MMUTableL1 /* 0x0000_0000 - 0x7F_FFFF_FFFF */
-.8byte SECT + 0x3
-.set SECT, MMUTableL1+0x1000 /* 0x80_0000_0000 - 0xFF_FFFF_FFFF */
-.8byte SECT + 0x3
-
- .section .mmu_tbl1,"a"
-
-MMUTableL1:
-
-.set SECT, MMUTableL2 /* 0x0000_0000 - 0x3FFF_FFFF */
-.8byte SECT + 0x3 /* 1GB DDR */
-
-.rept 0x3 /* 0x4000_0000 - 0xFFFF_FFFF */
-.set SECT, SECT + 0x1000 /*1GB DDR, 1GB PL, 2GB other devices n memory */
-.8byte SECT + 0x3
-.endr
-
-.set SECT,0x100000000
-.rept 0xC /* 0x0001_0000_0000 - 0x0003_FFFF_FFFF */
-.8byte SECT + reserved /* 12GB Reserved */
-.set SECT, SECT + 0x40000000
-.endr
-
-.rept 0x10 /* 0x0004_0000_0000 - 0x0007_FFFF_FFFF */
-.8byte SECT + Device /* 8GB PL, 8GB PCIe */
-.set SECT, SECT + 0x40000000
-.endr
-
-
-#ifdef XPAR_PSU_DDR_1_S_AXI_BASEADDR
-.set DDR_1_START, XPAR_PSU_DDR_1_S_AXI_BASEADDR
-.set DDR_1_END, XPAR_PSU_DDR_1_S_AXI_HIGHADDR
-.set DDR_1_SIZE, (DDR_1_END - DDR_1_START)+1
-.if DDR_1_SIZE > 0x800000000
-/* If DDR size is larger than 32GB, truncate to 32GB */
-.set DDR_1_REG, 0x20
-.else
-.set DDR_1_REG, DDR_1_SIZE/0x40000000
-.endif
-#else
-.set DDR_1_REG, 0
-#warning "There's no DDR_1 in the HW design. MMU translation table marks 32 GB DDR address space as undefined"
-#endif
-
-.set UNDEF_1_REG, 0x20 - DDR_1_REG
-
-.rept DDR_1_REG /* DDR based on size in hdf*/
-.8byte SECT + Memory
-.set SECT, SECT+0x40000000
-.endr
-
-.rept UNDEF_1_REG /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-
-.rept 0x1C0 /* 0x0010_0000_0000 - 0x007F_FFFF_FFFF */
-.8byte SECT + Device /* 448 GB PL */
-.set SECT, SECT + 0x40000000
-.endr
-
-
-.rept 0x100 /* 0x0080_0000_0000 - 0x00BF_FFFF_FFFF */
-.8byte SECT + Device /* 256GB PCIe */
-.set SECT, SECT + 0x40000000
-.endr
-
-
-.rept 0x100 /* 0x00C0_0000_0000 - 0x00FF_FFFF_FFFF */
-.8byte SECT + reserved /* 256GB reserved */
-.set SECT, SECT + 0x40000000
-.endr
-
-
-.section .mmu_tbl2,"a"
-
-MMUTableL2:
-
-.set SECT, 0
-
-#ifdef XPAR_PSU_DDR_0_S_AXI_BASEADDR
-.set DDR_0_START, XPAR_PSU_DDR_0_S_AXI_BASEADDR
-.set DDR_0_END, XPAR_PSU_DDR_0_S_AXI_HIGHADDR
-.set DDR_0_SIZE, (DDR_0_END - DDR_0_START)+1
-.if DDR_0_SIZE > 0x80000000
-/* If DDR size is larger than 2GB, truncate to 2GB */
-.set DDR_0_REG, 0x400
-.else
-.set DDR_0_REG, DDR_0_SIZE/0x200000
-.endif
-#else
-.set DDR_0_REG, 0
-#warning "There's no DDR_0 in the HW design. MMU translation table marks 2 GB DDR address space as undefined"
-#endif
-
-.set UNDEF_0_REG, 0x400 - DDR_0_REG
-
-.rept DDR_0_REG /* DDR based on size in hdf*/
-.8byte SECT + Memory
-.set SECT, SECT+0x200000
-.endr
-
-.rept UNDEF_0_REG /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x0200 /* 0x8000_0000 - 0xBFFF_FFFF */
-.8byte SECT + Device /* 1GB lower PL */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x0100 /* 0xC000_0000 - 0xDFFF_FFFF */
-.8byte SECT + Device /* 512MB QSPI */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x080 /* 0xE000_0000 - 0xEFFF_FFFF */
-.8byte SECT + Device /* 256MB lower PCIe */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x040 /* 0xF000_0000 - 0xF7FF_FFFF */
-.8byte SECT + reserved /* 128MB Reserved */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x8 /* 0xF800_0000 - 0xF8FF_FFFF */
-.8byte SECT + Device /* 16MB coresight */
-.set SECT, SECT+0x200000
-.endr
-
-/* 1MB RPU LLP is marked for 2MB region as the minimum block size in
- translation table is 2MB and adjacent 63MB reserved region is
- converted to 62MB */
-
-.rept 0x1 /* 0xF900_0000 - 0xF91F_FFFF */
-.8byte SECT + Device /* 2MB RPU low latency port */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x1F /* 0xF920_0000 - 0xFCFF_FFFF */
-.8byte SECT + reserved /* 62MB Reserved */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x8 /* 0xFD00_0000 - 0xFDFF_FFFF */
-.8byte SECT + Device /* 16MB FPS */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0xE /* 0xFE00_0000 - 0xFFBF_FFFF */
-.8byte SECT + Device /* 28MB LPS */
-.set SECT, SECT+0x200000
-.endr
-
- /* 0xFFC0_0000 - 0xFFDF_FFFF */
-.8byte SECT + Device /*2MB PMU/CSU */
-
-.set SECT, SECT+0x200000 /* 0xFFE0_0000 - 0xFFFF_FFFF*/
-.8byte SECT + Memory /*2MB OCM/TCM*/
-
-.end
-/**
-* @} End of "addtogroup a53_64_boot_code".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2b/50837d525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2b/50837d525243001d18b399c1eb9b3628
deleted file mode 100644
index 27b3df1..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2b/50837d525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,105 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#ifndef PROFILE_H
-#define PROFILE_H 1
-
-#include
-#include "xil_types.h"
-#include "profile_config.h"
-
-#ifdef PROC_MICROBLAZE
-#include "mblaze_nt_types.h"
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void _system_init( void ) ;
-void _system_clean( void ) ;
-void mcount(u32 frompc, u32 selfpc);
-void profile_intr_handler( void ) ;
-void _profile_init( void );
-
-
-
-/****************************************************************************
- * Profiling on hardware - Hash table maintained on hardware and data sent
- * to xmd for gmon.out generation.
- ****************************************************************************/
-/*
- * histogram counters are unsigned shorts (according to the kernel).
- */
-#define HISTCOUNTER u16
-
-struct tostruct {
- u32 selfpc;
- s32 count;
- s16 link;
- u16 pad;
-};
-
-struct fromstruct {
- u32 frompc ;
- s16 link ;
- u16 pad ;
-} ;
-
-/*
- * general rounding functions.
- */
-#define ROUNDDOWN(x,y) (((x)/(y))*(y))
-#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y))
-
-/*
- * The profiling data structures are housed in this structure.
- */
-struct gmonparam {
- s32 state;
-
- /* Histogram Information */
- u16 *kcount; /* No. of bins in histogram */
- u32 kcountsize; /* Histogram samples */
-
- /* Call-graph Information */
- struct fromstruct *froms;
- u32 fromssize;
- struct tostruct *tos;
- u32 tossize;
-
- /* Initialization I/Ps */
- u32 lowpc;
- u32 highpc;
- u32 textsize;
- /* u32 cg_froms, */
- /* u32 cg_tos, */
-};
-extern struct gmonparam *_gmonparam;
-extern s32 n_gmon_sections;
-
-/*
- * Possible states of profiling.
- */
-#define GMON_PROF_ON 0
-#define GMON_PROF_BUSY 1
-#define GMON_PROF_ERROR 2
-#define GMON_PROF_OFF 3
-
-/*
- * Sysctl definitions for extracting profiling information from the kernel.
- */
-#define GPROF_STATE 0 /* int: profiling enabling variable */
-#define GPROF_COUNT 1 /* struct: profile tick count buffer */
-#define GPROF_FROMS 2 /* struct: from location hash bucket */
-#define GPROF_TOS 3 /* struct: destination/count structure */
-#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PROFILE_H */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2b/c06891575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2b/c06891575243001d18b399c1eb9b3628
deleted file mode 100644
index 6d07851..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2b/c06891575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,60 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm.h
-*
-* @addtogroup a9_specific Cortex A9 Processor Specific Include Files
-*
-* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h.
-*
-* The xreg_cortexa9.h file contains definitions for inline assembler code.
-* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers,
-* co-processor registers and Debug registers.
-*
-* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
-* assembler instructions, available as macros. These can be very useful for
-* tasks such as setting or getting special purpose registers, synchronization,
-* or cache manipulation etc. These inline assembler instructions can be used
-* from drivers and user applications written in C.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 10/18/09 First release
-* 3.04a sdm 01/02/12 Remove redundant dsb in mcr instruction.
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-*
-******************************************************************************/
-#ifndef XPSEUDO_ASM_H
-#define XPSEUDO_ASM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xreg_cortexa9.h"
-#ifdef __GNUC__
- #include "xpseudo_asm_gcc.h"
-#elif defined (__ICCARM__)
- #include "xpseudo_asm_iccarm.h"
-#else
- #include "xpseudo_asm_rvct.h"
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XPSEUDO_ASM_H */
-/**
-* @} End of "addtogroup a9_specific".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2c/21c3a3585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2c/21c3a3585243001d18b399c1eb9b3628
deleted file mode 100644
index 9c39cba..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2c/21c3a3585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,15 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: MIT
-*
-******************************************************************************/
-#include "xil_types.h"
-
-/* Stub for exit() sys-call */
-__attribute__((weak)) void _sys_exit(__attribute__((unused)) s32 rc)
-{
- while(1) {
- ;
- }
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2c/709407565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2c/709407565243001d18b399c1eb9b3628
deleted file mode 100644
index 6d07851..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2c/709407565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,60 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm.h
-*
-* @addtogroup a9_specific Cortex A9 Processor Specific Include Files
-*
-* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h.
-*
-* The xreg_cortexa9.h file contains definitions for inline assembler code.
-* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers,
-* co-processor registers and Debug registers.
-*
-* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
-* assembler instructions, available as macros. These can be very useful for
-* tasks such as setting or getting special purpose registers, synchronization,
-* or cache manipulation etc. These inline assembler instructions can be used
-* from drivers and user applications written in C.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 10/18/09 First release
-* 3.04a sdm 01/02/12 Remove redundant dsb in mcr instruction.
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- --------- -------------------------------------------------------
-* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
-* function for PMUFW.
-* 7.2 adk 08/01/20 Added versal support for the XGetPSVersion_Info function.
-* 7.6 mus 08/23/21 Updated prototypes for functions which are not taking any
-* arguments with void keyword. This has been done to fix
-* compilation warnings with "-Wstrict-prototypes" flag.
-* It fixes CR#1108601.
-* 7.6 mus 08/30/21 Updated flag checking to fix compilation warnings
-* reported with "-Wundef" flag.
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */
-#define XPLATFORM_INFO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-#if defined (versal)
-#define XPAR_PMC_TAP_BASEADDR 0xF11A0000U
-#define XPAR_PMC_TAP_VERSION_OFFSET 0x00000004U
-#define XPLAT_PS_VERSION_ADDRESS (XPAR_PMC_TAP_BASEADDR + \
- XPAR_PMC_TAP_VERSION_OFFSET)
-#else
-#define XPAR_CSU_BASEADDR 0xFFCA0000U
-#define XPAR_CSU_VER_OFFSET 0x00000044U
-#define XPLAT_PS_VERSION_ADDRESS (XPAR_CSU_BASEADDR + \
- XPAR_CSU_VER_OFFSET)
-#endif
-#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
-#define XPLAT_ZYNQ_ULTRA_MP 0x1
-#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
-#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
-#define XPLAT_ZYNQ 0x4
-#define XPLAT_MICROBLAZE 0x5
-#define XPLAT_VERSAL 0x6U
-
-#define XPS_VERSION_1 0x0
-#define XPS_VERSION_2 0x1
-#define XPLAT_INFO_MASK (0xF)
-
-#if defined (versal)
-#define XPS_VERSION_INFO_MASK 0xFF00U
-#define XPS_VERSION_INFO_SHIFT 0x8U
-#define XPLAT_INFO_SHIFT 0x18U
-#else
-#define XPS_VERSION_INFO_MASK (0xF)
-#define XPS_VERSION_INFO_SHIFT 0x0U
-#define XPLAT_INFO_SHIFT 0xCU
-#endif
-
-/**************************** Type Definitions *******************************/
-/**
- *@endcond
- */
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-u32 XGetPlatform_Info(void);
-
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU) || defined (versal)
-u32 XGetPSVersion_Info(void);
-#endif
-
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
-u32 XGet_Zynq_UltraMp_Platform_info(void);
-#endif
-/************************** Function Prototypes ******************************/
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_platform_info".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2c/944e73565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2c/944e73565243001d18b399c1eb9b3628
deleted file mode 100644
index 0036459..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2c/944e73565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,14 +0,0 @@
-#include "xparameters.h"
-#include "xuartps_hw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-char inbyte(void);
-#ifdef __cplusplus
-}
-#endif
-
-char inbyte(void) {
- return XUartPs_RecvByte(STDIN_BASEADDRESS);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2c/c0f359595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2c/c0f359595243001d18b399c1eb9b3628
deleted file mode 100644
index ef12a6d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2c/c0f359595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,39 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-* File : microblaze_disable_icache.s
-* Date : 2002, March 20.
-* Company: Xilinx
-* Group : Emerging Software Technologies
-*
-* Summary:
-* Disable L1 icache on the microblaze.
-*
-*
-******************************************************************************/
-
-#include "xparameters.h"
-
- .text
- .globl microblaze_disable_icache
- .ent microblaze_disable_icache
- .align 2
-microblaze_disable_icache:
-#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
- rtsd r15, 8
- msrclr r0, 0x20
-#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- #Read the MSR register
- mfs r8, rmsr
- #Clear the icache enable bit
- andi r8, r8, ~(0x20)
- #Save the MSR register
- mts rmsr, r8
- #Return
- rtsd r15, 8
- nop
-#endif
- .end microblaze_disable_icache
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2c/f087d5555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2c/f087d5555243001d18b399c1eb9b3628
deleted file mode 100644
index 7307646..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2c/f087d5555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,11 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#include "xil_types.h"
-/* Stub for open sys-call */
-__weak s32 _sys_open(const char8* name, s32 openmode)
-{
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2d/40a89a525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2d/40a89a525243001d18b399c1eb9b3628
deleted file mode 100644
index 33822bf..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2d/40a89a525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,843 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
- *
- * @file xemacps.h
-* @addtogroup emacps_v3_15
-* @{
-* @details
- *
- * The Xilinx Embedded Processor Block Ethernet driver.
- *
- * For a full description of XEMACPS features, please see the hardware spec.
- * This driver supports the following features:
- * - Memory mapped access to host interface registers
- * - Statistics counter registers for RMON/MIB
- * - API for interrupt driven frame transfers for hardware configured DMA
- * - Virtual memory support
- * - Unicast, broadcast, and multicast receive address filtering
- * - Full and half duplex operation
- * - Automatic PAD & FCS insertion and stripping
- * - Flow control
- * - Support up to four 48bit addresses
- * - Address checking for four specific 48bit addresses
- * - VLAN frame support
- * - Pause frame support
- * - Large frame support up to 1536 bytes
- * - Checksum offload
- *
- * Driver Description
- *
- * The device driver enables higher layer software (e.g., an application) to
- * communicate to the XEmacPs. The driver handles transmission and reception
- * of Ethernet frames, as well as configuration and control. No pre or post
- * processing of frame data is performed. The driver does not validate the
- * contents of an incoming frame in addition to what has already occurred in
- * hardware.
- * A single device driver can support multiple devices even when those devices
- * have significantly different configurations.
- *
- * Initialization & Configuration
- *
- * The XEmacPs_Config structure is used by the driver to configure itself.
- * This configuration structure is typically created by the tool-chain based
- * on hardware build properties.
- *
- * The driver instance can be initialized in
- *
- * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a
- * configuration structure provided by the caller. If running in a system
- * with address translation, the provided virtual memory base address
- * replaces the physical address present in the configuration structure.
- *
- * The device supports DMA only as current development plan. No FIFO mode is
- * supported. The driver expects to start the DMA channels and expects that
- * the user has set up the buffer descriptor lists.
- *
- * Interrupts and Asynchronous Callbacks
- *
- * The driver has no dependencies on the interrupt controller. When an
- * interrupt occurs, the handler will perform a small amount of
- * housekeeping work, determine the source of the interrupt, and call the
- * appropriate callback function. All callbacks are registered by the user
- * level application.
- *
- * Virtual Memory
- *
- * All virtual to physical memory mappings must occur prior to accessing the
- * driver API.
- *
- * For DMA transactions, user buffers supplied to the driver must be in terms
- * of their physical address.
- *
- * DMA
- *
- * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
- * These BDs are typically chained together into a list the hardware follows
- * when transferring data in and out of the packet buffers. Each BD describes
- * a memory region containing either a full or partial Ethernet packet.
- *
- * Interrupt coalescing is not supported from this built-in DMA engine.
- *
- * This API requires the user to understand how the DMA operates. The
- * following paragraphs provide some explanation, but the user is encouraged
- * to read documentation in xemacps_bdring.h as well as study example code
- * that accompanies this driver.
- *
- * The API is designed to get BDs to and from the DMA engine in the most
- * efficient means possible. The first step is to establish a memory region
- * to contain all BDs for a specific channel. This is done with
- * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
- * follow as BDs are processed. The ring will consist of a user defined number
- * of BDs which will all be partially initialized. For example on the transmit
- * channel, the driver will initialize all BDs' so that they are configured
- * for transmit. The more fields that can be permanently setup at
- * initialization, then the fewer accesses will be needed to each BD while
- * the DMA engine is in operation resulting in better throughput and CPU
- * utilization. The best case initialization would require the user to set
- * only a frame buffer address and length prior to submitting the BD to the
- * engine.
- *
- * BDs move through the engine with the help of functions
- * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
- * and XEmacPs_BdRingFree().
- * All these functions handle BDs that are in place. That is, there are no
- * copies of BDs kept anywhere and any BD the user interacts with is an actual
- * BD from the same ring hardware accesses.
- *
- * BDs in the ring go through a series of states as follows:
- * 1. Idle. The driver controls BDs in this state.
- * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
- * reserve BD(s). Once allocated, the user may setup the BD(s) with
- * frame buffer address, length, and other attributes. The user controls
- * BDs in this state.
- * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
- * in this state are either waiting to be processed by hardware, are in
- * process, or have been processed. The DMA engine controls BDs in this
- * state.
- * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
- * user. Once retrieved, the user can examine each BD for the outcome of
- * the DMA transfer. The user controls BDs in this state. After examining
- * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
- * into state 1.
- *
- * Each of the four BD accessor functions operate on a set of BDs. A set is
- * defined as a segment of the BD ring consisting of one or more BDs. The user
- * views the set as a pointer to the first BD along with the number of BDs for
- * that set. The set can be navigated by using macros XEmacPs_BdNext(). The
- * user must exercise extreme caution when changing BDs in a set as there is
- * nothing to prevent doing a mBdNext past the end of the set and modifying a
- * BD out of bounds.
- *
- * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
- * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
- * tandem. The same BD set retrieved with BdRingAlloc should be the same one
- * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
- * BdRIngFree.
- *
- * Alignment & Data Cache Restrictions
- *
- * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
- * aligned. Please reference xemacps_bd.h for cache related macros.
- *
- * DMA Tx:
- *
- * - If frame buffers exist in cached memory, then they must be flushed
- * prior to committing them to hardware.
- *
- * DMA Rx:
- *
- * - If frame buffers exist in cached memory, then the cache must be
- * invalidated for the memory region containing the frame prior to data
- * access
- *
- * Both cache invalidate/flush are taken care of in driver code.
- *
- * Buffer Copying
- *
- * The driver is designed for a zero-copy buffer scheme. That is, the driver
- * will not copy buffers. This avoids potential throughput bottlenecks within
- * the driver. If byte copying is required, then the transfer will take longer
- * to complete.
- *
- * Checksum Offloading
- *
- * The Embedded Processor Block Ethernet can be configured to perform IP, TCP
- * and UDP checksum offloading in both receive and transmit directions.
- *
- * IP packets contain a 16-bit checksum field, which is the 16-bit 1s
- * complement of the 1s complement sum of all 16-bit words in the header.
- * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
- * 1s complement of the 1s complement sum of all 16-bit words in the header,
- * the data and a conceptual pseudo header.
- *
- * To calculate these checksums in software requires each byte of the packet
- * to be read. For TCP and UDP this can use a large amount of processing power.
- * Offloading the checksum calculation to hardware can result in significant
- * performance improvements.
- *
- * The transmit checksum offload is only available to use DMA in packet buffer
- * mode. This is because the complete frame to be transmitted must be read
- * into the packet buffer memory before the checksum can be calculated and
- * written to the header at the beginning of the frame.
- *
- * For IP, TCP or UDP receive checksum offload to be useful, the operating
- * system containing the protocol stack must be aware that this offload is
- * available so that it can make use of the fact that the hardware has verified
- * the checksum.
- *
- * When receive checksum offloading is enabled in the hardware, the IP header
- * checksum is checked, where the packet meets the following criteria:
- *
- * 1. If present, the VLAN header must be four octets long and the CFI bit
- * must not be set.
- * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
- * encoding.
- * 3. IP v4 packet.
- * 4. IP header is of a valid length.
- * 5. Good IP header checksum.
- * 6. No IP fragmentation.
- * 7. TCP or UDP packet.
- *
- * When an IP, TCP or UDP frame is received, the receive buffer descriptor
- * gives an indication if the hardware was able to verify the checksums.
- * There is also an indication if the frame had SNAP encapsulation. These
- * indication bits will replace the type ID match indication bits when the
- * receive checksum offload is enabled.
- *
- * If any of the checksums are verified incorrect by the hardware, the packet
- * is discarded and the appropriate statistics counter incremented.
- *
- * PHY Interfaces
- *
- * RGMII 1.3 is the only interface supported.
- *
- * Asserts
- *
- * Asserts are used within all Xilinx drivers to enforce constraints on
- * parameters. Asserts can be turned off on a system-wide basis by defining,
- * at compile time, the NDEBUG identifier. By default, asserts are turned on
- * and it is recommended that users leave asserts on during development. For
- * deployment use -DNDEBUG compiler switch to remove assert code.
- *
- * @note
- *
- * Xilinx drivers are typically composed of two parts, one is the driver
- * and the other is the adapter. The driver is independent of OS and processor
- * and is intended to be highly portable. The adapter is OS-specific and
- * facilitates communication between the driver and an OS.
- * This driver is intended to be RTOS and processor independent. Any needs for
- * dynamic memory management, threads or thread mutual exclusion, or cache
- * control must be satisfied bythe layer above this driver.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -------------------------------------------------------
- * 1.00a wsy 01/10/10 First release
- * 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file
- * xemacps_bdring.c is modified. Earlier it was checking for
- * "BdLimit"(passed argument) number of BDs for finding out
- * which BDs are successfully processed. Now one more check
- * is added. It looks for BDs till the current BD pointer
- * reaches HwTail. By doing this processing time is saved.
- * 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
- * xemacps_bdring.c is modified. Now start of packet is
- * searched for returning the number of BDs processed.
- * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
- * registers. Added a new API to set the bust length.
- * Added some new hash-defines.
- * 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for
- * Rx errors. Under heavy Rx traffic, there will be a large
- * number of errors related to receive buffer not available.
- * Because of a HW bug (SI #692601), under such heavy errors,
- * the Rx data path can become unresponsive. To reduce the
- * probabilities for hitting this HW bug, the SW writes to
- * bit 18 to flush a packet from Rx DPRAM immediately. The
- * changes for it are done in the function
- * XEmacPs_IntrHandler.
- * 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
- * removed. It is expected that all BDs are allocated in
- * from uncached area.
- * 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
- * to 0x1fff. This fixes the CR#744902.
- * Made changes in example file xemacps_example.h to fix compilation
- * issues with iarcc compiler.
- * 2.0 adk 10/12/13 Updated as per the New Tcl API's
- * 2.1 adk 11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
- * 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy
- * address in xparameters.h when GMII to RGMII converter
- * is present in hw.
- * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
- * changes.
- * 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
- * 1000BASE-X mode export proper values to the xparameters.h
- * file. Changes are made in the driver tcl file.
- * 3.0 adk 08/1/15 Don't include gem in peripheral test when gem is
- * configured with PCS/PMA Core. Changes are made in the
- * test app tcl(CR:827686).
- * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
- * 3.0 hk 03/18/15 Added support for jumbo frames. Increase AHB burst.
- * Disable extended mode. Perform all 64 bit changes under
- * check for arch64.
- * Remove "used bit set" from TX error interrupt masks.
- * 3.1 hk 07/27/15 Do not call error handler with '0' error code when
- * there is no error. CR# 869403
- * 08/10/15 Update upper 32 bit tx and rx queue ptr registers.
- * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
- * 3.4 ms 01/23/17 Modified xil_printf statement in main function for all
- * examples to ensure that "Successfully ran" and "Failed"
- * strings are available in all examples. This is a fix
- * for CR-965028.
- * ms 03/17/17 Modified text file in examples folder for doxygen
- * generation.
- * ms 04/05/17 Added tabspace for return statements in functions of
- * xemacps_ieee1588_example.c for proper documentation
- * while generating doxygen.
- * 3.5 hk 08/14/17 Update cache coherency information of the interface in
- * its config structure.
- * 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
- * changed to volatile.
- * Add API XEmacPs_BdRingPtrReset() to reset pointers
- * 3.8 hk 07/19/18 Fixed CPP, GCC and doxygen warnings - CR-1006327
- * hk 09/17/18 Fix PTP interrupt masks and cleanup comments.
- * 3.9 hk 01/23/19 Add RX watermark support
- * 3.11 sd 02/14/20 Add clock support
- * 3.13 nsk 12/14/20 Updated the tcl to not to use the instance names.
- *
- *
- *
- ****************************************************************************/
-
-#ifndef XEMACPS_H /* prevent circular inclusions */
-#define XEMACPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xemacps_hw.h"
-#include "xemacps_bd.h"
-#include "xemacps_bdring.h"
-#if defined (XCLOCKING)
-#include "xil_clocking.h"
-#endif
-
-/************************** Constant Definitions ****************************/
-
-/*
- * Device information
- */
-#define XEMACPS_DEVICE_NAME "xemacps"
-#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC"
-
-
-/** @name Configuration options
- *
- * Device configuration options. See the XEmacPs_SetOptions(),
- * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
- * use options.
- *
- * The default state of the options are noted and are what the device and
- * driver will be set to after calling XEmacPs_Reset() or
- * XEmacPs_Initialize().
- *
- * @{
- */
-
-#define XEMACPS_PROMISC_OPTION 0x00000001U
-/**< Accept all incoming packets.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_FRAME1536_OPTION 0x00000002U
-/**< Frame larger than 1516 support for Tx & Rx.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_VLAN_OPTION 0x00000004U
-/**< VLAN Rx & Tx frame support.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U
-/**< Enable recognition of flow control frames on Rx
- * This option defaults to enabled (set) */
-
-#define XEMACPS_FCS_STRIP_OPTION 0x00000020U
-/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
- * stripped.
- * This option defaults to enabled (set) */
-
-#define XEMACPS_FCS_INSERT_OPTION 0x00000040U
-/**< Generate FCS field and add PAD automatically for outgoing frames.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U
-/**< Enable Length/Type error checking for incoming frames. When this option is
- * set, the MAC will filter frames that have a mismatched type/length field
- * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
- * types of frames are encountered. When this option is cleared, the MAC will
- * allow these types of frames to be received.
- *
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U
-/**< Enable the transmitter.
- * This option defaults to enabled (set) */
-
-#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U
-/**< Enable the receiver
- * This option defaults to enabled (set) */
-
-#define XEMACPS_BROADCAST_OPTION 0x00000400U
-/**< Allow reception of the broadcast address
- * This option defaults to enabled (set) */
-
-#define XEMACPS_MULTICAST_OPTION 0x00000800U
-/**< Allows reception of multicast addresses programmed into hash
- * This option defaults to disabled (clear) */
-
-#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U
-/**< Enable the RX checksum offload
- * This option defaults to enabled (set) */
-
-#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U
-/**< Enable the TX checksum offload
- * This option defaults to enabled (set) */
-
-#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U
-#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U
-
-#define XEMACPS_DEFAULT_OPTIONS \
- ((u32)XEMACPS_FLOW_CONTROL_OPTION | \
- (u32)XEMACPS_FCS_INSERT_OPTION | \
- (u32)XEMACPS_FCS_STRIP_OPTION | \
- (u32)XEMACPS_BROADCAST_OPTION | \
- (u32)XEMACPS_LENTYPE_ERR_OPTION | \
- (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
- (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
- (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
- (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
-
-/**< Default options set when device is initialized or reset */
-/*@}*/
-
-/** @name Callback identifiers
- *
- * These constants are used as parameters to XEmacPs_SetHandler()
- * @{
- */
-#define XEMACPS_HANDLER_DMASEND 1U
-#define XEMACPS_HANDLER_DMARECV 2U
-#define XEMACPS_HANDLER_ERROR 3U
-/*@}*/
-
-/* Constants to determine the configuration of the hardware device. They are
- * used to allow the driver to verify it can operate with the hardware.
- */
-#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */
-
-/* The next few constants help upper layers determine the size of memory
- * pools used for Ethernet buffers and descriptor lists.
- */
-#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */
-
-#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */
-#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */
-#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */
-#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
-#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
-#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
- XEMACPS_TRL_SIZE)
-#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
- XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
-#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
- XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
-
-/* DMACR Bust length hash defines */
-
-#define XEMACPS_SINGLE_BURST 0x00000001
-#define XEMACPS_4BYTE_BURST 0x00000004
-#define XEMACPS_8BYTE_BURST 0x00000008
-#define XEMACPS_16BYTE_BURST 0x00000010
-
-
-/**************************** Type Definitions ******************************/
-/** @name Typedefs for callback functions
- *
- * These callbacks are invoked in interrupt context.
- * @{
- */
-/**
- * Callback invoked when frame(s) have been sent or received in interrupt
- * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
- *
- * @param CallBackRef is user data assigned when the callback was set.
- *
- * @note
- * See xemacps_hw.h for bitmasks definitions and the device hardware spec for
- * further information on their meaning.
- *
- */
-typedef void (*XEmacPs_Handler) (void *CallBackRef);
-
-/**
- * Callback when an asynchronous error occurs. To set this callback, invoke
- * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
- * parameter.
- *
- * @param CallBackRef is user data assigned when the callback was set.
- * @param Direction defines either receive or transmit error(s) has occurred.
- * @param ErrorWord definition varies with Direction
- *
- */
-typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
- u32 ErrorWord);
-
-/*@}*/
-
-/**
- * This typedef contains configuration information for a device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
- u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
- * describes whether Cache Coherent or not */
-#if defined (XCLOCKING)
- u32 RefClk; /**< Input clock */
-#endif
- u16 S1GDiv0; /**< 1Gbps Clock Divider 0 */
- u8 S1GDiv1; /**< 1Gbps Clock Divider 1 */
- u16 S100MDiv0; /**< 100Mbps Clock Divider 0 */
- u8 S100MDiv1; /**< 100Mbps Clock Divider 1 */
- u16 S10MDiv0; /**< 10Mbps Clock Divider 0 */
- u8 S10MDiv1; /**< 10Mbps Clock Divider 1 */
-} XEmacPs_Config;
-
-
-/**
- * The XEmacPs driver instance data. The user is required to allocate a
- * structure of this type for every XEmacPs device in the system. A pointer
- * to a structure of this type is then passed to the driver API functions.
- */
-typedef struct XEmacPs_Instance {
- XEmacPs_Config Config; /* Hardware configuration */
- u32 IsStarted; /* Device is currently started */
- u32 IsReady; /* Device is initialized and ready */
- u32 Options; /* Current options word */
-
- XEmacPs_BdRing TxBdRing; /* Transmit BD ring */
- XEmacPs_BdRing RxBdRing; /* Receive BD ring */
-
- XEmacPs_Handler SendHandler;
- XEmacPs_Handler RecvHandler;
- void *SendRef;
- void *RecvRef;
-
- XEmacPs_ErrHandler ErrorHandler;
- void *ErrorRef;
- u32 Version;
- u32 RxBufMask;
- u32 MaxMtuSize;
- u32 MaxFrameSize;
- u32 MaxVlanFrameSize;
-
-} XEmacPs;
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* Retrieve the Tx ring object. This object can be used in the various Ring
-* API functions.
-*
-* @param InstancePtr is the DMA channel to operate on.
-*
-* @return TxBdRing attribute
-*
-* @note
-* C-style signature:
-* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
-
-/****************************************************************************/
-/**
-* Retrieve the Rx ring object. This object can be used in the various Ring
-* API functions.
-*
-* @param InstancePtr is the DMA channel to operate on.
-*
-* @return RxBdRing attribute
-*
-* @note
-* C-style signature:
-* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
-
-/****************************************************************************/
-/**
-*
-* Enable interrupts specified in Mask. The corresponding interrupt for
-* each bit set to 1 in Mask, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to enable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntEnable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_IER_OFFSET, \
- ((Mask) & XEMACPS_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Disable interrupts specified in Mask. The corresponding interrupt for
-* each bit set to 1 in Mask, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to disable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntDisable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_IDR_OFFSET, \
- ((Mask) & XEMACPS_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Enable interrupts specified in Mask. The corresponding interrupt for
-* each bit set to 1 in Mask, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to enable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_INTQ1_IER_OFFSET, \
- ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Disable interrupts specified in Mask. The corresponding interrupt for
-* each bit set to 1 in Mask, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to disable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_INTQ1_IDR_OFFSET, \
- ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* This macro triggers trasmit circuit to send data currently in TX buffer(s).
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return
-*
-* @note
-*
-* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_Transmit(InstancePtr) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_NWCTRL_OFFSET, \
- (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
-
-/****************************************************************************/
-/**
-*
-* This macro determines if the device is configured with checksum offloading
-* on the receive channel
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return
-*
-* Boolean TRUE if the device is configured with checksum offloading, or
-* FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_IsRxCsum(InstancePtr) \
- ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
- ? TRUE : FALSE)
-
-/****************************************************************************/
-/**
-*
-* This macro determines if the device is configured with checksum offloading
-* on the transmit channel
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return
-*
-* Boolean TRUE if the device is configured with checksum offloading, or
-* FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_IsTxCsum(InstancePtr) \
- ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
- ? TRUE : FALSE)
-
-/************************** Function Prototypes *****************************/
-
-/****************************************************************************/
-/**
-*
-* This macro sets RX watermark register.
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-* @param High is the non-zero RX high watermark value. When SRAM fill level
-* is above this, a pause frame will be sent.
-* @param Low is the non-zero RX low watermark value. When SRAM fill level
-* is below this, a zero length pause frame will be sent IF the last
-* pause frame sent was non-zero.
-*
-* @return None
-*
-* @note
-*
-* Signature: void XEmacPs_SetRXWatermark(XEmacPs *InstancePtr, u16 High,
-* u16 Low)
-*
-*****************************************************************************/
-#define XEmacPs_SetRXWatermark(InstancePtr, High, Low) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_RXWATERMARK_OFFSET, \
- (High & XEMACPS_RXWM_HIGH_MASK) | \
- ((Low << XEMACPS_RXWM_LOW_SHFT_MSK) & XEMACPS_RXWM_LOW_MASK) |)
-
-/****************************************************************************/
-/**
-*
-* This macro gets RX watermark register.
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return RX watermark register value
-*
-* @note
-*
-* Signature: void XEmacPs_GetRXWatermark(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_GetRXWatermark(InstancePtr) \
- XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_RXWATERMARK_OFFSET)
-/*
- * Initialization functions in xemacps.c
- */
-LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
- UINTPTR EffectiveAddress);
-void XEmacPs_Start(XEmacPs *InstancePtr);
-void XEmacPs_Stop(XEmacPs *InstancePtr);
-void XEmacPs_Reset(XEmacPs *InstancePtr);
-void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
- u16 Direction);
-
-/*
- * Lookup configuration in xemacps_sinit.c
- */
-XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
-
-/*
- * Interrupt-related functions in xemacps_intr.c
- * DMA only and FIFO is not supported. This DMA does not support coalescing.
- */
-LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
- void *FuncPointer, void *CallBackRef);
-void XEmacPs_IntrHandler(void *XEmacPsPtr);
-
-/*
- * MAC configuration/control functions in XEmacPs_control.c
- */
-LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
-LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
-u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
-
-LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
-LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
-void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
-
-LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
-void XEmacPs_ClearHash(XEmacPs *InstancePtr);
-void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
-
-void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
- XEmacPs_MdcDiv Divisor);
-void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
-u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
-LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
- u32 RegisterNum, u16 *PhyDataPtr);
-LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
- u32 RegisterNum, u16 PhyData);
-LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
-
-LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
-void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2d/712b51575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2d/712b51575243001d18b399c1eb9b3628
deleted file mode 100644
index 4492ae0..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2d/712b51575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,54 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file rsa.h
-*
-* This file contains the RSA algorithm functions
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 4.00a sg 02/28/13 Initial release
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 3.00a mb 01/09/12 Initial release
-*
-*
-*
-* @note
-*
-******************************************************************************/
-
-#ifndef _FSBL_DEBUG_H
-#define _FSBL_DEBUG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-#define DEBUG_GENERAL 0x00000001 /* general debug messages */
-#define DEBUG_INFO 0x00000002 /* More debug information */
-
-#if defined (FSBL_DEBUG_INFO)
-#define fsbl_dbg_current_types ((DEBUG_INFO) | (DEBUG_GENERAL))
-#elif defined (FSBL_DEBUG)
-#define fsbl_dbg_current_types (DEBUG_GENERAL)
-#else
-#define fsbl_dbg_current_types 0
-#endif
-
-#ifdef STDOUT_BASEADDRESS
-#define fsbl_printf(type,...) \
- if (((type) & fsbl_dbg_current_types)) {xil_printf (__VA_ARGS__); }
-#else
-#define fsbl_printf(type, ...)
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _FSBL_DEBUG_H */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2d/e0665d545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2d/e0665d545243001d18b399c1eb9b3628
deleted file mode 100644
index a270af6..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2d/e0665d545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,691 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xscugic_hw.h
-* @addtogroup scugic_v4_6
-* @{
-*
-* This header file contains identifiers and HW access functions (or
-* macros) that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-* The driver functions/APIs are defined in xscugic.h.
-*
-* This GIC device has two parts, a distributor and CPU interface(s). Each part
-* has separate register definition sections.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------------
-* 1.00a drg 01/19/10 First release
-* 1.01a sdm 11/09/11 "xil_exception.h" added as include.
-* Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
-* added to enable or disable interrupts based on
-* Distributor Register base address. Normally users use
-* XScuGic instance and call XScuGic_Enable or
-* XScuGic_Disable to enable/disable interrupts. These
-* new macros are provided when user does not want to
-* use an instance pointer but still wants to enable or
-* disable interrupts.
-* Function prototypes for functions (present in newly
-* added file xscugic_hw.c) are added.
-* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
-* 702687).
-* 1.04a hk 05/04/13 Fix for CR#705621. Moved function prototypes
-* XScuGic_SetPriTrigTypeByDistAddr and
-* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
-* 3.0 pkp 12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
-* Zynq Ultrascale Mp
-* 3.0 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
-* 3.2 pkp 11/09/15 Corrected the interrupt processsor target mask value
-* for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
-* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
-* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
-* API's can be used by applications to unmap specific/all
-* interrupts from target CPU. It fixes CR#992490.
-* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
-* 4.1 asa 03/30/19 Removed macros for XScuGic_EnableIntr, and
-* XScuGic_DisableIntr. These are now C functions. This
-* change was to fix CR-1024716.
-* 4.1 mus 06/12/19 Updated XSCUGIC_MAX_NUM_INTR_INPUTS for Versal.
-* 4.6 sk 06/07/21 Delete the commented macro code to fix the MISRA-C warning.
-* 4.6 sk 08/05/21 Fix Scugic Misrac violations.
-*
-*
-*
-******************************************************************************/
-
-#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
-#define XSCUGIC_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xil_exception.h"
-#include "bspconfig.h"
-
-/************************** Constant Definitions *****************************/
-#if defined (versal) && !defined(ARMR5)
-#define GICv3
-#endif
-
-/*
- * The maximum number of interrupts supported by the hardware.
- */
-#ifdef PLATFORM_ZYNQ
-#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */
-#elif defined (versal)
-#define XSCUGIC_MAX_NUM_INTR_INPUTS 192U
-#else
-#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
-#endif
-
-/*
- * First Interrupt Id for SPI interrupts.
- */
-#define XSCUGIC_SPI_INT_ID_START 0x20
-/*
- * The maximum priority value that can be used in the GIC.
- */
-#define XSCUGIC_MAX_INTR_PRIO_VAL 248U
-#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U
-
-/** @name Distributor Interface Register Map
- *
- * Define the offsets from the base address for all Distributor registers of
- * the interrupt controller, some registers may be reserved in the hardware
- * device.
- * @{
- */
-#define XSCUGIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable
- Register */
-#define XSCUGIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller
- Type Register */
-#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID
- Register */
-#define XSCUGIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security
- Register */
-#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set
- Register */
-#define XSCUGIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */
-#define XSCUGIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set
- Register */
-#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear
- Register */
-#define XSCUGIC_ACTIVE_OFFSET 0x00000300U /**< Active Status Register */
-#define XSCUGIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */
-#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target
- Register 0x800-0x8FB */
-#define XSCUGIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration
- Register 0xC00-0xCFC */
-#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */
-#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register
- 0xd04-0xd7C */
-#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration
- Register */
-#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered
- Interrupt Register */
-#define XSCUGIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */
-#if defined (GICv3)
-#define XSCUGIC_PCELLID_OFFSET 0x0000FFF0U /**< Pcell ID Register */
-#else
-#define XSCUGIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */
-#endif
-/* @} */
-
-/** @name Distributor Enable Register
- * Controls if the distributor response to external interrupt inputs.
- * @{
- */
-#if defined (GICv3)
-#define XSCUGIC_EN_INT_MASK 0x00000003U /**< Interrupt In Enable */
-#else
-#define XSCUGIC_EN_INT_MASK 0x00000001U /**< Interrupt In Enable */
-#endif
-/* @} */
-
-/** @name Interrupt Controller Type Register
- * @{
- */
-#define XSCUGIC_LSPI_MASK 0x0000F800U /**< Number of Lockable
- Shared Peripheral
- Interrupts*/
-#define XSCUGIC_DOMAIN_MASK 0x00000400U /**< Number os Security domains*/
-#define XSCUGIC_CPU_NUM_MASK 0x000000E0U /**< Number of CPU Interfaces */
-#define XSCUGIC_NUM_INT_MASK 0x0000001FU /**< Number of Interrupt IDs */
-/* @} */
-
-/** @name Implementor ID Register
- * Implementor and revision information.
- * @{
- */
-#define XSCUGIC_REV_MASK 0x00FFF000U /**< Revision Number */
-#define XSCUGIC_IMPL_MASK 0x00000FFFU /**< Implementor */
-/* @} */
-
-/** @name Interrupt Security Registers
- * Each bit controls the security level of an interrupt, either secure or non
- * secure. These registers can only be accessed using secure read and write.
- * There are registers for each of the CPU interfaces at offset 0x080. A
- * register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x084.
- * @{
- */
-#define XSCUGIC_INT_NS_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Enable Set Register
- * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
- * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
- * bit to 0.
- * There are registers for each of the CPU interfaces at offset 0x100. With up
- * to 8 registers aliased to the same address. A register set for the SPI
- * interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x104.
- * @{
- */
-#define XSCUGIC_INT_EN_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Enable Clear Register
- * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
- * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
- * sets the corresponding bit to 0.
- * There are registers for each of the CPU interfaces at offset 0x180. With up
- * to 8 registers aliased to the same address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x184.
- * @{
- */
-#define XSCUGIC_INT_CLR_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Pending Set Register
- * Each bit controls the Pending or Active and Pending state of an interrupt, a
- * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
- * an interrupt to the pending state.
- * There are registers for each of the CPU interfaces at offset 0x200. With up
- * to 8 registers aliased to the same address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x204.
- * @{
- */
-#define XSCUGIC_PEND_SET_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Pending Clear Register
- * Each bit can clear the Pending or Active and Pending state of an interrupt, a
- * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
- * clears the pending state of an interrupt.
- * There are registers for each of the CPU interfaces at offset 0x280. With up
- * to 8 registers aliased to the same address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x284.
- * @{
- */
-#define XSCUGIC_PEND_CLR_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Active Status Register
- * Each bit provides the Active status of an interrupt, a
- * 0 is not Active, a 1 is Active. This is a read only register.
- * There are registers for each of the CPU interfaces at offset 0x300. With up
- * to 8 registers aliased to each address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x380.
- * @{
- */
-#define XSCUGIC_ACTIVE_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Priority Level Register
- * Each byte in a Priority Level Register sets the priority level of an
- * interrupt. Reading the register provides the priority level of an interrupt.
- * There are registers for each of the CPU interfaces at offset 0x400 through
- * 0x41C. With up to 8 registers aliased to each address.
- * 0 is highest priority, 0xFF is lowest.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 255 of these registers staring at location 0x420.
- * @{
- */
-#define XSCUGIC_PRIORITY_MASK 0x000000FFU /**< Each Byte corresponds to an
- INT_ID */
-#define XSCUGIC_PRIORITY_MAX 0x000000FFU /**< Highest value of a priority
- actually the lowest priority*/
-/* @} */
-
-/** @name SPI Target Register 0x800-0x8FB
- * Each byte references a separate SPI and programs which of the up to 8 CPU
- * interfaces are sent a Pending interrupt.
- * There are registers for each of the CPU interfaces at offset 0x800 through
- * 0x81C. With up to 8 registers aliased to each address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 255 of these registers staring at location 0x820.
- *
- * This driver does not support multiple CPU interfaces. These are included
- * for complete documentation.
- * @{
- */
-#define XSCUGIC_SPI_CPU7_MASK 0x00000080U /**< CPU 7 Mask*/
-#define XSCUGIC_SPI_CPU6_MASK 0x00000040U /**< CPU 6 Mask*/
-#define XSCUGIC_SPI_CPU5_MASK 0x00000020U /**< CPU 5 Mask*/
-#define XSCUGIC_SPI_CPU4_MASK 0x00000010U /**< CPU 4 Mask*/
-#define XSCUGIC_SPI_CPU3_MASK 0x00000008U /**< CPU 3 Mask*/
-#define XSCUGIC_SPI_CPU2_MASK 0x00000004U /**< CPU 2 Mask*/
-#define XSCUGIC_SPI_CPU1_MASK 0x00000002U /**< CPU 1 Mask*/
-#define XSCUGIC_SPI_CPU0_MASK 0x00000001U /**< CPU 0 Mask*/
-/* @} */
-
-/** @name Interrupt Configuration Register 0xC00-0xCFC
- * The interrupt configuration registers program an SFI to be active HIGH level
- * sensitive or rising edge sensitive.
- * Each bit pair describes the configuration for an INT_ID.
- * SFI Read Only b10 always
- * PPI Read Only depending on how the PPIs are configured.
- * b01 Active HIGH level sensitive
- * b11 Rising edge sensitive
- * SPI LSB is read only.
- * b01 Active HIGH level sensitive
- * b11 Rising edge sensitive/
- * There are registers for each of the CPU interfaces at offset 0xC00 through
- * 0xC04. With up to 8 registers aliased to each address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 255 of these registers staring at location 0xC08.
- * @{
- */
-#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */
-/* @} */
-
-/** @name PPI Status Register
- * Enables an external AMBA master to access the status of the PPI inputs.
- * A CPU can only read the status of its local PPI signals and cannot read the
- * status for other CPUs.
- * This register is aliased for each CPU interface.
- * @{
- */
-#define XSCUGIC_PPI_C15_MASK 0x00008000U /**< PPI Status */
-#define XSCUGIC_PPI_C14_MASK 0x00004000U /**< PPI Status */
-#define XSCUGIC_PPI_C13_MASK 0x00002000U /**< PPI Status */
-#define XSCUGIC_PPI_C12_MASK 0x00001000U /**< PPI Status */
-#define XSCUGIC_PPI_C11_MASK 0x00000800U /**< PPI Status */
-#define XSCUGIC_PPI_C10_MASK 0x00000400U /**< PPI Status */
-#define XSCUGIC_PPI_C09_MASK 0x00000200U /**< PPI Status */
-#define XSCUGIC_PPI_C08_MASK 0x00000100U /**< PPI Status */
-#define XSCUGIC_PPI_C07_MASK 0x00000080U /**< PPI Status */
-#define XSCUGIC_PPI_C06_MASK 0x00000040U /**< PPI Status */
-#define XSCUGIC_PPI_C05_MASK 0x00000020U /**< PPI Status */
-#define XSCUGIC_PPI_C04_MASK 0x00000010U /**< PPI Status */
-#define XSCUGIC_PPI_C03_MASK 0x00000008U /**< PPI Status */
-#define XSCUGIC_PPI_C02_MASK 0x00000004U /**< PPI Status */
-#define XSCUGIC_PPI_C01_MASK 0x00000002U /**< PPI Status */
-#define XSCUGIC_PPI_C00_MASK 0x00000001U /**< PPI Status */
-/* @} */
-
-/** @name SPI Status Register 0xd04-0xd7C
- * Enables an external AMBA master to access the status of the SPI inputs.
- * There are up to 63 registers if the maximum number of SPI inputs are
- * configured.
- * @{
- */
-#define XSCUGIC_SPI_N_MASK 0x00000001U /**< Each bit corresponds to an SPI
- input */
-/* @} */
-
-/** @name AHB Configuration Register
- * Provides the status of the CFGBIGEND input signal and allows the endianness
- * of the GIC to be set.
- * @{
- */
-#define XSCUGIC_AHB_END_MASK 0x00000004U /**< 0-GIC uses little Endian,
- 1-GIC uses Big Endian */
-#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002U /**< 0-Uses CFGBIGEND control,
- 1-use the AHB_END bit */
-#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U /**< State of CFGBIGEND */
-
-/* @} */
-
-/** @name Software Triggered Interrupt Register
- * Controls issuing of software interrupts.
- * @{
- */
-#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000U
-#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U /**< Target List filter
- b00-Use the target List
- b01-All CPUs except requester
- b10-To Requester
- b11-reserved */
-#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U /**< CPU Target list */
-#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U /**< 0= Use a secure interrupt */
-#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU /**< Set to the INTID
- signaled to the CPU*/
-/* @} */
-
-/** @name CPU Interface Register Map
- *
- * Define the offsets from the base address for all CPU registers of the
- * interrupt controller, some registers may be reserved in the hardware device.
- * @{
- */
-#define XSCUGIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control
- Register */
-#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */
-#define XSCUGIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */
-#define XSCUGIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */
-#define XSCUGIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */
-#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */
-#define XSCUGIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt
- Register */
-#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure
- Binary Point Register */
-
-/**< 0x00000020 to 0x00000FBC are reserved and should not be read or written
- * to. */
-/* @} */
-
-
-/** @name Control Register
- * CPU Interface Control register definitions
- * All bits are defined here although some are not available in the non-secure
- * mode.
- * @{
- */
-#define XSCUGIC_CNTR_SBPR_MASK 0x00000010U /**< Secure Binary Pointer,
- 0=separate registers,
- 1=both use bin_pt_s */
-#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008U /**< Use nFIQ_C for secure
- interrupts,
- 0= use IRQ for both,
- 1=Use FIQ for secure, IRQ for non*/
-#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U /**< Ack control for secure or non secure */
-#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002U /**< Non Secure enable */
-#define XSCUGIC_CNTR_EN_S_MASK 0x00000001U /**< Secure enable, 0=Disabled, 1=Enabled */
-/* @} */
-
-
-/** @name Binary Point Register
- * Binary Point register definitions
- * @{
- */
-
-#define XSCUGIC_BIN_PT_MASK 0x00000007U /**< Binary point mask value
- Value Secure Non-secure
- b000 0xFE 0xFF
- b001 0xFC 0xFE
- b010 0xF8 0xFC
- b011 0xF0 0xF8
- b100 0xE0 0xF0
- b101 0xC0 0xE0
- b110 0x80 0xC0
- b111 0x00 0x80
- */
-/*@}*/
-
-/** @name Interrupt Acknowledge Register
- * Interrupt Acknowledge register definitions
- * Identifies the current Pending interrupt, and the CPU ID for software
- * interrupts.
- */
-#define XSCUGIC_ACK_INTID_MASK 0x000003FFU /**< Interrupt ID */
-#define XSCUGIC_CPUID_MASK 0x00000C00U /**< CPU ID */
-/* @} */
-
-/** @name End of Interrupt Register
- * End of Interrupt register definitions
- * Allows the CPU to signal the GIC when it completes an interrupt service
- * routine.
- */
-#define XSCUGIC_EOI_INTID_MASK 0x000003FFU /**< Interrupt ID */
-
-/* @} */
-
-/** @name Running Priority Register
- * Running Priority register definitions
- * Identifies the interrupt priority level of the highest priority active
- * interrupt.
- */
-#define XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU /**< Interrupt Priority */
-/* @} */
-
-#if defined (GICv3)
-#define XSCUGIC_IROUTER_BASE_OFFSET 0x6000U
-#endif
-/*
- * Highest Pending Interrupt register definitions
- * Identifies the interrupt priority of the highest priority pending interrupt
- */
-#define XSCUGIC_PEND_INTID_MASK 0x000003FFU /**< Pending Interrupt ID */
-/* @} */
-#if defined (GICv3)
-/** @name ReDistributor Interface Register Map
- *
- * @{
- */
-#define XSCUGIC_RDIST_OFFSET 0x80000U
-#define XSCUGIC_RDIST_BASE_ADDRESS (XPAR_SCUGIC_0_DIST_BASEADDR + XSCUGIC_RDIST_OFFSET)
-#define XSCUGIC_RDIST_SGI_PPI_OFFSET 0x90000U
-#define XSCUGIC_RDIST_SGI_PPI_BASE_ADDRESS (XPAR_SCUGIC_0_DIST_BASEADDR + XSCUGIC_RDIST_SGI_PPI_OFFSET)
-#define XSCUGIC_RDIST_ISENABLE_OFFSET 0x100U
-#define XSCUGIC_RDIST_IPRIORITYR_OFFSET 0x400U
-#define XSCUGIC_RDIST_IGROUPR_OFFSET 0x80U
-#define XSCUGIC_RDIST_GRPMODR_OFFSET 0xD00U
-#define XSCUGIC_RDIST_INT_CONFIG_OFFSET 0xC00U
-#define XSCUGIC_RDIST_WAKER_OFFSET 0x14U
-#define XSCUGIC_SGIR_EL1_INITID_SHIFT 24U
-
-/*
- * GICR_IGROUPR register definitions
- */
-#if EL3
-#define XSCUGIC_DEFAULT_SECURITY 0x0U
-#else
-#define XSCUGIC_DEFAULT_SECURITY 0xFFFFFFFFU
-#endif
-/*
- * GICR_WAKER register definitions
- */
-#define XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK 0x7
-#endif
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Configuration Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Priority Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Routing Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_IROUTER_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_IROUTER_BASE_OFFSET + (InterruptID * 8))
-
-/****************************************************************************/
-/**
-*
-* Read the SPI Target Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
-/****************************************************************************/
-/**
-*
-* Read the SPI Target Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_SECURITY_TARGET_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_SECURITY_OFFSET + (((InterruptID)/32U)*4U))
-
-/****************************************************************************/
-/**
-*
-* Read the Re-distributor Interrupt configuration register offset
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_RDIST_INT_CONFIG_OFFSET + ((InterruptID /16)*4))
-
-/****************************************************************************/
-/**
-*
-* Read the Re-distributor Interrupt Priority register offset
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_RDIST_IPRIORITYR_OFFSET + (InterruptID * 4))
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Clear-Enable Register offset for an interrupt ID
-*
-* @param Register is the register offset for the clear/enable bank.
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
- ((Register) + (((InterruptID)/32U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the given Intc register.
-*
-* @param BaseAddress is the base address of the device.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_ReadReg(BaseAddress, RegOffset) \
- (Xil_In32((BaseAddress) + (RegOffset)))
-
-
-/****************************************************************************/
-/**
-*
-* Write the given Intc register.
-*
-* @param BaseAddress is the base address of the device.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
- (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
-
-
-/************************** Function Prototypes ******************************/
-
-void XScuGic_DeviceInterruptHandler(void *DeviceId);
-s32 XScuGic_DeviceInitialize(u32 DeviceId);
-void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
- Xil_InterruptHandler IntrHandler, void *CallBackRef);
-void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
- u8 Priority, u8 Trigger);
-void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
- u8 *Priority, u8 *Trigger);
-void XScuGic_InterruptMapFromCpuByDistAddr(u32 DistBaseAddress,
- u8 Cpu_Id, u32 Int_Id);
-void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
- u8 Cpu_Id, u32 Int_Id);
-void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
- u8 Cpu_Id);
-void XScuGic_EnableIntr (u32 DistBaseAddress, u32 Int_Id);
-void XScuGic_DisableIntr (u32 DistBaseAddress, u32 Int_Id);
-/************************** Variable Definitions *****************************/
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2e/d2496d585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2e/d2496d585243001d18b399c1eb9b3628
deleted file mode 100644
index 348ec47..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2e/d2496d585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
-Copyright DornerWorks 2016
-
-Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-following conditions are met:
-1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
-following disclaimer.
-
-THIS SOFTWARE IS PROVIDED BY DORNERWORKS FOR USE ON THE CONTRACTED PROJECT, AND ANY EXPRESS OR IMPLIED WARRANTY
-IS LIMITED TO THIS USE. FOR ALL OTHER USES THIS SOFTWARE IS PROVIDED ''AS IS'' AND ANY EXPRESS OR IMPLIED
-WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL DORNERWORKS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-#ifndef _ARM64_OPS_H_
-#define _ARM64_OPS_H_
-#include
-
-#define BUG() while(1){asm volatile (".word 0xe7f000f0\n");} /* Undefined instruction; will call our fault handler. */
-#define ASSERT(x) \
-do { \
- if (!(x)) { \
- printk("ASSERTION FAILED: %s at %s:%d.\n", \
- # x , \
- __FILE__, \
- __LINE__); \
- BUG(); \
- } \
-} while(0)
-
-#define BUG_ON(x) ASSERT(!(x))
-
-#define smp_processor_id() 0
-
-#define barrier() __asm__ __volatile__("": : :"memory")
-
-// disable interrupts
-static inline void local_irq_disable(void) {
- __asm__ __volatile__("cpsid i":::"memory");
-}
-
-// enable interrupts
-static inline void local_irq_enable(void) {
- __asm__ __volatile__("cpsie i":::"memory");
-}
-
-#define local_irq_save(x) { \
- __asm__ __volatile__("mrs %0, cpsr;cpsid i":"=r"(x)::"memory"); \
-}
-
-#define local_irq_restore(x) { \
- __asm__ __volatile__("msr cpsr_c, %0"::"r"(x):"memory"); \
-}
-
-#define local_save_flags(x) { \
- __asm__ __volatile__("mrs %0, cpsr":"=r"(x)::"memory"); \
-}
-
-static inline int irqs_disabled(void) {
- int x;
- local_save_flags(x);
- return x & 0x80;
-}
-
-#define dsb(scope) asm volatile("dsb " #scope : : : "memory")
-
-/* We probably only need "dmb" here, but we'll start by being paranoid. */
-#define mb() dsb(sy)
-#define rmb() dsb(ld)
-#define wmb() dsb(st)
-
-#define xchg(ptr,v) __atomic_exchange_n(ptr, v, __ATOMIC_SEQ_CST)
-
-/**
- * test_and_clear_bit - Clear a bit and return its old value
- * @nr: Bit to clear
- * @addr: Address to count from
- *
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- *
- * This operation is atomic.
- * If you need a memory barrier, use synch_test_and_clear_bit instead.
- */
-static __inline__ int test_and_clear_bit(int nr, volatile void * addr)
-{
- uint8_t *byte = ((uint8_t *)addr) + (nr >> 3);
- uint8_t bit = 1 << (nr & 7);
- uint8_t orig;
-
- orig = __atomic_fetch_and(byte, ~bit, __ATOMIC_RELAXED);
-
- return (orig & bit) != 0;
-}
-
-/**
- * Atomically set a bit and return the old value.
- * Similar to test_and_clear_bit.
- */
-static __inline__ int test_and_set_bit(int nr, volatile void *base)
-{
- uint8_t *byte = ((uint8_t *)base) + (nr >> 3);
- uint8_t bit = 1 << (nr & 7);
- uint8_t orig;
-
- orig = __atomic_fetch_or(byte, bit, __ATOMIC_RELAXED);
-
- return (orig & bit) != 0;
-}
-
-/**
- * Test whether a bit is set. */
-static __inline__ int test_bit(int nr, const volatile unsigned long *addr)
-{
- const uint8_t *ptr = (const uint8_t *) addr;
- return ((1 << (nr & 7)) & (ptr[nr >> 3])) != 0;
-}
-
-/**
- * Atomically set a bit in memory (like test_and_set_bit but discards result).
- */
-static __inline__ void set_bit(int nr, volatile unsigned long *addr)
-{
- test_and_set_bit(nr, addr);
-}
-
-/**
- * Atomically clear a bit in memory (like test_and_clear_bit but discards result).
- */
-static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
-{
- test_and_clear_bit(nr, addr);
-}
-
-/**
- * __ffs - find first (lowest) set bit in word.
- * @word: The word to search
- *
- * Undefined if no bit exists, so code should check against 0 first.
- */
-static __inline__ unsigned long __ffs(unsigned long word)
-{
- return __builtin_ctzl(word);
-}
-
-
-
-/********************* common arm32 and arm64 ****************************/
-
-/* If *ptr == old, then store new there (and return new).
- * Otherwise, return the old value.
- * Atomic. */
-#define synch_cmpxchg(ptr, old, new) \
-({ __typeof__(*ptr) stored = old; \
- __atomic_compare_exchange_n(ptr, &stored, new, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST) ? new : old; \
-})
-
-/* As test_and_clear_bit, but using __ATOMIC_SEQ_CST */
-static __inline__ int synch_test_and_clear_bit(int nr, volatile void *addr)
-{
- uint8_t *byte = ((uint8_t *)addr) + (nr >> 3);
- uint8_t bit = 1 << (nr & 7);
- uint8_t orig;
-
- orig = __atomic_fetch_and(byte, ~bit, __ATOMIC_SEQ_CST);
-
- return (orig & bit) != 0;
-}
-
-/* As test_and_set_bit, but using __ATOMIC_SEQ_CST */
-static __inline__ int synch_test_and_set_bit(int nr, volatile void *base)
-{
- uint8_t *byte = ((uint8_t *)base) + (nr >> 3);
- uint8_t bit = 1 << (nr & 7);
- uint8_t orig;
-
- orig = __atomic_fetch_or(byte, bit, __ATOMIC_SEQ_CST);
-
- return (orig & bit) != 0;
-}
-
-/* As set_bit, but using __ATOMIC_SEQ_CST */
-static __inline__ void synch_set_bit(int nr, volatile void *addr)
-{
- synch_test_and_set_bit(nr, addr);
-}
-
-/* As clear_bit, but using __ATOMIC_SEQ_CST */
-static __inline__ void synch_clear_bit(int nr, volatile void *addr)
-{
- synch_test_and_clear_bit(nr, addr);
-}
-
-/* As test_bit, but with a following memory barrier. */
-static __inline__ int synch_test_bit(int nr, volatile void *addr)
-{
- int result;
- result = test_bit(nr, addr);
- barrier();
- return result;
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2e/f0cba6545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2e/f0cba6545243001d18b399c1eb9b3628
deleted file mode 100644
index e93e4d4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2e/f0cba6545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,71 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xemacps_sinit.c
-* @addtogroup emacps_v3_15
-* @{
-*
-* This file contains lookup method by device ID when success, it returns
-* pointer to config table to be used to initialize the device.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 New
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xemacps.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-/*************************** Variable Definitions *****************************/
-extern XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES];
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-* Lookup the device configuration based on the unique device ID. The table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId is the unique device ID of the device being looked up.
-*
-* @return
-* A pointer to the configuration table entry corresponding to the given
-* device ID, or NULL if no match is found.
-*
-******************************************************************************/
-XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
-{
- XEmacPs_Config *CfgPtr = NULL;
- u32 i;
-
- for (i = 0U; i < (u32)XPAR_XEMACPS_NUM_INSTANCES; i++) {
- if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) {
- CfgPtr = &XEmacPs_ConfigTable[i];
- break;
- }
- }
-
- return (XEmacPs_Config *)(CfgPtr);
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2f/419b0a595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2f/419b0a595243001d18b399c1eb9b3628
deleted file mode 100644
index bb52012..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2f/419b0a595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,59 +0,0 @@
-###############################################################################
-# Copyright (c) 2011 - 2020 Xilinx, Inc. All rights reserved.
-# SPDX-License-Identifier: MIT
-###############################################################################
-DRIVER_LIB_VERSION = v1.0
-
-include config.make
-
-AS=$(ASSEMBLER)
-COMPILER=$(COMPILER)
-ARCHIVER=$(ARCHIVER)
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-INCLUDEFILES=*.h
-
-SRCFILES:=$(wildcard *.c)
-
-ASSEMBLY_SRCFILES:=$(wildcard *.s)
-
-OBJECTS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(wildcard *.c))))
-ASSEMBLY_OBJECTS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(wildcard *.s))))
-
-
-libs: $(LIBS)
-standalone_libs: ${OBJECTS} ${ASSEMBLY_OBJECTS}
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.s
- ${AS} --cpu Cortex-R5 --fpu VFPv3_D16 $(INCLUDES) -o $@ $<
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $<
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf ${ASSEMBLY_OBJECTS}
- rm -rf $(DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2f/601bd3595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2f/601bd3595243001d18b399c1eb9b3628
deleted file mode 100644
index 5c01051..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2f/601bd3595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1132 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
- *
- * @file xusbps.h
-* @addtogroup usbps_v2_7
-* @{
-* @details
- *
- * This file contains the implementation of the XUsbPs driver. It is the
- * driver for an USB controller in DEVICE or HOST mode.
- *
- *
Introduction
- *
- * The Spartan-3AF Embedded Peripheral Block contains a USB controller for
- * communication with serial peripherals or hosts. The USB controller supports
- * Host, Device and On the Go (OTG) applications.
- *
- *
USB Controller Features
- *
- * - Supports Low Speed USB 1.1 (1.5Mbps), Full Speed USB 1.1 (12Mbps), and
- * High Speed USB 2.0 (480Mbps) data speeds
- * - Supports Device, Host and OTG operational modes
- * - ULPI transceiver interface for USB 2.0 operation
- * - Integrated USB Full and Low speed serial transceiver interfaces for lowest
- * cost connections
- *
- *
Initialization & Configuration
- *
- * The configuration of the USB driver happens in multiple stages:
- *
- * - (a) Configuration of the basic parameters:
- * In this stage the basic parameters for the driver are configured,
- * including the base address and the controller ID.
- *
- * - (b) Configuration of the DEVICE endpoints (if applicable):
- * If DEVICE mode is desired, the endpoints of the controller need to be
- * configured using the XUsbPs_DeviceConfig data structure. Once the
- * endpoint configuration is set up in the data structure, The user then
- * needs to allocate the required amount of DMAable memory and
- * finalize the configuration of the XUsbPs_DeviceConfig data structure,
- * e.g. setting the DMAMemVirt and DMAMemPhys members.
- *
- * - (c) Configuration of the DEVICE modes:
- * In the second stage the parameters for DEVICE are configured.
- * The caller only needs to configure the modes that are
- * actually used. Configuration is done with the:
- * XUsbPs_ConfigureDevice()
- * Configuration parameters are defined and passed
- * into these functions using the:
- * XUsbPs_DeviceConfig data structures.
- *
- *
- *
USB Device Endpoints
- *
- * The USB core supports up to 4 endpoints. Each endpoint has two directions,
- * an OUT (RX) and an IN (TX) direction. Note that the direction is viewed from
- * the host's perspective. Endpoint 0 defaults to be the control endpoint and
- * does not need to be set up. Other endpoints need to be configured and set up
- * depending on the application. Only endpoints that are actuelly used by the
- * application need to be initialized.
- * See the example code (xusbps_intr_example.c) for more information.
- *
- *
- *
Interrupt Handling
- *
- * The USB core uses one interrupt line to report interrupts to the CPU.
- * Interrupts are handled by the driver's interrupt handler function
- * XUsbPs_IntrHandler().
- * It has to be registered with the OS's interrupt subsystem. The driver's
- * interrupt handler divides incoming interrupts into two categories:
- *
- * - General device interrupts
- * - Endopint related interrupts
- *
- * The user (typically the adapter layer) can register general interrupt
- * handler functions and endpoint specific interrupt handler functions with the
- * driver to receive those interrupts by calling the
- * XUsbPs_IntrSetHandler()
- * and
- * XUsbPs_EpSetHandler()
- * functions respectively. Calling these functions with a NULL pointer as the
- * argument for the function pointer will "clear" the handler function.
- *
- * The user can register one handler function for the generic interrupts and
- * two handler functions for each endpoint, one for the RX (OUT) and one for
- * the TX (IN) direction. For some applications it may be useful to register a
- * single endpoint handler function for muliple endpoints/directions.
- *
- * When a callback function is called by the driver, parameters identifying the
- * type of the interrupt will be passed into the handler functions. For general
- * interrupts the interrupt mask will be passed into the handler function. For
- * endpoint interrupts the parameters include the number of the endpoint, the
- * direction (OUT/IN) and the type of the interrupt.
- *
- *
- *
Data buffer handling
- *
- * Data buffers are sent to and received from endpoint using the
- * XUsbPs_EpBufferSend(), XUsbPs_EpBufferSendWithZLT()
- * and
- * XUsbPs_EpBufferReceive()
- * functions.
- *
- * User data buffer size is limited to 16 Kbytes. If the user wants to send a
- * data buffer that is bigger than this limit it needs to break down the data
- * buffer into multiple fragments and send the fragments individually.
- *
- * From the controller perspective Data buffers can be aligned at any boundary.
- * if the buffers are from cache region then the buffer and buffer size should
- * be aligned to cache line aligned
- *
- *
- *
Zero copy
- *
- * The driver uses a zero copy mechanism which imposes certain restrictions to
- * the way the user can handle the data buffers.
- *
- * One restriction is that the user needs to release a buffer after it is done
- * processing the data in the buffer.
- *
- * Similarly, when the user sends a data buffer it MUST not re-use the buffer
- * until it is notified by the driver that the buffer has been transmitted. The
- * driver will notify the user via the registered endpoint interrupt handling
- * function by sending a XUSBPS_EP_EVENT_DATA_TX event.
- *
- *
- *
DMA
- *
- * The driver uses DMA internally to move data from/to memory. This behaviour
- * is transparent to the user. Keeping the DMA handling hidden from the user
- * has the advantage that the same API can be used with USB cores that do not
- * support DMA.
- *
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- ----------------------------------------------------------
- * 1.00a wgr 10/10/10 First release
- * 1.02a wgr 05/16/12 Removed comments as they are showing up in SDK
- * Tabs for CR 657898
- * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet
- * handling.
- * 1.04a nm 10/23/12 Fixed CR# 679106.
- * 11/02/12 Fixed CR# 683931. Mult bits are set properly in dQH.
- * 2.00a kpc 04/03/14 Fixed CR#777763. Corrected the setup tripwire macro val.
- * 2.1 kpc 04/28/14 Removed unused function prototypes
- * 2.2 kpc 08/23/14 Exported XUsbPs_DeviceReset API as global for calling in
- * code coverage tests.
- * 2.3 kpc 02/19/14 Fixed CR#873972, CR#873974. Corrected the logic for proper
- * moving of dTD Head/Tail Pointers. Invalidate the cache
- * after buffer receive in Endpoint Buffer Handler.
- * 2.4 sg 04/26/16 Fixed CR#949693, Corrected the logic for EP flush
- * ms 03/17/17 Added readme.txt file in examples folder for doxygen
- * generation.
- * ms 04/10/17 Modified filename tag to include the file in doxygen
- * examples.
- * 2.5 pm 02/20/20 Added ISO support for usb 2.0 and ch9 common framework
- * calls.
- *
- *
- ******************************************************************************/
-
-#ifndef XUSBPS_H
-#define XUSBPS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xusbps_hw.h"
-#include "xil_types.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions *****************************/
-
-/**
- * @name System hang prevention Timeout counter value.
- *
- * This value is used throughout the code to initialize a Timeout counter that
- * is used when hard polling a register. The ides is to initialize the Timeout
- * counter to a value that is longer than any expected Timeout but short enough
- * so the system will continue to work and report an error while the user is
- * still paying attention. A reasonable Timeout time would be about 10 seconds.
- * The XUSBPS_TIMEOUT_COUNTER value should be chosen so a polling loop would
- * run about 10 seconds before a Timeout is detected. For example:
- *
- * int Timeout = XUSBPS_TIMEOUT_COUNTER;
- * while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- * XUSBPS_CMD_OFFSET) &
- * XUSBPS_CMD_RST_MASK) && --Timeout) {
- * ;
- * }
- * if (0 == Timeout) {
- * return XST_FAILURE;
- * }
- *
- */
-#define XUSBPS_TIMEOUT_COUNTER 1000000
-
-
-/**
- * @name Endpoint Direction (bitmask)
- * Definitions to be used with Endpoint related function that require a
- * 'Direction' parameter.
- *
- * NOTE:
- * The direction is always defined from the perspective of the HOST! This
- * means that an IN endpoint on the controller is used for sending data while
- * the OUT endpoint on the controller is used for receiving data.
- * @{
- */
-#define XUSBPS_EP_DIRECTION_IN 0x01 /**< Endpoint direction IN. */
-#define XUSBPS_EP_DIRECTION_OUT 0x02 /**< Endpoint direction OUT. */
-/* @} */
-
-
-/**
- * @name Endpoint Type
- * Definitions to be used with Endpoint related functions that require a 'Type'
- * parameter.
- * @{
- */
-#define XUSBPS_EP_TYPE_NONE 0 /**< Endpoint is not used. */
-#define XUSBPS_EP_TYPE_CONTROL 1 /**< Endpoint for Control Transfers */
-#define XUSBPS_EP_TYPE_ISOCHRONOUS 2 /**< Endpoint for isochronous data */
-#define XUSBPS_EP_TYPE_BULK 3 /**< Endpoint for BULK Transfers. */
-#define XUSBPS_EP_TYPE_INTERRUPT 4 /**< Endpoint for interrupt Transfers */
-/* @} */
-
-/**
- * Endpoint Max Packet Length in DeviceConfig is a coded value, ch9.6.6.
- *
- * @{
- */
-#define ENDPOINT_MAXP_LENGTH 0x400
-#define ENDPOINT_MAXP_MULT_MASK 0xC00
-#define ENDPOINT_MAXP_MULT_SHIFT 10
-/* @} */
-
-/**
- * @name Field names for status retrieval
- * Definitions for the XUsbPs_GetStatus() function call 'StatusType'
- * parameter.
- * @{
- */
-#define XUSBPS_EP_STS_ADDRESS 1 /**< Address of controller. */
-#define XUSBPS_EP_STS_CONTROLLER_STATE 2 /**< Current controller state. */
-/* @} */
-
- /*
- * Device Speeds
- */
- #define XUSBPS_SPEED_UNKNOWN 0U
- #define XUSBPS_SPEED_LOW 1U
- #define XUSBPS_SPEED_FULL 2U
- #define XUSBPS_SPEED_HIGH 3U
-
-/**
- * @name USB Default alternate setting
- *
- * @{
- */
-#define XUSBPS_DEFAULT_ALT_SETTING 0 /**< The default alternate setting is 0 */
-/* @} */
-
- /*
- * Device States
- */
- #define XUSBPS_STATE_ATTACHED 0U
- #define XUSBPS_STATE_POWERED 1U
- #define XUSBPS_STATE_DEFAULT 2U
- #define XUSBPS_STATE_ADDRESS 3U
- #define XUSBPS_STATE_CONFIGURED 4U
- #define XUSBPS_STATE_SUSPENDED 5U
-
-/**
- * @name Endpoint event types
- * Definitions that are used to identify events that occur on endpoints. Passed
- * to the endpoint event handler functions registered with
- * XUsbPs_EpSetHandler().
- * @{
- */
-#define XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED 0x01
- /**< Setup data has been received on the endpoint. */
-#define XUSBPS_EP_EVENT_DATA_RX 0x02
- /**< Data frame has been received on the endpoint. */
-#define XUSBPS_EP_EVENT_DATA_TX 0x03
- /**< Data frame has been sent on the endpoint. */
-/* @} */
-
-
-/*
- * Maximum packet size for endpoint, 1024
- * @{
- */
-#define XUSBPS_MAX_PACKET_SIZE 1024
- /**< Maximum value can be put into the queue head */
-/* @} */
-/**************************** Type Definitions *******************************/
-
-/******************************************************************************
- * This data type defines the callback function to be used for Endpoint
- * handlers.
- *
- * @param CallBackRef is the Callback reference passed in by the upper
- * layer when setting the handler, and is passed back to the upper
- * layer when the handler is called.
- * @param EpNum is the Number of the endpoint that caused the event.
- * @param EventType is the type of the event that occurred on the endpoint.
- * @param Data is a pointer to user data pointer specified when callback
- * was registered.
- */
-typedef void (*XUsbPs_EpHandlerFunc)(void *CallBackRef,
- u8 EpNum, u8 EventType, void *Data);
-
-/******************************************************************************
- * This data type defines the callback function to be used for Endpoint
- * handlers.
- *
- * @param CallBackRef is the Callback reference passed in by the upper
- * layer when setting the handler, and is passed back to the upper
- * layer when the handler is called.
- * @param RequestedBytes is the number of bytes requested to transfer.
- * @param BytesTxed is the actual number of bytes to be transfer.
- */
-typedef void (*XUsbPs_EpIsoHandlerFunc)(void *CallBackRef,
- u32 RequestedBytes, u32 BytesTxed);
-
-/******************************************************************************
- * This data type defines the callback function to be used for the general
- * interrupt handler.
- *
- * @param CallBackRef is the Callback reference passed in by the upper
- * layer when setting the handler, and is passed back to the upper
- * layer when the handler is called.
- * @param IrqMask is the Content of the interrupt status register. This
- * value can be used by the callback function to distinguish the
- * individual interrupt types.
- */
-typedef void (*XUsbPs_IntrHandlerFunc)(void *CallBackRef, u32 IrqMask);
-
-
-/******************************************************************************/
-
-/* The following type definitions are used for referencing Queue Heads and
- * Transfer Descriptors. The structures themselves are not used, however, the
- * types are used in the API to avoid using (void *) pointers.
- */
-typedef u8 XUsbPs_dQH[XUSBPS_dQH_ALIGN];
-typedef u8 XUsbPs_dTD[XUSBPS_dTD_ALIGN];
-
-
-/**
- * The following data structures are used internally by the L0/L1 driver.
- * Their contents MUST NOT be changed by the upper layers.
- */
-
-/**
- * The following data structure represents OUT endpoint.
- */
-typedef struct {
- XUsbPs_dQH *dQH;
- /**< Pointer to the Queue Head structure of the endpoint. */
-
- XUsbPs_dTD *dTDs;
- /**< Pointer to the first dTD of the dTD list for this
- * endpoint. */
-
- XUsbPs_dTD *dTDCurr;
- /**< Buffer to the currently processed descriptor. */
-
- u8 *dTDBufs;
- /**< Pointer to the first buffer of the buffer list for this
- * endpoint. */
-
- XUsbPs_EpHandlerFunc HandlerFunc;
- XUsbPs_EpIsoHandlerFunc HandlerIsoFunc;
- /**< Handler function for this endpoint. */
- void *HandlerRef;
- /**< User data reference for the handler. */
- u32 RequestedBytes; /**< RequestedBytes for transfer */
- u32 BytesTxed; /**< Actual Bytes transferred */
- u8 *BufferPtr; /**< Buffer location */
- u8 MemAlloted; /**< Mem alloted and data is not received */
- u32 Interval; /**< Data transfer service interval */
-} XUsbPs_EpOut;
-
-
-/**
- * The following data structure represents IN endpoint.
- */
-typedef struct {
- XUsbPs_dQH *dQH;
- /**< Pointer to the Queue Head structure of the endpoint. */
-
- XUsbPs_dTD *dTDs;
- /**< List of pointers to the Transfer Descriptors of the
- * endpoint. */
-
- XUsbPs_dTD *dTDHead;
- /**< Buffer to the next available descriptor in the list. */
-
- XUsbPs_dTD *dTDTail;
- /**< Buffer to the last unsent descriptor in the list*/
-
- XUsbPs_EpHandlerFunc HandlerFunc;
- XUsbPs_EpIsoHandlerFunc HandlerIsoFunc;
- /**< Handler function for this endpoint. */
- void *HandlerRef;
- /**< User data reference for the handler. */
- u32 RequestedBytes; /**< RequestedBytes for transfer */
- u32 BytesTxed; /**< Actual Bytes transferred */
- u8 *BufferPtr; /**< Buffer location */
- u32 Interval; /**< Data transfer service interval */
-} XUsbPs_EpIn;
-
-
-/**
- * The following data structure represents an endpoint used internally
- * by the L0/L1 driver.
- */
-typedef struct {
- /* Each endpoint has an OUT and an IN component.
- */
- XUsbPs_EpOut Out; /**< OUT endpoint structure */
- XUsbPs_EpIn In; /**< IN endpoint structure */
-} XUsbPs_Endpoint;
-
-
-
-/**
- * The following structure is used by the user to receive Setup Data from an
- * endpoint. Using this structure simplifies the process of interpreting the
- * setup data in the core's data fields.
- *
- * The naming scheme for the members of this structure is different from the
- * naming scheme found elsewhere in the code. The members of this structure are
- * defined in the Chapter 9 USB reference guide. Using this naming scheme makes
- * it easier for people familiar with the standard to read the code.
- */
-typedef struct {
- u8 bmRequestType; /**< bmRequestType in setup data */
- u8 bRequest; /**< bRequest in setup data */
- u16 wValue; /**< wValue in setup data */
- u16 wIndex; /**< wIndex in setup data */
- u16 wLength; /**< wLength in setup data */
-}
-XUsbPs_SetupData;
-
-
-/**
- * Data structures used to configure endpoints.
- */
-typedef struct {
- u32 Type;
- /**< Endpoint type:
- - XUSBPS_EP_TYPE_CONTROL
- - XUSBPS_EP_TYPE_ISOCHRONOUS
- - XUSBPS_EP_TYPE_BULK
- - XUSBPS_EP_TYPE_INTERRUPT */
-
- u32 NumBufs;
- /**< Number of buffers to be handled by this endpoint. */
- u32 BufSize;
- /**< Buffer size. Only relevant for OUT (receive) Endpoints. */
-
- u16 MaxPacketSize;
- /**< Maximum packet size for this endpoint. This number will
- * define the maximum number of bytes sent on the wire per
- * transaction. Range: 0..1024 */
-} XUsbPs_EpSetup;
-
-
-/**
- * Endpoint configuration structure.
- */
-typedef struct {
- XUsbPs_EpSetup Out; /**< OUT component of endpoint. */
- XUsbPs_EpSetup In; /**< IN component of endpoint. */
-} XUsbPs_EpConfig;
-
-
-/**
- * The XUsbPs_DeviceConfig structure contains the configuration information to
- * configure the USB controller for DEVICE mode. This data structure is used
- * with the XUsbPs_ConfigureDevice() function call.
- */
-typedef struct {
- u8 NumEndpoints; /**< Number of Endpoints for the controller.
- This number depends on the runtime
- configuration of driver. The driver may
- configure fewer endpoints than are available
- in the core. */
-
- XUsbPs_EpConfig EpCfg[XUSBPS_MAX_ENDPOINTS];
- /**< List of endpoint configurations. */
-
-
- u32 DMAMemPhys; /**< Physical base address of DMAable memory
- allocated for the driver. */
-
- /* The following members are used internally by the L0/L1 driver. They
- * MUST NOT be accesses and/or modified in any way by the upper layers.
- *
- * The reason for having these members is that we generally try to
- * avoid allocating memory in the L0/L1 driver as we want to be OS
- * independent. In order to avoid allocating memory for this data
- * structure wihin L0/L1 we put it into the XUsbPs_DeviceConfig
- * structure which is allocated by the caller.
- */
- XUsbPs_Endpoint Ep[XUSBPS_MAX_ENDPOINTS];
- /**< List of endpoint metadata structures. */
-
- u32 PhysAligned; /**< 64 byte aligned base address of the DMA
- memory block. Will be computed and set by
- the L0/L1 driver. */
-} XUsbPs_DeviceConfig;
-
-
-/**
- * The XUsbPs_Config structure contains configuration information for the USB
- * controller.
- *
- * This structure only contains the basic configuration for the controller. The
- * caller also needs to initialize the controller for the DEVICE mode
- * using the XUsbPs_DeviceConfig data structures with the
- * XUsbPs_ConfigureDevice() function call
- */
-typedef struct {
- u16 DeviceID; /**< Unique ID of controller. */
- u32 BaseAddress; /**< Core register base address. */
-} XUsbPs_Config;
-
-typedef XUsbPs_Config Usb_Config;
-
-struct Usb_DevData {
- u8 Speed;
- u8 State;
-
- void *PrivateData;
-};
-
-/**
- * The XUsbPs driver instance data. The user is required to allocate a
- * variable of this type for every USB controller in the system. A pointer to a
- * variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XUsbPs_SetupData SetupData;
- /**< Setup Packet buffer */
- XUsbPs_Config Config; /**< Configuration structure */
-
- int CurrentAltSetting; /**< Current alternative setting of interface */
-
- void *UserDataPtr; /**< Data pointer to be used by upper layers to
- store application dependent data structures.
- The upper layers are responsible to allocated
- and free the memory. The driver will not
- mofidy this data pointer. */
-
- /**
- * The following structures hold the configuration for DEVICE mode
- * of the controller. They are initialized using the
- * XUsbPs_ConfigureDevice() function call.
- */
- XUsbPs_DeviceConfig DeviceConfig;
- /**< Configuration for the DEVICE mode. */
-
- XUsbPs_IntrHandlerFunc HandlerFunc;
- /**< Handler function for the controller. */
- void *HandlerRef;
- /**< User data reference for the handler. */
- u32 HandlerMask;
- /**< User interrupt mask. Defines which interrupts will cause
- * the callback to be called. */
- struct Usb_DevData *AppData;
- u8 IsConfigDone;
- void *data_ptr; /* pointer for storing applications data */
-} XUsbPs;
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/******************************************************************************
- *
- * USB CONTROLLER RELATED MACROS
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
- * This macro returns the current frame number.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @return The current frame number.
- *
- * @note C-style signature:
- * u32 XUsbPs_GetFrameNum(const XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_GetFrameNum(InstancePtr) \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, XUSBPS_FRAME_OFFSET)
-
-
-/*****************************************************************************/
-/**
- * This macro starts the USB engine.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @note C-style signature:
- * void XUsbPs_Start(XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_Start(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
-
-
-/*****************************************************************************/
-/**
- * This macro stops the USB engine.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @note C-style signature:
- * void XUsbPs_Stop(XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_Stop(InstancePtr) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
-
-
-/*****************************************************************************/
-/**
- * This macro forces the USB engine to be in Full Speed (FS) mode.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @note C-style signature:
- * void XUsbPs_ForceFS(XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_ForceFS(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
- XUSBPS_PORTSCR_PFSC_MASK)
-
-
-/*****************************************************************************/
-/**
- * This macro starts the USB Timer 0, with repeat option for period of
- * one second.
- *
- * @param InstancePtr is a pointer to XUsbPs instance of the controller.
- * @param Interval is the interval for Timer0 to generate an interrupt
- *
- * @note C-style signature:
- * void XUsbPs_StartTimer0(XUsbPs *InstancePtr, u32 Interval)
- *
- ******************************************************************************/
-#define XUsbPs_StartTimer0(InstancePtr, Interval) \
-{ \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_TIMER0_LD_OFFSET, (Interval)); \
- XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
- XUSBPS_TIMER_RUN_MASK | \
- XUSBPS_TIMER_RESET_MASK | \
- XUSBPS_TIMER_REPEAT_MASK); \
-} \
-
-
-/*****************************************************************************/
-/**
-* This macro stops Timer 0.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_StopTimer0(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_StopTimer0(InstancePtr) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
- XUSBPS_TIMER_RUN_MASK)
-
-
-/*****************************************************************************/
-/**
-* This macro reads Timer 0.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_ReadTimer0(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_ReadTimer0(InstancePtr) \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_TIMER0_CTL_OFFSET) & \
- XUSBPS_TIMER_COUNTER_MASK
-
-
-/*****************************************************************************/
-/**
-* This macro force remote wakeup on host
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_RemoteWakeup(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_RemoteWakeup(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
- XUSBPS_PORTSCR_FPR_MASK)
-
-
-/******************************************************************************
- *
- * ENDPOINT RELATED MACROS
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
-* This macro enables the given endpoint for the given direction.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is number of the endpoint to enable.
-* @param Dir is direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpEnable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpEnable(InstancePtr, EpNum, Dir) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro disables the given endpoint for the given direction.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is the number of the endpoint to disable.
-* @param Dir is the direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpDisable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpDisable(InstancePtr, EpNum, Dir) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro stalls the given endpoint for the given direction, and flush
-* the buffers.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is number of the endpoint to stall.
-* @param Dir is the direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpStall(InstancePtr, EpNum, Dir) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro unstalls the given endpoint for the given direction.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is the Number of the endpoint to unstall.
-* @param Dir is the Direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpUnStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpUnStall(InstancePtr, EpNum, Dir) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro flush an endpoint upon interface disable
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is the number of the endpoint to flush.
-* @param Dir is the direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpFlush(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpFlush(InstancePtr, EpNum, Dir) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPFLUSH_OFFSET, \
- 1 << (EpNum + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? \
- XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT))) \
-
-/*****************************************************************************/
-/**
-* This macro enables the interrupts defined by the bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param IntrMask is the Bit mask of interrupts to be enabled.
-*
-* @note C-style signature:
-* void XUsbPs_IntrEnable(XUsbPs *InstancePtr, u32 IntrMask)
-*
-******************************************************************************/
-#define XUsbPs_IntrEnable(InstancePtr, IntrMask) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
-
-
-/*****************************************************************************/
-/**
-* This function disables the interrupts defined by the bit mask.
-*
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param IntrMask is a Bit mask of interrupts to be disabled.
-*
-* @note C-style signature:
-* void XUsbPs_IntrDisable(XUsbPs *InstancePtr, u32 IntrMask)
-*
-******************************************************************************/
-#define XUsbPs_IntrDisable(InstancePtr, IntrMask) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
-
-
-/*****************************************************************************/
-/**
-* This macro enables the endpoint NAK interrupts defined by the bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be
-* enabled.
-* @note C-style signature:
-* void XUsbPs_NakIntrEnable(XUsbPs *InstancePtr, u32 NakIntrMask)
-*
-******************************************************************************/
-#define XUsbPs_NakIntrEnable(InstancePtr, NakIntrMask) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
-
-
-/*****************************************************************************/
-/**
-* This macro disables the endpoint NAK interrupts defined by the bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param NakIntrMask is a Bit mask of endpoint NAK interrupts to be
-* disabled.
-*
-* @note
-* C-style signature:
-* void XUsbPs_NakIntrDisable(XUsbPs *InstancePtr, u32 NakIntrMask)
-*
-******************************************************************************/
-#define XUsbPs_NakIntrDisable(InstancePtr, NakIntrMask) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
-
-
-/*****************************************************************************/
-/**
-* This function clears the endpoint NAK interrupts status defined by the
-* bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be cleared.
-*
-* @note C-style signature:
-* void XUsbPs_NakIntrClear(XUsbPs *InstancePtr, u32 NakIntrMask)
-*
-******************************************************************************/
-#define XUsbPs_NakIntrClear(InstancePtr, NakIntrMask) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_EPNAKISR_OFFSET, NakIntrMask)
-
-
-
-/*****************************************************************************/
-/**
-* This macro sets the Interrupt Threshold value in the control register
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param Threshold is the Interrupt threshold to be set.
-* Allowed values:
-* - XUSBPS_CMD_ITHRESHOLD_0 - Immediate interrupt
-* - XUSBPS_CMD_ITHRESHOLD_1 - 1 Frame
-* - XUSBPS_CMD_ITHRESHOLD_2 - 2 Frames
-* - XUSBPS_CMD_ITHRESHOLD_4 - 4 Frames
-* - XUSBPS_CMD_ITHRESHOLD_8 - 8 Frames
-* - XUSBPS_CMD_ITHRESHOLD_16 - 16 Frames
-* - XUSBPS_CMD_ITHRESHOLD_32 - 32 Frames
-* - XUSBPS_CMD_ITHRESHOLD_64 - 64 Frames
-*
-* @note
-* C-style signature:
-* void XUsbPs_SetIntrThreshold(XUsbPs *InstancePtr, u8 Threshold)
-*
-******************************************************************************/
-#define XUsbPs_SetIntrThreshold(InstancePtr, Threshold) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_CMD_OFFSET, (Threshold))\
-
-
-/*****************************************************************************/
-/**
-* This macro sets the Tripwire bit in the USB command register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_SetTripwire(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_SetSetupTripwire(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, \
- XUSBPS_CMD_SUTW_MASK)
-
-
-/*****************************************************************************/
-/**
-* This macro clears the Tripwire bit in the USB command register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_ClrTripwire(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_ClrSetupTripwire(InstancePtr) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, \
- XUSBPS_CMD_SUTW_MASK)
-
-
-/*****************************************************************************/
-/**
-* This macro checks if the Tripwire bit in the USB command register is set.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @return
-* - TRUE: The tripwire bit is still set.
-* - FALSE: The tripwire bit has been cleared.
-*
-* @note C-style signature:
-* int XUsbPs_TripwireIsSet(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_SetupTripwireIsSet(InstancePtr) \
- (XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_CMD_OFFSET) & \
- XUSBPS_CMD_SUTW_MASK ? TRUE : FALSE)
-
-
-/******************************************************************************
-*
-* GENERAL REGISTER / BIT MANIPULATION MACROS
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-* This macro sets the given bit mask in the register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param RegOffset is the register offset to be written.
-* @param Bits is the Bits to be set in the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XUsbPs_SetBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
-*
-*****************************************************************************/
-#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- RegOffset) | (Bits));
-
-
-/****************************************************************************/
-/**
-*
-* This macro clears the given bits in the register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param RegOffset is the register offset to be written.
-* @param Bits are the bits to be cleared in the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XUsbPs_ClrBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
-*
-*****************************************************************************/
-#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- RegOffset) & ~(Bits));
-
-
-/************************** Function Prototypes ******************************/
-
-/**
- * Setup / Initialize functions.
- *
- * Implemented in file xusbps.c
- */
-int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
- const XUsbPs_Config *ConfigPtr, u32 BaseAddress);
-
-int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr,
- const XUsbPs_DeviceConfig *CfgPtr);
-
-/**
- * Common functions used for DEVICE/HOST mode.
- */
-int XUsbPs_Reset(XUsbPs *InstancePtr);
-
-void XUsbPs_DeviceReset(XUsbPs *InstancePtr);
-
-/**
- * DEVICE mode specific functions.
- */
-int XUsbPs_BusReset(XUsbPs *InstancePtr);
-int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address);
-
-
-/**
- * Handling Suspend and Resume.
- *
- * Implemented in xusbps.c
- */
-int XUsbPs_Suspend(const XUsbPs *InstancePtr);
-int XUsbPs_Resume(const XUsbPs *InstancePtr);
-int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr);
-
-
-/*
- * Functions for managing Endpoints / Transfers
- *
- * Implemented in file xusbps_endpoint.c
- */
-int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum,
- const u8 *BufferPtr, u32 BufferLen);
-int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum,
- const u8 *BufferPtr, u32 BufferLen);
-int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
- u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle);
-void XUsbPs_EpBufferRelease(u32 Handle);
-
-int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
- XUsbPs_EpHandlerFunc CallBackFunc,
- void *CallBackRef);
-s32 XUsbPs_EpSetIsoHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
- XUsbPs_EpIsoHandlerFunc CallBackFunc);
-int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum,
- XUsbPs_SetupData *SetupDataPtr);
-
-int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction);
-
-int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr,
- int EpNum, unsigned short NewDirection, int DirectionChanged);
-
-/*
- * Interrupt handling functions
- *
- * Implemented in file xusbps_intr.c
- */
-void XUsbPs_IntrHandler(void *InstancePtr);
-
-int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
- XUsbPs_IntrHandlerFunc CallBackFunc,
- void *CallBackRef, u32 Mask);
-void XUsbPs_EpGetData(XUsbPs *InstancePtr, u8 EpNum, u32 BufferLen);
-
-s32 XUsbPs_EpDataBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
- u8 *BufferPtr, u32 BufferLen);
-/*
- * Helper functions for static configuration.
- * Implemented in xusbps_sinit.c
- */
-XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceId);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XUSBPS_H */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2f/70050a565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2f/70050a565243001d18b399c1eb9b3628
deleted file mode 100644
index a2443fe..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2f/70050a565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,100 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xtime_l.c
-*
-* This file contains low level functions to get/set time from the Global Timer
-* register in the ARM Cortex A9 MP core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 1.00a rp/sdm 11/03/09 Initial release.
-* 3.07a sgd 07/05/12 Updated get/set time functions to make use Global Timer
-* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
-* displaying same warnings multiple times. It fixes CR#1090562.
-*
-*
-* @note None.
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "xtime_l.h"
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER)
-#pragma message ("For the sleep routines, Global timer is being used")
-#endif
-/****************************************************************************/
-/**
-* @brief Set the time in the Global Timer Counter Register.
-*
-* @param Xtime_Global: 64-bit Value to be written to the Global Timer
-* Counter Register.
-*
-* @return None.
-*
-* @note When this function is called by any one processor in a multi-
-* processor environment, reference time will reset/lost for all
-* processors.
-*
-****************************************************************************/
-void XTime_SetTime(XTime Xtime_Global)
-{
- /* Disable Global Timer */
- Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x0);
-
- /* Updating Global Timer Counter Register */
- Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_LOWER_OFFSET, (u32)Xtime_Global);
- Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_UPPER_OFFSET,
- (u32)((u32)(Xtime_Global>>32U)));
-
- /* Enable Global Timer */
- Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x1);
-}
-
-/****************************************************************************/
-/**
-* @brief Get the time from the Global Timer Counter Register.
-*
-* @param Xtime_Global: Pointer to the 64-bit location which will be
-* updated with the current timer value.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XTime_GetTime(XTime *Xtime_Global)
-{
- u32 low;
- u32 high;
-
- /* Reading Global Timer Counter Register */
- do
- {
- high = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET);
- low = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_LOWER_OFFSET);
- } while(Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET) != high);
-
- *Xtime_Global = (((XTime) high) << 32U) | (XTime) low;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2f/81a6ba585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2f/81a6ba585243001d18b399c1eb9b3628
deleted file mode 100644
index 68408ea..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2f/81a6ba585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,28 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/*
- *
- * This is a template implementation of the "__open" function used by
- * the standard library. Replace it with a system-specific
- * implementation.
- *
- * The "__open" function opens the file named "filename" as specified
- * by "mode".
- * open -- open a file descriptor. We don't have a filesystem, so
- * we return an error.
- *
- */
-
-#include
-#include "xil_types.h"
-
-sint32 __open(const char8 * filename, sint32 mode);
-
-sint32 __open(const char8 * filename, sint32 mode)
-{
-return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2f/90e187595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2f/90e187595243001d18b399c1eb9b3628
deleted file mode 100644
index b80c577..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2f/90e187595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,281 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#ifndef PROFILE_TIMER_HW_H
-#define PROFILE_TIMER_HW_H
-
-#include "profile.h"
-
-#ifdef PROC_PPC
-#if defined __GNUC__
-# define SYNCHRONIZE_IO __asm__ volatile ("eieio")
-#elif defined __DCC__
-# define SYNCHRONIZE_IO __asm volatile(" eieio")
-#else
-# define SYNCHRONIZE_IO
-#endif
-#endif
-
-#ifdef PROC_PPC
-#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
-#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
-#else
-#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
-#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
-#endif
-
-#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
- ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \
- (u32)(RegOffset)), (u32)(ValueToWrite))
-
-#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
- ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
-
-#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
- ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (RegisterValue))
-
-#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \
- ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
-
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef PROC_PPC
-#include "xexception_l.h"
-#include "xtime_l.h"
-#include "xpseudo_asm.h"
-#endif
-
-#ifdef TIMER_CONNECT_INTC
-#include "xintc_l.h"
-#include "xintc.h"
-#endif /* TIMER_CONNECT_INTC */
-
-#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
-#include "xtmrctr_l.h"
-#endif
-
-#ifdef PROC_CORTEXA9
-#include "xscutimer_hw.h"
-#include "xscugic.h"
-#endif
-
-extern u32 timer_clk_ticks ;
-
-/*--------------------------------------------------------------------
- * PowerPC Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_PPC
-
-#ifdef PPC_PIT_INTERRUPT
-u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */
-#endif
-
-#ifdef PROC_PPC440
-#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
-#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
-#define XREG_SPR_PIT XREG_SPR_DEC
-#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
-#endif
-
-/* --------------------------------------------------------------------
- * Disable the Timer - During Profiling
- *
- * For PIT Timer -
- * 1. XTime_PITDisableInterrupt() ;
- * 2. Store the remaining timer clk tick
- * 3. Stop the PIT Timer
- *-------------------------------------------------------------------- */
-
-#ifdef PPC_PIT_INTERRUPT
-#define disable_timer() \
- { \
- u32 val; \
- val=mfspr(XREG_SPR_TCR); \
- mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \
- timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
- mtspr(XREG_SPR_PIT, 0); \
- }
-#else
-#define disable_timer() \
- { \
- u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(addr); \
- tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
- ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
- }
-#endif
-
-
-
-/* --------------------------------------------------------------------
- * Enable the Timer
- *
- * For PIT Timer -
- * 1. Load the remaining timer clk ticks
- * 2. XTime_PITEnableInterrupt() ;
- *-------------------------------------------------------------------- */
-#ifdef PPC_PIT_INTERRUPT
-#define enable_timer() \
- { \
- u32 val; \
- val=mfspr(XREG_SPR_TCR); \
- mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
- mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
- }
-#else
-#define enable_timer() \
- { \
- u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(addr); \
- tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
- ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
- }
-#endif
-
-
-
-/* --------------------------------------------------------------------
- * Send Ack to Timer Interrupt
- *
- * For PIT Timer -
- * 1. Load the timer clk ticks
- * 2. Enable AutoReload and Interrupt
- * 3. Clear PIT Timer Status bits
- *-------------------------------------------------------------------- */
-#ifdef PPC_PIT_INTERRUPT
-#define timer_ack() \
- { \
- u32 val; \
- mtspr(XREG_SPR_PIT, timer_clk_ticks); \
- mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
- val=mfspr(XREG_SPR_TCR); \
- mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
- }
-#else
-#define timer_ack() \
- { \
- u32 csr; \
- csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
- ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
- }
-#endif
-
-/*-------------------------------------------------------------------- */
-#endif /* PROC_PPC */
-/* -------------------------------------------------------------------- */
-
-
-
-
-/* --------------------------------------------------------------------
- * MicroBlaze Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_MICROBLAZE
-
-/* --------------------------------------------------------------------
- * Disable the Timer during Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define disable_timer() \
- { \
- u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
- Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
- Addr += (u32)XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(Addr); \
- tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
- u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
- OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
- OutAddr += (u32)XTC_TCSR_OFFSET; \
- ProfIo_Out32(OutAddr, (u32)tmp_v); \
- }
-
-
-/* --------------------------------------------------------------------
- * Enable the Timer after Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define enable_timer() \
- { \
- u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
- Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
- Addr += (u32)XTC_TCSR_OFFSET; \
- u32 tmp_v = (u32)ProfIo_In32(Addr); \
- tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \
- ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
- }
-
-
-/* --------------------------------------------------------------------
- * Send Ack to Timer Interrupt
- *
- *-------------------------------------------------------------------- */
-#define timer_ack() \
- { \
- u32 csr; \
- csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \
- ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \
- }
-
-/*-------------------------------------------------------------------- */
-#endif /* PROC_MICROBLAZE */
-/*-------------------------------------------------------------------- */
-
-/* --------------------------------------------------------------------
- * Cortex A9 Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_CORTEXA9
-
-/* --------------------------------------------------------------------
- * Disable the Timer during Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define disable_timer() \
-{ \
- u32 Reg; \
- Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
- Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
- Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
-}
-
-
-/* --------------------------------------------------------------------
- * Enable the Timer after Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define enable_timer() \
-{ \
- u32 Reg; \
- Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
- Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
- Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
-}
-
-
-/* --------------------------------------------------------------------
- * Send Ack to Timer Interrupt
- *
- *-------------------------------------------------------------------- */
-#define timer_ack() \
-{ \
- Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
- (u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
-}
-
-/*-------------------------------------------------------------------- */
-#endif /* PROC_CORTEXA9 */
-/*-------------------------------------------------------------------- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2f/f039d6575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2f/f039d6575243001d18b399c1eb9b3628
deleted file mode 100644
index e1bcd93..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/2f/f039d6575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,762 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
- *
- * @file xemacps_bd.h
-* @addtogroup emacps_v3_15
-* @{
- *
- * This header provides operations to manage buffer descriptors in support
- * of scatter-gather DMA.
- *
- * The API exported by this header defines abstracted macros that allow the
- * user to read/write specific BD fields.
- *
- * Buffer Descriptors
- *
- * A buffer descriptor (BD) defines a DMA transaction. The macros defined by
- * this header file allow access to most fields within a BD to tailor a DMA
- * transaction according to user and hardware requirements. See the hardware
- * IP DMA spec for more information on BD fields and how they affect transfers.
- *
- * The XEmacPs_Bd structure defines a BD. The organization of this structure
- * is driven mainly by the hardware for use in scatter-gather DMA transfers.
- *
- * Performance
- *
- * Limiting I/O to BDs can improve overall performance of the DMA channel.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -------------------------------------------------------
- * 1.00a wsy 01/10/10 First release
- * 2.1 srt 07/15/14 Add support for Zynq Ultrascale MP GEM specification
- * and 64-bit changes.
- * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
- * 3.0 hk 02/20/15 Added support for jumbo frames.
- * Disable extended mode. Perform all 64 bit changes under
- * check for arch64.
- * 3.2 hk 11/18/15 Change BD typedef and number of words.
- * 3.8 hk 08/18/18 Remove duplicate definition of XEmacPs_BdSetLength
- * 3.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
- *
- *
- *
- * ***************************************************************************
- */
-
-#ifndef XEMACPS_BD_H /* prevent circular inclusions */
-#define XEMACPS_BD_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-#ifdef __aarch64__
-/* Minimum BD alignment */
-#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U
-#define XEMACPS_BD_NUM_WORDS 4U
-#else
-/* Minimum BD alignment */
-#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U
-#define XEMACPS_BD_NUM_WORDS 2U
-#endif
-
-/**
- * The XEmacPs_Bd is the type for buffer descriptors (BDs).
- */
-typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- * Zero out BD fields
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Nothing
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClear(BdPtr) \
- memset((BdPtr), 0, sizeof(XEmacPs_Bd))
-
-/****************************************************************************/
-/**
-*
-* Read the given Buffer Descriptor word.
-*
-* @param BaseAddress is the base address of the BD to read
-* @param Offset is the word offset to be read
-*
-* @return The 32-bit value of the field
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)
-*
-*****************************************************************************/
-#define XEmacPs_BdRead(BaseAddress, Offset) \
- (*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given Buffer Descriptor word.
-*
-* @param BaseAddress is the base address of the BD to write
-* @param Offset is the word offset to be written
-* @param Data is the 32-bit value to write to the field
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)
-*
-*****************************************************************************/
-#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \
- (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
-
-/*****************************************************************************/
-/**
- * Set the BD's Address field (word 0).
- *
- * @param BdPtr is the BD pointer to operate on
- * @param Addr is the value to write to BD's status field.
- *
- * @note :
- *
- * C-style signature:
- * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
- *
- *****************************************************************************/
-#if defined(__aarch64__) || defined(__arch64__)
-#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- (u32)((Addr) & ULONG64_LO_MASK)); \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
- (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
-#else
-#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
-#endif
-
-/*****************************************************************************/
-/**
- * Set the BD's Address field (word 0).
- *
- * @param BdPtr is the BD pointer to operate on
- * @param Addr is the value to write to BD's status field.
- *
- * @note : Due to some bits are mixed within receive BD's address field,
- * read-modify-write is performed.
- *
- * C-style signature:
- * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
- *
- *****************************************************************************/
-#ifdef __aarch64__
-#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- ~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
- (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
-#else
-#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))
-#endif
-
-/*****************************************************************************/
-/**
- * Set the BD's Status field (word 1).
- *
- * @param BdPtr is the BD pointer to operate on
- * @param Data is the value to write to BD's status field.
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetStatus(BdPtr, Data) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))
-
-
-/*****************************************************************************/
-/**
- * Retrieve the BD's Packet DMA transfer status word (word 1).
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Status word
- *
- * @note
- * C-style signature:
- * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)
- *
- * Due to the BD bit layout differences in transmit and receive. User's
- * caution is required.
- *****************************************************************************/
-#define XEmacPs_BdGetStatus(BdPtr) \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
-
-
-/*****************************************************************************/
-/**
- * Get the address (bits 0..31) of the BD's buffer address (word 0)
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#if defined(__aarch64__) || defined(__arch64__)
-#define XEmacPs_BdGetBufAddr(BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
-#else
-#define XEmacPs_BdGetBufAddr(BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
-#endif
-
-/*****************************************************************************/
-/**
- * Set transfer length in bytes for the given BD. The length must be set each
- * time a BD is submitted to hardware.
- *
- * @param BdPtr is the BD pointer to operate on
- * @param LenBytes is the number of bytes to transfer.
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
-
-
-/*****************************************************************************/
-/**
- * Retrieve the BD length field.
- *
- * For Tx channels, the returned value is the same as that written with
- * XEmacPs_BdSetLength().
- *
- * For Rx channels, the returned value is the size of the received packet.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Length field processed by hardware or set by
- * XEmacPs_BdSetLength().
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
- * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
- *
- *****************************************************************************/
-#define XEmacPs_BdGetLength(BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_LEN_MASK)
-
-/*****************************************************************************/
-/**
- * Retrieve the RX frame size.
- *
- * The returned value is the size of the received packet.
- * This API supports jumbo frame sizes if enabled.
- *
- * @param InstancePtr is the pointer to XEmacps instance
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Length field processed by hardware or set by
- * XEmacPs_BdSetLength().
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr)
- * RxBufMask is dependent on whether jumbo is enabled or not.
- *
- *****************************************************************************/
-#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- (InstancePtr)->RxBufMask)
-
-/*****************************************************************************/
-/**
- * Test whether the given BD has been marked as the last BD of a packet.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsLast(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Tell the DMA engine that the given transmit BD marks the end of the current
- * packet to be processed.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetLast(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_LAST_MASK))
-
-
-/*****************************************************************************/
-/**
- * Tell the DMA engine that the current packet does not end with the given
- * BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearLast(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_LAST_MASK))
-
-
-/*****************************************************************************/
-/**
- * Set this bit to mark the last descriptor in the receive buffer descriptor
- * list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-/*#define XEmacPs_BdSetRxWrap(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
- XEMACPS_RXBUF_WRAP_MASK))
-*/
-
-/*****************************************************************************/
-/**
- * Determine the wrap bit of the receive BD which indicates end of the
- * BD list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxWrap(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Sets this bit to mark the last descriptor in the transmit buffer
- * descriptor list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-/*#define XEmacPs_BdSetTxWrap(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_WRAP_MASK))
-*/
-
-/*****************************************************************************/
-/**
- * Determine the wrap bit of the transmit BD which indicates end of the
- * BD list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxWrap(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/*
- * Must clear this bit to enable the MAC to write data to the receive
- * buffer. Hardware sets this bit once it has successfully written a frame to
- * memory. Once set, software has to clear the bit before the buffer can be
- * used again. This macro clear the new bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearRxNew(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- ~XEMACPS_RXBUF_NEW_MASK))
-
-
-/*****************************************************************************/
-/**
- * Determine the new bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxNew(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Software sets this bit to disable the buffer to be read by the hardware.
- * Hardware sets this bit for the first buffer of a frame once it has been
- * successfully transmitted. This macro sets this bit of transmit BD to avoid
- * confusion.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetTxUsed(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_USED_MASK))
-
-
-/*****************************************************************************/
-/**
- * Software clears this bit to enable the buffer to be read by the hardware.
- * Hardware sets this bit for the first buffer of a frame once it has been
- * successfully transmitted. This macro clears this bit of transmit BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearTxUsed(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_USED_MASK))
-
-
-/*****************************************************************************/
-/**
- * Determine the used bit of the transmit BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxUsed(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if a frame fails to be transmitted due to too many retries.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxRetry(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if a frame fails to be transmitted due to data can not be
- * feteched in time or buffers are exhausted.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxUrun(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if a frame fails to be transmitted due to buffer is exhausted
- * mid-frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxExh(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Sets this bit, no CRC will be appended to the current frame. This control
- * bit must be set for the first buffer in a frame and will be ignored for
- * the subsequent buffers of a frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * This bit must be clear when using the transmit checksum generation offload,
- * otherwise checksum generation and substitution will not occur.
- *
- * C-style signature:
- * UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetTxNoCRC(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_NOCRC_MASK))
-
-
-/*****************************************************************************/
-/**
- * Clear this bit, CRC will be appended to the current frame. This control
- * bit must be set for the first buffer in a frame and will be ignored for
- * the subsequent buffers of a frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * This bit must be clear when using the transmit checksum generation offload,
- * otherwise checksum generation and substitution will not occur.
- *
- * C-style signature:
- * UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearTxNoCRC(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_NOCRC_MASK))
-
-
-/*****************************************************************************/
-/**
- * Determine the broadcast bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxBcast(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the multicast hash bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxMultiHash(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the unicast hash bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxUniHash(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if the received frame is a VLAN Tagged frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxVlan(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if the received frame has Type ID of 8100h and null VLAN
- * identifier(Priority tag).
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxPri(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if the received frame's Concatenation Format Indicator (CFI) of
- * the frames VLANTCI field was set.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxCFI(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the End Of Frame (EOF) bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxEOF(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the Start Of Frame (SOF) bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxSOF(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
-
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3/027b9c595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3/027b9c595243001d18b399c1eb9b3628
deleted file mode 100644
index fd80a0d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3/027b9c595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,62 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_clocking.h
-*
-* The xil_clocking.h file contains clocking related functions and macros.
-* certain conditions.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 7.2 sd 12/11/19 First release
-* 7.2 sd 03/20/20 Added checking for isolation case
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00 pkp 05/29/14 First release
-* 6.02 pkp 01/22/17 Added support for EL1 non-secure
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-#include "xil_mmu.h"
-#include "bspconfig.h"
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-#define BLOCK_SIZE_2MB 0x200000U
-#define BLOCK_SIZE_1GB 0x40000000U
-#define ADDRESS_LIMIT_4GB 0x100000000UL
-
-/************************** Variable Definitions *****************************/
-
-extern INTPTR MMUTableL1;
-extern INTPTR MMUTableL2;
-
-/************************** Function Prototypes ******************************/
-/*****************************************************************************/
-/**
-* @brief It sets the memory attributes for a section, in the translation
-* table. If the address (defined by Addr) is less than 4GB, the
-* memory attribute(attrib) is set for a section of 2MB memory. If the
-* address (defined by Addr) is greater than 4GB, the memory attribute
-* (attrib) is set for a section of 1GB memory.
-*
-* @param Addr: 64-bit address for which attributes are to be set.
-* @param attrib: Attribute for the specified memory region. xil_mmu.h
-* contains commonly used memory attributes definitions which can be
-* utilized for this function.
-*
-* @return None.
-*
-* @note The MMU and D-cache need not be disabled before changing an
-* translation table attribute.
-*
-******************************************************************************/
-void Xil_SetTlbAttributes(UINTPTR Addr, u64 attrib)
-{
- INTPTR *ptr;
- INTPTR section;
- u64 block_size;
- /* if region is less than 4GB MMUTable level 2 need to be modified */
- if(Addr < ADDRESS_LIMIT_4GB){
- /* block size is 2MB for addressed < 4GB*/
- block_size = BLOCK_SIZE_2MB;
- section = Addr / block_size;
- ptr = &MMUTableL2 + section;
- }
- /* if region is greater than 4GB MMUTable level 1 need to be modified */
- else{
- /* block size is 1GB for addressed > 4GB */
- block_size = BLOCK_SIZE_1GB;
- section = Addr / block_size;
- ptr = &MMUTableL1 + section;
- }
- *ptr = (Addr & (~(block_size-1))) | attrib;
-
- Xil_DCacheFlush();
-
- if (EL3 == 1)
- mtcptlbi(ALLE3);
- else if (EL1_NONSECURE == 1)
- mtcptlbi(VMALLE1);
-
- dsb(); /* ensure completion of the BP and TLB invalidation */
- isb(); /* synchronize context on this processor */
-
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3/f0ecc7585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3/f0ecc7585243001d18b399c1eb9b3628
deleted file mode 100644
index a146f83..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3/f0ecc7585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,387 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_exception.h
-*
-* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
-* For exception related functions that can be used across all Xilinx supported
-* processors, please use xil_exception.h.
-*
-* @addtogroup arm_exception_apis ARM Processor Exception Handling
-* @{
-* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
-* utilized for enabling/disabling IRQ, registering/removing handler for
-* exceptions or initializing exception vector table with null handler.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
-* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler.
-* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.
-* 7.0 mus 01/03/19 Tweak Xil_ExceptionEnableMask and
-* Xil_ExceptionDisableMask macros to support legacy
-* examples for Cortexa72 EL3 exception level.
-* 7.3 mus 04/15/20 Added Xil_EnableNestedInterrupts and
-* Xil_DisableNestedInterrupts macros for ARMv8.
-* For Cortexa72, these macro's would not be supported
-* at EL3, as Cortexa72 is using GIC-500(GICv3), which
-* triggeres only FIQ at EL3. Fix for CR#1062506
-# 7.6 mus 09/17/21 Updated flag checking to fix warning reported with
-# -Wundef compiler option CR#1110261
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
-#define XIL_EXCEPTION_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#include "bspconfig.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions ****************************/
-
-#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
-#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
-#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
-
-#define XIL_EXCEPTION_ID_FIRST 0U
-#if defined (__aarch64__)
-#define XIL_EXCEPTION_ID_SYNC_INT 1U
-#define XIL_EXCEPTION_ID_IRQ_INT 2U
-#define XIL_EXCEPTION_ID_FIQ_INT 3U
-#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
-#define XIL_EXCEPTION_ID_LAST 5U
-#else
-#define XIL_EXCEPTION_ID_RESET 0U
-#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
-#define XIL_EXCEPTION_ID_SWI_INT 2U
-#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
-#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
-#define XIL_EXCEPTION_ID_IRQ_INT 5U
-#define XIL_EXCEPTION_ID_FIQ_INT 6U
-#define XIL_EXCEPTION_ID_LAST 6U
-#endif
-
-/*
- * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
- */
-#if defined (versal) && !defined(ARMR5) && EL3
-#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_FIQ_INT
-#else
-#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
-#endif
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef is the exception handler function.
- */
-typedef void (*Xil_ExceptionHandler)(void *data);
-typedef void (*Xil_InterruptHandler)(void *data);
-
-/**
-*@endcond
-*/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* @brief Enable Exceptions.
-*
-* @param Mask: Value for enabling the exceptions.
-*
-* @return None.
-*
-* @note If bit is 0, exception is enabled.
-* C-Style signature: void Xil_ExceptionEnableMask(Mask)
-*
-******************************************************************************/
-#if defined (versal) && !defined(ARMR5) && EL3
-/*
- * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
- * only FIQ at EL3. Hence, tweaking this macro to always enable FIQ
- * ignoring argument passed by user.
- */
-#define Xil_ExceptionEnableMask(Mask) \
- mtcpsr(mfcpsr() & ~ ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
-#elif defined (__GNUC__) || defined (__ICCARM__)
-#define Xil_ExceptionEnableMask(Mask) \
- mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
-#else
-#define Xil_ExceptionEnableMask(Mask) \
- { \
- register u32 Reg __asm("cpsr"); \
- mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
- }
-#endif
-/****************************************************************************/
-/**
-* @brief Enable the IRQ exception.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-#if defined (versal) && !defined(ARMR5) && EL3
-#define Xil_ExceptionEnable() \
- Xil_ExceptionEnableMask(XIL_EXCEPTION_FIQ)
-#else
-#define Xil_ExceptionEnable() \
- Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
-#endif
-
-/****************************************************************************/
-/**
-* @brief Disable Exceptions.
-*
-* @param Mask: Value for disabling the exceptions.
-*
-* @return None.
-*
-* @note If bit is 1, exception is disabled.
-* C-Style signature: Xil_ExceptionDisableMask(Mask)
-*
-******************************************************************************/
-#if defined (versal) && !defined(ARMR5) && EL3
-/*
- * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
- * only FIQ at EL3. Hence, tweaking this macro to always disable FIQ
- * ignoring argument passed by user.
- */
-#define Xil_ExceptionDisableMask(Mask) \
- mtcpsr(mfcpsr() | ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
-#elif defined (__GNUC__) || defined (__ICCARM__)
-#define Xil_ExceptionDisableMask(Mask) \
- mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
-#else
-#define Xil_ExceptionDisableMask(Mask) \
- { \
- register u32 Reg __asm("cpsr"); \
- mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
- }
-#endif
-/****************************************************************************/
-/**
-* Disable the IRQ exception.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_ExceptionDisable() \
- Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
-
-#if ( defined (PLATFORM_ZYNQMP) && defined (EL3) && (EL3==1) )
-/****************************************************************************/
-/**
-* @brief Enable nested interrupts by clearing the I bit in DAIF.This
-* macro is defined for Cortex-A53 64 bit mode BSP configured to run
-* at EL3.. However,it is not defined for Versal Cortex-A72 BSP
-* configured to run at EL3. Reason is, Cortex-A72 is coupled
-* with GIC-500(GICv3 specifications) and it triggers only FIQ at EL3.
-*
-* @return None.
-*
-* @note This macro is supposed to be used from interrupt handlers. In the
-* interrupt handler the interrupts are disabled by default (I bit
-* is set as 1). To allow nesting of interrupts, this macro should be
-* used. It clears the I bit. Once that bit is cleared and provided the
-* preemption of interrupt conditions are met in the GIC, nesting of
-* interrupts will start happening.
-* Caution: This macro must be used with caution. Before calling this
-* macro, the user must ensure that the source of the current IRQ
-* is appropriately cleared. Otherwise, as soon as we clear the I
-* bit, there can be an infinite loop of interrupts with an
-* eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
- __asm__ __volatile__ ("mrs X1, ELR_EL3"); \
- __asm__ __volatile__ ("mrs X2, SPSR_EL3"); \
- __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-/****************************************************************************/
-/**
-* @brief Disable the nested interrupts by setting the I bit in DAIF. This
-* macro is defined for Cortex-A53 64 bit mode BSP configured to run
-* at EL3.
-*
-* @return None.
-*
-* @note This macro is meant to be called in the interrupt service routines.
-* This macro cannot be used independently. It can only be used when
-* nesting of interrupts have been enabled by using the macro
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-* point. The user then must call this macro before exiting the interrupt
-* service routine. This macro puts the ARM back in IRQ mode and
-* hence sets back the I bit.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
- __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \
- __asm__ __volatile__ ("msr ELR_EL3, X1"); \
- __asm__ __volatile__ ("msr SPSR_EL3, X2"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-#elif (defined (EL1_NONSECURE) && (EL1_NONSECURE==1))
-/****************************************************************************/
-/**
-* @brief Enable nested interrupts by clearing the I bit in DAIF.This
-* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit
-* BSP configured to run at EL1 NON SECURE
-*
-* @return None.
-*
-* @note This macro is supposed to be used from interrupt handlers. In the
-* interrupt handler the interrupts are disabled by default (I bit
-* is set as 1). To allow nesting of interrupts, this macro should be
-* used. It clears the I bit. Once that bit is cleared and provided the
-* preemption of interrupt conditions are met in the GIC, nesting of
-* interrupts will start happening.
-* Caution: This macro must be used with caution. Before calling this
-* macro, the user must ensure that the source of the current IRQ
-* is appropriately cleared. Otherwise, as soon as we clear the I
-* bit, there can be an infinite loop of interrupts with an
-* eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
- __asm__ __volatile__ ("mrs X1, ELR_EL1"); \
- __asm__ __volatile__ ("mrs X2, SPSR_EL1"); \
- __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-/****************************************************************************/
-/**
-* @brief Disable the nested interrupts by setting the I bit in DAIF. This
-* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit
-* BSP configured to run at EL1 NON SECURE
-*
-* @return None.
-*
-* @note This macro is meant to be called in the interrupt service routines.
-* This macro cannot be used independently. It can only be used when
-* nesting of interrupts have been enabled by using the macro
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-* point. The user then must call this macro before exiting the interrupt
-* service routine. This macro puts the ARM back in IRQ mode and
-* hence sets back the I bit.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
- __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \
- __asm__ __volatile__ ("msr ELR_EL1, X1"); \
- __asm__ __volatile__ ("msr SPSR_EL1, X2"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-#elif (!defined (__aarch64__) && !defined (ARMA53_32))
-/****************************************************************************/
-/**
-* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This
-* API is defined for cortex-a9 and cortex-r5.
-*
-* @return None.
-*
-* @note This macro is supposed to be used from interrupt handlers. In the
-* interrupt handler the interrupts are disabled by default (I and F
-* are 1). To allow nesting of interrupts, this macro should be
-* used. It clears the I and F bits by changing the ARM mode to
-* system mode. Once these bits are cleared and provided the
-* preemption of interrupt conditions are met in the GIC, nesting of
-* interrupts will start happening.
-* Caution: This macro must be used with caution. Before calling this
-* macro, the user must ensure that the source of the current IRQ
-* is appropriately cleared. Otherwise, as soon as we clear the I and
-* F bits, there can be an infinite loop of interrupts with an
-* eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
- __asm__ __volatile__ ("stmfd sp!, {lr}"); \
- __asm__ __volatile__ ("mrs lr, spsr"); \
- __asm__ __volatile__ ("stmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
- __asm__ __volatile__ ("stmfd sp!, {lr}");
-/****************************************************************************/
-/**
-* @brief Disable the nested interrupts by setting the I and F bits. This API
-* is defined for cortex-a9 and cortex-r5.
-*
-* @return None.
-*
-* @note This macro is meant to be called in the interrupt service routines.
-* This macro cannot be used independently. It can only be used when
-* nesting of interrupts have been enabled by using the macro
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-* point. The user then must call this macro before exiting the interrupt
-* service routine. This macro puts the ARM back in IRQ/FIQ mode and
-* hence sets back the I and F bits.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr cpsr_c, #0x92"); \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr spsr_cxsf, lr"); \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
-
-#endif
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler Handler,
- void *Data);
-
-extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
-extern void Xil_GetExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler *Handler, void **Data);
-
-extern void Xil_ExceptionInit(void);
-#if defined (__aarch64__)
-void Xil_SyncAbortHandler(void *CallBackRef);
-void Xil_SErrorAbortHandler(void *CallBackRef);
-#else
-extern void Xil_DataAbortHandler(void *CallBackRef);
-extern void Xil_PrefetchAbortHandler(void *CallBackRef);
-extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
-#endif
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_EXCEPTION_H */
-/**
-* @} End of "addtogroup arm_exception_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/30/20c767545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/30/20c767545243001d18b399c1eb9b3628
deleted file mode 100644
index d61e2b5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/30/20c767545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,118 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xsdps_core.h
-* @addtogroup sdps_v3_13
-* @{
-*
-* This header file contains the identifiers and basic HW access driver
-* functions (or macros) that can be used to access the device. Other driver
-* functions are defined in xsdps.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 3.9 mn 03/03/20 Restructured the code for more readability and modularity
-* mn 03/16/20 Move XSdPs_Select_Card API to User APIs
-* 3.12 sk 01/28/21 Added support for non-blocking write.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00 drg/jz 01/13/10 First Release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
-* 3.7 aru 08/17/18 Resolved MISRA-C mandatory violations.(CR#1007755)
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xuartps.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Function Prototypes *****************************/
-
-static void ReceiveDataHandler(XUartPs *InstancePtr);
-static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus);
-static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus);
-static void ReceiveTimeoutHandler(XUartPs *InstancePtr);
-static void ModemHandler(XUartPs *InstancePtr);
-
-
-/* Internal function prototypes implemented in xuartps.c */
-extern u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
-extern u32 XUartPs_SendBuffer(XUartPs *InstancePtr);
-
-/************************** Variable Definitions ****************************/
-
-typedef void (*Handler)(XUartPs *InstancePtr);
-
-/****************************************************************************/
-/**
-*
-* This function gets the interrupt mask
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-* The current interrupt mask. The mask indicates which interrupts
-* are enabled.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr)
-{
- /* Assert validates the input argument */
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /* Read the Interrupt Mask register */
- return (XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IMR_OFFSET));
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the interrupt mask.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-* @param Mask contains the interrupts to be enabled or disabled.
-* A '1' enables an interrupt, and a '0' disables.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask)
-{
- u32 TempMask = Mask;
- /* Assert validates the input arguments */
- Xil_AssertVoid(InstancePtr != NULL);
-
- TempMask &= (u32)XUARTPS_IXR_MASK;
-
- /* Write the mask to the IER Register */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IER_OFFSET, TempMask);
-
- /* Write the inverse of the Mask to the IDR register */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IDR_OFFSET, (~TempMask));
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the handler that will be called when an event (interrupt)
-* occurs that needs application's attention.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-* @param FuncPtr is the pointer to the callback function.
-* @param CallBackRef is the upper layer callback reference passed back
-* when the callback function is invoked.
-*
-* @return None.
-*
-* @note
-*
-* There is no assert on the CallBackRef since the driver doesn't know what it
-* is (nor should it)
-*
-*****************************************************************************/
-void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
- void *CallBackRef)
-{
- /*
- * Asserts validate the input arguments
- * CallBackRef not checked, no way to know what is valid
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(FuncPtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- InstancePtr->Handler = (XUartPs_Handler)FuncPtr;
- InstancePtr->CallBackRef = CallBackRef;
-}
-
-/****************************************************************************/
-/**
-*
-* This function is the interrupt handler for the driver.
-* It must be connected to an interrupt system by the application such that it
-* can be called when an interrupt occurs.
-*
-* @param InstancePtr contains a pointer to the driver instance
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XUartPs_InterruptHandler(XUartPs *InstancePtr)
-{
- u32 IsrStatus;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the interrupt ID register to determine which
- * interrupt is active
- */
- IsrStatus = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IMR_OFFSET);
-
- IsrStatus &= XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_ISR_OFFSET);
-
- /* Dispatch an appropriate handler. */
- if((IsrStatus & ((u32)XUARTPS_IXR_RXOVR | (u32)XUARTPS_IXR_RXEMPTY |
- (u32)XUARTPS_IXR_RXFULL)) != (u32)0) {
- /* Received data interrupt */
- ReceiveDataHandler(InstancePtr);
- }
-
- if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL))
- != (u32)0) {
- /* Transmit data interrupt */
- SendDataHandler(InstancePtr, IsrStatus);
- }
-
- /* XUARTPS_IXR_RBRK is applicable only for Zynq Ultrascale+ MP */
- if ((IsrStatus & ((u32)XUARTPS_IXR_OVER | (u32)XUARTPS_IXR_FRAMING |
- (u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK)) != (u32)0) {
- /* Received Error Status interrupt */
- ReceiveErrorHandler(InstancePtr, IsrStatus);
- }
-
- if((IsrStatus & ((u32)XUARTPS_IXR_TOUT)) != (u32)0) {
- /* Received Timeout interrupt */
- ReceiveTimeoutHandler(InstancePtr);
- }
-
- if((IsrStatus & ((u32)XUARTPS_IXR_DMS)) != (u32)0) {
- /* Modem status interrupt */
- ModemHandler(InstancePtr);
- }
-
- /* Clear the interrupt status. */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_ISR_OFFSET,
- IsrStatus);
-
-}
-
-/****************************************************************************/
-/*
-*
-* This function handles interrupts for receive errors which include
-* overrun errors, framing errors, parity errors, and the break interrupt.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus)
-{
- u32 EventData;
- u32 Event;
-
- InstancePtr->is_rxbs_error = 0;
-
- if ((InstancePtr->Platform == XPLAT_ZYNQ_ULTRA_MP) &&
- (IsrStatus & ((u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK
- | (u32)XUARTPS_IXR_FRAMING))) {
- InstancePtr->is_rxbs_error = 1;
- }
- /*
- * If there are bytes still to be received in the specified buffer
- * go ahead and receive them. Removing bytes from the RX FIFO will
- * clear the interrupt.
- */
-
- (void)XUartPs_ReceiveBuffer(InstancePtr);
-
- if (!(InstancePtr->is_rxbs_error)) {
- Event = XUARTPS_EVENT_RECV_ERROR;
- EventData = InstancePtr->ReceiveBuffer.RequestedBytes -
- InstancePtr->ReceiveBuffer.RemainingBytes;
-
- /*
- * Call the application handler to indicate that there is a receive
- * error or a break interrupt, if the application cares about the
- * error it call a function to get the last errors.
- */
- InstancePtr->Handler(InstancePtr->CallBackRef,
- Event,
- EventData);
- }
-}
-
-/****************************************************************************/
-/**
-*
-* This function handles the receive timeout interrupt. This interrupt occurs
-* whenever a number of bytes have been present in the RX FIFO and the receive
-* data line has been idle for at lease 4 or more character times, (the timeout
-* is set using XUartPs_SetrecvTimeout() function).
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-static void ReceiveTimeoutHandler(XUartPs *InstancePtr)
-{
- u32 Event;
-
- /*
- * If there are bytes still to be received in the specified buffer
- * go ahead and receive them. Removing bytes from the RX FIFO will
- * clear the interrupt.
- */
- if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
- (void)XUartPs_ReceiveBuffer(InstancePtr);
- }
-
- /*
- * If there are no more bytes to receive then indicate that this is
- * not a receive timeout but the end of the buffer reached, a timeout
- * normally occurs if # of bytes is not divisible by FIFO threshold,
- * don't rely on previous test of remaining bytes since receive
- * function updates it
- */
- if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
- Event = XUARTPS_EVENT_RECV_TOUT;
- } else {
- Event = XUARTPS_EVENT_RECV_DATA;
- }
-
- /*
- * Call the application handler to indicate that there is a receive
- * timeout or data event
- */
- InstancePtr->Handler(InstancePtr->CallBackRef, Event,
- InstancePtr->ReceiveBuffer.RequestedBytes -
- InstancePtr->ReceiveBuffer.RemainingBytes);
-
-}
-/****************************************************************************/
-/**
-*
-* This function handles the interrupt when data is in RX FIFO.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-static void ReceiveDataHandler(XUartPs *InstancePtr)
-{
- /*
- * If there are bytes still to be received in the specified buffer
- * go ahead and receive them. Removing bytes from the RX FIFO will
- * clear the interrupt.
- */
- if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
- (void)XUartPs_ReceiveBuffer(InstancePtr);
- }
-
- /* If the last byte of a message was received then call the application
- * handler, this code should not use an else from the previous check of
- * the number of bytes to receive because the call to receive the buffer
- * updates the bytes ramained
- */
- if (InstancePtr->ReceiveBuffer.RemainingBytes == (u32)0) {
- InstancePtr->Handler(InstancePtr->CallBackRef,
- XUARTPS_EVENT_RECV_DATA,
- (InstancePtr->ReceiveBuffer.RequestedBytes -
- InstancePtr->ReceiveBuffer.RemainingBytes));
- }
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function handles the interrupt when data has been sent, the transmit
-* FIFO is empty (transmitter holding register).
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-* @param IsrStatus is the register value for channel status register
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus)
-{
-
- /*
- * If there are not bytes to be sent from the specified buffer then disable
- * the transmit interrupt so it will stop interrupting as it interrupts
- * any time the FIFO is empty
- */
- if (InstancePtr->SendBuffer.RemainingBytes == (u32)0) {
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IDR_OFFSET,
- ((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL));
-
- /* Call the application handler to indicate the sending is done */
- InstancePtr->Handler(InstancePtr->CallBackRef,
- XUARTPS_EVENT_SENT_DATA,
- InstancePtr->SendBuffer.RequestedBytes -
- InstancePtr->SendBuffer.RemainingBytes);
- }
-
- /* If TX FIFO is empty, send more. */
- else if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY)) != (u32)0) {
- (void)XUartPs_SendBuffer(InstancePtr);
- }
- else {
- /* Else with dummy entry for MISRA-C Compliance.*/
- ;
- }
-}
-
-/****************************************************************************/
-/**
-*
-* This function handles modem interrupts. It does not do any processing
-* except to call the application handler to indicate a modem event.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-static void ModemHandler(XUartPs *InstancePtr)
-{
- u32 MsrRegister;
-
- /*
- * Read the modem status register so that the interrupt is acknowledged
- * and it can be passed to the callback handler with the event
- */
- MsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_MODEMSR_OFFSET);
-
- /*
- * Call the application handler to indicate the modem status changed,
- * passing the modem status and the event data in the call
- */
- InstancePtr->Handler(InstancePtr->CallBackRef,
- XUARTPS_EVENT_MODEM,
- MsrRegister);
-
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/30/417552555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/30/417552555243001d18b399c1eb9b3628
deleted file mode 100644
index ef843de..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/30/417552555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,94 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xtime_l.h
-*
-* @addtogroup a53_64_time_apis Cortex A53 64bit Mode Time Functions
-* xtime_l.h provides access to the 64-bit physical timer counter.
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 5.00 pkp 05/29/14 First release
-* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep
-* implementation
-* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
-* displaying same warnings multiple times. It fixes CR#1090562.
-*
-*
-*
-******************************************************************************/
-
-#ifndef XTIME_H /* prevent circular inclusions */
-#define XTIME_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *@cond nocomments
- */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xparameters.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-typedef u64 XTime;
-
-/************************** Constant Definitions *****************************/
-#if defined (versal)
-#if defined (SLEEP_TIMER_BASEADDR)
-#define COUNTS_PER_SECOND SLEEP_TIMER_FREQUENCY
-#else
-#define COUNTS_PER_SECOND XPAR_CPU_CORTEXA72_0_TIMESTAMP_CLK_FREQ
-#endif
-#define XIOU_SCNTRS_BASEADDR 0xFF140000U
-#define XIOU_SCNTRS_FREQ XPAR_CPU_CORTEXA72_0_TIMESTAMP_CLK_FREQ
-#else
-#if defined (SLEEP_TIMER_BASEADDR)
-#define COUNTS_PER_SECOND SLEEP_TIMER_FREQUENCY
-#else
-#define COUNTS_PER_SECOND XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ
-#endif
-#define XIOU_SCNTRS_BASEADDR 0xFF260000U
-#define XIOU_SCNTRS_FREQ XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ
-#endif
-#define XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET 0x00000000U
-#define XIOU_SCNTRS_FREQ_REG_OFFSET 0x00000020U
-#define XIOU_SCNTRS_CNT_CNTRL_REG_EN 0x00000001U
-#define XIOU_SCNTRS_CNT_CNTRL_REG_EN_MASK 0x00000001U
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void XTime_StartTimer(void);
-
-/**
- *@endcond
- */
-
-void XTime_SetTime(XTime Xtime_Global);
-void XTime_GetTime(XTime *Xtime_Global);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XTIME_H */
-/**
-* @} End of "addtogroup a53_64_time_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/30/5070f4575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/30/5070f4575243001d18b399c1eb9b3628
deleted file mode 100644
index 2e5cbd5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/30/5070f4575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,146 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xgpiops_hw.h
-* @addtogroup gpiops_v3_9
-* @{
-*
-* This header file contains the identifiers and basic driver functions (or
-* macros) that can be used to access the device. Other driver functions
-* are defined in xgpiops.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------
-* 1.00a sv 01/15/10 First Release
-* 1.02a hk 08/22/13 Added low level reset API function prototype and
-* related constant definitions
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/13/15 Corrected reset values of banks.
-* 3.5 sne 03/14/19 Added versal support.
-*
-*
-******************************************************************************/
-#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
-#define XGPIOPS_HW_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register offsets for the GPIO. Each register is 32 bits.
- * @{
- */
-#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /**< Mask and Data Register LSW, WO */
-#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /**< Mask and Data Register MSW, WO */
-#define XGPIOPS_DATA_OFFSET 0x00000040U /**< Data Register, RW */
-#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /**< Data Register - Input, RO */
-#define XGPIOPS_DIRM_OFFSET 0x00000204U /**< Direction Mode Register, RW */
-#define XGPIOPS_OUTEN_OFFSET 0x00000208U /**< Output Enable Register, RW */
-#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /**< Interrupt Mask Register, RO */
-#define XGPIOPS_INTEN_OFFSET 0x00000210U /**< Interrupt Enable Register, WO */
-#define XGPIOPS_INTDIS_OFFSET 0x00000214U /**< Interrupt Disable Register, WO*/
-#define XGPIOPS_INTSTS_OFFSET 0x00000218U /**< Interrupt Status Register, RO */
-#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /**< Interrupt Type Register, RW */
-#define XGPIOPS_INTPOL_OFFSET 0x00000220U /**< Interrupt Polarity Register, RW */
-#define XGPIOPS_INTANY_OFFSET 0x00000224U /**< Interrupt On Any Register, RW */
-/** @} */
-
-/** @name Register offsets for each Bank.
- * @{
- */
-#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /**< Data/Mask Registers offset */
-#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /**< Data Registers offset */
-#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /**< Registers offset */
-/** @} */
-
-/* For backwards compatibility */
-#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40 /**< Mask for backward support */
-
-/** @name Interrupt type reset values for each bank
- * @{
- */
-#ifdef XPAR_PSU_GPIO_0_BASEADDR
-#define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-#define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-#define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-#else
-#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /**< Resets specific to Zynq */
-#define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU /**< Resets specific to Zynq */
-#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU /**< Resets specific to Zynq */
-#endif
-
-#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /**< Reset common to both platforms */
-#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-/** @} */
-#define XGPIOPS_PS_GPIO_BASEADDR 0xFF0B0000U /**< Flag for Base Address for PS_GPIO in Versal */
-#define XGPIOPS_ZERO 0U /**< Flag for 0 Value */
-#define XGPIOPS_ONE 1U /**< Flag for 1 Value */
-#define XGPIOPS_TWO 2U /**< Flag for 2 Value */
-#define XGPIOPS_THREE 3U /**< Flag for 3 Value */
-#define XGPIOPS_FOUR 4U /**< Flag for 4 Value */
-#define XGPIOPS_SIX 6U /**< Flag for 6 Value */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* This macro reads the given register.
-*
-* @param BaseAddr is the base address of the device.
-* @param RegOffset is the register offset to be read.
-*
-* @return The 32-bit value of the register
-*
-* @note None.
-*
-*****************************************************************************/
-#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + (u32)(RegOffset))
-
-/****************************************************************************/
-/**
-*
-* This macro writes to the given register.
-*
-* @param BaseAddr is the base address of the device.
-* @param RegOffset is the offset of the register to be written.
-* @param Data is the 32-bit value to write to the register.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
-
-/************************** Function Prototypes ******************************/
-
-void XGpioPs_ResetHw(UINTPTR BaseAddress);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XGPIOPS_HW_H */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/30/e036ca585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/30/e036ca585243001d18b399c1eb9b3628
deleted file mode 100644
index ba7531d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/30/e036ca585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,143 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2017 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/*****************************************************************************/
-/**
-*
-* @file xil_sleeptimer.c
-*
-* This file provides the common helper routines for the sleep API's
-*
-*
-* MODIFICATION HISTORY :
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 6.6 srm 10/18/17 First Release.
-* 6.6 srm 04/20/18 Fixed compilation warning in Xil_SleepTTCCommon API
-* 7.0 mus 03/27/19 Updated XTime_StartTTCTimer to skip IOU slcr address
-* space access, if processor is nonsecure and IOU slcr
-* address space is secure. CR#1015725.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.0 pkp 05/29/14 First release
-* 5.5 pkp 04/15/16 Updated the Xil_DCacheInvalidate,
-* Xil_DCacheInvalidateLine and Xil_DCacheInvalidateRange
-* functions description for proper explanation
-* 6.2 pkp 01/22/17 Added support for EL1 non-secure
-* 6.2 asa 01/31/17 The existing Xil_DCacheDisable API first flushes the
-* D caches and then disables it. The problem with that is,
-* potentially there will be a small window after the cache
-* flush operation and before the we disable D caches where
-* we might have valid data in cache lines. In such a
-* scenario disabling the D cache can lead to unknown behavior.
-* The ideal solution to this is to use assembly code for
-* the complete API and avoid any memory accesses. But with
-* that we will end up having a huge amount on assembly code
-* which is not maintainable. Changes are done to use a mix
-* of assembly and C code. All local variables are put in
-* registers. Also function calls are avoided in the API to
-* avoid using stack memory.
-* These changes fix CR#966220.
-* 6.2 mus 02/13/17 The new api Xil_ConfigureL1Prefetch is added to disable pre-fetching/configure
-* the maximum number of outstanding data prefetches allowed in
-* L1 cache system.It fixes CR#967864.
-* 6.6 mus 02/27/18 Updated Xil_DCacheInvalidateRange and
-* Xil_ICacheInvalidateRange APIs to change the data type of
-* "cacheline" variable as "INTPTR", This change has been done
-* to avoid the truncation of upper DDR addresses to 32 bit.It
-* fixes CR#995581.
-* 6.6 mus 03/15/18 By default CPUACTLR_EL1 is accessible only from EL3, it
-* results into abort if accessed from EL1 non secure privilege
-* level. Updated Xil_ConfigureL1Prefetch function to access
-* CPUACTLR_EL1 only for EL3.
-* 6.8 mn 08/01/18 Optimize the Xil_DCacheInvalidateRange() function to remove
-* redundant operations
-* 6.8 asa 09/15/18 Fix bug in the Xil_DCacheInvalidateRange API introduced while
-* making optimizations in the previous patch. This change fixes
-* CR-1008926.
-* 7.0 mus 10/12/18 Updated Xil_DCacheInvalidateLine and Xil_DCacheInvalidateRange
-* APIs to replace IVAC instruction with CIVAC. So that, these
-* APIs will always do flush + invalidate in case of Cortexa53 as
-* well as Cortexa72 processor.
-* 7.1 mus 09/17/19 Xil_DCacheFlushRange and Xil_DCacheInvalidateRange are executing
-* same functionality (clean + validate). Removed
-* Xil_DCacheFlushRange function implementation and defined it as
-* macro. Xil_DCacheFlushRange macro points to the
-* Xil_DCacheInvalidateRange API to avoid code duplication.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xil_io.h"
-#include "xpseudo_asm.h"
-#include "xparameters.h"
-#include "xreg_cortexa53.h"
-#include "xil_exception.h"
-#include "bspconfig.h"
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-#define IRQ_FIQ_MASK 0xC0U /* Mask IRQ and FIQ interrupts in cpsr */
-
-/****************************************************************************/
-/**
-* @brief Enable the Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheEnable(void)
-{
- u32 CtrlReg;
-
- if (EL3 == 1) {
- CtrlReg = mfcp(SCTLR_EL3);
- } else if (EL1_NONSECURE == 1) {
- CtrlReg = mfcp(SCTLR_EL1);
- } else {
- CtrlReg = 0U;
- }
-
- /* enable caches only if they are disabled */
- if((CtrlReg & XREG_CONTROL_DCACHE_BIT) == 0X00000000U){
-
- /* invalidate the Data cache */
- Xil_DCacheInvalidate();
-
- CtrlReg |= XREG_CONTROL_DCACHE_BIT;
-
- if (EL3 == 1) {
- /* enable the Data cache for el3*/
- mtcp(SCTLR_EL3,CtrlReg);
- } else if (EL1_NONSECURE == 1) {
- /* enable the Data cache for el1*/
- mtcp(SCTLR_EL1,CtrlReg);
- }
- }
-}
-
-/****************************************************************************/
-/**
-* @brief Disable the Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheDisable(void)
-{
- register u32 CsidReg;
- register u32 C7Reg;
- register u32 LineSize;
- register u32 NumWays;
- register u32 Way;
- register u32 WayIndex;
- register u32 WayAdjust;
- register u32 Set;
- register u32 SetIndex;
- register u32 NumSet;
- register u32 CacheLevel;
-
- dsb();
- asm(
- "mov x0, #0\n\t"
-#if EL3==1
- "mrs x0, sctlr_el3 \n\t"
- "and w0, w0, #0xfffffffb\n\t"
- "msr sctlr_el3, x0\n\t"
-#elif EL1_NONSECURE==1
- "mrs x0, sctlr_el1 \n\t"
- "and w0, w0, #0xfffffffb\n\t"
- "msr sctlr_el1, x0\n\t"
-#endif
- "dsb sy\n\t"
- );
-
- /* Number of level of cache*/
- CacheLevel = 0U;
- /* Select cache level 0 and D cache in CSSR */
- mtcp(CSSELR_EL1,CacheLevel);
- isb();
-
- CsidReg = mfcp(CCSIDR_EL1);
-
- /* Get the cacheline size, way size, index size from csidr */
- LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
-
- /* Number of Ways */
- NumWays = (CsidReg & 0x00001FFFU) >> 3U;
- NumWays += 0x00000001U;
-
- /*Number of Set*/
- NumSet = (CsidReg >> 13U) & 0x00007FFFU;
- NumSet += 0x00000001U;
-
- WayAdjust = clz(NumWays) - (u32)0x0000001FU;
-
- Way = 0U;
- Set = 0U;
-
- /* Flush all the cachelines */
- for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set | CacheLevel;
- mtcpdc(CISW,C7Reg);
- Set += (0x00000001U << LineSize);
- }
- Set = 0U;
- Way += (0x00000001U << WayAdjust);
- }
-
- /* Wait for Flush to complete */
- dsb();
-
- /* Select cache level 1 and D cache in CSSR */
- CacheLevel += (0x00000001U << 1U);
- mtcp(CSSELR_EL1,CacheLevel);
- isb();
-
- CsidReg = mfcp(CCSIDR_EL1);
-
- /* Get the cacheline size, way size, index size from csidr */
- LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
-
- /* Number of Ways */
- NumWays = (CsidReg & 0x00001FFFU) >> 3U;
- NumWays += 0x00000001U;
-
- /* Number of Sets */
- NumSet = (CsidReg >> 13U) & 0x00007FFFU;
- NumSet += 0x00000001U;
-
- WayAdjust=clz(NumWays) - (u32)0x0000001FU;
-
- Way = 0U;
- Set = 0U;
-
- /* Flush all the cachelines */
- for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set | CacheLevel;
- mtcpdc(CISW,C7Reg);
- Set += (0x00000001U << LineSize);
- }
- Set=0U;
- Way += (0x00000001U<> 3U;
- NumWays += 0X00000001U;
-
- /*Number of Set*/
- NumSet = (CsidReg >> 13U) & 0x00007FFFU;
- NumSet += 0X00000001U;
-
- WayAdjust = clz(NumWays) - (u32)0x0000001FU;
-
- Way = 0U;
- Set = 0U;
-
- /* Invalidate all the cachelines */
- for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set | CacheLevel;
- mtcpdc(ISW,C7Reg);
- Set += (0x00000001U << LineSize);
- }
- Set = 0U;
- Way += (0x00000001U << WayAdjust);
- }
-
- /* Wait for invalidate to complete */
- dsb();
-
- /* Select cache level 1 and D cache in CSSR */
- CacheLevel += (0x00000001U<<1U) ;
- mtcp(CSSELR_EL1,CacheLevel);
- isb();
-
- CsidReg = mfcp(CCSIDR_EL1);
-
- /* Get the cacheline size, way size, index size from csidr */
- LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
-
- /* Number of Ways */
- NumWays = (CsidReg & 0x00001FFFU) >> 3U;
- NumWays += 0x00000001U;
-
- /* Number of Sets */
- NumSet = (CsidReg >> 13U) & 0x00007FFFU;
- NumSet += 0x00000001U;
-
- WayAdjust = clz(NumWays) - (u32)0x0000001FU;
-
- Way = 0U;
- Set = 0U;
-
- /* Invalidate all the cachelines */
- for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set | CacheLevel;
- mtcpdc(ISW,C7Reg);
- Set += (0x00000001U << LineSize);
- }
- Set = 0U;
- Way += (0x00000001U << WayAdjust);
- }
- /* Wait for invalidate to complete */
- dsb();
-
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate a Data cache line. The cacheline is cleaned and
-* invalidated.
-*
-* @param adr: 64bit address of the data to be flushed.
-*
-* @return None.
-*
-* @note In Cortex-A53, functionality to simply invalid the cachelines
-* is not present. Such operations are a problem for an environment
-* that supports virtualisation. It would allow one OS to invalidate
-* a line belonging to another OS. This could lead to the other OS
-* crashing because of the loss of essential data. Hence, such
-* operations are promoted to clean and invalidate which avoids such
-* corruption.
-*
-****************************************************************************/
-void Xil_DCacheInvalidateLine(INTPTR adr)
-{
-
- u32 currmask;
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- /* Select cache level 0 and D cache in CSSR */
- mtcp(CSSELR_EL1,0x0);
- mtcpdc(CIVAC,(adr & (~0x3F)));
- /* Wait for invalidate to complete */
- dsb();
- /* Select cache level 1 and D cache in CSSR */
- mtcp(CSSELR_EL1,0x2);
- mtcpdc(IVAC,(adr & (~0x3F)));
- /* Wait for invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the Data cache for the given address range.
-* The cachelines present in the adderss range are cleaned and
-* invalidated
-*
-* @param adr: 64bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-* @note In Cortex-A53, functionality to simply invalid the cachelines
-* is not present. Such operations are a problem for an environment
-* that supports virtualisation. It would allow one OS to invalidate
-* a line belonging to another OS. This could lead to the other OS
-* crashing because of the loss of essential data. Hence, such
-* operations are promoted to clean and invalidate which avoids such
-* corruption.
-*
-****************************************************************************/
-void Xil_DCacheInvalidateRange(INTPTR adr, INTPTR len)
-{
- const INTPTR cacheline = 64U;
- INTPTR end = adr + len;
- adr = adr & (~0x3F);
- u32 currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- if (len != 0U) {
- while (adr < end) {
- mtcpdc(CIVAC,adr);
- adr += cacheline;
- }
- }
- /* Wait for invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheFlush(void)
-{
- register u32 CsidReg, C7Reg;
- u32 LineSize, NumWays;
- u32 Way, WayIndex,WayAdjust, Set, SetIndex, NumSet, CacheLevel;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
-
- /* Number of level of cache*/
-
- CacheLevel = 0U;
- /* Select cache level 0 and D cache in CSSR */
- mtcp(CSSELR_EL1,CacheLevel);
- isb();
-
- CsidReg = mfcp(CCSIDR_EL1);
-
- /* Get the cacheline size, way size, index size from csidr */
- LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
-
- /* Number of Ways */
- NumWays = (CsidReg & 0x00001FFFU) >> 3U;
- NumWays += 0x00000001U;
-
- /*Number of Set*/
- NumSet = (CsidReg >> 13U) & 0x00007FFFU;
- NumSet += 0x00000001U;
-
- WayAdjust = clz(NumWays) - (u32)0x0000001FU;
-
- Way = 0U;
- Set = 0U;
-
- /* Flush all the cachelines */
- for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set | CacheLevel;
- mtcpdc(CISW,C7Reg);
- Set += (0x00000001U << LineSize);
- }
- Set = 0U;
- Way += (0x00000001U << WayAdjust);
- }
-
- /* Wait for Flush to complete */
- dsb();
-
- /* Select cache level 1 and D cache in CSSR */
- CacheLevel += (0x00000001U << 1U);
- mtcp(CSSELR_EL1,CacheLevel);
- isb();
-
- CsidReg = mfcp(CCSIDR_EL1);
-
- /* Get the cacheline size, way size, index size from csidr */
- LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
-
- /* Number of Ways */
- NumWays = (CsidReg & 0x00001FFFU) >> 3U;
- NumWays += 0x00000001U;
-
- /* Number of Sets */
- NumSet = (CsidReg >> 13U) & 0x00007FFFU;
- NumSet += 0x00000001U;
-
- WayAdjust=clz(NumWays) - (u32)0x0000001FU;
-
- Way = 0U;
- Set = 0U;
-
- /* Flush all the cachelines */
- for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set | CacheLevel;
- mtcpdc(CISW,C7Reg);
- Set += (0x00000001U << LineSize);
- }
- Set=0U;
- Way += (0x00000001U<
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.00 pkp 05/29/14 First release
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 5.00 pkp 08/29/14 First release
-* 5.04 pkp 02/19/16 XTime_StartTimer API is added to configure TTC3 timer
-* when present. XTime_GetTime is modified to give 64bit
-* output using timer overflow when TTC3 present.
-* XTime_SetTime is modified to configure TTC3 counter
-* value when present.
-* 5.04 pkp 03/11/16 XTime_StartTimer is modified to avoid enabling the
-* overflow interrupt and XTime_GetTime & XTime_SetTime
-* are modified to read and write TTC counter value
-* respectively
-* 5.04 pkp
-* 6.0 mus 08/11/16 Removed implementation of XTime_SetTime API, since
-* TTC counter value register is read only.
-* 6.6 srm 10/18/17 Removed XTime_StartTimer API and made XTime_GetTime,
-* XTime_SetTime applicable for all the instances of TTC
-* 7.2 mus 01/29/20 Updated XTime_GetTime to use CortexR5 PMU cycle
-* counter, in case sleep timer (ttc3/ttc2) is not
-* present in the HW design. It fixes CR#1051591.
-* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
-* displaying same warnings multiple times. It fixes CR#1090562.
-*
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "xtime_l.h"
-#include "xpseudo_asm.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xdebug.h"
-#include "xpm_counter.h"
-#include "xil_sleeptimer.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-#if defined (SLEEP_TIMER_BASEADDR)
-#pragma message ("For the sleep routines, TTC3/TTC2 is used")
-#elif !defined (DONT_USE_PMU_FOR_SLEEP_ROUTINES)
-#pragma message ("For the sleep routines, CortexR5 PMU cycle counter is used")
-#else
-#pragma message ("For the sleep routines, machine cycles are used")
-#endif
-
-/****************************************************************************/
-/**
-* @brief TTC Timer runs continuously and the time can not be set as
-* desired. This API doesn't contain anything. It is defined to have
-* uniformity across platforms.
-*
-* @param Xtime_Global: 32 bit value to be written to the timer counter
-* register.
-*
-* @return None.
-*
-* @note In multiprocessor environment reference time will reset/lost for
-* all processors, when this function called by any one processor.
-*
-****************************************************************************/
-void XTime_SetTime(XTime Xtime_Global)
-{
- (void) Xtime_Global;
-/*Timer cannot be set to desired value, so the API is left unimplemented*/
- xdbg_printf(XDBG_DEBUG_GENERAL,
- "XTime_SetTime:Timer cannot be set to desired value,so API is not implemented\n");
-}
-
-/****************************************************************************/
-/**
-* @brief Get the time from the timer counter register.
-*
-* @param Xtime_Global: Pointer to the 32 bit location to be updated with
-* the time current value of timer counter register.
-*
-* @return None.
-*
-****************************************************************************/
-void XTime_GetTime(XTime *Xtime_Global)
-{
-#if defined (SLEEP_TIMER_BASEADDR)
- *Xtime_Global = Xil_In32(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET);
-#elif !defined (DONT_USE_PMU_FOR_SLEEP_ROUTINES)
- #if defined (__GNUC__)
- *Xtime_Global = Xpm_ReadCycleCounterVal();
- #elif defined (__ICCARM__)
- Xpm_ReadCycleCounterVal(*Xtime_Global);
- #endif
-#endif
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/32/900fc8545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/32/900fc8545243001d18b399c1eb9b3628
deleted file mode 100644
index a3d5ae4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/32/900fc8545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,399 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xqspips_hw.h
-* @addtogroup qspips_v3_9
-* @{
-*
-* This header file contains the identifiers and basic HW access driver
-* functions (or macros) that can be used to access the device. Other driver
-* functions are defined in xqspips.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00 sdm 11/25/10 First release
-* 2.00a ka 07/25/12 Added a few register defines for CR 670297
-* and removed some defines of reserved fields for
-* CR 671468
-* Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
-* bit in Configuration register.
-* 2.01a sg 02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
-* which need write to clear. Removed Read zeros mask from
-* LQSPI Config register.
-* 2.03a hk 08/22/13 Added prototypes of API's for QSPI reset and
-* linear mode initialization for boot. Added related
-* constant definitions.
-* 3.1 hk 08/13/14 Changed definition of CR reset value masks to set/reset
-* required bits leaving reserved bits untouched. CR# 796813.
-* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
-* controller does not update FIFO status flags as expected
-* when thresholds are used.
-* 3.6 akm 03/28/19 Fixed memory leak issue while reading from qspi.(CR#1016357)
-*
-*
-*
-******************************************************************************/
-#ifndef XQSPIPS_HW_H /* prevent circular inclusions */
-#define XQSPIPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets from the base address of an QSPI device.
- * @{
- */
-#define XQSPIPS_CR_OFFSET 0x00 /**< Configuration Register */
-#define XQSPIPS_SR_OFFSET 0x04 /**< Interrupt Status */
-#define XQSPIPS_IER_OFFSET 0x08 /**< Interrupt Enable */
-#define XQSPIPS_IDR_OFFSET 0x0c /**< Interrupt Disable */
-#define XQSPIPS_IMR_OFFSET 0x10 /**< Interrupt Enabled Mask */
-#define XQSPIPS_ER_OFFSET 0x14 /**< Enable/Disable Register */
-#define XQSPIPS_DR_OFFSET 0x18 /**< Delay Register */
-#define XQSPIPS_TXD_00_OFFSET 0x1C /**< Transmit 4-byte inst/data */
-#define XQSPIPS_RXD_OFFSET 0x20 /**< Data Receive Register */
-#define XQSPIPS_SICR_OFFSET 0x24 /**< Slave Idle Count */
-#define XQSPIPS_TXWR_OFFSET 0x28 /**< Transmit FIFO Watermark */
-#define XQSPIPS_RXWR_OFFSET 0x2C /**< Receive FIFO Watermark */
-#define XQSPIPS_GPIO_OFFSET 0x30 /**< GPIO Register */
-#define XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38 /**< Loopback Delay Adjust Reg */
-#define XQSPIPS_TXD_01_OFFSET 0x80 /**< Transmit 1-byte inst */
-#define XQSPIPS_TXD_10_OFFSET 0x84 /**< Transmit 2-byte inst */
-#define XQSPIPS_TXD_11_OFFSET 0x88 /**< Transmit 3-byte inst */
-#define XQSPIPS_LQSPI_CR_OFFSET 0xA0 /**< Linear QSPI config register */
-#define XQSPIPS_LQSPI_SR_OFFSET 0xA4 /**< Linear QSPI status register */
-#define XQSPIPS_MOD_ID_OFFSET 0xFC /**< Module ID register */
-
-/* @} */
-
-/** @name Configuration Register
- *
- * This register contains various control bits that
- * affect the operation of the QSPI device. Read/Write.
- * @{
- */
-
-#define XQSPIPS_CR_IFMODE_MASK 0x80000000 /**< Flash mem interface mode */
-#define XQSPIPS_CR_ENDIAN_MASK 0x04000000 /**< Tx/Rx FIFO endianness */
-#define XQSPIPS_CR_MANSTRT_MASK 0x00010000 /**< Manual Transmission Start */
-#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start
- Enable */
-#define XQSPIPS_CR_SSFORCE_MASK 0x00004000 /**< Force Slave Select */
-#define XQSPIPS_CR_SSCTRL_MASK 0x00000400 /**< Slave Select Decode */
-#define XQSPIPS_CR_SSCTRL_SHIFT 10 /**< Slave Select Decode shift */
-#define XQSPIPS_CR_DATA_SZ_MASK 0x000000C0 /**< Size of word to be
- transferred */
-#define XQSPIPS_CR_PRESC_MASK 0x00000038 /**< Prescaler Setting */
-#define XQSPIPS_CR_PRESC_SHIFT 3 /**< Prescaler shift */
-#define XQSPIPS_CR_PRESC_MAXIMUM 0x07 /**< Prescaler maximum value */
-
-#define XQSPIPS_CR_CPHA_MASK 0x00000004 /**< Phase Configuration */
-#define XQSPIPS_CR_CPOL_MASK 0x00000002 /**< Polarity Configuration */
-
-#define XQSPIPS_CR_MSTREN_MASK 0x00000001 /**< Master Mode Enable */
-
-#define XQSPIPS_CR_HOLD_B_MASK 0x00080000 /**< HOLD_B Pin Drive Enable */
-
-#define XQSPIPS_CR_REF_CLK_MASK 0x00000100 /**< Ref clk bit - should be 0 */
-
-/* Deselect the Slave select line and set the transfer size to 32 at reset */
-#define XQSPIPS_CR_RESET_MASK_SET XQSPIPS_CR_IFMODE_MASK | \
- XQSPIPS_CR_SSCTRL_MASK | \
- XQSPIPS_CR_DATA_SZ_MASK | \
- XQSPIPS_CR_MSTREN_MASK | \
- XQSPIPS_CR_SSFORCE_MASK | \
- XQSPIPS_CR_HOLD_B_MASK
-#define XQSPIPS_CR_RESET_MASK_CLR XQSPIPS_CR_CPOL_MASK | \
- XQSPIPS_CR_CPHA_MASK | \
- XQSPIPS_CR_PRESC_MASK | \
- XQSPIPS_CR_MANSTRTEN_MASK | \
- XQSPIPS_CR_MANSTRT_MASK | \
- XQSPIPS_CR_ENDIAN_MASK | \
- XQSPIPS_CR_REF_CLK_MASK
-/* @} */
-
-
-/** @name QSPI Interrupt Registers
- *
- * QSPI Status Register
- *
- * This register holds the interrupt status flags for an QSPI device. Some
- * of the flags are level triggered, which means that they are set as long
- * as the interrupt condition exists. Other flags are edge triggered,
- * which means they are set once the interrupt condition occurs and remain
- * set until they are cleared by software. The interrupts are cleared by
- * writing a '1' to the interrupt bit position in the Status Register.
- * Read/Write.
- *
- * QSPI Interrupt Enable Register
- *
- * This register is used to enable chosen interrupts for an QSPI device.
- * Writing a '1' to a bit in this register sets the corresponding bit in the
- * QSPI Interrupt Mask register. Write only.
- *
- * QSPI Interrupt Disable Register
- *
- * This register is used to disable chosen interrupts for an QSPI device.
- * Writing a '1' to a bit in this register clears the corresponding bit in the
- * QSPI Interrupt Mask register. Write only.
- *
- * QSPI Interrupt Mask Register
- *
- * This register shows the enabled/disabled interrupts of an QSPI device.
- * Read only.
- *
- * All four registers have the same bit definitions. They are only defined once
- * for each of the Interrupt Enable Register, Interrupt Disable Register,
- * Interrupt Mask Register, and Channel Interrupt Status Register
- * @{
- */
-
-#define XQSPIPS_IXR_TXUF_MASK 0x00000040 /**< QSPI Tx FIFO Underflow */
-#define XQSPIPS_IXR_RXFULL_MASK 0x00000020 /**< QSPI Rx FIFO Full */
-#define XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010 /**< QSPI Rx FIFO Not Empty */
-#define XQSPIPS_IXR_TXFULL_MASK 0x00000008 /**< QSPI Tx FIFO Full */
-#define XQSPIPS_IXR_TXOW_MASK 0x00000004 /**< QSPI Tx FIFO Overwater */
-#define XQSPIPS_IXR_RXOVR_MASK 0x00000001 /**< QSPI Rx FIFO Overrun */
-#define XQSPIPS_IXR_DFLT_MASK 0x00000025 /**< QSPI default interrupts
- mask */
-#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041 /**< Interrupts which
- need write to clear */
-#define XQSPIPS_ISR_RESET_STATE 0x00000004 /**< Default to tx/rx empty */
-#define XQSPIPS_IXR_DISABLE_ALL 0x0000007D /**< Disable all interrupts */
-/* @} */
-
-
-/** @name Enable Register
- *
- * This register is used to enable or disable an QSPI device.
- * Read/Write
- * @{
- */
-#define XQSPIPS_ER_ENABLE_MASK 0x00000001 /**< QSPI Enable Bit Mask */
-/* @} */
-
-
-/** @name Delay Register
- *
- * This register is used to program timing delays in
- * slave mode. Read/Write
- * @{
- */
-#define XQSPIPS_DR_NSS_MASK 0xFF000000 /**< Delay to de-assert slave select
- between two words mask */
-#define XQSPIPS_DR_NSS_SHIFT 24 /**< Delay to de-assert slave select
- between two words shift */
-#define XQSPIPS_DR_BTWN_MASK 0x00FF0000 /**< Delay Between Transfers
- mask */
-#define XQSPIPS_DR_BTWN_SHIFT 16 /**< Delay Between Transfers shift */
-#define XQSPIPS_DR_AFTER_MASK 0x0000FF00 /**< Delay After Transfers mask */
-#define XQSPIPS_DR_AFTER_SHIFT 8 /**< Delay After Transfers shift */
-#define XQSPIPS_DR_INIT_MASK 0x000000FF /**< Delay Initially mask */
-/* @} */
-
-/** @name Slave Idle Count Registers
- *
- * This register defines the number of pclk cycles the slave waits for a the
- * QSPI clock to become stable in quiescent state before it can detect the start
- * of the next transfer in CPHA = 1 mode.
- * Read/Write
- *
- * @{
- */
-#define XQSPIPS_SICR_MASK 0x000000FF /**< Slave Idle Count Mask */
-/* @} */
-
-
-/** @name Transmit FIFO Watermark Register
- *
- * This register defines the watermark setting for the Transmit FIFO.
- *
- * @{
- */
-#define XQSPIPS_TXWR_MASK 0x0000003F /**< Transmit Watermark Mask */
-#define XQSPIPS_TXWR_RESET_VALUE 0x00000001 /**< Transmit Watermark
- * register reset value */
-
-/* @} */
-
-/** @name Receive FIFO Watermark Register
- *
- * This register defines the watermark setting for the Receive FIFO.
- *
- * @{
- */
-#define XQSPIPS_RXWR_MASK 0x0000003F /**< Receive Watermark Mask */
-#define XQSPIPS_RXWR_RESET_VALUE 0x00000001 /**< Receive Watermark
- * register reset value */
-
-/* @} */
-
-/** @name FIFO Depth
- *
- * This macro provides the depth of transmit FIFO and receive FIFO.
- *
- * @{
- */
-#define XQSPIPS_FIFO_DEPTH 63 /**< FIFO depth (words) */
-/* @} */
-
-
-/** @name Linear QSPI Configuration Register
- *
- * This register contains various control bits that
- * affect the operation of the Linear QSPI controller. Read/Write.
- *
- * @{
- */
-#define XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */
-#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */
-#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Separate memory bus */
-#define XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */
-#define XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */
-#define XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */
-#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O
- or quad I/O */
-#define XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700 /**< Number of dummy bytes
- between addr and return
- read data */
-#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */
-#define XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B /**< Default CR value */
-/* @} */
-
-/** @name Linear QSPI Status Register
- *
- * This register contains various status bits of the Linear QSPI controller.
- * Read/Write.
- *
- * @{
- */
-#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004 /**< AXI Data FSM Error
- received */
-#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002 /**< AXI write command
- received */
-/* @} */
-
-
-/** @name Loopback Delay Adjust Register
- *
- * This register contains various bit masks of Loopback Delay Adjust Register.
- *
- * @{
- */
-
-#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */
-
-/* @} */
-
-
-/** @name SLCR Register
- *
- * Register offsets from SLCR base address.
- *
- * @{
- */
-
-#define SLCR_LOCK 0x00000004 /**< SLCR Write Protection Lock */
-#define SLCR_UNLOCK 0x00000008 /**< SLCR Write Protection Unlock */
-#define LQSPI_RST_CTRL 0x00000230 /**< Quad SPI Software Reset Control */
-#define SLCR_LOCKSTA 0x0000000C /**< SLCR Write Protection status */
-
-/* @} */
-
-
-/** @name SLCR Register
- *
- * Bit Masks of above SLCR Registers .
- *
- * @{
- */
-
-#ifndef XPAR_XSLCR_0_BASEADDR
-#define XPAR_XSLCR_0_BASEADDR 0xF8000000
-#endif
-#define SLCR_LOCK_MASK 0x767B /**< Write Protection Lock mask*/
-#define SLCR_UNLOCK_MASK 0xDF0D /**< SLCR Write Protection Unlock */
-#define LQSPI_RST_CTRL_MASK 0x3 /**< Quad SPI Software Reset Control */
-
-/* @} */
-
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XQspiPs_In32 Xil_In32
-#define XQspiPs_Out32 Xil_Out32
-#define XQSPIPS_DUMMY_TX_DATA 0xFFFFFFFF
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-#define XQspiPs_ReadReg(BaseAddress, RegOffset) \
- XQspiPs_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u32 RegisterValue)
-*
-******************************************************************************/
-#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Functions implemented in xqspips_hw.c
- */
-void XQspiPs_ResetHw(u32 BaseAddress);
-void XQspiPs_LinearInit(u32 BaseAddress);
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/32/e17b8c565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/32/e17b8c565243001d18b399c1eb9b3628
deleted file mode 100644
index fccfe4d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/32/e17b8c565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,67 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/*****************************************************************************/
-/**
-*
-* @file microblaze_exception_handler.c
-*
-* This file contains exception handler registration routines for
-* the MicroBlaze processor.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Date Changes
-* ----- -------- -----------------------------------------------
-* 1.00b 06/24/04 First release
-*
-*
-******************************************************************************/
-
-
-/***************************** Include Files *********************************/
-#include "microblaze_exceptions_i.h"
-#include "microblaze_exceptions_g.h"
-
-#ifdef MICROBLAZE_EXCEPTIONS_ENABLED /* If exceptions are enabled in the processor */
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-extern MB_ExceptionVectorTableEntry MB_ExceptionVectorTable[];
-/****************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* Registers an exception handler for the MicroBlaze. The
-* argument provided in this call as the DataPtr is used as the argument
-* for the handler when it is called.
-*
-* @param ExceptionId is the id of the exception to register this handler
-* for.
-* @param Top level handler.
-* @param DataPtr is a reference to data that will be passed to the handler
-* when it gets called.
-* @return None.
-*
-****************************************************************************/
-void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr)
-{
- MB_ExceptionVectorTable[ExceptionId].Handler = Handler;
- MB_ExceptionVectorTable[ExceptionId].CallBackRef = DataPtr;
-}
-
-#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/33/21a96c545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/33/21a96c545243001d18b399c1eb9b3628
deleted file mode 100644
index 27a10ad..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/33/21a96c545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,425 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xuartps_hw.h
-* @addtogroup uartps_v3_11
-* @{
-*
-* This header file contains the hardware interface of an XUartPs device.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00 drg/jz 01/12/10 First Release
-* 1.03a sg 09/04/12 Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
-* and XUARTPS_IXR_TTRIG.
-* Modified the names of these defines
-* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
-* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
-* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
-* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
-* 1.05a hk 08/22/13 Added prototype for uart reset and related
-* constant definitions.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
-* 3.6 ms 02/16/18 Updates flow control mode offset value in
-* modem control register.
-*
-*
-* The xil_testcache.h file contains utility functions to test cache.
-*
-* @{
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 07/29/09 First release
-*
-*
-******************************************************************************/
-
-/**
-*@cond nocomments
-*/
-
-#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */
-#define XIL_TESTCACHE_H /* by using protection macros */
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern s32 Xil_TestDCacheRange(void);
-extern s32 Xil_TestDCacheAll(void);
-extern s32 Xil_TestICacheRange(void);
-extern s32 Xil_TestICacheAll(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
-
-/**
-* @} End of "addtogroup common_test_utils".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/33/a1a7ca545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/33/a1a7ca545243001d18b399c1eb9b3628
deleted file mode 100644
index c4b6b47..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/33/a1a7ca545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,74 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xqspips_sinit.c
-* @addtogroup qspips_v3_9
-* @{
-*
-* The implementation of the XQspiPs component's static initialization
-* functionality.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00 sdm 11/25/10 First release
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xqspips.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-extern XQspiPs_Config XQspiPs_ConfigTable[];
-
-/*****************************************************************************/
-/**
-*
-* Looks up the device configuration based on the unique device ID. A table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId contains the ID of the device to look up the
-* configuration for.
-*
-* @return
-*
-* A pointer to the configuration found or NULL if the specified device ID was
-* not found. See xqspips.h for the definition of XQspiPs_Config.
-*
-* @note None.
-*
-******************************************************************************/
-XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId)
-{
- XQspiPs_Config *CfgPtr = NULL;
- int Index;
-
- for (Index = 0; Index < XPAR_XQSPIPS_NUM_INSTANCES; Index++) {
- if (XQspiPs_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XQspiPs_ConfigTable[Index];
- break;
- }
- }
- return CfgPtr;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/33/c1be4d595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/33/c1be4d595243001d18b399c1eb9b3628
deleted file mode 100644
index f0c63a3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/33/c1be4d595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,30 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#include
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) sint32 _isatty(sint32 fd);
-}
-#endif
-
-/*
- * isatty -- returns 1 if connected to a terminal device,
- * returns 0 if not. Since we're hooked up to a
- * serial port, we'll say yes _AND return a 1.
- */
-__attribute__((weak)) sint32 isatty(sint32 fd)
-{
- (void)fd;
- return (1);
-}
-
-__attribute__((weak)) sint32 _isatty(sint32 fd)
-{
- (void)fd;
- return (1);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/33/c2eb9c555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/33/c2eb9c555243001d18b399c1eb9b3628
deleted file mode 100644
index bbf3bb8..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/33/c2eb9c555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,35 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include "xil_types.h"
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) char8 *sbrk (s32 nbytes);
-}
-#endif
-
-extern u8 _heap_start[];
-extern u8 _heap_end[];
-extern char8 HeapBase[];
-extern char8 HeapLimit[];
-
-
-
-__attribute__((weak)) char8 *sbrk (s32 nbytes)
-{
- char8 *base;
- static char8 *heap_ptr = HeapBase;
-
- base = heap_ptr;
- if((heap_ptr != NULL) && (heap_ptr + nbytes <= (char8 *)&HeapLimit + 1)) {
- heap_ptr += nbytes;
- return base;
- } else {
- errno = ENOMEM;
- return ((char8 *)-1);
- }
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/34/102cb0525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/34/102cb0525243001d18b399c1eb9b3628
deleted file mode 100644
index 77e1f3d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/34/102cb0525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,74 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache_vxworks.h
-*
-* Contains the cache related functions for VxWorks that is wrapped by
-* xil_cache.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 12/11/09 Initial release
-*
-*
-*
-* @note
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_CACHE_VXWORKS_H
-#define XIL_CACHE_VXWORKS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "vxWorks.h"
-#include "vxLib.h"
-#include "sysLibExtra.h"
-#include "cacheLib.h"
-
-#if (CPU_FAMILY==PPC)
-
-#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
-
-#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
-
-#define Xil_DCacheInvalidateRange(Addr, Len) \
- cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
-
-#define Xil_DCacheFlushRange(Addr, Len) \
- cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
-
-#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
-
-#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
-
-#define Xil_ICacheInvalidateRange(Addr, Len) \
- cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
-
-
-#else
-#error "Unknown processor / architecture. Must be PPC for VxWorks."
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
- *@endcond
- */
\ No newline at end of file
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/34/20a6b7525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/34/20a6b7525243001d18b399c1eb9b3628
deleted file mode 100644
index 853ef6b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/34/20a6b7525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,412 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_io.h
-*
-* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
-*
-* The xil_io.h file contains the interface for the general I/O component, which
-* encapsulates the Input/Output functions for the processors that do not
-* require any special I/O handling.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/29/14 First release
-* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
-* ARM processors
-* 7.20 har 01/03/20 Added Xil_SecureOut32 for avoiding blindwrite for
-* CR-1049218
-* 7.30 kpt 09/21/20 Moved Xil_EndianSwap16 and Xil_EndianSwap32 to
-* xil_io.h and made them as static inline
-* am 10/13/20 Changed the return type of Xil_SecureOut32 function
-* from u32 to int
-* 7.50 dp 02/12/21 Fix compilation error in Xil_EndianSwap32() that occur
-* when -Werror=conversion compiler flag is enabled
-* 7.5 mus 05/17/21 Update the functions with comments. It fixes CR#1067739.
-*
-*
-******************************************************************************/
-
-#ifndef XIL_IO_H /* prevent circular inclusions */
-#define XIL_IO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_printf.h"
-#include "xstatus.h"
-
-#if defined (__MICROBLAZE__)
-#include "mb_interface.h"
-#else
-#include "xpseudo_asm.h"
-#endif
-
-/************************** Function Prototypes ******************************/
-#ifdef ENABLE_SAFETY
-extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
-#endif
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#if defined __GNUC__
-#if defined (__MICROBLAZE__)
-# define INST_SYNC mbar(0)
-# define DATA_SYNC mbar(1)
-# else
-# define SYNCHRONIZE_IO dmb()
-# define INST_SYNC isb()
-# define DATA_SYNC dsb()
-# endif
-#else
-# define SYNCHRONIZE_IO
-# define INST_SYNC
-# define DATA_SYNC
-# define INST_SYNC
-# define DATA_SYNC
-#endif
-
-#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
-#define INLINE inline
-#else
-#define INLINE __inline
-#endif
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading
-* from the specified address and returning the 8 bit Value read from
-* that address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 8 bit Value read from the specified input address.
-
-*
-******************************************************************************/
-static INLINE u8 Xil_In8(UINTPTR Addr)
-{
- return *(volatile u8 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading from
-* the specified address and returning the 16 bit Value read from that
-* address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 16 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u16 Xil_In16(UINTPTR Addr)
-{
- return *(volatile u16 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by
-* reading from the specified address and returning the 32 bit Value
-* read from that address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 32 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u32 Xil_In32(UINTPTR Addr)
-{
- return *(volatile u32 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading the
-* 64 bit Value read from that address.
-*
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 64 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u64 Xil_In64(UINTPTR Addr)
-{
- return *(volatile u64 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for an memory location by
-* writing the 8 bit Value to the the specified address.
-*
-* @param Addr: contains the address to perform the output operation
-* @param Value: contains the 8 bit Value to be written at the specified
-* address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
-{
- /* write 8 bit value to specified address */
- volatile u8 *LocalAddr = (volatile u8 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 16 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains the Value to be written at the specified address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
-{
- /* write 16 bit value to specified address */
- volatile u16 *LocalAddr = (volatile u16 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 32 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains the 32 bit Value to be written at the specified
-* address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
-{
- /* write 32 bit value to specified address */
-#ifndef ENABLE_SAFETY
- volatile u32 *LocalAddr = (volatile u32 *)Addr;
- *LocalAddr = Value;
-#else
- XStl_RegUpdate(Addr, Value);
-#endif
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 64 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains 64 bit Value to be written at the specified address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
-{
- /* write 64 bit value to specified address */
- volatile u64 *LocalAddr = (volatile u64 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
- *
- * @brief Performs an output operation for a memory location by writing the
- * 32 bit Value to the the specified address and then reading it
- * back to verify the value written in the register.
- *
- * @param Addr contains the address to perform the output operation
- * @param Value contains 32 bit Value to be written at the specified address
- *
- * @return Returns Status
- * - XST_SUCCESS on success
- * - XST_FAILURE on failure
- *
- *****************************************************************************/
-static INLINE int Xil_SecureOut32(UINTPTR Addr, u32 Value)
-{
- int Status = XST_FAILURE;
- u32 ReadReg;
- u32 ReadRegTemp;
-
- /* writing 32 bit value to specified address */
- Xil_Out32(Addr, Value);
-
- /* verify value written to specified address with multiple reads */
- ReadReg = Xil_In32(Addr);
- ReadRegTemp = Xil_In32(Addr);
-
- if( (ReadReg == Value) && (ReadRegTemp == Value) ) {
- Status = XST_SUCCESS;
- }
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a 16-bit endian conversion.
-*
-* @param Data: 16 bit value to be converted
-*
-* @return 16 bit Data with converted endianness
-*
-******************************************************************************/
-static INLINE __attribute__((always_inline)) u16 Xil_EndianSwap16(u16 Data)
-{
- return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a 32-bit endian conversion.
-*
-* @param Data: 32 bit value to be converted
-*
-* @return 32 bit data with converted endianness
-*
-******************************************************************************/
-static INLINE __attribute__((always_inline)) u32 Xil_EndianSwap32(u32 Data)
-{
- u16 LoWord;
- u16 HiWord;
-
- /* get each of the half words from the 32 bit word */
-
- LoWord = (u16) (Data & 0x0000FFFFU);
- HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
-
- /* byte swap each of the 16 bit half words */
-
- LoWord = (u16)(((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
- HiWord = (u16)(((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
-
- /* swap the half words before returning the value */
-
- return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-# define Xil_In16LE Xil_In16
-# define Xil_In32LE Xil_In32
-# define Xil_Out16LE Xil_Out16
-# define Xil_Out32LE Xil_Out32
-# define Xil_Htons Xil_EndianSwap16
-# define Xil_Htonl Xil_EndianSwap32
-# define Xil_Ntohs Xil_EndianSwap16
-# define Xil_Ntohl Xil_EndianSwap32
-# else
-# define Xil_In16BE Xil_In16
-# define Xil_In32BE Xil_In32
-# define Xil_Out16BE Xil_Out16
-# define Xil_Out32BE Xil_Out32
-# define Xil_Htons(Data) (Data)
-# define Xil_Htonl(Data) (Data)
-# define Xil_Ntohs(Data) (Data)
-# define Xil_Ntohl(Data) (Data)
-#endif
-#else
-# define Xil_In16LE Xil_In16
-# define Xil_In32LE Xil_In32
-# define Xil_Out16LE Xil_Out16
-# define Xil_Out32LE Xil_Out32
-# define Xil_Htons Xil_EndianSwap16
-# define Xil_Htonl Xil_EndianSwap32
-# define Xil_Ntohs Xil_EndianSwap16
-# define Xil_Ntohl Xil_EndianSwap32
-#endif
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE u16 Xil_In16BE(UINTPTR Addr)
-#else
-static INLINE u16 Xil_In16LE(UINTPTR Addr)
-#endif
-#else
-static INLINE u16 Xil_In16BE(UINTPTR Addr)
-#endif
-{
- u16 value = Xil_In16(Addr);
- return Xil_EndianSwap16(value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE u32 Xil_In32BE(UINTPTR Addr)
-#else
-static INLINE u32 Xil_In32LE(UINTPTR Addr)
-#endif
-#else
-static INLINE u32 Xil_In32BE(UINTPTR Addr)
-#endif
-{
- u32 value = Xil_In32(Addr);
- return Xil_EndianSwap32(value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
-#else
-static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
-#endif
-#else
-static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
-#endif
-{
- Value = Xil_EndianSwap16(Value);
- Xil_Out16(Addr, Value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
-#else
-static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
-#endif
-#else
-static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
-#endif
-{
- Value = Xil_EndianSwap32(Value);
- Xil_Out32(Addr, Value);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_io_interfacing_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/34/310579545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/34/310579545243001d18b399c1eb9b3628
deleted file mode 100644
index eb496ea..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/34/310579545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,39 +0,0 @@
-DRIVER_LIB_VERSION = 1.0
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I$(INCLUDEDIR)
-
-SRCFILES:=$(wildcard *.c)
-
-OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
-
-libs: $(OBJECTS)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf ${DEPFILES}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/34/31569e565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/34/31569e565243001d18b399c1eb9b3628
deleted file mode 100644
index 472cee4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/34/31569e565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,54 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2008 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-* microblaze_invalidate_cache_ext_range (unsigned int cacheaddr, unsigned int len)
-*
-*Invalidate an L2 cache range
-*
-*Parameters:
-* 'cacheaddr' - address in the L2 cache where invalidation begins
-* 'len ' - length (in bytes) worth of Dcache to be invalidated
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-#include "microblaze_instructions.h"
-
-#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
-
- .text
- .globl microblaze_invalidate_cache_ext_range
- .ent microblaze_invalidate_cache_ext_range
- .align 2
-
-microblaze_invalidate_cache_ext_range:
-#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
- beqi r6, Loop_done
-
- ADD r6, r5, r6
- ADDIK r6, r6, -1
-
- ANDI r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
- ANDI r5, r5, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
-
- RSUBK r6, r5, r6
-
-Loop_start:
- wdc.ext.clear r5, r6
-#if defined (__arch64__ )
- addlik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
- beagei r6, Loop_start
-#else
- bneid r6, Loop_start
- addik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
-#endif
-
-Loop_done:
-#endif
- rtsd r15, 8
- nop
-
- .end microblaze_invalidate_cache_ext_range
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/34/706a1a545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/34/706a1a545243001d18b399c1eb9b3628
deleted file mode 100644
index 08af00b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/34/706a1a545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,93 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/*****************************************************************************/
-/**
-* @file sleep.h
-*
-* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep
-* related APIs.
-*
-*
-* MODIFICATION HISTORY :
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 6.6 srm 11/02/17 Added processor specific sleep routines
-* function prototypes.
-*
-*
-*
-******************************************************************************/
-
-#ifndef SLEEP_H
-#define SLEEP_H
-
-#include "xil_types.h"
-#include "xil_io.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*****************************************************************************/
-/**
-*
-* This macro polls an address periodically until a condition is met or till the
-* timeout occurs.
-* The minimum timeout for calling this macro is 100us. If the timeout is less
-* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
-* If the timeout is not a multiple of 100us, it waits for a timeout of
-* the next usec value which is a multiple of 100us.
-*
-* @param IO_func - accessor function to read the register contents.
-* Depends on the register width.
-* @param ADDR - Address to be polled
-* @param VALUE - variable to read the value
-* @param COND - Condition to checked (usually involves VALUE)
-* @param TIMEOUT_US - timeout in micro seconds
-*
-* @return 0 - when the condition is met
-* -1 - when the condition is not met till the timeout period
-*
-* @note none
-*
-*****************************************************************************/
-#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
- ( { \
- u64 timeout = TIMEOUT_US/100; \
- if(TIMEOUT_US%100!=0) \
- timeout++; \
- for(;;) { \
- VALUE = IO_func(ADDR); \
- if(COND) \
- break; \
- else { \
- usleep(100); \
- timeout--; \
- if(timeout==0) \
- break; \
- } \
- } \
- (timeout>0) ? 0 : -1; \
- } )
-
-void usleep(unsigned long useconds);
-void sleep(unsigned int seconds);
-int usleep_R5(unsigned long useconds);
-unsigned sleep_R5(unsigned int seconds);
-int usleep_MB(unsigned long useconds);
-unsigned sleep_MB(unsigned int seconds);
-int usleep_A53(unsigned long useconds);
-unsigned sleep_A53(unsigned int seconds);
-int usleep_A9(unsigned long useconds);
-unsigned sleep_A9(unsigned int seconds);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/34/a1927d575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/34/a1927d575243001d18b399c1eb9b3628
deleted file mode 100644
index a146f83..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/34/a1927d575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,387 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_exception.h
-*
-* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
-* For exception related functions that can be used across all Xilinx supported
-* processors, please use xil_exception.h.
-*
-* @addtogroup arm_exception_apis ARM Processor Exception Handling
-* @{
-* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
-* utilized for enabling/disabling IRQ, registering/removing handler for
-* exceptions or initializing exception vector table with null handler.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
-* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler.
-* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.
-* 7.0 mus 01/03/19 Tweak Xil_ExceptionEnableMask and
-* Xil_ExceptionDisableMask macros to support legacy
-* examples for Cortexa72 EL3 exception level.
-* 7.3 mus 04/15/20 Added Xil_EnableNestedInterrupts and
-* Xil_DisableNestedInterrupts macros for ARMv8.
-* For Cortexa72, these macro's would not be supported
-* at EL3, as Cortexa72 is using GIC-500(GICv3), which
-* triggeres only FIQ at EL3. Fix for CR#1062506
-# 7.6 mus 09/17/21 Updated flag checking to fix warning reported with
-# -Wundef compiler option CR#1110261
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
-#define XIL_EXCEPTION_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#include "bspconfig.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions ****************************/
-
-#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
-#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
-#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
-
-#define XIL_EXCEPTION_ID_FIRST 0U
-#if defined (__aarch64__)
-#define XIL_EXCEPTION_ID_SYNC_INT 1U
-#define XIL_EXCEPTION_ID_IRQ_INT 2U
-#define XIL_EXCEPTION_ID_FIQ_INT 3U
-#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
-#define XIL_EXCEPTION_ID_LAST 5U
-#else
-#define XIL_EXCEPTION_ID_RESET 0U
-#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
-#define XIL_EXCEPTION_ID_SWI_INT 2U
-#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
-#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
-#define XIL_EXCEPTION_ID_IRQ_INT 5U
-#define XIL_EXCEPTION_ID_FIQ_INT 6U
-#define XIL_EXCEPTION_ID_LAST 6U
-#endif
-
-/*
- * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
- */
-#if defined (versal) && !defined(ARMR5) && EL3
-#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_FIQ_INT
-#else
-#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
-#endif
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef is the exception handler function.
- */
-typedef void (*Xil_ExceptionHandler)(void *data);
-typedef void (*Xil_InterruptHandler)(void *data);
-
-/**
-*@endcond
-*/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* @brief Enable Exceptions.
-*
-* @param Mask: Value for enabling the exceptions.
-*
-* @return None.
-*
-* @note If bit is 0, exception is enabled.
-* C-Style signature: void Xil_ExceptionEnableMask(Mask)
-*
-******************************************************************************/
-#if defined (versal) && !defined(ARMR5) && EL3
-/*
- * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
- * only FIQ at EL3. Hence, tweaking this macro to always enable FIQ
- * ignoring argument passed by user.
- */
-#define Xil_ExceptionEnableMask(Mask) \
- mtcpsr(mfcpsr() & ~ ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
-#elif defined (__GNUC__) || defined (__ICCARM__)
-#define Xil_ExceptionEnableMask(Mask) \
- mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
-#else
-#define Xil_ExceptionEnableMask(Mask) \
- { \
- register u32 Reg __asm("cpsr"); \
- mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
- }
-#endif
-/****************************************************************************/
-/**
-* @brief Enable the IRQ exception.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-#if defined (versal) && !defined(ARMR5) && EL3
-#define Xil_ExceptionEnable() \
- Xil_ExceptionEnableMask(XIL_EXCEPTION_FIQ)
-#else
-#define Xil_ExceptionEnable() \
- Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
-#endif
-
-/****************************************************************************/
-/**
-* @brief Disable Exceptions.
-*
-* @param Mask: Value for disabling the exceptions.
-*
-* @return None.
-*
-* @note If bit is 1, exception is disabled.
-* C-Style signature: Xil_ExceptionDisableMask(Mask)
-*
-******************************************************************************/
-#if defined (versal) && !defined(ARMR5) && EL3
-/*
- * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
- * only FIQ at EL3. Hence, tweaking this macro to always disable FIQ
- * ignoring argument passed by user.
- */
-#define Xil_ExceptionDisableMask(Mask) \
- mtcpsr(mfcpsr() | ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
-#elif defined (__GNUC__) || defined (__ICCARM__)
-#define Xil_ExceptionDisableMask(Mask) \
- mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
-#else
-#define Xil_ExceptionDisableMask(Mask) \
- { \
- register u32 Reg __asm("cpsr"); \
- mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
- }
-#endif
-/****************************************************************************/
-/**
-* Disable the IRQ exception.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_ExceptionDisable() \
- Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
-
-#if ( defined (PLATFORM_ZYNQMP) && defined (EL3) && (EL3==1) )
-/****************************************************************************/
-/**
-* @brief Enable nested interrupts by clearing the I bit in DAIF.This
-* macro is defined for Cortex-A53 64 bit mode BSP configured to run
-* at EL3.. However,it is not defined for Versal Cortex-A72 BSP
-* configured to run at EL3. Reason is, Cortex-A72 is coupled
-* with GIC-500(GICv3 specifications) and it triggers only FIQ at EL3.
-*
-* @return None.
-*
-* @note This macro is supposed to be used from interrupt handlers. In the
-* interrupt handler the interrupts are disabled by default (I bit
-* is set as 1). To allow nesting of interrupts, this macro should be
-* used. It clears the I bit. Once that bit is cleared and provided the
-* preemption of interrupt conditions are met in the GIC, nesting of
-* interrupts will start happening.
-* Caution: This macro must be used with caution. Before calling this
-* macro, the user must ensure that the source of the current IRQ
-* is appropriately cleared. Otherwise, as soon as we clear the I
-* bit, there can be an infinite loop of interrupts with an
-* eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
- __asm__ __volatile__ ("mrs X1, ELR_EL3"); \
- __asm__ __volatile__ ("mrs X2, SPSR_EL3"); \
- __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-/****************************************************************************/
-/**
-* @brief Disable the nested interrupts by setting the I bit in DAIF. This
-* macro is defined for Cortex-A53 64 bit mode BSP configured to run
-* at EL3.
-*
-* @return None.
-*
-* @note This macro is meant to be called in the interrupt service routines.
-* This macro cannot be used independently. It can only be used when
-* nesting of interrupts have been enabled by using the macro
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-* point. The user then must call this macro before exiting the interrupt
-* service routine. This macro puts the ARM back in IRQ mode and
-* hence sets back the I bit.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
- __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \
- __asm__ __volatile__ ("msr ELR_EL3, X1"); \
- __asm__ __volatile__ ("msr SPSR_EL3, X2"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-#elif (defined (EL1_NONSECURE) && (EL1_NONSECURE==1))
-/****************************************************************************/
-/**
-* @brief Enable nested interrupts by clearing the I bit in DAIF.This
-* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit
-* BSP configured to run at EL1 NON SECURE
-*
-* @return None.
-*
-* @note This macro is supposed to be used from interrupt handlers. In the
-* interrupt handler the interrupts are disabled by default (I bit
-* is set as 1). To allow nesting of interrupts, this macro should be
-* used. It clears the I bit. Once that bit is cleared and provided the
-* preemption of interrupt conditions are met in the GIC, nesting of
-* interrupts will start happening.
-* Caution: This macro must be used with caution. Before calling this
-* macro, the user must ensure that the source of the current IRQ
-* is appropriately cleared. Otherwise, as soon as we clear the I
-* bit, there can be an infinite loop of interrupts with an
-* eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
- __asm__ __volatile__ ("mrs X1, ELR_EL1"); \
- __asm__ __volatile__ ("mrs X2, SPSR_EL1"); \
- __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-/****************************************************************************/
-/**
-* @brief Disable the nested interrupts by setting the I bit in DAIF. This
-* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit
-* BSP configured to run at EL1 NON SECURE
-*
-* @return None.
-*
-* @note This macro is meant to be called in the interrupt service routines.
-* This macro cannot be used independently. It can only be used when
-* nesting of interrupts have been enabled by using the macro
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-* point. The user then must call this macro before exiting the interrupt
-* service routine. This macro puts the ARM back in IRQ mode and
-* hence sets back the I bit.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
- __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \
- __asm__ __volatile__ ("msr ELR_EL1, X1"); \
- __asm__ __volatile__ ("msr SPSR_EL1, X2"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-#elif (!defined (__aarch64__) && !defined (ARMA53_32))
-/****************************************************************************/
-/**
-* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This
-* API is defined for cortex-a9 and cortex-r5.
-*
-* @return None.
-*
-* @note This macro is supposed to be used from interrupt handlers. In the
-* interrupt handler the interrupts are disabled by default (I and F
-* are 1). To allow nesting of interrupts, this macro should be
-* used. It clears the I and F bits by changing the ARM mode to
-* system mode. Once these bits are cleared and provided the
-* preemption of interrupt conditions are met in the GIC, nesting of
-* interrupts will start happening.
-* Caution: This macro must be used with caution. Before calling this
-* macro, the user must ensure that the source of the current IRQ
-* is appropriately cleared. Otherwise, as soon as we clear the I and
-* F bits, there can be an infinite loop of interrupts with an
-* eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
- __asm__ __volatile__ ("stmfd sp!, {lr}"); \
- __asm__ __volatile__ ("mrs lr, spsr"); \
- __asm__ __volatile__ ("stmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
- __asm__ __volatile__ ("stmfd sp!, {lr}");
-/****************************************************************************/
-/**
-* @brief Disable the nested interrupts by setting the I and F bits. This API
-* is defined for cortex-a9 and cortex-r5.
-*
-* @return None.
-*
-* @note This macro is meant to be called in the interrupt service routines.
-* This macro cannot be used independently. It can only be used when
-* nesting of interrupts have been enabled by using the macro
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-* point. The user then must call this macro before exiting the interrupt
-* service routine. This macro puts the ARM back in IRQ/FIQ mode and
-* hence sets back the I and F bits.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr cpsr_c, #0x92"); \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr spsr_cxsf, lr"); \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
-
-#endif
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler Handler,
- void *Data);
-
-extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
-extern void Xil_GetExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler *Handler, void **Data);
-
-extern void Xil_ExceptionInit(void);
-#if defined (__aarch64__)
-void Xil_SyncAbortHandler(void *CallBackRef);
-void Xil_SErrorAbortHandler(void *CallBackRef);
-#else
-extern void Xil_DataAbortHandler(void *CallBackRef);
-extern void Xil_PrefetchAbortHandler(void *CallBackRef);
-extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
-#endif
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_EXCEPTION_H */
-/**
-* @} End of "addtogroup arm_exception_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/34/b021d2545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/34/b021d2545243001d18b399c1eb9b3628
deleted file mode 100644
index d6b7040..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/34/b021d2545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,949 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xscugic_hw.c
-* @addtogroup scugic_v4_6
-* @{
-*
-* This file contains low-level driver functions that can be used to access the
-* device. The user should refer to the hardware device specification for more
-* details of the device operation.
-* These routines are used when the user does not want to create an instance of
-* XScuGic structure but still wants to use the ScuGic device. Hence the
-* routines provided here take device id or scugic base address as arguments.
-* Separate static versions of DistInit and CPUInit are provided to implement
-* the low level driver routines.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.01a sdm 07/18/11 First release
-* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
-* 702687).
-* Added support to direct interrupts to the appropriate
-* CPU. Earlier interrupts were directed to CPU1
-* (hard coded). Now depending upon the CPU selected by
-* the user (xparameters.h), interrupts will be directed
-* to the relevant CPU.This fixes CR 699688.
-* 1.04a hk 05/04/13 Fix for CR#705621. Moved functions
-* XScuGic_SetPriTrigTypeByDistAddr and
-* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.c
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.6 kvn 02/17/17 Add support for changing GIC CPU master at run time.
-* kvn 02/28/17 Make the CpuId as static variable and Added new
-* XScugiC_GetCpuId to access CpuId.
-* 3.9 mus 02/21/18 Added new API's
-* XScuGic_InterruptUnmapFromCpuByDistAddr and
-* XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
-* API's can be used by applications to unmap
-* specific/all interrupts from target CPU. It fixes
-* CR#992490.
-* 3.10 mus 07/17/18 Updated XScuGic_DeviceInterruptHandler to fix array
-* overrun reported by coverity tool. It fixes
-* CR#1006344.
-* 3.10 mus 07/17/18 Updated file to fix the various coding style issues
-* reported by checkpatch. It fixes CR#1006344.
-* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
-* It fixes CR#1007753
-* 3.10 mus 09/19/18 Update documentation for XScuGic_RegisterHandler to
-* fix doxygen warnings.
-* 4.1 asa 03/30/19 Made changes not to direct each interrupt to all
-* available CPUs by default. This was breaking AMP
-* behavior. Instead every time an interrupt enable
-* request is received, the interrupt was mapped to
-* the respective CPU. There were several other changes
-* made to implement this including adding APIs:
-* XScuGic_InterruptMapFromCpuByDistAddr,
-* XScuGic_EnableIntr, and XScuGic_DisableIntr.
-* This set of changes was to fix CR-1024716.
-* 4.1 mus 06/12/19 Updated existing low level API's to support GIC500. It
-* fixes CR#1033401.
-* 4.3 mus 05/11/20 Added assert checks in XScuGic_EnableIntr and
-* XScuGic_DisableIntr API. It fixes CR#1063034.
-* 4.5 asa 03/07/21 Added spinlock protection for critical sections in the
-* code. The sections are critical when applications
-* running on separate CPUs (R5s or A9s) try to update
-* the same register. The spinlock mechanism used here
-* used exclusive load and store instructions. To ensure
-* that legacy behavior is not broken, unless someone
-* enables spinlocks explicitely in their applications
-* the existing flow will remain unchanged. On how to
-* enable spinlocks, please refer to the documentations
-* at: lib/bsp/standalone/src/arm/common/gcc/xil_spinlock.c
-* 4.6 sk 08/05/21 Fix Scugic Misrac violations.
-* 4.7 sk 09/14/21 Fix gcc compiler warnings for A72 processor.
-*
-*
-******************************************************************************/
-
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xscugic.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-static void DistInit(const XScuGic_Config *Config);
-#if !defined (GICv3)
-static void CPUInit(const XScuGic_Config *Config);
-#endif
-static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress);
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* DistInit initializes the distributor of the GIC. The
-* initialization entails:
-*
-* - Write the trigger mode, priority and target CPU
-* - All interrupt sources are disabled
-* - Enable the distributor
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-* @param CpuID is the Cpu ID to be initialized.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-static void DistInit(const XScuGic_Config *Config)
-{
- u32 Int_Id;
-
-#if (defined (USE_AMP) && (USE_AMP==1))
- #warning "Building GIC for AMP"
-
- /*
- * The distributor should not be initialized by FreeRTOS in the case of
- * AMP -- it is assumed that Linux is the master of this device in that
- * case.
- */
- return;
-#endif
-
-#if defined (GICv3)
- u32 Temp;
- u32 Waker_State;
-
- Waker_State = XScuGic_ReadReg((Config->DistBaseAddress) +
- XSCUGIC_RDIST_OFFSET,XSCUGIC_RDIST_WAKER_OFFSET);
- XScuGic_WriteReg((Config->DistBaseAddress) +
- XSCUGIC_RDIST_OFFSET,XSCUGIC_RDIST_WAKER_OFFSET,
- Waker_State & (~ XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK));
- /* Enable system reg interface through ICC_SRE_EL1 */
-#if EL3
- XScuGic_Enable_SystemReg_CPU_Interface_EL3();
-#endif
- XScuGic_Enable_SystemReg_CPU_Interface_EL1();
- isb();
-
- Temp = XScuGic_ReadReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET);
- Temp |= (XSCUGIC500_DCTLR_ARE_NS_ENABLE | XSCUGIC500_DCTLR_ARE_S_ENABLE);
- Temp &= ~(XSCUGIC_EN_INT_MASK);
- XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, Temp);
-#else
- XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, 0U);
-#endif
-
- /*
- * Set the security domains in the int_security registers for non-secure
- * interrupts. All are secure, so leave at the default. Set to 1 for
- * non-secure interrupts.
- */
-
-
- /*
- * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
- */
-
- /*
- * 1. The trigger mode in the int_config register
- * Only write to the SPI interrupts, so start at 32
- */
- for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
- Int_Id = Int_Id+16U) {
- /*
- * Each INT_ID uses two bits, or 16 INT_ID per register
- * Set them all to be level sensitive, active HIGH.
- */
- XScuGic_WriteReg(Config->DistBaseAddress,
- XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), 0U);
- }
-
-
-#define DEFAULT_PRIORITY 0xa0a0a0a0U
- for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
- Int_Id = Int_Id+4U) {
- /*
- * 2. The priority using int the priority_level register
- * The priority_level and spi_target registers use one byte per
- * INT_ID.
- * Write a default value that can be changed elsewhere.
- */
- XScuGic_WriteReg(Config->DistBaseAddress,
- XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
- DEFAULT_PRIORITY);
- }
-
-#if defined (GICv3)
- for (Int_Id = 0U; Int_IdDistBaseAddress,
- XSCUGIC_SECURITY_TARGET_OFFSET_CALC(Int_Id),
- XSCUGIC_DEFAULT_SECURITY);
- }
- /*
- * Set security for SGI/PPI
- *
- */
- XScuGic_WriteReg( Config->DistBaseAddress + XSCUGIC_RDIST_SGI_PPI_OFFSET,
- XSCUGIC_RDIST_IGROUPR_OFFSET, XSCUGIC_DEFAULT_SECURITY);
-#endif
-
- for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
- Int_Id = Int_Id+32U) {
- /*
- * 4. Enable the SPI using the enable_set register.
- * Leave all disabled for now.
- */
- XScuGic_WriteReg(Config->DistBaseAddress,
- XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET,
- Int_Id),
- 0xFFFFFFFFU);
-
- }
-
-#if defined (GICv3)
- Temp = XScuGic_ReadReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET);
- Temp |= XSCUGIC_EN_INT_MASK;
- XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, Temp);
- XScuGic_Enable_Group1_Interrupts();
- XScuGic_Enable_Group0_Interrupts();
- XScuGic_set_priority_filter(0xff);
-#else
-
- XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET,
- XSCUGIC_EN_INT_MASK);
-#endif
-
-}
-
-#if !defined (GICv3)
-/*****************************************************************************/
-/**
-*
-* CPUInit initializes the CPU Interface of the GIC. The initialization entails:
-*
-* - Set the priority of the CPU.
-* - Enable the CPU interface
-*
-* @param ConfigPtr is a pointer to a config table for the particular
-* device this driver is associated with.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-static void CPUInit(const XScuGic_Config *Config)
-{
- /*
- * Program the priority mask of the CPU using the Priority mask
- * register
- */
- XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CPU_PRIOR_OFFSET,
- 0xF0U);
-
- /*
- * If the CPU operates in both security domains, set parameters in the
- * control_s register.
- * 1. Set FIQen=1 to use FIQ for secure interrupts,
- * 2. Program the AckCtl bit
- * 3. Program the SBPR bit to select the binary pointer behavior
- * 4. Set EnableS = 1 to enable secure interrupts
- * 5. Set EnbleNS = 1 to enable non secure interrupts
- */
-
- /*
- * If the CPU operates only in the secure domain, setup the
- * control_s register.
- * 1. Set FIQen=1,
- * 2. Set EnableS=1, to enable the CPU interface to signal secure .
- * interrupts Only enable the IRQ output unless secure interrupts
- * are needed.
- */
- XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CONTROL_OFFSET, 0x07U);
-
-}
-#endif
-
-/*****************************************************************************/
-/**
-*
-* Initialize the GIC based on the device id. The
-* initialization entails:
-*
-* - Initialize distributor interface
-* - Initialize cpu interface
-*
-* @param DeviceId is device id to be worked on.
-*
-* @return
-*
-* - XST_SUCCESS if initialization was successful
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-s32 XScuGic_DeviceInitialize(u32 DeviceId)
-{
- XScuGic_Config *Config;
-
- Config = &XScuGic_ConfigTable[(u32)DeviceId];
- DistInit(Config);
-#if !defined (GICv3)
- CPUInit(Config);
-#endif
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-* This function is the primary interrupt handler for the driver. It must be
-* connected to the interrupt source such that it is called when an interrupt of
-* the interrupt controller is active. It will resolve which interrupts are
-* active and enabled and call the appropriate interrupt handler. It uses
-* the Interrupt Type information to determine when to acknowledge the
-* interrupt.Highest priority interrupts are serviced first.
-*
-* This function assumes that an interrupt vector table has been previously
-* initialized. It does not verify that entries in the table are valid before
-* calling an interrupt handler.
-*
-* @param DeviceId is the unique identifier for the ScuGic device.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XScuGic_DeviceInterruptHandler(void *DeviceId)
-{
-
- u32 InterruptID;
-#if !defined (GICv3)
- u32 IntIDFull;
-#endif
- XScuGic_VectorTableEntry *TablePtr;
- XScuGic_Config *CfgPtr;
-
- CfgPtr = &XScuGic_ConfigTable[(INTPTR)DeviceId];
-
-#if defined (GICv3)
- InterruptID = XScuGic_get_IntID();
-#else
- /*
- * Read the int_ack register to identify the highest priority
- * interrupt ID and make sure it is valid. Reading Int_Ack will
- * clear the interrupt in the GIC.
- */
- IntIDFull = XScuGic_ReadReg(CfgPtr->CpuBaseAddress,
- XSCUGIC_INT_ACK_OFFSET);
- InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
-
-#endif
- if (XSCUGIC_MAX_NUM_INTR_INPUTS <= InterruptID) {
- goto IntrExit;
- }
-
- /*
- * If the interrupt is shared, do some locking here if there are
- * multiple processors.
- */
- /*
- * If preemption is required:
- * Re-enable preemption by setting the CPSR I bit for non-secure ,
- * interrupts or the F bit for secure interrupts
- */
-
- /*
- * If we need to change security domains, issue a SMC instruction here.
- */
-
- /*
- * Execute the ISR. Jump into the Interrupt service routine based on
- * the IRQSource. A software trigger is cleared by the ACK.
- */
- TablePtr = &(CfgPtr->HandlerTable[InterruptID]);
- if (TablePtr != NULL) {
- TablePtr->Handler(TablePtr->CallBackRef);
- }
-
-IntrExit:
- /*
- * Write to the EOI register, we are all done here.
- * Let this function return, the boot code will restore the stack.
- */
-#if defined (GICv3)
- XScuGic_ack_Int(InterruptID);
-#else
- XScuGic_WriteReg(CfgPtr->CpuBaseAddress, XSCUGIC_EOI_OFFSET, IntIDFull);
-#endif
-
- /*
- * Return from the interrupt. Change security domains could happen
- * here.
- */
-}
-
-/*****************************************************************************/
-/**
-*
-* Register a handler function for a specific interrupt ID. The vector table
-* of the interrupt controller is updated, overwriting any previous handler.
-* The handler function will be called when an interrupt occurs for the given
-* interrupt ID.
-*
-* @param BaseAddress is the CPU Interface Register base address of the
-* interrupt controller whose vector table will be modified.
-* @param InterruptID is the interrupt ID to be associated with the input
-* handler.
-* @param IntrHandler is the function pointer that will be added to
-* the vector table for the given interrupt ID.
-* @param CallBackRef is the argument that will be passed to the new
-* handler function when it is called. This is user-specific.
-*
-* @return None.
-*
-* @note
-*
-* Note that this function has no effect if the input base address is invalid.
-*
-******************************************************************************/
-void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
- Xil_InterruptHandler IntrHandler, void *CallBackRef)
-{
- XScuGic_Config *CfgPtr;
- CfgPtr = LookupConfigByBaseAddress(BaseAddress);
-
- if (CfgPtr != NULL) {
- if (IntrHandler != NULL) {
- CfgPtr->HandlerTable[InterruptID].Handler =
- (Xil_InterruptHandler)IntrHandler;
- }
- if (CallBackRef != NULL) {
- CfgPtr->HandlerTable[InterruptID].CallBackRef =
- CallBackRef;
- }
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Looks up the device configuration based on the CPU interface base address of
-* the device. A table contains the configuration info for each device in the
-* system.
-*
-* @param CpuBaseAddress is the CPU Interface Register base address.
-*
-* @return A pointer to the configuration structure for the specified
-* device, or NULL if the device was not found.
-*
-* @note None.
-*
-******************************************************************************/
-static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress)
-{
- XScuGic_Config *CfgPtr = NULL;
- u32 Index;
-
- for (Index = 0U; Index < XPAR_SCUGIC_NUM_INSTANCES; Index++) {
- if (XScuGic_ConfigTable[Index].CpuBaseAddress ==
- CpuBaseAddress) {
- CfgPtr = &XScuGic_ConfigTable[Index];
- break;
- }
- }
-
- return (XScuGic_Config *)CfgPtr;
-}
-
-/****************************************************************************/
-/**
-* Sets the interrupt priority and trigger type for the specificd IRQ source.
-*
-* @param DistBaseAddress is the distributor base address
-* @param Int_Id is the IRQ source number to modify
-* @param Priority is the new priority for the IRQ source. 0 is highest
-* priority, 0xF8(248) is lowest. There are 32 priority
-* levels supported with a step of 8. Hence the supported
-* priorities are 0, 8, 16, 32, 40 ..., 248.
-* @param Trigger is the new trigger type for the IRQ source.
-* Each bit pair describes the configuration for an INT_ID.
-* SFI Read Only b10 always
-* PPI Read Only depending on how the PPIs are configured.
-* b01 Active HIGH level sensitive
-* b11 Rising edge sensitive
-* SPI LSB is read only.
-* b01 Active HIGH level sensitive
-* b11 Rising edge sensitive/
-*
-* @return None.
-*
-* @note This API has the similar functionality of XScuGic_SetPriority
-* TriggerType() and should be used when there is no InstancePtr.
-*
-*****************************************************************************/
-void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
- u8 Priority, u8 Trigger)
-{
- u32 RegValue;
-#if defined (GICv3)
- u32 Temp;
- u32 Index;
-#endif
- u8 LocalPriority = Priority;
-
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(Trigger <= XSCUGIC_INT_CFG_MASK);
- Xil_AssertVoid(LocalPriority <= XSCUGIC_MAX_INTR_PRIO_VAL);
-#if defined (GICv3)
- if (Int_Id < XSCUGIC_SPI_INT_ID_START )
- {
- XScuGic_WriteReg(DistBaseAddress + XSCUGIC_RDIST_SGI_PPI_OFFSET,
- XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(Int_Id),Priority);
- Temp = XScuGic_ReadReg(DistBaseAddress + XSCUGIC_RDIST_SGI_PPI_OFFSET,
- XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(Int_Id));
- Index = XScuGic_Get_Rdist_Int_Trigger_Index(Int_Id);
- Temp |= (Trigger << Index);
- XScuGic_WriteReg(DistBaseAddress + XSCUGIC_RDIST_SGI_PPI_OFFSET,
- XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(Int_Id),Temp);
- return;
- }
-#endif
-
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
-
- /*
- * Determine the register to write to using the Int_Id.
- */
- RegValue = XScuGic_ReadReg(DistBaseAddress,
- XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
-
- /*
- * The priority bits are Bits 7 to 3 in GIC Priority Register. This
- * means the number of priority levels supported are 32 and they are
- * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
- * The lower order 3 bits are masked before putting it in the register.
- */
- LocalPriority = LocalPriority & XSCUGIC_INTR_PRIO_MASK;
- /*
- * Shift and Mask the correct bits for the priority and trigger in the
- * register
- */
- RegValue &= ~((u32)XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
- RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
-
- /*
- * Write the value back to the register.
- */
- XScuGic_WriteReg(DistBaseAddress, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
- RegValue);
- /*
- * Determine the register to write to using the Int_Id.
- */
- RegValue = XScuGic_ReadReg(DistBaseAddress,
- XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id));
-
- /*
- * Shift and Mask the correct bits for the priority and trigger in the
- * register
- */
- RegValue &= ~((u32)XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
- RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
-
- /*
- * Write the value back to the register.
- */
- XScuGic_WriteReg(DistBaseAddress, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
- RegValue);
-
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-}
-
-/****************************************************************************/
-/**
-* Gets the interrupt priority and trigger type for the specificd IRQ source.
-*
-* @param DistBaseAddress is the distributor base address
-* @param Int_Id is the IRQ source number to modify
-* @param Priority is a pointer to the value of the priority of the IRQ
-* source. This is a return value.
-* @param Trigger is pointer to the value of the trigger of the IRQ
-* source. This is a return value.
-*
-* @return None.
-*
-* @note This API has the similar functionality of XScuGic_GetPriority
-* TriggerType() and should be used when there is no InstancePtr.
-*
-*****************************************************************************/
-void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
- u8 *Priority, u8 *Trigger)
-{
- u32 RegValue;
-
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(Priority != NULL);
- Xil_AssertVoid(Trigger != NULL);
-
- /*
- * Determine the register to read to using the Int_Id.
- */
- RegValue = XScuGic_ReadReg(DistBaseAddress,
- XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
-
- /*
- * Shift and Mask the correct bits for the priority and trigger in the
- * register
- */
- RegValue = RegValue >> ((Int_Id%4U)*8U);
- *Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
-
- /*
- * Determine the register to read to using the Int_Id.
- */
- RegValue = XScuGic_ReadReg(DistBaseAddress,
- XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id));
-
- /*
- * Shift and Mask the correct bits for the priority and trigger in the
- * register
- */
- RegValue = RegValue >> ((Int_Id%16U)*2U);
-
- *Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
-}
-
-/****************************************************************************/
-/**
-* Sets the target CPU for the interrupt of a peripheral
-*
-* @param DistBaseAddress is the device base address
-* @param Cpu_Id is a CPU number from which the interrupt has to be
-* unmapped
-* @param Int_Id is the IRQ source number to modify
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_InterruptMapFromCpuByDistAddr(u32 DistBaseAddress,
- u8 Cpu_Id, u32 Int_Id)
-{
- u32 RegValue;
-#if !defined (GICv3)
- u32 Offset;
- u8 Cpu_CoreId;
-#endif
-
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
-#if defined (GICv3)
- u32 Temp;
- if (Int_Id >= 32) {
- Temp = Int_Id - 32;
- RegValue = XScuGic_ReadReg(DistBaseAddress,
- XSCUGIC_IROUTER_OFFSET_CALC(Temp));
- RegValue |= (Cpu_Id);
- XScuGic_WriteReg(DistBaseAddress, XSCUGIC_IROUTER_OFFSET_CALC(Temp),
- RegValue);
- }
-#else
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
- RegValue = XScuGic_ReadReg(DistBaseAddress,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
-
- Offset = (Int_Id & 0x3U);
- Cpu_CoreId = (0x1U << Cpu_Id);
-
- RegValue |= (u32)(Cpu_CoreId) << (Offset*8U);
-
- XScuGic_WriteReg(DistBaseAddress,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
- RegValue);
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-#endif
-}
-
-/****************************************************************************/
-/**
-* Unmaps specific SPI interrupt from the target CPU
-*
-* @param DistBaseAddress is the device base address
-* @param Cpu_Id is a CPU number from which the interrupt has to be
-* unmapped
-* @param Int_Id is the IRQ source number to modify
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
- u8 Cpu_Id, u32 Int_Id)
-{
- u32 RegValue;
-#if !defined (GICv3)
- u32 Offset;
- u32 Cpu_CoreId;
-#endif
-
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
-#if defined (GICv3)
- u32 Temp;
- if (Int_Id >= 32 && Cpu_Id != 0) {
- Temp = Int_Id - 32;
- RegValue = XScuGic_ReadReg(DistBaseAddress,
- XSCUGIC_IROUTER_OFFSET_CALC(Temp));
- RegValue &= ~(Cpu_Id);
- XScuGic_WriteReg(DistBaseAddress, XSCUGIC_IROUTER_OFFSET_CALC(Temp),
- RegValue);
- } else if (Cpu_Id == 0) {
- xil_printf("Error: Unable to unmap interrupt id %d from core %d",Int_Id,Cpu_Id);
- }
-#else
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
-
- RegValue = XScuGic_ReadReg(DistBaseAddress,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
-
- Offset = (Int_Id & 0x3U);
- Cpu_CoreId = ((u32)0x1U << Cpu_Id);
-
- RegValue &= ~(Cpu_CoreId << (Offset*8U));
- XScuGic_WriteReg(DistBaseAddress,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), RegValue);
-
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-#endif
-}
-
-/****************************************************************************/
-/**
-* Unmaps all SPI interrupts from the target CPU
-*
-* @param DistBaseAddress is the device base address
-* @param Cpu_Id is a CPU number from which the interrupts has to be
-* unmapped
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
- u8 Cpu_Id)
-{
- u32 Int_Id;
- u32 Target_Cpu;
- u32 LocalCpuID = ((u32)1U << Cpu_Id);
-
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
-
- LocalCpuID |= LocalCpuID << 8U;
- LocalCpuID |= LocalCpuID << 16U;
-
- for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
- Int_Id = Int_Id+4U) {
-
- Target_Cpu = XScuGic_ReadReg(DistBaseAddress,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
- /* Remove LocalCpuID from interrupt target register */
- Target_Cpu &= (~LocalCpuID);
- XScuGic_WriteReg(DistBaseAddress,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu);
-
- }
-
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-}
-
-/*****************************************************************************/
-/**
-*
-* Enables the interrupt source provided as the argument Int_Id. Any pending
-* interrupt condition for the specified Int_Id will occur after this function is
-* called.
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-* @param Int_Id contains the ID of the interrupt source and should be
-* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XScuGic_EnableIntr (u32 DistBaseAddress, u32 Int_Id)
-{
- u8 Cpu_Id = (u8)XScuGic_GetCpuID();
-#if defined (GICv3)
- u32 Temp;
-#endif
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
-
-#if defined (GICv3)
- if (Int_Id < XSCUGIC_SPI_INT_ID_START) {
- XScuGic_InterruptMapFromCpuByDistAddr(DistBaseAddress, Cpu_Id,
- Int_Id);
-
- Int_Id &= 0x1f;
- Int_Id = 1 << Int_Id;
-
- Temp = XScuGic_ReadReg(DistBaseAddress +
- XSCUGIC_RDIST_SGI_PPI_OFFSET, XSCUGIC_RDIST_ISENABLE_OFFSET);
- Temp |= Int_Id;
- XScuGic_WriteReg(DistBaseAddress + XSCUGIC_RDIST_SGI_PPI_OFFSET,
- XSCUGIC_RDIST_ISENABLE_OFFSET,Temp);
- }
-#endif
-
- XScuGic_InterruptMapFromCpuByDistAddr(DistBaseAddress, Cpu_Id, Int_Id);
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
- XScuGic_WriteReg((DistBaseAddress), XSCUGIC_ENABLE_SET_OFFSET +
- (((Int_Id) / 32U) * 4U), ((u32)0x00000001U << ((Int_Id) % 32U)));
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-}
-
-/*****************************************************************************/
-/**
-*
-* Disables the interrupt source provided as the argument Int_Id such that the
-* interrupt controller will not cause interrupts for the specified Int_Id. The
-* interrupt controller will continue to hold an interrupt condition for the
-* Int_Id, but will not cause an interrupt.
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-* @param Int_Id contains the ID of the interrupt source and should be
-* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XScuGic_DisableIntr (u32 DistBaseAddress, u32 Int_Id)
-{
- u8 Cpu_Id = (u8)XScuGic_GetCpuID();
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
-
-#if defined (GICv3)
- u32 Temp;
-
- if (Int_Id < XSCUGIC_SPI_INT_ID_START) {
-
- XScuGic_InterruptUnmapFromCpuByDistAddr(DistBaseAddress +
- XSCUGIC_RDIST_SGI_PPI_OFFSET, Cpu_Id, Int_Id);
-
- Int_Id &= 0x1f;
- Int_Id = 1 << Int_Id;
-
- Temp = XScuGic_ReadReg(DistBaseAddress + XSCUGIC_RDIST_SGI_PPI_OFFSET,
- XSCUGIC_RDIST_ISENABLE_OFFSET);
- Temp &= ~Int_Id;
- XScuGic_WriteReg(DistBaseAddress + XSCUGIC_RDIST_SGI_PPI_OFFSET,
- XSCUGIC_RDIST_ISENABLE_OFFSET,Temp);
- }
-#endif
- XScuGic_InterruptUnmapFromCpuByDistAddr(DistBaseAddress, Cpu_Id, Int_Id);
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
- XScuGic_WriteReg((DistBaseAddress), XSCUGIC_DISABLE_OFFSET +
- (((Int_Id) / 32U) * 4U), ((u32)0x00000001U << ((Int_Id) % 32U)));
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-}
-
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/34/c0b3bd585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/34/c0b3bd585243001d18b399c1eb9b3628
deleted file mode 100644
index 9bfebb2..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/34/c0b3bd585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,51 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*
- *
- *
- * The "__read" function reads a number of bytes, at most "size" into
- * the memory area pointed to by "buffer". It returns the number of
- * bytes read, 0 at the end of the file, or _LLIO_ERROR if failure
- * occurs.
- *
- * The template implementation below should return a
- * character value, or -1 on failure.
- *
- */
-
-#include
-#include "xparameters.h"
-#include "xil_types.h"
-
-size_t __read(sint32 handle, u8 * buffer, size_t size);
-
-size_t __read(sint32 handle, u8 * buffer, size_t size)
-{
-
-#ifdef STDIN_BASEADDRESS
- s32 i;
- s32 numbytes = 0;
- char8* LocalBuf = buffer;
-
- (void)handle;
- if(LocalBuf != NULL) {
- for (i = 0; i < size; i++) {
- numbytes++;
- *(LocalBuf + i) = inbyte();
- if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
- break;
- }
- }
- }
-
- return numbytes;
-#else
- (void)handle;
- (void)buffer;
- (void)size;
- return 0;
-#endif
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/35/002049585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/35/002049585243001d18b399c1eb9b3628
deleted file mode 100644
index 20c1170..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/35/002049585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,73 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************
-*
-* @file sleep.c
-*
-* This function provides a second delay using the Generic Counter register in
-* the ARM Cortex A53 MPcore.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 5.4 pkp 28/01/16 Modified the sleep API to configure Time Stamp
-* generator only when disable using frequency from
-* xparamters.h instead of hardcoding
-* 5.05 pkp 13/04/16 Modified sleep routine to call XTime_StartTimer
-* which enables timer only when it is disabled and
-* read counter value directly from register instead
-* of calling XTime_GetTime for optimization
-* 6.0 mus 08/18/16 Updated the sleep signature. Fix for CR#956899
-* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
-* implementation. Now sleep routines will use Timer
-* specified by the user (i.e. Global timer/TTC timer)
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "sleep.h"
-#include "xtime_l.h"
-#include "xparameters.h"
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#include "xil_sleeptimer.h"
-#endif
-
-/*****************************************************************************/
-/**
-*
-* This API is used to provide delays in seconds
-*
-* @param seconds requested
-*
-* @return 0 always
-*
-* @note None.
-*
-****************************************************************************/
-unsigned sleep_A53(unsigned int seconds)
-{
-#if defined (SLEEP_TIMER_BASEADDR)
- Xil_SleepTTCCommon(seconds, COUNTS_PER_SECOND);
-#else
- XTime tEnd, tCur;
- /* Start global timer counter, it will only be enabled if it is disabled */
- XTime_StartTimer();
-
- tCur = arch_counter_get_cntvct();
- tEnd = tCur + (((XTime) seconds) * COUNTS_PER_SECOND);
- do
- {
- tCur = arch_counter_get_cntvct();
- } while (tCur < tEnd);
-#endif
-
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/35/21c767545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/35/21c767545243001d18b399c1eb9b3628
deleted file mode 100644
index 2de567a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/35/21c767545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1410 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xsdps_hw.h
-* @addtogroup sdps_v3_13
-* @{
-*
-* This header file contains the identifiers and basic HW access driver
-* functions (or macros) that can be used to access the device. Other driver
-* functions are defined in xsdps.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a hk/sg 10/17/13 Initial release
-* 2.5 sg 07/09/15 Added SD 3.0 features
-* kvn 07/15/15 Modified the code according to MISRAC-2012.
-* 2.7 sk 12/10/15 Added support for MMC cards.
-* sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
-* 2.8 sk 04/20/16 Added new workaround for auto tuning.
-* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
-* sk 07/16/16 Added support for UHS modes.
-* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
-* operating modes.
-* 3.1 sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
-* 3.2 sk 03/20/17 Add support for EL1 non-secure mode.
-* 3.3 mn 08/22/17 Updated for Word Access System support
-* mn 09/06/17 Added support for ARMCC toolchain
-* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
-* 3.6 mn 07/06/18 Fix Doxygen warnings for sdps driver
-* 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
-* mn 05/21/19 Set correct tap delays for Versal
-* mn 05/21/19 Disable DLL Reset code for Versal
-* mn 07/03/19 Update Input Tap Delays for Versal
-* 3.9 mn 03/03/20 Restructured the code for more readability and modularity
-*
-*
-*
-******************************************************************************/
-
-#ifndef SD_HW_H_
-#define SD_HW_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets from the base address of an SD device.
- * @{
- */
-
-#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address
- Register */
-#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET
- /**< SDMA System Address
- Low Register */
-#define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */
-#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address
- High Register */
-#define XSDPS_ARGMT2_HI_OFFSET 0x02U /**< Argument2 High Register */
-
-#define XSDPS_BLK_SIZE_OFFSET 0x04U /**< Block Size Register */
-#define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */
-#define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */
-#define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET
- /**< Argument1 Register */
-#define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */
-
-#define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */
-#define XSDPS_CMD_OFFSET 0x0EU /**< Command Register */
-#define XSDPS_RESP0_OFFSET 0x10U /**< Response0 Register */
-#define XSDPS_RESP1_OFFSET 0x14U /**< Response1 Register */
-#define XSDPS_RESP2_OFFSET 0x18U /**< Response2 Register */
-#define XSDPS_RESP3_OFFSET 0x1CU /**< Response3 Register */
-#define XSDPS_BUF_DAT_PORT_OFFSET 0x20U /**< Buffer Data Port */
-#define XSDPS_PRES_STATE_OFFSET 0x24U /**< Present State */
-#define XSDPS_HOST_CTRL1_OFFSET 0x28U /**< Host Control 1 */
-#define XSDPS_POWER_CTRL_OFFSET 0x29U /**< Power Control */
-#define XSDPS_BLK_GAP_CTRL_OFFSET 0x2AU /**< Block Gap Control */
-#define XSDPS_WAKE_UP_CTRL_OFFSET 0x2BU /**< Wake Up Control */
-#define XSDPS_CLK_CTRL_OFFSET 0x2CU /**< Clock Control */
-#define XSDPS_TIMEOUT_CTRL_OFFSET 0x2EU /**< Timeout Control */
-#define XSDPS_SW_RST_OFFSET 0x2FU /**< Software Reset */
-#define XSDPS_NORM_INTR_STS_OFFSET 0x30U /**< Normal Interrupt
- Status Register */
-#define XSDPS_ERR_INTR_STS_OFFSET 0x32U /**< Error Interrupt
- Status Register */
-#define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34U /**< Normal Interrupt
- Status Enable Register */
-#define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36U /**< Error Interrupt
- Status Enable Register */
-#define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38U /**< Normal Interrupt
- Signal Enable Register */
-#define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3AU /**< Error Interrupt
- Signal Enable Register */
-
-#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3CU /**< Auto CMD12 Error Status
- Register */
-#define XSDPS_HOST_CTRL2_OFFSET 0x3EU /**< Host Control2 Register */
-#define XSDPS_CAPS_OFFSET 0x40U /**< Capabilities Register */
-#define XSDPS_CAPS_EXT_OFFSET 0x44U /**< Capabilities Extended */
-#define XSDPS_MAX_CURR_CAPS_OFFSET 0x48U /**< Maximum Current
- Capabilities Register */
-#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4CU /**< Maximum Current
- Capabilities Ext Register */
-#define XSDPS_FE_ERR_INT_STS_OFFSET 0x52U /**< Force Event for
- Error Interrupt Status */
-#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50U /**< Auto CM12 Error Interrupt
- Status Register */
-#define XSDPS_ADMA_ERR_STS_OFFSET 0x54U /**< ADMA Error Status
- Register */
-#define XSDPS_ADMA_SAR_OFFSET 0x58U /**< ADMA System Address
- Register */
-#define XSDPS_ADMA_SAR_EXT_OFFSET 0x5CU /**< ADMA System Address
- Extended Register */
-#define XSDPS_PRE_VAL_1_OFFSET 0x60U /**< Preset Value Register */
-#define XSDPS_PRE_VAL_2_OFFSET 0x64U /**< Preset Value Register */
-#define XSDPS_PRE_VAL_3_OFFSET 0x68U /**< Preset Value Register */
-#define XSDPS_PRE_VAL_4_OFFSET 0x6CU /**< Preset Value Register */
-#define XSDPS_BOOT_TOUT_CTRL_OFFSET 0x70U /**< Boot timeout control
- register */
-
-#define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0U /**< Shared Bus Control
- Register */
-#define XSDPS_SLOT_INTR_STS_OFFSET 0xFCU /**< Slot Interrupt Status
- Register */
-#define XSDPS_HOST_CTRL_VER_OFFSET 0xFEU /**< Host Controller Version
- Register */
-
-/** @} */
-
-/** @name Control Register - Host control, Power control,
- * Block Gap control and Wakeup control
- *
- * This register contains bits for various configuration options of
- * the SD host controller. Read/Write apart from the reserved bits.
- * @{
- */
-
-#define XSDPS_HC_LED_MASK 0x00000001U /**< LED Control */
-#define XSDPS_HC_WIDTH_MASK 0x00000002U /**< Bus width */
-#define XSDPS_HC_BUS_WIDTH_4 0x00000002U
-#define XSDPS_HC_SPEED_MASK 0x00000004U /**< High Speed */
-#define XSDPS_HC_DMA_MASK 0x00000018U /**< DMA Mode Select */
-#define XSDPS_HC_DMA_SDMA_MASK 0x00000000U /**< SDMA Mode */
-#define XSDPS_HC_DMA_ADMA1_MASK 0x00000008U /**< ADMA1 Mode */
-#define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010U /**< ADMA2 Mode - 32 bit */
-#define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018U /**< ADMA2 Mode - 64 bit */
-#define XSDPS_HC_EXT_BUS_WIDTH 0x00000020U /**< Bus width - 8 bit */
-#define XSDPS_HC_CARD_DET_TL_MASK 0x00000040U /**< Card Detect Tst Lvl */
-#define XSDPS_HC_CARD_DET_SD_MASK 0x00000080U /**< Card Detect Sig Det */
-
-#define XSDPS_PC_BUS_PWR_MASK 0x00000001U /**< Bus Power Control */
-#define XSDPS_PC_BUS_VSEL_MASK 0x0000000EU /**< Bus Voltage Select */
-#define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000EU /**< Bus Voltage 3.3V */
-#define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000CU /**< Bus Voltage 3.0V */
-#define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000AU /**< Bus Voltage 1.8V */
-#define XSDPS_PC_EMMC_HW_RST_MASK 0x00000010U /**< HW reset for eMMC */
-
-#define XSDPS_BGC_STP_REQ_MASK 0x00000001U /**< Block Gap Stop Req */
-#define XSDPS_BGC_CNT_REQ_MASK 0x00000002U /**< Block Gap Cont Req */
-#define XSDPS_BGC_RWC_MASK 0x00000004U /**< Block Gap Rd Wait */
-#define XSDPS_BGC_INTR_MASK 0x00000008U /**< Block Gap Intr */
-#define XSDPS_BGC_SPI_MODE_MASK 0x00000010U /**< Block Gap SPI Mode */
-#define XSDPS_BGC_BOOT_EN_MASK 0x00000020U /**< Block Gap Boot Enb */
-#define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040U /**< Block Gap Alt BootEn */
-#define XSDPS_BGC_BOOT_ACK_MASK 0x00000080U /**< Block Gap Boot Ack */
-
-#define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001U /**< Wakeup Card Intr */
-#define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002U /**< Wakeup Card Insert */
-#define XSDPS_WC_WUP_ON_REM_MASK 0x00000004U /**< Wakeup Card Removal */
-
-/** @} */
-
-/** @name Control Register - Clock control, Timeout control & Software reset
- *
- * This register contains bits for configuration options of clock, timeout and
- * software reset.
- * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
- * @{
- */
-
-#define XSDPS_CC_INT_CLK_EN_MASK 0x00000001U /**< INT clk enable */
-#define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002U /**< INT clk stable */
-#define XSDPS_CC_SD_CLK_EN_MASK 0x00000004U /**< SD clk enable */
-#define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020U /**< SD clk gen selection */
-#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x00000003U /**< SD clk freq sel upper */
-#define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x000000FFU /**< SD clk freq sel */
-#define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000U /**< Divider 256 */
-#define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000U /**< Divider 128 */
-#define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000U /**< Divider 64 */
-#define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000U /**< Divider 32 */
-#define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800U /**< Divider 16 */
-#define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400U /**< Divider 8 */
-#define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200U /**< Divider 4 */
-#define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100U /**< Divider 2 */
-#define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000U /**< Base clock */
-#define XSDPS_CC_MAX_DIV_CNT 256U /**< Max divider count */
-#define XSDPS_CC_EXT_MAX_DIV_CNT 2046U /**< Max extended divider count */
-#define XSDPS_CC_EXT_DIV_SHIFT 6U /**< Ext divider shift */
-
-#define XSDPS_TC_CNTR_VAL_MASK 0x0000000FU /**< Data timeout counter */
-
-#define XSDPS_SWRST_ALL_MASK 0x00000001U /**< Software Reset All */
-#define XSDPS_SWRST_CMD_LINE_MASK 0x00000002U /**< Software reset for CMD line */
-#define XSDPS_SWRST_DAT_LINE_MASK 0x00000004U /**< Software reset for DAT line */
-
-#define XSDPS_CC_MAX_NUM_OF_DIV 9U /**< Max number of Clock dividers */
-#define XSDPS_CC_DIV_SHIFT 8U /**< Clock Divider shift */
-
-/** @} */
-
-/** @name SD Interrupt Registers
- *
- * Normal and Error Interrupt Status Register
- * This register shows the normal and error interrupt status.
- * Status enable register affects reads of this register.
- * If Signal enable register is set and the corresponding status bit is set,
- * interrupt is generated.
- * Write to clear except
- * Error_interrupt and Card_Interrupt bits - Read only
- *
- * Normal and Error Interrupt Status Enable Register
- * Setting this register bits enables Interrupt status.
- * Read/Write except Fixed_to_0 bit (Read only)
- *
- * Normal and Error Interrupt Signal Enable Register
- * This register is used to select which interrupt status is
- * indicated to the Host System as the interrupt.
- * Read/Write except Fixed_to_0 bit (Read only)
- *
- * All three registers have same bit definitions
- * @{
- */
-
-#define XSDPS_INTR_CC_MASK 0x00000001U /**< Command Complete */
-#define XSDPS_INTR_TC_MASK 0x00000002U /**< Transfer Complete */
-#define XSDPS_INTR_BGE_MASK 0x00000004U /**< Block Gap Event */
-#define XSDPS_INTR_DMA_MASK 0x00000008U /**< DMA Interrupt */
-#define XSDPS_INTR_BWR_MASK 0x00000010U /**< Buffer Write Ready */
-#define XSDPS_INTR_BRR_MASK 0x00000020U /**< Buffer Read Ready */
-#define XSDPS_INTR_CARD_INSRT_MASK 0x00000040U /**< Card Insert */
-#define XSDPS_INTR_CARD_REM_MASK 0x00000080U /**< Card Remove */
-#define XSDPS_INTR_CARD_MASK 0x00000100U /**< Card Interrupt */
-#define XSDPS_INTR_INT_A_MASK 0x00000200U /**< INT A Interrupt */
-#define XSDPS_INTR_INT_B_MASK 0x00000400U /**< INT B Interrupt */
-#define XSDPS_INTR_INT_C_MASK 0x00000800U /**< INT C Interrupt */
-#define XSDPS_INTR_RE_TUNING_MASK 0x00001000U /**< Re-Tuning Interrupt */
-#define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00002000U /**< Boot Ack Recv
- Interrupt */
-#define XSDPS_INTR_BOOT_TERM_MASK 0x00004000U /**< Boot Terminate
- Interrupt */
-#define XSDPS_INTR_ERR_MASK 0x00008000U /**< Error Interrupt */
-#define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFFU
-
-#define XSDPS_INTR_ERR_CT_MASK 0x00000001U /**< Command Timeout
- Error */
-#define XSDPS_INTR_ERR_CCRC_MASK 0x00000002U /**< Command CRC Error */
-#define XSDPS_INTR_ERR_CEB_MASK 0x00000004U /**< Command End Bit
- Error */
-#define XSDPS_INTR_ERR_CI_MASK 0x00000008U /**< Command Index Error */
-#define XSDPS_INTR_ERR_DT_MASK 0x00000010U /**< Data Timeout Error */
-#define XSDPS_INTR_ERR_DCRC_MASK 0x00000020U /**< Data CRC Error */
-#define XSDPS_INTR_ERR_DEB_MASK 0x00000040U /**< Data End Bit Error */
-#define XSDPS_INTR_ERR_CUR_LMT_MASK 0x00000080U /**< Current Limit Error */
-#define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100U /**< Auto CMD12 Error */
-#define XSDPS_INTR_ERR_ADMA_MASK 0x00000200U /**< ADMA Error */
-#define XSDPS_INTR_ERR_TR_MASK 0x00001000U /**< Tuning Error */
-#define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000U /**< Vendor Specific
- Error */
-#define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FFU /**< Mask for error bits */
-/** @} */
-
-/** @name Block Size and Block Count Register
- *
- * This register contains the block count for current transfer,
- * block size and SDMA buffer size.
- * Read/Write except for reserved bits.
- * @{
- */
-
-#define XSDPS_BLK_SIZE_MASK 0x00000FFFU /**< Transfer Block Size */
-#define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000U /**< Host SDMA Buffer Size */
-#define XSDPS_BLK_SIZE_1024 0x400U
-#define XSDPS_BLK_SIZE_2048 0x800U
-#define XSDPS_BLK_CNT_MASK 0x0000FFFFU /**< Block Count for
- Current Transfer */
-
-/** @} */
-
-/** @name Transfer Mode and Command Register
- *
- * The Transfer Mode register is used to control the data transfers and
- * Command register is used for command generation
- * Read/Write except for reserved bits.
- * @{
- */
-
-#define XSDPS_TM_DMA_EN_MASK 0x00000001U /**< DMA Enable */
-#define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002U /**< Block Count Enable */
-#define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004U /**< Auto CMD12 Enable */
-#define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010U /**< Data Transfer
- Direction Select */
-#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020U /**< Multi/Single
- Block Select */
-
-#define XSDPS_CMD_RESP_SEL_MASK 0x00000003U /**< Response Type
- Select */
-#define XSDPS_CMD_RESP_NONE_MASK 0x00000000U /**< No Response */
-#define XSDPS_CMD_RESP_L136_MASK 0x00000001U /**< Response length 138 */
-#define XSDPS_CMD_RESP_L48_MASK 0x00000002U /**< Response length 48 */
-#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003U /**< Response length 48 &
- check busy after
- response */
-#define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008U /**< Command CRC Check
- Enable */
-#define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010U /**< Command Index Check
- Enable */
-#define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020U /**< Data Present Select */
-#define XSDPS_CMD_TYPE_MASK 0x000000C0U /**< Command Type */
-#define XSDPS_CMD_TYPE_NORM_MASK 0x00000000U /**< CMD Type - Normal */
-#define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040U /**< CMD Type - Suspend */
-#define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080U /**< CMD Type - Resume */
-#define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0U /**< CMD Type - Abort */
-#define XSDPS_CMD_MASK 0x00003F00U /**< Command Index Mask -
- Set to CMD0-63,
- AMCD0-63 */
-
-/** @} */
-
-/** @name Auto CMD Error Status Register
- *
- * This register is read only register which contains
- * information about the error status of Auto CMD 12 and 23.
- * Read Only
- * @{
- */
-#define XSDPS_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
- executed */
-#define XSDPS_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
- Error */
-#define XSDPS_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
-#define XSDPS_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
- Error */
-#define XSDPS_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
-#define XSDPS_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
- Auto CMD12 Error */
-/** @} */
-
-/** @name Host Control2 Register
- *
- * This register contains extended configuration bits.
- * Read Write
- * @{
- */
-#define XSDPS_HC2_UHS_MODE_MASK 0x0007U /**< UHS Mode select bits */
-#define XSDPS_HC2_UHS_MODE_SDR12_MASK 0x0000U /**< SDR12 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_SDR25_MASK 0x0001U /**< SDR25 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_SDR50_MASK 0x0002U /**< SDR50 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_SDR104_MASK 0x0003U /**< SDR104 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_DDR50_MASK 0x0004U /**< DDR50 UHS Mode */
-#define XSDPS_HC2_1V8_EN_MASK 0x0008U /**< 1.8V Signal Enable */
-#define XSDPS_HC2_DRV_STR_SEL_MASK 0x0030U /**< Driver Strength
- Selection */
-#define XSDPS_HC2_DRV_STR_B_MASK 0x0000U /**< Driver Strength B */
-#define XSDPS_HC2_DRV_STR_A_MASK 0x0010U /**< Driver Strength A */
-#define XSDPS_HC2_DRV_STR_C_MASK 0x0020U /**< Driver Strength C */
-#define XSDPS_HC2_DRV_STR_D_MASK 0x0030U /**< Driver Strength D */
-#define XSDPS_HC2_EXEC_TNG_MASK 0x0040U /**< Execute Tuning */
-#define XSDPS_HC2_SAMP_CLK_SEL_MASK 0x0080U /**< Sampling Clock
- Selection */
-#define XSDPS_HC2_ASYNC_INTR_EN_MASK 0x4000U /**< Asynchronous Interrupt
- Enable */
-#define XSDPS_HC2_PRE_VAL_EN_MASK 0x8000U /**< Preset Value Enable */
-
-/** @} */
-
-/** @name Capabilities Register
- *
- * Capabilities register is a read only register which contains
- * information about the host controller.
- * Sufficient if read once after power on.
- * Read Only
- * @{
- */
-#define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003FU /**< Timeout clock freq
- select */
-#define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080U /**< Timeout clock unit -
- MHz/KHz */
-#define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000U /**< Max block length */
-#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000U /**< Max block 512 bytes */
-#define XSDPS_CAP_MAX_BL_LN_1024_MASK 0x00010000U /**< Max block 1024 bytes */
-#define XSDPS_CAP_MAX_BL_LN_2048_MASK 0x00020000U /**< Max block 2048 bytes */
-#define XSDPS_CAP_MAX_BL_LN_4096_MASK 0x00030000U /**< Max block 4096 bytes */
-
-#define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000U /**< Extended media bus */
-#define XSDPS_CAP_ADMA2_MASK 0x00080000U /**< ADMA2 support */
-#define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000U /**< High speed support */
-#define XSDPS_CAP_SDMA_MASK 0x00400000U /**< SDMA support */
-#define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000U /**< Suspend/Resume
- support */
-#define XSDPS_CAP_VOLT_3V3_MASK 0x01000000U /**< 3.3V support */
-#define XSDPS_CAP_VOLT_3V0_MASK 0x02000000U /**< 3.0V support */
-#define XSDPS_CAP_VOLT_1V8_MASK 0x04000000U /**< 1.8V support */
-
-#define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000U /**< 64 bit system bus
- support */
-/* Spec 2.0 */
-#define XSDPS_CAP_INTR_MODE_MASK 0x08000000U /**< Interrupt mode
- support */
-#define XSDPS_CAP_SPI_MODE_MASK 0x20000000U /**< SPI mode */
-#define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x40000000U /**< SPI block mode */
-
-
-/* Spec 3.0 */
-#define XSDPS_CAPS_ASYNC_INTR_MASK 0x20000000U /**< Async Interrupt
- support */
-#define XSDPS_CAPS_SLOT_TYPE_MASK 0xC0000000U /**< Slot Type */
-#define XSDPS_CAPS_REM_CARD 0x00000000U /**< Removable Slot */
-#define XSDPS_CAPS_EMB_SLOT 0x40000000U /**< Embedded Slot */
-#define XSDPS_CAPS_SHR_BUS 0x80000000U /**< Shared Bus Slot */
-
-#define XSDPS_ECAPS_SDR50_MASK 0x00000001U /**< SDR50 Mode support */
-#define XSDPS_ECAPS_SDR104_MASK 0x00000002U /**< SDR104 Mode support */
-#define XSDPS_ECAPS_DDR50_MASK 0x00000004U /**< DDR50 Mode support */
-#define XSDPS_ECAPS_DRV_TYPE_A_MASK 0x00000010U /**< DriverType A support */
-#define XSDPS_ECAPS_DRV_TYPE_C_MASK 0x00000020U /**< DriverType C support */
-#define XSDPS_ECAPS_DRV_TYPE_D_MASK 0x00000040U /**< DriverType D support */
-#define XSDPS_ECAPS_TMR_CNT_MASK 0x00000F00U /**< Timer Count for
- Re-tuning */
-#define XSDPS_ECAPS_USE_TNG_SDR50_MASK 0x00002000U /**< SDR50 Mode needs
- tuning */
-#define XSDPS_ECAPS_RE_TNG_MODES_MASK 0x0000C000U /**< Re-tuning modes
- support */
-#define XSDPS_ECAPS_RE_TNG_MODE1_MASK 0x00000000U /**< Re-tuning mode 1 */
-#define XSDPS_ECAPS_RE_TNG_MODE2_MASK 0x00004000U /**< Re-tuning mode 2 */
-#define XSDPS_ECAPS_RE_TNG_MODE3_MASK 0x00008000U /**< Re-tuning mode 3 */
-#define XSDPS_ECAPS_CLK_MULT_MASK 0x00FF0000U /**< Clock Multiplier value
- for Programmable clock
- mode */
-#define XSDPS_ECAPS_SPI_MODE_MASK 0x01000000U /**< SPI mode */
-#define XSDPS_ECAPS_SPI_BLK_MODE_MASK 0x02000000U /**< SPI block mode */
-
-/** @} */
-
-/** @name Present State Register
- *
- * Gives the current status of the host controller
- * Read Only
- * @{
- */
-
-#define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001U /**< Command inhibit - CMD */
-#define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002U /**< Command Inhibit - DAT */
-#define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004U /**< DAT line active */
-#define XSDPS_PSR_RE_TUNING_REQ_MASK 0x00000008U /**< Re-tuning request */
-#define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100U /**< Write transfer active */
-#define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200U /**< Read transfer active */
-#define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400U /**< Buffer write enable */
-#define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800U /**< Buffer read enable */
-#define XSDPS_PSR_CARD_INSRT_MASK 0x00010000U /**< Card inserted */
-#define XSDPS_PSR_CARD_STABLE_MASK 0x00020000U /**< Card state stable */
-#define XSDPS_PSR_CARD_DPL_MASK 0x00040000U /**< Card detect pin level */
-#define XSDPS_PSR_WPS_PL_MASK 0x00080000U /**< Write protect switch
- pin level */
-#define XSDPS_PSR_DAT30_SG_LVL_MASK 0x00F00000U /**< Data 3:0 signal lvl */
-#define XSDPS_PSR_CMD_SG_LVL_MASK 0x01000000U /**< Cmd Line signal lvl */
-#define XSDPS_PSR_DAT74_SG_LVL_MASK 0x1E000000U /**< Data 7:4 signal lvl */
-
-/** @} */
-
-/** @name Maximum Current Capabilities Register
- *
- * This register is read only register which contains
- * information about current capabilities at each voltage levels.
- * Read Only
- * @{
- */
-#define XSDPS_MAX_CUR_CAPS_1V8_MASK 0x00000F00U /**< Maximum Current
- Capability at 1.8V */
-#define XSDPS_MAX_CUR_CAPS_3V0_MASK 0x000000F0U /**< Maximum Current
- Capability at 3.0V */
-#define XSDPS_MAX_CUR_CAPS_3V3_MASK 0x0000000FU /**< Maximum Current
- Capability at 3.3V */
-/** @} */
-
-
-/** @name Force Event for Auto CMD Error Status Register
- *
- * This register is write only register which contains
- * control bits to generate events for Auto CMD error status.
- * Write Only
- * @{
- */
-#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
- executed */
-#define XSDPS_FE_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
- Error */
-#define XSDPS_FE_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
-#define XSDPS_FE_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
- Error */
-#define XSDPS_FE_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
-#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
- Auto CMD12 Error */
-/** @} */
-
-
-
-/** @name Force Event for Error Interrupt Status Register
- *
- * This register is write only register which contains
- * control bits to generate events of error interrupt status register.
- * Write Only
- * @{
- */
-#define XSDPS_FE_INTR_ERR_CT_MASK 0x0001U /**< Command Timeout
- Error */
-#define XSDPS_FE_INTR_ERR_CCRC_MASK 0x0002U /**< Command CRC Error */
-#define XSDPS_FE_INTR_ERR_CEB_MASK 0x0004U /**< Command End Bit
- Error */
-#define XSDPS_FE_INTR_ERR_CI_MASK 0x0008U /**< Command Index Error */
-#define XSDPS_FE_INTR_ERR_DT_MASK 0x0010U /**< Data Timeout Error */
-#define XSDPS_FE_INTR_ERR_DCRC_MASK 0x0020U /**< Data CRC Error */
-#define XSDPS_FE_INTR_ERR_DEB_MASK 0x0040U /**< Data End Bit Error */
-#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK 0x0080U /**< Current Limit Error */
-#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK 0x0100U /**< Auto CMD Error */
-#define XSDPS_FE_INTR_ERR_ADMA_MASK 0x0200U /**< ADMA Error */
-#define XSDPS_FE_INTR_ERR_TR_MASK 0x1000U /**< Target Response */
-#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK 0xE000U /**< Vendor Specific
- Error */
-
-/** @} */
-
-/** @name ADMA Error Status Register
- *
- * This register is read only register which contains
- * status information about ADMA errors.
- * Read Only
- * @{
- */
-#define XSDPS_ADMA_ERR_MM_LEN_MASK 0x04U /**< ADMA Length Mismatch
- Error */
-#define XSDPS_ADMA_ERR_STATE_MASK 0x03U /**< ADMA Error State */
-#define XSDPS_ADMA_ERR_STATE_STOP_MASK 0x00U /**< ADMA Error State
- STOP */
-#define XSDPS_ADMA_ERR_STATE_FDS_MASK 0x01U /**< ADMA Error State
- FDS */
-#define XSDPS_ADMA_ERR_STATE_TFR_MASK 0x03U /**< ADMA Error State
- TFR */
-/** @} */
-
-/** @name Preset Values Register
- *
- * This register is read only register which contains
- * preset values for each of speed modes.
- * Read Only
- * @{
- */
-#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK 0x03FFU /**< SDCLK Frequency
- Select Value */
-#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK 0x0400U /**< Clock Generator
- Mode Select */
-#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK 0xC000U /**< Driver Strength
- Select Value */
-
-/** @} */
-
-/** @name Slot Interrupt Status Register
- *
- * This register is read only register which contains
- * interrupt slot signal for each slot.
- * Read Only
- * @{
- */
-#define XSDPS_SLOT_INTR_STS_INT_MASK 0x0007U /**< Interrupt Signal
- mask */
-
-/** @} */
-
-/** @name Host Controller Version Register
- *
- * This register is read only register which contains
- * Host Controller and Vendor Specific version.
- * Read Only
- * @{
- */
-#define XSDPS_HC_VENDOR_VER 0xFF00U /**< Vendor
- Specification
- version mask */
-#define XSDPS_HC_SPEC_VER_MASK 0x00FFU /**< Host
- Specification
- version mask */
-#define XSDPS_HC_SPEC_V3 0x0002U /**< HC spec version 3 */
-#define XSDPS_HC_SPEC_V2 0x0001U /**< HC spec version 2 */
-#define XSDPS_HC_SPEC_V1 0x0000U /**< HC spec version 1 */
-/** @} */
-
-/** @name Block size mask for 512 bytes
- *
- * Block size mask for 512 bytes - This is the default block size.
- * @{
- */
-
-#define XSDPS_BLK_SIZE_512_MASK 0x200U /**< Blk Size 512 */
-
-/** @} */
-
-/** @name Commands
- *
- * Constant definitions for commands and response related to SD
- * @{
- */
-/**
- * Command/Response related to SD/eMMC
- */
-
-#define XSDPS_APP_CMD_PREFIX 0x8000U
-#define CMD0 0x0000U
-#define CMD1 0x0100U
-#define CMD2 0x0200U
-#define CMD3 0x0300U
-#define CMD4 0x0400U
-#define CMD5 0x0500U
-#define CMD6 0x0600U
-#define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600U)
-#define CMD7 0x0700U
-#define CMD8 0x0800U
-#define CMD9 0x0900U
-#define CMD10 0x0A00U
-#define CMD11 0x0B00U
-#define CMD12 0x0C00U
-#define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00U)
-#define CMD16 0x1000U
-#define CMD17 0x1100U
-#define CMD18 0x1200U
-#define CMD19 0x1300U
-#define CMD21 0x1500U
-#define CMD23 0x1700U
-#define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700U)
-#define CMD24 0x1800U
-#define CMD25 0x1900U
-#define CMD41 0x2900U
-#define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900U)
-#define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00U)
-#define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300U)
-#define CMD52 0x3400U
-#define CMD55 0x3700U
-#define CMD58 0x3A00U
-
-#define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK
-#define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
- (u32)XSDPS_CMD_INX_CHK_EN_MASK
-
-#define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
- (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
-
-#define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
-#define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK
-
-#define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
- (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
-
-/** @} */
-
-/**
- * @name Card Interface
- * @{
- */
-/**
- * Card Interface Conditions Definitions
- */
-#define XSDPS_CIC_CHK_PATTERN 0xAAU
-#define XSDPS_CIC_VOLT_MASK (0xFU<<8)
-#define XSDPS_CIC_VOLT_2V7_3V6 (1U<<8)
-#define XSDPS_CIC_VOLT_LOW (1U<<9)
-/** @} */
-
-/**
- * @name OCR
- * @{
- */
-/**
- * Operation Conditions Register Definitions
- */
-#define XSDPS_OCR_PWRUP_STS (1U<<31)
-#define XSDPS_OCR_CC_STS (1U<<30)
-#define XSDPS_OCR_S18 (1U<<24)
-#define XSDPS_OCR_3V5_3V6 (1U<<23)
-#define XSDPS_OCR_3V4_3V5 (1U<<22)
-#define XSDPS_OCR_3V3_3V4 (1U<<21)
-#define XSDPS_OCR_3V2_3V3 (1U<<20)
-#define XSDPS_OCR_3V1_3V2 (1U<<19)
-#define XSDPS_OCR_3V0_3V1 (1U<<18)
-#define XSDPS_OCR_2V9_3V0 (1U<<17)
-#define XSDPS_OCR_2V8_2V9 (1U<<16)
-#define XSDPS_OCR_2V7_2V8 (1U<<15)
-#define XSDPS_OCR_1V7_1V95 (1U<<7)
-#define XSDPS_OCR_HIGH_VOL 0x00FF8000U
-#define XSDPS_OCR_LOW_VOL 0x00000080U
-/** @} */
-
-/**
- * @name Card Configuration
- * @{
- */
-/**
- * SD Card Configuration Register Definitions
- */
-#define XSDPS_SCR_REG_LEN 8U
-#define XSDPS_SCR_STRUCT_MASK (0xFU<<28)
-#define XSDPS_SCR_SPEC_MASK (0xFU<<24)
-#define XSDPS_SCR_SPEC_1V0 0U
-#define XSDPS_SCR_SPEC_1V1 (1U<<24)
-#define XSDPS_SCR_SPEC_2V0_3V0 (2U<<24)
-#define XSDPS_SCR_MEM_VAL_AF_ERASE (1U<<23)
-#define XSDPS_SCR_SEC_SUPP_MASK (7U<<20)
-#define XSDPS_SCR_SEC_SUPP_NONE 0U
-#define XSDPS_SCR_SEC_SUPP_1V1 (2U<<20)
-#define XSDPS_SCR_SEC_SUPP_2V0 (3U<<20)
-#define XSDPS_SCR_SEC_SUPP_3V0 (4U<<20)
-#define XSDPS_SCR_BUS_WIDTH_MASK (0xFU<<16)
-#define XSDPS_SCR_BUS_WIDTH_1 (1U<<16)
-#define XSDPS_SCR_BUS_WIDTH_4 (4U<<16)
-#define XSDPS_SCR_SPEC3_MASK (1U<<12)
-#define XSDPS_SCR_SPEC3_2V0 0U
-#define XSDPS_SCR_SPEC3_3V0 (1U<<12)
-#define XSDPS_SCR_CMD_SUPP_MASK 0x3U
-#define XSDPS_SCR_CMD23_SUPP (1U<<1)
-#define XSDPS_SCR_CMD20_SUPP (1U<<0)
-/** @} */
-
-/**
- * @name Card Status
- * @{
- */
-/**
- * Card Status Register Definitions
- */
-#define XSDPS_CD_STS_OUT_OF_RANGE (1U<<31)
-#define XSDPS_CD_STS_ADDR_ERR (1U<<30)
-#define XSDPS_CD_STS_BLK_LEN_ERR (1U<<29)
-#define XSDPS_CD_STS_ER_SEQ_ERR (1U<<28)
-#define XSDPS_CD_STS_ER_PRM_ERR (1U<<27)
-#define XSDPS_CD_STS_WP_VIO (1U<<26)
-#define XSDPS_CD_STS_IS_LOCKED (1U<<25)
-#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL (1U<<24)
-#define XSDPS_CD_STS_CMD_CRC_ERR (1U<<23)
-#define XSDPS_CD_STS_ILGL_CMD (1U<<22)
-#define XSDPS_CD_STS_CARD_ECC_FAIL (1U<<21)
-#define XSDPS_CD_STS_CC_ERR (1U<<20)
-#define XSDPS_CD_STS_ERR (1U<<19)
-#define XSDPS_CD_STS_CSD_OVRWR (1U<<16)
-#define XSDPS_CD_STS_WP_ER_SKIP (1U<<15)
-#define XSDPS_CD_STS_CARD_ECC_DIS (1U<<14)
-#define XSDPS_CD_STS_ER_RST (1U<<13)
-#define XSDPS_CD_STS_CUR_STATE (0xFU<<9)
-#define XSDPS_CD_STS_RDY_FOR_DATA (1U<<8)
-#define XSDPS_CD_STS_APP_CMD (1U<<5)
-#define XSDPS_CD_STS_AKE_SEQ_ERR (1U<<2)
-/** @} */
-
-/**
- * @name Switch function
- * @{
- */
-/**
- * Switch Function Definitions CMD6
- */
-#define XSDPS_SWITCH_SD_RESP_LEN 64U
-
-#define XSDPS_SWITCH_FUNC_SWITCH (1U<<31)
-#define XSDPS_SWITCH_FUNC_CHECK 0U
-/** @} */
-
-/**
- * @name Mode Function
- * @{
- */
-/**
- * Mode function groups definitions.
- */
-#define XSDPS_MODE_FUNC_GRP1 1U
-#define XSDPS_MODE_FUNC_GRP2 2U
-#define XSDPS_MODE_FUNC_GRP3 3U
-#define XSDPS_MODE_FUNC_GRP4 4U
-#define XSDPS_MODE_FUNC_GRP5 5U
-#define XSDPS_MODE_FUNC_GRP6 6U
-
-#define XSDPS_FUNC_GRP_DEF_VAL 0xFU
-#define XSDPS_FUNC_ALL_GRP_DEF_VAL 0xFFFFFFU
-/** @} */
-
-/**
- * @name Operating modes
- * @{
- */
-/**
- * SD operating modes in UHS.
- */
-#define XSDPS_ACC_MODE_DEF_SDR12 0U
-#define XSDPS_ACC_MODE_HS_SDR25 1U
-#define XSDPS_ACC_MODE_SDR50 2U
-#define XSDPS_ACC_MODE_SDR104 3U
-#define XSDPS_ACC_MODE_DDR50 4U
-/** @} */
-
-/**
- * @name General definitions
- * @{
- */
-/**
- * Definitions related to Driver strength, Current limit and
- * CSD specific data.
- */
-#define XSDPS_CMD_SYS_ARG_SHIFT 4U
-#define XSDPS_CMD_SYS_DEF 0U
-#define XSDPS_CMD_SYS_eC 1U
-#define XSDPS_CMD_SYS_OTP 3U
-#define XSDPS_CMD_SYS_ASSD 4U
-#define XSDPS_CMD_SYS_VEND 5U
-
-#define XSDPS_DRV_TYPE_ARG_SHIFT 8U
-#define XSDPS_DRV_TYPE_B 0U
-#define XSDPS_DRV_TYPE_A 1U
-#define XSDPS_DRV_TYPE_C 2U
-#define XSDPS_DRV_TYPE_D 3U
-
-#define XSDPS_CUR_LIM_ARG_SHIFT 12U
-#define XSDPS_CUR_LIM_200 0U
-#define XSDPS_CUR_LIM_400 1U
-#define XSDPS_CUR_LIM_600 2U
-#define XSDPS_CUR_LIM_800 3U
-
-#define CSD_SPEC_VER_MASK 0x3C0000U
-#define READ_BLK_LEN_MASK 0x00000F00U
-#define C_SIZE_MULT_MASK 0x00000380U
-#define C_SIZE_LOWER_MASK 0xFFC00000U
-#define C_SIZE_UPPER_MASK 0x00000003U
-#define CSD_STRUCT_MASK 0x00C00000U
-#define CSD_V2_C_SIZE_MASK 0x3FFFFF00U
-/** @} */
-
-/**
- * @name Extended Card Specific Data
- * @{
- */
-/**
- * EXT_CSD field definitions
- */
-#define XSDPS_EXT_CSD_SIZE 512U
-
-#define EXT_CSD_WR_REL_PARAM_EN (1U<<2)
-
-#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40U)
-#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10U)
-#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04U)
-#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01U)
-
-#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7U)
-#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1U)
-#define EXT_CSD_PART_CONFIG_ACC_BOOT1 (0x2U)
-#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U)
-#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U)
-#define EXT_CSD_PART_CONFIG_BYTE (179U)
-#define XSDPS_MMC_PART_CFG_0_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
- | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
- | ((u32)(0U) << 8U))
-
-#define XSDPS_MMC_PART_CFG_1_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
- | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
- | ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT0 << 8U))
-
-#define XSDPS_MMC_PART_CFG_2_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
- | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
- | ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT1 << 8U))
-
-#define EXT_CSD_PART_SUPPORT_PART_EN (0x1U)
-
-#define EXT_CSD_CMD_SET_NORMAL (1U<<0)
-#define EXT_CSD_CMD_SET_SECURE (1U<<1)
-#define EXT_CSD_CMD_SET_CPSECURE (1U<<2)
-
-#define EXT_CSD_CARD_TYPE_26 (1U<<0) /* Card can run at 26MHz */
-#define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */
-#define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */
-#define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */
- /* DDR mode @1.8V or 3V I/O */
-#define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */
- /* DDR mode @1.2V I/O */
-#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
- | EXT_CSD_CARD_TYPE_DDR_1_2V)
-#define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */
-#define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */
- /* SDR mode @1.2V I/O */
-#define EXT_CSD_BUS_WIDTH_BYTE 183U
-#define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */
-#define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */
-#define EXT_CSD_BUS_WIDTH_8_BIT 2U /* Card is in 8 bit mode */
-#define EXT_CSD_BUS_WIDTH_DDR_4_BIT 5U /* Card is in 4 bit DDR mode */
-#define EXT_CSD_BUS_WIDTH_DDR_8_BIT 6U /* Card is in 8 bit DDR mode */
-
-#define EXT_CSD_HS_TIMING_BYTE 185U
-#define EXT_CSD_HS_TIMING_DEF 0U
-#define EXT_CSD_HS_TIMING_HIGH 1U /* Card is in high speed mode */
-#define EXT_CSD_HS_TIMING_HS200 2U /* Card is in HS200 mode */
-
-#define EXT_CSD_RST_N_FUN_BYTE 162U
-#define EXT_CSD_RST_N_FUN_TEMP_DIS 0U /* RST_n signal is temporarily disabled */
-#define EXT_CSD_RST_N_FUN_PERM_EN 1U /* RST_n signal is permanently enabled */
-#define EXT_CSD_RST_N_FUN_PERM_DIS 2U /* RST_n signal is permanently disabled */
-
-#define XSDPS_EXT_CSD_CMD_SET 0U
-#define XSDPS_EXT_CSD_SET_BITS 1U
-#define XSDPS_EXT_CSD_CLR_BITS 2U
-#define XSDPS_EXT_CSD_WRITE_BYTE 3U
-/** @} */
-
-/**
- * @name SD/eMMC Bus Speed and Bus Width Arguments
- * @{
- */
-/**
- * SD/MMC Arguments for Bus Speed and Bus Width.
- */
-#define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
- | ((u32)EXT_CSD_HS_TIMING_DEF << 8))
-
-#define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
- | ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
-
-#define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
- | ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
-
-#define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8))
-
-#define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
-
-#define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
-
-#define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
-
-#define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
-
-#define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
- | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
-
-#define XSDPS_MMC_DELAY_FOR_SWITCH 1000U
-
-/** @} */
-
-/**
- * @name General Delay definitions
- * @{
- */
-/**
- * @400KHz, in usec
- */
-#define XSDPS_74CLK_DELAY 2960U
-#define XSDPS_100CLK_DELAY 4000U
-#define XSDPS_INIT_DELAY 10000U
-/** @} */
-
-#define XSDPS_DEF_VOLT_LVL XSDPS_PC_BUS_VSEL_3V0_MASK /**< Default voltage level */
-#define XSDPS_CARD_DEF_ADDR 0x1234U /**< Card Default address */
-
-#define XSDPS_CARD_SD 1U /**< SD card */
-#define XSDPS_CARD_MMC 2U /**< MMC card */
-#define XSDPS_CARD_SDIO 3U /**< SDIO card */
-#define XSDPS_CARD_SDCOMBO 4U /**< SDCOMBO card */
-#define XSDPS_CHIP_EMMC 5U /**< EMMC chip */
-
-
-/**
- *@name ADMA2 Descriptor related definitions
- * @{
- */
-/**
- * ADMA2 Descriptor related definitions
- */
-#define XSDPS_DESC_MAX_LENGTH 65536U
-
-#define XSDPS_DESC_VALID (0x1U << 0)
-#define XSDPS_DESC_END (0x1U << 1)
-#define XSDPS_DESC_INT (0x1U << 2)
-#define XSDPS_DESC_TRAN (0x2U << 4)
-
-/** @} */
-
-/* For changing clock frequencies */
-#define XSDPS_CLK_400_KHZ 400000U /**< 400 KHZ */
-#define XSDPS_CLK_50_MHZ 50000000U /**< 50 MHZ */
-#define XSDPS_CLK_52_MHZ 52000000U /**< 52 MHZ */
-#define XSDPS_SD_VER_1_0 0x1U /**< SD ver 1 */
-#define XSDPS_SD_VER_2_0 0x2U /**< SD ver 2 */
-#define XSDPS_SCR_BLKCNT 1U /**< SCR Block Count */
-#define XSDPS_SCR_BLKSIZE 8U /**< SCR Block Size */
-#define XSDPS_1_BIT_WIDTH 0x1U /**< Bus Width 1 */
-#define XSDPS_4_BIT_WIDTH 0x2U /**< Bus Width 4 */
-#define XSDPS_8_BIT_WIDTH 0x3U /**< Bus Width 8 */
-#define XSDPS_UHS_SPEED_MODE_SDR12 0x0U /**< SDR12 mode */
-#define XSDPS_UHS_SPEED_MODE_SDR25 0x1U /**< SDR25 mode */
-#define XSDPS_UHS_SPEED_MODE_SDR50 0x2U /**< SDR50 mode */
-#define XSDPS_UHS_SPEED_MODE_SDR104 0x3U /**< SDR104 mode */
-#define XSDPS_UHS_SPEED_MODE_DDR50 0x4U /**< DDR50 mode */
-#define XSDPS_HIGH_SPEED_MODE 0x5U /**< High Speed mode */
-#define XSDPS_DEFAULT_SPEED_MODE 0x6U /**< Default speed mode */
-#define XSDPS_HS200_MODE 0x7U /**< eMMC HS200 mode */
-#define XSDPS_DDR52_MODE 0x4U /**< eMMC DDR52 mode */
-#define XSDPS_SWITCH_CMD_BLKCNT 1U /**< Blk cnt for SWITCH cmd */
-#define XSDPS_SWITCH_CMD_BLKSIZE 64U /**< Blk sz for SWITCH cmd */
-#define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U /**< SWITCH cmd to Get HS */
-#define XSDPS_SWITCH_CMD_HS_SET 0x80FFFFF1U /**< SWITCH cmd to Set HS */
-#define XSDPS_SWITCH_CMD_SDR12_SET 0x80FFFFF0U /**< SWITCH cmd to Set SDR12 */
-#define XSDPS_SWITCH_CMD_SDR25_SET 0x80FFFFF1U /**< SWITCH cmd to Set SDR25 */
-#define XSDPS_SWITCH_CMD_SDR50_SET 0x80FFFFF2U /**< SWITCH cmd to Set SDR50 */
-#define XSDPS_SWITCH_CMD_SDR104_SET 0x80FFFFF3U /**< SWITCH cmd to Set SDR104 */
-#define XSDPS_SWITCH_CMD_DDR50_SET 0x80FFFFF4U /**< SWITCH cmd to Set DDR50 */
-#define XSDPS_EXT_CSD_CMD_BLKCNT 1U /**< Blk Cnt for EXT CSD */
-#define XSDPS_EXT_CSD_CMD_BLKSIZE 512U /**< Blk Sz for EXT CSD */
-#define XSDPS_TUNING_CMD_BLKCNT 1U /**< Blk Cnt for Tuning cmd */
-#define XSDPS_TUNING_CMD_BLKSIZE 64U /**< Blk Sz for Tuning cmd */
-#define XSDPS_SD_STATUS_BLKCNT 1U /**< Blk Cnt for SD status */
-#define XSDPS_SD_STATUS_BLKSIZE 64U /**< Blk Sz for SD status */
-
-#define XSDPS_HIGH_SPEED_MAX_CLK 50000000U /**< Max clk for HS mode */
-#define XSDPS_UHS_SDR104_MAX_CLK 208000000U /**< Max clk for SDR104 mode */
-#define XSDPS_UHS_SDR50_MAX_CLK 100000000U /**< Max clk for SDR50 mode */
-#define XSDPS_UHS_DDR50_MAX_CLK 50000000U /**< Max clk for DDR50 mode */
-#define XSDPS_UHS_SDR25_MAX_CLK 50000000U /**< Max clk for SDR25 mode */
-#define XSDPS_UHS_SDR12_MAX_CLK 25000000U /**< Max clk for SDR12 mode */
-
-#define SD_DRIVER_TYPE_B 0x01U /**< Driver Type B */
-#define SD_DRIVER_TYPE_A 0x02U /**< Driver Type A */
-#define SD_DRIVER_TYPE_C 0x04U /**< Driver Type C */
-#define SD_DRIVER_TYPE_D 0x08U /**< Driver Type D */
-#define SD_SET_CURRENT_LIMIT_200 0U /**< Current limit 200mA */
-#define SD_SET_CURRENT_LIMIT_400 1U /**< Current limit 400mA */
-#define SD_SET_CURRENT_LIMIT_600 2U /**< Current limit 600mA */
-#define SD_SET_CURRENT_LIMIT_800 3U /**< Current limit 800mA */
-
-#define SD_MAX_CURRENT_200 (1U << SD_SET_CURRENT_LIMIT_200) /**< Current limit 200mA Arg */
-#define SD_MAX_CURRENT_400 (1U << SD_SET_CURRENT_LIMIT_400) /**< Current limit 400mA Arg */
-#define SD_MAX_CURRENT_600 (1U << SD_SET_CURRENT_LIMIT_600) /**< Current limit 600mA Arg */
-#define SD_MAX_CURRENT_800 (1U << SD_SET_CURRENT_LIMIT_800) /**< Current limit 800mA Arg */
-
-#define XSDPS_SD_SDR12_MAX_CLK 25000000U /**< Max clk for SDR12 mode */
-#define XSDPS_SD_SDR25_MAX_CLK 50000000U /**< Max clk for SDR25 mode */
-#define XSDPS_SD_SDR50_MAX_CLK 100000000U /**< Max clk for SDR50 mode */
-#define XSDPS_SD_DDR50_MAX_CLK 50000000U /**< Max clk for DDR50 mode */
-#define XSDPS_SD_SDR104_MAX_CLK 208000000U /**< Max clk for SDR104 mode */
-/**
- * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller
- * than the clock value coming from the core. This value is kept to safely
- * switch to SDR104 mode if the SD card supports it.
- */
-#define XSDPS_SD_INPUT_MAX_CLK 175000000U
-
-#define XSDPS_MMC_HS200_MAX_CLK 200000000U /**< Max clk for MMC HS200 mode */
-#define XSDPS_MMC_HSD_MAX_CLK 52000000U /**< Max clk for MMC HSD mode */
-#define XSDPS_MMC_DDR_MAX_CLK 52000000U /**< Max clk for MMC DDR52 mode */
-
-/**
- * @name Card states
- * @{
- */
-/**
- * Definition for Card state.
- */
-#define XSDPS_CARD_STATE_IDLE 0U
-#define XSDPS_CARD_STATE_RDY 1U
-#define XSDPS_CARD_STATE_IDEN 2U
-#define XSDPS_CARD_STATE_STBY 3U
-#define XSDPS_CARD_STATE_TRAN 4U
-#define XSDPS_CARD_STATE_DATA 5U
-#define XSDPS_CARD_STATE_RCV 6U
-#define XSDPS_CARD_STATE_PROG 7U
-#define XSDPS_CARD_STATE_DIS 8U
-#define XSDPS_CARD_STATE_BTST 9U
-#define XSDPS_CARD_STATE_SLP 10U
-/** @} */
-
-#define XSDPS_SLOT_REM 0U /**< Removable slot */
-#define XSDPS_SLOT_EMB 1U /**< Embedded slot */
-
-#define XSDPS_WIDTH_8 8U /**< Bus width 8 */
-#define XSDPS_WIDTH_4 4U /**< Bus width 4 */
-
-/**
- * @name Tap delays
- * @{
- */
-/**
- * SD/eMMC ITAP and OTAP delays for different operating modes
- * for both Versal and ZynqMP platforms.
- */
-#ifdef versal
-#define SD_ITAPDLY_SEL_MASK 0x000000FFU
-#define SD_OTAPDLY_SEL_MASK 0x0000003FU
-#define SD_ITAPDLY 0x0000F0F8U
-#define SD_OTAPDLY 0x0000F0FCU
-#define SD0_DLL_CTRL 0x00000448U
-#define SD1_DLL_CTRL 0x000004C8U
-#define SD_DLL_RST 0x00000004U
-#define SD_ITAPCHGWIN 0x00000200U
-#define SD_ITAPDLYENA 0x00000100U
-#define SD_OTAPDLYENA 0x00000040U
-#define SD_OTAPDLYSEL_HS200_B0 0x00000002U
-#define SD_OTAPDLYSEL_HS200_B2 0x00000002U
-#define SD_ITAPDLYSEL_SD50 0x0000000EU
-#define SD_OTAPDLYSEL_SD50 0x00000003U
-#define SD_ITAPDLYSEL_SD_DDR50 0x00000036U
-#define SD_ITAPDLYSEL_EMMC_DDR50 0x0000001EU
-#define SD_OTAPDLYSEL_SD_DDR50 0x00000003U
-#define SD_OTAPDLYSEL_EMMC_DDR50 0x00000005U
-#define SD_ITAPDLYSEL_HSD 0x0000002CU
-#define SD_OTAPDLYSEL_SD_HSD 0x00000004U
-#define SD_OTAPDLYSEL_EMMC_HSD 0x00000005U
-#else
-#define SD0_ITAPDLY_SEL_MASK 0x000000FFU
-#define SD0_OTAPDLY_SEL_MASK 0x0000003FU
-#define SD1_ITAPDLY_SEL_MASK 0x00FF0000U
-#define SD1_OTAPDLY_SEL_MASK 0x003F0000U
-#define SD_DLL_CTRL 0x00000358U
-#define SD_ITAPDLY 0x00000314U
-#define SD_OTAPDLY 0x00000318U
-#define SD0_DLL_RST 0x00000004U
-#define SD1_DLL_RST 0x00040000U
-#define SD0_ITAPCHGWIN 0x00000200U
-#define SD0_ITAPDLYENA 0x00000100U
-#define SD0_OTAPDLYENA 0x00000040U
-#define SD1_ITAPCHGWIN 0x02000000U
-#define SD1_ITAPDLYENA 0x01000000U
-#define SD1_OTAPDLYENA 0x00400000U
-#define SD_OTAPDLYSEL_HS200_B0 0x00000003U
-#define SD_OTAPDLYSEL_HS200_B2 0x00000002U
-#define SD_ITAPDLYSEL_SD50 0x00000014U
-#define SD_OTAPDLYSEL_SD50 0x00000003U
-#define SD_ITAPDLYSEL_SD_DDR50 0x0000003DU
-#define SD_ITAPDLYSEL_EMMC_DDR50 0x00000012U
-#define SD_OTAPDLYSEL_SD_DDR50 0x00000004U
-#define SD_OTAPDLYSEL_EMMC_DDR50 0x00000006U
-#define SD_ITAPDLYSEL_HSD 0x00000015U
-#define SD_OTAPDLYSEL_SD_HSD 0x00000005U
-#define SD_OTAPDLYSEL_EMMC_HSD 0x00000006U
-#endif
-/** @} */
-
-#ifdef __MICROBLAZE__
-#define XPS_SYS_CTRL_BASEADDR 0xFF180000U /**< System controller Baseaddress */
-#endif
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#define XSdPs_In64 Xil_In64 /**< Low level 64-bit data read */
-#define XSdPs_Out64 Xil_Out64 /**< Low level 64-bit data write */
-
-#define XSdPs_In32 Xil_In32 /**< Low level 32-bit data read */
-#define XSdPs_Out32 Xil_Out32 /**< Low level 32-bit data write */
-
-#define XSdPs_In16 Xil_In16 /**< Low level 16-bit data read */
-#define XSdPs_Out16 Xil_Out16 /**< Low level 16-bit data write */
-
-#define XSdPs_In8 Xil_In8 /**< Low level 8-bit data read */
-#define XSdPs_Out8 Xil_Out8 /**< Low level 8-bit data write */
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param InstancePtr is the pointer to the sdps instance.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
-*
-******************************************************************************/
-#define XSdPs_ReadReg64(InstancePtr, RegOffset) \
- XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset)
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param InstancePtr is the pointer to the sdps instance.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
-* u64 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
- XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
- (RegisterValue))
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-#define XSdPs_ReadReg(BaseAddress, RegOffset) \
- XSdPs_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u32 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg >>= ((RegOffset & 0x3)*8);
- return (u16)Reg;
-#else
- return XSdPs_In16((BaseAddress) + (RegOffset));
-#endif
-}
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u16 RegisterValue)
-*
-******************************************************************************/
-
-static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg &= ~(0xFFFFU<<((RegOffset & 0x3)*8));
- Reg |= RegisterValue <<((RegOffset & 0x3)*8);
- XSdPs_Out32(BaseAddress, Reg);
-#else
- XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue));
-#endif
-}
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg >>= ((RegOffset & 0x3)*8);
- return (u8)Reg;
-#else
- return XSdPs_In8((BaseAddress) + (RegOffset));
-#endif
-}
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u8 RegisterValue)
-*
-******************************************************************************/
-static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg &= ~(0xFFU<<((RegOffset & 0x3)*8));
- Reg |= RegisterValue <<((RegOffset & 0x3)*8);
- XSdPs_Out32(BaseAddress, Reg);
-#else
- XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue));
-#endif
-}
-/***************************************************************************/
-/**
-* Macro to get present status register
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u8 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_GetPresentStatusReg(BaseAddress) \
- XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SD_HW_H_ */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/35/32f9f7545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/35/32f9f7545243001d18b399c1eb9b3628
deleted file mode 100644
index 8f62bbb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/35/32f9f7545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1711 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xsdps_host.c
-* @addtogroup sdps_v3_13
-* @{
-*
-* Contains the interface functions of the XSdPs driver.
-* See xsdps.h for a detailed description of the device and driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 3.9 mn 03/03/20 Restructured the code for more readability and modularity
-* mn 03/16/20 Add code to get card ID for MMC/eMMC
-* 3.10 mn 07/09/20 Modified code to prevent removing pull up on D3 line
-* mn 07/30/20 Read 16Bit value for Block Size Register
-* 3.11 sk 12/01/20 Tap programming sequence updates like disable OTAPEN
-* always, write zero to tap register for zero tap value.
-* sk 12/17/20 Removed checking platform specific SD macros and used
-* Baseaddress instead.
-* 3.13 sk 08/10/21 Limit the SD operating frequency to 19MHz for Versal.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xsdps_core.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-#if EL1_NONSECURE && defined (__aarch64__)
-void XSdps_Smc(XSdPs *InstancePtr, u32 RegOffset, u32 Mask, u32 Val)
-{
- (void)Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(InstancePtr->SlcrBaseAddr +
- RegOffset) | ((u64)Mask << 32),
- (u64)Val, 0, 0, 0, 0, 0);
-}
-#endif
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* Switches the SD card voltage from 3v3 to 1v8
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-******************************************************************************/
-s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr)
-{
- s32 Status;
-
- /* Setup the voltage switching sequence */
- Status = XSdPs_SetupVoltageSwitch(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Set the card voltage to 1.8V */
- Status = XSdPs_CardSetVoltage18(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Check if the bus is high */
- Status = XSdPs_CheckBusHigh(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function initiates the transfer to or from SD card.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure
-*
-******************************************************************************/
-s32 XSdPs_SetupTransfer(XSdPs *InstancePtr)
-{
- u32 PresentStateReg;
- s32 Status;
-
- if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
- ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
- != XSDPS_CAPS_EMB_SLOT)) {
- if(InstancePtr->Config.CardDetect != 0U) {
- /* Check status to ensure card is initialized */
- PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
- }
-
- /* Set block size to 512 if not already set */
- if(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
- Status = XSdPs_SetBlkSize(InstancePtr,
- XSDPS_BLK_SIZE_512_MASK);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function resets the SD card.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Value is the type of reset
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure
-*
-******************************************************************************/
-s32 XSdPs_Reset(XSdPs *InstancePtr, u8 Value)
-{
- s32 Status;
-
- /* "Software reset for all" is initiated */
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
- Value);
-
- Status = XSdPs_CheckResetDone(InstancePtr, Value);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function sets bit to start execution of tuning.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-void XSdPs_SetExecTuning(XSdPs *InstancePtr)
-{
- u16 CtrlReg;
-
- CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET);
- CtrlReg |= XSDPS_HC2_EXEC_TNG_MASK;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET, CtrlReg);
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function does SD mode initialization.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if initialization is successful
-* - XST_FAILURE if failure
-*
-******************************************************************************/
-s32 XSdPs_SdModeInit(XSdPs *InstancePtr)
-{
- s32 Status;
-#ifdef __ICCARM__
-#pragma data_alignment = 32
- static u8 SCR[8] = { 0U };
-#else
- static u8 SCR[8] __attribute__ ((aligned(32))) = { 0U };
-#endif
-#if SD_HS_MODE_ENABLE
- u8 ReadBuff[64] = { 0U };
-#endif
-
- Status = XSdPs_Get_BusWidth(InstancePtr, SCR);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if ((SCR[1] & WIDTH_4_BIT_SUPPORT) != 0U) {
- InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
- Status = XSdPs_Change_BusWidth(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
-#if SD_HS_MODE_ENABLE
- /* Get speed supported by device */
- Status = XSdPs_Get_BusSpeed(InstancePtr, ReadBuff);
- if (Status != XST_SUCCESS) {
- goto RETURN_PATH;
- }
-
- if (((SCR[2] & SCR_SPEC_VER_3) != 0U) &&
- (ReadBuff[13] >= UHS_SDR50_SUPPORT) &&
- (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8) &&
- (InstancePtr->Switch1v8 == 0U)) {
-
- InstancePtr->Switch1v8 = 1U;
-
- Status = XSdPs_CardSetVoltage18(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- if (InstancePtr->Switch1v8 != 0U) {
-
- /* Identify the UHS mode supported by card */
- XSdPs_Identify_UhsMode(InstancePtr, ReadBuff);
-
- Status = XSdPs_Change_BusSpeed(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } else {
- /*
- * card supports CMD6 when SD_SPEC field in SCR register
- * indicates that the Physical Layer Specification Version
- * is 1.10 or later. So for SD v1.0 cmd6 is not supported.
- */
- if (SCR[0] != 0U) {
- /* Check for high speed support */
- if (((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) &&
- (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
- InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
- InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD_HSD;
- InstancePtr->ITapDelay = SD_ITAPDLYSEL_HSD;
- Status = XSdPs_Change_BusSpeed(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
- }
- }
-#endif
-
- Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function does MMC mode initialization.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if initialization is successful
-* - XST_FAILURE if failure
-*
-******************************************************************************/
-s32 XSdPs_MmcModeInit(XSdPs *InstancePtr)
-{
- s32 Status;
-#ifdef __ICCARM__
-#pragma data_alignment = 32
- static u8 ExtCsd[512];
-#else
- static u8 ExtCsd[512] __attribute__ ((aligned(32)));
-#endif
-
- InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
- Status = XSdPs_Change_BusWidth(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24;
- InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16;
- InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8;
- InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1];
-
- if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
- EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) &&
- (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
- InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
- Status = XSdPs_Change_BusSpeed(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function does eMMC mode initialization.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if initialization is successful
-* - XST_FAILURE if failure
-*
-******************************************************************************/
-s32 XSdPs_EmmcModeInit(XSdPs *InstancePtr)
-{
- s32 Status;
-
-#ifdef __ICCARM__
-#pragma data_alignment = 32
- static u8 ExtCsd[512];
-#else
- static u8 ExtCsd[512] __attribute__ ((aligned(32)));
-#endif
-
- if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
- (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) {
- /* in case of eMMC data width 8-bit */
- InstancePtr->BusWidth = XSDPS_8_BIT_WIDTH;
- } else if (InstancePtr->Config.BusWidth == XSDPS_WIDTH_4) {
- /* in case of eMMC data width 4-bit */
- InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
- } else {
- /* in case of eMMC data width 1-bit */
- InstancePtr->BusWidth = XSDPS_1_BIT_WIDTH;
- }
-
- Status = XSdPs_Change_BusWidth(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Get Extended CSD */
- Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24;
- InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16;
- InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8;
- InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1];
-
- XSdPs_IdentifyEmmcMode(InstancePtr, ExtCsd);
-
- if (InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) {
- Status = XSdPs_Change_BusSpeed(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XSdPs_CheckEmmcTiming(InstancePtr, ExtCsd);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
- Status = XSdPs_Change_BusWidth(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
- }
-
- /* Enable Rst_n_Fun bit if it is disabled */
- if(ExtCsd[EXT_CSD_RST_N_FUN_BYTE] == EXT_CSD_RST_N_FUN_TEMP_DIS) {
- Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, XSDPS_MMC_RST_FUN_EN_ARG);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function disables the bus power.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-void XSdPs_DisableBusPower(XSdPs *InstancePtr)
-{
- /* Disable SD bus power and issue eMMC HW reset */
- if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_POWER_CTRL_OFFSET, XSDPS_PC_EMMC_HW_RST_MASK);
- } else {
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_POWER_CTRL_OFFSET, 0x0);
- }
-
- /* 1ms delay to poweroff card */
- (void)usleep(1000U);
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function enables the bus power.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-void XSdPs_EnableBusPower(XSdPs *InstancePtr)
-{
- /* Select voltage and enable bus power. */
- if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_POWER_CTRL_OFFSET,
- (XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK) &
- ~XSDPS_PC_EMMC_HW_RST_MASK);
- } else {
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_POWER_CTRL_OFFSET,
- XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK);
- }
-
- /* 0.2ms Delay after bus power on*/
- usleep(200);
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function enumerates the SD card.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_SdCardEnum(XSdPs *InstancePtr)
-{
- s32 Status;
-
- /* Check if the card is present */
- Status = XSdPs_CheckCardDetect(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Reset the SD card */
- Status = XSdPs_CardReset(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Get the card interface condition */
- Status = XSdPs_CardIfCond(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Get the card operating condition */
- Status = XSdPs_CardOpCond(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Get the card ID */
- Status = XSdPs_GetCardId(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Get the CSD register */
- Status = XSdPs_GetCsd(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Change clock to default clock 25MHz */
- /*
- * SD default speed mode timing should be closed at 19 MHz.
- * The reason for this is SD requires a voltage level shifter.
- * This limitation applies to ZynqMPSoC.
- */
- if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
- InstancePtr->BusSpeed = SD_CLK_19_MHZ;
- } else {
- InstancePtr->BusSpeed = SD_CLK_25_MHZ;
- }
- Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Select the card to transition to transfer state */
- Status = XSdPs_Select_Card(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function enumerates the MMC card.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_MmcCardEnum(XSdPs *InstancePtr)
-{
- s32 Status;
-
- /* Check if the card is preset */
- Status = XSdPs_CheckCardDetect(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Reset the card */
- Status = XSdPs_CardReset(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Get the card operating condition */
- Status = XSdPs_CardOpCond(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Get the card ID */
- Status = XSdPs_GetCardId(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Get the CSD register */
- Status = XSdPs_GetCsd(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Change clock to default clock 26MHz */
- InstancePtr->BusSpeed = SD_CLK_26_MHZ;
- Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Send select card command to transition to transfer state */
- Status = XSdPs_Select_Card(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function performs SD tuning.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
-{
- s32 Status;
-
-#ifndef versal
- /* Issue DLL Reset to load new SDHC tuned tap values */
- Status = XSdPs_DllReset(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
-#endif
-
- /* Perform the auto tuning */
- Status = XSdPs_AutoTuning(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
-#ifndef versal
- /* Issue DLL Reset to load new SDHC tuned tap values */
- Status = XSdPs_DllReset(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
-#endif
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to enable the clock.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param ClockReg is the clock value to be set.
-*
-* @return
-* - XST_SUCCESS if success
-* - XST_FAILURE if failure
-*
-******************************************************************************/
-s32 XSdPs_EnableClock(XSdPs *InstancePtr, u16 ClockReg)
-{
- u32 Timeout = 150000U;
- s32 Status;
- u16 ReadReg;
-
- ClockReg |= (u16)XSDPS_CC_INT_CLK_EN_MASK;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET, ClockReg);
-
- /* Wait for 150ms for internal clock to stabilize */
- do {
- ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- Timeout = Timeout - 1U;
- usleep(1);
- } while (((ReadReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U)
- && (Timeout != 0U));
-
- if (Timeout == 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- /* Enable SD clock */
- ClockReg |= XSDPS_CC_SD_CLK_EN_MASK;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET, ClockReg);
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to calculate the bus speed.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Arg is the argument to be sent along with the command.
-* This could be address or any other information
-*
-* @return
-* - XST_SUCCESS if success
-* - XST_FAILURE if failure
-*
-******************************************************************************/
-s32 XSdPs_CalcBusSpeed(XSdPs *InstancePtr, u32 *Arg)
-{
- s32 Status = XST_SUCCESS;
-
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
- switch (InstancePtr->Mode) {
- case XSDPS_UHS_SPEED_MODE_SDR12:
- *Arg = XSDPS_SWITCH_CMD_SDR12_SET;
- InstancePtr->BusSpeed = XSDPS_SD_SDR12_MAX_CLK;
- break;
- case XSDPS_UHS_SPEED_MODE_SDR25:
- *Arg = XSDPS_SWITCH_CMD_SDR25_SET;
- InstancePtr->BusSpeed = XSDPS_SD_SDR25_MAX_CLK;
- break;
- case XSDPS_UHS_SPEED_MODE_SDR50:
- *Arg = XSDPS_SWITCH_CMD_SDR50_SET;
- InstancePtr->BusSpeed = XSDPS_SD_SDR50_MAX_CLK;
- break;
- case XSDPS_UHS_SPEED_MODE_SDR104:
- *Arg = XSDPS_SWITCH_CMD_SDR104_SET;
- InstancePtr->BusSpeed = XSDPS_SD_SDR104_MAX_CLK;
- break;
- case XSDPS_UHS_SPEED_MODE_DDR50:
- *Arg = XSDPS_SWITCH_CMD_DDR50_SET;
- InstancePtr->BusSpeed = XSDPS_SD_DDR50_MAX_CLK;
- break;
- case XSDPS_HIGH_SPEED_MODE:
- *Arg = XSDPS_SWITCH_CMD_HS_SET;
- InstancePtr->BusSpeed = XSDPS_CLK_50_MHZ;
- break;
- default:
- Status = XST_FAILURE;
- break;
- }
- } else {
- switch (InstancePtr->Mode) {
- case XSDPS_HS200_MODE:
- *Arg = XSDPS_MMC_HS200_ARG;
- InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK;
- break;
- case XSDPS_DDR52_MODE:
- *Arg = XSDPS_MMC_HIGH_SPEED_ARG;
- InstancePtr->BusSpeed = XSDPS_MMC_DDR_MAX_CLK;
- break;
- case XSDPS_HIGH_SPEED_MODE:
- *Arg = XSDPS_MMC_HIGH_SPEED_ARG;
- InstancePtr->BusSpeed = XSDPS_MMC_HSD_MAX_CLK;
- break;
- default:
- Status = XST_FAILURE;
- break;
- }
- }
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to do the DMA transfer to or from SD card.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param BlkCnt - Block count passed by the user.
-* @param BlkSize - Block size passed by the user.
-* @param Buff - Pointer to the data buffer for a DMA transfer.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because another transfer
-* is in progress or command or data inhibit is set
-*
-******************************************************************************/
-void XSdPs_SetupReadDma(XSdPs *InstancePtr, u16 BlkCnt, u16 BlkSize, u8 *Buff)
-{
- BlkSize &= XSDPS_BLK_SIZE_MASK;
-
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_SIZE_OFFSET, BlkSize);
-
- if (InstancePtr->Dma64BitAddr >= ADDRESS_BEYOND_32BIT) {
- XSdPs_SetupADMA2DescTbl64Bit(InstancePtr, BlkCnt);
- } else {
- XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
- if (InstancePtr->Config.IsCacheCoherent == 0U) {
- Xil_DCacheInvalidateRange((INTPTR)Buff,
- (INTPTR)BlkCnt * BlkSize);
- }
- }
-
- if (BlkCnt == 1U) {
- InstancePtr->TransferMode = XSDPS_TM_BLK_CNT_EN_MASK |
- XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
- } else {
- InstancePtr->TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK |
- XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK |
- XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK;
- }
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to do the DMA transfer to or from SD card.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param BlkCnt - Block count passed by the user.
-* @param BlkSize - Block size passed by the user.
-* @param Buff - Pointer to the data buffer for a DMA transfer.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because another transfer
-* is in progress or command or data inhibit is set
-*
-******************************************************************************/
-void XSdPs_SetupWriteDma(XSdPs *InstancePtr, u16 BlkCnt, u16 BlkSize, const u8 *Buff)
-{
- BlkSize &= XSDPS_BLK_SIZE_MASK;
-
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_SIZE_OFFSET, BlkSize);
-
- if (InstancePtr->Dma64BitAddr >= ADDRESS_BEYOND_32BIT) {
- XSdPs_SetupADMA2DescTbl64Bit(InstancePtr, BlkCnt);
- } else {
- XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
- if (InstancePtr->Config.IsCacheCoherent == 0U) {
- Xil_DCacheFlushRange((INTPTR)Buff,
- (INTPTR)BlkCnt * BlkSize);
- }
- }
-
- if (BlkCnt == 1U) {
- InstancePtr->TransferMode = XSDPS_TM_BLK_CNT_EN_MASK |
- XSDPS_TM_DMA_EN_MASK;
- } else {
- InstancePtr->TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK |
- XSDPS_TM_BLK_CNT_EN_MASK |
- XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to setup ADMA2 descriptor table for 32-bit DMA
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param BlkCnt - block count.
-* @param Buff pointer to data buffer.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-void XSdPs_Setup32ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
-{
-#ifdef __ICCARM__
-#pragma data_alignment = 32
- static XSdPs_Adma2Descriptor32 Adma2_DescrTbl[32];
-#else
- static XSdPs_Adma2Descriptor32 Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
-#endif
- u32 TotalDescLines;
- u64 DescNum;
- u32 BlkSize;
-
- /* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */
- BlkSize = (u32)XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_SIZE_OFFSET) &
- XSDPS_BLK_SIZE_MASK;
-
- if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) {
- TotalDescLines = 1U;
- } else {
- TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH);
- if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) {
- TotalDescLines += 1U;
- }
- }
-
- for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) {
- Adma2_DescrTbl[DescNum].Address =
- (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
- Adma2_DescrTbl[DescNum].Attribute =
- XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
- Adma2_DescrTbl[DescNum].Length = 0U;
- }
-
- Adma2_DescrTbl[TotalDescLines-1].Address =
- (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
-
- Adma2_DescrTbl[TotalDescLines-1].Attribute =
- XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
-
- Adma2_DescrTbl[TotalDescLines-1].Length =
- (u16)((BlkCnt*BlkSize) - (u32)(DescNum*XSDPS_DESC_MAX_LENGTH));
-
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
- (u32)((UINTPTR)&(Adma2_DescrTbl[0]) & (u32)~0x0));
-
- if (InstancePtr->Config.IsCacheCoherent == 0U) {
- Xil_DCacheFlushRange((INTPTR)&(Adma2_DescrTbl[0]),
- sizeof(XSdPs_Adma2Descriptor32) * 32U);
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to setup ADMA2 descriptor table for 64-bit DMA
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param BlkCnt - block count.
-* @param Buff pointer to data buffer.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-void XSdPs_Setup64ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
-{
-#ifdef __ICCARM__
-#pragma data_alignment = 32
- static XSdPs_Adma2Descriptor64 Adma2_DescrTbl[32];
-#else
- static XSdPs_Adma2Descriptor64 Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
-#endif
- u32 TotalDescLines;
- u64 DescNum;
- u32 BlkSize;
-
- /* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */
- BlkSize = (u32)XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_SIZE_OFFSET) &
- XSDPS_BLK_SIZE_MASK;
-
- if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) {
- TotalDescLines = 1U;
- } else {
- TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH);
- if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) {
- TotalDescLines += 1U;
- }
- }
-
- for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) {
- Adma2_DescrTbl[DescNum].Address =
- ((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
- Adma2_DescrTbl[DescNum].Attribute =
- XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
- Adma2_DescrTbl[DescNum].Length = 0U;
- }
-
- Adma2_DescrTbl[TotalDescLines-1].Address =
- (u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
-
- Adma2_DescrTbl[TotalDescLines-1].Attribute =
- XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
-
- Adma2_DescrTbl[TotalDescLines-1].Length =
- (u16)((BlkCnt*BlkSize) - (u32)(DescNum*XSDPS_DESC_MAX_LENGTH));
-
-#if defined(__aarch64__) || defined(__arch64__)
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_EXT_OFFSET,
- (u32)((UINTPTR)(Adma2_DescrTbl)>>32U));
-#endif
-
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
- (u32)((UINTPTR)&(Adma2_DescrTbl[0]) & (u32)~0x0));
-
- if (InstancePtr->Config.IsCacheCoherent == 0U) {
- Xil_DCacheFlushRange((INTPTR)&(Adma2_DescrTbl[0]),
- sizeof(XSdPs_Adma2Descriptor64) * 32U);
- }
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used calculate the clock divisor value.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param SelFreq is the selected frequency
-*
-* @return Clock divisor value
-*
-******************************************************************************/
-u32 XSdPs_CalcClock(XSdPs *InstancePtr, u32 SelFreq)
-{
- u16 ClockVal = 0U;
- u16 DivCnt;
- u16 Divisor = 0U;
-
- if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
- /* Calculate divisor */
- for (DivCnt = 0x1U; DivCnt <= XSDPS_CC_EXT_MAX_DIV_CNT; DivCnt++) {
- if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
- Divisor = DivCnt >> 1;
- break;
- }
- }
- } else {
- /* Calculate divisor */
- for (DivCnt = 0x1U; DivCnt <= XSDPS_CC_MAX_DIV_CNT; DivCnt <<= 1U) {
- if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
- Divisor = DivCnt / 2U;
- break;
- }
- }
- }
-
- ClockVal |= (Divisor & XSDPS_CC_SDCLK_FREQ_SEL_MASK) << XSDPS_CC_DIV_SHIFT;
- ClockVal |= ((Divisor >> 8U) & XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK) << XSDPS_CC_EXT_DIV_SHIFT;
-
- return ClockVal;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to Set or Reset the DLL
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param EnRst is a flag indicating whether to Assert or De-assert Reset.
-*
-* @return None
-*
-* @note This API is specific to ZynqMP platform.
-*
-******************************************************************************/
-void XSdPs_DllRstCtrl(XSdPs *InstancePtr, u8 EnRst)
-{
-#ifndef versal
- u32 BaseAddress;
- u32 DllCtrl;
-
- BaseAddress = InstancePtr->Config.BaseAddress;
- if (BaseAddress == XSDPS_ZYNQMP_SD0_BASE) {
-#if EL1_NONSECURE && defined (__aarch64__)
- (void)DllCtrl;
-
- XSdps_Smc(InstancePtr, SD_DLL_CTRL, SD0_DLL_RST, (EnRst == 1U) ? SD0_DLL_RST : 0U);
-#else
- DllCtrl = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_DLL_CTRL);
- if (EnRst == 1U) {
- DllCtrl |= SD0_DLL_RST;
- } else {
- DllCtrl &= ~SD0_DLL_RST;
- }
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_DLL_CTRL, DllCtrl);
-#endif
- } else {
-#if EL1_NONSECURE && defined (__aarch64__)
- (void)DllCtrl;
-
- XSdps_Smc(InstancePtr, SD_DLL_CTRL, SD1_DLL_RST, (EnRst == 1U) ? SD1_DLL_RST : 0U);
-#else
- DllCtrl = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_DLL_CTRL);
- if (EnRst == 1U) {
- DllCtrl |= SD1_DLL_RST;
- } else {
- DllCtrl &= ~SD1_DLL_RST;
- }
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_DLL_CTRL, DllCtrl);
-#endif
- }
-#else
- (void)InstancePtr;
- (void)EnRst;
-#endif
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* Function to configure the Tap Delays.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-void XSdPs_ConfigTapDelay(XSdPs *InstancePtr)
-{
- u32 BaseAddress;
- u32 TapDelay;
- u32 ITapDelay;
- u32 OTapDelay;
-
- BaseAddress = InstancePtr->Config.BaseAddress;
- TapDelay = 0U;
- ITapDelay = InstancePtr->ITapDelay;
- OTapDelay = InstancePtr->OTapDelay;
-
-#ifdef versal
- (void) BaseAddress;
- if (ITapDelay) {
- TapDelay = SD_ITAPCHGWIN;
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_ITAPDLY, TapDelay);
- /* Program the ITAPDLY */
- TapDelay |= SD_ITAPDLYENA;
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_ITAPDLY, TapDelay);
- TapDelay |= ITapDelay;
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_ITAPDLY, TapDelay);
- TapDelay &= ~SD_ITAPCHGWIN;
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_ITAPDLY, TapDelay);
- } else {
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_ITAPDLY, 0x0);
- }
-
- /* Program the OTAPDLY */
- if (OTapDelay) {
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_OTAPDLY, OTapDelay);
- } else {
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, SD_OTAPDLY, 0x0);
- }
-#else
- if (BaseAddress == XSDPS_ZYNQMP_SD0_BASE) {
-#if EL1_NONSECURE && defined (__aarch64__)
- (void)TapDelay;
- if (ITapDelay) {
- XSdps_Smc(InstancePtr, SD_ITAPDLY, SD0_ITAPCHGWIN, SD0_ITAPCHGWIN);
- XSdps_Smc(InstancePtr, SD_ITAPDLY, SD0_ITAPDLYENA, SD0_ITAPDLYENA);
- XSdps_Smc(InstancePtr, SD_ITAPDLY, SD0_ITAPDLY_SEL_MASK, ITapDelay);
- XSdps_Smc(InstancePtr, SD_ITAPDLY, SD0_ITAPCHGWIN, 0U);
- } else {
- XSdps_Smc(InstancePtr, SD_ITAPDLY, (SD0_ITAPDLY_SEL_MASK |
- SD0_ITAPCHGWIN | SD0_ITAPDLYENA), 0x0);
- }
- if (OTapDelay) {
- XSdps_Smc(InstancePtr, SD_OTAPDLY, SD0_OTAPDLY_SEL_MASK, OTapDelay);
- } else {
- XSdps_Smc(InstancePtr, SD_OTAPDLY, SD0_OTAPDLY_SEL_MASK, 0x0);
- }
-#else
- if (ITapDelay) {
- TapDelay = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY);
- TapDelay |= SD0_ITAPCHGWIN;
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay);
- /* Program the ITAPDLY */
- TapDelay |= SD0_ITAPDLYENA;
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay);
- TapDelay &= ~SD0_ITAPDLY_SEL_MASK;
- TapDelay |= ITapDelay;
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay);
- TapDelay &= ~SD0_ITAPCHGWIN;
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay);
- } else {
- TapDelay = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY);
- TapDelay &= ~(u32)(SD0_ITAPDLY_SEL_MASK | SD0_ITAPCHGWIN | SD0_ITAPDLYENA);
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay);
- }
- if (OTapDelay) {
- /* Program the OTAPDLY */
- TapDelay = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_OTAPDLY);
- TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
- TapDelay |= OTapDelay;
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_OTAPDLY, TapDelay);
- } else {
- TapDelay = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_OTAPDLY);
- TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_OTAPDLY, TapDelay);
- }
-#endif
- } else {
- ITapDelay = ITapDelay << 16U;
- OTapDelay = OTapDelay << 16U;
-#if EL1_NONSECURE && defined (__aarch64__)
- (void)TapDelay;
- if (ITapDelay) {
- XSdps_Smc(InstancePtr, SD_ITAPDLY, SD1_ITAPCHGWIN, SD1_ITAPCHGWIN);
- XSdps_Smc(InstancePtr, SD_ITAPDLY, SD1_ITAPDLYENA, SD1_ITAPDLYENA);
- XSdps_Smc(InstancePtr, SD_ITAPDLY, SD1_ITAPDLY_SEL_MASK, ITapDelay);
- XSdps_Smc(InstancePtr, SD_ITAPDLY, SD1_ITAPCHGWIN, 0U);
- } else {
- XSdps_Smc(InstancePtr, SD_ITAPDLY, (SD1_ITAPDLY_SEL_MASK |
- SD1_ITAPCHGWIN | SD1_ITAPDLYENA), 0x0);
- }
- if (OTapDelay) {
- XSdps_Smc(InstancePtr, SD_OTAPDLY, SD1_OTAPDLY_SEL_MASK, OTapDelay);
- } else {
- XSdps_Smc(InstancePtr, SD_OTAPDLY, SD1_OTAPDLY_SEL_MASK, 0x0);
- }
-#else
- if (ITapDelay) {
- TapDelay = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY);
- TapDelay |= SD1_ITAPCHGWIN;
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay);
- /* Program the ITAPDLY */
- TapDelay |= SD1_ITAPDLYENA;
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay);
- TapDelay &= ~SD1_ITAPDLY_SEL_MASK;
- TapDelay |= ITapDelay;
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay);
- TapDelay &= ~SD1_ITAPCHGWIN;
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay);
- } else {
- TapDelay = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY);
- TapDelay &= ~(u32)(SD1_ITAPDLY_SEL_MASK | SD1_ITAPCHGWIN | SD1_ITAPDLYENA);
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_ITAPDLY, TapDelay);
- }
- if (OTapDelay) {
- /* Program the OTAPDLY */
- TapDelay = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_OTAPDLY);
- TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
- TapDelay |= OTapDelay;
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_OTAPDLY, TapDelay);
- } else {
- TapDelay = XSdPs_ReadReg(InstancePtr->SlcrBaseAddr, SD_OTAPDLY);
- TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
- XSdPs_WriteReg(InstancePtr->SlcrBaseAddr, SD_OTAPDLY, TapDelay);
- }
-#endif
- }
-#endif /* versal */
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to set voltage to 1.8V.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if successful
-* - XST_FAILURE if failure
-*
-******************************************************************************/
-s32 XSdPs_SetVoltage18(XSdPs *InstancePtr)
-{
- s32 Status;
- u16 CtrlReg;
-
- /* Enabling 1.8V in controller */
- CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET);
- CtrlReg |= XSDPS_HC2_1V8_EN_MASK;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET,
- CtrlReg);
-
- /* Wait minimum 5mSec */
- (void)usleep(5000U);
-
- /* Check for 1.8V signal enable bit is cleared by Host */
- Status = XSdPs_CheckVoltage18(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used configure the Power Level.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-void XSdPs_ConfigPower(XSdPs *InstancePtr)
-{
- u8 PowerLevel;
-
- if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V3_MASK) != 0U) {
- PowerLevel = XSDPS_PC_BUS_VSEL_3V3_MASK;
- } else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V0_MASK) != 0U) {
- PowerLevel = XSDPS_PC_BUS_VSEL_3V0_MASK;
- } else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_1V8_MASK) != 0U) {
- PowerLevel = XSDPS_PC_BUS_VSEL_1V8_MASK;
- } else {
- PowerLevel = 0U;
- }
-
- /* Select voltage based on capability and enable bus power. */
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_POWER_CTRL_OFFSET,
- PowerLevel | XSDPS_PC_BUS_PWR_MASK);
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used configure the DMA.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-void XSdPs_ConfigDma(XSdPs *InstancePtr)
-{
- if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
- /* Enable ADMA2 in 64bit mode. */
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL1_OFFSET,
- XSDPS_HC_DMA_ADMA2_64_MASK);
- } else {
- /* Enable ADMA2 in 32bit mode. */
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL1_OFFSET,
- XSDPS_HC_DMA_ADMA2_32_MASK);
- }
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used configure the Interrupts.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-void XSdPs_ConfigInterrupt(XSdPs *InstancePtr)
-{
- /* Enable all interrupt status except card interrupt initially */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_EN_OFFSET,
- XSDPS_NORM_INTR_ALL_MASK & (~XSDPS_INTR_CARD_MASK));
-
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_EN_OFFSET,
- XSDPS_ERROR_INTR_ALL_MASK);
-
- /* Disable all interrupt signals by default. */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_SIG_EN_OFFSET, 0x0U);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_SIG_EN_OFFSET, 0x0U);
-
-}
-
-/*****************************************************************************/
-/**
-* This function does SD command generation.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Cmd is the command to be sent.
-* @param Arg is the argument to be sent along with the command.
-* This could be address or any other information
-* @param BlkCnt - Block count passed by the user.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because another transfer
-* is in progress or command or data inhibit is set
-*
-******************************************************************************/
-s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt)
-{
- u32 Timeout = 10000000U;
- u32 StatusReg;
- s32 Status;
-
- Status = XSdPs_SetupCmd(InstancePtr, Arg, BlkCnt);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XSdPs_SendCmd(InstancePtr, Cmd);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Polling for response for now */
- do {
- StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET);
- if ((Cmd == CMD21) || (Cmd == CMD19)) {
- if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET) & XSDPS_INTR_BRR_MASK) != 0U){
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_BRR_MASK);
- break;
- }
- }
-
- if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
- Status = (s32)XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET);
- if (((u32)Status & ~XSDPS_INTR_ERR_CT_MASK) == 0U) {
- Status = XSDPS_CT_ERROR;
- }
- /* Write to clear error bits */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET,
- XSDPS_ERROR_INTR_ALL_MASK);
- goto RETURN_PATH;
- }
- Timeout = Timeout - 1U;
- } while (((StatusReg & XSDPS_INTR_CC_MASK) == 0U)
- && (Timeout != 0U));
- /* Write to clear bit */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET,
- XSDPS_INTR_CC_MASK);
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-* This function is used to check if the transfer is completed successfully.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdps_CheckTransferDone(XSdPs *InstancePtr)
-{
- u32 Timeout = 5000000U;
- u16 StatusReg;
- s32 Status;
-
- /*
- * Check for transfer complete
- * Polling for response for now
- */
- do {
- StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET);
- if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
- /* Write to clear error bits */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET,
- XSDPS_ERROR_INTR_ALL_MASK);
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- Timeout = Timeout - 1U;
- usleep(1);
- } while (((StatusReg & XSDPS_INTR_TC_MASK) == 0U)
- && (Timeout != 0U));
-
- if (Timeout == 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- /* Write to clear bit */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to check if the CMD/DATA bus is idle or not.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Value is to selct Cmd bus or Dat bus
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_CheckBusIdle(XSdPs *InstancePtr, u32 Value)
-{
- u32 Timeout = 10000000U;
- u32 PresentStateReg;
- u32 StatusReg;
- s32 Status;
-
- PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- /* Check for Card Present */
- if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) != 0U) {
- /* Check for SD idle */
- do {
- StatusReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- Timeout = Timeout - 1;
- usleep(1);
- } while (((StatusReg & Value) != 0U)
- && (Timeout != 0U));
- }
-
- if (Timeout == 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function frames the Command register for a particular command.
-* Note that this generates only the command register value i.e.
-* the upper 16 bits of the transfer mode and command register.
-* This value is already shifted to be upper 16 bits and can be directly
-* OR'ed with transfer mode register value.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Cmd is the Command to be sent.
-*
-* @return Command register value complete with response type and
-* data, CRC and index related flags.
-*
-******************************************************************************/
-u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd)
-{
- u32 RetVal;
-
- RetVal = Cmd;
-
- switch(Cmd) {
- case CMD0:
- RetVal |= RESP_NONE;
- break;
- case CMD1:
- RetVal |= RESP_R3;
- break;
- case CMD2:
- RetVal |= RESP_R2;
- break;
- case CMD3:
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
- RetVal |= RESP_R6;
- } else {
- RetVal |= RESP_R1;
- }
- break;
- case CMD4:
- RetVal |= RESP_NONE;
- break;
- case CMD5:
- RetVal |= RESP_R1B;
- break;
- case CMD6:
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
- RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
- } else {
- RetVal |= RESP_R1B;
- }
- break;
- case ACMD6:
- RetVal |= RESP_R1;
- break;
- case CMD7:
- RetVal |= RESP_R1;
- break;
- case CMD8:
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
- RetVal |= RESP_R1;
- } else {
- RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
- }
- break;
- case CMD9:
- RetVal |= RESP_R2;
- break;
- case CMD11:
- case CMD10:
- case CMD12:
- RetVal |= RESP_R1;
- break;
- case ACMD13:
- RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
- break;
- case CMD16:
- RetVal |= RESP_R1;
- break;
- case CMD17:
- case CMD18:
- case CMD19:
- case CMD21:
- RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
- break;
- case CMD23:
- case ACMD23:
- case CMD24:
- case CMD25:
- RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
- break;
- case ACMD41:
- RetVal |= RESP_R3;
- break;
- case ACMD42:
- RetVal |= RESP_R1;
- break;
- case ACMD51:
- RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
- break;
- case CMD52:
- case CMD55:
- RetVal |= RESP_R1;
- break;
- case CMD58:
- break;
- default :
- RetVal |= Cmd;
- break;
- }
-
- return RetVal;
-}
-
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/35/907085595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/35/907085595243001d18b399c1eb9b3628
deleted file mode 100644
index 13d2cc5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/35/907085595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,59 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include "profile.h"
-
-/* XMD Initializes the following Global Variables Value during Program
- * Download with appropriate values. */
-
-#ifdef PROC_MICROBLAZE
-
-extern s32 microblaze_init(void);
-
-#elif defined PROC_PPC
-
-extern s32 powerpc405_init(void);
-
-#else
-
-extern s32 cortexa9_init(void);
-
-#endif
-
-s32 profile_version = 1; /* Version of S/W Intrusive Profiling library */
-
-u32 binsize = (u32)BINSIZE; /* Histogram Bin Size */
-u32 cpu_clk_freq = (u32)CPU_FREQ_HZ ; /* CPU Clock Frequency */
-u32 sample_freq_hz = (u32)SAMPLE_FREQ_HZ ; /* Histogram Sampling Frequency */
-u32 timer_clk_ticks = (u32)TIMER_CLK_TICKS ;/* Timer Clock Ticks for the Timer */
-
-/* Structure for Storing the Profiling Data */
-struct gmonparam *_gmonparam = (struct gmonparam *)(0xffffffffU);
-s32 n_gmon_sections = 1;
-
-/* This is the initialization code, which is called from the crtinit. */
-
-void _profile_init( void )
-{
-/* print("Gmon Init called....\r\n") */
-/* putnum(n_gmon_sections) , print("\r\n") */
-/* if( _gmonparam == 0xffffffff ) */
-/* printf("Gmonparam is NULL !!\r\n") */
-/* for( i = 0, i < n_gmon_sections, i++ )[ */
-/* putnum( _gmonparam[i].lowpc) , print("\t") */
-/* putnum( _gmonparam[i].highpc) , print("\r\n") */
-/* putnum( _gmonparam[i].textsize ), print("\r\n") */
-/* putnum( _gmonparam[i].kcountsize * sizeof(unsigned short)), print("\r\n") */
-/* ] */
-
-#ifdef PROC_MICROBLAZE
- (void)microblaze_init();
-#elif defined PROC_PPC
- powerpc405_init();
-#else
- (void)cortexa9_init();
-#endif
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/35/e0724f565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/35/e0724f565243001d18b399c1eb9b3628
deleted file mode 100644
index 08af00b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/35/e0724f565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,93 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/*****************************************************************************/
-/**
-* @file sleep.h
-*
-* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep
-* related APIs.
-*
-*
-* MODIFICATION HISTORY :
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 6.6 srm 11/02/17 Added processor specific sleep routines
-* function prototypes.
-*
-*
-*
-******************************************************************************/
-
-#ifndef SLEEP_H
-#define SLEEP_H
-
-#include "xil_types.h"
-#include "xil_io.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*****************************************************************************/
-/**
-*
-* This macro polls an address periodically until a condition is met or till the
-* timeout occurs.
-* The minimum timeout for calling this macro is 100us. If the timeout is less
-* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
-* If the timeout is not a multiple of 100us, it waits for a timeout of
-* the next usec value which is a multiple of 100us.
-*
-* @param IO_func - accessor function to read the register contents.
-* Depends on the register width.
-* @param ADDR - Address to be polled
-* @param VALUE - variable to read the value
-* @param COND - Condition to checked (usually involves VALUE)
-* @param TIMEOUT_US - timeout in micro seconds
-*
-* @return 0 - when the condition is met
-* -1 - when the condition is not met till the timeout period
-*
-* @note none
-*
-*****************************************************************************/
-#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
- ( { \
- u64 timeout = TIMEOUT_US/100; \
- if(TIMEOUT_US%100!=0) \
- timeout++; \
- for(;;) { \
- VALUE = IO_func(ADDR); \
- if(COND) \
- break; \
- else { \
- usleep(100); \
- timeout--; \
- if(timeout==0) \
- break; \
- } \
- } \
- (timeout>0) ? 0 : -1; \
- } )
-
-void usleep(unsigned long useconds);
-void sleep(unsigned int seconds);
-int usleep_R5(unsigned long useconds);
-unsigned sleep_R5(unsigned int seconds);
-int usleep_MB(unsigned long useconds);
-unsigned sleep_MB(unsigned int seconds);
-int usleep_A53(unsigned long useconds);
-unsigned sleep_A53(unsigned int seconds);
-int usleep_A9(unsigned long useconds);
-unsigned sleep_A9(unsigned int seconds);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/35/e323ee565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/35/e323ee565243001d18b399c1eb9b3628
deleted file mode 100644
index d1c27df..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/35/e323ee565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,765 +0,0 @@
-/******************************************************************************/
-/**
-* Copyright (c) 2019 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-* @file xil_util.c
-*
-* This file contains xil utility functions
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.4 mmd 04/21/19 First release.
-* 7.2 nava 08/01/20 Updated Xil_WaitForEvent() and Xil_WaitForEvents(()
-* API to use microsecond timeout instead of a free
-* counter.
-* 7.3 kal 06/30/20 Converted Xil_Ceil macro to API.
-* rpo 08/19/20 Added function for read,modify,write
-* kal 09/22/20 Changed the param type from const char to const char*
-* to avoid copying key onto stack
-* td 10/16/20 Added Xil_Strcpy, Xil_Strcat, Xil_SecureMemCpy and
-* Xil_MemCmp functions
-* 7.4 am 11/26/20 Added Xil_StrCpyRange function
-* 7.6 kpt 07/15/21 Added Xil_SecureZeroize function
-*
-*
-*
-*****************************************************************************/
-
-/****************************** Include Files *********************************/
-#include "xil_util.h"
-#include "sleep.h"
-
-/************************** Constant Definitions ****************************/
-#define MAX_NIBBLES 8U
-
-/************************** Function Prototypes *****************************/
-
-/******************************************************************************/
-/**
-* This API ceils the provided float value.
-*
-* @param Value is a float variable which has to ceiled to nearest
-* integer.
-*
-* @return Returns ceiled value.
-*
-*******************************************************************************/
-int Xil_Ceil(float Value)
-{
- int Result = Value;
-
- if (Value > Result) {
- Result = Result + 1;
- }
-
- return Result;
-}
-
-/****************************************************************************/
-/**
- * Converts the char into the equivalent nibble.
- * Ex: 'a' -> 0xa, 'A' -> 0xa, '9'->0x9
- *
- * @param InChar - Input character to be converted to nibble.
- * Valid characters are between 0-9, a-f, A-F
- * @param Num - Memory location where nibble is to be stored
- *
- * @return
- * XST_SUCCESS - Character converted to nibble
- * XST_FAILURE - Invalid input character
- *
- * @note None.
- *
- *****************************************************************************/
-
-u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num)
-{
- u32 Status;
-
- /* Convert the char to nibble */
- if ((InChar >= (u8)'0') && (InChar <= (u8)'9')) {
- *Num = InChar - (u8)'0';
- Status = XST_SUCCESS;
- }
- else if ((InChar >= (u8)'a') && (InChar <= (u8)'f')) {
- *Num = InChar - (u8)'a' + 10U;
- Status = XST_SUCCESS;
- }
- else if ((InChar >= (u8)'A') && (InChar <= (u8)'F')) {
- *Num = InChar - (u8)'A' + 10U;
- Status = XST_SUCCESS;
- }
- else {
- Status = XST_FAILURE;
- }
-
- return Status;
-}
-
-/****************************************************************************/
-/*
- * Converts the string into the equivalent Hex buffer.
- * Ex: "abc123" -> {0xab, 0xc1, 0x23}
- *
- * @param Str - Pointer to string to be converted to Hex.
- * Accepted characters in string are between 0-9, a-f and A-F
- * @param Buf - Pointer to memory location where converted hex values are to
- * be stored.
- * @param Len - Length of input string
- *
- * @return
- * XST_SUCCESS - Input string is converted to hex
- * XST_FAILURE - Invalid character in inpit string
- *
- * @note None.
- *
- *****************************************************************************/
-u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len)
-{
- u32 Status = XST_FAILURE;
- u8 ConvertedLen = 0U, index = 0U;
- u8 Nibble[MAX_NIBBLES] = {0U};
- u8 i;
-
- while (ConvertedLen < Len) {
- for (i = 0U; i < MAX_NIBBLES; i++) {
- Status = Xil_ConvertCharToNibble(Str[ConvertedLen],
- &Nibble[i]);
- ConvertedLen = ConvertedLen +1U;
- if (Status != XST_SUCCESS) {
- /* Error converting char to nibble */
- goto END;
- }
- }
-
- buf[index] = ((Nibble[0] << (u8)28U) | (Nibble[1] << (u8)24U) |
- (Nibble[2] << (u8)20U) | (Nibble[3] << (u8)16U) |
- (Nibble[4] << (u8)12U) | (Nibble[5] << (u8)8U) |
- (Nibble[6] << (u8)4U) | (u32)Nibble[7]);
- index++;
- }
-END:
- return Status;
-}
-
-/****************************************************************************/
-/*
- * Waits for the event
- *
- * @param RegAddr - Address of register to be checked for event(s) occurrence
- * @param EventMask - Mask indicating event(s) to be checked
- * @param Event - Specific event(s) value to be checked
- * @param Timeout - Max number of microseconds to wait for an event(s).
- *
- * @return
- * XST_SUCCESS - On occurrence of the event(s).
- * XST_FAILURE - Event did not occur before counter reaches 0
- *
- * @note None.
- *
- *****************************************************************************/
-u32 Xil_WaitForEvent(u32 RegAddr, u32 EventMask, u32 Event, u32 Timeout)
-{
- u32 EventStatus;
- u32 PollCount = Timeout;
- u32 Status = XST_FAILURE;
-
- while(PollCount > 0) {
- EventStatus = Xil_In32(RegAddr) & EventMask;
- if (EventStatus == Event) {
- Status = XST_SUCCESS;
- break;
- }
- PollCount--;
- usleep(1U);
- }
-
- return Status;
-}
-
-
-/******************************************************************************/
-/**
- * Waits for the events. Returns on occurrence of first event / timeout.
- *
- * @param EventsRegAddr - Address of register to be checked for event(s)
- * occurrence
- * @param EventsMask - Mask indicating event(s) to be checked
- * @param WaitEvents - Specific event(s) to be checked
- * @param Timeout - Max number of microseconds to wait for an event(s).
- * @param Events - Mask of Events occurred returned in memory pointed by
- * this variable
- *
- * @return
- * XST_SUCCESS - On occurrence of the event(s).
- * XST_FAILURE - Event did not occur before counter reaches 0
- *
- ******************************************************************************/
-u32 Xil_WaitForEvents(u32 EventsRegAddr, u32 EventsMask, u32 WaitEvents,
- u32 Timeout, u32* Events)
-{
- u32 EventStatus;
- u32 PollCount = Timeout;
- u32 Status = XST_TIMEOUT;
-
- *Events = 0x00;
- do {
- EventStatus = Xil_In32(EventsRegAddr);
- EventStatus &= EventsMask;
- if(EventStatus & WaitEvents) {
- Status = XST_SUCCESS;
- *Events = EventStatus;
- break;
- }
- PollCount--;
- usleep(1U);
- }
- while(PollCount > 0);
-
- return Status;
-}
-
-/******************************************************************************/
-/**
- * Checks whether the passed character is a valid hex digit
- *
- * @param Ch - Pointer to the input character
- *
- * @return
- * XST_SUCCESS - on valid hex digit
- * XST_FAILURE - on invalid hex digit
- *
- * @note None.
- *
- ******************************************************************************/
-u32 Xil_IsValidHexChar(const char *Ch)
-{
- u32 Status = XST_FAILURE;
-
- if(NULL == Ch) {
- goto END;
- }
- if ((*Ch >= '0' && *Ch <='9')||
- (*Ch >= 'a' && *Ch <='f')||
- (*Ch >= 'A' && *Ch <='F')) {
-
- Status = XST_SUCCESS;
- }
-END:
- return Status;
-}
-
-/******************************************************************************/
-/**
- * Validate the input string contains only hexadecimal characters
- *
- * @param HexStr - Pointer to string to be validated
- *
- * @return
- * XST_SUCCESS - On valid input hex string
- * XST_INVALID_PARAM - On invalid length of the input string
- * XST_FAILURE - On non hexadecimal character in string
- *
- * @note None
- *
- ******************************************************************************/
-u32 Xil_ValidateHexStr(const char *HexStr)
-{
- u32 Idx;
- u32 Len;
- u32 Status = XST_INVALID_PARAM;
-
- if(NULL == HexStr) {
- goto END;
- }
-
- Len = Xil_Strnlen(HexStr, XIL_MAX_HEX_STR_LEN + 1U);
- if (Len > XIL_MAX_HEX_STR_LEN) {
- goto END;
- }
-
- for (Idx = 0U; Idx < Len; Idx++) {
- Status = Xil_IsValidHexChar(&HexStr[Idx]);
- if (Status != XST_SUCCESS) {
- break;
- }
- }
-
-END:
- return Status;
-}
-
-/****************************************************************************/
-/**
- * Converts the string into the equivalent Hex buffer.
- * Ex: "abc123" -> {0xab, 0xc1, 0x23}
- *
- * @param Str is a Input String. Will support the lower and upper case values.
- * Value should be between 0-9, a-f and A-F
- * @param Buf is Output buffer.
- * @param Len of the input string. Should have even values
- *
- * @return
- * - XST_SUCCESS no errors occurred.
- * - XST_FAILURE an error when input parameters are not valid
- * - an error when input buffer has invalid values
- *
- * TDD Test Cases:
- * ---Initialization---
- * Len is odd
- * Len is zero
- * Str is NULL
- * Buf is NULL
- * ---Functionality---
- * Str input with only numbers
- * Str input with All values in A-F
- * Str input with All values in a-f
- * Str input with values in a-f, 0-9, A-F
- * Str input with values in a-z, 0-9, A-Z
- * Boundary Cases
- * Memory Bounds of buffer checking
- * ****************************************************************************/
-u32 Xil_ConvertStringToHexBE(const char *Str, u8 *Buf, u32 Len)
-{
- u32 ConvertedLen;
- u8 LowerNibble = 0U;
- u8 UpperNibble = 0U;
- u32 Status = (u32)XST_FAILURE;
-
- if ((Str == NULL) || (Buf == NULL)) {
- Status = (u32)XST_INVALID_PARAM;
- goto END;
- }
-
- if ((Len == 0U) || ((Len % XIL_SIZE_OF_BYTE_IN_BITS) != 0U)) {
- Status = (u32)XST_INVALID_PARAM;
- goto END;
- }
-
- if(Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) {
- Status = (u32)XST_INVALID_PARAM;
- goto END;
- }
-
- ConvertedLen = 0U;
- while (ConvertedLen < (Len / XIL_SIZE_OF_NIBBLE_IN_BITS)) {
- if (Xil_ConvertCharToNibble(Str[ConvertedLen],&UpperNibble)
- == (u32)XST_SUCCESS) {
- if (Xil_ConvertCharToNibble(Str[ConvertedLen+1],
- &LowerNibble) == (u32)XST_SUCCESS) {
- Buf[ConvertedLen/2] =
- (UpperNibble << XIL_SIZE_OF_NIBBLE_IN_BITS) |
- LowerNibble;
- }
- else {
- Status = (u32)XST_INVALID_PARAM;
- goto END;
- }
- }
- else {
- Status = (u32)XST_INVALID_PARAM;
- goto END;
- }
- ConvertedLen += 2U;
- }
- Status = (u32)XST_SUCCESS;
-END:
- return Status;
-}
-
-/******************************************************************************/
-/**
- * Converts the string into the equivalent Hex buffer.
- * Ex: "abc123" -> {0x23, 0xc1, 0xab}
- *
- * @param Str - Input String to be converted to hex number in little
- * endian format. Valid characters of input strin are between
- * 0-9, a-f and A-F
- * @param Buf - Pointer to memory location where converted hex numbers are to
- * be stored.
- * @param Len - Expected number of output bits
- *
- * @return
- * XST_SUCCESS - Input string is converted to hex number(s)
- * XST_FAILURE - Invalid input character detected in input string
- *
- * @note
- *
- ******************************************************************************/
-u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len)
-{
- u32 ConvertedLen;
- u8 LowerNibble = 0U;
- u8 UpperNibble = 0U;
- u32 StrIndex;
- u32 Status = XST_FAILURE;
-
- if ((NULL == Str) || (NULL == Buf)) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- if ((Len == 0U) || ((Len % XIL_SIZE_OF_BYTE_IN_BITS) != 0U)) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- if(Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- StrIndex = (Len / XIL_SIZE_OF_BYTE_IN_BITS) - 1U;
- ConvertedLen = 0U;
- while (ConvertedLen < (Len / XIL_SIZE_OF_NIBBLE_IN_BITS)) {
- Status = Xil_ConvertCharToNibble(Str[ConvertedLen],
- &UpperNibble);
- if (XST_SUCCESS == Status) {
- Status = Xil_ConvertCharToNibble(Str[ConvertedLen + 1],
- &LowerNibble);
- if (XST_SUCCESS == Status) {
- Buf[StrIndex] =
- (UpperNibble << XIL_SIZE_OF_NIBBLE_IN_BITS) |
- LowerNibble;
- StrIndex = StrIndex - 1U;
- }
- else {
- Status = XST_INVALID_PARAM;
- goto END;
- }
- }
- else {
- Status = XST_INVALID_PARAM;
- goto END;
- }
- ConvertedLen += 2U;
- }
-
- Status = XST_SUCCESS;
-END:
- return Status;
-}
-
-/******************************************************************************/
-/**
- * Returns the length of input string.
- *
- * @param Str - Input string
- * @param MaxLen - Maximum expected length of the input string
- *
- * @return
- * Returns length of the input string if length is less than MaxLen.
- * Returns MaxLen if the length of the input string is >= MaxLen.
- *
- * @note
- *
- ******************************************************************************/
-u32 Xil_Strnlen(const char *Str, u32 MaxLen)
-{
- const char *InStr = Str;
- u32 StrLen = 0U;
-
- if (NULL == Str) {
- goto END;
- }
-
- while(StrLen < MaxLen) {
- if ('\0' == *InStr) {
- break;
- }
- StrLen++;
- InStr++;
- }
-
-END:
- return StrLen;
-}
-
-/*****************************************************************************/
-/**
- * @brief This function will Read, Modify and Write to an address.
- *
- * @param Addr denotes Address
- * @param Mask denotes the bits to be modified
- * @param Value is the value to be written to the address
- *
- * @return None
- *
- *****************************************************************************/
-void Xil_UtilRMW32(u32 Addr, u32 Mask, u32 Value)
-{
- u32 Val;
-
- Val = Xil_In32(Addr);
- Val = (Val & (~Mask)) | (Mask & Value);
- Xil_Out32(Addr, Val);
-}
-
-/*****************************************************************************/
-/**
- * @brief This functions copies source string to destination string. This
- * function is a safe version of strcpy
- *
- * @param DestPtr is pointer to destination string
- * @param SrcPtr is pointer to source string
- * @param Size is the maximum number of bytes of the source string
- * to be copied
- *
- * @return XST_SUCCESS on success and error code on failure
- *
- ******************************************************************************/
-int Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size)
-{
- int Status = XST_FAILURE;
- u32 Count;
-
- if ((SrcPtr == NULL) || (DestPtr == NULL) || (Size == 0U)) {
- goto END;
- }
-
- for (Count = 0U; (SrcPtr[Count] != '\0') && (Count < Size); ++Count) {
- DestPtr[Count] = SrcPtr[Count];
- }
- if (Count == Size) {
- DestPtr[0U] = '\0';
- goto END;
- }
- DestPtr[Count] = '\0';
- Status = XST_SUCCESS;
-
-END:
- return Status;
-}
-
-/****************************************************************************/
-/**
- * @brief Copies specified range from source string to destination string
- *
- * @param Src is a pointer to source string
- * @param Dst is a pointer to destination string
- * @param From is 0 based index from where string copy starts
- * @param To is 0 based index till which string is copied
- * @param MaxSrcLen is the maximum length of source string
- * @param MaxDstLen is the maximum length of destination string
- *
- * @return XST_SUCCESS on success
- * XST_FAILURE on failure
- *
- * @note None
- *
- ****************************************************************************/
-int Xil_StrCpyRange(const u8 *Src, u8 *Dst, u32 From, u32 To, u32 MaxSrcLen,
- u32 MaxDstLen)
-{
- int Status = XST_FAILURE;
- u32 SrcLength;
- u32 Index;
-
- if ((Src == NULL) || (Dst == NULL)) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- if ((To >= MaxSrcLen) || (To < From)) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- if ((To - From + 1U) >= MaxDstLen) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- SrcLength = Xil_Strnlen((const char *)Src, MaxSrcLen);
- if (To >= SrcLength) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- for (Index = From; Index <= To && Src[Index]!= '\0'; Index++) {
- Dst[Index - From] = Src[Index];
- }
-
- Dst[Index - From] = '\0';
- Status = XST_SUCCESS;
-
-END:
- return Status;
-}
-
-/*****************************************************************************/
-/**
- * @brief This function appends string2 to string1. This function is a safe
- * version of strcat
- *
- * @param Str1Ptr is pointer to string1
- * @param Str2Ptr is pointer to string2
- * @param Size is the maximum number of bytes Str1 can hold
- *
- * @return XST_SUCCESS on success and error code on failure
- *
- ******************************************************************************/
-int Xil_Strcat(char* Str1Ptr, const char* Str2Ptr, const u32 Size)
-{
- int Status = XST_FAILURE;
- u32 Count = 0U;
- u32 CountTmp = 0U;
-
- if ((Str1Ptr == NULL) || (Str2Ptr == NULL) || (Size == 0U)) {
- goto END;
- }
-
- while ((Count < Size) && (Str1Ptr[Count] != '\0')) {
- Count++;
- }
-
- while ((Str2Ptr[CountTmp] != '\0') && (Count < Size)) {
- Str1Ptr[Count++] = Str2Ptr[CountTmp++];
- }
- if (Count == Size) {
- Str1Ptr[0U] = '\0';
- goto END;
- }
- Str1Ptr[Count] = '\0';
- Status = XST_SUCCESS;
-
-END:
- return Status;
-}
-
-/*****************************************************************************/
-/**
- * @brief This function copies Len bytes from source memory to destination
- * memory. If Len is greater than DestPtrLen, then DestPtr is also
- * filled with 0s till DestPtrLen bytes and is considered as a failure.
- * This function is a secure implementation of memcpy
- *
- * @param DestPtr is pointer to destination address
- * @param DestPtrLen is the memory alloted to the destination buffer
- * @param SrcPtr is pointer to source address
- * @param Len is number of bytes to be copied
- *
- * @return XST_SUCCESS on success and error code on failure
- *
- ******************************************************************************/
-int Xil_SecureMemCpy(void * DestPtr, u32 DestPtrLen, const void * SrcPtr, u32 Len)
-{
- int Status = XST_FAILURE;
- u8 *Dest = (u8 *)DestPtr;
- const u8 *Src = (const u8 *)SrcPtr;
-
- if ((DestPtr == NULL) || (SrcPtr == NULL)) {
- goto END;
- }
-
- if (Len > DestPtrLen) {
- while (DestPtrLen != 0U) {
- *Dest = 0U;
- Dest++;
- DestPtrLen--;
- }
- goto END;
- }
-
- /* Loop and copy. */
- while (Len != 0U) {
- *Dest = *Src;
- Dest++;
- Src++;
- Len--;
- }
- Status = XST_SUCCESS;
-
-END:
- return Status;
-}
-
-/*****************************************************************************/
-/**
- * @brief This function compares Len bytes from memory1 and memory2. This
- * function is a secure implementation of memcmp
- *
- * @param Buf1Ptr is pointer to memory1
- * @param Buf2Ptr is pointer to memory2
- * @param Len is number of byets to be compared
- *
- * @return 0 if contents of both the memory regions are same,
- * -1 if first non-matching character has lower value in Buf1Ptr
- * 1 if first non-matching character is greater value in Buf1Ptr
- *
- ******************************************************************************/
-int Xil_MemCmp(const void * Buf1Ptr, const void * Buf2Ptr, u32 Len)
-{
- volatile int RetVal = 1;
- const u8 *Buf1 = Buf1Ptr;
- const u8 *Buf2 = Buf2Ptr;
- u32 Size = Len;
-
- /* Assert validates the input arguments */
- if ((Buf1 == NULL) || (Buf2 == NULL) || (Len == 0x0U)) {
- goto END;
- }
-
- /* Loop and compare */
- while (Size != 0U) {
- if (*Buf1 > *Buf2) {
- RetVal = 1;
- goto END;
- } else if (*Buf1 < *Buf2) {
- RetVal = -1;
- goto END;
- } else {
- Buf1++;
- Buf2++;
- Size--;
- }
- }
-
- /* Make sure size is zero to know the whole of data is compared */
- if (Size == 0U) {
- RetVal = 0;
- }
-
-END:
- return RetVal;
-}
-
-/*****************************************************************************/
-/**
- * @brief This function is used to zeroize the memory
- *
- * @param DataPtr Pointer to the memory which need to be zeroized.
- * @param Length Length of the data in bytes.
- *
- * @return
- * - XST_SUCCESS: If Zeroization is successful.
- * - XST_FAILURE: If Zeroization is not successful.
- ********************************************************************************/
-int Xil_SecureZeroize(u8 *DataPtr, const u32 Length)
-{
- u32 Index;
- int Status = XST_FAILURE;
-
- /* Clear the data */
- (void)memset(DataPtr, 0, Length);
-
- /* Read it back to verify */
- for (Index = 0U; Index < Length; Index++) {
- if (DataPtr[Index] != 0x00U) {
- goto END;
- }
- }
- if (Index == Length) {
- Status = XST_SUCCESS;
- }
-
-END:
- return Status;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/36/00cd41585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/36/00cd41585243001d18b399c1eb9b3628
deleted file mode 100644
index 3f926ac..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/36/00cd41585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,101 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xil-crt0.S
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 5.4 pkp 18/12/15 Initialized global constructor for C++ applications
-* 6.6 srm 10/18/17 Added timer configuration using XTime_StartTTCTimer API.
-* Now the TTC instance as specified by the user will be
-* started.
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#include "xparameters.h"
- .file "xil-crt0.S"
- .section ".got2","aw"
- .align 2
-
- .text
-.Lsbss_start:
- .long __sbss_start
-
-.Lsbss_end:
- .long __sbss_end
-
-.Lbss_start:
- .long __bss_start__
-
-.Lbss_end:
- .long __bss_end__
-
-
-.Lstack:
- .long __stack
-
- .globl _startup
-_startup:
-
- mov r0, #0
-
- /* clear sbss */
- ldr r1,.Lsbss_start /* calculate beginning of the SBSS */
- ldr r2,.Lsbss_end /* calculate end of the SBSS */
-
-.Lloop_sbss:
- cmp r1,r2
- bge .Lenclsbss /* If no SBSS, no clearing required */
- str r0, [r1], #4
- b .Lloop_sbss
-
-.Lenclsbss:
- /* clear bss */
- ldr r1,.Lbss_start /* calculate beginning of the BSS */
- ldr r2,.Lbss_end /* calculate end of the BSS */
-
-.Lloop_bss:
- cmp r1,r2
- bge .Lenclbss /* If no BSS, no clearing required */
- str r0, [r1], #4
- b .Lloop_bss
-
-.Lenclbss:
- /* set stack pointer */
- ldr r13,.Lstack /* stack address */
-
- /* run global constructors */
- bl __libc_init_array
-
- /* Reset and start Triple Timer Counter */
- #if defined (SLEEP_TIMER_BASEADDR)
- bl XTime_StartTTCTimer
- #endif
-
- /* make sure argc and argv are valid */
- mov r0, #0
- mov r1, #0
-
- bl main /* Jump to main C code */
-
- /* Cleanup global constructors */
- bl __libc_fini_array
-
- bl exit
-
-.Lexit: /* should never get here */
- b .Lexit
-
-.Lstart:
- .size _startup,.Lstart-_startup
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/36/20a96c545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/36/20a96c545243001d18b399c1eb9b3628
deleted file mode 100644
index bb3765d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/36/20a96c545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,504 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xuartps.h
-* @addtogroup uartps_v3_11
-* @{
-* @details
-*
-* This driver supports the following features:
-*
-* - Dynamic data format (baud rate, data bits, stop bits, parity)
-* - Polled mode
-* - Interrupt driven mode
-* - Transmit and receive FIFOs (32 byte FIFO depth)
-* - Access to the external modem control lines
-*
-* Initialization & Configuration
-*
-* The XUartPs_Config structure is used by the driver to configure itself.
-* Fields inside this structure are properties of XUartPs based on its hardware
-* build.
-*
-* To support multiple runtime loading and initialization strategies employed
-* by various operating systems, the driver instance can be initialized in the
-* following way:
-*
-* - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-* configuration structure provided by the caller. If running in a system
-* with address translation, the parameter EffectiveAddr should be the
-* virtual address.
-*
-* Baud Rate
-*
-* The UART has an internal baud rate generator, which furnishes the baud rate
-* clock for both the receiver and the transmitter. The input clock frequency
-* can be either the master clock or the master clock divided by 8, configured
-* through the mode register.
-*
-* Accompanied with the baud rate divider register, the baud rate is determined
-* by:
-*
-* where bgen is the value of the baud rate generator, and bdiv is the value of
-* baud rate divider.
-*
-* Interrupts
-*
-* The FIFOs are not flushed when the driver is initialized, but a function is
-* provided to allow the user to reset the FIFOs if desired.
-*
-* The driver defaults to no interrupts at initialization such that interrupts
-* must be enabled if desired. An interrupt is generated for one of the
-* following conditions.
-*
-* - A change in the modem signals
-* - Data in the receive FIFO for a configuable time without receiver activity
-* - A parity error
-* - A framing error
-* - An overrun error
-* - Transmit FIFO is full
-* - Transmit FIFO is empty
-* - Receive FIFO is full
-* - Receive FIFO is empty
-* - Data in the receive FIFO equal to the receive threshold
-*
-* The application can control which interrupts are enabled using the
-* XUartPs_SetInterruptMask() function.
-*
-* In order to use interrupts, it is necessary for the user to connect the
-* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
-* system of the application. A separate handler should be provided by the
-* application to communicate with the interrupt system, and conduct
-* application specific interrupt handling. An application registers its own
-* handler through the XUartPs_SetHandler() function.
-*
-* Data Transfer
-*
-* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
-* driver to allow data to be sent and received. They can be used in either
-* polled or interrupt mode.
-*
-* @note
-*
-* The default configuration for the UART after initialization is:
-*
-* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
-* - 8 data bits
-* - 1 stop bit
-* - no parity
-* - FIFO's are enabled with a receive threshold of 8 bytes
-* - The RX timeout is enabled with a timeout of 1 (4 char times)
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00a drg/jz 01/12/10 First Release
-* 1.00a sdm 09/27/11 Fixed compiler warnings and also a bug
-* in XUartPs_SetFlowDelay where the value was not
-* being written to the register.
-* 1.01a sdm 12/20/11 Removed the InputClockHz parameter from the XUartPs
-* instance structure and the driver is updated to use
-* InputClockHz parameter from the XUartPs_Config config
-* structure.
-* Added a parameter to XUartPs_Config structure which
-* specifies whether the user has selected Modem pins
-* to be connected to MIO or FMIO.
-* Added the tcl file to generate the xparameters.h
-* 1.02a sg 05/16/12 Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
-* 1.03a sg 07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
-* with the correct values for CR 666724
-* Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
-* and XUARTPS_IXR_TTRIG.
-* Modified the name of these defines
-* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
-* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
-* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
-* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
-* 1.05a hk 08/22/13 Added API for uart reset and related
-* constant definitions.
-* 2.0 hk 03/07/14 Version number revised.
-* 2.1 hk 04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
-* 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing
-* baud rate. CR# 804281.
-* 3.0 vm 12/09/14 Modified source code according to misrac guideline.
-* Support for Zynq Ultrascale Mp added.
-* 3.1 kvn 04/10/15 Modified code for latest RTL changes. Also added
-* platform variable in driver instance structure.
-* 3.1 adk 14/03/16 Include interrupt examples in the peripheral test when
-* uart is connected to a valid interrupt controller CR#946803.
-* 3.2 rk 07/20/16 Modified the logic for transmission break bit set
-* 3.4 ms 01/23/17 Added xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 3.6 ms 02/16/18 Updates the flow control mode offset value in modem
-* control register.
-* 3.7 aru 08/17/18 Resolved MISRA-C:2012 compliance mandatory violations.
-* 3.9 rna 12/03/19 Modified the XUARTPS_MAX_RATE macro.
-* 3.9 sd 02/06/20 Added clock support
-*
-*
-*
-*****************************************************************************/
-
-#ifndef XUARTPS_H /* prevent circular inclusions */
-#define XUARTPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xuartps_hw.h"
-#include "xplatform_info.h"
-#if defined (XCLOCKING)
-#include "xil_clocking.h"
-#endif
-
-/************************** Constant Definitions ****************************/
-
-/*
- * The following constants indicate the max and min baud rates and these
- * numbers are based only on the testing that has been done. The hardware
- * is capable of other baud rates.
- */
-#define XUARTPS_MAX_RATE 6240000U
-#define XUARTPS_MIN_RATE 110U
-
-#define XUARTPS_DFT_BAUDRATE 115200U /* Default baud rate */
-
-/** @name Configuration options
- * @{
- */
-/**
- * These constants specify the options that may be set or retrieved
- * with the driver, each is a unique bit mask such that multiple options
- * may be specified. These constants indicate the available options
- * in active state.
- *
- */
-
-#define XUARTPS_OPTION_SET_BREAK 0x0080U /**< Starts break transmission */
-#define XUARTPS_OPTION_STOP_BREAK 0x0040U /**< Stops break transmission */
-#define XUARTPS_OPTION_RESET_TMOUT 0x0020U /**< Reset the receive timeout */
-#define XUARTPS_OPTION_RESET_TX 0x0010U /**< Reset the transmitter */
-#define XUARTPS_OPTION_RESET_RX 0x0008U /**< Reset the receiver */
-#define XUARTPS_OPTION_ASSERT_RTS 0x0004U /**< Assert the RTS bit */
-#define XUARTPS_OPTION_ASSERT_DTR 0x0002U /**< Assert the DTR bit */
-#define XUARTPS_OPTION_SET_FCM 0x0001U /**< Turn on flow control mode */
-/*@}*/
-
-
-/** @name Channel Operational Mode
- *
- * The UART can operate in one of four modes: Normal, Local Loopback, Remote
- * Loopback, or automatic echo.
- *
- * @{
- */
-
-#define XUARTPS_OPER_MODE_NORMAL (u8)0x00U /**< Normal Mode */
-#define XUARTPS_OPER_MODE_AUTO_ECHO (u8)0x01U /**< Auto Echo Mode */
-#define XUARTPS_OPER_MODE_LOCAL_LOOP (u8)0x02U /**< Local Loopback Mode */
-#define XUARTPS_OPER_MODE_REMOTE_LOOP (u8)0x03U /**< Remote Loopback Mode */
-
-/* @} */
-
-/** @name Data format values
- *
- * These constants specify the data format that the driver supports.
- * The data format includes the number of data bits, the number of stop
- * bits and parity.
- *
- * @{
- */
-#define XUARTPS_FORMAT_8_BITS 0U /**< 8 data bits */
-#define XUARTPS_FORMAT_7_BITS 2U /**< 7 data bits */
-#define XUARTPS_FORMAT_6_BITS 3U /**< 6 data bits */
-
-#define XUARTPS_FORMAT_NO_PARITY 4U /**< No parity */
-#define XUARTPS_FORMAT_MARK_PARITY 3U /**< Mark parity */
-#define XUARTPS_FORMAT_SPACE_PARITY 2U /**< parity */
-#define XUARTPS_FORMAT_ODD_PARITY 1U /**< Odd parity */
-#define XUARTPS_FORMAT_EVEN_PARITY 0U /**< Even parity */
-
-#define XUARTPS_FORMAT_2_STOP_BIT 2U /**< 2 stop bits */
-#define XUARTPS_FORMAT_1_5_STOP_BIT 1U /**< 1.5 stop bits */
-#define XUARTPS_FORMAT_1_STOP_BIT 0U /**< 1 stop bit */
-/*@}*/
-
-/** @name Callback events
- *
- * These constants specify the handler events that an application can handle
- * using its specific handler function. Note that these constants are not bit
- * mask, so only one event can be passed to an application at a time.
- *
- * @{
- */
-#define XUARTPS_EVENT_RECV_DATA 1U /**< Data receiving done */
-#define XUARTPS_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */
-#define XUARTPS_EVENT_SENT_DATA 3U /**< Data transmission done */
-#define XUARTPS_EVENT_RECV_ERROR 4U /**< A receive error detected */
-#define XUARTPS_EVENT_MODEM 5U /**< Modem status changed */
-#define XUARTPS_EVENT_PARE_FRAME_BRKE 6U /**< A receive parity, frame, break
- * error detected */
-#define XUARTPS_EVENT_RECV_ORERR 7U /**< A receive overrun error detected */
-
-/*@}*/
-
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of device (IPIF) */
- u32 InputClockHz;/**< Input clock frequency */
- s32 ModemPinsConnected; /** Specifies whether modem pins are connected
- * to MIO or FMIO */
-#if defined (XCLOCKING)
- u32 RefClk; /**< Input clock frequency */
-#endif
-} XUartPs_Config;
-
-/* Keep track of state information about a data buffer in the interrupt mode. */
-typedef struct {
- u8 *NextBytePtr;
- u32 RequestedBytes;
- u32 RemainingBytes;
-} XUartPsBuffer;
-
-/**
- * Keep track of data format setting of a device.
- */
-typedef struct {
- u32 BaudRate; /**< In bps, ie 1200 */
- u32 DataBits; /**< Number of data bits */
- u32 Parity; /**< Parity */
- u8 StopBits; /**< Number of stop bits */
-} XUartPsFormat;
-
-/******************************************************************************/
-/**
- * This data type defines a handler that an application defines to communicate
- * with interrupt system to retrieve state information about an application.
- *
- * @param CallBackRef is a callback reference passed in by the upper layer
- * when setting the handler, and is passed back to the upper layer
- * when the handler is called. It is used to find the device driver
- * instance.
- * @param Event contains one of the event constants indicating events that
- * have occurred.
- * @param EventData contains the number of bytes sent or received at the
- * time of the call for send and receive events and contains the
- * modem status for modem events.
- *
- ******************************************************************************/
-typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
- u32 EventData);
-
-/**
- * The XUartPs driver instance data structure. A pointer to an instance data
- * structure is passed around by functions to refer to a specific driver
- * instance.
- */
-typedef struct {
- XUartPs_Config Config; /* Configuration data structure */
- u32 InputClockHz; /* Input clock frequency */
- u32 IsReady; /* Device is initialized and ready */
- u32 BaudRate; /* Current baud rate */
-
- XUartPsBuffer SendBuffer;
- XUartPsBuffer ReceiveBuffer;
-
- XUartPs_Handler Handler;
- void *CallBackRef; /* Callback reference for event handler */
- u32 Platform;
- u8 is_rxbs_error;
-} XUartPs;
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* Get the UART Channel Status Register.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_GetChannelStatus(InstancePtr) \
- Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
-
-/****************************************************************************/
-/**
-* Get the UART Mode Control Register.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XUartPs_GetControl(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_GetModeControl(InstancePtr) \
- Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
-
-/****************************************************************************/
-/**
-* Set the UART Mode Control Register.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
-*
-******************************************************************************/
-#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
- Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
- (u32)(RegisterValue))
-
-/****************************************************************************/
-/**
-* Enable the transmitter and receiver of the UART.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_EnableUart(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_EnableUart(InstancePtr) \
- Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
- ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
- (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
-
-/****************************************************************************/
-/**
-* Disable the transmitter and receiver of the UART.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_DisableUart(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_DisableUart(InstancePtr) \
- Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
- (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
- (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
-
-/****************************************************************************/
-/**
-* Determine if the transmitter FIFO is empty.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-* - TRUE if a byte can be sent
-* - FALSE if the Transmitter Fifo is not empty
-*
-* @note C-Style signature:
-* u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_IsTransmitEmpty(InstancePtr) \
- ((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
- (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
-
-
-/************************** Function Prototypes *****************************/
-
-/* Static lookup function implemented in xuartps_sinit.c */
-XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
-
-/* Interface functions implemented in xuartps.c */
-s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
- XUartPs_Config * Config, u32 EffectiveAddr);
-
-u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
- u32 NumBytes);
-
-u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
- u32 NumBytes);
-
-s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
-
-/* Options functions in xuartps_options.c */
-void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
-
-u16 XUartPs_GetOptions(XUartPs *InstancePtr);
-
-void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
-
-u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
-
-u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
-
-u32 XUartPs_IsSending(XUartPs *InstancePtr);
-
-u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
-
-void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
-
-u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
-
-void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
-
-u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
-
-void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
-
-s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
-
-void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
-
-/* interrupt functions in xuartps_intr.c */
-u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
-
-void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
-
-void XUartPs_InterruptHandler(XUartPs *InstancePtr);
-
-void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
- void *CallBackRef);
-
-/* self-test functions in xuartps_selftest.c */
-s32 XUartPs_SelfTest(XUartPs *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/36/303d3a565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/36/303d3a565243001d18b399c1eb9b3628
deleted file mode 100644
index 9be0b25..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/36/303d3a565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,176 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file asm_vectors.S
-*
-* This file contains the initial vector table for the Cortex A9 processor
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 1.00a ecm/sdm 10/20/09 Initial version
-* 3.05a sdm 02/02/12 Save lr when profiling is enabled
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-* 4.00a pkp 22/01/14 Modified return addresses for interrupt
-* handlers (DataAbortHandler and SVCHandler)
-* to fix CR#767251
-* 5.1 pkp 05/13/15 Saved the addresses of instruction causing data
-* abort and prefetch abort into DataAbortAddr and
-* PrefetchAbortAddr for further use to fix CR#854523
-* 5.4 pkp 12/03/15 Added handler for undefined exception
-* 6.8 mus 04/27/18 Removed __ARM_NEON__ flag definition. Now,
-* saving/restoring of of HW floating point register
-* would be done through newly introduced flag
-* FPU_HARD_FLOAT_ABI_ENABLED. This new flag will be
-* configured based on the -mfpu-abi option in extra
-* compiler flags.
-*
-* MODIFICATION HISTORY :
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 6.6 srm 10/18/17 First Release.
-* 7.0 mus 01/07/19 Add cpp extern macro
-*
-*
-*****************************************************************************/
-
-/**
- *@cond nocomments
- */
-#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */
-#define XIL_SLEEPTIMER_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**************************** Include Files ********************************/
-
-#include "xil_io.h"
-#include "xparameters.h"
-#include "bspconfig.h"
-
-/************************** Constant Definitions *****************************/
-
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
-#define XSLEEP_TIMER_REG_SHIFT 32U
-#define XSleep_ReadCounterVal Xil_In32
-#define XCntrVal u32
-#else
-#define XSLEEP_TIMER_REG_SHIFT 16U
-#define XSleep_ReadCounterVal Xil_In16
-#define XCntrVal u16
-#endif
-
-#if defined(ARMR5) || (defined (__aarch64__) && EL3==1) || defined (ARMA53_32)
-#if defined (versal)
-#define CRL_TTC_RST 0xFF5E0344U
-#define CRL_TTC_BASE_RST_MASK 0x1U
-#else
-#define RST_LPD_IOU2 0xFF5E0238U
-#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U
-#endif
-#endif
-
-#if defined (SLEEP_TIMER_BASEADDR)
-/** @name Register Map
-*
-* Register offsets from the base address of the TTC device
-*
-* @{
-*/
- #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U
- /**< Clock Control Register */
- #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU
- /**< Counter Control Register*/
- #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U
- /**< Current Counter Value */
-/* @} */
-/** @name Clock Control Register
-* Clock Control Register definitions of TTC
-* @{
-*/
- #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U
- /**< Prescale enable */
-/* @} */
-/** @name Counter Control Register
-* Counter Control Register definitions of TTC
-* @{
-*/
-#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U
- /**< Disable the counter */
-#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U
- /**< Reset counter */
-/* @} */
-
-/**************************** Type Definitions *******************************/
-/**
- *@endcond
- */
-/************************** Function Prototypes ******************************/
-
-void Xil_SleepTTCCommon(u32 delay, u64 frequency);
-void XTime_StartTTCTimer();
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_SLEEPTIMER_H */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/36/a01a91575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/36/a01a91575243001d18b399c1eb9b3628
deleted file mode 100644
index edf6684..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/36/a01a91575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,558 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpm_counter.h
-*
-* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions
-*
-* Cortex A9 event counter functions can be utilized to configure and control
-* the Cortex-A9 performance monitor events.
-*
-* Cortex-A9 performance monitor has six event counters which can be used to
-* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines
-* configurations XPM_CNTRCFGx which can be used to program the event counters
-* to count a set of events.
-*
-* @note
-* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
-* being used for time keeping.
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-*
-******************************************************************************/
-
-/**
-*@cond nocomments
-*/
-
-#ifndef XPMCOUNTER_H /* prevent circular inclusions */
-#define XPMCOUNTER_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/************************** Constant Definitions ****************************/
-
-/* Number of performance counters */
-#define XPM_CTRCOUNT 6U
-
-/* The following constants define the Cortex-A9 Performance Monitor Events */
-
-/*
- * Software increment. The register is incremented only on writes to the
- * Software Increment Register
- */
-#define XPM_EVENT_SOFTINCR 0x00U
-
-/*
- * Instruction fetch that causes a refill at (at least) the lowest level(s) of
- * instruction or unified cache. Includes the speculative linefills in the
- * count
- */
-#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
-
-/*
- * Instruction fetch that causes a TLB refill at (at least) the lowest level of
- * TLB. Includes the speculative requests in the count
- */
-#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
-
-/*
- * Data read or write operation that causes a refill at (at least) the lowest
- * level(s)of data or unified cache. Counts the number of allocations performed
- * in the Data Cache due to a read or a write
- */
-#define XPM_EVENT_DATA_CACHEREFILL 0x03U
-
-/*
- * Data read or write operation that causes a cache access at (at least) the
- * lowest level(s) of data or unified cache. This includes speculative reads
- */
-#define XPM_EVENT_DATA_CACHEACCESS 0x04U
-
-/*
- * Data read or write operation that causes a TLB refill at (at least) the
- * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
- * CP15 Cache operation by MVA and CP15 VA to PA operations
- */
-#define XPM_EVENT_DATA_TLBREFILL 0x05U
-
-/*
- * Data read architecturally executed. Counts the number of data read
- * instructions accepted by the Load Store Unit. This includes counting the
- * speculative and aborted LDR/LDM, as well as the reads due to the SWP
- * instructions
- */
-#define XPM_EVENT_DATA_READS 0x06U
-
-/*
- * Data write architecturally executed. Counts the number of data write
- * instructions accepted by the Load Store Unit. This includes counting the
- * speculative and aborted STR/STM, as well as the writes due to the SWP
- * instructions
- */
-#define XPM_EVENT_DATA_WRITE 0x07U
-
-/* Exception taken. Counts the number of exceptions architecturally taken.*/
-#define XPM_EVENT_EXCEPTION 0x09U
-
-/* Exception return architecturally executed.*/
-#define XPM_EVENT_EXCEPRETURN 0x0AU
-
-/*
- * Change to ContextID retired. Counts the number of instructions
- * architecturally executed writing into the ContextID Register
- */
-#define XPM_EVENT_CHANGECONTEXT 0x0BU
-
-/*
- * Software change of PC, except by an exception, architecturally executed.
- * Count the number of PC changes architecturally executed, excluding the PC
- * changes due to taken exceptions
- */
-#define XPM_EVENT_SW_CHANGEPC 0x0CU
-
-/*
- * Immediate branch architecturally executed (taken or not taken). This includes
- * the branches which are flushed due to a previous load/store which aborts
- * late
- */
-#define XPM_EVENT_IMMEDBRANCH 0x0DU
-
-/*
- * Unaligned access architecturally executed. Counts the number of aborted
- * unaligned accessed architecturally executed, and the number of not-aborted
- * unaligned accesses, including the speculative ones
- */
-#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
-
-/*
- * Branch mispredicted/not predicted. Counts the number of mispredicted or
- * not-predicted branches executed. This includes the branches which are flushed
- * due to a previous load/store which aborts late
- */
-#define XPM_EVENT_BRANCHMISS 0x10U
-
-/*
- * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
- * event is not exported on the PMUEVENT bus
- */
-#define XPM_EVENT_CLOCKCYCLES 0x11U
-
-/*
- * Branches or other change in program flow that could have been predicted by
- * the branch prediction resources of the processor. This includes the branches
- * which are flushed due to a previous load/store which aborts late
- */
-#define XPM_EVENT_BRANCHPREDICT 0x12U
-
-/*
- * Java bytecode execute. Counts the number of Java bytecodes being decoded,
- * including speculative ones
- */
-#define XPM_EVENT_JAVABYTECODE 0x40U
-
-/*
- * Software Java bytecode executed. Counts the number of software java bytecodes
- * being decoded, including speculative ones
- */
-#define XPM_EVENT_SWJAVABYTECODE 0x41U
-
-/*
- * Jazelle backward branches executed. Counts the number of Jazelle taken
- * branches being executed. This includes the branches which are flushed due
- * to a previous load/store which aborts late
- */
-#define XPM_EVENT_JAVABACKBRANCH 0x42U
-
-/*
- * Coherent linefill miss Counts the number of coherent linefill requests
- * performed by the Cortex-A9 processor which also miss in all the other
- * Cortex-A9 processors, meaning that the request is sent to the external
- * memory
- */
-#define XPM_EVENT_COHERLINEMISS 0x50U
-
-/*
- * Coherent linefill hit. Counts the number of coherent linefill requests
- * performed by the Cortex-A9 processor which hit in another Cortex-A9
- * processor, meaning that the linefill data is fetched directly from the
- * relevant Cortex-A9 cache
- */
-#define XPM_EVENT_COHERLINEHIT 0x51U
-
-/*
- * Instruction cache dependent stall cycles. Counts the number of cycles where
- * the processor is ready to accept new instructions, but does not receive any
- * due to the instruction side not being able to provide any and the
- * instruction cache is currently performing at least one linefill
- */
-#define XPM_EVENT_INSTRSTALL 0x60U
-
-/*
- * Data cache dependent stall cycles. Counts the number of cycles where the core
- * has some instructions that it cannot issue to any pipeline, and the Load
- * Store unit has at least one pending linefill request, and no pending
- */
-#define XPM_EVENT_DATASTALL 0x61U
-
-/*
- * Main TLB miss stall cycles. Counts the number of cycles where the processor
- * is stalled waiting for the completion of translation table walks from the
- * main TLB. The processor stalls can be due to the instruction side not being
- * able to provide the instructions, or to the data side not being able to
- * provide the necessary data, due to them waiting for the main TLB translation
- * table walk to complete
- */
-#define XPM_EVENT_MAINTLBSTALL 0x62U
-
-/*
- * Counts the number of STREX instructions architecturally executed and
- * passed
- */
-#define XPM_EVENT_STREXPASS 0x63U
-
-/*
- * Counts the number of STREX instructions architecturally executed and
- * failed
- */
-#define XPM_EVENT_STREXFAIL 0x64U
-
-/*
- * Data eviction. Counts the number of eviction requests due to a linefill in
- * the data cache
- */
-#define XPM_EVENT_DATAEVICT 0x65U
-
-/*
- * Counts the number of cycles where the issue stage does not dispatch any
- * instruction because it is empty or cannot dispatch any instructions
- */
-#define XPM_EVENT_NODISPATCH 0x66U
-
-/*
- * Counts the number of cycles where the issue stage is empty
- */
-#define XPM_EVENT_ISSUEEMPTY 0x67U
-
-/*
- * Counts the number of instructions going through the Register Renaming stage.
- * This number is an approximate number of the total number of instructions
- * speculatively executed, and even more approximate of the total number of
- * instructions architecturally executed. The approximation depends mainly on
- * the branch misprediction rate.
- * The renaming stage can handle two instructions in the same cycle so the event
- * is two bits long:
- * - b00 no instructions renamed
- * - b01 one instruction renamed
- * - b10 two instructions renamed
- */
-#define XPM_EVENT_INSTRRENAME 0x68U
-
-/*
- * Counts the number of procedure returns whose condition codes do not fail,
- * excluding all returns from exception. This count includes procedure returns
- * which are flushed due to a previous load/store which aborts late.
- * Only the following instructions are reported:
- * - BX R14
- * - MOV PC LR
- * - POP {..,pc}
- * - LDR pc,[sp],#offset
- * The following instructions are not reported:
- * - LDMIA R9!,{..,PC} (ThumbEE state only)
- * - LDR PC,[R9],#offset (ThumbEE state only)
- * - BX R0 (Rm != R14)
- * - MOV PC,R0 (Rm != R14)
- * - LDM SP,{...,PC} (writeback not specified)
- * - LDR PC,[SP,#offset] (wrong addressing mode)
- */
-#define XPM_EVENT_PREDICTFUNCRET 0x6EU
-
-/*
- * Counts the number of instructions being executed in the main execution
- * pipeline of the processor, the multiply pipeline and arithmetic logic unit
- * pipeline. The counted instructions are still speculative
- */
-#define XPM_EVENT_MAINEXEC 0x70U
-
-/*
- * Counts the number of instructions being executed in the processor second
- * execution pipeline (ALU). The counted instructions are still speculative
- */
-#define XPM_EVENT_SECEXEC 0x71U
-
-/*
- * Counts the number of instructions being executed in the Load/Store unit. The
- * counted instructions are still speculative
- */
-#define XPM_EVENT_LDRSTR 0x72U
-
-/*
- * Counts the number of Floating-point instructions going through the Register
- * Rename stage. Instructions are still speculative in this stage.
- *Two floating-point instructions can be renamed in the same cycle so the event
- * is two bitslong:
- *0b00 no floating-point instruction renamed
- *0b01 one floating-point instruction renamed
- *0b10 two floating-point instructions renamed
- */
-#define XPM_EVENT_FLOATRENAME 0x73U
-
-/*
- * Counts the number of Neon instructions going through the Register Rename
- * stage.Instructions are still speculative in this stage.
- * Two NEON instructions can be renamed in the same cycle so the event is two
- * bits long:
- *0b00 no NEON instruction renamed
- *0b01 one NEON instruction renamed
- *0b10 two NEON instructions renamed
- */
-#define XPM_EVENT_NEONRENAME 0x74U
-
-/*
- * Counts the number of cycles where the processor is stalled because PLD slots
- * are all full
- */
-#define XPM_EVENT_PLDSTALL 0x80U
-
-/*
- * Counts the number of cycles when the processor is stalled and the data side
- * is stalled too because it is full and executing writes to the external
- * memory
- */
-#define XPM_EVENT_WRITESTALL 0x81U
-
-/*
- * Counts the number of stall cycles due to main TLB misses on requests issued
- * by the instruction side
- */
-#define XPM_EVENT_INSTRTLBSTALL 0x82U
-
-/*
- * Counts the number of stall cycles due to main TLB misses on requests issued
- * by the data side
- */
-#define XPM_EVENT_DATATLBSTALL 0x83U
-
-/*
- * Counts the number of stall cycles due to micro TLB misses on the instruction
- * side. This event does not include main TLB miss stall cycles that are already
- * counted in the corresponding main TLB event
- */
-#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
-
-/*
- * Counts the number of stall cycles due to micro TLB misses on the data side.
- * This event does not include main TLB miss stall cycles that are already
- * counted in the corresponding main TLB event
- */
-#define XPM_EVENT_DATA_uTLBSTALL 0x85U
-
-/*
- * Counts the number of stall cycles because of the execution of a DMB memory
- * barrier. This includes all DMB instructions being executed, even
- * speculatively
- */
-#define XPM_EVENT_DMB_STALL 0x86U
-
-/*
- * Counts the number of cycles during which the integer core clock is enabled
- */
-#define XPM_EVENT_INT_CLKEN 0x8AU
-
-/*
- * Counts the number of cycles during which the Data Engine clock is enabled
- */
-#define XPM_EVENT_DE_CLKEN 0x8BU
-
-/*
- * Counts the number of ISB instructions architecturally executed
- */
-#define XPM_EVENT_INSTRISB 0x90U
-
-/*
- * Counts the number of DSB instructions architecturally executed
- */
-#define XPM_EVENT_INSTRDSB 0x91U
-
-/*
- * Counts the number of DMB instructions speculatively executed
- */
-#define XPM_EVENT_INSTRDMB 0x92U
-
-/*
- * Counts the number of external interrupts executed by the processor
- */
-#define XPM_EVENT_EXTINT 0x93U
-
-/*
- * PLE cache line request completed
- */
-#define XPM_EVENT_PLE_LRC 0xA0U
-
-/*
- * PLE cache line request skipped
- */
-#define XPM_EVENT_PLE_LRS 0xA1U
-
-/*
- * PLE FIFO flush
- */
-#define XPM_EVENT_PLE_FLUSH 0xA2U
-
-/*
- * PLE request complete
- */
-#define XPM_EVENT_PLE_CMPL 0xA3U
-
-/*
- * PLE FIFO overflow
- */
-#define XPM_EVENT_PLE_OVFL 0xA4U
-
-/*
- * PLE request programmed
- */
-#define XPM_EVENT_PLE_PROG 0xA5U
-
-/*
- * The following constants define the configurations for Cortex-A9 Performance
- * Monitor Events. Each configuration configures the event counters for a set
- * of events.
- * -----------------------------------------------
- * Config PmCtr0... PmCtr5
- * -----------------------------------------------
- * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR,
- * XPM_EVENT_INSRFETCH_CACHEREFILL,
- * XPM_EVENT_INSTRFECT_TLBREFILL,
- * XPM_EVENT_DATA_CACHEREFILL,
- * XPM_EVENT_DATA_CACHEACCESS,
- * XPM_EVENT_DATA_TLBREFILL }
- *
- * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS,
- * XPM_EVENT_DATA_WRITE,
- * XPM_EVENT_EXCEPTION,
- * XPM_EVENT_EXCEPRETURN,
- * XPM_EVENT_CHANGECONTEXT,
- * XPM_EVENT_SW_CHANGEPC }
- *
- * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH,
- * XPM_EVENT_UNALIGNEDACCESS,
- * XPM_EVENT_BRANCHMISS,
- * XPM_EVENT_CLOCKCYCLES,
- * XPM_EVENT_BRANCHPREDICT,
- * XPM_EVENT_JAVABYTECODE }
- *
- * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE,
- * XPM_EVENT_JAVABACKBRANCH,
- * XPM_EVENT_COHERLINEMISS,
- * XPM_EVENT_COHERLINEHIT,
- * XPM_EVENT_INSTRSTALL,
- * XPM_EVENT_DATASTALL }
- *
- * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL,
- * XPM_EVENT_STREXPASS,
- * XPM_EVENT_STREXFAIL,
- * XPM_EVENT_DATAEVICT,
- * XPM_EVENT_NODISPATCH,
- * XPM_EVENT_ISSUEEMPTY }
- *
- * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME,
- * XPM_EVENT_PREDICTFUNCRET,
- * XPM_EVENT_MAINEXEC,
- * XPM_EVENT_SECEXEC,
- * XPM_EVENT_LDRSTR,
- * XPM_EVENT_FLOATRENAME }
- *
- * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME,
- * XPM_EVENT_PLDSTALL,
- * XPM_EVENT_WRITESTALL,
- * XPM_EVENT_INSTRTLBSTALL,
- * XPM_EVENT_DATATLBSTALL,
- * XPM_EVENT_INSTR_uTLBSTALL }
- *
- * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL,
- * XPM_EVENT_DMB_STALL,
- * XPM_EVENT_INT_CLKEN,
- * XPM_EVENT_DE_CLKEN,
- * XPM_EVENT_INSTRISB,
- * XPM_EVENT_INSTRDSB }
- *
- * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB,
- * XPM_EVENT_EXTINT,
- * XPM_EVENT_PLE_LRC,
- * XPM_EVENT_PLE_LRS,
- * XPM_EVENT_PLE_FLUSH,
- * XPM_EVENT_PLE_CMPL }
- *
- * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL,
- * XPM_EVENT_PLE_PROG,
- * XPM_EVENT_PLE_LRC,
- * XPM_EVENT_PLE_LRS,
- * XPM_EVENT_PLE_FLUSH,
- * XPM_EVENT_PLE_CMPL }
- *
- * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL,
- * XPM_EVENT_INSRFETCH_CACHEREFILL,
- * XPM_EVENT_INSTRFECT_TLBREFILL,
- * XPM_EVENT_DATA_CACHEREFILL,
- * XPM_EVENT_DATA_CACHEACCESS,
- * XPM_EVENT_DATA_TLBREFILL }
- */
-#define XPM_CNTRCFG1 0
-#define XPM_CNTRCFG2 1
-#define XPM_CNTRCFG3 2
-#define XPM_CNTRCFG4 3
-#define XPM_CNTRCFG5 4
-#define XPM_CNTRCFG6 5
-#define XPM_CNTRCFG7 6
-#define XPM_CNTRCFG8 7
-#define XPM_CNTRCFG9 8
-#define XPM_CNTRCFG10 9
-#define XPM_CNTRCFG11 10
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/**
-*@endcond
-*/
-
-/************************** Function Prototypes *****************************/
-
-/* Interface functions to access performance counters from abstraction layer */
-void Xpm_SetEvents(s32 PmcrCfg);
-void Xpm_GetEventCounters(u32 *PmCtrValue);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-* @} End of "addtogroup a9_event_counter_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/36/a048b3575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/36/a048b3575243001d18b399c1eb9b3628
deleted file mode 100644
index acef5d8..0000000
Binary files a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/36/a048b3575243001d18b399c1eb9b3628 and /dev/null differ
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/36/b17d87575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/36/b17d87575243001d18b399c1eb9b3628
deleted file mode 100644
index fa58233..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/36/b17d87575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,78 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_spinlock.h
-*
-* This header file contains function prototypes to be used while using Xilinx
-* spinlocking mechanism.
-* Please refer to file header contents of xil_spinlock.c to understand in
-* detail the spinlocking mechanism.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 7.5 asa 02/16/21 First release
-* 7.6 sk 08/05/21 Add Boolean check and braces for Xil_IsSpinLockEnabled
-* if condition to fix misrac violations.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm 03/10/10 First release
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xscutimer.h"
-
-/************************** Constant Definitions *****************************/
-
-#define XSCUTIMER_SELFTEST_VALUE 0xA55AF00FU
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/****************************************************************************/
-/**
-*
-* Run a self-test on the timer. This test clears the timer enable bit in
-* the control register, writes to the timer load register and verifies the
-* value read back matches the value written and restores the control register
-* and the timer load register.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return
-* - XST_SUCCESS if self-test was successful.
-* - XST_FAILURE if self test was not successful.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XScuTimer_SelfTest(XScuTimer *InstancePtr)
-{
- u32 Register;
- u32 CtrlOrig;
- u32 LoadOrig;
- s32 Status;
-
- /*
- * Assert to ensure the inputs are valid and the instance has been
- * initialized.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Save the contents of the Control Register and stop the timer.
- */
- CtrlOrig = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
- XSCUTIMER_CONTROL_OFFSET);
- Register = CtrlOrig & (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK);
- XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
- XSCUTIMER_CONTROL_OFFSET, Register);
-
- /*
- * Save the contents of the Load Register.
- * Load a new test value in the Load Register, read it back and
- * compare it with the written value.
- */
- LoadOrig = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
- XSCUTIMER_LOAD_OFFSET);
- XScuTimer_LoadTimer(InstancePtr, XSCUTIMER_SELFTEST_VALUE);
- Register = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
- XSCUTIMER_LOAD_OFFSET);
-
- /*
- * Restore the contents of the Load Register and Control Register.
- */
- XScuTimer_LoadTimer(InstancePtr, LoadOrig);
- XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
- XSCUTIMER_CONTROL_OFFSET, CtrlOrig);
-
- /*
- * Return a Failure if the contents of the Load Register do not
- * match with the value written to it.
- */
- if (Register != XSCUTIMER_SELFTEST_VALUE) {
- Status = (s32)XST_FAILURE;
- }
- else {
- Status = (s32)XST_SUCCESS;
- }
-
- return Status;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/37/90bf75565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/37/90bf75565243001d18b399c1eb9b3628
deleted file mode 100644
index f0c63a3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/37/90bf75565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,30 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#include
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) sint32 _isatty(sint32 fd);
-}
-#endif
-
-/*
- * isatty -- returns 1 if connected to a terminal device,
- * returns 0 if not. Since we're hooked up to a
- * serial port, we'll say yes _AND return a 1.
- */
-__attribute__((weak)) sint32 isatty(sint32 fd)
-{
- (void)fd;
- return (1);
-}
-
-__attribute__((weak)) sint32 _isatty(sint32 fd)
-{
- (void)fd;
- return (1);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/37/b15f8c575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/37/b15f8c575243001d18b399c1eb9b3628
deleted file mode 100644
index 31156ee..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/37/b15f8c575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,96 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xl2cc_counter.h
-*
-* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions
-*
-* xl2cc_counter.h contains APIs for configuring and controlling the event
-* counters in PL310 L2 cache controller.
-* PL310 has two event counters which can be used to count variety of events
-* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions
-* for different configurations which can be used for the event counters to
-* count a set of events.
-*
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
-* inside the APIs
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-*
-******************************************************************************/
-
-/**
-*@cond nocomments
-*/
-
-#ifndef L2CCCOUNTER_H /* prevent circular inclusions */
-#define L2CCCOUNTER_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/************************** Constant Definitions ****************************/
-
-/*
- * The following constants define the event codes for the event counters.
- */
-#define XL2CC_CO 0x1
-#define XL2CC_DRHIT 0x2
-#define XL2CC_DRREQ 0x3
-#define XL2CC_DWHIT 0x4
-#define XL2CC_DWREQ 0x5
-#define XL2CC_DWTREQ 0x6
-#define XL2CC_IRHIT 0x7
-#define XL2CC_IRREQ 0x8
-#define XL2CC_WA 0x9
-#define XL2CC_IPFALLOC 0xa
-#define XL2CC_EPFHIT 0xb
-#define XL2CC_EPFALLOC 0xc
-#define XL2CC_SRRCVD 0xd
-#define XL2CC_SRCONF 0xe
-#define XL2CC_EPFRCVD 0xf
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/**
-*@endcond
-*/
-
-/************************** Function Prototypes *****************************/
-
-void XL2cc_EventCtrInit(s32 Event0, s32 Event1);
-void XL2cc_EventCtrStart(void);
-void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* L2CCCOUNTER_H */
-/**
-* @} End of "addtogroup l2_event_counter_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/37/c09e8e565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/37/c09e8e565243001d18b399c1eb9b3628
deleted file mode 100644
index 069dad9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/37/c09e8e565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,36 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file microblaze_exceptions_g.h
-*
-* This file contains the exception handling information for the MicroBlaze
-* processor. This file is usually generated by LibGen.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Date Changes
-* ----- -------- -----------------------------------------------
-* 1.00a 06/24/04 First release
-*
-*
-******************************************************************************/
-#ifndef MICROBLAZE_EXCEPTIONS_G_H /* prevent circular inclusions */
-#define MICROBLAZE_EXCEPTIONS_G_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define MICROBLAZE_EXCEPTIONS_ENABLED 1
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/38/003b1e545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/38/003b1e545243001d18b399c1eb9b3628
deleted file mode 100644
index 51cc7c5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/38/003b1e545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,477 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xadcps_hw.h
-* @addtogroup xadcps_v2_6
-* @{
-*
-* This header file contains identifiers and basic driver functions (or
-* macros) that can be used to access the XADC device through the Device
-* Config Interface of the Zynq.
-*
-*
-* Refer to the device specification for more information about this driver.
-*
-* @note None.
-*
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a bss 12/22/11 First release based on the XPS/AXI xadc driver
-* 1.03a bss 11/01/13 Modified macros to use correct Register offsets
-* CR#749687
-* 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors.
-*
-*
-*
-*****************************************************************************/
-#ifndef XADCPS_HW_H /* Prevent circular inclusions */
-#define XADCPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**@name Register offsets of XADC in the Device Config
- *
- * The following constants provide access to each of the registers of the
- * XADC device.
- * @{
- */
-
-#define XADCPS_CFG_OFFSET 0x00U /**< Configuration Register */
-#define XADCPS_INT_STS_OFFSET 0x04U /**< Interrupt Status Register */
-#define XADCPS_INT_MASK_OFFSET 0x08U /**< Interrupt Mask Register */
-#define XADCPS_MSTS_OFFSET 0x0CU /**< Misc status register */
-#define XADCPS_CMDFIFO_OFFSET 0x10U /**< Command FIFO Register */
-#define XADCPS_RDFIFO_OFFSET 0x14U /**< Read FIFO Register */
-#define XADCPS_MCTL_OFFSET 0x18U /**< Misc control register */
-
-/* @} */
-
-
-
-
-
-/** @name XADC Config Register Bit definitions
- * @{
- */
-#define XADCPS_CFG_ENABLE_MASK 0x80000000U /**< Enable access from PS mask */
-#define XADCPS_CFG_CFIFOTH_MASK 0x00F00000U /**< Command FIFO Threshold mask */
-#define XADCPS_CFG_DFIFOTH_MASK 0x000F0000U /**< Data FIFO Threshold mask */
-#define XADCPS_CFG_WEDGE_MASK 0x00002000U /**< Write Edge Mask */
-#define XADCPS_CFG_REDGE_MASK 0x00001000U /**< Read Edge Mask */
-#define XADCPS_CFG_TCKRATE_MASK 0x00000300U /**< Clock freq control */
-#define XADCPS_CFG_IGAP_MASK 0x0000001FU /**< Idle Gap between
- * successive commands */
-/* @} */
-
-
-/** @name XADC Interrupt Status/Mask Register Bit definitions
- *
- * The definitions are same for the Interrupt Status Register and
- * Interrupt Mask Register. They are defined only once.
- * @{
- */
-#define XADCPS_INTX_ALL_MASK 0x000003FFU /**< Alarm Signals Mask */
-#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200U /**< CMD FIFO less than threshold */
-#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100U /**< Data FIFO greater than threshold */
-#define XADCPS_INTX_OT_MASK 0x00000080U /**< Over temperature Alarm Status */
-#define XADCPS_INTX_ALM_ALL_MASK 0x0000007FU /**< Alarm Signals Mask */
-#define XADCPS_INTX_ALM6_MASK 0x00000040U /**< Alarm 6 Mask */
-#define XADCPS_INTX_ALM5_MASK 0x00000020U /**< Alarm 5 Mask */
-#define XADCPS_INTX_ALM4_MASK 0x00000010U /**< Alarm 4 Mask */
-#define XADCPS_INTX_ALM3_MASK 0x00000008U /**< Alarm 3 Mask */
-#define XADCPS_INTX_ALM2_MASK 0x00000004U /**< Alarm 2 Mask */
-#define XADCPS_INTX_ALM1_MASK 0x00000002U /**< Alarm 1 Mask */
-#define XADCPS_INTX_ALM0_MASK 0x00000001U /**< Alarm 0 Mask */
-
-/* @} */
-
-
-/** @name XADC Miscellaneous Register Bit definitions
- * @{
- */
-#define XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000U /**< Command FIFO Level mask */
-#define XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000U /**< Data FIFO Level Mask */
-#define XADCPS_MSTS_CFIFOF_MASK 0x00000800U /**< Command FIFO Full Mask */
-#define XADCPS_MSTS_CFIFOE_MASK 0x00000400U /**< Command FIFO Empty Mask */
-#define XADCPS_MSTS_DFIFOF_MASK 0x00000200U /**< Data FIFO Full Mask */
-#define XADCPS_MSTS_DFIFOE_MASK 0x00000100U /**< Data FIFO Empty Mask */
-#define XADCPS_MSTS_OT_MASK 0x00000080U /**< Over Temperature Mask */
-#define XADCPS_MSTS_ALM_MASK 0x0000007FU /**< Alarms Mask */
-/* @} */
-
-
-/** @name XADC Miscellaneous Control Register Bit definitions
- * @{
- */
-#define XADCPS_MCTL_RESET_MASK 0x00000010U /**< Reset XADC */
-#define XADCPS_MCTL_FLUSH_MASK 0x00000001U /**< Flush the FIFOs */
-/* @} */
-
-
-/**@name Internal Register offsets of the XADC
- *
- * The following constants provide access to each of the internal registers of
- * the XADC device.
- * @{
- */
-
-/*
- * XADC Internal Channel Registers
- */
-#define XADCPS_TEMP_OFFSET 0x00U /**< On-chip Temperature Reg */
-#define XADCPS_VCCINT_OFFSET 0x01U /**< On-chip VCCINT Data Reg */
-#define XADCPS_VCCAUX_OFFSET 0x02U /**< On-chip VCCAUX Data Reg */
-#define XADCPS_VPVN_OFFSET 0x03U /**< ADC out of VP/VN */
-#define XADCPS_VREFP_OFFSET 0x04U /**< On-chip VREFP Data Reg */
-#define XADCPS_VREFN_OFFSET 0x05U /**< On-chip VREFN Data Reg */
-#define XADCPS_VBRAM_OFFSET 0x06U /**< On-chip VBRAM , 7 Series */
-#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08U /**< ADC A Supply Offset Reg */
-#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09U /**< ADC A Offset Data Reg */
-#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0AU /**< ADC A Gain Error Reg */
-#define XADCPS_VCCPINT_OFFSET 0x0DU /**< On-chip VCCPINT Reg, Zynq */
-#define XADCPS_VCCPAUX_OFFSET 0x0EU /**< On-chip VCCPAUX Reg, Zynq */
-#define XADCPS_VCCPDRO_OFFSET 0x0FU /**< On-chip VCCPDRO Reg, Zynq */
-
-/*
- * XADC External Channel Registers
- */
-#define XADCPS_AUX00_OFFSET 0x10U /**< ADC out of VAUXP0/VAUXN0 */
-#define XADCPS_AUX01_OFFSET 0x11U /**< ADC out of VAUXP1/VAUXN1 */
-#define XADCPS_AUX02_OFFSET 0x12U /**< ADC out of VAUXP2/VAUXN2 */
-#define XADCPS_AUX03_OFFSET 0x13U /**< ADC out of VAUXP3/VAUXN3 */
-#define XADCPS_AUX04_OFFSET 0x14U /**< ADC out of VAUXP4/VAUXN4 */
-#define XADCPS_AUX05_OFFSET 0x15U /**< ADC out of VAUXP5/VAUXN5 */
-#define XADCPS_AUX06_OFFSET 0x16U /**< ADC out of VAUXP6/VAUXN6 */
-#define XADCPS_AUX07_OFFSET 0x17U /**< ADC out of VAUXP7/VAUXN7 */
-#define XADCPS_AUX08_OFFSET 0x18U /**< ADC out of VAUXP8/VAUXN8 */
-#define XADCPS_AUX09_OFFSET 0x19U /**< ADC out of VAUXP9/VAUXN9 */
-#define XADCPS_AUX10_OFFSET 0x1AU /**< ADC out of VAUXP10/VAUXN10 */
-#define XADCPS_AUX11_OFFSET 0x1BU /**< ADC out of VAUXP11/VAUXN11 */
-#define XADCPS_AUX12_OFFSET 0x1CU /**< ADC out of VAUXP12/VAUXN12 */
-#define XADCPS_AUX13_OFFSET 0x1DU /**< ADC out of VAUXP13/VAUXN13 */
-#define XADCPS_AUX14_OFFSET 0x1EU /**< ADC out of VAUXP14/VAUXN14 */
-#define XADCPS_AUX15_OFFSET 0x1FU /**< ADC out of VAUXP15/VAUXN15 */
-
-/*
- * XADC Registers for Maximum/Minimum data captured for the
- * on chip Temperature/VCCINT/VCCAUX data.
- */
-#define XADCPS_MAX_TEMP_OFFSET 0x20U /**< Max Temperature Reg */
-#define XADCPS_MAX_VCCINT_OFFSET 0x21U /**< Max VCCINT Register */
-#define XADCPS_MAX_VCCAUX_OFFSET 0x22U /**< Max VCCAUX Register */
-#define XADCPS_MAX_VCCBRAM_OFFSET 0x23U /**< Max BRAM Register, 7 series */
-#define XADCPS_MIN_TEMP_OFFSET 0x24U /**< Min Temperature Reg */
-#define XADCPS_MIN_VCCINT_OFFSET 0x25U /**< Min VCCINT Register */
-#define XADCPS_MIN_VCCAUX_OFFSET 0x26U /**< Min VCCAUX Register */
-#define XADCPS_MIN_VCCBRAM_OFFSET 0x27U /**< Min BRAM Register, 7 series */
-#define XADCPS_MAX_VCCPINT_OFFSET 0x28U /**< Max VCCPINT Register, Zynq */
-#define XADCPS_MAX_VCCPAUX_OFFSET 0x29U /**< Max VCCPAUX Register, Zynq */
-#define XADCPS_MAX_VCCPDRO_OFFSET 0x2AU /**< Max VCCPDRO Register, Zynq */
-#define XADCPS_MIN_VCCPINT_OFFSET 0x2CU /**< Min VCCPINT Register, Zynq */
-#define XADCPS_MIN_VCCPAUX_OFFSET 0x2DU /**< Min VCCPAUX Register, Zynq */
-#define XADCPS_MIN_VCCPDRO_OFFSET 0x2EU /**< Min VCCPDRO Register,Zynq */
- /* Undefined 0x2F to 0x3E */
-#define XADCPS_FLAG_OFFSET 0x3FU /**< Flag Register */
-
-/*
- * XADC Configuration Registers
- */
-#define XADCPS_CFR0_OFFSET 0x40U /**< Configuration Register 0 */
-#define XADCPS_CFR1_OFFSET 0x41U /**< Configuration Register 1 */
-#define XADCPS_CFR2_OFFSET 0x42U /**< Configuration Register 2 */
-
-/* Test Registers 0x43 to 0x47 */
-
-/*
- * XADC Sequence Registers
- */
-#define XADCPS_SEQ00_OFFSET 0x48U /**< Seq Reg 00 Adc Channel Selection */
-#define XADCPS_SEQ01_OFFSET 0x49U /**< Seq Reg 01 Adc Channel Selection */
-#define XADCPS_SEQ02_OFFSET 0x4AU /**< Seq Reg 02 Adc Average Enable */
-#define XADCPS_SEQ03_OFFSET 0x4BU /**< Seq Reg 03 Adc Average Enable */
-#define XADCPS_SEQ04_OFFSET 0x4CU /**< Seq Reg 04 Adc Input Mode Select */
-#define XADCPS_SEQ05_OFFSET 0x4DU /**< Seq Reg 05 Adc Input Mode Select */
-#define XADCPS_SEQ06_OFFSET 0x4EU /**< Seq Reg 06 Adc Acquisition Select */
-#define XADCPS_SEQ07_OFFSET 0x4FU /**< Seq Reg 07 Adc Acquisition Select */
-
-/*
- * XADC Alarm Threshold/Limit Registers (ATR)
- */
-#define XADCPS_ATR_TEMP_UPPER_OFFSET 0x50U /**< Temp Upper Alarm Register */
-#define XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51U /**< VCCINT Upper Alarm Reg */
-#define XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52U /**< VCCAUX Upper Alarm Reg */
-#define XADCPS_ATR_OT_UPPER_OFFSET 0x53U /**< Over Temp Upper Alarm Reg */
-#define XADCPS_ATR_TEMP_LOWER_OFFSET 0x54U /**< Temp Lower Alarm Register */
-#define XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55U /**< VCCINT Lower Alarm Reg */
-#define XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56U /**< VCCAUX Lower Alarm Reg */
-#define XADCPS_ATR_OT_LOWER_OFFSET 0x57U /**< Over Temp Lower Alarm Reg */
-#define XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58U /**< VBRAM Upper Alarm, 7 series */
-#define XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59U /**< VCCPINT Upper Alarm, Zynq */
-#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5AU /**< VCCPAUX Upper Alarm, Zynq */
-#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5BU /**< VCCPDRO Upper Alarm, Zynq */
-#define XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5CU /**< VRBAM Lower Alarm, 7 Series */
-#define XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5DU /**< VCCPINT Lower Alarm, Zynq */
-#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5EU /**< VCCPAUX Lower Alarm, Zynq */
-#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5FU /**< VCCPDRO Lower Alarm, Zynq */
-
-/* Undefined 0x60 to 0x7F */
-
-/*@}*/
-
-
-
-/**
- * @name Configuration Register 0 (CFR0) mask(s)
- * @{
- */
-#define XADCPS_CFR0_CAL_AVG_MASK 0x00008000U /**< Averaging enable Mask */
-#define XADCPS_CFR0_AVG_VALID_MASK 0x00003000U /**< Averaging bit Mask */
-#define XADCPS_CFR0_AVG1_MASK 0x00000000U /**< No Averaging */
-#define XADCPS_CFR0_AVG16_MASK 0x00001000U /**< Average 16 samples */
-#define XADCPS_CFR0_AVG64_MASK 0x00002000U /**< Average 64 samples */
-#define XADCPS_CFR0_AVG256_MASK 0x00003000U /**< Average 256 samples */
-#define XADCPS_CFR0_AVG_SHIFT 12U /**< Averaging bits shift */
-#define XADCPS_CFR0_MUX_MASK 0x00000800U /**< External Mask Enable */
-#define XADCPS_CFR0_DU_MASK 0x00000400U /**< Bipolar/Unipolar mode */
-#define XADCPS_CFR0_EC_MASK 0x00000200U /**< Event driven/
- * Continuous mode selection
- */
-#define XADCPS_CFR0_ACQ_MASK 0x00000100U /**< Add acquisition by 6 ADCCLK */
-#define XADCPS_CFR0_CHANNEL_MASK 0x0000001FU /**< Channel number bit Mask */
-
-/*@}*/
-
-/**
- * @name Configuration Register 1 (CFR1) mask(s)
- * @{
- */
-#define XADCPS_CFR1_SEQ_VALID_MASK 0x0000F000U /**< Sequence bit Mask */
-#define XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x00000000U /**< Default Safe Mode */
-#define XADCPS_CFR1_SEQ_ONEPASS_MASK 0x00001000U /**< Onepass through Seq */
-#define XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x00002000U /**< Continuous Cycling Seq */
-#define XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x00003000U /**< Single channel - No Seq */
-#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x00004000U /**< Simulataneous Sampling Mask */
-#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x00008000U /**< Independent Mode */
-#define XADCPS_CFR1_SEQ_SHIFT 12U /**< Sequence bit shift */
-#define XADCPS_CFR1_ALM_VCCPDRO_MASK 0x00000800U /**< Alm 6 - VCCPDRO, Zynq */
-#define XADCPS_CFR1_ALM_VCCPAUX_MASK 0x00000400U /**< Alm 5 - VCCPAUX, Zynq */
-#define XADCPS_CFR1_ALM_VCCPINT_MASK 0x00000200U /**< Alm 4 - VCCPINT, Zynq */
-#define XADCPS_CFR1_ALM_VBRAM_MASK 0x00000100U /**< Alm 3 - VBRAM, 7 series */
-#define XADCPS_CFR1_CAL_VALID_MASK 0x000000F0U /**< Valid Calibration Mask */
-#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x00000080U /**< Calibration 3 -Power
- Supply Gain/Offset
- Enable */
-#define XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x00000040U /**< Calibration 2 -Power
- Supply Offset Enable */
-#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x00000020U /**< Calibration 1 -ADC Gain
- Offset Enable */
-#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x00000010U /**< Calibration 0 -ADC Offset
- Enable */
-#define XADCPS_CFR1_CAL_DISABLE_MASK 0x00000000U /**< No Calibration */
-#define XADCPS_CFR1_ALM_ALL_MASK 0x00000F0FU /**< Mask for all alarms */
-#define XADCPS_CFR1_ALM_VCCAUX_MASK 0x00000008U /**< Alarm 2 - VCCAUX Enable */
-#define XADCPS_CFR1_ALM_VCCINT_MASK 0x00000004U /**< Alarm 1 - VCCINT Enable */
-#define XADCPS_CFR1_ALM_TEMP_MASK 0x00000002U /**< Alarm 0 - Temperature */
-#define XADCPS_CFR1_OT_MASK 0x00000001U /**< Over Temperature Enable */
-
-/*@}*/
-
-/**
- * @name Configuration Register 2 (CFR2) mask(s)
- * @{
- */
-#define XADCPS_CFR2_CD_VALID_MASK 0xFF00U /**
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00 sdm 11/25/10 First release
-* 2.00a kka 07/25/12 Removed the selection for the following options:
-* Master mode (XQSPIPS_MASTER_OPTION) and
-* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
-* as the QSPI driver supports the Master mode
-* and Flash Interface mode. The driver doesnot support
-* Slave mode or the legacy mode.
-* Added the option for setting the Holdb_dr bit in the
-* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
-* is the option to be used for setting this bit in the
-* configuration register.
-* 2.01a sg 02/03/13 SetDelays and GetDelays API's include DelayNss parameter.
-*
-* 2.02a hk 26/03/13 Removed XQspi_Reset() in Set_Options() function when
-* LQSPI_MODE_OPTION is set. Moved Enable() to XQpsiPs_LqspiRead().
-* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
-* to remove compilation warnings. CR# 868893.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xqspips.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/*
- * Create the table of options which are processed to get/set the device
- * options. These options are table driven to allow easy maintenance and
- * expansion of the options.
- */
-typedef struct {
- u32 Option;
- u32 Mask;
-} OptionsMap;
-
-static OptionsMap OptionsTable[] = {
- {XQSPIPS_CLK_ACTIVE_LOW_OPTION, XQSPIPS_CR_CPOL_MASK},
- {XQSPIPS_CLK_PHASE_1_OPTION, XQSPIPS_CR_CPHA_MASK},
- {XQSPIPS_FORCE_SSELECT_OPTION, XQSPIPS_CR_SSFORCE_MASK},
- {XQSPIPS_MANUAL_START_OPTION, XQSPIPS_CR_MANSTRTEN_MASK},
- {XQSPIPS_HOLD_B_DRIVE_OPTION, XQSPIPS_CR_HOLD_B_MASK},
-};
-
-#define XQSPIPS_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionsMap))
-
-/*****************************************************************************/
-/**
-*
-* This function sets the options for the QSPI device driver. The options control
-* how the device behaves relative to the QSPI bus. The device must be idle
-* rather than busy transferring data before setting these device options.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param Options contains the specified options to be set. This is a bit
-* mask where a 1 means to turn the option on, and a 0 means to
-* turn the option off. One or more bit values may be contained in
-* the mask. See the bit definitions named XQSPIPS_*_OPTIONS in
-* the file xqspips.h.
-*
-* @return
-* - XST_SUCCESS if options are successfully set.
-* - XST_DEVICE_BUSY if the device is currently transferring data.
-* The transfer must complete or be aborted before setting options.
-*
-* @note
-* This function is not thread-safe.
-*
-******************************************************************************/
-s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options)
-{
- u32 ConfigReg;
- unsigned int Index;
- u32 QspiOptions;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Do not allow to modify the Control Register while a transfer is in
- * progress. Not thread-safe.
- */
- if (InstancePtr->IsBusy) {
- return XST_DEVICE_BUSY;
- }
-
- QspiOptions = Options & XQSPIPS_LQSPI_MODE_OPTION;
- Options &= ~XQSPIPS_LQSPI_MODE_OPTION;
-
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
-
- /*
- * Loop through the options table, turning the option on or off
- * depending on whether the bit is set in the incoming options flag.
- */
- for (Index = 0; Index < XQSPIPS_NUM_OPTIONS; Index++) {
- if (Options & OptionsTable[Index].Option) {
- /* Turn it on */
- ConfigReg |= OptionsTable[Index].Mask;
- } else {
- /* Turn it off */
- ConfigReg &= ~(OptionsTable[Index].Mask);
- }
- }
-
- /*
- * Now write the control register. Leave it to the upper layers
- * to restart the device.
- */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET,
- ConfigReg);
-
- /*
- * Check for the LQSPI configuration options.
- */
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_LQSPI_CR_OFFSET);
-
-
- if (QspiOptions & XQSPIPS_LQSPI_MODE_OPTION) {
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_LQSPI_CR_OFFSET,
- XQSPIPS_LQSPI_CR_RST_STATE);
- XQspiPs_SetSlaveSelect(InstancePtr);
- } else {
- ConfigReg &= ~XQSPIPS_LQSPI_CR_LINEAR_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_LQSPI_CR_OFFSET, ConfigReg);
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function gets the options for the QSPI device. The options control how
-* the device behaves relative to the QSPI bus.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return
-*
-* Options contains the specified options currently set. This is a bit value
-* where a 1 means the option is on, and a 0 means the option is off.
-* See the bit definitions named XQSPIPS_*_OPTIONS in file xqspips.h.
-*
-* @note None.
-*
-******************************************************************************/
-u32 XQspiPs_GetOptions(XQspiPs *InstancePtr)
-{
- u32 OptionsFlag = 0;
- u32 ConfigReg;
- unsigned int Index;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Get the current options from QSPI configuration register.
- */
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
-
- /*
- * Loop through the options table to grab options
- */
- for (Index = 0; Index < XQSPIPS_NUM_OPTIONS; Index++) {
- if (ConfigReg & OptionsTable[Index].Mask) {
- OptionsFlag |= OptionsTable[Index].Option;
- }
- }
-
- /*
- * Check for the LQSPI configuration options.
- */
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_LQSPI_CR_OFFSET);
-
- if ((ConfigReg & XQSPIPS_LQSPI_CR_LINEAR_MASK) != 0) {
- OptionsFlag |= XQSPIPS_LQSPI_MODE_OPTION;
- }
-
- return OptionsFlag;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets the clock prescaler for an QSPI device. The device
-* must be idle rather than busy transferring data before setting these device
-* options.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param Prescaler is the value that determine how much the clock should
-* be divided by. Use the XQSPIPS_CLK_PRESCALE_* constants defined
-* in xqspips.h for this setting.
-*
-* @return
-* - XST_SUCCESS if options are successfully set.
-* - XST_DEVICE_BUSY if the device is currently transferring data.
-* The transfer must complete or be aborted before setting options.
-*
-* @note
-* This function is not thread-safe.
-*
-******************************************************************************/
-s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler)
-{
- u32 ConfigReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Prescaler <= XQSPIPS_CR_PRESC_MAXIMUM);
-
- /*
- * Do not allow the slave select to change while a transfer is in
- * progress. Not thread-safe.
- */
- if (InstancePtr->IsBusy) {
- return XST_DEVICE_BUSY;
- }
-
- /*
- * Read the configuration register, mask out the interesting bits, and set
- * them with the shifted value passed into the function. Write the
- * results back to the configuration register.
- */
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
-
- ConfigReg &= ~XQSPIPS_CR_PRESC_MASK;
- ConfigReg |= (u32) (Prescaler & XQSPIPS_CR_PRESC_MAXIMUM) <<
- XQSPIPS_CR_PRESC_SHIFT;
-
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET,
- ConfigReg);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function gets the clock prescaler of an QSPI device.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return The prescaler value.
-*
-* @note None.
-*
-*
-******************************************************************************/
-u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr)
-{
- u32 ConfigReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
-
- ConfigReg &= XQSPIPS_CR_PRESC_MASK;
-
- return (u8)(ConfigReg >> XQSPIPS_CR_PRESC_SHIFT);
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets the delay register for the QSPI device driver.
-* The delay register controls the Delay Between Transfers, Delay After
-* Transfers, and the Delay Initially. The default value is 0x0. The range of
-* each delay value is 0-255.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param DelayNss is the delay to de-assert slave select between
-* two word transfers.
-* @param DelayBtwn is the delay between one Slave Select being
-* de-activated and the activation of another slave. The delay is
-* the number of master clock periods given by DelayBtwn + 2.
-* @param DelayAfter define the delay between the last bit of the current
-* byte transfer and the first bit of the next byte transfer.
-* The delay in number of master clock periods is given as:
-* CHPA=0:DelayInit+DelayAfter+3
-* CHPA=1:DelayAfter+1
-* @param DelayInit is the delay between asserting the slave select signal
-* and the first bit transfer. The delay int number of master clock
-* periods is DelayInit+1.
-*
-* @return
-* - XST_SUCCESS if delays are successfully set.
-* - XST_DEVICE_BUSY if the device is currently transferring data.
-* The transfer must complete or be aborted before setting options.
-*
-* @note None.
-*
-******************************************************************************/
-int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
- u8 DelayAfter, u8 DelayInit)
-{
- u32 DelayRegister;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Do not allow the delays to change while a transfer is in
- * progress. Not thread-safe.
- */
- if (InstancePtr->IsBusy) {
- return XST_DEVICE_BUSY;
- }
-
- /* Shift, Mask and OR the values to build the register settings */
- DelayRegister = (u32) DelayNss << XQSPIPS_DR_NSS_SHIFT;
- DelayRegister |= (u32) DelayBtwn << XQSPIPS_DR_BTWN_SHIFT;
- DelayRegister |= (u32) DelayAfter << XQSPIPS_DR_AFTER_SHIFT;
- DelayRegister |= (u32) DelayInit;
-
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_DR_OFFSET, DelayRegister);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function gets the delay settings for an QSPI device.
-* The delay register controls the Delay Between Transfers, Delay After
-* Transfers, and the Delay Initially. The default value is 0x0.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param DelayNss is a pointer to the Delay to de-assert slave select
-* between two word transfers.
-* @param DelayBtwn is a pointer to the Delay Between transfers value.
-* This is a return parameter.
-* @param DelayAfter is a pointer to the Delay After transfer value.
-* This is a return parameter.
-* @param DelayInit is a pointer to the Delay Initially value. This is
-* a return parameter.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
- u8 *DelayAfter, u8 *DelayInit)
-{
- u32 DelayRegister;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- DelayRegister = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_DR_OFFSET);
-
- *DelayInit = (u8)(DelayRegister & XQSPIPS_DR_INIT_MASK);
-
- *DelayAfter = (u8)((DelayRegister & XQSPIPS_DR_AFTER_MASK) >>
- XQSPIPS_DR_AFTER_SHIFT);
-
- *DelayBtwn = (u8)((DelayRegister & XQSPIPS_DR_BTWN_MASK) >>
- XQSPIPS_DR_BTWN_SHIFT);
-
- *DelayNss = (u8)((DelayRegister & XQSPIPS_DR_NSS_MASK) >>
- XQSPIPS_DR_NSS_SHIFT);
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/38/120cb5595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/38/120cb5595243001d18b399c1eb9b3628
deleted file mode 100644
index aa666d1..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/38/120cb5595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1568 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_testmem.c
-* @addtogroup common_test_utils
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 08/25/09 First release
-* 7.5 mus 03/10/21 Added new set of Xil_TestMem32, Xil_TestMem16 and
-* Xil_TestMem8 APIs to support memory test for memory
-* regions mapped at extended addresses
-* (addresses > 4 GB). These new set of APIs would be
-* compiled only for 32 bit Microblaze processor, if
-* XPAR_MICROBLAZE_ADDR_SIZE is greater than 32.
-* It fixes CR#1089129.
-* 7.6 mus 07/29/21 Updated Xil_TestMem8 to fix issues reported by static
-* analysis tool. It fixes CR#1105956.
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xil_testmem.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions ****************************/
-/************************** Function Prototypes *****************************/
-
-static u32 RotateLeft(u32 Input, u8 Width);
-
-/* define ROTATE_RIGHT to give access to this functionality */
-/* #define ROTATE_RIGHT */
-#ifdef ROTATE_RIGHT
-static u32 RotateRight(u32 Input, u8 Width);
-#endif /* ROTATE_RIGHT */
-
-#if defined(__MICROBLAZE__) && !defined(__arch64__) && (XPAR_MICROBLAZE_ADDR_SIZE > 32)
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 8-bit wide memory test.
-*
-* @param Addrlow: lower 32 bit address of memory to be tested.
-* @param Addrhigh: upper 32 bit address of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: type of test selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u8 Val;
- u8 WordMem8;
- s32 Status = 0;
- u64 Addr = (Addrlow + ((u64)Addrhigh << 32));
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * select the proper Subtest(s)
- */
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from XIL_TESTMEM_INIT_VALUE
- */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- sbea(Addr+I, Val);
- Val++;
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = XIL_TESTMEM_INIT_VALUE;
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference
- * Val
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = lbuea(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val++;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking ones test
- */
-
- for (j = 0U; j < NUM_OF_BITS_IN_BYTE; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
- Val = (u8)((u32)1 << j);
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
- for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) {
- /* write memory location */
- sbea(Addr+I, Val);
- Val = (u8)RotateLeft(Val, 8U);
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u8)((u32)1 << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) {
- /* read memory location */
- WordMem8 = lbuea(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = (u8)RotateLeft(Val, NUM_OF_BITS_IN_BYTE);
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible initial test
- * Patterns for walking zeros test
- */
-
- for (j = 0U; j < NUM_OF_BITS_IN_BYTE; j++) {
- /*
- * Generate an initial value for walking ones test to test
- * for bad data bits
- */
- Val = (u8) (~(1U << j));
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
- for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) {
- /* write memory location */
- sbea(Addr+I, Val);
- Val = ~((u8)RotateLeft(~Val, NUM_OF_BITS_IN_BYTE));
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u8) (~(1U << j));
- /* Read the values from each location that was written */
- for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) {
- /* read memory location */
- WordMem8 = lbuea(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val = ~((u8)RotateLeft(~Val, NUM_OF_BITS_IN_BYTE));
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- Val = (u8) (~((INTPTR) (Addr + I)));
- sbea(Addr+I, Val);
- }
-
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = lbuea(Addr+I);
- Val = (u8) (~((INTPTR) (Addr+I)));
- if ((WordMem8 ^ Val) != 0x00U) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
-
- if (Pattern == (u8)0) {
- Val = 0xA5U;
- }
- else {
- Val = Pattern;
- }
- /*
- * Fill the memory with fixed Pattern
- */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- sbea(Addr+I, Val);
- }
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed Pattern
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = lbuea(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
-End_Label:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 16-bit wide memory test.
-*
-* @param Addrlow: lower 32 bit address of memory to be tested.
-* @param Addrhigh: upper 32 bit address of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant Pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: type of test selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u16 Val;
- u16 WordMem16;
- s32 Status = 0;
- u64 Addr = (Addrlow + ((u64)Addrhigh << 32));
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * selectthe proper Subtest(s)
- */
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from 'XIL_TESTMEM_INIT_VALUE'
- */
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) {
- /* write memory location */
- shea(Addr+I, Val);
- Val++;
- I = I + NUM_OF_BYTES_IN_HW;
- }
-
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference val
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) {
- /* read memory location */
- WordMem16 = lhuea(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val++;
- I = I + NUM_OF_BYTES_IN_HW;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial test
- * Patterns for walking ones test
- */
-
- for (j = 0U; j < NUM_OF_BITS_IN_HW; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = (u16)((u32)1 << j);
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) {
- /* write memory location */
- shea(Addr+I,Val);
- Val = (u16)RotateLeft(Val, 16U);
- I = I + NUM_OF_BYTES_IN_HW;
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u16)((u32)1 << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) {
- /* read memory location */
- WordMem16 = lhuea(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = (u16)RotateLeft(Val, NUM_OF_BITS_IN_HW);
- I = I + NUM_OF_BYTES_IN_HW;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking zeros test
- */
-
- for (j = 0U; j < NUM_OF_BITS_IN_HW; j++) {
- /*
- * Generate an initial value for walking ones
- * test to test for bad
- * data bits
- */
-
- Val = ~(1U << j);
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW);) {
- shea(Addr+I, Val);
- Val = ~((u16)RotateLeft(~Val, 16U));
- I = I + NUM_OF_BYTES_IN_HW;
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = ~(1U << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) {
- WordMem16= lhuea(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = ~((u16)RotateLeft(~Val, NUM_OF_BITS_IN_HW));
- I = I + NUM_OF_BYTES_IN_HW;
- }
-
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) {
- /* write memory location */
- Val = (u16) (~((INTPTR)((Addr+I))));
- shea(Addr+I, Val);
- I = I + NUM_OF_BYTES_IN_HW;
- }
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW*Words); ) {
- /* read memory location */
- //WordMem16 = *(Addr+I);
- WordMem16 = lhuea(Addr+I);
- Val = (u16) (~((INTPTR) ((Addr+I))));
- if ((WordMem16 ^ Val) != 0x0000U) {
- Status = -1;
- goto End_Label;
- }
- I = I + NUM_OF_BYTES_IN_HW;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
- if (Pattern == (u16)0) {
- Val = 0xDEADU;
- }
- else {
- Val = Pattern;
- }
-
- /*
- * Fill the memory with fixed pattern
- */
-
- for (I = 0U; I < (2*Words);) {
- /* write memory location */
- shea(Addr+I, Val);
- I = I + NUM_OF_BYTES_IN_HW;
- }
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed pattern
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) {
- /* read memory location */
- WordMem16=lhuea(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- I = I + NUM_OF_BYTES_IN_HW;
- }
- }
-End_Label:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 32-bit wide memory test.
-*
-* @param Addrlow: lower 32 bit address of memory to be tested.
-* @param Addrhigh: upper 32 bit address of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: test type selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-* - 0 is returned for a pass
-* - 1 is returned for a failure
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u32 Val;
- u32 WordMem32;
- s32 Status = 0;
- u64 Addr = (Addrlow + ((u64)Addrhigh << 32));
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
-
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from 'XIL_TESTMEM_INIT_VALUE'
- */
- for (I = 0U; I <(NUM_OF_BYTES_IN_WORD * Words);) {
- swea(Addr+I, Val);
- Val++;
- I = I + NUM_OF_BYTES_IN_WORD;
- }
-
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference
- * Val
- */
-
- for (I = 0U; I < ( NUM_OF_BYTES_IN_WORD * Words);) {
- WordMem32 = lwea(Addr+I);
-
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val++;
- I = I + NUM_OF_BYTES_IN_WORD;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking ones test
- */
-
- for (j = 0U; j < NUM_OF_BITS_IN_WORD; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = (1U << j);
-
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * NUM_OF_BITS_IN_WORD);) {
- /* write memory location */
- swea(Addr+I, Val);
- Val = (u32) RotateLeft(Val, NUM_OF_BITS_IN_WORD);
- I = I + NUM_OF_BYTES_IN_WORD;
- }
-
- /*
- * Restore the reference 'val' to the
- * initial value
- */
- Val = 1U << j;
-
- /* Read the values from each location that was
- * written */
- for (I = 0U; I < ((u32)32 * NUM_OF_BYTES_IN_WORD);) {
- /* read memory location */
-
- WordMem32 = lwea(Addr+I);
-
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val = (u32)RotateLeft(Val, NUM_OF_BITS_IN_WORD);
- I = I + NUM_OF_BYTES_IN_WORD;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible
- * initial test Patterns for walking zeros test
- */
-
- for (j = 0U; j < NUM_OF_BITS_IN_WORD; j++) {
-
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = ~(1U << j);
-
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (NUM_OF_BITS_IN_WORD * NUM_OF_BYTES_IN_WORD);) {
- /* write memory location */
- swea(Addr+I, Val);
- Val = ~((u32)RotateLeft(~Val, NUM_OF_BITS_IN_WORD));
- I = I + NUM_OF_BYTES_IN_WORD;
- }
-
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
-
- Val = ~(1U << j);
-
- /* Read the values from each location that was
- * written */
- for (I = 0U; I < (NUM_OF_BITS_IN_WORD * NUM_OF_BYTES_IN_WORD);) {
- /* read memory location */
- WordMem32 = lwea(Addr+I);
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = ~((u32)RotateLeft(~Val, NUM_OF_BITS_IN_WORD));
- I = I + NUM_OF_BYTES_IN_WORD;
- }
-
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) {
- /* write memory location */
- Val = (u32) (~((INTPTR) (Addr+I)));
- swea(Addr+I, Val);
- I = I + NUM_OF_BYTES_IN_WORD;
- }
-
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) {
- /* Read the location */
- WordMem32 = lwea(Addr+I);
- Val = (u32) (~((INTPTR) (Addr+I)));
-
- if ((WordMem32 ^ Val) != 0x00000000U) {
- Status = -1;
- goto End_Label;
- }
- I = I + NUM_OF_BYTES_IN_WORD;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
-
- if (Pattern == (u32)0) {
- Val = 0xDEADBEEFU;
- }
- else {
- Val = Pattern;
- }
-
- /*
- * Fill the memory with fixed Pattern
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) {
- /* write memory location */
- swea(Addr+I, Val);
- I = I + NUM_OF_BYTES_IN_WORD;
- }
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed Pattern
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) {
-
- /* read memory location */
-
- WordMem32 = lwea(Addr+I);
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
- I = I + NUM_OF_BYTES_IN_WORD;
- }
- }
-
-End_Label:
- return Status;
-}
-
-#else
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 32-bit wide memory test.
-*
-* @param Addr: pointer to the region of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: test type selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-* - 0 is returned for a pass
-* - 1 is returned for a failure
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u32 Val;
- u32 FirtVal;
- u32 WordMem32;
- s32 Status = 0;
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
- FirtVal = XIL_TESTMEM_INIT_VALUE;
-
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from 'FirtVal'
- */
- for (I = 0U; I < Words; I++) {
- *(Addr+I) = Val;
- Val++;
- }
-
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = FirtVal;
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference
- * Val
- */
-
- for (I = 0U; I < Words; I++) {
- WordMem32 = *(Addr+I);
-
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val++;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking ones test
- */
-
- for (j = 0U; j < (u32)32; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = (1U << j);
-
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (u32)32; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = (u32) RotateLeft(Val, 32U);
- }
-
- /*
- * Restore the reference 'val' to the
- * initial value
- */
- Val = 1U << j;
-
- /* Read the values from each location that was
- * written */
- for (I = 0U; I < (u32)32; I++) {
- /* read memory location */
-
- WordMem32 = *(Addr+I);
-
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val = (u32)RotateLeft(Val, 32U);
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible
- * initial test Patterns for walking zeros test
- */
-
- for (j = 0U; j < (u32)32; j++) {
-
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = ~(1U << j);
-
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (u32)32; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = ~((u32)RotateLeft(~Val, 32U));
- }
-
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
-
- Val = ~(1U << j);
-
- /* Read the values from each location that was
- * written */
- for (I = 0U; I < (u32)32; I++) {
- /* read memory location */
- WordMem32 = *(Addr+I);
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = ~((u32)RotateLeft(~Val, 32U));
- }
-
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- Val = (u32) (~((INTPTR) (&Addr[I])));
- *(Addr+I) = Val;
- }
-
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < Words; I++) {
- /* Read the location */
- WordMem32 = *(Addr+I);
- Val = (u32) (~((INTPTR) (&Addr[I])));
-
- if ((WordMem32 ^ Val) != 0x00000000U) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
-
- if (Pattern == (u32)0) {
- Val = 0xDEADBEEFU;
- }
- else {
- Val = Pattern;
- }
-
- /*
- * Fill the memory with fixed Pattern
- */
-
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- }
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed Pattern
- */
-
- for (I = 0U; I < Words; I++) {
-
- /* read memory location */
-
- WordMem32 = *(Addr+I);
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
-End_Label:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 16-bit wide memory test.
-*
-* @param Addr: pointer to the region of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant Pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: type of test selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-* @note Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u16 Val;
- u16 FirtVal;
- u16 WordMem16;
- s32 Status = 0;
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
- FirtVal = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * selectthe proper Subtest(s)
- */
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from 'FirtVal'
- */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val++;
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = FirtVal;
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference val
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val++;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial test
- * Patterns for walking ones test
- */
-
- for (j = 0U; j < (u32)16; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = (u16)((u32)1 << j);
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (u32)16; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = (u16)RotateLeft(Val, 16U);
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u16)((u32)1 << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < (u32)16; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = (u16)RotateLeft(Val, 16U);
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking zeros test
- */
-
- for (j = 0U; j < (u32)16; j++) {
- /*
- * Generate an initial value for walking ones
- * test to test for bad
- * data bits
- */
-
- Val = ~(1U << j);
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (u32)16; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = ~((u16)RotateLeft(~Val, 16U));
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = ~(1U << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < (u32)16; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = ~((u16)RotateLeft(~Val, 16U));
- }
-
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- Val = (u16) (~((INTPTR)(&Addr[I])));
- *(Addr+I) = Val;
- }
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- Val = (u16) (~((INTPTR) (&Addr[I])));
- if ((WordMem16 ^ Val) != 0x0000U) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
- if (Pattern == (u16)0) {
- Val = 0xDEADU;
- }
- else {
- Val = Pattern;
- }
-
- /*
- * Fill the memory with fixed pattern
- */
-
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- }
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed pattern
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
-End_Label:
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 8-bit wide memory test.
-*
-* @param Addr: pointer to the region of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: type of test selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u8 Val;
- u8 FirtVal;
- u8 WordMem8;
- s32 Status = 0;
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
- FirtVal = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * select the proper Subtest(s)
- */
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from 'FirtVal'
- */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val++;
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = FirtVal;
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference
- * Val
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val++;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking ones test
- */
-
- for (j = 0U; j < (u32)8; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
- Val = (u8)((u32)1 << j);
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
- for (I = 0U; I < (u32)8; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = (u8)RotateLeft(Val, 8U);
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u8)((u32)1 << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < (u32)8; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = (u8)RotateLeft(Val, 8U);
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible initial test
- * Patterns for walking zeros test
- */
-
- for (j = 0U; j < (u32)8; j++) {
- /*
- * Generate an initial value for walking ones test to test
- * for bad data bits
- */
- Val = (u8) (~(1U << j));
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
- for (I = 0U; I < (u32)8; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = ~((u8)RotateLeft(~Val, 8U));
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u8) (~(1U << j));
- /* Read the values from each location that was written */
- for (I = 0U; I < (u32)8; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val = ~((u8)RotateLeft(~Val, 8U));
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- Val = (u8) (~((INTPTR) (&Addr[I])));
- *(Addr+I) = Val;
- }
-
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- Val = (u8) (~((INTPTR) (&Addr[I])));
- if ((WordMem8 ^ Val) != 0x00U) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
-
- if (Pattern == (u8)0) {
- Val = 0xA5U;
- }
- else {
- Val = Pattern;
- }
- /*
- * Fill the memory with fixed Pattern
- */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- }
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed Pattern
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
-End_Label:
- return Status;
-}
-#endif
-
-/*****************************************************************************/
-/**
-*
-* @brief Rotates the provided value to the left one bit position
-*
-* @param Input is value to be rotated to the left
-* @param Width is the number of bits in the input data
-*
-* @return The resulting unsigned long value of the rotate left
-*
-*
-*****************************************************************************/
-static u32 RotateLeft(u32 Input, u8 Width)
-{
- u32 Msb;
- u32 ReturnVal;
- u32 WidthMask;
- u32 MsbMask;
- u32 LocalInput = Input;
-
- /*
- * set up the WidthMask and the MsbMask
- */
-
- MsbMask = 1U << (Width - 1U);
-
- WidthMask = (MsbMask << (u32)1) - (u32)1;
-
- /*
- * set the Width of the Input to the correct width
- */
-
- LocalInput = LocalInput & WidthMask;
-
- Msb = LocalInput & MsbMask;
-
- ReturnVal = LocalInput << 1U;
-
- if (Msb != 0x00000000U) {
- ReturnVal = ReturnVal | (u32)0x00000001;
- }
-
- ReturnVal = ReturnVal & WidthMask;
-
- return ReturnVal;
-
-}
-
-#ifdef ROTATE_RIGHT
-/*****************************************************************************/
-/**
-*
-* @brief Rotates the provided value to the right one bit position
-*
-* @param Input: value to be rotated to the right
-* @param Width: number of bits in the input data
-*
-* @return
-* The resulting u32 value of the rotate right
-*
-*****************************************************************************/
-static u32 RotateRight(u32 Input, u8 Width)
-{
- u32 Lsb;
- u32 ReturnVal;
- u32 WidthMask;
- u32 MsbMask;
- u32 LocalInput = Input;
- /*
- * set up the WidthMask and the MsbMask
- */
-
- MsbMask = 1U << (Width - 1U);
-
- WidthMask = (MsbMask << 1U) - 1U;
-
- /*
- * set the width of the input to the correct width
- */
-
- LocalInput = LocalInput & WidthMask;
-
- ReturnVal = LocalInput >> 1U;
-
- Lsb = LocalInput & 0x00000001U;
-
- if (Lsb != 0x00000000U) {
- ReturnVal = ReturnVal | MsbMask;
- }
-
- ReturnVal = ReturnVal & WidthMask;
-
- return ReturnVal;
-
-}
-#endif /* ROTATE_RIGHT */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/38/33767b545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/38/33767b545243001d18b399c1eb9b3628
deleted file mode 100644
index 6bb6c18..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/38/33767b545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,37 +0,0 @@
-DRIVER_LIB_VERSION = 1.0
-COMPILER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I$(INCLUDEDIR)
-
-SRCFILES:=$(wildcard *.c)
-
-OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
-
-libs: $(OBJECTS)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf $(DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/38/5086a3565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/38/5086a3565243001d18b399c1eb9b3628
deleted file mode 100644
index fb87133..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/38/5086a3565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,70 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2008 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-*
-* microblaze_invalidate_icache()
-*
-* Invalidate the entire ICache
-*
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-#include "microblaze_instructions.h"
-
-#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020
-#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
-
-#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
-#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
-#endif
-
-#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
-#define MB_VERSION_LT_v720
-#endif
-
- .text
- .globl microblaze_invalidate_icache
- .ent microblaze_invalidate_icache
- .align 2
-
-microblaze_invalidate_icache:
-#if (XPAR_MICROBLAZE_USE_ICACHE==1) && (XPAR_MICROBLAZE_ALLOW_ICACHE_WR==1)
-
-#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */
- mfs r9, rmsr
- andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
- mts rmsr, r10
-#endif
- ADDIK r5, r0, XPAR_MICROBLAZE_ICACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Align to cache line */
- ADDIK r6, r5, XPAR_MICROBLAZE_CACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN)) /* Compute end */
-L_start:
- wic r5, r0 /* Invalidate the Cache */
-
- CMPU r18, r5, r6 /* Are we at the end? */
- BLEI r18, L_done
-
-#if defined (__arch64__ )
- addlik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the address by 4 */
- breai L_start
-#else
- brid L_start /* Branch to the beginning of the loop */
- addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the address by 4 (delay slot) */
-#endif
-L_done:
- rtsd r15, 8 /* Return */
-
-#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
- mts rmsr, r9
-#else
- nop
-#endif
-
-#else
- rtsd r15, 8 /* Return */
- nop
-#endif
- .end microblaze_invalidate_icache
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/38/50eef7535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/38/50eef7535243001d18b399c1eb9b3628
deleted file mode 100644
index 39b5bda..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/38/50eef7535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,51 +0,0 @@
-########################################################################
-# This is file which used to generate QEMU(which emulates A9 core)
-# commandline(start_qemu.sh script) which used in Zynq HW-EMU.
-# This is a template file which is packaged in platform and it gets
-# processed by Vitis tool to generate meaningful file.
-#
-# This file contains flag and value pairs and they must be seperated
-# into two lines value followed by flag. Below are the common/mandated
-# flag and value pairs used for emulating Zynq. User can add more
-# commandline args to this file depends on requirements.
-#
-# For more details on the QEMU commandline, please refer to
-# the QEMU user guide UG1169.
-########################################################################
-#
-#
-# selects emulated machine
--M
-arm-generic-fdt-7series
-#
-#
-# redirect the serial port to specified char dev (i.e stdio, tcp port, file etc)
--serial
-/dev/null
--serial
-mon:stdio
-#
-#
-# Register writes to SLCR block, to set PLL and CLK_CTRL regs (required for linux)
--device
-loader,addr=0xf8000008,data=0xDF0D,data-len=4
--device
-loader,addr=0xf8000140,data=0x00500801,data-len=4
--device
-loader,addr=0xf800012c,data=0x1ed044d,data-len=4
--device
-loader,addr=0xf8000108,data=0x0001e008,data-len=4
--device
-loader,addr=0xF800025C,data=0x00000005,data-len=4
--device
-loader,addr=0xF8000240,data=0x00000000,data-len=4
-#
-#
-# Boot device selection
--boot
-mode=5
-#
-#
-# Guest software to load during boot up
--kernel
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/38/705b55555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/38/705b55555243001d18b399c1eb9b3628
deleted file mode 100644
index 35d8058..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/38/705b55555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,147 +0,0 @@
-/*******************************************************************************
-* Copyright (c) 2018 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-*******************************************************************************/
-
-
-#ifndef __XFPD_SLCR_H__
-#define __XFPD_SLCR_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *@cond nocomments
- */
-
-/**
- * XfpdSlcr Base Address
- */
-#define XFPD_SLCR_BASEADDR 0xFD610000UL
-
-/**
- * Register: XfpdSlcrWprot0
- */
-#define XFPD_SLCR_WPROT0 ( ( XFPD_SLCR_BASEADDR ) + 0x00000000UL )
-#define XFPD_SLCR_WPROT0_RSTVAL 0x00000001UL
-
-#define XFPD_SLCR_WPROT0_ACT_SHIFT 0UL
-#define XFPD_SLCR_WPROT0_ACT_WIDTH 1UL
-#define XFPD_SLCR_WPROT0_ACT_MASK 0x00000001UL
-#define XFPD_SLCR_WPROT0_ACT_DEFVAL 0x1UL
-
-/**
- * Register: XfpdSlcrCtrl
- */
-#define XFPD_SLCR_CTRL ( ( XFPD_SLCR_BASEADDR ) + 0x00000004UL )
-#define XFPD_SLCR_CTRL_RSTVAL 0x00000000UL
-
-#define XFPD_SLCR_CTRL_SLVERR_EN_SHIFT 0UL
-#define XFPD_SLCR_CTRL_SLVERR_EN_WIDTH 1UL
-#define XFPD_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL
-#define XFPD_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL
-
-/**
- * Register: XfpdSlcrIsr
- */
-#define XFPD_SLCR_ISR ( ( XFPD_SLCR_BASEADDR ) + 0x00000008UL )
-#define XFPD_SLCR_ISR_RSTVAL 0x00000000UL
-
-#define XFPD_SLCR_ISR_ADDR_DECODE_ERR_SHIFT 0UL
-#define XFPD_SLCR_ISR_ADDR_DECODE_ERR_WIDTH 1UL
-#define XFPD_SLCR_ISR_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XFPD_SLCR_ISR_ADDR_DECODE_ERR_DEFVAL 0x0UL
-
-/**
- * Register: XfpdSlcrImr
- */
-#define XFPD_SLCR_IMR ( ( XFPD_SLCR_BASEADDR ) + 0x0000000CUL )
-#define XFPD_SLCR_IMR_RSTVAL 0x00000001UL
-
-#define XFPD_SLCR_IMR_ADDR_DECODE_ERR_SHIFT 0UL
-#define XFPD_SLCR_IMR_ADDR_DECODE_ERR_WIDTH 1UL
-#define XFPD_SLCR_IMR_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XFPD_SLCR_IMR_ADDR_DECODE_ERR_DEFVAL 0x1UL
-
-/**
- * Register: XfpdSlcrIer
- */
-#define XFPD_SLCR_IER ( ( XFPD_SLCR_BASEADDR ) + 0x00000010UL )
-#define XFPD_SLCR_IER_RSTVAL 0x00000000UL
-
-#define XFPD_SLCR_IER_ADDR_DECODE_ERR_SHIFT 0UL
-#define XFPD_SLCR_IER_ADDR_DECODE_ERR_WIDTH 1UL
-#define XFPD_SLCR_IER_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XFPD_SLCR_IER_ADDR_DECODE_ERR_DEFVAL 0x0UL
-
-/**
- * Register: XfpdSlcrIdr
- */
-#define XFPD_SLCR_IDR ( ( XFPD_SLCR_BASEADDR ) + 0x00000014UL )
-#define XFPD_SLCR_IDR_RSTVAL 0x00000000UL
-
-#define XFPD_SLCR_IDR_ADDR_DECODE_ERR_SHIFT 0UL
-#define XFPD_SLCR_IDR_ADDR_DECODE_ERR_WIDTH 1UL
-#define XFPD_SLCR_IDR_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XFPD_SLCR_IDR_ADDR_DECODE_ERR_DEFVAL 0x0UL
-
-/**
- * Register: XfpdSlcrItr
- */
-#define XFPD_SLCR_ITR ( ( XFPD_SLCR_BASEADDR ) + 0x00000018UL )
-#define XFPD_SLCR_ITR_RSTVAL 0x00000000UL
-
-#define XFPD_SLCR_ITR_ADDR_DECODE_ERR_SHIFT 0UL
-#define XFPD_SLCR_ITR_ADDR_DECODE_ERR_WIDTH 1UL
-#define XFPD_SLCR_ITR_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XFPD_SLCR_ITR_ADDR_DECODE_ERR_DEFVAL 0x0UL
-
-/**
- * Register: XfpdSlcrWdtClkSel
- */
-#define XFPD_SLCR_WDT_CLK_SEL ( ( XFPD_SLCR_BASEADDR ) + 0x00000100UL )
-#define XFPD_SLCR_WDT_CLK_SEL_RSTVAL 0x00000000UL
-
-#define XFPD_SLCR_WDT_CLK_SEL_SHIFT 0UL
-#define XFPD_SLCR_WDT_CLK_SEL_WIDTH 1UL
-#define XFPD_SLCR_WDT_CLK_SEL_MASK 0x00000001UL
-#define XFPD_SLCR_WDT_CLK_SEL_DEFVAL 0x0UL
-
-/**
- * Register: XfpdSlcrApugicCtrl
- */
-#define XFPD_SLCR_APUGIC_CTRL ( ( XFPD_SLCR_BASEADDR ) + 0x0000010CUL )
-#define XFPD_SLCR_APUGIC_CTRL_RSTVAL 0x00040004UL
-
-#define XFPD_SLCR_APUGIC_CTRL_AWQOS_SHIFT 16UL
-#define XFPD_SLCR_APUGIC_CTRL_AWQOS_WIDTH 4UL
-#define XFPD_SLCR_APUGIC_CTRL_AWQOS_MASK 0x000f0000UL
-#define XFPD_SLCR_APUGIC_CTRL_AWQOS_DEFVAL 0x4UL
-
-#define XFPD_SLCR_APUGIC_CTRL_ARQOS_SHIFT 0UL
-#define XFPD_SLCR_APUGIC_CTRL_ARQOS_WIDTH 4UL
-#define XFPD_SLCR_APUGIC_CTRL_ARQOS_MASK 0x0000000fUL
-#define XFPD_SLCR_APUGIC_CTRL_ARQOS_DEFVAL 0x4UL
-
-/**
- * Register: XfpdSlcrAfiFs
- */
-#define XFPD_SLCR_AFI_FS ( ( XFPD_SLCR_BASEADDR ) + 0x00005000UL )
-#define XFPD_SLCR_AFI_FS_RSTVAL 0x00000200UL
-
-#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT 8UL
-#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_WIDTH 2UL
-#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_MASK 0x00000300UL
-#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL 0x2UL
-
-/**
- *@endcond
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XFPD_SLCR_H__ */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7b/60b568294146001d13a480ec55035cc1 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/38/e0ef26388449001d13a480ec55035cc1
similarity index 99%
rename from Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7b/60b568294146001d13a480ec55035cc1
rename to Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/38/e0ef26388449001d13a480ec55035cc1
index 6d17ed8..c1f1467 100644
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7b/60b568294146001d13a480ec55035cc1
+++ b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/38/e0ef26388449001d13a480ec55035cc1
@@ -207,6 +207,7 @@ void writeOffsets() {
void setFocusPoint(int idx, double x, double y, double z) {
for (int i=0; i
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00 pkp 05/29/14 First release
-* 6.02 pkp 01/22/17 Added support for EL1 non-secure
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-#include "xil_mmu.h"
-#include "bspconfig.h"
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-#define BLOCK_SIZE_2MB 0x200000U
-#define BLOCK_SIZE_1GB 0x40000000U
-#define ADDRESS_LIMIT_4GB 0x100000000UL
-
-/************************** Variable Definitions *****************************/
-
-extern INTPTR MMUTableL1;
-extern INTPTR MMUTableL2;
-
-/************************** Function Prototypes ******************************/
-/*****************************************************************************/
-/**
-* @brief It sets the memory attributes for a section, in the translation
-* table. If the address (defined by Addr) is less than 4GB, the
-* memory attribute(attrib) is set for a section of 2MB memory. If the
-* address (defined by Addr) is greater than 4GB, the memory attribute
-* (attrib) is set for a section of 1GB memory.
-*
-* @param Addr: 64-bit address for which attributes are to be set.
-* @param attrib: Attribute for the specified memory region. xil_mmu.h
-* contains commonly used memory attributes definitions which can be
-* utilized for this function.
-*
-* @return None.
-*
-* @note The MMU and D-cache need not be disabled before changing an
-* translation table attribute.
-*
-******************************************************************************/
-void Xil_SetTlbAttributes(UINTPTR Addr, u64 attrib)
-{
- INTPTR *ptr;
- INTPTR section;
- u64 block_size;
- /* if region is less than 4GB MMUTable level 2 need to be modified */
- if(Addr < ADDRESS_LIMIT_4GB){
- /* block size is 2MB for addressed < 4GB*/
- block_size = BLOCK_SIZE_2MB;
- section = Addr / block_size;
- ptr = &MMUTableL2 + section;
- }
- /* if region is greater than 4GB MMUTable level 1 need to be modified */
- else{
- /* block size is 1GB for addressed > 4GB */
- block_size = BLOCK_SIZE_1GB;
- section = Addr / block_size;
- ptr = &MMUTableL1 + section;
- }
- *ptr = (Addr & (~(block_size-1))) | attrib;
-
- Xil_DCacheFlush();
-
- if (EL3 == 1)
- mtcptlbi(ALLE3);
- else if (EL1_NONSECURE == 1)
- mtcptlbi(VMALLE1);
-
- dsb(); /* ensure completion of the BP and TLB invalidation */
- isb(); /* synchronize context on this processor */
-
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/39/305f6a545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/39/305f6a545243001d18b399c1eb9b3628
deleted file mode 100644
index 1e9e6fb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/39/305f6a545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,522 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xstatus.h
-*
-* @addtogroup common_status_codes Xilinx software status codes
-*
-* The xstatus.h file contains the Xilinx software status codes.These codes are
-* used throughout the Xilinx device drivers.
-*
-* @{
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XSTATUS_H /* prevent circular inclusions */
-#define XSTATUS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/*********************** Common statuses 0 - 500 *****************************/
-/**
-@name Common Status Codes for All Device Drivers
-@{
-*/
-#define XST_SUCCESS 0L
-#define XST_FAILURE 1L
-#define XST_DEVICE_NOT_FOUND 2L
-#define XST_DEVICE_BLOCK_NOT_FOUND 3L
-#define XST_INVALID_VERSION 4L
-#define XST_DEVICE_IS_STARTED 5L
-#define XST_DEVICE_IS_STOPPED 6L
-#define XST_FIFO_ERROR 7L /*!< An error occurred during an
- operation with a FIFO such as
- an underrun or overrun, this
- error requires the device to
- be reset */
-#define XST_RESET_ERROR 8L /*!< An error occurred which requires
- the device to be reset */
-#define XST_DMA_ERROR 9L /*!< A DMA error occurred, this error
- typically requires the device
- using the DMA to be reset */
-#define XST_NOT_POLLED 10L /*!< The device is not configured for
- polled mode operation */
-#define XST_FIFO_NO_ROOM 11L /*!< A FIFO did not have room to put
- the specified data into */
-#define XST_BUFFER_TOO_SMALL 12L /*!< The buffer is not large enough
- to hold the expected data */
-#define XST_NO_DATA 13L /*!< There was no data available */
-#define XST_REGISTER_ERROR 14L /*!< A register did not contain the
- expected value */
-#define XST_INVALID_PARAM 15L /*!< An invalid parameter was passed
- into the function */
-#define XST_NOT_SGDMA 16L /*!< The device is not configured for
- scatter-gather DMA operation */
-#define XST_LOOPBACK_ERROR 17L /*!< A loopback test failed */
-#define XST_NO_CALLBACK 18L /*!< A callback has not yet been
- registered */
-#define XST_NO_FEATURE 19L /*!< Device is not configured with
- the requested feature */
-#define XST_NOT_INTERRUPT 20L /*!< Device is not configured for
- interrupt mode operation */
-#define XST_DEVICE_BUSY 21L /*!< Device is busy */
-#define XST_ERROR_COUNT_MAX 22L /*!< The error counters of a device
- have maxed out */
-#define XST_IS_STARTED 23L /*!< Used when part of device is
- already started i.e.
- sub channel */
-#define XST_IS_STOPPED 24L /*!< Used when part of device is
- already stopped i.e.
- sub channel */
-#define XST_DATA_LOST 26L /*!< Driver defined error */
-#define XST_RECV_ERROR 27L /*!< Generic receive error */
-#define XST_SEND_ERROR 28L /*!< Generic transmit error */
-#define XST_NOT_ENABLED 29L /*!< A requested service is not
- available because it has not
- been enabled */
-#define XST_NO_ACCESS 30L /* Generic access error */
-#define XST_TIMEOUT 31L /*!< Event timeout occurred */
-
-/** @} */
-/***************** Utility Component statuses 401 - 500 *********************/
-/**
-@name Utility Component Status Codes 401 - 500
-@{
-*/
-#define XST_MEMTEST_FAILED 401L /*!< Memory test failed */
-
-/** @} */
-/***************** Common Components statuses 501 - 1000 *********************/
-/**
-@name Packet Fifo Status Codes 501 - 510
-@{
-*/
-/********************* Packet Fifo statuses 501 - 510 ************************/
-
-#define XST_PFIFO_LACK_OF_DATA 501L /*!< Not enough data in FIFO */
-#define XST_PFIFO_NO_ROOM 502L /*!< Not enough room in FIFO */
-#define XST_PFIFO_BAD_REG_VALUE 503L /*!< Self test, a register value
- was invalid after reset */
-#define XST_PFIFO_ERROR 504L /*!< Generic packet FIFO error */
-#define XST_PFIFO_DEADLOCK 505L /*!< Packet FIFO is reporting
- * empty and full simultaneously
- */
-/** @} */
-/**
-@name DMA Status Codes 511 - 530
-@{
-*/
-/************************** DMA statuses 511 - 530 ***************************/
-
-#define XST_DMA_TRANSFER_ERROR 511L /*!< Self test, DMA transfer
- failed */
-#define XST_DMA_RESET_REGISTER_ERROR 512L /*!< Self test, a register value
- was invalid after reset */
-#define XST_DMA_SG_LIST_EMPTY 513L /*!< Scatter gather list contains
- no buffer descriptors ready
- to be processed */
-#define XST_DMA_SG_IS_STARTED 514L /*!< Scatter gather not stopped */
-#define XST_DMA_SG_IS_STOPPED 515L /*!< Scatter gather not running */
-#define XST_DMA_SG_LIST_FULL 517L /*!< All the buffer descriptors of
- the scatter gather list are
- being used */
-#define XST_DMA_SG_BD_LOCKED 518L /*!< The scatter gather buffer
- descriptor which is to be
- copied over in the scatter
- list is locked */
-#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /*!< No buffer descriptors have been
- put into the scatter gather
- list to be committed */
-#define XST_DMA_SG_COUNT_EXCEEDED 521L /*!< The packet count threshold
- specified was larger than the
- total # of buffer descriptors
- in the scatter gather list */
-#define XST_DMA_SG_LIST_EXISTS 522L /*!< The scatter gather list has
- already been created */
-#define XST_DMA_SG_NO_LIST 523L /*!< No scatter gather list has
- been created */
-#define XST_DMA_SG_BD_NOT_COMMITTED 524L /*!< The buffer descriptor which was
- being started was not committed
- to the list */
-#define XST_DMA_SG_NO_DATA 525L /*!< The buffer descriptor to start
- has already been used by the
- hardware so it can't be reused
- */
-#define XST_DMA_SG_LIST_ERROR 526L /*!< General purpose list access
- error */
-#define XST_DMA_BD_ERROR 527L /*!< General buffer descriptor
- error */
-/** @} */
-/**
-@name IPIF Status Codes Codes 531 - 550
-@{
-*/
-/************************** IPIF statuses 531 - 550 ***************************/
-
-#define XST_IPIF_REG_WIDTH_ERROR 531L /*!< An invalid register width
- was passed into the function */
-#define XST_IPIF_RESET_REGISTER_ERROR 532L /*!< The value of a register at
- reset was not valid */
-#define XST_IPIF_DEVICE_STATUS_ERROR 533L /*!< A write to the device interrupt
- status register did not read
- back correctly */
-#define XST_IPIF_DEVICE_ACK_ERROR 534L /*!< The device interrupt status
- register did not reset when
- acked */
-#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /*!< The device interrupt enable
- register was not updated when
- other registers changed */
-#define XST_IPIF_IP_STATUS_ERROR 536L /*!< A write to the IP interrupt
- status register did not read
- back correctly */
-#define XST_IPIF_IP_ACK_ERROR 537L /*!< The IP interrupt status register
- did not reset when acked */
-#define XST_IPIF_IP_ENABLE_ERROR 538L /*!< IP interrupt enable register was
- not updated correctly when other
- registers changed */
-#define XST_IPIF_DEVICE_PENDING_ERROR 539L /*!< The device interrupt pending
- register did not indicate the
- expected value */
-#define XST_IPIF_DEVICE_ID_ERROR 540L /*!< The device interrupt ID register
- did not indicate the expected
- value */
-#define XST_IPIF_ERROR 541L /*!< Generic ipif error */
-/** @} */
-
-/****************** Device specific statuses 1001 - 4095 *********************/
-/**
-@name Ethernet Status Codes 1001 - 1050
-@{
-*/
-/********************* Ethernet statuses 1001 - 1050 *************************/
-
-#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /*!< Memory space is not big enough
- * to hold the minimum number of
- * buffers or descriptors */
-#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /*!< Memory allocation failed */
-#define XST_EMAC_MII_READ_ERROR 1003L /*!< MII read error */
-#define XST_EMAC_MII_BUSY 1004L /*!< An MII operation is in progress */
-#define XST_EMAC_OUT_OF_BUFFERS 1005L /*!< Driver is out of buffers */
-#define XST_EMAC_PARSE_ERROR 1006L /*!< Invalid driver init string */
-#define XST_EMAC_COLLISION_ERROR 1007L /*!< Excess deferral or late
- * collision on polled send */
-/** @} */
-/**
-@name UART Status Codes 1051 - 1075
-@{
-*/
-/*********************** UART statuses 1051 - 1075 ***************************/
-#define XST_UART
-
-#define XST_UART_INIT_ERROR 1051L
-#define XST_UART_START_ERROR 1052L
-#define XST_UART_CONFIG_ERROR 1053L
-#define XST_UART_TEST_FAIL 1054L
-#define XST_UART_BAUD_ERROR 1055L
-#define XST_UART_BAUD_RANGE 1056L
-
-/** @} */
-/**
-@name IIC Status Codes 1076 - 1100
-@{
-*/
-/************************ IIC statuses 1076 - 1100 ***************************/
-
-#define XST_IIC_SELFTEST_FAILED 1076 /*!< self test failed */
-#define XST_IIC_BUS_BUSY 1077 /*!< bus found busy */
-#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /*!< mastersend attempted with */
- /* general call address */
-#define XST_IIC_STAND_REG_RESET_ERROR 1079 /*!< A non parameterizable reg */
- /* value after reset not valid */
-#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /*!< Tx fifo included in design */
- /* value after reset not valid */
-#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /*!< Rx fifo included in design */
- /* value after reset not valid */
-#define XST_IIC_TBA_REG_RESET_ERROR 1082 /*!< 10 bit addr incl in design */
- /* value after reset not valid */
-#define XST_IIC_CR_READBACK_ERROR 1083 /*!< Read of the control register */
- /* didn't return value written */
-#define XST_IIC_DTR_READBACK_ERROR 1084 /*!< Read of the data Tx reg */
- /* didn't return value written */
-#define XST_IIC_DRR_READBACK_ERROR 1085 /*!< Read of the data Receive reg */
- /* didn't return value written */
-#define XST_IIC_ADR_READBACK_ERROR 1086 /*!< Read of the data Tx reg */
- /* didn't return value written */
-#define XST_IIC_TBA_READBACK_ERROR 1087 /*!< Read of the 10 bit addr reg */
- /* didn't return written value */
-#define XST_IIC_NOT_SLAVE 1088 /*!< The device isn't a slave */
-#define XST_IIC_ARB_LOST 1089 /*!< Arbitration lost for master */
-/** @} */
-/**
-@name ATMC Status Codes 1101 - 1125
-@{
-*/
-/*********************** ATMC statuses 1101 - 1125 ***************************/
-
-#define XST_ATMC_ERROR_COUNT_MAX 1101L /*!< the error counters in the ATM
- controller hit the max value
- which requires the statistics
- to be cleared */
-/** @} */
-/**
-@name Flash Status Codes 1126 - 1150
-@{
-*/
-/*********************** Flash statuses 1126 - 1150 **************************/
-
-#define XST_FLASH_BUSY 1126L /*!< Flash is erasing or programming
- */
-#define XST_FLASH_READY 1127L /*!< Flash is ready for commands */
-#define XST_FLASH_ERROR 1128L /*!< Flash had detected an internal
- error. Use XFlash_DeviceControl
- to retrieve device specific codes
- */
-#define XST_FLASH_ERASE_SUSPENDED 1129L /*!< Flash is in suspended erase state
- */
-#define XST_FLASH_WRITE_SUSPENDED 1130L /*!< Flash is in suspended write state
- */
-#define XST_FLASH_PART_NOT_SUPPORTED 1131L /*!< Flash type not supported by
- driver */
-#define XST_FLASH_NOT_SUPPORTED 1132L /*!< Operation not supported */
-#define XST_FLASH_TOO_MANY_REGIONS 1133L /*!< Too many erase regions */
-#define XST_FLASH_TIMEOUT_ERROR 1134L /*!< Programming or erase operation
- aborted due to a timeout */
-#define XST_FLASH_ADDRESS_ERROR 1135L /*!< Accessed flash outside its
- addressible range */
-#define XST_FLASH_ALIGNMENT_ERROR 1136L /*!< Write alignment error */
-#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /*!< Couldn't return immediately from
- write/erase function with
- XFL_NON_BLOCKING_WRITE/ERASE
- option cleared */
-#define XST_FLASH_CFI_QUERY_ERROR 1138L /*!< Failed to query the device */
-/** @} */
-/**
-@name SPI Status Codes 1151 - 1175
-@{
-*/
-/*********************** SPI statuses 1151 - 1175 ****************************/
-
-#define XST_SPI_MODE_FAULT 1151 /*!< master was selected as slave */
-#define XST_SPI_TRANSFER_DONE 1152 /*!< data transfer is complete */
-#define XST_SPI_TRANSMIT_UNDERRUN 1153 /*!< slave underruns transmit register */
-#define XST_SPI_RECEIVE_OVERRUN 1154 /*!< device overruns receive register */
-#define XST_SPI_NO_SLAVE 1155 /*!< no slave has been selected yet */
-#define XST_SPI_TOO_MANY_SLAVES 1156 /*!< more than one slave is being
- * selected */
-#define XST_SPI_NOT_MASTER 1157 /*!< operation is valid only as master */
-#define XST_SPI_SLAVE_ONLY 1158 /*!< device is configured as slave-only
- */
-#define XST_SPI_SLAVE_MODE_FAULT 1159 /*!< slave was selected while disabled */
-#define XST_SPI_SLAVE_MODE 1160 /*!< device has been addressed as slave */
-#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /*!< device received data in slave mode */
-
-#define XST_SPI_COMMAND_ERROR 1162 /*!< unrecognised command - qspi only */
-#define XST_SPI_POLL_DONE 1163 /*!< controller completed polling the
- device for status */
-/** @} */
-/**
-@name OPB Arbiter Status Codes 1176 - 1200
-@{
-*/
-/********************** OPB Arbiter statuses 1176 - 1200 *********************/
-
-#define XST_OPBARB_INVALID_PRIORITY 1176 /*!< the priority registers have either
- * one master assigned to two or more
- * priorities, or one master not
- * assigned to any priority
- */
-#define XST_OPBARB_NOT_SUSPENDED 1177 /*!< an attempt was made to modify the
- * priority levels without first
- * suspending the use of priority
- * levels
- */
-#define XST_OPBARB_PARK_NOT_ENABLED 1178 /*!< bus parking by id was enabled but
- * bus parking was not enabled
- */
-#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /*!< the arbiter must be in fixed
- * priority mode to allow the
- * priorities to be changed
- */
-/** @} */
-/**
-@name INTC Status Codes 1201 - 1225
-@{
-*/
-/************************ Intc statuses 1201 - 1225 **************************/
-
-#define XST_INTC_FAIL_SELFTEST 1201 /*!< self test failed */
-#define XST_INTC_CONNECT_ERROR 1202 /*!< interrupt already in use */
-/** @} */
-/**
-@name TmrCtr Status Codes 1226 - 1250
-@{
-*/
-/********************** TmrCtr statuses 1226 - 1250 **************************/
-
-#define XST_TMRCTR_TIMER_FAILED 1226 /*!< self test failed */
-/** @} */
-/**
-@name WdtTb Status Codes 1251 - 1275
-@{
-*/
-/********************** WdtTb statuses 1251 - 1275 ***************************/
-
-#define XST_WDTTB_TIMER_FAILED 1251L
-/** @} */
-/**
-@name PlbArb status Codes 1276 - 1300
-@{
-*/
-/********************** PlbArb statuses 1276 - 1300 **************************/
-
-#define XST_PLBARB_FAIL_SELFTEST 1276L
-/** @} */
-/**
-@name Plb2Opb Status Codes 1301 - 1325
-@{
-*/
-/********************** Plb2Opb statuses 1301 - 1325 *************************/
-
-#define XST_PLB2OPB_FAIL_SELFTEST 1301L
-/** @} */
-/**
-@name Opb2Plb Status 1326 - 1350
-@{
-*/
-/********************** Opb2Plb statuses 1326 - 1350 *************************/
-
-#define XST_OPB2PLB_FAIL_SELFTEST 1326L
-/** @} */
-/**
-@name SysAce Status Codes 1351 - 1360
-@{
-*/
-/********************** SysAce statuses 1351 - 1360 **************************/
-
-#define XST_SYSACE_NO_LOCK 1351L /*!< No MPU lock has been granted */
-/** @} */
-/**
-@name PCI Bridge Status Codes 1361 - 1375
-@{
-*/
-/********************** PCI Bridge statuses 1361 - 1375 **********************/
-
-#define XST_PCI_INVALID_ADDRESS 1361L
-/** @} */
-/**
-@name FlexRay Constants 1400 - 1409
-@{
-*/
-/********************** FlexRay constants 1400 - 1409 *************************/
-
-#define XST_FR_TX_ERROR 1400
-#define XST_FR_TX_BUSY 1401
-#define XST_FR_BUF_LOCKED 1402
-#define XST_FR_NO_BUF 1403
-/** @} */
-/**
-@name USB constants 1410 - 1420
-@{
-*/
-/****************** USB constants 1410 - 1420 *******************************/
-
-#define XST_USB_ALREADY_CONFIGURED 1410
-#define XST_USB_BUF_ALIGN_ERROR 1411
-#define XST_USB_NO_DESC_AVAILABLE 1412
-#define XST_USB_BUF_TOO_BIG 1413
-#define XST_USB_NO_BUF 1414
-/** @} */
-/**
-@name HWICAP constants 1421 - 1429
-@{
-*/
-/****************** HWICAP constants 1421 - 1429 *****************************/
-
-#define XST_HWICAP_WRITE_DONE 1421
-
-/** @} */
-/**
-@name AXI VDMA constants 1430 - 1440
-@{
-*/
-/****************** AXI VDMA constants 1430 - 1440 *****************************/
-
-#define XST_VDMA_MISMATCH_ERROR 1430
-/** @} */
-/**
-@name NAND Flash Status Codes 1441 - 1459
-@{
-*/
-/*********************** NAND Flash statuses 1441 - 1459 *********************/
-
-#define XST_NAND_BUSY 1441L /*!< Flash is erasing or
- * programming
- */
-#define XST_NAND_READY 1442L /*!< Flash is ready for commands
- */
-#define XST_NAND_ERROR 1443L /*!< Flash had detected an
- * internal error.
- */
-#define XST_NAND_PART_NOT_SUPPORTED 1444L /*!< Flash type not supported by
- * driver
- */
-#define XST_NAND_OPT_NOT_SUPPORTED 1445L /*!< Operation not supported
- */
-#define XST_NAND_TIMEOUT_ERROR 1446L /*!< Programming or erase
- * operation aborted due to a
- * timeout
- */
-#define XST_NAND_ADDRESS_ERROR 1447L /*!< Accessed flash outside its
- * addressible range
- */
-#define XST_NAND_ALIGNMENT_ERROR 1448L /*!< Write alignment error
- */
-#define XST_NAND_PARAM_PAGE_ERROR 1449L /*!< Failed to read parameter
- * page of the device
- */
-#define XST_NAND_CACHE_ERROR 1450L /*!< Flash page buffer error
- */
-
-#define XST_NAND_WRITE_PROTECTED 1451L /*!< Flash is write protected
- */
-/** @} */
-
-/**************************** Type Definitions *******************************/
-
-typedef s32 XStatus;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
-
-/**
-* @} End of "addtogroup common_status_codes".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/39/6039ec545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/39/6039ec545243001d18b399c1eb9b3628
deleted file mode 100644
index 4b5c4cd..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/39/6039ec545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,105 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xscuwdt_selftest.c
-* @addtogroup scuwdt_v2_4
-* @{
-*
-* Contains diagnostic self-test functions for the XScuWdt driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xscuwdt.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/****************************************************************************/
-/**
-*
-* Run a self-test on the WDT. This test stops the watchdog, writes a value to
-* the watchdog load register, starts the watchdog and verifies that the value
-* read from the counter register is less that the value written to the load
-* register. It then restores the control register and the watchdog load
-* register.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return
-* - XST_SUCCESS if self-test was successful.
-* - XST_FAILURE if the WDT is not decrementing.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XScuWdt_SelfTest(XScuWdt *InstancePtr)
-{
- s32 SelfTestStatus;
- u32 Register;
- u32 CtrlOrig;
- u32 LoadOrig;
-
- /*
- * Assert to ensure the inputs are valid and the instance has been
- * initialized.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Stop the watchdog timer.
- */
- CtrlOrig = XScuWdt_GetControlReg(InstancePtr);
- XScuWdt_SetControlReg(InstancePtr,
- CtrlOrig & (~(u32)XSCUWDT_CONTROL_WD_ENABLE_MASK));
-
- LoadOrig = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,
- XSCUWDT_LOAD_OFFSET);
- XScuWdt_LoadWdt(InstancePtr, 0xFFFFFFFFU);
-
- /*
- * Start the watchdog timer and check if the watchdog counter is
- * decrementing.
- */
- XScuWdt_SetControlReg(InstancePtr,
- CtrlOrig | (u32)XSCUWDT_CONTROL_WD_ENABLE_MASK);
-
- Register = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,
- XSCUWDT_COUNTER_OFFSET);
-
- XScuWdt_LoadWdt(InstancePtr, LoadOrig);
- XScuWdt_SetControlReg(InstancePtr, CtrlOrig);
-
- if (Register == 0xFFFFFFFFU) {
- SelfTestStatus = (s32)XST_FAILURE;
- }
- else {
- SelfTestStatus = (s32)XST_SUCCESS;
- }
-
- return SelfTestStatus;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/39/6074f1555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/39/6074f1555243001d18b399c1eb9b3628
deleted file mode 100644
index efa60da..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/39/6074f1555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,66 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************
-*
-* @file sleep.c
-*
-* This function provides a second delay using the Global Timer register in
-* the ARM Cortex A9 MP core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm 11/11/09 First release
-* 3.07a sgd 07/05/12 Updated sleep function to make use Global
-* 6.0 asa 08/15/16 Updated the sleep signature. Fix for CR#956899.
-* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
-* implementation. Now sleep routines will use Timer
-* specified by the user (i.e. Global timer/TTC timer)
-*
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "sleep.h"
-#include "xtime_l.h"
-#include "xparameters.h"
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#include "xil_sleeptimer.h"
-#endif
-
-/*****************************************************************************/
-/*
-*
-* This API is used to provide delays in seconds
-*
-* @param seconds requested
-*
-* @return 0 always
-*
-* @note None.
-*
-****************************************************************************/
-unsigned sleep_A9(unsigned int seconds)
-{
-#if defined (SLEEP_TIMER_BASEADDR)
- Xil_SleepTTCCommon(seconds, COUNTS_PER_SECOND);
-#else
- XTime tEnd, tCur;
-
- XTime_GetTime(&tCur);
- tEnd = tCur + (((XTime) seconds) * COUNTS_PER_SECOND);
- do
- {
- XTime_GetTime(&tCur);
- } while (tCur < tEnd);
-#endif
-
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/39/f0e1c6555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/39/f0e1c6555243001d18b399c1eb9b3628
deleted file mode 100644
index e40988e..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/39/f0e1c6555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,366 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_spinlock.c
-*
-* Implements a spinlocking mechanism using ARM load-exclusive and
-* store-exclusive instructions.
-*
-* spinlocks in baremetal world are useful mainly for AMP kind of use cases
-* where different applications run in different CPUs in a CPU cluster and
-* they have a common resource to work with.
-* A simple yet common example is:
-* R5-0 and R5-1 have separate applications and at runtime they try to access a
-* shared register space (GIC) or shared memory space. Mutual exclusion is
-* really needed for such use cases.
-* Similar use case applies for Zynq CortexA9-0 and CortesA9-1.
-*
-* The spinlock mechanism provided with this file is very simple to cater to
-* baremetal world requirements.
-*
-* A) Unlike OS type of use cases, at any point of time, only a single lock
-* can be used. There is no way in BM world we can support multiple locks
-* at the same time.
-* B) The spinlocking is available for ARM v7 (Cortex-R5 and Cortex-A9).
-* C) Users need to provide a lock (essentially a shared address), and a flag
-* (also a shared address) for spinlocking to work. These shared addresses
-* must be agreed upon by apps running on both CPUs. Needless to say,
-* the linker scripts must change accordingly so that apps running on both
-* CPUs can have a shared DDR region from which address can be used for
-* spinlocking.
-* D) The address that is used for spinlocking and the address that is used
-* as flag address must be in a memory region that is strongly-ordered
-* or device memory.
-* E) Like any similar standard use cases, one application running in any
-* of the CPUs must create the spinlock address. It is advisable that the
-* the same application must destroy or release the spinlock address,
-* though nothing stops the other CPU in destroying and releasing the
-* spinlock addresses. There has to be understanding between applications
-* running on both the CPUs to ensure that correct ordering is followed.
-* Once a spinlock is released, it spinlock APIs cannot be used anymore.
-* F) Once a spinlock address is created it can be used any number of times
-* to protect critical sections as long as a certain set of rules are
-* followed and a certain set of sequences are followed. More about the
-* sequences later in this description.
-* G) To re-iterate, the spinlocking mechanism provided through this file is
-* pretty rudimentary. Users can always improvise. The use case that
-* the whole mechanism is trying to solve is: common register space
-* being accesses in an AMP scenario by independent applications running
-* at multiple CPUs.
-*
-* The usage of APIs provided in this file are summarized below.
-* A) Applications running at both the CPUs ensure that they allocate shared
-* memory space to be used for locking and flag maintenance.
-* B) The memory allocated as shared should be of minimum size 1 MB. This
-* limitation is because the way translation tables/memory map is setup
-* for R5 or A9. In future, this limitation can be brought down 4 KB.
-* C) The spinlock and the flag address must be uncached. Users need to c
-* all Xilinx provided API Xil_SetTlbAttributes to mark the shared
-* 1 MB memory space as strongly ordered or device memory.
-* D) Both the applications must call the API Xil_InitializeSpinLock with
-* the spinlock address, flag address and flag value to be used. Currently
-* only one flag value is supported (i.e. XIL_SPINLOCK_ENABLE with
-* a value of 1).
-* Only if the Xil_InitializeSpinLock returns success, should they
-* proceed to use Xil_SpinLock and Xil_SpinUnlock.
-* F) Afterwards applications can start using the APIs Xil_SpinLock() and
-* Xil_SpinUnlock() to protect the critical sections.
-* G) It is highly suggested to use Xil_IsSpinLockEnabled() as a check
-* before using Xil_SpinLock() or Xil_SpinUnlock(). Refer to the code
-* snippet below.
-* H) If spinlock is no more needed by an application, they can use the API
-* Xil_ReleaseSpinLock().
-* I) Once a spinlock is created it can be used as many numbers of time as
-* needed.
-*
-* A typical code snippet with R5 as an example and lock address falling
-* in the 1 MB memory region (0x300000 to 0x400000) is given below.
-*
-* Code snippet for R5-0 (that runs first):
-* int main()
-* {
-* u32 *sharedlockaddr = (int *)0x300008;
-* u32 *sharedlockflagaddr = int *)0x30000C;
-* Xil_SetTlbAttributes(0x300000,STRONG_ORDERD_SHARED | PRIV_RW_USER_RW);
-* Xil_InitializeSpinLock((UINTPTR)sharedlockaddr,(UINTPTR)sharedlockflagaddr,
-* XIL_SPINLOCK_ENABLE);
-* ....
-* ....
-* if (Xil_IsSpinLockEnabled())
-* Xil_SpinLock();
-* // Critical Section
-* ....
-* ....
-* if (Xil_IsSpinLockEnabled())
-* Xil_SpinUnlock();
-* .....
-* .....
-* Xil_ReleaseSpinLock();
-* } // End of main
-*
-* * Code snippet for R5-1 (that runs second):
-* int main()
-* {
-* u32 *sharedlockaddr = (int *)0x300008;
-* u32 *sharedlockflagaddr = int *)0x30000C;
-* Xil_SetTlbAttributes(0x300000,STRONG_ORDERD_SHARED | PRIV_RW_USER_RW);
-* Xil_InitializeSpinLock((UINTPTR)sharedlockaddr,(UINTPTR)sharedlockflagaddr,
-* XIL_SPINLOCK_ENABLE);
-* ....
-* if (Xil_IsSpinLockEnabled())
-* Xil_SpinLock();
-* // Critical Section
-* ....
-* ....
-* if (Xil_IsSpinLockEnabled())
-* Xil_SpinUnlock();
-* .....
-* .....
-* Xil_ReleaseSpinLock();
-* } // End of main
-*
-* Xil_SpinLock() and Xil_SpinLock() return XST_FAILURE if the spinlock
-* is initialized. Instead of calling Xil_IsSpinLockEnabled before using
-* Xil_SpinLock() or Xil_SpinLock(), users can also check the return
-* value of Xil_SpinLock and Xil_SpinLock. If a lock is not initialized,
-* Xil_SpinLock will just return failure and not perform load-exclusive
-* operations.
-*
-* Guidelines on when to use the spinlocking mechanism in Xilinx baremetal
-* environment:
-* A) Spinlocking mechanism can only be used for Cortex-R5s (split mode)
-* and Cortex-A9s (Zynq).
-* B) In Cortex-R5 split mode or Cortex-A9 cluster, applications running on
-* both the CPUs, by design should never be sharing the same peripheral.
-* It is impossible to support such use cases reliably.
-* Hence none of the peripheral drivers (except GIC driver) have
-* spinlocking support added into their APIs.
-* C) GIC register space is shared by both the CPUs (R5 split mode, A9s).
-* The GIC driver APIs have spinlocking mechanism added to the relevant
-* APIs. Users need to follow the guidelines stated earlier to enable
-* the spinlocks and use them.
-* It is really advisable to use spinlock mechanism for use cases where
-* applications running on multiple CPUs can simultaneously access
-* GIC register space through driver APIs.
-* D) The spinlock mechanism can be used to protect any critical region
-* implemented through shared memory space.
-*
-* IMPORTANT NOTE: Circular spinlocks are not allowed (as expected).
-* Use case where an application calls Xil_SpinLock back to back without
-* calling Xil_SpinUnlock in between will/may result in a deadlock
-* condition.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 7.5 asa 02/23/21 First release
-* 7.5 asa 04/28/21 Fixed bug Xil_IsSpinLockEnabled to avoid
-* dereferencing to address zero.
-*
-*
-******************************************************************************/
-
-
-/***************************** Include Files ********************************/
-#if !defined (__aarch64__) && defined(__GNUC__) && !defined(__clang__)
-#include "xil_spinlock.h"
-
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-
-/************************** Variable Definitions ****************************/
-static UINTPTR Xil_Spinlock_Addr = 0x0;
-static UINTPTR Xil_Spinlock_Flag_Addr = 0x0;
-
-/************************** Function Prototypes *****************************/
-
-/****************************************************************************/
-/**
-*
-* @brief Used at the beginning of a critical section. This API takes the
-* lock using load-exclusive and store-exclusive operations. In
-* case the lock is not available (being held by an application
-* running at the other CPU and doing operations inside the
-* critical section, the control will never go out from the API
-* till the other CPU releases the lock.
-*
-* @param None.
-*
-* @return XST_FAILURE: If spinlock is not properly initialized.
-* XST_SUCCESS: If the lock was successfully obtained.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 Xil_SpinLock(void)
-{
- UINTPTR lockaddr = Xil_Spinlock_Addr;
- u32 LockTempVar;
-
- if (Xil_Spinlock_Addr == 0) {
- return XST_FAILURE;
- }
-
- __asm__ __volatile__(
- "1: ldrex %0, [%1] \n"
- " teq %0, %3 \n"
- " strexeq %0, %2, [%1] \n"
- " teqeq %0, #0 \n"
- " bne 1b \n"
- " dmb \n"
- : "=&r" (LockTempVar)
- : "r" (lockaddr), "r"(XIL_SPINLOCK_LOCKVAL), "r"(XIL_SPINLOCK_RESETVAL)
- : "cc");
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* @brief Used to release a lock previously held by calling Xil_SpinLock.
-*
-* @param None.
-*
-* @return XST_FAILURE: If spinlock is not properly initialized.
-* XST_SUCCESS: If the lock was successfully obtained.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 Xil_SpinUnlock(void)
-{
- UINTPTR lockaddr = Xil_Spinlock_Addr;
-
- if (Xil_Spinlock_Addr == 0) {
- return XST_FAILURE;
- }
- __asm__ __volatile__(
- "dmb \n"
- "str %1, [%0] \n"
- :
- : "r" (lockaddr), "r" (XIL_SPINLOCK_RESETVAL)
- : "cc");
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-* @brief Used to initialize a spinlock.
-*
-* @param lockaddr: Address of the lock variable. The address must be in
-* a shared memory region.
-* lockflagaddr: Address of the flag variable. The address must be
-* in a shared memory region.
-* lockflag: The value of the flag. Currently only one value
-* is supported, which is XIL_SPINLOCK_ENABLE.
-*
-* @return XST_SUCCESS, if the initialization succeeded.
-* XST_FAILURE, if the initialization failed
-*
-* @note None.
-*
-*****************************************************************************/
-u32 Xil_InitializeSpinLock(UINTPTR lockaddr, UINTPTR lockflagaddr,
- u32 lockflag)
-{
- if (Xil_Spinlock_Flag_Addr == 0) {
- Xil_Spinlock_Flag_Addr = lockflagaddr;
- if (*(u32 *)Xil_Spinlock_Flag_Addr == XIL_SPINLOCK_ENABLED) {
- /*
- * spinlock is already initialized by one of the CPUs, just update
- * the local variable Xil_Spinlock_Addr with the passed address
- * and dont write to the lock value as it might be currently
- * getting used.
- */
- /*
- * Ensure to update the global variable Xil_Spinlock_Addr only
- * if it is zero. A non-zero value may mean that there is something
- * wrong.
- */
- if (Xil_Spinlock_Addr == 0) {
- Xil_Spinlock_Addr = lockaddr;
- } else {
- /*
- * May be spinlock is already initialized and the user has not
- * called Xil_ReleaseSpinLock before calling Xil_InitializeSpinLock.
- */
- return XST_FAILURE;
- }
- } else {
- /* All good, do the necessary initializations */
- Xil_Spinlock_Addr = lockaddr;
- *(u32 *)(Xil_Spinlock_Addr) = XIL_SPINLOCK_RESETVAL;
- *(u32 *)(Xil_Spinlock_Flag_Addr) = lockflag;
- }
- return XST_SUCCESS;
- } else {
- /*
- * Most probably spinlock is already initialized and the user has not
- * called Xil_ReleaseSpinLock before calling Xil_InitializeSpinLock.
- */
- return XST_FAILURE;
- }
-}
-
-
-/****************************************************************************/
-/**
-* @brief Used to release the spinlock. Typically called by the application
-* once spinlock feature is no more required.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void Xil_ReleaseSpinLock(void)
-{
- Xil_Spinlock_Addr = 0;
- Xil_Spinlock_Flag_Addr = 0;
-}
-
-/****************************************************************************/
-/**
-* @brief Used to know if the spinlock feature has been enabled. To ensure
-* that spinlock feature does not break use cases where lock is
-* not initialized, the application must call this API first to know
-* if it can use spinlock. If this API returns non-zero value, an
-* application should then use Xil_SpinLock or Xil_SpinUnlock.
-*
-* @param None
-*
-* @return Non-zero, if spinlock is already initialized and can be used.
-* Zero, if spinlock is not initialized.
-*
-* @note
-*
-*****************************************************************************/
-u32 Xil_IsSpinLockEnabled(void)
-{
- u32 retVal = FALSE;
-
- if (Xil_Spinlock_Flag_Addr != 0) {
- if (*(u32 *)(Xil_Spinlock_Flag_Addr) == XIL_SPINLOCK_ENABLED) {
- retVal = TRUE;
- }
- }
- return retVal;
-}
-#endif /* !(__aarch64__) && (__GNUC__) && !(__clang__)*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3a/013a2d555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3a/013a2d555243001d18b399c1eb9b3628
deleted file mode 100644
index 481481d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3a/013a2d555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,344 +0,0 @@
-;/******************************************************************************
-;* Copyright (c) 2018 - 2020 Xilinx, Inc. All rights reserved.
-;* SPDX-License-Identifier: MIT
-;******************************************************************************/
-;/*****************************************************************************/
-;/**
-;* @file translation_table.s
-;*
-;* @addtogroup a53_64_boot_code
-;* @{
-;*
translation_table.S
-;* translation_table.S contains a static page table required by MMU for
-;* cortex-A53. This translation table is flat mapped (input address = output
-;* address) with default memory attributes defined for zynq ultrascale+
-;* architecture. It utilizes translation granule size of 4KB with 2MB section
-;* size for initial 4GB memory and 1GB section size for memory after 4GB.
-;* The overview of translation table memory attributes is described below.
-;*
-;*| | Memory Range | Definition in Translation Table |
-;*|-----------------------|-----------------------------|-----------------------------------|
-;*| DDR | 0x0000000000 - 0x007FFFFFFF | Normal write-back Cacheable |
-;*| PL | 0x0080000000 - 0x00BFFFFFFF | Strongly Ordered |
-;*| QSPI, lower PCIe | 0x00C0000000 - 0x00EFFFFFFF | Strongly Ordered |
-;*| Reserved | 0x00F0000000 - 0x00F7FFFFFF | Unassigned |
-;*| STM Coresight | 0x00F8000000 - 0x00F8FFFFFF | Strongly Ordered |
-;*| GIC | 0x00F9000000 - 0x00F91FFFFF | Strongly Ordered |
-;*| Reserved | 0x00F9200000 - 0x00FCFFFFFF | Unassigned |
-;*| FPS, LPS slaves | 0x00FD000000 - 0x00FFBFFFFF | Strongly Ordered |
-;*| CSU, PMU | 0x00FFC00000 - 0x00FFDFFFFF | Strongly Ordered |
-;*| TCM, OCM | 0x00FFE00000 - 0x00FFFFFFFF | Normal inner write-back cacheable |
-;*| Reserved | 0x0100000000 - 0x03FFFFFFFF | Unassigned |
-;*| PL, PCIe | 0x0400000000 - 0x07FFFFFFFF | Strongly Ordered |
-;*| DDR | 0x0800000000 - 0x0FFFFFFFFF | Normal inner write-back cacheable |
-;*| PL, PCIe | 0x1000000000 - 0xBFFFFFFFFF | Strongly Ordered |
-;*| Reserved | 0xC000000000 - 0xFFFFFFFFFF | Unassigned |
-;*
-;* @note
-;*
-;* For DDR region 0x0000000000 - 0x007FFFFFFF, a system where DDR is less than
-;* 2GB, region after DDR and before PL is marked as undefined/reserved in
-;* translation table. Region 0xF9100000 - 0xF91FFFFF is reserved memory in
-;* 0x00F9000000 - 0x00F91FFFFF range, but it is marked as strongly ordered
-;* because minimum section size in translation table section is 2MB. Region
-;* 0x00FFC00000 - 0x00FFDFFFFF contains CSU and PMU memory which are marked as
-;* Device since it is less than 1MB and falls in a region with device memory.
-;*
-;*
-;* MODIFICATION HISTORY:
-;*
-;* Ver Who Date Changes
-;* ----- ---- -------- ---------------------------------------------------
-;* 7.0 cjp 02/26/19 First release
-;*
-;******************************************************************************/
-
-#include "xparameters.h"
-#include "bspconfig.h"
-
- EXPORT MMUTableL0
- EXPORT MMUTableL1
- EXPORT MMUTableL2
-
- GBLA abscnt
- GBLA count
- GBLA sect
-
-; Fault
-Reserved EQU 0
-#if (EL1_NONSECURE == 1)
-Memory EQU 0x405:OR:(2:SHL:8):OR:0x0 ; Normal writeback write allocate outer shared read write
-#else
-Memory EQU 0x405:OR:(3:SHL:8):OR:0x0 ; Normal writeback write allocate inner shared read write
-#endif
-Device EQU 0x409:OR:(1:SHL:53):OR:(1:SHL:54):OR:0x0 ; Strongly ordered read write non executable
-
- AREA |.mmu_tbl0|, CODE, ALIGN=12
-
-MMUTableL0
-
- DCQU MMUTableL1+0x3 ; 0x0000_0000 - 0x7F_FFFF_FFFF
- DCQU MMUTableL1+0x1000+0x3 ; 0x80_0000_0000 - 0xFF_FFFF_FFFF
-
- AREA |.mmu_tbl1|, CODE, ALIGN=12
-
-MMUTableL1
-
-;
-; 0x4000_0000 - 0xFFFF_FFFF
-; 1GB DDR, 1GB PL, 2GB other devices n memory
-;
-count SETA 0
- WHILE count<0x4
- DCQU MMUTableL2+count*0x1000+0x3
-count SETA count+1
- WEND
-
-Fixlocl1 EQU 0x100000000
-abscnt SETA 0
-
-;
-; 0x0001_0000_0000 - 0x0003_FFFF_FFFF
-; 12GB Reserved
-;
-count SETA 0
- WHILE count<0xc
- DCQU Fixlocl1+abscnt*0x40000000+Reserved
-count SETA count+1
-abscnt SETA abscnt+1
- WEND
-
-;
-; 0x0004_0000_0000 - 0x0007_FFFF_FFFF
-; 8GB PL, 8GB PCIe
-;
-count SETA 0
- WHILE count<0x10
- DCQU Fixlocl1+abscnt*0x40000000+Device
-count SETA count+1
-abscnt SETA abscnt+1
- WEND
-
-#ifdef XPAR_PSU_DDR_1_S_AXI_BASEADDR
-DDR_1_START EQU XPAR_PSU_DDR_1_S_AXI_BASEADDR
-DDR_1_END EQU XPAR_PSU_DDR_1_S_AXI_HIGHADDR
-DDR_1_SIZE EQU (DDR_1_END - DDR_1_START + 1)
-#if (DDR_1_SIZE > 0x800000000)
-DDR_1_REG EQU 0x20 ; If DDR size is larger than 32GB, truncate to 32GB
-#else
-DDR_1_REG EQU DDR_1_SIZE / 0x40000000
-#endif
-#else
-DDR_1_REG EQU 0
-#endif
-
-UNDEF_1_REG EQU (0x20 - DDR_1_REG)
-
-; DDR based on size in hdf
-count SETA 0
- WHILE count 0x80000000)
-DDR_0_REG EQU 0x400 ; If DDR size is larger than 2GB, truncate to 2GB
-#else
-DDR_0_REG EQU DDR_0_SIZE / 0x200000
-#endif
-#else
-DDR_0_REG EQU 0
-#endif
-
-UNDEF_0_REG EQU (0x400 - DDR_0_REG)
-
-; DDR based on size in hdf
-count SETA 0
- WHILE count
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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-
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-
-
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3a/90a7e4595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3a/90a7e4595243001d18b399c1eb9b3628
deleted file mode 100644
index f0e1906..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3a/90a7e4595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,58 +0,0 @@
-###############################################################################
-# Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved.
-# SPDX-License-Identifier: MIT
-###############################################################################
-DRIVER_LIB_VERSION = v1.0
-
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS =
-LIB=libxilffs.a
-
-ifeq ($(notdir $(COMPILER)) , iccarm)
- EXTRA_ARCHIVE_FLAGS=--create
-else
-ifeq ($(notdir $(COMPILER)) , armcc)
- EXTRA_ARCHIVE_FLAGS=--create
-else
-ifeq ($(notdir $(COMPILER)) , armclang)
- EXTRA_ARCHIVE_FLAGS=-rc
-else
- EXTRA_ARCHIVE_FLAGS=rc
-endif
-endif
-endif
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-FATFS_DIR = ./
-FATFS_SRCS := $(wildcard *.c)
-FATFS_OBJS = $(addprefix $(FATFS_DIR), $(FATFS_SRCS:%.c=%.o))
-libs: libxilffs.a
-
-libxilffs.a: $(FATFS_OBJS)
- $(ARCHIVER) $(EXTRA_ARCHIVE_FLAGS) ${RELEASEDIR}/${LIB} ${FATFS_OBJS}
-DEPFILES := $(FATFS_SRCS:%.c=$(FATFS_DIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(FATFS_DIR)%.o: $(FATFS_DIR)%.c
- $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $<
-
-.PHONY: include
-include: libxilffs_includes
-
-libxilffs_includes: $(addprefix $(INCLUDEDIR), $(subst include/,,$(wildcard include/*.h)))
-
-$(INCLUDEDIR)%.h: include/%.h
- $(CP) $< $@
-
-clean:
- rm -rf $(FATFS_OBJS)
- rm -rf ${RELEASEDIR}/${LIB}
- rm -rf ${DEPFILES}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3a/a15252595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3a/a15252595243001d18b399c1eb9b3628
deleted file mode 100644
index 5d13db7..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3a/a15252595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,19 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/* The errno variable is stored in the reentrancy structure. This
- function returns its address for use by the macro errno defined in
- errno.h. */
-
-#include
-#include
-#include "xil_types.h"
-sint32 * __errno (void);
-
-sint32 *
-__errno (void)
-{
- return &_REENT->_errno;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3a/a1f449565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3a/a1f449565243001d18b399c1eb9b3628
deleted file mode 100644
index da7e768..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3a/a1f449565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,36 +0,0 @@
-/* print.c -- print a string on the output device.
- *
- * Copyright (c) 1995 Cygnus Support
- *
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- *
- */
-
-/*
- * print -- do a raw print of a string
- */
-#include "xil_printf.h"
-
-void print(const char8 *ptr)
-{
-#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
- XPVXenConsole_Write(ptr);
-#else
-#ifdef STDOUT_BASEADDRESS
- while (*ptr != (char8)0) {
- outbyte (*ptr);
- ptr++;
- }
-#else
-(void)ptr;
-#endif
-#endif
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3a/b151b8575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3a/b151b8575243001d18b399c1eb9b3628
deleted file mode 100644
index 6f40407..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3a/b151b8575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,52 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xcoresightpsdcc.h
-* @addtogroup coresightps_dcc_v1_8
-* @{
-* @details
-*
-* CoreSight driver component.
-*
-* The coresight is a part of debug communication channel (DCC) group. Jtag UART
-* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
-* ARM target in XSDB console before running the jtag terminal command. Using the
-* coresight driver component, the output stream can be directed to a log file.
-*
-* @note None.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------
-* 1.00 kvn 02/14/15 First release
-* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
-* kvn 08/18/15 Modified Makefile according to compiler changes.
-* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
-* for MB BSPs. Instead it throws up a warning. This
-* fixes the CR#953056.
-* 1.5 sne 01/19/19 Fixed MISRA-C Violations CR#1025101.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#ifndef XCORESIGHTPSDCC_H /* prevent circular inclusions */
-#define XCORESIGHTPSDCC_H /* by using protection macros */
-#ifndef __MICROBLAZE__
-#include
-
-void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
-
-u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
-#endif
-#endif
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3a/d3496d585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3a/d3496d585243001d18b399c1eb9b3628
deleted file mode 100644
index 8e8bfd9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3a/d3496d585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
-Copyright DornerWorks 2016
-
-Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-following conditions are met:
-1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
-following disclaimer.
-
-THIS SOFTWARE IS PROVIDED BY DORNERWORKS FOR USE ON THE CONTRACTED PROJECT, AND ANY EXPRESS OR IMPLIED WARRANTY
-IS LIMITED TO THIS USE. FOR ALL OTHER USES THIS SOFTWARE IS PROVIDED ''AS IS'' AND ANY EXPRESS OR IMPLIED
-WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL DORNERWORKS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#include "xen.h"
-
-
-.globl HYPERVISOR_console_io;
-.align 4;
-HYPERVISOR_console_io:
- mov x16, __HYPERVISOR_console_io;
- hvc 0xEA1;
- ret;
-
-
-.globl HYPERVISOR_hvm_op;
-.align 4;
-HYPERVISOR_hvm_op:
- mov x16, __HYPERVISOR_hvm_op;
- hvc 0xEA1;
- ret;
-
-.globl HYPERVISOR_memory_op;
-.align 4;
-HYPERVISOR_memory_op:
- mov x16, __HYPERVISOR_memory_op;
- hvc 0xEA1;
- ret;
-
-.globl HYPERVISOR_event_channel_op;
-.align 4;
-HYPERVISOR_event_channel_op:
- mov x16, __HYPERVISOR_event_channel_op
- hvc 0xEA1;
- ret;
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3b/109ef6585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3b/109ef6585243001d18b399c1eb9b3628
deleted file mode 100644
index d21e13a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3b/109ef6585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,92 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2012 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_mmu.h
-*
-* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions
-*
-* MMU functions equip users to enable MMU, disable MMU and modify default
-* memory attributes of MMU table as per the need.
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 01/12/12 Initial version
-* 4.2 pkp 07/21/14 Included xil_types.h file which contains definition for
-* u32 which resolves issue of CR#805869
-* 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 01/12/12 Initial version
-* 4.2 pkp 07/21/14 Included xil_types.h file which contains definition for
-* u32 which resolves issue of CR#805869
-* 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-* MODIFICATION HISTORY :
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 6.6 srm 11/02/17 Added processor specific sleep routines
-* function prototypes.
-*
-*
-*
-******************************************************************************/
-
-#ifndef SLEEP_H
-#define SLEEP_H
-
-#include "xil_types.h"
-#include "xil_io.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*****************************************************************************/
-/**
-*
-* This macro polls an address periodically until a condition is met or till the
-* timeout occurs.
-* The minimum timeout for calling this macro is 100us. If the timeout is less
-* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
-* If the timeout is not a multiple of 100us, it waits for a timeout of
-* the next usec value which is a multiple of 100us.
-*
-* @param IO_func - accessor function to read the register contents.
-* Depends on the register width.
-* @param ADDR - Address to be polled
-* @param VALUE - variable to read the value
-* @param COND - Condition to checked (usually involves VALUE)
-* @param TIMEOUT_US - timeout in micro seconds
-*
-* @return 0 - when the condition is met
-* -1 - when the condition is not met till the timeout period
-*
-* @note none
-*
-*****************************************************************************/
-#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
- ( { \
- u64 timeout = TIMEOUT_US/100; \
- if(TIMEOUT_US%100!=0) \
- timeout++; \
- for(;;) { \
- VALUE = IO_func(ADDR); \
- if(COND) \
- break; \
- else { \
- usleep(100); \
- timeout--; \
- if(timeout==0) \
- break; \
- } \
- } \
- (timeout>0) ? 0 : -1; \
- } )
-
-void usleep(unsigned long useconds);
-void sleep(unsigned int seconds);
-int usleep_R5(unsigned long useconds);
-unsigned sleep_R5(unsigned int seconds);
-int usleep_MB(unsigned long useconds);
-unsigned sleep_MB(unsigned int seconds);
-int usleep_A53(unsigned long useconds);
-unsigned sleep_A53(unsigned int seconds);
-int usleep_A9(unsigned long useconds);
-unsigned sleep_A9(unsigned int seconds);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3c/116c2e585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3c/116c2e585243001d18b399c1eb9b3628
deleted file mode 100644
index 154f808..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3c/116c2e585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1564 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xsdps_card.c
-* @addtogroup sdps_v3_13
-* @{
-*
-* Contains the interface functions of the XSdPs driver.
-* See xsdps.h for a detailed description of the device and driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 3.9 mn 03/03/20 Restructured the code for more readability and modularity
-* mn 03/16/20 Move XSdPs_Select_Card API to User APIs
-* 3.10 mn 06/05/20 Check Transfer completion separately from XSdPs_Read and
-* XSdPs_Write APIs
-* mn 10/15/20 Modify power cycle API to poll for SD bus lines to go
-* low for versal platform
-* 3.12 sk 01/28/21 Added support for non-blocking write.
-* sk 02/12/21 Fix the issue in reading CID and CSD.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xsdps_core.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-* @brief
-* This function performs SD read in polled mode.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Arg is the address passed by the user that is to be sent as
-* argument along with the command.
-* @param BlkCnt - Block count passed by the user.
-* @param Buff - Pointer to the data buffer for a DMA transfer.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because another transfer
-* is in progress or command or data inhibit is set
-*
-******************************************************************************/
-s32 XSdPs_Read(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
-{
- s32 Status;
-
- XSdPs_SetupReadDma(InstancePtr, BlkCnt, InstancePtr->BlkSize, Buff);
-
- if (BlkCnt == 1U) {
- /* Send single block read command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD17, Arg, BlkCnt);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
- } else {
- /* Send multiple blocks read command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
- }
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function performs SD write in polled mode.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Arg is the address passed by the user that is to be sent as
-* argument along with the command.
-* @param BlkCnt - Block count passed by the user.
-* @param Buff - Pointer to the data buffer for a DMA transfer.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because another transfer
-* is in progress or command or data inhibit is set
-*
-******************************************************************************/
-s32 XSdPs_Write(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
-{
- s32 Status;
-
- XSdPs_SetupWriteDma(InstancePtr, BlkCnt, InstancePtr->BlkSize, Buff);
-
- if (BlkCnt == 1U) {
- /* Send single block write command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD24, Arg, BlkCnt);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
- } else {
- /* Send multiple blocks write command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
- }
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to check for the transfer complete.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if transfer was successful
-* - XST_FAILURE if failure
-* - XST_DEVICE_BUSY - if the transfer is still in progress
-*
-******************************************************************************/
-s32 XSdPs_CheckTransferComplete(XSdPs *InstancePtr)
-{
- u16 StatusReg;
- s32 Status;
-
- if (InstancePtr->IsBusy == FALSE) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /*
- * Check for transfer complete
- */
- StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET);
- if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
- /* Write to clear error bits */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET,
- XSDPS_ERROR_INTR_ALL_MASK);
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if ((StatusReg & XSDPS_INTR_TC_MASK) == 0U) {
- Status = XST_DEVICE_BUSY;
- goto RETURN_PATH;
- }
-
- /* Write to clear bit */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
-
- InstancePtr->IsBusy = FALSE;
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* Identify type of card using CMD0 + CMD1 sequence
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-******************************************************************************/
-s32 XSdPs_IdentifyCard(XSdPs *InstancePtr)
-{
- s32 Status;
-
- if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
- ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
- == XSDPS_CAPS_EMB_SLOT)) {
- InstancePtr->CardType = XSDPS_CHIP_EMMC;
- Status = XST_SUCCESS;
- goto RETURN_PATH;
- }
-
- /* 74 CLK delay after card is powered up, before the first command. */
- usleep(XSDPS_INIT_DELAY);
-
- /* CMD0 no response expected */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Host High Capacity support & High voltage window */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
- XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
- if (Status != XST_SUCCESS) {
- InstancePtr->CardType = XSDPS_CARD_SD;
- } else {
- InstancePtr->CardType = XSDPS_CARD_MMC;
- }
-
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
-
- Status = XSdPs_Reset(InstancePtr, XSDPS_SWRST_CMD_LINE_MASK);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* SD initialization is done in this function
-*
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because
-* a) SD is already initialized
-* b) There is no card inserted
-* c) One of the steps (commands) in the
- initialization cycle failed
-*
-* @note This function initializes the SD card by following its
-* initialization and identification state diagram.
-* CMD0 is sent to reset card.
-* CMD8 and ACDM41 are sent to identify voltage and
-* high capacity support
-* CMD2 and CMD3 are sent to obtain Card ID and
-* Relative card address respectively.
-* CMD9 is sent to read the card specific data.
-*
-******************************************************************************/
-s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr)
-{
- s32 Status;
-
-#ifndef UHS_MODE_ENABLE
- InstancePtr->Config.BusWidth = XSDPS_WIDTH_4;
-#endif
-
- Status = XSdPs_SdCardEnum(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XSdPs_SdModeInit(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* Mmc initialization is done in this function
-*
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because
-* a) MMC is already initialized
-* b) There is no card inserted
-* c) One of the steps (commands) in the initialization
-* cycle failed
-* @note This function initializes the SD card by following its
-* initialization and identification state diagram.
-* CMD0 is sent to reset card.
-* CMD1 sent to identify voltage and high capacity support
-* CMD2 and CMD3 are sent to obtain Card ID and
-* Relative card address respectively.
-* CMD9 is sent to read the card specific data.
-*
-******************************************************************************/
-s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr)
-{
- s32 Status;
-
- Status = XSdPs_MmcCardEnum(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if (((InstancePtr->CardType == XSDPS_CARD_MMC) &&
- (InstancePtr->Card_Version > CSD_SPEC_VER_3)) &&
- (InstancePtr->HC_Version == XSDPS_HC_SPEC_V2)) {
- Status = XSdPs_MmcModeInit(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } else if (InstancePtr->CardType == XSDPS_CHIP_EMMC) {
- Status = XSdPs_EmmcModeInit(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } else {
- Status = XST_FAILURE;
- goto RETURN_PATH;
-
- }
-
- if (InstancePtr->Mode != XSDPS_DDR52_MODE) {
- Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } else {
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_SIZE_OFFSET, XSDPS_BLK_SIZE_512_MASK);
- InstancePtr->BlkSize = XSDPS_BLK_SIZE_512_MASK;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function checks if the card is present or not.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_CheckCardDetect(XSdPs *InstancePtr)
-{
- u32 PresentStateReg;
- s32 Status;
-
- if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
- ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
- == XSDPS_CAPS_EMB_SLOT)) {
- Status = XST_SUCCESS;
- goto RETURN_PATH;
- }
-
- if(InstancePtr->Config.CardDetect != 0U) {
- /*
- * Check the present state register to make sure
- * card is inserted and detected by host controller
- */
- PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function sends CMD0 to reset the card.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_CardReset(XSdPs *InstancePtr)
-{
- s32 Status;
-
- /* CMD0 no response expected */
- Status = XSdPs_CmdTransfer(InstancePtr, (u32)CMD0, 0U, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function sends command to get the card interface details.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_CardIfCond(XSdPs *InstancePtr)
-{
- u32 RespOCR;
- s32 Status;
-
- /*
- * CMD8; response expected
- * 0x1AA - Supply Voltage 2.7 - 3.6V and AA is pattern
- */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD8,
- XSDPS_CMD8_VOL_PATTERN, 0U);
- if ((Status != XST_SUCCESS) && (Status != XSDPS_CT_ERROR)) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if (Status == XSDPS_CT_ERROR) {
- Status = XSdPs_Reset(InstancePtr, XSDPS_SWRST_CMD_LINE_MASK);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
- }
-
- RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET);
- if (RespOCR != XSDPS_CMD8_VOL_PATTERN) {
- InstancePtr->Card_Version = XSDPS_SD_VER_1_0;
- } else {
- InstancePtr->Card_Version = XSDPS_SD_VER_2_0;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function sends command to get the card operating condition.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_CardOpCond(XSdPs *InstancePtr)
-{
- u32 RespOCR;
- s32 Status;
- u32 Arg;
-
- /* Send ACMD41 while card is still busy with power up */
- do {
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
- Status = XSdPs_CmdTransfer(InstancePtr, CMD55, 0U, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U);
- if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
- (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) {
- Arg |= XSDPS_OCR_S18;
- }
-
- /* 0x40300000 - Host High Capacity support & 3.3V window */
- Status = XSdPs_CmdTransfer(InstancePtr, ACMD41,
- Arg, 0U);
- } else {
- /* Send CMD1 while card is still busy with power up */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
- XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
- }
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Response with card capacity */
- RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET);
- } while ((RespOCR & XSDPS_RESPOCR_READY) == 0U);
-
- /* Update HCS support flag based on card capacity response */
- if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) {
- InstancePtr->HCS = 1U;
- }
-
- if ((RespOCR & XSDPS_OCR_S18) != 0U) {
- InstancePtr->Switch1v8 = 1U;
- Status = XSdPs_Switch_Voltage(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to get the card ID.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_GetCardId(XSdPs *InstancePtr)
-{
- s32 Status;
-
- /* CMD2 for Card ID */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- InstancePtr->CardID[0] =
- XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET);
- InstancePtr->CardID[1] =
- XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP1_OFFSET);
- InstancePtr->CardID[2] =
- XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP2_OFFSET);
- InstancePtr->CardID[3] =
- XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP3_OFFSET);
-
- if(InstancePtr->CardType == XSDPS_CARD_SD) {
- do {
- Status = XSdPs_CmdTransfer(InstancePtr, CMD3, 0U, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /*
- * Relative card address is stored as the upper 16 bits
- * This is to avoid shifting when sending commands
- */
- InstancePtr->RelCardAddr =
- XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET) & 0xFFFF0000U;
- } while (InstancePtr->RelCardAddr == 0U);
- } else {
- /* Set relative card address */
- InstancePtr->RelCardAddr = 0x12340000U;
- Status = XSdPs_CmdTransfer(InstancePtr, CMD3, (InstancePtr->RelCardAddr), 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to get the CSD register from the card.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_GetCsd(XSdPs *InstancePtr)
-{
- s32 Status;
- u32 CSD[4];
- u32 BlkLen;
- u32 DeviceSize;
- u32 Mult;
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /*
- * Card specific data is read.
- * Currently not used for any operation.
- */
- CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP0_OFFSET);
- CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP1_OFFSET);
- CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP2_OFFSET);
- CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_RESP3_OFFSET);
-
- InstancePtr->CardSpecData[0] = CSD[0];
- InstancePtr->CardSpecData[1] = CSD[1];
- InstancePtr->CardSpecData[2] = CSD[2];
- InstancePtr->CardSpecData[3] = CSD[3];
-
- if (InstancePtr->CardType != XSDPS_CARD_SD) {
- InstancePtr->Card_Version = (u8)((u32)(CSD[3] & CSD_SPEC_VER_MASK) >>18U);
- Status = XST_SUCCESS;
- goto RETURN_PATH;
- }
-
- if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 0U) {
- BlkLen = 1U << ((u32)(CSD[2] & READ_BLK_LEN_MASK) >> 8U);
- Mult = 1U << ((u32)((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U);
- DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U;
- DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U;
- DeviceSize = (DeviceSize + 1U) * Mult;
- DeviceSize = DeviceSize * BlkLen;
- InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK);
- } else if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 1U) {
- InstancePtr->SectorCount = (((CSD[1] & CSD_V2_C_SIZE_MASK) >> 8U) +
- 1U) * 1024U;
- } else {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to set the card voltage to 1.8V.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_CardSetVoltage18(XSdPs *InstancePtr)
-{
- s32 Status;
- u16 CtrlReg;
- u16 ClockReg;
-
- /* Stop the clock */
- CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
- CtrlReg);
-
- /* Check for 1.8V signal enable bit is cleared by Host */
- Status = XSdPs_SetVoltage18(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- /* Enable the clock in the controller */
- Status = XSdPs_EnableClock(InstancePtr, ClockReg);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- /* Wait for 1mSec */
- (void)usleep(1000U);
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to do initial Reset Configuration.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_ResetConfig(XSdPs *InstancePtr)
-{
- s32 Status;
-
- XSdPs_DisableBusPower(InstancePtr);
-
-#ifdef versal
- if ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
- != XSDPS_CAPS_EMB_SLOT) {
- u32 Timeout = 200000U;
- u32 PresentStateReg;
-
- /* Check for SD Bus Lines low */
- do {
- PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- Timeout = Timeout - 1U;
- usleep(1);
- } while (((PresentStateReg & XSDPS_PSR_DAT30_SG_LVL_MASK) != 0U)
- && (Timeout != 0U));
- }
-#endif
-
- Status = XSdPs_Reset(InstancePtr, XSDPS_SWRST_ALL_MASK);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- XSdPs_EnableBusPower(InstancePtr);
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to do initial Host Configuration.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-void XSdPs_HostConfig(XSdPs *InstancePtr)
-{
- XSdPs_ConfigPower(InstancePtr);
-
- XSdPs_ConfigDma(InstancePtr);
-
- XSdPs_ConfigInterrupt(InstancePtr);
-
- /*
- * Transfer mode register - default value
- * DMA enabled, block count enabled, data direction card to host(read)
- */
- InstancePtr->TransferMode = XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK |
- XSDPS_TM_DAT_DIR_SEL_MASK;
-
- /* Set block size to 512 by default */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_SIZE_OFFSET, XSDPS_BLK_SIZE_512_MASK);
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function checks for Reset Done bits to be cleared after a reset assert.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Value is the bits to be checked to be cleared.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_CheckResetDone(XSdPs *InstancePtr, u8 Value)
-{
- u32 Timeout = 1000000U;
- u32 ReadReg;
- s32 Status;
-
- /* Proceed with initialization only after reset is complete */
- do {
- ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
- XSDPS_SW_RST_OFFSET);
- Timeout = Timeout - 1U;
- usleep(1);
- } while (((ReadReg & Value) != 0U)
- && (Timeout != 0U));
-
- if (Timeout == 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to setup the voltage switch.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_SetupVoltageSwitch(XSdPs *InstancePtr)
-{
- u32 Timeout = 10000;
- s32 Status;
- u32 ReadReg;
-
- /* Send switch voltage command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD11, 0U, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Wait for CMD and DATA line to go low */
- do {
- ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- Timeout = Timeout - 1;
- usleep(1);
- } while (((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK |
- XSDPS_PSR_DAT30_SG_LVL_MASK)) != 0U)
- && (Timeout != 0U));
-
- if (Timeout == 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to check if the Cmd and Dat buses are high.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_CheckBusHigh(XSdPs *InstancePtr)
-{
- u32 Timeout = 10000;
- s32 Status;
- u32 ReadReg;
-
- /* Wait for CMD and DATA line to go high */
- Timeout = MAX_TIMEOUT;
- do {
- ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- Timeout = Timeout - 1;
- usleep(1);
- } while (((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK))
- != (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK))
- && (Timeout != 0U));
-
- if (Timeout == 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to Identify the supported UHS mode. This API will assign the
-* corresponding tap delay API to the Config_TapDelay pointer based on the
-* supported bus speed.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param ReadBuff contains the response for CMD6
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff)
-{
- if (((ReadBuff[13] & UHS_SDR104_SUPPORT) != 0U) &&
- (InstancePtr->Config.InputClockHz >= XSDPS_SD_INPUT_MAX_CLK)) {
- InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR104;
- if (InstancePtr->Config.BankNumber == 2U) {
- InstancePtr->OTapDelay = SD_OTAPDLYSEL_HS200_B2;
- } else {
- InstancePtr->OTapDelay = SD_OTAPDLYSEL_HS200_B0;
- }
- } else if (((ReadBuff[13] & UHS_SDR50_SUPPORT) != 0U) &&
- (InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR50_MAX_CLK)) {
- InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR50;
- InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD50;
- } else if (((ReadBuff[13] & UHS_DDR50_SUPPORT) != 0U) &&
- (InstancePtr->Config.InputClockHz >= XSDPS_SD_DDR50_MAX_CLK)) {
- InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_DDR50;
- InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD_DDR50;
- InstancePtr->ITapDelay = SD_ITAPDLYSEL_SD_DDR50;
- } else if (((ReadBuff[13] & UHS_SDR25_SUPPORT) != 0U) &&
- (InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR25_MAX_CLK)) {
- InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR25;
- InstancePtr->OTapDelay = SD_OTAPDLYSEL_SD_HSD;
- InstancePtr->ITapDelay = SD_ITAPDLYSEL_HSD;
- } else {
- InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR12;
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to set Tap Delay w.r.t speed modes
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-void XSdPs_SetTapDelay(XSdPs *InstancePtr)
-{
- if ((InstancePtr->Mode == XSDPS_DEFAULT_SPEED_MODE) ||
- (InstancePtr->Mode == XSDPS_UHS_SPEED_MODE_SDR12)) {
- return;
- }
-
-#ifndef versal
- /* Issue DLL Reset */
- XSdPs_DllRstCtrl(InstancePtr, 1U);
-#endif
-
- /* Configure the Tap Delay Registers */
- XSdPs_ConfigTapDelay(InstancePtr);
-
-#ifndef versal
- /* Release the DLL out of reset */
- XSdPs_DllRstCtrl(InstancePtr, 0U);
-#endif
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to change the SD Bus Speed.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_Change_SdBusSpeed(XSdPs *InstancePtr)
-{
- s32 Status;
- u32 Arg;
- u16 BlkCnt;
- u16 BlkSize;
- u16 CtrlReg;
- u8 ReadBuff[64] = {0U};
-
- Status = XSdPs_CalcBusSpeed(InstancePtr, &Arg);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
- BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
-
- XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, ReadBuff);
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, BlkCnt);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Check for transfer done */
- Status = XSdps_CheckTransferDone(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- if (InstancePtr->Switch1v8 != 0U) {
- /* Set UHS mode in controller */
- CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET);
- CtrlReg &= (u16)(~XSDPS_HC2_UHS_MODE_MASK);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET,
- CtrlReg | InstancePtr->Mode);
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to change the eMMC bus speed.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_Change_MmcBusSpeed(XSdPs *InstancePtr)
-{
- s32 Status;
- u32 Arg;
-
- Status = XSdPs_CalcBusSpeed(InstancePtr, &Arg);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Check for transfer done */
- Status = XSdps_CheckTransferDone(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to do the Auto tuning.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_AutoTuning(XSdPs *InstancePtr)
-{
- s32 Status;
- u16 BlkSize;
- u8 TuningCount;
-
- BlkSize = XSDPS_TUNING_CMD_BLKSIZE;
- if(InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH)
- {
- BlkSize = BlkSize*2U;
- }
- BlkSize &= XSDPS_BLK_SIZE_MASK;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
- BlkSize);
-
- InstancePtr->TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK;
-
- XSdPs_SetExecTuning(InstancePtr);
- /*
- * workaround which can work for 1.0/2.0 silicon for auto tuning.
- * This can be revisited for 3.0 silicon if necessary.
- */
- /* Wait for ~60 clock cycles to reset the tap values */
- (void)usleep(1U);
-
- for (TuningCount = 0U; TuningCount < MAX_TUNING_COUNT; TuningCount++) {
-
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
- Status = XSdPs_CmdTransfer(InstancePtr, CMD19, 0U, 1U);
- } else {
- Status = XSdPs_CmdTransfer(InstancePtr, CMD21, 0U, 1U);
- }
-
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_EXEC_TNG_MASK) == 0U) {
- break;
- }
- }
-
- if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_SAMP_CLK_SEL_MASK) == 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Wait for ~12 clock cycles to synchronize the new tap values */
- (void)usleep(1U);
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to setup ADMA2 descriptor table
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param BlkCnt - block count.
-* @param Buff pointer to data buffer.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
-{
- if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
- XSdPs_Setup64ADMA2DescTbl(InstancePtr, BlkCnt, Buff);
- } else {
- XSdPs_Setup32ADMA2DescTbl(InstancePtr, BlkCnt, Buff);
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to setup ADMA2 descriptor table for 64 Bit DMA
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param BlkCnt - block count.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-void XSdPs_SetupADMA2DescTbl64Bit(XSdPs *InstancePtr, u32 BlkCnt)
-{
-#ifdef __ICCARM__
-#pragma data_alignment = 32
- static XSdPs_Adma2Descriptor64 Adma2_DescrTbl[32];
-#else
- static XSdPs_Adma2Descriptor64 Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
-#endif
- u32 TotalDescLines;
- u64 DescNum;
- u32 BlkSize;
-
- /* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */
- BlkSize = (u32)XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_SIZE_OFFSET) &
- XSDPS_BLK_SIZE_MASK;
-
- if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) {
-
- TotalDescLines = 1U;
-
- } else {
-
- TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH);
- if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) {
- TotalDescLines += 1U;
- }
-
- }
-
- for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) {
- Adma2_DescrTbl[DescNum].Address =
- InstancePtr->Dma64BitAddr +
- (DescNum*XSDPS_DESC_MAX_LENGTH);
- Adma2_DescrTbl[DescNum].Attribute =
- XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
- Adma2_DescrTbl[DescNum].Length = 0U;
- }
-
- Adma2_DescrTbl[TotalDescLines-1].Address =
- InstancePtr->Dma64BitAddr +
- (DescNum*XSDPS_DESC_MAX_LENGTH);
-
- Adma2_DescrTbl[TotalDescLines-1].Attribute =
- XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
-
- Adma2_DescrTbl[TotalDescLines-1].Length =
- (u16)((BlkCnt*BlkSize) - (u32)(DescNum*XSDPS_DESC_MAX_LENGTH));
-
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
- (u32)((UINTPTR)&(Adma2_DescrTbl[0]) & (u32)~0x0));
-
- if (InstancePtr->Config.IsCacheCoherent == 0U) {
- Xil_DCacheFlushRange((INTPTR)&(Adma2_DescrTbl[0]),
- sizeof(XSdPs_Adma2Descriptor64) * 32U);
- }
-
- /* Clear the 64-Bit Address variable */
- InstancePtr->Dma64BitAddr = 0U;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to reset the DLL
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_DllReset(XSdPs *InstancePtr)
-{
- u32 ClockReg;
- s32 Status;
-
- /* Disable clock */
- ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- ClockReg &= ~XSDPS_CC_SD_CLK_EN_MASK;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET, (u16)ClockReg);
-
- /* Issue DLL Reset to load zero tap values */
- XSdPs_DllRstCtrl(InstancePtr, 1U);
-
- /* Wait for 2 micro seconds */
- (void)usleep(2U);
-
- XSdPs_DllRstCtrl(InstancePtr, 0U);
-
- ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET);
- /* Enable the clock in the controller */
- Status = XSdPs_EnableClock(InstancePtr, ClockReg);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to identify the eMMC speed mode.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param ExtCsd is the extended CSD register from the card
-*
-* @return None
-*
-******************************************************************************/
-void XSdPs_IdentifyEmmcMode(XSdPs *InstancePtr, const u8 *ExtCsd)
-{
- if (InstancePtr->BusWidth < XSDPS_4_BIT_WIDTH) {
- InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
- } else {
- /* Check for card supported speed */
- if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
- (EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 |
- EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) {
- InstancePtr->Mode = XSDPS_HS200_MODE;
- if (InstancePtr->Config.BankNumber == 2U) {
- InstancePtr->OTapDelay = SD_OTAPDLYSEL_HS200_B2;
- } else {
- InstancePtr->OTapDelay = SD_OTAPDLYSEL_HS200_B0;
- }
- } else if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
- (EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED |
- EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED)) != 0U) {
- InstancePtr->Mode = XSDPS_DDR52_MODE;
- InstancePtr->OTapDelay = SD_OTAPDLYSEL_EMMC_DDR50;
- InstancePtr->ITapDelay = SD_ITAPDLYSEL_EMMC_DDR50;
- } else if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
- EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) {
- InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
- InstancePtr->OTapDelay = SD_OTAPDLYSEL_EMMC_HSD;
- InstancePtr->ITapDelay = SD_ITAPDLYSEL_HSD;
- } else {
- InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
- }
- }
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to check the eMMC timing.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param ExtCsd is the extended CSD register from the card
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_CheckEmmcTiming(XSdPs *InstancePtr, u8 *ExtCsd)
-{
- s32 Status;
-
- Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if (InstancePtr->Mode == XSDPS_HS200_MODE) {
- if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } else if ((InstancePtr->Mode == XSDPS_HIGH_SPEED_MODE) ||
- (InstancePtr->Mode == XSDPS_DDR52_MODE)) {
- if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } else {
- Status = XST_FAILURE;
- }
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to set the clock to the passed frequency.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param SelFreq is the selected frequency
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_SetClock(XSdPs *InstancePtr, u32 SelFreq)
-{
- u16 ClockReg;
- s32 Status;
-
- /* Disable clock */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_CLK_CTRL_OFFSET, 0U);
-
- /* If selected frequency is zero, return from here */
- if (SelFreq == 0U) {
- Status = XST_SUCCESS;
- goto RETURN_PATH ;
- }
-
- /* Calculate the clock */
- ClockReg = XSdPs_CalcClock(InstancePtr, SelFreq);
-
- /* Enable the clock in the controller */
- Status = XSdPs_EnableClock(InstancePtr, ClockReg);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function checks if the voltage is set to 1.8V or not.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if voltage is 1.8V
-* - XST_FAILURE if voltage is not 1.8V
-*
-******************************************************************************/
-s32 XSdPs_CheckVoltage18(XSdPs *InstancePtr)
-{
- u32 Status;
-
- if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_1V8_EN_MASK) == 0U) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function initializes the command sequence.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Arg is the address passed by the user that is to be sent as
-* argument along with the command.
-* @param BlkCnt - Block count passed by the user.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_SetupCmd(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt)
-{
- s32 Status;
-
- /*
- * Check the command inhibit to make sure no other
- * command transfer is in progress
- */
- Status = XSdPs_CheckBusIdle(InstancePtr, XSDPS_PSR_INHIBIT_CMD_MASK);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- /* Write block count register */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_BLK_CNT_OFFSET, (u16)BlkCnt);
-
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_TIMEOUT_CTRL_OFFSET, 0xEU);
-
- /* Write argument register */
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress,
- XSDPS_ARGMT_OFFSET, Arg);
-
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function initiates the Cmd transfer to SD card.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Cmd is the command to be sent
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure
-*
-******************************************************************************/
-s32 XSdPs_SendCmd(XSdPs *InstancePtr, u32 Cmd)
-{
- u32 PresentStateReg;
- u32 CommandReg;
- s32 Status;
-
- /* Command register is set to trigger transfer of command */
- CommandReg = XSdPs_FrameCmd(InstancePtr, Cmd);
-
- /*
- * Mask to avoid writing to reserved bits 31-30
- * This is necessary because 0x8000 is used by this software to
- * distinguish between ACMD and CMD of same number
- */
- CommandReg = CommandReg & 0x3FFFU;
-
- /*
- * Check for data inhibit in case of command using DAT lines.
- * For Tuning Commands DAT lines check can be ignored.
- */
- if ((Cmd != CMD21) && (Cmd != CMD19)) {
- PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_PRES_STATE_OFFSET);
- if (((PresentStateReg & XSDPS_PSR_INHIBIT_DAT_MASK) != 0U) &&
- ((CommandReg & XSDPS_DAT_PRESENT_SEL_MASK) != 0U)) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET,
- (CommandReg << 16) | InstancePtr->TransferMode);
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
- return Status;
-
-}
-
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3c/30f9f7545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3c/30f9f7545243001d18b399c1eb9b3628
deleted file mode 100644
index d61e2b5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3c/30f9f7545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,118 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xsdps_core.h
-* @addtogroup sdps_v3_13
-* @{
-*
-* This header file contains the identifiers and basic HW access driver
-* functions (or macros) that can be used to access the device. Other driver
-* functions are defined in xsdps.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 3.9 mn 03/03/20 Restructured the code for more readability and modularity
-* mn 03/16/20 Move XSdPs_Select_Card API to User APIs
-* 3.12 sk 01/28/21 Added support for non-blocking write.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00 hbm 03/29/2010 First Release
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xdmaps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/****************************************************************************/
-/**
-*
-* This function runs a self-test on the driver and hardware device. This self
-* test performs a local loopback and verifies data can be sent and received.
-*
-* The time for this test is proportional to the baud rate that has been set
-* prior to calling this function.
-*
-* The mode and control registers are restored before return.
-*
-* @param InstPtr is a pointer to the XDmaPs instance
-*
-* @return
-*
-* - XST_SUCCESS if the test was successful
-* - XST_FAILURE if the test failed
-*
-* @note
-*
-* This function can hang if the hardware is not functioning properly.
-*
-******************************************************************************/
-int XDmaPs_SelfTest(XDmaPs *InstPtr)
-{
- u32 BaseAddr = InstPtr->Config.BaseAddress;
- int i;
-
- if (XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
- & XDMAPS_DBGSTATUS_BUSY)
- return XST_FAILURE;
-
- for (i = 0; i < XDMAPS_CHANNELS_PER_DEV; i++) {
- if (XDmaPs_ReadReg(BaseAddr,
- XDmaPs_CSn_OFFSET(i)))
- return XST_FAILURE;
- }
- return XST_SUCCESS;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3c/c002ae555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3c/c002ae555243001d18b399c1eb9b3628
deleted file mode 100644
index b8b9f7a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3c/c002ae555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,34 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/*
- *
- * This is a template implementation of the "__lseek" function used by
- * the standard library. Replace it with a system-specific
- * implementation.
- *
- * The "__lseek" function makes the next file operation (__read or
- * __write) act on a new location. The parameter "whence" specifies
- * how the "offset" parameter should be interpreted according to the
- * following table:
- *
- * 0 (=SEEK_SET) - Goto location "offset".
- * 1 (=SEEK_CUR) - Go "offset" bytes from the current location.
- * 2 (=SEEK_END) - Go to "offset" bytes from the end.
- *
- * This function should return the current file position, or -1 on
- * failure.
- */
-
-#include
-#include
-#include "xil_types.h"
-LONG __lseek(sint32 handle, LONG offset, sint32 whence);
-
-LONG __lseek(sint32 handle, LONG offset, sint32 whence)
-{
- return (-1);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3d/104e33585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3d/104e33585243001d18b399c1eb9b3628
deleted file mode 100644
index 7de36d8..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3d/104e33585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,38 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 2021.2
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2022 Xilinx, Inc. All Rights Reserved.
-* SPDX-License-Identifier: MIT
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xsdps.h"
-
-/*
-* The configuration table for devices
-*/
-
-XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES] =
-{
- {
- XPAR_PS7_SD_0_DEVICE_ID,
- XPAR_PS7_SD_0_BASEADDR,
- XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ,
- XPAR_PS7_SD_0_HAS_CD,
- XPAR_PS7_SD_0_HAS_WP,
- XPAR_PS7_SD_0_BUS_WIDTH,
- XPAR_PS7_SD_0_MIO_BANK,
- XPAR_PS7_SD_0_HAS_EMIO,
- XPAR_PS7_SD_0_IS_CACHE_COHERENT
- }
-};
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3d/105a43555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3d/105a43555243001d18b399c1eb9b3628
deleted file mode 100644
index 3c79b0b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3d/105a43555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,56 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm.h
-*
-* @addtogroup a53_64_specific Cortex A53 64bit Processor Specific Include Files
-*
-* The xpseudo_asm.h includes xreg_cortexa53.h and xpseudo_asm_gcc.h.
-* The xreg_cortexa53.h file contains definitions for inline assembler code.
-* It provides inline definitions for Cortex A53 GPRs, SPRs and floating point
-* registers.
-*
-* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
-* assembler instructions, available as macros. These can be very useful for
-* tasks such as setting or getting special purpose registers, synchronization,
-* or cache manipulation etc. These inline assembler instructions can be used
-* from drivers and user applications written in C.
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.00 pkp 05/29/14 First release
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------------
-* 1.00a drg 01/19/10 First release
-* 1.01a sdm 11/09/11 "xil_exception.h" added as include.
-* Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
-* added to enable or disable interrupts based on
-* Distributor Register base address. Normally users use
-* XScuGic instance and call XScuGic_Enable or
-* XScuGic_Disable to enable/disable interrupts. These
-* new macros are provided when user does not want to
-* use an instance pointer but still wants to enable or
-* disable interrupts.
-* Function prototypes for functions (present in newly
-* added file xscugic_hw.c) are added.
-* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
-* 702687).
-* 1.04a hk 05/04/13 Fix for CR#705621. Moved function prototypes
-* XScuGic_SetPriTrigTypeByDistAddr and
-* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
-* 3.0 pkp 12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
-* Zynq Ultrascale Mp
-* 3.0 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
-* 3.2 pkp 11/09/15 Corrected the interrupt processsor target mask value
-* for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
-* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
-* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
-* API's can be used by applications to unmap specific/all
-* interrupts from target CPU. It fixes CR#992490.
-* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
-* 4.1 asa 03/30/19 Removed macros for XScuGic_EnableIntr, and
-* XScuGic_DisableIntr. These are now C functions. This
-* change was to fix CR-1024716.
-* 4.1 mus 06/12/19 Updated XSCUGIC_MAX_NUM_INTR_INPUTS for Versal.
-* 4.6 sk 06/07/21 Delete the commented macro code to fix the MISRA-C warning.
-* 4.6 sk 08/05/21 Fix Scugic Misrac violations.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
-* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
-* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
-* in xadcps.c to fix CR #693371
-* 1.03a bss 11/01/13 Modified xadcps_hw.h to use correct Register offsets
-* CR#749687
-* 2.1 bss 08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
-* XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
-* XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
-* functions.
-* Modified Assert for XAdcPs_SetSingleChParams in
-* xadcps.c to fix CR #807563.
-* 2.2 bss 04/27/14 Modified to use correct Device Config base address in
-* xadcps.c (CR#854437).
-* ms 01/23/17 Added xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/05/17 Modified Comment lines in functions of xadcps
-* examples to recognize it as documentation block
-* for doxygen generation.
-* 2.3 mn 07/09/18 Fix Doxygen warning
-* 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors.
-* aad 12/17/20 Added missing function declarations and removed
-* functions with no definitions.
-*
-*
-*
-*****************************************************************************/
-#ifndef XADCPS_H /* Prevent circular inclusions */
-#define XADCPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xadcps_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**
- * @name Indexes for the different channels.
- * @{
- */
-#define XADCPS_CH_TEMP 0x0U /**< On Chip Temperature */
-#define XADCPS_CH_VCCINT 0x1U /**< VCCINT */
-#define XADCPS_CH_VCCAUX 0x2U /**< VCCAUX */
-#define XADCPS_CH_VPVN 0x3U /**< VP/VN Dedicated analog inputs */
-#define XADCPS_CH_VREFP 0x4U /**< VREFP */
-#define XADCPS_CH_VREFN 0x5U /**< VREFN */
-#define XADCPS_CH_VBRAM 0x6U /**< On-chip VBRAM Data Reg, 7 series */
-#define XADCPS_CH_SUPPLY_CALIB 0x07U /**< Supply Calib Data Reg */
-#define XADCPS_CH_ADC_CALIB 0x08U /**< ADC Offset Channel Reg */
-#define XADCPS_CH_GAINERR_CALIB 0x09U /**< Gain Error Channel Reg */
-#define XADCPS_CH_VCCPINT 0x0DU /**< On-chip PS VCCPINT Channel , Zynq */
-#define XADCPS_CH_VCCPAUX 0x0EU /**< On-chip PS VCCPAUX Channel , Zynq */
-#define XADCPS_CH_VCCPDRO 0x0FU /**< On-chip PS VCCPDRO Channel , Zynq */
-#define XADCPS_CH_AUX_MIN 16U /**< Channel number for 1st Aux Channel */
-#define XADCPS_CH_AUX_MAX 31U /**< Channel number for Last Aux channel */
-
-/*@}*/
-
-
-/**
- * @name Indexes for reading the Calibration Coefficient Data.
- * @{
- */
-#define XADCPS_CALIB_SUPPLY_COEFF 0U /**< Supply Offset Calib Coefficient */
-#define XADCPS_CALIB_ADC_COEFF 1U /**< ADC Offset Calib Coefficient */
-#define XADCPS_CALIB_GAIN_ERROR_COEFF 2U /**< Gain Error Calib Coefficient*/
-/*@}*/
-
-
-/**
- * @name Indexes for reading the Minimum/Maximum Measurement Data.
- * @{
- */
-#define XADCPS_MAX_TEMP 0U /**< Maximum Temperature Data */
-#define XADCPS_MAX_VCCINT 1U /**< Maximum VCCINT Data */
-#define XADCPS_MAX_VCCAUX 2U /**< Maximum VCCAUX Data */
-#define XADCPS_MAX_VBRAM 3U /**< Maximum VBRAM Data */
-#define XADCPS_MIN_TEMP 4U /**< Minimum Temperature Data */
-#define XADCPS_MIN_VCCINT 5U /**< Minimum VCCINT Data */
-#define XADCPS_MIN_VCCAUX 6U /**< Minimum VCCAUX Data */
-#define XADCPS_MIN_VBRAM 7U /**< Minimum VBRAM Data */
-#define XADCPS_MAX_VCCPINT 8U /**< Maximum VCCPINT Register , Zynq */
-#define XADCPS_MAX_VCCPAUX 9U /**< Maximum VCCPAUX Register , Zynq */
-#define XADCPS_MAX_VCCPDRO 0xAU /**< Maximum VCCPDRO Register , Zynq */
-#define XADCPS_MIN_VCCPINT 0xCU /**< Minimum VCCPINT Register , Zynq */
-#define XADCPS_MIN_VCCPAUX 0xDU /**< Minimum VCCPAUX Register , Zynq */
-#define XADCPS_MIN_VCCPDRO 0xEU /**< Minimum VCCPDRO Register , Zynq */
-
-/*@}*/
-
-
-/**
- * @name Alarm Threshold(Limit) Register (ATR) indexes.
- * @{
- */
-#define XADCPS_ATR_TEMP_UPPER 0U /**< High user Temperature */
-#define XADCPS_ATR_VCCINT_UPPER 1U /**< VCCINT high voltage limit register */
-#define XADCPS_ATR_VCCAUX_UPPER 2U /**< VCCAUX high voltage limit register */
-#define XADCPS_ATR_OT_UPPER 3U /**< VCCAUX high voltage limit register */
-#define XADCPS_ATR_TEMP_LOWER 4U /**< Upper Over Temperature limit Reg */
-#define XADCPS_ATR_VCCINT_LOWER 5U /**< VCCINT high voltage limit register */
-#define XADCPS_ATR_VCCAUX_LOWER 6U /**< VCCAUX low voltage limit register */
-#define XADCPS_ATR_OT_LOWER 7U /**< Lower Over Temperature limit */
-#define XADCPS_ATR_VBRAM_UPPER_ 8U /**< VRBAM Upper Alarm Reg, 7 Series */
-#define XADCPS_ATR_VCCPINT_UPPER 9U /**< VCCPINT Upper Alarm Reg, Zynq */
-#define XADCPS_ATR_VCCPAUX_UPPER 0xAU /**< VCCPAUX Upper Alarm Reg, Zynq */
-#define XADCPS_ATR_VCCPDRO_UPPER 0xBU /**< VCCPDRO Upper Alarm Reg, Zynq */
-#define XADCPS_ATR_VBRAM_LOWER 0xCU /**< VRBAM Lower Alarm Reg, 7 Series */
-#define XADCPS_ATR_VCCPINT_LOWER 0xDU /**< VCCPINT Lower Alarm Reg , Zynq */
-#define XADCPS_ATR_VCCPAUX_LOWER 0xEU /**< VCCPAUX Lower Alarm Reg , Zynq */
-#define XADCPS_ATR_VCCPDRO_LOWER 0xFU /**< VCCPDRO Lower Alarm Reg , Zynq */
-
-/*@}*/
-
-
-/**
- * @name Averaging to be done for the channels.
- * @{
- */
-#define XADCPS_AVG_0_SAMPLES 0U /**< No Averaging */
-#define XADCPS_AVG_16_SAMPLES 1U /**< Average 16 samples */
-#define XADCPS_AVG_64_SAMPLES 2U /**< Average 64 samples */
-#define XADCPS_AVG_256_SAMPLES 3U /**< Average 256 samples */
-
-/*@}*/
-
-
-/**
- * @name Channel Sequencer Modes of operation
- * @{
- */
-#define XADCPS_SEQ_MODE_SAFE 0U /**< Default Safe Mode */
-#define XADCPS_SEQ_MODE_ONEPASS 1U /**< Onepass through Sequencer */
-#define XADCPS_SEQ_MODE_CONTINPASS 2U /**< Continuous Cycling Sequencer */
-#define XADCPS_SEQ_MODE_SINGCHAN 3U /**< Single channel -No Sequencing */
-#define XADCPS_SEQ_MODE_SIMUL_SAMPLING 4U /**< Simultaneous sampling */
-#define XADCPS_SEQ_MODE_INDEPENDENT 8U /**< Independent mode */
-
-/*@}*/
-
-
-
-/**
- * @name Power Down Modes
- * @{
- */
-#define XADCPS_PD_MODE_NONE 0U /**< No Power Down */
-#define XADCPS_PD_MODE_ADCB 1U /**< Power Down ADC B */
-#define XADCPS_PD_MODE_XADC 2U /**< Power Down ADC A and ADC B */
-/*@}*/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the XADC/ADC
- * device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Device base address */
-} XAdcPs_Config;
-
-
-/**
- * The driver's instance data. The user is required to allocate a variable
- * of this type for every XADC/ADC device in the system. A pointer to
- * a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XAdcPs_Config Config; /**< XAdcPs_Config of current device */
- u32 IsReady; /**< Device is initialized and ready */
-
-} XAdcPs;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-*
-* This macro checks if the XADC device is in Event Sampling mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return
-* - TRUE if the device is in Event Sampling Mode.
-* - FALSE if the device is in Continuous Sampling Mode.
-*
-* @note C-Style signature:
-* int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);
-*
-*****************************************************************************/
-#define XAdcPs_IsEventSamplingModeSet(InstancePtr) \
- (((XAdcPs_ReadInternalReg(InstancePtr, \
- XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ? \
- TRUE : FALSE))
-
-
-/****************************************************************************/
-/**
-*
-* This macro checks if the XADC device is in External Mux mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return
-* - TRUE if the device is in External Mux Mode.
-* - FALSE if the device is NOT in External Mux Mode.
-*
-* @note C-Style signature:
-* int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);
-*
-*****************************************************************************/
-#define XAdcPs_IsExternalMuxModeSet(InstancePtr) \
- (((XAdcPs_ReadInternalReg(InstancePtr, \
- XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ? \
- TRUE : FALSE))
-
-/****************************************************************************/
-/**
-*
-* This macro converts XADC Raw Data to Temperature(centigrades).
-*
-* @param AdcData is the Raw ADC Data from XADC.
-*
-* @return The Temperature in centigrades.
-*
-* @note C-Style signature:
-* float XAdcPs_RawToTemperature(u32 AdcData);
-*
-*****************************************************************************/
-#define XAdcPs_RawToTemperature(AdcData) \
- ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
-
-/****************************************************************************/
-/**
-*
-* This macro converts XADC/ADC Raw Data to Voltage(volts).
-*
-* @param AdcData is the XADC/ADC Raw Data.
-*
-* @return The Voltage in volts.
-*
-* @note C-Style signature:
-* float XAdcPs_RawToVoltage(u32 AdcData);
-*
-*****************************************************************************/
-#define XAdcPs_RawToVoltage(AdcData) \
- ((((float)(AdcData))* (3.0f))/65536.0f)
-
-/****************************************************************************/
-/**
-*
-* This macro converts Temperature in centigrades to XADC/ADC Raw Data.
-*
-* @param Temperature is the Temperature in centigrades to be
-* converted to XADC/ADC Raw Data.
-*
-* @return The XADC/ADC Raw Data.
-*
-* @note C-Style signature:
-* int XAdcPs_TemperatureToRaw(float Temperature);
-*
-*****************************************************************************/
-#define XAdcPs_TemperatureToRaw(Temperature) \
- ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
-
-/****************************************************************************/
-/**
-*
-* This macro converts Voltage in Volts to XADC/ADC Raw Data.
-*
-* @param Voltage is the Voltage in volts to be converted to
-* XADC/ADC Raw Data.
-*
-* @return The XADC/ADC Raw Data.
-*
-* @note C-Style signature:
-* int XAdcPs_VoltageToRaw(float Voltage);
-*
-*****************************************************************************/
-#define XAdcPs_VoltageToRaw(Voltage) \
- ((int)((Voltage)*65536.0f/3.0f))
-
-
-/****************************************************************************/
-/**
-*
-* This macro is used for writing to the XADC Registers using the
-* command FIFO.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Data is the value to be written to XADC register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);
-*
-*****************************************************************************/
-#define XAdcPs_WriteFifo(InstancePtr, Data) \
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XADCPS_CMDFIFO_OFFSET, Data);
-
-
-/****************************************************************************/
-/**
-*
-* This macro is used for reading from the XADC Registers using the
-* data FIFO.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return Data read from the FIFO
-*
-* @note C-Style signature:
-* u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);
-*
-*****************************************************************************/
-#define XAdcPs_ReadFifo(InstancePtr) \
- XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XADCPS_RDFIFO_OFFSET);
-
-
-/************************** Function Prototypes *****************************/
-
-
-
-/**
- * Functions in xadcps_sinit.c
- */
-XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
-
-/**
- * Functions in xadcps.c
- */
-int XAdcPs_CfgInitialize(XAdcPs *InstancePtr,
- XAdcPs_Config *ConfigPtr,
- u32 EffectiveAddr);
-
-void XAdcPs_SetConfigRegister(XAdcPs *InstancePtr, u32 Data);
-u32 XAdcPs_GetConfigRegister(XAdcPs *InstancePtr);
-
-u32 XAdcPs_GetMiscStatus(XAdcPs *InstancePtr);
-
-void XAdcPs_SetMiscCtrlRegister(XAdcPs *InstancePtr, u32 Data);
-u32 XAdcPs_GetMiscCtrlRegister(XAdcPs *InstancePtr);
-
-void XAdcPs_Reset(XAdcPs *InstancePtr);
-
-u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel);
-
-u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType);
-
-u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType);
-
-void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average);
-u8 XAdcPs_GetAvg(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
- u8 Channel,
- int IncreaseAcqCycles,
- int IsEventMode,
- int IsDifferentialMode);
-
-
-void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask);
-u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr);
-
-void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration);
-u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr);
-
-void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode);
-u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr);
-
-void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor);
-u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask);
-u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask);
-u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask);
-u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask);
-u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr);
-
-void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value);
-u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg);
-
-void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr);
-void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr);
-
-void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode);
-
-int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr);
-
-void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel);
-
-void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode);
-
-u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr);
-
-/**
- * Functions in xadcps_selftest.c
- */
-int XAdcPs_SelfTest(XAdcPs *InstancePtr);
-
-/**
- * Functions in xadcps_intr.c
- */
-void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask);
-void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask);
-u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr);
-
-u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr);
-void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* End of protection macro. */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3e/502304545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3e/502304545243001d18b399c1eb9b3628
deleted file mode 100644
index 5050be5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3e/502304545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,117 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 666666687
-#define DDR_FREQ 533333374
-#define DCI_FREQ 10158730
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 125000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 100000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 111111115
-#define WDT_FREQ 111111115
-#define TTC_FREQ 50000000
-#define CAN_FREQ 10000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 50000000
-#define FPGA1_FREQ 10000000
-#define FPGA2_FREQ 10000000
-#define FPGA3_FREQ 10000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3e/50287d585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3e/50287d585243001d18b399c1eb9b3628
deleted file mode 100644
index 4978960..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3e/50287d585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,328 +0,0 @@
-/*******************************************************************************
-* Copyright (c) 2018 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-*******************************************************************************/
-
-
-#ifndef __XLPD_SLCR_SECURE_H__
-#define __XLPD_SLCR_SECURE_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *@cond nocomments
- */
-
-/**
- * XlpdSlcrSecure Base Address
- */
-#define XLPD_SLCR_SECURE_BASEADDR 0xFF510000UL
-
-/**
- * Register: XlpdSlcrSecureCtrl
- */
-#define XLPD_SLCR_SECURE_CTRL ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL )
-#define XLPD_SLCR_SECURE_CTRL_RSTVAL 0x00000000UL
-
-#define XLPD_SLCR_SECURE_CTRL_SLVERR_EN_SHIFT 0UL
-#define XLPD_SLCR_SECURE_CTRL_SLVERR_EN_WIDTH 1UL
-#define XLPD_SLCR_SECURE_CTRL_SLVERR_EN_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_CTRL_SLVERR_EN_DEFVAL 0x0UL
-
-/**
- * Register: XlpdSlcrSecureIsr
- */
-#define XLPD_SLCR_SECURE_ISR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL )
-#define XLPD_SLCR_SECURE_ISR_RSTVAL 0x00000000UL
-
-#define XLPD_SLCR_SECURE_ISR_ADDR_DECODE_ERR_SHIFT 0UL
-#define XLPD_SLCR_SECURE_ISR_ADDR_DECODE_ERR_WIDTH 1UL
-#define XLPD_SLCR_SECURE_ISR_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_ISR_ADDR_DECODE_ERR_DEFVAL 0x0UL
-
-/**
- * Register: XlpdSlcrSecureImr
- */
-#define XLPD_SLCR_SECURE_IMR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL )
-#define XLPD_SLCR_SECURE_IMR_RSTVAL 0x00000001UL
-
-#define XLPD_SLCR_SECURE_IMR_ADDR_DECODE_ERR_SHIFT 0UL
-#define XLPD_SLCR_SECURE_IMR_ADDR_DECODE_ERR_WIDTH 1UL
-#define XLPD_SLCR_SECURE_IMR_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_IMR_ADDR_DECODE_ERR_DEFVAL 0x1UL
-
-/**
- * Register: XlpdSlcrSecureIer
- */
-#define XLPD_SLCR_SECURE_IER ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL )
-#define XLPD_SLCR_SECURE_IER_RSTVAL 0x00000000UL
-
-#define XLPD_SLCR_SECURE_IER_ADDR_DECODE_ERR_SHIFT 0UL
-#define XLPD_SLCR_SECURE_IER_ADDR_DECODE_ERR_WIDTH 1UL
-#define XLPD_SLCR_SECURE_IER_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_IER_ADDR_DECODE_ERR_DEFVAL 0x0UL
-
-/**
- * Register: XlpdSlcrSecureIdr
- */
-#define XLPD_SLCR_SECURE_IDR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL )
-#define XLPD_SLCR_SECURE_IDR_RSTVAL 0x00000000UL
-
-#define XLPD_SLCR_SECURE_IDR_ADDR_DECODE_ERR_SHIFT 0UL
-#define XLPD_SLCR_SECURE_IDR_ADDR_DECODE_ERR_WIDTH 1UL
-#define XLPD_SLCR_SECURE_IDR_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_IDR_ADDR_DECODE_ERR_DEFVAL 0x0UL
-
-/**
- * Register: XlpdSlcrSecureItr
- */
-#define XLPD_SLCR_SECURE_ITR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL )
-#define XLPD_SLCR_SECURE_ITR_RSTVAL 0x00000000UL
-
-#define XLPD_SLCR_SECURE_ITR_ADDR_DECODE_ERR_SHIFT 0UL
-#define XLPD_SLCR_SECURE_ITR_ADDR_DECODE_ERR_WIDTH 1UL
-#define XLPD_SLCR_SECURE_ITR_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_ITR_ADDR_DECODE_ERR_DEFVAL 0x0UL
-
-/**
- * Register: XlpdSlcrSecureRpu0
- */
-#define XLPD_SLCR_SECURE_RPU0 ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL )
-#define XLPD_SLCR_SECURE_RPU0_RSTVAL 0x00000000UL
-
-#define XLPD_SLCR_SECURE_RPU0_TZ_SHIFT 0UL
-#define XLPD_SLCR_SECURE_RPU0_TZ_WIDTH 1UL
-#define XLPD_SLCR_SECURE_RPU0_TZ_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_RPU0_TZ_DEFVAL 0x0UL
-
-/**
- * Register: XlpdSlcrSecureRpu1
- */
-#define XLPD_SLCR_SECURE_RPU1 ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000024UL )
-#define XLPD_SLCR_SECURE_RPU1_RSTVAL 0x00000000UL
-
-#define XLPD_SLCR_SECURE_RPU1_TZ_SHIFT 0UL
-#define XLPD_SLCR_SECURE_RPU1_TZ_WIDTH 1UL
-#define XLPD_SLCR_SECURE_RPU1_TZ_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_RPU1_TZ_DEFVAL 0x0UL
-
-/**
- * Register: XlpdSlcrSecureXmpu
- */
-#define XLPD_SLCR_SECURE_XMPU ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000028UL )
-#define XLPD_SLCR_SECURE_XMPU_RSTVAL 0x00000000UL
-
-#define XLPD_SLCR_SECURE_XMPU_TZ_SHIFT 0UL
-#define XLPD_SLCR_SECURE_XMPU_TZ_WIDTH 1UL
-#define XLPD_SLCR_SECURE_XMPU_TZ_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_XMPU_TZ_DEFVAL 0x0UL
-
-/**
- * Register: XlpdSlcrSecureXppu
- */
-#define XLPD_SLCR_SECURE_XPPU ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x0000002CUL )
-#define XLPD_SLCR_SECURE_XPPU_RSTVAL 0x00000000UL
-
-#define XLPD_SLCR_SECURE_XPPU_TZ_SHIFT 0UL
-#define XLPD_SLCR_SECURE_XPPU_TZ_WIDTH 1UL
-#define XLPD_SLCR_SECURE_XPPU_TZ_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_XPPU_TZ_DEFVAL 0x0UL
-
-/**
- * Register: XlpdSlcrSecureSafetyChk
- */
-#define XLPD_SLCR_SECURE_SAFETY_CHK ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL )
-#define XLPD_SLCR_SECURE_SAFETY_CHK_RSTVAL 0x00000000UL
-
-#define XLPD_SLCR_SECURE_SAFETY_CHK_VAL_SHIFT 0UL
-#define XLPD_SLCR_SECURE_SAFETY_CHK_VAL_WIDTH 32UL
-#define XLPD_SLCR_SECURE_SAFETY_CHK_VAL_MASK 0xffffffffUL
-#define XLPD_SLCR_SECURE_SAFETY_CHK_VAL_DEFVAL 0x0UL
-
-/**
- * Register: XlpdSlcrSecureCpmPcsr
- */
-#define XLPD_SLCR_SECURE_CPM_PCSR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000038UL )
-#define XLPD_SLCR_SECURE_CPM_PCSR_RSTVAL 0x00000001UL
-
-#define XLPD_SLCR_SECURE_CPM_PCSR_TZ_SHIFT 0UL
-#define XLPD_SLCR_SECURE_CPM_PCSR_TZ_WIDTH 1UL
-#define XLPD_SLCR_SECURE_CPM_PCSR_TZ_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_CPM_PCSR_TZ_DEFVAL 0x1UL
-
-/**
- * Register: XlpdSlcrSecureIpi
- */
-#define XLPD_SLCR_SECURE_IPI ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000040UL )
-#define XLPD_SLCR_SECURE_IPI_RSTVAL 0x00000001UL
-
-#define XLPD_SLCR_SECURE_IPI_TZ_SHIFT 0UL
-#define XLPD_SLCR_SECURE_IPI_TZ_WIDTH 1UL
-#define XLPD_SLCR_SECURE_IPI_TZ_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_IPI_TZ_DEFVAL 0x1UL
-
-/**
- * Register: XlpdSlcrSecureCrl
- */
-#define XLPD_SLCR_SECURE_CRL ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000044UL )
-#define XLPD_SLCR_SECURE_CRL_RSTVAL 0x00000001UL
-
-#define XLPD_SLCR_SECURE_CRL_TZ_SHIFT 0UL
-#define XLPD_SLCR_SECURE_CRL_TZ_WIDTH 1UL
-#define XLPD_SLCR_SECURE_CRL_TZ_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_CRL_TZ_DEFVAL 0x1UL
-
-/**
- * Register: XlpdSlcrSecure
- */
-#define XLPD_SLCR_SECURE ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000048UL )
-#define XLPD_SLCR_SECURE_RSTVAL 0x00000003UL
-
-#define XLPD_SLCR_SECURE_INTLPD_TZ_SHIFT 1UL
-#define XLPD_SLCR_SECURE_INTLPD_TZ_WIDTH 1UL
-#define XLPD_SLCR_SECURE_INTLPD_TZ_MASK 0x00000002UL
-#define XLPD_SLCR_SECURE_INTLPD_TZ_DEFVAL 0x1UL
-
-#define XLPD_SLCR_SECURE_TZ_SHIFT 0UL
-#define XLPD_SLCR_SECURE_TZ_WIDTH 1UL
-#define XLPD_SLCR_SECURE_TZ_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_TZ_DEFVAL 0x1UL
-
-/**
- * Register: XlpdSlcrSecureHsdp
- */
-#define XLPD_SLCR_SECURE_HSDP ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x0000004CUL )
-#define XLPD_SLCR_SECURE_HSDP_RSTVAL 0x00000007UL
-
-#define XLPD_SLCR_SECURE_HSDP_TZ_SHIFT 1UL
-#define XLPD_SLCR_SECURE_HSDP_TZ_WIDTH 1UL
-#define XLPD_SLCR_SECURE_HSDP_TZ_MASK 0x00000002UL
-#define XLPD_SLCR_SECURE_HSDP_TZ_DEFVAL 0x1UL
-
-#define XLPD_SLCR_SECURE_HSDP_APB_TZ_SHIFT 0UL
-#define XLPD_SLCR_SECURE_HSDP_APB_TZ_WIDTH 1UL
-#define XLPD_SLCR_SECURE_HSDP_APB_TZ_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_HSDP_APB_TZ_DEFVAL 0x1UL
-
-/**
- * Register: XlpdSlcrSecureAfi
- */
-#define XLPD_SLCR_SECURE_AFI ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000050UL )
-#define XLPD_SLCR_SECURE_AFI_RSTVAL 0x00000001UL
-
-#define XLPD_SLCR_SECURE_AFI_FM_TZ_SHIFT 0UL
-#define XLPD_SLCR_SECURE_AFI_FM_TZ_WIDTH 1UL
-#define XLPD_SLCR_SECURE_AFI_FM_TZ_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_AFI_FM_TZ_DEFVAL 0x1UL
-
-/**
- * Register: XlpdSlcrSecurePsm
- */
-#define XLPD_SLCR_SECURE_PSM ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000054UL )
-#define XLPD_SLCR_SECURE_PSM_RSTVAL 0x00000000UL
-
-#define XLPD_SLCR_SECURE_PSM_TZ_SHIFT 0UL
-#define XLPD_SLCR_SECURE_PSM_TZ_WIDTH 1UL
-#define XLPD_SLCR_SECURE_PSM_TZ_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_PSM_TZ_DEFVAL 0x0UL
-
-/**
- * Register: XlpdSlcrSecureAdma0
- */
-#define XLPD_SLCR_SECURE_ADMA0 ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000060UL )
-#define XLPD_SLCR_SECURE_ADMA0_RSTVAL 0x00000000UL
-
-#define XLPD_SLCR_SECURE_ADMA0_TZ_SHIFT 0UL
-#define XLPD_SLCR_SECURE_ADMA0_TZ_WIDTH 1UL
-#define XLPD_SLCR_SECURE_ADMA0_TZ_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_ADMA0_TZ_DEFVAL 0x0UL
-
-/**
- * Register: XlpdSlcrSecureAdma1
- */
-#define XLPD_SLCR_SECURE_ADMA1 ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000064UL )
-#define XLPD_SLCR_SECURE_ADMA1_RSTVAL 0x00000000UL
-
-#define XLPD_SLCR_SECURE_ADMA1_TZ_SHIFT 0UL
-#define XLPD_SLCR_SECURE_ADMA1_TZ_WIDTH 1UL
-#define XLPD_SLCR_SECURE_ADMA1_TZ_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_ADMA1_TZ_DEFVAL 0x0UL
-
-/**
- * Register: XlpdSlcrSecureAdma2
- */
-#define XLPD_SLCR_SECURE_ADMA2 ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000068UL )
-#define XLPD_SLCR_SECURE_ADMA2_RSTVAL 0x00000000UL
-
-#define XLPD_SLCR_SECURE_ADMA2_TZ_SHIFT 0UL
-#define XLPD_SLCR_SECURE_ADMA2_TZ_WIDTH 1UL
-#define XLPD_SLCR_SECURE_ADMA2_TZ_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_ADMA2_TZ_DEFVAL 0x0UL
-
-/**
- * Register: XlpdSlcrSecureAdma3
- */
-#define XLPD_SLCR_SECURE_ADMA3 ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x0000006CUL )
-#define XLPD_SLCR_SECURE_ADMA3_RSTVAL 0x00000000UL
-
-#define XLPD_SLCR_SECURE_ADMA3_TZ_SHIFT 0UL
-#define XLPD_SLCR_SECURE_ADMA3_TZ_WIDTH 1UL
-#define XLPD_SLCR_SECURE_ADMA3_TZ_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_ADMA3_TZ_DEFVAL 0x0UL
-
-/**
- * Register: XlpdSlcrSecureAdma4
- */
-#define XLPD_SLCR_SECURE_ADMA4 ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000070UL )
-#define XLPD_SLCR_SECURE_ADMA4_RSTVAL 0x00000000UL
-
-#define XLPD_SLCR_SECURE_ADMA4_TZ_SHIFT 0UL
-#define XLPD_SLCR_SECURE_ADMA4_TZ_WIDTH 1UL
-#define XLPD_SLCR_SECURE_ADMA4_TZ_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_ADMA4_TZ_DEFVAL 0x0UL
-
-/**
- * Register: XlpdSlcrSecureAdma5
- */
-#define XLPD_SLCR_SECURE_ADMA5 ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000074UL )
-#define XLPD_SLCR_SECURE_ADMA5_RSTVAL 0x00000000UL
-
-#define XLPD_SLCR_SECURE_ADMA5_TZ_SHIFT 0UL
-#define XLPD_SLCR_SECURE_ADMA5_TZ_WIDTH 1UL
-#define XLPD_SLCR_SECURE_ADMA5_TZ_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_ADMA5_TZ_DEFVAL 0x0UL
-
-/**
- * Register: XlpdSlcrSecureAdma6
- */
-#define XLPD_SLCR_SECURE_ADMA6 ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000078UL )
-#define XLPD_SLCR_SECURE_ADMA6_RSTVAL 0x00000000UL
-
-#define XLPD_SLCR_SECURE_ADMA6_TZ_SHIFT 0UL
-#define XLPD_SLCR_SECURE_ADMA6_TZ_WIDTH 1UL
-#define XLPD_SLCR_SECURE_ADMA6_TZ_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_ADMA6_TZ_DEFVAL 0x0UL
-
-/**
- * Register: XlpdSlcrSecureAdma7
- */
-#define XLPD_SLCR_SECURE_ADMA7 ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x0000007CUL )
-#define XLPD_SLCR_SECURE_ADMA7_RSTVAL 0x00000000UL
-
-#define XLPD_SLCR_SECURE_ADMA7_TZ_SHIFT 0UL
-#define XLPD_SLCR_SECURE_ADMA7_TZ_WIDTH 1UL
-#define XLPD_SLCR_SECURE_ADMA7_TZ_MASK 0x00000001UL
-#define XLPD_SLCR_SECURE_ADMA7_TZ_DEFVAL 0x0UL
-
-/**
- *@endcond
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XLPD_SLCR_SECURE_H__ */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3e/804e1c595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3e/804e1c595243001d18b399c1eb9b3628
deleted file mode 100644
index 368a2db..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3e/804e1c595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,108 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file usleep.c
-*
-* This function supports user configurable sleep implementation.
-* This provides a microsecond delay using the timer specified by the user in
-* the ARM Cortex R5 MP core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 02/20/14 First release
-* 5.04 pkp 02/19/16 usleep routine is modified to use TTC3 if present
-* else it will use set of assembly instructions to
-* provide the required delay
-* 5.04 pkp 03/09/16 Assembly routine for usleep is modified to avoid
-* disabling the interrupt
-* 5.04 pkp 03/11/16 Compare the counter value to previously read value
-* to detect the overflow for TTC3
-* 6.0 asa 08/15/16 Updated the usleep signature. Fix for CR#956899.
-* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
-* implementation. Now sleep routines will use TTC
-* instance specified by user.
-* 7.2 mus 01/29/20 Updated sleep routines to use CortexR5 PMU for delay
-* generation, in case TTC3/TTC2 instances are not
-* present in HW design. If user dont want to use PMU
-* counter for sleep routines, BSP needs to be compiled
-* with "DONT_USE_PMU_FOR_SLEEP_ROUTINES" flag. It fixes
-* CR#1051591.
-*
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "sleep.h"
-#include "xtime_l.h"
-#include "xparameters.h"
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#include "xreg_cortexr5.h"
-#include "xpm_counter.h"
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#include "xil_sleeptimer.h"
-#endif
-
-/*****************************************************************************/
-/**
-*
-* This API gives a delay in microseconds
-*
-* @param useconds requested
-*
-* @return 0 always
-*
-* @note By default, usleep is implemented using TTC3. Although user is
-* given an option to select other instances of TTC. When the user
-* selects other instances of TTC, usleep is implemented by that
-* specific TTC instance. If the user didn't select any other instance
-* of TTC specifically and when TTC3 is absent, usleep is implemented
-* using assembly instructions which is tested with instruction and
-* data caches enabled and it gives proper delay. It may give more
-* delay than exepcted when caches are disabled. If interrupt comes
-* when usleep using assembly instruction is being executed, the delay
-* may be greater than what is expected since once the interrupt is
-* served count resumes from where it was interrupted unlike the case
-* of TTC3 where counter keeps running while interrupt is being served.
-*
-****************************************************************************/
-
-int usleep_R5(unsigned long useconds)
-{
-#if defined (SLEEP_TIMER_BASEADDR)
- Xil_SleepTTCCommon(useconds, COUNTS_PER_USECOND);
-#elif !defined (DONT_USE_PMU_FOR_SLEEP_ROUTINES)
- Xpm_SleepPerfCounter(useconds, COUNTS_PER_USECOND);
-#else
-#if defined (__GNUC__)
- __asm__ __volatile__ (
-#elif defined (__ICCARM__)
- __asm volatile (
-#endif
- "push {r0,r1,r3} \n"
- "mov r0, %[usec] \n"
- "mov r1, %[iter] \n"
- "1: \n"
- "mov r3, r1 \n"
- "2: \n"
- "subs r3, r3, #0x1\n"
- "bne 2b \n"
- "subs r0, r0, #0x1 \n"
- "bne 1b \n"
- "pop {r0,r1,r3} \n"
- ::[iter] "r" (ITERS_PER_USEC), [usec] "r" (useconds)
- );
-#endif
-
-return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3e/81af15545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3e/81af15545243001d18b399c1eb9b3628
deleted file mode 100644
index 6f009c6..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3e/81af15545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,24 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 2021.2
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2022 Xilinx, Inc. All Rights Reserved.
-* SPDX-License-Identifier: MIT
-
-*
-* Description: Configurations for Standalone BSP
-*
-*******************************************************************/
-
-#ifndef BSPCONFIG_H /* prevent circular inclusions */
-#define BSPCONFIG_H /* by using protection macros */
-
-#define MICROBLAZE_PVR_NONE
-
-/* Definition for hard-float ABI */
-#define FPU_HARD_FLOAT_ABI_ENABLED 1
-
-#endif /*end of __BSPCONFIG_H_*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3e/d2c2bb595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3e/d2c2bb595243001d18b399c1eb9b3628
deleted file mode 100644
index d1bd537..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3e/d2c2bb595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,320 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xparameters_ps.h
-*
-* This file contains the address definitions for the hard peripherals
-* attached to the ARM Cortex A9 core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 1.00a ecm/sdm 02/01/10 Initial version
-* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
-* driver tcl
-* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
-* 6.6 srm 10/18/17 Added ARMA9 macro to identify CortexA9
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 02/04/02 First release
-* 2.00a jhl 12/16/02 Update for dual channel and interrupt support
-* 2.11a mta 03/21/07 Updated to new coding style
-* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the macros
-* XGpio_mWriteReg to XGpio_WriteReg, and XGpio_mReadReg
-* to XGpio_ReadReg.
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xgpio.h"
-#include "xgpio_i.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-
-/****************************************************************************/
-/**
-* Set output discrete(s) to logic 1 for the specified GPIO channel.
-*
-* @param InstancePtr is a pointer to an XGpio instance to be worked on.
-* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
-* @param Mask is the set of bits that will be set to 1 in the discrete
-* data register. All other bits in the data register are
-* unaffected.
-*
-* @return None.
-*
-* @note
-*
-* The hardware must be built for dual channels if this function is used
-* with any channel other than 1. If it is not, this function will assert.
-*
-* This API can only be used if the GPIO_IO ports in the IP are used for
-* connecting to the external output ports.
-*
-*****************************************************************************/
-void XGpio_DiscreteSet(XGpio * InstancePtr, unsigned Channel, u32 Mask)
-{
- u32 Current;
- unsigned DataOffset;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((Channel == 1) ||
- ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
-
- /* Calculate the offset to the data register of the GPIO */
- DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET;
-
- /*
- * Read the contents of the data register, merge in Mask and write
- * back results
- */
- Current = XGpio_ReadReg(InstancePtr->BaseAddress, DataOffset);
- Current |= Mask;
- XGpio_WriteReg(InstancePtr->BaseAddress, DataOffset, Current);
-}
-
-
-/****************************************************************************/
-/**
-* Set output discrete(s) to logic 0 for the specified GPIO channel.
-*
-* @param InstancePtr is a pointer to an XGpio instance to be worked on.
-* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
-* @param Mask is the set of bits that will be set to 0 in the discrete
-* data register. All other bits in the data register are
-* unaffected.
-*
-* @return None.
-*
-* @note
-*
-* The hardware must be built for dual channels if this function is used
-* with any channel other than 1. If it is not, this function will assert.
-*
-* This API can only be used if the GPIO_IO ports in the IP are used for
-* connecting to the external output ports.
-*
-*****************************************************************************/
-void XGpio_DiscreteClear(XGpio * InstancePtr, unsigned Channel, u32 Mask)
-{
- u32 Current;
- unsigned DataOffset;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((Channel == 1) ||
- ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
-
- /* Calculate the offset to the data register of the GPIO */
- DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET;
-
- /*
- * Read the contents of the data register, merge in Mask and write
- * back results
- */
- Current = XGpio_ReadReg(InstancePtr->BaseAddress, DataOffset);
- Current &= ~Mask;
- XGpio_WriteReg(InstancePtr->BaseAddress, DataOffset, Current);
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3f/403abe565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3f/403abe565243001d18b399c1eb9b3628
deleted file mode 100644
index b80c577..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3f/403abe565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,281 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#ifndef PROFILE_TIMER_HW_H
-#define PROFILE_TIMER_HW_H
-
-#include "profile.h"
-
-#ifdef PROC_PPC
-#if defined __GNUC__
-# define SYNCHRONIZE_IO __asm__ volatile ("eieio")
-#elif defined __DCC__
-# define SYNCHRONIZE_IO __asm volatile(" eieio")
-#else
-# define SYNCHRONIZE_IO
-#endif
-#endif
-
-#ifdef PROC_PPC
-#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
-#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
-#else
-#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
-#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
-#endif
-
-#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
- ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \
- (u32)(RegOffset)), (u32)(ValueToWrite))
-
-#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
- ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
-
-#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
- ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (RegisterValue))
-
-#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \
- ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
-
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef PROC_PPC
-#include "xexception_l.h"
-#include "xtime_l.h"
-#include "xpseudo_asm.h"
-#endif
-
-#ifdef TIMER_CONNECT_INTC
-#include "xintc_l.h"
-#include "xintc.h"
-#endif /* TIMER_CONNECT_INTC */
-
-#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
-#include "xtmrctr_l.h"
-#endif
-
-#ifdef PROC_CORTEXA9
-#include "xscutimer_hw.h"
-#include "xscugic.h"
-#endif
-
-extern u32 timer_clk_ticks ;
-
-/*--------------------------------------------------------------------
- * PowerPC Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_PPC
-
-#ifdef PPC_PIT_INTERRUPT
-u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */
-#endif
-
-#ifdef PROC_PPC440
-#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
-#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
-#define XREG_SPR_PIT XREG_SPR_DEC
-#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
-#endif
-
-/* --------------------------------------------------------------------
- * Disable the Timer - During Profiling
- *
- * For PIT Timer -
- * 1. XTime_PITDisableInterrupt() ;
- * 2. Store the remaining timer clk tick
- * 3. Stop the PIT Timer
- *-------------------------------------------------------------------- */
-
-#ifdef PPC_PIT_INTERRUPT
-#define disable_timer() \
- { \
- u32 val; \
- val=mfspr(XREG_SPR_TCR); \
- mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \
- timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
- mtspr(XREG_SPR_PIT, 0); \
- }
-#else
-#define disable_timer() \
- { \
- u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(addr); \
- tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
- ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
- }
-#endif
-
-
-
-/* --------------------------------------------------------------------
- * Enable the Timer
- *
- * For PIT Timer -
- * 1. Load the remaining timer clk ticks
- * 2. XTime_PITEnableInterrupt() ;
- *-------------------------------------------------------------------- */
-#ifdef PPC_PIT_INTERRUPT
-#define enable_timer() \
- { \
- u32 val; \
- val=mfspr(XREG_SPR_TCR); \
- mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
- mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
- }
-#else
-#define enable_timer() \
- { \
- u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(addr); \
- tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
- ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
- }
-#endif
-
-
-
-/* --------------------------------------------------------------------
- * Send Ack to Timer Interrupt
- *
- * For PIT Timer -
- * 1. Load the timer clk ticks
- * 2. Enable AutoReload and Interrupt
- * 3. Clear PIT Timer Status bits
- *-------------------------------------------------------------------- */
-#ifdef PPC_PIT_INTERRUPT
-#define timer_ack() \
- { \
- u32 val; \
- mtspr(XREG_SPR_PIT, timer_clk_ticks); \
- mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
- val=mfspr(XREG_SPR_TCR); \
- mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
- }
-#else
-#define timer_ack() \
- { \
- u32 csr; \
- csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
- ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
- }
-#endif
-
-/*-------------------------------------------------------------------- */
-#endif /* PROC_PPC */
-/* -------------------------------------------------------------------- */
-
-
-
-
-/* --------------------------------------------------------------------
- * MicroBlaze Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_MICROBLAZE
-
-/* --------------------------------------------------------------------
- * Disable the Timer during Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define disable_timer() \
- { \
- u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
- Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
- Addr += (u32)XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(Addr); \
- tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
- u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
- OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
- OutAddr += (u32)XTC_TCSR_OFFSET; \
- ProfIo_Out32(OutAddr, (u32)tmp_v); \
- }
-
-
-/* --------------------------------------------------------------------
- * Enable the Timer after Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define enable_timer() \
- { \
- u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
- Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
- Addr += (u32)XTC_TCSR_OFFSET; \
- u32 tmp_v = (u32)ProfIo_In32(Addr); \
- tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \
- ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
- }
-
-
-/* --------------------------------------------------------------------
- * Send Ack to Timer Interrupt
- *
- *-------------------------------------------------------------------- */
-#define timer_ack() \
- { \
- u32 csr; \
- csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \
- ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \
- }
-
-/*-------------------------------------------------------------------- */
-#endif /* PROC_MICROBLAZE */
-/*-------------------------------------------------------------------- */
-
-/* --------------------------------------------------------------------
- * Cortex A9 Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_CORTEXA9
-
-/* --------------------------------------------------------------------
- * Disable the Timer during Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define disable_timer() \
-{ \
- u32 Reg; \
- Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
- Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
- Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
-}
-
-
-/* --------------------------------------------------------------------
- * Enable the Timer after Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define enable_timer() \
-{ \
- u32 Reg; \
- Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
- Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
- Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
-}
-
-
-/* --------------------------------------------------------------------
- * Send Ack to Timer Interrupt
- *
- *-------------------------------------------------------------------- */
-#define timer_ack() \
-{ \
- Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
- (u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
-}
-
-/*-------------------------------------------------------------------- */
-#endif /* PROC_CORTEXA9 */
-/*-------------------------------------------------------------------- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3f/4105b2565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3f/4105b2565243001d18b399c1eb9b3628
deleted file mode 100644
index 571acd9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3f/4105b2565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,112 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_exception.h
-*
-* @addtogroup microblaze_exception_apis Microblaze Exception APIs
-* @{
-*
-* The xil_exception.h file, available in the /src/microblaze folder,
-* contains Microblaze specific exception related APIs and macros. Application programs
-* can use these APIs for various exception related operations. For example, enable exception,
-* disable exception, register exception hander.
-*
-* @note To use exception related functions, xil_exception.h must be added in source code
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00 hbm 07/28/09 Initial release
-*
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
-#define XIL_EXCEPTION_H /* by using protection macros */
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/*
- * These constants are specific to Microblaze processor.
- */
-
-#define XIL_EXCEPTION_ID_FIRST 0U
-#define XIL_EXCEPTION_ID_FSL 0U
-#define XIL_EXCEPTION_ID_UNALIGNED_ACCESS 1U
-#define XIL_EXCEPTION_ID_ILLEGAL_OPCODE 2U
-#define XIL_EXCEPTION_ID_M_AXI_I_EXCEPTION 3U
-#define XIL_EXCEPTION_ID_IPLB_EXCEPTION 3U
-#define XIL_EXCEPTION_ID_M_AXI_D_EXCEPTION 4U
-#define XIL_EXCEPTION_ID_DPLB_EXCEPTION 4U
-#define XIL_EXCEPTION_ID_DIV_BY_ZERO 5U
-#define XIL_EXCEPTION_ID_FPU 6U
-#define XIL_EXCEPTION_ID_STACK_VIOLATION 7U
-#define XIL_EXCEPTION_ID_MMU 7U
-#define XIL_EXCEPTION_ID_LAST XIL_EXCEPTION_ID_MMU
-
-/*
- * XIL_EXCEPTION_ID_INT is defined for all processors, but with different value.
- */
-#define XIL_EXCEPTION_ID_INT 16U /**
- * exception ID for interrupt
- */
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef is the exception handler function.
- */
-typedef void (*Xil_ExceptionHandler)(void *Data);
-
-/**
- * This data type defines an interrupt handler for a device.
- * The argument points to the instance of the component
- */
-typedef void (*XInterruptHandler) (void *InstancePtr);
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-extern void Xil_ExceptionRegisterHandler(u32 Id,
- Xil_ExceptionHandler Handler,
- void *Data);
-
-extern void Xil_ExceptionRemoveHandler(u32 Id);
-
-extern void Xil_ExceptionInit(void);
-extern void Xil_ExceptionEnable(void);
-extern void Xil_ExceptionDisable(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-/**
- *@endcond
- */
-
-/**
-* @} End of "addtogroup microblaze_exception_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3f/414821545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3f/414821545243001d18b399c1eb9b3628
deleted file mode 100644
index a8544b3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3f/414821545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,40 +0,0 @@
-/*******************************************************************************
-* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-*******************************************************************************/
-
-/******************************************************************************/
-/**
- *
- * @file xddrps.h
- * @addtogroup ddrps_v1_2
- * @{
- * @details
- *
- * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps
- * IP core.
- *
- * @note None.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.0 nsk 08/06/15 First Release
- * 1.0 nsk 08/20/15 Updated define_addr_params in ddrps.tcl
- * to support PBD Designs (CR #876857)
- *
- *
- *
-*******************************************************************************/
-
-#ifndef XDDRPS_H_
-/* Prevent circular inclusions by using protection macros. */
-#define XDDRPS_H_
-
-/******************************* Include Files ********************************/
-
-
-#endif /* XDDRPS_H_ */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3f/a0edd0585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3f/a0edd0585243001d18b399c1eb9b3628
deleted file mode 100644
index 3972482..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/3f/a0edd0585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,15 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#include "xil_types.h"
-/* Stub for iserror() function */
-__weak s32 _sys_iserror(s32 status)
-{
- if(status<0) {
- return 1;
- }
-
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4/017b9c595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4/017b9c595243001d18b399c1eb9b3628
deleted file mode 100644
index 50df3c5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4/017b9c595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,128 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_clocking.c
-*
-* The xil_clocking.c file contains clocking related functions and macros.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 7.2 sd 02/06/20 First release of clocking
-* 7.2 sd 03/20/20 Added checking for isolation case
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00 pkp 02/10/14 First release
-* 5.04 pkp 12/18/15 Initialized global constructor for C++ applications
-* 5.04 pkp 02/19/16 Added timer configuration using XTime_StartTimer API when
-* TTC3 is present
-* 6.4 asa 08/16/17 Added call to Xil_InitializeExistingMPURegConfig to
-* initialize the MPU configuration table with the MPU
-* configurations already set in Init_Mpu function.
-* 6.6 srm 10/18/17 Updated the timer configuration with XTime_StartTTCTimer.
-* Now the timer instance as specified by the user will be
-* started.
-* 7.2 mus 10/22/19 Defined RPU_TZ_MASK as #define instead of variable.
-* 7.2 sd 03/20/20 Add clocking support.
-*
-*
-******************************************************************************/
-#include "xparameters.h"
-#include "bspconfig.h"
- .file "xil-crt0.S"
- .section ".got2","aw"
- .align 2
-/*
- * 0th bit of PROCESSOR_ACCESS_VALUE macro signifies trustzone
- * setting for RPU address space
- */
-#define RPU_TZ_MASK 0x1
- .text
-.Lsbss_start:
- .long __sbss_start
-
-.Lsbss_end:
- .long __sbss_end
-
-.Lbss_start:
- .long __bss_start__
-
-.Lbss_end:
- .long __bss_end__
-
-.Lstack:
- .long __stack
-
-.set RPU_0_PWRCTL, 0xFF9A0108
-.set RPU_1_PWRCTL, 0xFF9A0208
-.set MPIDR_AFF0, 0xFF
-.set PWRCTL_MASK, 0x1
-
- .globl _startup
-
-_startup:
- bl __cpu_init /* Initialize the CPU first (BSP provides this) */
-#if (PROCESSOR_ACCESS_VALUE & RPU_TZ_MASK)
- mrc p15, 0, r0, c0, c0, 5 /* Read MPIDR register */
- ands r0, r0, #MPIDR_AFF0 /* Get affinity level 0 */
- bne core1
- ldr r10, =RPU_0_PWRCTL /* Load PWRCTRL address for core 0 */
- b test_boot_status
-
-core1:
- ldr r10, =RPU_1_PWRCTL /* Load PWRCTRL address for core 1 */
-
-test_boot_status:
- ldr r11, [r10] /* Read PWRCTRL register */
- ands r11, r11, #PWRCTL_MASK /* Extract and test core's PWRCTRL */
-
- /* if warm reset, skip the clearing of BSS and SBSS */
- bne .Lenclbss
-#endif
- mov r0, #0
-
- /* clear sbss */
- ldr r1,.Lsbss_start /* calculate beginning of the SBSS */
- ldr r2,.Lsbss_end /* calculate end of the SBSS */
-
-.Lloop_sbss:
- cmp r1,r2
- bge .Lenclsbss /* If no SBSS, no clearing required */
- str r0, [r1], #4
- b .Lloop_sbss
-
-.Lenclsbss:
- /* clear bss */
- ldr r1,.Lbss_start /* calculate beginning of the BSS */
- ldr r2,.Lbss_end /* calculate end of the BSS */
-
-.Lloop_bss:
- cmp r1,r2
- bge .Lenclbss /* If no BSS, no clearing required */
- str r0, [r1], #4
- b .Lloop_bss
-
-.Lenclbss:
-
- /* set stack pointer */
- ldr r13,.Lstack /* stack address */
-
- /* configure the timer if TTC is present */
-#ifdef SLEEP_TIMER_BASEADDR
- bl XTime_StartTTCTimer
-#endif
- bl Xil_InitializeExistingMPURegConfig /* Initialize MPU config */
- /* run global constructors */
- bl __libc_init_array
-
- /* make sure argc and argv are valid */
- mov r0, #0
- mov r1, #0
-
-#ifdef XCLOCKING
- bl Xil_ClockInit
-#endif
- bl main /* Jump to main C code */
-
- /* Cleanup global constructors */
- bl __libc_fini_array
-
- bl exit
-
-.Lexit: /* should never get here */
- b .Lexit
-
-.Lstart:
- .size _startup,.Lstart-_startup
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4/5019d6545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4/5019d6545243001d18b399c1eb9b3628
deleted file mode 100644
index ab10094..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4/5019d6545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,92 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xscugic_selftest.c
-* @addtogroup scugic_v4_6
-* @{
-*
-* Contains diagnostic self-test functions for the XScuGic driver.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a drg 01/19/10 First release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.10 mus 07/17/18 Updated file to fix the various coding style issues
-* reported by checkpatch. It fixes CR#1006344.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xscugic.h"
-
-/************************** Constant Definitions *****************************/
-
-#define XSCUGIC_PCELL_ID 0xB105F00DU
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-*
-* Run a self-test on the driver/device. This test reads the ID registers and
-* compares them.
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-*
-* @return
-*
-* -XST_SUCCESS if self-test is successful.
-* -XST_FAILURE if the self-test is not successful.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XScuGic_SelfTest(XScuGic *InstancePtr)
-{
- u32 RegValue1 = 0U;
- u32 Index;
- s32 Status;
-
- /*
- * Assert the arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the ID registers.
- */
- for (Index = 0U; Index <= 3U; Index++) {
- RegValue1 |= XScuGic_DistReadReg(InstancePtr,
- ((u32)XSCUGIC_PCELLID_OFFSET + (Index * 4U))) <<
- (Index * 8U);
- }
-
- if (XSCUGIC_PCELL_ID != RegValue1) {
- Status = XST_FAILURE;
- } else {
- Status = XST_SUCCESS;
- }
- return Status;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4/50c046565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4/50c046565243001d18b399c1eb9b3628
deleted file mode 100644
index 811d2b0..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4/50c046565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,23 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#ifndef UNDEFINE_FILE_OPS
-#include "xil_types.h"
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) s32 _close(s32 fd);
-}
-#endif
-
-/*
- * close -- We don't need to do anything, but pretend we did.
- */
-
-__attribute__((weak)) s32 _close(s32 fd)
-{
- (void)fd;
- return (0);
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4/523cd9565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4/523cd9565243001d18b399c1eb9b3628
deleted file mode 100644
index 69567bd..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4/523cd9565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,336 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xil_exception.c
-*
-* This file contains low-level driver functions for the Cortex A53,A9,R5 exception
-* Handler.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 6.0 mus 27/07/16 Consolidated exceptions for a53,a9 and r5
-* processors and added Xil_UndefinedExceptionHandler
-* for a53 32 bit and r5 as well.
-* 6.4 mus 08/06/17 Updated debug prints to replace %x with the %lx, to
-* fix the warnings.
-* 6.7 mna 26/04/18 Add an API to obtain a corresponding
-* Xil_ExceptionHandler entry from XExc_VectorTable.
-* 6.7 asa 18/05/18 Fix bugs in the API Xil_GetExceptionRegisterHandler.
-* 7.0 mus 07/03/19 Tweak Xil_ExceptionRegisterHandler and
-* Xil_GetExceptionRegisterHandler to support legacy
-* examples for Cortexa72 EL3 exception level.
-* 7.3 mus 07/27/20 Updated Xil_ExceptionRegisterHandler and
-* Xil_GetExceptionRegisterHandler to ignore
-* Exception_id, only if its pointing to IRQ.
-* It fixes CR#1069524
-*
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_exception.h"
-#include "xpseudo_asm.h"
-#include "xdebug.h"
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-typedef struct {
- Xil_ExceptionHandler Handler;
- void *Data;
-} XExc_VectorTableEntry;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Function Prototypes *****************************/
-static void Xil_ExceptionNullHandler(void *Data);
-/************************** Variable Definitions *****************************/
-/*
- * Exception vector table to store handlers for each exception vector.
- */
-#if defined (__aarch64__)
-XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
-{
- {Xil_ExceptionNullHandler, NULL},
- {Xil_SyncAbortHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
- {Xil_SErrorAbortHandler, NULL},
-
-};
-#else
-XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
-{
- {Xil_ExceptionNullHandler, NULL},
- {Xil_UndefinedExceptionHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
- {Xil_PrefetchAbortHandler, NULL},
- {Xil_DataAbortHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
-};
-#endif
-#if !defined (__aarch64__)
-u32 DataAbortAddr; /* Address of instruction causing data abort */
-u32 PrefetchAbortAddr; /* Address of instruction causing prefetch abort */
-u32 UndefinedExceptionAddr; /* Address of instruction causing Undefined
- exception */
-#endif
-
-/*****************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* This function is a stub Handler that is the default Handler that gets called
-* if the application has not setup a Handler for a specific exception. The
-* function interface has to match the interface specified for a Handler even
-* though none of the arguments are used.
-*
-* @param Data is unused by this function.
-*
-* @return None.
-*
-*****************************************************************************/
-static void Xil_ExceptionNullHandler(void *Data)
-{
- (void) Data;
-DieLoop: goto DieLoop;
-}
-
-/****************************************************************************/
-/**
-* @brief The function is a common API used to initialize exception handlers
-* across all supported arm processors. For ARM Cortex-A53, Cortex-R5,
-* and Cortex-A9, the exception handlers are being initialized
-* statically and this function does not do anything.
-* However, it is still present to take care of backward compatibility
-* issues (in earlier versions of BSPs, this API was being used to
-* initialize exception handlers).
-*
-* @return None.
-*
-*****************************************************************************/
-void Xil_ExceptionInit(void)
-{
- return;
-}
-
-/*****************************************************************************/
-/**
-* @brief Register a handler for a specific exception. This handler is being
-* called when the processor encounters the specified exception.
-*
-* @param Exception_id contains the ID of the exception source and should
-* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
-* See xil_exception.h for further information.
-* @param Handler to the Handler for that exception.
-* @param Data is a reference to Data that will be passed to the
-* Handler when it gets called.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler Handler,
- void *Data)
-{
-#if defined (versal) && !defined(ARMR5) && EL3
- if ( XIL_EXCEPTION_ID_IRQ_INT == Exception_id )
- {
- /*
- * Cortexa72 processor in versal is coupled with GIC-500, and
- * GIC-500 supports only FIQ at EL3. Hence, tweaking this API
- * to act on IRQ, if Exception_id is pointing to IRQ
- */
- Exception_id = XIL_EXCEPTION_ID_FIQ_INT;
- }
-#endif
- XExc_VectorTable[Exception_id].Handler = Handler;
- XExc_VectorTable[Exception_id].Data = Data;
-}
-
-/*****************************************************************************/
-/**
-* @brief Get a handler for a specific exception. This handler is being
-* called when the processor encounters the specified exception.
-*
-* @param Exception_id contains the ID of the exception source and should
-* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
-* See xil_exception.h for further information.
-* @param Handler to the Handler for that exception.
-* @param Data is a reference to Data that will be passed to the
-* Handler when it gets called.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_GetExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler *Handler,
- void **Data)
-{
-#if defined (versal) && !defined(ARMR5) && EL3
- if ( XIL_EXCEPTION_ID_IRQ_INT == Exception_id )
- {
- /*
- * Cortexa72 processor in versal is coupled with GIC-500, and
- * GIC-500 supports only FIQ at EL3. Hence, tweaking this API
- * to act on IRQ, if Exception_id is pointing to IRQ
- */
-
- Exception_id = XIL_EXCEPTION_ID_FIQ_INT;
- }
-#endif
-
- *Handler = XExc_VectorTable[Exception_id].Handler;
- *Data = XExc_VectorTable[Exception_id].Data;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Removes the Handler for a specific exception Id. The stub Handler
-* is then registered for this exception Id.
-*
-* @param Exception_id contains the ID of the exception source and should
-* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
-* See xil_exception.h for further information.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ExceptionRemoveHandler(u32 Exception_id)
-{
- Xil_ExceptionRegisterHandler(Exception_id,
- Xil_ExceptionNullHandler,
- NULL);
-}
-
-#if defined (__aarch64__)
-/*****************************************************************************/
-/**
-*
-* Default Synchronous abort handler which prints a debug message on console if
-* Debug flag is enabled
-*
-* @return None.
-*
-****************************************************************************/
-
-void Xil_SyncAbortHandler(void *CallBackRef){
- (void) CallBackRef;
- xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
- while(1) {
- ;
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Default SError abort handler which prints a debug message on console if
-* Debug flag is enabled
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_SErrorAbortHandler(void *CallBackRef){
- (void) CallBackRef;
- xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
- while(1) {
- ;
- }
-}
-#else
-/*****************************************************************************/
-/**
-*
-* Default Data abort handler which prints data fault status register through
-* which information about data fault can be acquired
-*
-* @return None.
-*
-****************************************************************************/
-
-void Xil_DataAbortHandler(void *CallBackRef){
- (void) CallBackRef;
-#ifdef DEBUG
- u32 FaultStatus;
-
- xdbg_printf(XDBG_DEBUG_ERROR, "Data abort \n");
- #ifdef __GNUC__
- FaultStatus = mfcp(XREG_CP15_DATA_FAULT_STATUS);
- #elif defined (__ICCARM__)
- mfcp(XREG_CP15_DATA_FAULT_STATUS,FaultStatus);
- #else
- { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS);
- FaultStatus = Reg; }
- #endif
- xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register %lx\n",FaultStatus);
- xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Data abort %lx\n",DataAbortAddr);
-#endif
- while(1) {
- ;
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Default Prefetch abort handler which prints prefetch fault status register through
-* which information about instruction prefetch fault can be acquired
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_PrefetchAbortHandler(void *CallBackRef){
- (void) CallBackRef;
-#ifdef DEBUG
- u32 FaultStatus;
-
- xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort \n");
- #ifdef __GNUC__
- FaultStatus = mfcp(XREG_CP15_INST_FAULT_STATUS);
- #elif defined (__ICCARM__)
- mfcp(XREG_CP15_INST_FAULT_STATUS,FaultStatus);
- #else
- { volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS);
- FaultStatus = Reg; }
- #endif
- xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register %lx\n",FaultStatus);
- xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Prefetch abort %lx\n",PrefetchAbortAddr);
-#endif
- while(1) {
- ;
- }
-}
-/*****************************************************************************/
-/**
-*
-* Default undefined exception handler which prints address of the undefined
-* instruction if debug prints are enabled
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_UndefinedExceptionHandler(void *CallBackRef){
- (void) CallBackRef;
- xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %lx\n",UndefinedExceptionAddr);
- while(1) {
- ;
- }
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4/c038ab545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4/c038ab545243001d18b399c1eb9b3628
deleted file mode 100644
index 832093c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4/c038ab545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,229 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xgpio.c
-* @addtogroup gpio_v4_8
-* @{
-*
-* The implementation of the XGpio driver's basic functionality. See xgpio.h
-* for more information about the driver.
-*
-* @note
-*
-* None
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 02/04/02 First release
-* 2.00a jhl 12/16/02 Update for dual channel and interrupt support
-* 2.01a jvb 12/13/05 Changed Initialize() into CfgInitialize(), and made
-* CfgInitialize() take a pointer to a config structure
-* instead of a device id. Moved Initialize() into
-* xgpio_sinit.c, and had Initialize() call CfgInitialize()
-* after it retrieved the config structure using the device
-* id. Removed include of xparameters.h along with any
-* dependencies on xparameters.h and the _g.c config table.
-* 2.11a mta 03/21/07 Updated to new coding style, added GetDataDirection
-* 2.12a sv 11/21/07 Updated driver to support access through DCR bus
-* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the
-* macros to remove _m from the name.
-* 4.1 lks 11/18/15 Clean up of the comments in the code and
-* removed support for DCR bridge
-* 4.2 sk 08/16/16 Used UINTPTR instead of u32 for Baseaddress as part of
-* adding 64 bit support. CR# 867425.
-* Changed the prototype of XGpio_CfgInitialize API.
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xgpio.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-
-/************************** Function Prototypes *****************************/
-
-
-/****************************************************************************/
-/**
-* Initialize the XGpio instance provided by the caller based on the
-* given configuration data.
-*
-* Nothing is done except to initialize the InstancePtr.
-*
-* @param InstancePtr is a pointer to an XGpio instance. The memory the
-* pointer references must be pre-allocated by the caller. Further
-* calls to manipulate the driver through the XGpio API must be
-* made with this pointer.
-* @param Config is a reference to a structure containing information
-* about a specific GPIO device. This function initializes an
-* InstancePtr object for a specific device specified by the
-* contents of Config. This function can initialize multiple
-* instance objects with the use of multiple calls giving different
-* Config information on each call.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. The caller is responsible for keeping the address
-* mapping from EffectiveAddr to the device physical base address
-* unchanged once this function is invoked. Unexpected errors may
-* occur if the address mapping changes after this function is
-* called. If address translation is not used, use
-* Config->BaseAddress for this parameters, passing the physical
-* address instead.
-*
-* @return
-* - XST_SUCCESS if the initialization is successful.
-*
-* @note None.
-*
-*****************************************************************************/
-int XGpio_CfgInitialize(XGpio * InstancePtr, XGpio_Config * Config,
- UINTPTR EffectiveAddr)
-{
- /* Assert arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /* Set some default values. */
- InstancePtr->BaseAddress = EffectiveAddr;
-
- InstancePtr->InterruptPresent = Config->InterruptPresent;
- InstancePtr->IsDual = Config->IsDual;
-
- /*
- * Indicate the instance is now ready to use, initialized without error
- */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
- return (XST_SUCCESS);
-}
-
-
-/****************************************************************************/
-/**
-* Set the input/output direction of all discrete signals for the specified
-* GPIO channel.
-*
-* @param InstancePtr is a pointer to an XGpio instance to be worked on.
-* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
-* @param DirectionMask is a bitmask specifying which discretes are input
-* and which are output. Bits set to 0 are output and bits set to 1
-* are input.
-*
-* @return None.
-*
-* @note The hardware must be built for dual channels if this function
-* is used with any channel other than 1. If it is not, this
-* function will assert.
-*
-*****************************************************************************/
-void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
- u32 DirectionMask)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((Channel == 1) ||
- ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
-
- XGpio_WriteReg(InstancePtr->BaseAddress,
- ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_TRI_OFFSET,
- DirectionMask);
-}
-
-/****************************************************************************/
-/**
-* Get the input/output direction of all discrete signals for the specified
-* GPIO channel.
-*
-* @param InstancePtr is a pointer to an XGpio instance to be worked on.
-* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
-*
-* @return Bitmask specifying which discretes are input and
-* which are output. Bits set to 0 are output and bits set to 1 are
-* input.
-*
-* @note
-*
-* The hardware must be built for dual channels if this function is used
-* with any channel other than 1. If it is not, this function will assert.
-*
-*****************************************************************************/
-u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((Channel == 1) ||
- ((Channel == 2) &&
- (InstancePtr->IsDual == TRUE)));
-
- return XGpio_ReadReg(InstancePtr->BaseAddress,
- ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_TRI_OFFSET);
-}
-
-/****************************************************************************/
-/**
-* Read state of discretes for the specified GPIO channel.
-*
-* @param InstancePtr is a pointer to an XGpio instance to be worked on.
-* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
-*
-* @return Current copy of the discretes register.
-*
-* @note The hardware must be built for dual channels if this function
-* is used with any channel other than 1. If it is not, this
-* function will assert.
-*
-*****************************************************************************/
-u32 XGpio_DiscreteRead(XGpio * InstancePtr, unsigned Channel)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((Channel == 1) ||
- ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
-
- return XGpio_ReadReg(InstancePtr->BaseAddress,
- ((Channel - 1) * XGPIO_CHAN_OFFSET) +
- XGPIO_DATA_OFFSET);
-}
-
-/****************************************************************************/
-/**
-* Write to discretes register for the specified GPIO channel.
-*
-* @param InstancePtr is a pointer to an XGpio instance to be worked on.
-* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
-* @param Data is the value to be written to the discretes register.
-*
-* @return None.
-*
-* @note The hardware must be built for dual channels if this function
-* is used with any channel other than 1. If it is not, this
-* function will assert. See also XGpio_DiscreteSet() and
-* XGpio_DiscreteClear().
-*
-*****************************************************************************/
-void XGpio_DiscreteWrite(XGpio * InstancePtr, unsigned Channel, u32 Data)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((Channel == 1) ||
- ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
-
- XGpio_WriteReg(InstancePtr->BaseAddress,
- ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET,
- Data);
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4/e16e1a585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4/e16e1a585243001d18b399c1eb9b3628
deleted file mode 100644
index de98c61..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4/e16e1a585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,345 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xscutimer.h
-* @addtogroup scutimer_v2_3
-* @{
-* @details
-*
-* The timer driver supports the Cortex A9 private timer.
-*
-* The timer driver supports the following features:
-* - Normal mode and Auto reload mode
-* - Interrupts (Interrupt handler is not provided in this driver. Application
-* has to register it's own handler)
-*
-* Initialization and Configuration
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate with the Timer.
-*
-* XScuTimer_CfgInitialize() API is used to initialize the Timer. The
-* user needs to first call the XScuTimer_LookupConfig() API which returns
-* the Configuration structure pointer which is passed as a parameter to
-* the XScuTimer_CfgInitialize() API.
-*
-* Interrupts
-*
-* The Timer hardware supports interrupts.
-*
-* This driver does not provide a Interrupt Service Routine (ISR) for the device.
-* It is the responsibility of the application to provide one if needed. Refer to
-* the interrupt example provided with this driver for details on using the
-* Timer in interrupt mode.
-*
-* Virtual Memory
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-* Threads
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* Asserts
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* Building the driver
-*
-* The XScuTimer driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-*
-*
-* NOTE:
-* The timer is not a part of the snoop control unit as indicated by the
-* prefix "scu" in the name of the driver.
-* It is an independent module in APU.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm 03/10/10 First release
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 2.3 mus 08/31/20 Updated makefile to support parallel make and
-* incremental builds, it would help to reduce compilation
-* time.
-*
-*
-******************************************************************************/
-#ifndef XSCUTIMER_H /* prevent circular inclusions */
-#define XSCUTIMER_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xscutimer_hw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddr; /**< Base address of the device */
-} XScuTimer_Config;
-
-/**
- * The XScuTimer driver instance data. The user is required to allocate a
- * variable of this type for every timer device in the system.
- * A pointer to a variable of this type is then passed to the driver API
- * functions.
- */
-typedef struct {
- XScuTimer_Config Config; /**< Hardware Configuration */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStarted; /**< Device timer is running */
-} XScuTimer;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Check if the timer has expired.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return
-* - TRUE if the timer has expired.
-* - FALSE if the timer has not expired.
-*
-* @note C-style signature:
-* int XScuTimer_IsExpired(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_IsExpired(InstancePtr) \
- ((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_ISR_OFFSET) & \
- XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
- XSCUTIMER_ISR_EVENT_FLAG_MASK)
-
-/****************************************************************************/
-/**
-*
-* Re-start the timer. This macro will read the timer load register
-* and writes the same value to load register to update the counter register.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_RestartTimer(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_RestartTimer(InstancePtr) \
- XScuTimer_LoadTimer((InstancePtr), \
- XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_LOAD_OFFSET))
-
-/****************************************************************************/
-/**
-*
-* Write to the timer load register. This will also update the
-* timer counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-* @param Value is the count to be loaded in to the load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_LoadTimer(InstancePtr, Value) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_LOAD_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer counter register value. It can be called at any
-* time.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return Contents of the timer counter register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_GetCounterValue(InstancePtr) \
- XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_COUNTER_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Enable auto-reload mode.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_EnableAutoReload(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) | \
- XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
-
-/****************************************************************************/
-/**
-*
-* Disable auto-reload mode.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_DisableAutoReload(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) & \
- ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Enable the Timer interrupt.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_EnableInterrupt(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) | \
- XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
-
-/****************************************************************************/
-/**
-*
-* Disable the Timer interrupt.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_DisableInterrupt(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) & \
- ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
-
-/*****************************************************************************/
-/**
-*
-* This function reads the interrupt status.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_GetInterruptStatus(InstancePtr) \
- XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_ISR_OFFSET)
-
-/*****************************************************************************/
-/**
-*
-* This function clears the interrupt status.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_ClearInterruptStatus(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Lookup configuration in xscutimer_sinit.c
- */
-XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId);
-
-/*
- * Selftest function in xscutimer_selftest.c
- */
-s32 XScuTimer_SelfTest(XScuTimer *InstancePtr);
-
-/*
- * Interface functions in xscutimer.c
- */
-s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
- XScuTimer_Config *ConfigPtr, u32 EffectiveAddress);
-void XScuTimer_Start(XScuTimer *InstancePtr);
-void XScuTimer_Stop(XScuTimer *InstancePtr);
-void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue);
-u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/40/11ba2d565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/40/11ba2d565243001d18b399c1eb9b3628
deleted file mode 100644
index ff13d1e..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/40/11ba2d565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,610 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_mpu.c
-*
-* This file provides APIs for enabling/disabling MPU and setting the memory
-* attributes for sections, in the MPU translation table.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00 pkp 02/10/14 Initial version
-* 6.2 mus 01/27/17 Updated to support IAR compiler
-* 6.4 asa 08/16/17 Added many APIs for MPU access to make MPU usage
-* user-friendly. The APIs added are: Xil_UpdateMPUConfig,
-* Xil_GetMPUConfig, Xil_GetNumOfFreeRegions,
-* Xil_GetNextMPURegion, Xil_DisableMPURegionByRegNum,
-* Xil_GetMPUFreeRegMask, Xil_SetMPURegionByRegNum, and
-* Xil_InitializeExistingMPURegConfig.
-* Added a new array of structure of type XMpuConfig to
-* represent the MPU configuration table.
-* 6.8 aru 07/02/18 Returned the pointer instead of address
-* of that pointer in Xil_MemMap().
-* 7.5 asa 03/01/21 Ensure that Mpu_Config does not stay in .boot/.vector
-* sections which generally should be executable code
-* which can be allocated and not written.
-* Mpu_Config array is populated during boot time, hence
-* cannot be placed in .bss or .data section. Putting
-* Mpu_Config in a new .bootdata section.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-#include "xil_mpu.h"
-#include "xdebug.h"
-#include "xstatus.h"
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-#define MPU_REGION_SIZE_MIN 0x20
-/************************** Variable Definitions *****************************/
-
-static const struct {
- u64 size;
- unsigned int encoding;
-}region_size[] = {
- { 0x20, REGION_32B },
- { 0x40, REGION_64B },
- { 0x80, REGION_128B },
- { 0x100, REGION_256B },
- { 0x200, REGION_512B },
- { 0x400, REGION_1K },
- { 0x800, REGION_2K },
- { 0x1000, REGION_4K },
- { 0x2000, REGION_8K },
- { 0x4000, REGION_16K },
- { 0x8000, REGION_32K },
- { 0x10000, REGION_64K },
- { 0x20000, REGION_128K },
- { 0x40000, REGION_256K },
- { 0x80000, REGION_512K },
- { 0x100000, REGION_1M },
- { 0x200000, REGION_2M },
- { 0x400000, REGION_4M },
- { 0x800000, REGION_8M },
- { 0x1000000, REGION_16M },
- { 0x2000000, REGION_32M },
- { 0x4000000, REGION_64M },
- { 0x8000000, REGION_128M },
- { 0x10000000, REGION_256M },
- { 0x20000000, REGION_512M },
- { 0x40000000, REGION_1G },
- { 0x80000000, REGION_2G },
- { 0x100000000, REGION_4G },
-};
-
-#if defined (__GNUC__)
-XMpu_Config Mpu_Config __attribute__((section(".bootdata")));
-#elif defined (__ICCARM__)
-#pragma default_function_attributes = @ ".bootdata"
-XMpu_Config Mpu_Config;
-#endif
-
-/************************** Function Prototypes ******************************/
-void Xil_InitializeExistingMPURegConfig(void);
-/*****************************************************************************/
-/**
-* @brief This function sets the memory attributes for a section covering
-* 1MB, of memory in the translation table.
-*
-* @param addr: 32-bit address for which memory attributes need to be set.
-* @param attrib: Attribute for the given memory region.
-* @return None.
-*
-*
-******************************************************************************/
-void Xil_SetTlbAttributes(INTPTR addr, u32 attrib)
-{
- INTPTR Localaddr = addr;
- Localaddr &= (~(0xFFFFFU));
- /* Setting the MPU region with given attribute with 1MB size */
- Xil_SetMPURegion(Localaddr, 0x100000, attrib);
-}
-
-/*****************************************************************************/
-/**
-* @brief Set the memory attributes for a section of memory in the
-* translation table.
-*
-* @param addr: 32-bit address for which memory attributes need to be set..
-* @param size: size is the size of the region.
-* @param attrib: Attribute for the given memory region.
-* @return None.
-*
-*
-******************************************************************************/
-u32 Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib)
-{
- u32 Regionsize = 0;
- INTPTR Localaddr = addr;
- u32 NextAvailableMemRegion;
- unsigned int i;
-
- NextAvailableMemRegion = Xil_GetNextMPURegion();
- if (NextAvailableMemRegion == 0xFF) {
- xdbg_printf(DEBUG, "No regions available\r\n");
- return XST_FAILURE;
- }
-
- Xil_DCacheFlush();
- Xil_ICacheInvalidate();
-
- mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,NextAvailableMemRegion);
- isb();
-
- /* Lookup the size. */
- for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) {
- if (size <= region_size[i].size) {
- Regionsize = region_size[i].encoding;
- break;
- }
- }
-
- Localaddr &= ~(region_size[i].size - 1);
-
- Regionsize <<= 1;
- Regionsize |= REGION_EN;
- dsb();
- mtcp(XREG_CP15_MPU_REG_BASEADDR, Localaddr); /* Set base address of a region */
- mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL, attrib); /* Set the control attribute */
- mtcp(XREG_CP15_MPU_REG_SIZE_EN, Regionsize); /* set the region size and enable it*/
- dsb();
- isb();
- Xil_UpdateMPUConfig(NextAvailableMemRegion, Localaddr, Regionsize, attrib);
- return XST_SUCCESS;
-}
-/*****************************************************************************/
-/**
-* @brief Enable MPU for Cortex R5 processor. This function invalidates I
-* cache and flush the D Caches, and then enables the MPU.
-*
-* @return None.
-*
-******************************************************************************/
-void Xil_EnableMPU(void)
-{
- u32 CtrlReg, Reg;
- s32 DCacheStatus=0, ICacheStatus=0;
- /* enable caches only if they are disabled */
-#if defined (__GNUC__)
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
-#endif
- if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) {
- DCacheStatus=1;
- }
- if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) {
- ICacheStatus=1;
- }
-
- if(DCacheStatus != 0) {
- Xil_DCacheDisable();
- }
- if(ICacheStatus != 0){
- Xil_ICacheDisable();
- }
-#if defined (__GNUC__)
- Reg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL,Reg);
-#endif
- Reg |= 0x00000001U;
- dsb();
- mtcp(XREG_CP15_SYS_CONTROL, Reg);
- isb();
- /* enable caches only if they are disabled in routine*/
- if(DCacheStatus != 0) {
- Xil_DCacheEnable();
- }
- if(ICacheStatus != 0) {
- Xil_ICacheEnable();
- }
-}
-
-/*****************************************************************************/
-/**
-* @brief Disable MPU for Cortex R5 processors. This function invalidates I
-* cache and flush the D Caches, and then disabes the MPU.
-*
-* @return None.
-*
-******************************************************************************/
-void Xil_DisableMPU(void)
-{
- u32 CtrlReg, Reg;
- s32 DCacheStatus=0, ICacheStatus=0;
- /* enable caches only if they are disabled */
-
-#if defined (__GNUC__)
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
-#endif
- if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) {
- DCacheStatus=1;
- }
- if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) {
- ICacheStatus=1;
- }
-
- if(DCacheStatus != 0) {
- Xil_DCacheDisable();
- }
- if(ICacheStatus != 0){
- Xil_ICacheDisable();
- }
-
- mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0);
-#if defined (__GNUC__)
- Reg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL,Reg);
-#endif
- Reg &= ~(0x00000001U);
- dsb();
- mtcp(XREG_CP15_SYS_CONTROL, Reg);
- isb();
- /* enable caches only if they are disabled in routine*/
- if(DCacheStatus != 0) {
- Xil_DCacheEnable();
- }
- if(ICacheStatus != 0) {
- Xil_ICacheEnable();
- }
-}
-
-/*****************************************************************************/
-/**
-* @brief Update the MPU configuration for the requested region number in
-* the global MPU configuration table.
-*
-* @param reg_num: The requested region number to be updated information for.
-* @param address: 32 bit address for start of the region.
-* @param size: Requested size of the region.
-* @param attrib: Attribute for the corresponding region.
-* @return XST_FAILURE: When the requested region number if 16 or more.
-* XST_SUCCESS: When the MPU configuration table is updated.
-*
-*
-******************************************************************************/
-u32 Xil_UpdateMPUConfig(u32 reg_num, INTPTR address, u32 size, u32 attrib)
-{
- u32 ReturnVal = XST_SUCCESS;
- u32 Tempsize = size;
- u32 Index;
-
- if (reg_num >= MAX_POSSIBLE_MPU_REGS) {
- xdbg_printf(DEBUG, "Invalid region number\r\n");
- ReturnVal = XST_FAILURE;
- goto exit;
- }
-
- if (size & REGION_EN) {
- Mpu_Config[reg_num].RegionStatus = MPU_REG_ENABLED;
- Mpu_Config[reg_num].BaseAddress = address;
- Tempsize &= (~REGION_EN);
- Tempsize >>= 1;
- /* Lookup the size. */
- for (Index = 0; Index <
- sizeof region_size / sizeof region_size[0]; Index++) {
- if (Tempsize <= region_size[Index].encoding) {
- Mpu_Config[reg_num].Size = region_size[Index].size;
- break;
- }
- }
- Mpu_Config[reg_num].Attribute = attrib;
- } else {
- Mpu_Config[reg_num].RegionStatus = 0U;
- Mpu_Config[reg_num].BaseAddress = 0U;
- Mpu_Config[reg_num].Size = 0U;
- Mpu_Config[reg_num].Attribute = 0U;
- }
-
-exit:
- return ReturnVal;
-}
-
-/*****************************************************************************/
-/**
-* @brief The MPU configuration table is passed to the caller.
-*
-* @param mpuconfig: This is of type XMpu_Config which is an array of
-* 16 entries of type structure representing the MPU config table
-* @return none
-*
-*
-******************************************************************************/
-void Xil_GetMPUConfig (XMpu_Config mpuconfig) {
- u32 Index = 0U;
-
- while (Index < MAX_POSSIBLE_MPU_REGS) {
- mpuconfig[Index].RegionStatus = Mpu_Config[Index].RegionStatus;
- mpuconfig[Index].BaseAddress = Mpu_Config[Index].BaseAddress;
- mpuconfig[Index].Attribute = Mpu_Config[Index].Attribute;
- mpuconfig[Index].Size = Mpu_Config[Index].Size;
- Index++;
- }
-}
-
-/*****************************************************************************/
-/**
-* @brief Returns the total number of free MPU regions available.
-*
-* @return Number of free regions available to users
-*
-*
-******************************************************************************/
-u32 Xil_GetNumOfFreeRegions (void) {
- u32 Index = 0U;
- int NumofFreeRegs = 0U;
-
- while (Index < MAX_POSSIBLE_MPU_REGS) {
- if (MPU_REG_DISABLED == Mpu_Config[Index].RegionStatus) {
- NumofFreeRegs++;
- }
- Index++;
- }
- return NumofFreeRegs;
-}
-
-/*****************************************************************************/
-/**
-* @brief Returns the total number of free MPU regions available in the form
-* of a mask. A bit of 1 in the returned 16 bit value represents the
-* corresponding region number to be available.
-* For example, if this function returns 0xC0000, this would mean, the
-* regions 14 and 15 are available to users.
-*
-* @return The free region mask as a 16 bit value
-*
-*
-******************************************************************************/
-u16 Xil_GetMPUFreeRegMask (void) {
- u32 Index = 0U;
- u16 FreeRegMask = 0U;
-
- while (Index < MAX_POSSIBLE_MPU_REGS) {
- if (MPU_REG_DISABLED == Mpu_Config[Index].RegionStatus) {
- FreeRegMask |= (1U << Index);
- }
- Index++;
- }
- return FreeRegMask;
-}
-
-/*****************************************************************************/
-/**
-* @brief Disables the corresponding region number as passed by the user.
-*
-* @param reg_num: The region number to be disabled
-* @return XST_SUCCESS: If the region could be disabled successfully
-* XST_FAILURE: If the requested region number is 16 or more.
-*
-*
-******************************************************************************/
-u32 Xil_DisableMPURegionByRegNum (u32 reg_num) {
- u32 Temp = 0U;
- u32 ReturnVal = XST_FAILURE;
-
- if (reg_num >= 16U) {
- xdbg_printf(DEBUG, "Invalid region number\r\n");
- goto exit1;
- }
- Xil_DCacheFlush();
- Xil_ICacheInvalidate();
-
- mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num);
-#if defined (__GNUC__)
- Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
-#endif
- Temp &= (~REGION_EN);
- dsb();
- mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
- dsb();
- isb();
- Xil_UpdateMPUConfig(reg_num, 0U, 0U, 0U);
- ReturnVal = XST_SUCCESS;
-
-exit1:
- return ReturnVal;
-}
-
-/*****************************************************************************/
-/**
-* @brief Enables the corresponding region number as passed by the user.
-*
-* @param reg_num: The region number to be enabled
-* @param addr: 32 bit address for start of the region.
-* @param size: Requested size of the region.
-* @param attrib: Attribute for the corresponding region.
-* @return XST_SUCCESS: If the region could be created successfully
-* XST_FAILURE: If the requested region number is 16 or more.
-*
-*
-******************************************************************************/
-u32 Xil_SetMPURegionByRegNum (u32 reg_num, INTPTR addr, u64 size, u32 attrib)
-{
- u32 ReturnVal = XST_SUCCESS;
- INTPTR Localaddr = addr;
- u32 Regionsize = 0;
- u32 Index;
-
- if (reg_num >= 16U) {
- xdbg_printf(DEBUG, "Invalid region number\r\n");
- ReturnVal = XST_FAILURE;
- goto exit2;
- }
-
- if (Mpu_Config[reg_num].RegionStatus == MPU_REG_ENABLED) {
- xdbg_printf(DEBUG, "Region already enabled\r\n");
- ReturnVal = XST_FAILURE;
- goto exit2;
- }
-
- Xil_DCacheFlush();
- Xil_ICacheInvalidate();
- mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num);
- isb();
-
- /* Lookup the size. */
- for (Index = 0; Index <
- sizeof region_size / sizeof region_size[0]; Index++) {
- if (size <= region_size[Index].size) {
- Regionsize = region_size[Index].encoding;
- break;
- }
- }
-
- Localaddr &= ~(region_size[Index].size - 1);
- Regionsize <<= 1;
- Regionsize |= REGION_EN;
- dsb();
- mtcp(XREG_CP15_MPU_REG_BASEADDR, Localaddr);
- mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL, attrib);
- mtcp(XREG_CP15_MPU_REG_SIZE_EN, Regionsize);
- dsb();
- isb();
- Xil_UpdateMPUConfig(reg_num, Localaddr, Regionsize, attrib);
-exit2:
- return ReturnVal;
-
-}
-
-/*****************************************************************************/
-/**
-* @brief Initializes the MPU configuration table that are setup in the
-* R5 boot code in the Init_Mpu function called before C main.
-*
-* @return none
-*
-*
-******************************************************************************/
-void Xil_InitializeExistingMPURegConfig(void)
-{
- u32 Index = 0U;
- u32 Index1 = 0U;
- u32 MPURegSize;
- INTPTR MPURegBA;
- u32 MPURegAttrib;
- u32 Tempsize;
-
- while (Index < MAX_POSSIBLE_MPU_REGS) {
- mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index);
-#if defined (__GNUC__)
- MPURegSize = mfcp(XREG_CP15_MPU_REG_SIZE_EN);
- MPURegBA = mfcp(XREG_CP15_MPU_REG_BASEADDR);
- MPURegAttrib = mfcp(XREG_CP15_MPU_REG_ACCESS_CTRL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_MPU_REG_SIZE_EN,MPURegSize);
- mfcp(XREG_CP15_MPU_REG_BASEADDR, MPURegBA);
- mfcp(XREG_CP15_MPU_REG_ACCESS_CTRL, MPURegAttrib);
-#endif
- if (MPURegSize & REGION_EN) {
- Mpu_Config[Index].RegionStatus = MPU_REG_ENABLED;
- Mpu_Config[Index].BaseAddress = MPURegBA;
- Mpu_Config[Index].Attribute = MPURegAttrib;
- Tempsize = MPURegSize & (~REGION_EN);
- Tempsize >>= 1;
- for (Index1 = 0; Index1 <
- (sizeof (region_size) / sizeof (region_size[0])); Index1++) {
- if (Tempsize <= region_size[Index1].encoding) {
- Mpu_Config[Index].Size = region_size[Index1].size;
- break;
- }
- }
- }
- Index++;
- }
-}
-
-/*****************************************************************************/
-/**
-* @brief Returns the next available free MPU region
-*
-* @return The free MPU region available
-*
-*
-******************************************************************************/
-u32 Xil_GetNextMPURegion(void)
-{
- u32 Index = 0U;
- u32 NextAvailableReg = 0xFF;
- while (Index < MAX_POSSIBLE_MPU_REGS) {
- if (Mpu_Config[Index].RegionStatus != MPU_REG_ENABLED) {
- NextAvailableReg = Index;
- break;
- }
- Index++;
- }
- return NextAvailableReg;
-}
-
-#ifdef __GNUC__
-#define u32overflow(a, b) ({typeof(a) s; __builtin_uadd_overflow(a, b, &s); })
-#else
-#define u32overflow(a, b) ((a) > ((a) + (b)))
-#endif /* __GNUC__ */
-
-/*****************************************************************************/
-/**
-* @brief Memory mapping for Cortex-R5F. If successful, the mapped
-* region will include all of the memory requested, but may
-* include more. Specifically, it will be a power of 2 in
-* size, aligned on a boundary of that size.
-*
-* @param Physaddr is base physical address at which to start mapping.
-* NULL in Physaddr masks possible mapping errors.
-* @param size of region to be mapped.
-* @param flags used to set translation table.
-*
-* @return Physaddr on success, NULL on error. Ambiguous if Physaddr==NULL
-*
-* @cond Xil_MemMap_internal
-* @note: u32overflow() is defined for readability and (for __GNUC__) to
-* - force the type of the check to be the same as the first argument
-* - hide the otherwise unused third argument of the builtin
-* - improve safety by choosing the explicit _uadd_ version.
-* Consider __builtin_add_overflow_p() when available.
-* Use an alternative (less optimal?) for compilers w/o the builtin.
-* @endcond
-******************************************************************************/
-void *Xil_MemMap(UINTPTR Physaddr, size_t size, u32 flags)
-{
- size_t Regionsize = MPU_REGION_SIZE_MIN;
- UINTPTR Basephysaddr = 0, end = Physaddr + size;
-
- if (!flags)
- return (void *)Physaddr;
- if (u32overflow(Physaddr, size))
- return NULL;
- for ( ; Regionsize != 0; Regionsize <<= 1) {
- if (Regionsize >= size) {
- Basephysaddr = Physaddr & ~(Regionsize - 1);
- if (u32overflow(Basephysaddr, Regionsize))
- break;
- if ((Basephysaddr + Regionsize) >= end)
- return Xil_SetMPURegion(Basephysaddr,
- Regionsize, flags) == XST_SUCCESS ?
- (void *)Physaddr : NULL;
- }
- }
- return NULL;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/40/21238e595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/40/21238e595243001d18b399c1eb9b3628
deleted file mode 100644
index f0102aa..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/40/21238e595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,54 +0,0 @@
-/* putnum.c -- put a hex number on the output device.
- *
- * Copyright (c) 1995 Cygnus Support
- *
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
- * putnum -- print a 32 bit number in hex
- */
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-
-/************************** Function Prototypes ******************************/
-extern void print (const char8 *ptr);
-void putnum(u32 num);
-
-void putnum(u32 num)
-{
- char8 buf[9];
- s32 cnt;
- s32 i;
- char8 *ptr;
- u32 digit;
- for(i = 0; i<9; i++) {
- buf[i] = '0';
- }
-
- ptr = buf;
- for (cnt = 7 ; cnt >= 0 ; cnt--) {
- digit = (num >> (cnt * 4U)) & 0x0000000fU;
-
- if (digit <= 9U) {
- digit += (u32)'0';
- *ptr = ((char8) digit);
- ptr += 1;
- } else {
- digit += ((u32)'a' - (u32)10);
- *ptr = ((char8)digit);
- ptr += 1;
- }
- }
-
- print (buf);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/40/30416f545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/40/30416f545243001d18b399c1eb9b3628
deleted file mode 100644
index 5c01051..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/40/30416f545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1132 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
- *
- * @file xusbps.h
-* @addtogroup usbps_v2_7
-* @{
-* @details
- *
- * This file contains the implementation of the XUsbPs driver. It is the
- * driver for an USB controller in DEVICE or HOST mode.
- *
- *
Introduction
- *
- * The Spartan-3AF Embedded Peripheral Block contains a USB controller for
- * communication with serial peripherals or hosts. The USB controller supports
- * Host, Device and On the Go (OTG) applications.
- *
- *
USB Controller Features
- *
- * - Supports Low Speed USB 1.1 (1.5Mbps), Full Speed USB 1.1 (12Mbps), and
- * High Speed USB 2.0 (480Mbps) data speeds
- * - Supports Device, Host and OTG operational modes
- * - ULPI transceiver interface for USB 2.0 operation
- * - Integrated USB Full and Low speed serial transceiver interfaces for lowest
- * cost connections
- *
- *
Initialization & Configuration
- *
- * The configuration of the USB driver happens in multiple stages:
- *
- * - (a) Configuration of the basic parameters:
- * In this stage the basic parameters for the driver are configured,
- * including the base address and the controller ID.
- *
- * - (b) Configuration of the DEVICE endpoints (if applicable):
- * If DEVICE mode is desired, the endpoints of the controller need to be
- * configured using the XUsbPs_DeviceConfig data structure. Once the
- * endpoint configuration is set up in the data structure, The user then
- * needs to allocate the required amount of DMAable memory and
- * finalize the configuration of the XUsbPs_DeviceConfig data structure,
- * e.g. setting the DMAMemVirt and DMAMemPhys members.
- *
- * - (c) Configuration of the DEVICE modes:
- * In the second stage the parameters for DEVICE are configured.
- * The caller only needs to configure the modes that are
- * actually used. Configuration is done with the:
- * XUsbPs_ConfigureDevice()
- * Configuration parameters are defined and passed
- * into these functions using the:
- * XUsbPs_DeviceConfig data structures.
- *
- *
- *
USB Device Endpoints
- *
- * The USB core supports up to 4 endpoints. Each endpoint has two directions,
- * an OUT (RX) and an IN (TX) direction. Note that the direction is viewed from
- * the host's perspective. Endpoint 0 defaults to be the control endpoint and
- * does not need to be set up. Other endpoints need to be configured and set up
- * depending on the application. Only endpoints that are actuelly used by the
- * application need to be initialized.
- * See the example code (xusbps_intr_example.c) for more information.
- *
- *
- *
Interrupt Handling
- *
- * The USB core uses one interrupt line to report interrupts to the CPU.
- * Interrupts are handled by the driver's interrupt handler function
- * XUsbPs_IntrHandler().
- * It has to be registered with the OS's interrupt subsystem. The driver's
- * interrupt handler divides incoming interrupts into two categories:
- *
- * - General device interrupts
- * - Endopint related interrupts
- *
- * The user (typically the adapter layer) can register general interrupt
- * handler functions and endpoint specific interrupt handler functions with the
- * driver to receive those interrupts by calling the
- * XUsbPs_IntrSetHandler()
- * and
- * XUsbPs_EpSetHandler()
- * functions respectively. Calling these functions with a NULL pointer as the
- * argument for the function pointer will "clear" the handler function.
- *
- * The user can register one handler function for the generic interrupts and
- * two handler functions for each endpoint, one for the RX (OUT) and one for
- * the TX (IN) direction. For some applications it may be useful to register a
- * single endpoint handler function for muliple endpoints/directions.
- *
- * When a callback function is called by the driver, parameters identifying the
- * type of the interrupt will be passed into the handler functions. For general
- * interrupts the interrupt mask will be passed into the handler function. For
- * endpoint interrupts the parameters include the number of the endpoint, the
- * direction (OUT/IN) and the type of the interrupt.
- *
- *
- *
Data buffer handling
- *
- * Data buffers are sent to and received from endpoint using the
- * XUsbPs_EpBufferSend(), XUsbPs_EpBufferSendWithZLT()
- * and
- * XUsbPs_EpBufferReceive()
- * functions.
- *
- * User data buffer size is limited to 16 Kbytes. If the user wants to send a
- * data buffer that is bigger than this limit it needs to break down the data
- * buffer into multiple fragments and send the fragments individually.
- *
- * From the controller perspective Data buffers can be aligned at any boundary.
- * if the buffers are from cache region then the buffer and buffer size should
- * be aligned to cache line aligned
- *
- *
- *
Zero copy
- *
- * The driver uses a zero copy mechanism which imposes certain restrictions to
- * the way the user can handle the data buffers.
- *
- * One restriction is that the user needs to release a buffer after it is done
- * processing the data in the buffer.
- *
- * Similarly, when the user sends a data buffer it MUST not re-use the buffer
- * until it is notified by the driver that the buffer has been transmitted. The
- * driver will notify the user via the registered endpoint interrupt handling
- * function by sending a XUSBPS_EP_EVENT_DATA_TX event.
- *
- *
- *
DMA
- *
- * The driver uses DMA internally to move data from/to memory. This behaviour
- * is transparent to the user. Keeping the DMA handling hidden from the user
- * has the advantage that the same API can be used with USB cores that do not
- * support DMA.
- *
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- ----------------------------------------------------------
- * 1.00a wgr 10/10/10 First release
- * 1.02a wgr 05/16/12 Removed comments as they are showing up in SDK
- * Tabs for CR 657898
- * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet
- * handling.
- * 1.04a nm 10/23/12 Fixed CR# 679106.
- * 11/02/12 Fixed CR# 683931. Mult bits are set properly in dQH.
- * 2.00a kpc 04/03/14 Fixed CR#777763. Corrected the setup tripwire macro val.
- * 2.1 kpc 04/28/14 Removed unused function prototypes
- * 2.2 kpc 08/23/14 Exported XUsbPs_DeviceReset API as global for calling in
- * code coverage tests.
- * 2.3 kpc 02/19/14 Fixed CR#873972, CR#873974. Corrected the logic for proper
- * moving of dTD Head/Tail Pointers. Invalidate the cache
- * after buffer receive in Endpoint Buffer Handler.
- * 2.4 sg 04/26/16 Fixed CR#949693, Corrected the logic for EP flush
- * ms 03/17/17 Added readme.txt file in examples folder for doxygen
- * generation.
- * ms 04/10/17 Modified filename tag to include the file in doxygen
- * examples.
- * 2.5 pm 02/20/20 Added ISO support for usb 2.0 and ch9 common framework
- * calls.
- *
- *
- ******************************************************************************/
-
-#ifndef XUSBPS_H
-#define XUSBPS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xusbps_hw.h"
-#include "xil_types.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions *****************************/
-
-/**
- * @name System hang prevention Timeout counter value.
- *
- * This value is used throughout the code to initialize a Timeout counter that
- * is used when hard polling a register. The ides is to initialize the Timeout
- * counter to a value that is longer than any expected Timeout but short enough
- * so the system will continue to work and report an error while the user is
- * still paying attention. A reasonable Timeout time would be about 10 seconds.
- * The XUSBPS_TIMEOUT_COUNTER value should be chosen so a polling loop would
- * run about 10 seconds before a Timeout is detected. For example:
- *
- * int Timeout = XUSBPS_TIMEOUT_COUNTER;
- * while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- * XUSBPS_CMD_OFFSET) &
- * XUSBPS_CMD_RST_MASK) && --Timeout) {
- * ;
- * }
- * if (0 == Timeout) {
- * return XST_FAILURE;
- * }
- *
- */
-#define XUSBPS_TIMEOUT_COUNTER 1000000
-
-
-/**
- * @name Endpoint Direction (bitmask)
- * Definitions to be used with Endpoint related function that require a
- * 'Direction' parameter.
- *
- * NOTE:
- * The direction is always defined from the perspective of the HOST! This
- * means that an IN endpoint on the controller is used for sending data while
- * the OUT endpoint on the controller is used for receiving data.
- * @{
- */
-#define XUSBPS_EP_DIRECTION_IN 0x01 /**< Endpoint direction IN. */
-#define XUSBPS_EP_DIRECTION_OUT 0x02 /**< Endpoint direction OUT. */
-/* @} */
-
-
-/**
- * @name Endpoint Type
- * Definitions to be used with Endpoint related functions that require a 'Type'
- * parameter.
- * @{
- */
-#define XUSBPS_EP_TYPE_NONE 0 /**< Endpoint is not used. */
-#define XUSBPS_EP_TYPE_CONTROL 1 /**< Endpoint for Control Transfers */
-#define XUSBPS_EP_TYPE_ISOCHRONOUS 2 /**< Endpoint for isochronous data */
-#define XUSBPS_EP_TYPE_BULK 3 /**< Endpoint for BULK Transfers. */
-#define XUSBPS_EP_TYPE_INTERRUPT 4 /**< Endpoint for interrupt Transfers */
-/* @} */
-
-/**
- * Endpoint Max Packet Length in DeviceConfig is a coded value, ch9.6.6.
- *
- * @{
- */
-#define ENDPOINT_MAXP_LENGTH 0x400
-#define ENDPOINT_MAXP_MULT_MASK 0xC00
-#define ENDPOINT_MAXP_MULT_SHIFT 10
-/* @} */
-
-/**
- * @name Field names for status retrieval
- * Definitions for the XUsbPs_GetStatus() function call 'StatusType'
- * parameter.
- * @{
- */
-#define XUSBPS_EP_STS_ADDRESS 1 /**< Address of controller. */
-#define XUSBPS_EP_STS_CONTROLLER_STATE 2 /**< Current controller state. */
-/* @} */
-
- /*
- * Device Speeds
- */
- #define XUSBPS_SPEED_UNKNOWN 0U
- #define XUSBPS_SPEED_LOW 1U
- #define XUSBPS_SPEED_FULL 2U
- #define XUSBPS_SPEED_HIGH 3U
-
-/**
- * @name USB Default alternate setting
- *
- * @{
- */
-#define XUSBPS_DEFAULT_ALT_SETTING 0 /**< The default alternate setting is 0 */
-/* @} */
-
- /*
- * Device States
- */
- #define XUSBPS_STATE_ATTACHED 0U
- #define XUSBPS_STATE_POWERED 1U
- #define XUSBPS_STATE_DEFAULT 2U
- #define XUSBPS_STATE_ADDRESS 3U
- #define XUSBPS_STATE_CONFIGURED 4U
- #define XUSBPS_STATE_SUSPENDED 5U
-
-/**
- * @name Endpoint event types
- * Definitions that are used to identify events that occur on endpoints. Passed
- * to the endpoint event handler functions registered with
- * XUsbPs_EpSetHandler().
- * @{
- */
-#define XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED 0x01
- /**< Setup data has been received on the endpoint. */
-#define XUSBPS_EP_EVENT_DATA_RX 0x02
- /**< Data frame has been received on the endpoint. */
-#define XUSBPS_EP_EVENT_DATA_TX 0x03
- /**< Data frame has been sent on the endpoint. */
-/* @} */
-
-
-/*
- * Maximum packet size for endpoint, 1024
- * @{
- */
-#define XUSBPS_MAX_PACKET_SIZE 1024
- /**< Maximum value can be put into the queue head */
-/* @} */
-/**************************** Type Definitions *******************************/
-
-/******************************************************************************
- * This data type defines the callback function to be used for Endpoint
- * handlers.
- *
- * @param CallBackRef is the Callback reference passed in by the upper
- * layer when setting the handler, and is passed back to the upper
- * layer when the handler is called.
- * @param EpNum is the Number of the endpoint that caused the event.
- * @param EventType is the type of the event that occurred on the endpoint.
- * @param Data is a pointer to user data pointer specified when callback
- * was registered.
- */
-typedef void (*XUsbPs_EpHandlerFunc)(void *CallBackRef,
- u8 EpNum, u8 EventType, void *Data);
-
-/******************************************************************************
- * This data type defines the callback function to be used for Endpoint
- * handlers.
- *
- * @param CallBackRef is the Callback reference passed in by the upper
- * layer when setting the handler, and is passed back to the upper
- * layer when the handler is called.
- * @param RequestedBytes is the number of bytes requested to transfer.
- * @param BytesTxed is the actual number of bytes to be transfer.
- */
-typedef void (*XUsbPs_EpIsoHandlerFunc)(void *CallBackRef,
- u32 RequestedBytes, u32 BytesTxed);
-
-/******************************************************************************
- * This data type defines the callback function to be used for the general
- * interrupt handler.
- *
- * @param CallBackRef is the Callback reference passed in by the upper
- * layer when setting the handler, and is passed back to the upper
- * layer when the handler is called.
- * @param IrqMask is the Content of the interrupt status register. This
- * value can be used by the callback function to distinguish the
- * individual interrupt types.
- */
-typedef void (*XUsbPs_IntrHandlerFunc)(void *CallBackRef, u32 IrqMask);
-
-
-/******************************************************************************/
-
-/* The following type definitions are used for referencing Queue Heads and
- * Transfer Descriptors. The structures themselves are not used, however, the
- * types are used in the API to avoid using (void *) pointers.
- */
-typedef u8 XUsbPs_dQH[XUSBPS_dQH_ALIGN];
-typedef u8 XUsbPs_dTD[XUSBPS_dTD_ALIGN];
-
-
-/**
- * The following data structures are used internally by the L0/L1 driver.
- * Their contents MUST NOT be changed by the upper layers.
- */
-
-/**
- * The following data structure represents OUT endpoint.
- */
-typedef struct {
- XUsbPs_dQH *dQH;
- /**< Pointer to the Queue Head structure of the endpoint. */
-
- XUsbPs_dTD *dTDs;
- /**< Pointer to the first dTD of the dTD list for this
- * endpoint. */
-
- XUsbPs_dTD *dTDCurr;
- /**< Buffer to the currently processed descriptor. */
-
- u8 *dTDBufs;
- /**< Pointer to the first buffer of the buffer list for this
- * endpoint. */
-
- XUsbPs_EpHandlerFunc HandlerFunc;
- XUsbPs_EpIsoHandlerFunc HandlerIsoFunc;
- /**< Handler function for this endpoint. */
- void *HandlerRef;
- /**< User data reference for the handler. */
- u32 RequestedBytes; /**< RequestedBytes for transfer */
- u32 BytesTxed; /**< Actual Bytes transferred */
- u8 *BufferPtr; /**< Buffer location */
- u8 MemAlloted; /**< Mem alloted and data is not received */
- u32 Interval; /**< Data transfer service interval */
-} XUsbPs_EpOut;
-
-
-/**
- * The following data structure represents IN endpoint.
- */
-typedef struct {
- XUsbPs_dQH *dQH;
- /**< Pointer to the Queue Head structure of the endpoint. */
-
- XUsbPs_dTD *dTDs;
- /**< List of pointers to the Transfer Descriptors of the
- * endpoint. */
-
- XUsbPs_dTD *dTDHead;
- /**< Buffer to the next available descriptor in the list. */
-
- XUsbPs_dTD *dTDTail;
- /**< Buffer to the last unsent descriptor in the list*/
-
- XUsbPs_EpHandlerFunc HandlerFunc;
- XUsbPs_EpIsoHandlerFunc HandlerIsoFunc;
- /**< Handler function for this endpoint. */
- void *HandlerRef;
- /**< User data reference for the handler. */
- u32 RequestedBytes; /**< RequestedBytes for transfer */
- u32 BytesTxed; /**< Actual Bytes transferred */
- u8 *BufferPtr; /**< Buffer location */
- u32 Interval; /**< Data transfer service interval */
-} XUsbPs_EpIn;
-
-
-/**
- * The following data structure represents an endpoint used internally
- * by the L0/L1 driver.
- */
-typedef struct {
- /* Each endpoint has an OUT and an IN component.
- */
- XUsbPs_EpOut Out; /**< OUT endpoint structure */
- XUsbPs_EpIn In; /**< IN endpoint structure */
-} XUsbPs_Endpoint;
-
-
-
-/**
- * The following structure is used by the user to receive Setup Data from an
- * endpoint. Using this structure simplifies the process of interpreting the
- * setup data in the core's data fields.
- *
- * The naming scheme for the members of this structure is different from the
- * naming scheme found elsewhere in the code. The members of this structure are
- * defined in the Chapter 9 USB reference guide. Using this naming scheme makes
- * it easier for people familiar with the standard to read the code.
- */
-typedef struct {
- u8 bmRequestType; /**< bmRequestType in setup data */
- u8 bRequest; /**< bRequest in setup data */
- u16 wValue; /**< wValue in setup data */
- u16 wIndex; /**< wIndex in setup data */
- u16 wLength; /**< wLength in setup data */
-}
-XUsbPs_SetupData;
-
-
-/**
- * Data structures used to configure endpoints.
- */
-typedef struct {
- u32 Type;
- /**< Endpoint type:
- - XUSBPS_EP_TYPE_CONTROL
- - XUSBPS_EP_TYPE_ISOCHRONOUS
- - XUSBPS_EP_TYPE_BULK
- - XUSBPS_EP_TYPE_INTERRUPT */
-
- u32 NumBufs;
- /**< Number of buffers to be handled by this endpoint. */
- u32 BufSize;
- /**< Buffer size. Only relevant for OUT (receive) Endpoints. */
-
- u16 MaxPacketSize;
- /**< Maximum packet size for this endpoint. This number will
- * define the maximum number of bytes sent on the wire per
- * transaction. Range: 0..1024 */
-} XUsbPs_EpSetup;
-
-
-/**
- * Endpoint configuration structure.
- */
-typedef struct {
- XUsbPs_EpSetup Out; /**< OUT component of endpoint. */
- XUsbPs_EpSetup In; /**< IN component of endpoint. */
-} XUsbPs_EpConfig;
-
-
-/**
- * The XUsbPs_DeviceConfig structure contains the configuration information to
- * configure the USB controller for DEVICE mode. This data structure is used
- * with the XUsbPs_ConfigureDevice() function call.
- */
-typedef struct {
- u8 NumEndpoints; /**< Number of Endpoints for the controller.
- This number depends on the runtime
- configuration of driver. The driver may
- configure fewer endpoints than are available
- in the core. */
-
- XUsbPs_EpConfig EpCfg[XUSBPS_MAX_ENDPOINTS];
- /**< List of endpoint configurations. */
-
-
- u32 DMAMemPhys; /**< Physical base address of DMAable memory
- allocated for the driver. */
-
- /* The following members are used internally by the L0/L1 driver. They
- * MUST NOT be accesses and/or modified in any way by the upper layers.
- *
- * The reason for having these members is that we generally try to
- * avoid allocating memory in the L0/L1 driver as we want to be OS
- * independent. In order to avoid allocating memory for this data
- * structure wihin L0/L1 we put it into the XUsbPs_DeviceConfig
- * structure which is allocated by the caller.
- */
- XUsbPs_Endpoint Ep[XUSBPS_MAX_ENDPOINTS];
- /**< List of endpoint metadata structures. */
-
- u32 PhysAligned; /**< 64 byte aligned base address of the DMA
- memory block. Will be computed and set by
- the L0/L1 driver. */
-} XUsbPs_DeviceConfig;
-
-
-/**
- * The XUsbPs_Config structure contains configuration information for the USB
- * controller.
- *
- * This structure only contains the basic configuration for the controller. The
- * caller also needs to initialize the controller for the DEVICE mode
- * using the XUsbPs_DeviceConfig data structures with the
- * XUsbPs_ConfigureDevice() function call
- */
-typedef struct {
- u16 DeviceID; /**< Unique ID of controller. */
- u32 BaseAddress; /**< Core register base address. */
-} XUsbPs_Config;
-
-typedef XUsbPs_Config Usb_Config;
-
-struct Usb_DevData {
- u8 Speed;
- u8 State;
-
- void *PrivateData;
-};
-
-/**
- * The XUsbPs driver instance data. The user is required to allocate a
- * variable of this type for every USB controller in the system. A pointer to a
- * variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XUsbPs_SetupData SetupData;
- /**< Setup Packet buffer */
- XUsbPs_Config Config; /**< Configuration structure */
-
- int CurrentAltSetting; /**< Current alternative setting of interface */
-
- void *UserDataPtr; /**< Data pointer to be used by upper layers to
- store application dependent data structures.
- The upper layers are responsible to allocated
- and free the memory. The driver will not
- mofidy this data pointer. */
-
- /**
- * The following structures hold the configuration for DEVICE mode
- * of the controller. They are initialized using the
- * XUsbPs_ConfigureDevice() function call.
- */
- XUsbPs_DeviceConfig DeviceConfig;
- /**< Configuration for the DEVICE mode. */
-
- XUsbPs_IntrHandlerFunc HandlerFunc;
- /**< Handler function for the controller. */
- void *HandlerRef;
- /**< User data reference for the handler. */
- u32 HandlerMask;
- /**< User interrupt mask. Defines which interrupts will cause
- * the callback to be called. */
- struct Usb_DevData *AppData;
- u8 IsConfigDone;
- void *data_ptr; /* pointer for storing applications data */
-} XUsbPs;
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/******************************************************************************
- *
- * USB CONTROLLER RELATED MACROS
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
- * This macro returns the current frame number.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @return The current frame number.
- *
- * @note C-style signature:
- * u32 XUsbPs_GetFrameNum(const XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_GetFrameNum(InstancePtr) \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, XUSBPS_FRAME_OFFSET)
-
-
-/*****************************************************************************/
-/**
- * This macro starts the USB engine.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @note C-style signature:
- * void XUsbPs_Start(XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_Start(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
-
-
-/*****************************************************************************/
-/**
- * This macro stops the USB engine.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @note C-style signature:
- * void XUsbPs_Stop(XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_Stop(InstancePtr) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
-
-
-/*****************************************************************************/
-/**
- * This macro forces the USB engine to be in Full Speed (FS) mode.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @note C-style signature:
- * void XUsbPs_ForceFS(XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_ForceFS(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
- XUSBPS_PORTSCR_PFSC_MASK)
-
-
-/*****************************************************************************/
-/**
- * This macro starts the USB Timer 0, with repeat option for period of
- * one second.
- *
- * @param InstancePtr is a pointer to XUsbPs instance of the controller.
- * @param Interval is the interval for Timer0 to generate an interrupt
- *
- * @note C-style signature:
- * void XUsbPs_StartTimer0(XUsbPs *InstancePtr, u32 Interval)
- *
- ******************************************************************************/
-#define XUsbPs_StartTimer0(InstancePtr, Interval) \
-{ \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_TIMER0_LD_OFFSET, (Interval)); \
- XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
- XUSBPS_TIMER_RUN_MASK | \
- XUSBPS_TIMER_RESET_MASK | \
- XUSBPS_TIMER_REPEAT_MASK); \
-} \
-
-
-/*****************************************************************************/
-/**
-* This macro stops Timer 0.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_StopTimer0(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_StopTimer0(InstancePtr) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
- XUSBPS_TIMER_RUN_MASK)
-
-
-/*****************************************************************************/
-/**
-* This macro reads Timer 0.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_ReadTimer0(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_ReadTimer0(InstancePtr) \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_TIMER0_CTL_OFFSET) & \
- XUSBPS_TIMER_COUNTER_MASK
-
-
-/*****************************************************************************/
-/**
-* This macro force remote wakeup on host
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_RemoteWakeup(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_RemoteWakeup(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
- XUSBPS_PORTSCR_FPR_MASK)
-
-
-/******************************************************************************
- *
- * ENDPOINT RELATED MACROS
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
-* This macro enables the given endpoint for the given direction.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is number of the endpoint to enable.
-* @param Dir is direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpEnable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpEnable(InstancePtr, EpNum, Dir) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro disables the given endpoint for the given direction.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is the number of the endpoint to disable.
-* @param Dir is the direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpDisable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpDisable(InstancePtr, EpNum, Dir) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro stalls the given endpoint for the given direction, and flush
-* the buffers.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is number of the endpoint to stall.
-* @param Dir is the direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpStall(InstancePtr, EpNum, Dir) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro unstalls the given endpoint for the given direction.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is the Number of the endpoint to unstall.
-* @param Dir is the Direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpUnStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpUnStall(InstancePtr, EpNum, Dir) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro flush an endpoint upon interface disable
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is the number of the endpoint to flush.
-* @param Dir is the direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpFlush(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpFlush(InstancePtr, EpNum, Dir) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPFLUSH_OFFSET, \
- 1 << (EpNum + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? \
- XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT))) \
-
-/*****************************************************************************/
-/**
-* This macro enables the interrupts defined by the bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param IntrMask is the Bit mask of interrupts to be enabled.
-*
-* @note C-style signature:
-* void XUsbPs_IntrEnable(XUsbPs *InstancePtr, u32 IntrMask)
-*
-******************************************************************************/
-#define XUsbPs_IntrEnable(InstancePtr, IntrMask) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
-
-
-/*****************************************************************************/
-/**
-* This function disables the interrupts defined by the bit mask.
-*
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param IntrMask is a Bit mask of interrupts to be disabled.
-*
-* @note C-style signature:
-* void XUsbPs_IntrDisable(XUsbPs *InstancePtr, u32 IntrMask)
-*
-******************************************************************************/
-#define XUsbPs_IntrDisable(InstancePtr, IntrMask) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
-
-
-/*****************************************************************************/
-/**
-* This macro enables the endpoint NAK interrupts defined by the bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be
-* enabled.
-* @note C-style signature:
-* void XUsbPs_NakIntrEnable(XUsbPs *InstancePtr, u32 NakIntrMask)
-*
-******************************************************************************/
-#define XUsbPs_NakIntrEnable(InstancePtr, NakIntrMask) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
-
-
-/*****************************************************************************/
-/**
-* This macro disables the endpoint NAK interrupts defined by the bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param NakIntrMask is a Bit mask of endpoint NAK interrupts to be
-* disabled.
-*
-* @note
-* C-style signature:
-* void XUsbPs_NakIntrDisable(XUsbPs *InstancePtr, u32 NakIntrMask)
-*
-******************************************************************************/
-#define XUsbPs_NakIntrDisable(InstancePtr, NakIntrMask) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
-
-
-/*****************************************************************************/
-/**
-* This function clears the endpoint NAK interrupts status defined by the
-* bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be cleared.
-*
-* @note C-style signature:
-* void XUsbPs_NakIntrClear(XUsbPs *InstancePtr, u32 NakIntrMask)
-*
-******************************************************************************/
-#define XUsbPs_NakIntrClear(InstancePtr, NakIntrMask) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_EPNAKISR_OFFSET, NakIntrMask)
-
-
-
-/*****************************************************************************/
-/**
-* This macro sets the Interrupt Threshold value in the control register
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param Threshold is the Interrupt threshold to be set.
-* Allowed values:
-* - XUSBPS_CMD_ITHRESHOLD_0 - Immediate interrupt
-* - XUSBPS_CMD_ITHRESHOLD_1 - 1 Frame
-* - XUSBPS_CMD_ITHRESHOLD_2 - 2 Frames
-* - XUSBPS_CMD_ITHRESHOLD_4 - 4 Frames
-* - XUSBPS_CMD_ITHRESHOLD_8 - 8 Frames
-* - XUSBPS_CMD_ITHRESHOLD_16 - 16 Frames
-* - XUSBPS_CMD_ITHRESHOLD_32 - 32 Frames
-* - XUSBPS_CMD_ITHRESHOLD_64 - 64 Frames
-*
-* @note
-* C-style signature:
-* void XUsbPs_SetIntrThreshold(XUsbPs *InstancePtr, u8 Threshold)
-*
-******************************************************************************/
-#define XUsbPs_SetIntrThreshold(InstancePtr, Threshold) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_CMD_OFFSET, (Threshold))\
-
-
-/*****************************************************************************/
-/**
-* This macro sets the Tripwire bit in the USB command register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_SetTripwire(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_SetSetupTripwire(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, \
- XUSBPS_CMD_SUTW_MASK)
-
-
-/*****************************************************************************/
-/**
-* This macro clears the Tripwire bit in the USB command register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_ClrTripwire(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_ClrSetupTripwire(InstancePtr) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, \
- XUSBPS_CMD_SUTW_MASK)
-
-
-/*****************************************************************************/
-/**
-* This macro checks if the Tripwire bit in the USB command register is set.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @return
-* - TRUE: The tripwire bit is still set.
-* - FALSE: The tripwire bit has been cleared.
-*
-* @note C-style signature:
-* int XUsbPs_TripwireIsSet(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_SetupTripwireIsSet(InstancePtr) \
- (XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_CMD_OFFSET) & \
- XUSBPS_CMD_SUTW_MASK ? TRUE : FALSE)
-
-
-/******************************************************************************
-*
-* GENERAL REGISTER / BIT MANIPULATION MACROS
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-* This macro sets the given bit mask in the register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param RegOffset is the register offset to be written.
-* @param Bits is the Bits to be set in the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XUsbPs_SetBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
-*
-*****************************************************************************/
-#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- RegOffset) | (Bits));
-
-
-/****************************************************************************/
-/**
-*
-* This macro clears the given bits in the register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param RegOffset is the register offset to be written.
-* @param Bits are the bits to be cleared in the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XUsbPs_ClrBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
-*
-*****************************************************************************/
-#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- RegOffset) & ~(Bits));
-
-
-/************************** Function Prototypes ******************************/
-
-/**
- * Setup / Initialize functions.
- *
- * Implemented in file xusbps.c
- */
-int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
- const XUsbPs_Config *ConfigPtr, u32 BaseAddress);
-
-int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr,
- const XUsbPs_DeviceConfig *CfgPtr);
-
-/**
- * Common functions used for DEVICE/HOST mode.
- */
-int XUsbPs_Reset(XUsbPs *InstancePtr);
-
-void XUsbPs_DeviceReset(XUsbPs *InstancePtr);
-
-/**
- * DEVICE mode specific functions.
- */
-int XUsbPs_BusReset(XUsbPs *InstancePtr);
-int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address);
-
-
-/**
- * Handling Suspend and Resume.
- *
- * Implemented in xusbps.c
- */
-int XUsbPs_Suspend(const XUsbPs *InstancePtr);
-int XUsbPs_Resume(const XUsbPs *InstancePtr);
-int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr);
-
-
-/*
- * Functions for managing Endpoints / Transfers
- *
- * Implemented in file xusbps_endpoint.c
- */
-int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum,
- const u8 *BufferPtr, u32 BufferLen);
-int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum,
- const u8 *BufferPtr, u32 BufferLen);
-int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
- u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle);
-void XUsbPs_EpBufferRelease(u32 Handle);
-
-int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
- XUsbPs_EpHandlerFunc CallBackFunc,
- void *CallBackRef);
-s32 XUsbPs_EpSetIsoHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
- XUsbPs_EpIsoHandlerFunc CallBackFunc);
-int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum,
- XUsbPs_SetupData *SetupDataPtr);
-
-int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction);
-
-int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr,
- int EpNum, unsigned short NewDirection, int DirectionChanged);
-
-/*
- * Interrupt handling functions
- *
- * Implemented in file xusbps_intr.c
- */
-void XUsbPs_IntrHandler(void *InstancePtr);
-
-int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
- XUsbPs_IntrHandlerFunc CallBackFunc,
- void *CallBackRef, u32 Mask);
-void XUsbPs_EpGetData(XUsbPs *InstancePtr, u8 EpNum, u32 BufferLen);
-
-s32 XUsbPs_EpDataBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
- u8 *BufferPtr, u32 BufferLen);
-/*
- * Helper functions for static configuration.
- * Implemented in xusbps_sinit.c
- */
-XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceId);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XUSBPS_H */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/40/626fcb585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/40/626fcb585243001d18b399c1eb9b3628
deleted file mode 100644
index fa58233..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/40/626fcb585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,78 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_spinlock.h
-*
-* This header file contains function prototypes to be used while using Xilinx
-* spinlocking mechanism.
-* Please refer to file header contents of xil_spinlock.c to understand in
-* detail the spinlocking mechanism.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 7.5 asa 02/16/21 First release
-* 7.6 sk 08/05/21 Add Boolean check and braces for Xil_IsSpinLockEnabled
-* if condition to fix misrac violations.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00 drg/jz 01/13/10 First Release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xstatus.h"
-#include "xparameters.h"
-#include "xuartps.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-extern XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES];
-
-/************************** Function Prototypes *****************************/
-
-/****************************************************************************/
-/**
-*
-* Looks up the device configuration based on the unique device ID. The table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId contains the ID of the device
-*
-* @return A pointer to the configuration structure or NULL if the
-* specified device is not in the system.
-*
-* @note None.
-*
-******************************************************************************/
-XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId)
-{
- XUartPs_Config *CfgPtr = NULL;
-
- u32 Index;
-
- for (Index = 0U; Index < (u32)XPAR_XUARTPS_NUM_INSTANCES; Index++) {
- if (XUartPs_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XUartPs_ConfigTable[Index];
- break;
- }
- }
-
- return (XUartPs_Config *)CfgPtr;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/40/d13691565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/40/d13691565243001d18b399c1eb9b3628
deleted file mode 100644
index d72dfa4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/40/d13691565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,53 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2008 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-* microblaze_flush_cache_ext_range (unsigned int cacheaddr, unsigned int len)
-*
-*Flush a L2 Cache range
-*
-*Parameters:
-* 'cacheaddr' - address in the L2 cache where the flush begins
-* 'len ' - length (in bytes) worth of L2 cache to be flushed
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-#include "microblaze_instructions.h"
-
-#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
-
- .text
- .globl microblaze_flush_cache_ext_range
- .ent microblaze_flush_cache_ext_range
- .align 2
-
-microblaze_flush_cache_ext_range:
-#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
- beqi r6, Loop_done
-
- ADDIK r6, r6, -1
- ADD r6, r5, r6
-
- ANDI r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
- ANDI r5, r5, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
-
- RSUBK r6, r5, r6
-Loop_start:
- wdc.ext.flush r5, r6
-#if defined (__arch64__ )
- addlik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
- beagei r6, Loop_start
-#else
- bneid r6, Loop_start
- addik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
-#endif
-
-Loop_done:
-#endif
- rtsd r15, 8
- nop
-
- .end microblaze_flush_cache_ext_range
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/41/806f5b585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/41/806f5b585243001d18b399c1eb9b3628
deleted file mode 100644
index 166f2bb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/41/806f5b585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,454 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file boot.S
-*
-* @addtogroup a53_64_boot_code Cortex A53 64bit Processor Boot Code
-* @{
-*
boot.S
-*
-* The boot code performs minimum configuration which is required for an
-* application. Cortex-A53 starts by checking current exception level. If the
-* current exception level is EL3 and BSP is built for EL3, it will do
-* initialization required for application execution at EL3. Below is a
-* sequence illustrating what all configuration is performed before control
-* reaches to main function for EL3 execution.
-*
-* 1. Program vector table base for exception handling
-* 2. Set reset vector table base address
-* 3. Program stack pointer for EL3
-* 4. Routing of interrupts to EL3
-* 5. Enable ECC protection
-* 6. Program generic counter frequency
-* 7. Invalidate instruction cache, data cache and TLBs
-* 8. Configure MMU registers and program base address of translation table
-* 9. Transfer control to _start which clears BSS sections and runs global
-* constructor before jumping to main application
-*
-* If the current exception level is EL1 and BSP is also built for EL1_NONSECURE
-* it will perform initialization required for application execution at EL1
-* non-secure. For all other combination, the execution will go into infinite
-* loop. Below is a sequence illustrating what all configuration is performed
-* before control reaches to main function for EL1 execution.
-*
-* 1. Program vector table base for exception handling
-* 2. Program stack pointer for EL1
-* 3. Invalidate instruction cache, data cache and TLBs
-* 4. Configure MMU registers and program base address of translation table
-* 5. Transfer control to _start which clears BSS sections and runs global
-* constructor before jumping to main application
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 5.00 pkp 05/21/14 Initial version
-* 6.00 pkp 07/25/16 Program the counter frequency
-* 6.02 pkp 01/22/17 Added support for EL1 non-secure
-* 6.02 pkp 01/24/17 Clearing status of FPUStatus variable to ensure it
-* holds correct value.
-* 6.3 mus 04/20/17 CPU Cache protection bit in the L2CTLR_EL1 will be in
-* set state on reset. So, setting that bit through boot
-* code is redundant, hence removed the code which sets
-* CPU cache protection bit.
-* 6.4 mus 08/11/17 Implemented ARM erratum 855873.It fixes
-* CR#982209.
-* 6.6 mus 01/19/18 Added isb after writing to the cpacr_el1/cptr_el3,
-* to ensure floating-point unit is disabled, before
-* any subsequent instruction.
-* 7.0 mus 03/26/18 Updated TCR_EL3/TCR_EL1 as per versal address map
-* 7.3 mus 04/24/20 Corrected CPACR_EL1 handling at EL1 NS
-*
-*
-*
-******************************************************************************/
-
-#include "xparameters.h"
-#include "bspconfig.h"
-#include "xil_errata.h"
-
-.globl MMUTableL0
-.globl MMUTableL1
-.globl MMUTableL2
-.global _prestart
-.global _boot
-
-.global __el3_stack
-.global __el2_stack
-.global __el1_stack
-.global __el0_stack
-.global _vector_table
-
-.set EL3_stack, __el3_stack
-.set EL2_stack, __el2_stack
-.set EL1_stack, __el1_stack
-.set EL0_stack, __el0_stack
-
-.set TT_S1_FAULT, 0x0
-.set TT_S1_TABLE, 0x3
-
-.set L0Table, MMUTableL0
-.set L1Table, MMUTableL1
-.set L2Table, MMUTableL2
-.set vector_base, _vector_table
-.set rvbar_base, 0xFD5C0040
-
-#if defined (versal)
-.set counterfreq, XPAR_CPU_CORTEXA72_0_TIMESTAMP_CLK_FREQ
-#else
-.set counterfreq, XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ
-#endif
-
-.set MODE_EL1, 0x5
-.set DAIF_BIT, 0x1C0
-
-.section .boot,"ax"
-
-
-/* this initializes the various processor modes */
-
-_prestart:
-_boot:
- mov x0, #0
- mov x1, #0
- mov x2, #0
- mov x3, #0
- mov x4, #0
- mov x5, #0
- mov x6, #0
- mov x7, #0
- mov x8, #0
- mov x9, #0
- mov x10, #0
- mov x11, #0
- mov x12, #0
- mov x13, #0
- mov x14, #0
- mov x15, #0
- mov x16, #0
- mov x17, #0
- mov x18, #0
- mov x19, #0
- mov x20, #0
- mov x21, #0
- mov x22, #0
- mov x23, #0
- mov x24, #0
- mov x25, #0
- mov x26, #0
- mov x27, #0
- mov x28, #0
- mov x29, #0
- mov x30, #0
-#if 0 //don't put other a53 cpus in wfi
- //Which core am I
- // ----------------
- mrs x0, MPIDR_EL1
- and x0, x0, #0xFF //Mask off to leave Aff0
- cbz x0, OKToRun //If core 0, run the primary init code
-EndlessLoop0:
- wfi
- b EndlessLoop0
-#endif
-OKToRun:
-
- mrs x0, currentEL
- cmp x0, #0xC
- beq InitEL3
-
- cmp x0, #0x4
- beq InitEL1
-
- b error // go to error if current exception level is neither EL3 nor EL1
-InitEL3:
-.if (EL3 == 1)
- /*Set vector table base address*/
- ldr x1, =vector_base
- msr VBAR_EL3,x1
-
- /* Set reset vector address */
- /* Get the cpu ID */
- mrs x0, MPIDR_EL1
- and x0, x0, #0xFF
- mov w0, w0
- ldr w2, =rvbar_base
- /* calculate the rvbar base address for particular CPU core */
- mov w3, #0x8
- mul w0, w0, w3
- add w2, w2, w0
- /* store vector base address to RVBAR */
- str x1, [x2]
-
- /*Define stack pointer for current exception level*/
- ldr x2,=EL3_stack
- mov sp,x2
-
- /* Enable Trapping of SIMD/FPU register for standalone BSP */
- mov x0, #0
-#ifndef FREERTOS_BSP
- orr x0, x0, #(0x1 << 10)
-#endif
- msr CPTR_EL3, x0
- isb
-
- /*
- * Clear FPUStatus variable to make sure that it contains current
- * status of FPU i.e. disabled. In case of a warm restart execution
- * when bss sections are not cleared, it may contain previously updated
- * value which does not hold true now.
- */
-#ifndef FREERTOS_BSP
- ldr x0,=FPUStatus
- str xzr, [x0]
-#endif
- /* Configure SCR_EL3 */
- mov w1, #0 //; Initial value of register is unknown
- orr w1, w1, #(1 << 11) //; Set ST bit (Secure EL1 can access CNTPS_TVAL_EL1, CNTPS_CTL_EL1 & CNTPS_CVAL_EL1)
- orr w1, w1, #(1 << 10) //; Set RW bit (EL1 is AArch64, as this is the Secure world)
- orr w1, w1, #(1 << 3) //; Set EA bit (SError routed to EL3)
- orr w1, w1, #(1 << 2) //; Set FIQ bit (FIQs routed to EL3)
- orr w1, w1, #(1 << 1) //; Set IRQ bit (IRQs routed to EL3)
- msr SCR_EL3, x1
-
- /*configure cpu auxiliary control register EL1 */
- ldr x0,=0x80CA000 // L1 Data prefetch control - 5, Enable device split throttle, 2 independent data prefetch streams
-#if CONFIG_ARM_ERRATA_855873
- /*
- * Set ENDCCASCI bit in CPUACTLR_EL1 register, to execute data
- * cache clean operations as data cache clean and invalidate
- *
- */
- orr x0, x0, #(1 << 44) //; Set ENDCCASCI bit
-#endif
- msr S3_1_C15_C2_0, x0 //CPUACTLR_EL1
-
- /* program the counter frequency */
- ldr x0,=counterfreq
- msr CNTFRQ_EL0, x0
-
- /*Enable hardware coherency between cores*/
- mrs x0, S3_1_c15_c2_1 //Read EL1 CPU Extended Control Register
- orr x0, x0, #(1 << 6) //Set the SMPEN bit
- msr S3_1_c15_c2_1, x0 //Write EL1 CPU Extended Control Register
- isb
-
- tlbi ALLE3
- ic IALLU //; Invalidate I cache to PoU
- bl invalidate_dcaches
- dsb sy
- isb
-
- ldr x1, =L0Table //; Get address of level 0 for TTBR0_EL3
- msr TTBR0_EL3, x1 //; Set TTBR0_EL3
-
- /**********************************************
- * Set up memory attributes
- * This equates to:
- * 0 = b01000100 = Normal, Inner/Outer Non-Cacheable
- * 1 = b11111111 = Normal, Inner/Outer WB/WA/RA
- * 2 = b00000000 = Device-nGnRnE
- * 3 = b00000100 = Device-nGnRE
- * 4 = b10111011 = Normal, Inner/Outer WT/WA/RA
- **********************************************/
- ldr x1, =0x000000BB0400FF44
- msr MAIR_EL3, x1
-
-#if defined (versal)
- /**********************************************
- * Set up TCR_EL3
- * Physical Address Size PS = 100 -> 44bits 16 TB
- * Granual Size TG0 = 00 -> 4KB
- * size offset of the memory region T0SZ = 20 -> (region size 2^(64-20) = 2^44)
- ***************************************************/
- ldr x1,=0x80843514
-#else
- /**********************************************
- * Set up TCR_EL3
- * Physical Address Size PS = 010 -> 40bits 1TB
- * Granual Size TG0 = 00 -> 4KB
- * size offset of the memory region T0SZ = 24 -> (region size 2^(64-24) = 2^40)
- ***************************************************/
- ldr x1,=0x80823518
-#endif
- msr TCR_EL3, x1
- isb
-
- /* Enable SError Exception for asynchronous abort */
- mrs x1,DAIF
- bic x1,x1,#(0x1<<8)
- msr DAIF,x1
-
- /* Configure SCTLR_EL3 */
- mov x1, #0 //Most of the SCTLR_EL3 bits are unknown at reset
- orr x1, x1, #(1 << 12) //Enable I cache
- orr x1, x1, #(1 << 3) //Enable SP alignment check
- orr x1, x1, #(1 << 2) //Enable caches
- orr x1, x1, #(1 << 0) //Enable MMU
- msr SCTLR_EL3, x1
- dsb sy
- isb
-
- b _startup //jump to start
-.else
- b error // present exception level and selected exception level mismatch
-.endif
-
-InitEL1:
-.if (EL1_NONSECURE == 1)
- /*Set vector table base address*/
- ldr x1, =vector_base
- msr VBAR_EL1,x1
-
- /* Trap floating point access only in case of standalone BSP */
-#ifdef FREERTOS_BSP
- mrs x0, CPACR_EL1
- orr x0, x0, #(0x3 << 20)
- msr CPACR_EL1, x0
-#else
- mrs x0, CPACR_EL1
- bic x0, x0, #(0x3 << 20)
- msr CPACR_EL1, x0
-#endif
- isb
-
- /*
- * Clear FPUStatus variable to make sure that it contains current
- * status of FPU i.e. disabled. In case of a warm restart execution
- * when bss sections are not cleared, it may contain previously updated
- * value which does not hold true now.
- */
-#ifndef FREERTOS_BSP
- ldr x0,=FPUStatus
- str xzr, [x0]
-#endif
- /*Define stack pointer for current exception level*/
- ldr x2,=EL1_stack
- mov sp,x2
-
- /* Disable MMU first */
- mov x1,#0x0
- msr SCTLR_EL1, x1
- isb
-
- TLBI VMALLE1
-
- ic IALLU //; Invalidate I cache to PoU
- bl invalidate_dcaches
- dsb sy
- isb
-
- ldr x1, =L0Table //; Get address of level 0 for TTBR0_EL1
- msr TTBR0_EL1, x1 //; Set TTBR0_EL1
-
- /**********************************************
- * Set up memory attributes
- * This equates to:
- * 0 = b01000100 = Normal, Inner/Outer Non-Cacheable
- * 1 = b11111111 = Normal, Inner/Outer WB/WA/RA
- * 2 = b00000000 = Device-nGnRnE
- * 3 = b00000100 = Device-nGnRE
- * 4 = b10111011 = Normal, Inner/Outer WT/WA/RA
- **********************************************/
- ldr x1, =0x000000BB0400FF44
- msr MAIR_EL1, x1
-
- #if defined (versal)
- /**********************************************
- * Set up TCR_EL1
- * Physical Address Size PS = 100 -> 44bits 16TB
- * Granual Size TG0 = 00 -> 4KB
- * size offset of the memory region T0SZ = 20 -> (region size 2^(64-20) = 2^44)
- ***************************************************/
- ldr x1,=0x485800514
- #else
- /**********************************************
- * Set up TCR_EL1
- * Physical Address Size PS = 010 -> 44bits 16TB
- * Granual Size TG0 = 00 -> 4KB
- * size offset of the memory region T0SZ = 24 -> (region size 2^(64-24) = 2^40)
- ***************************************************/
- ldr x1,=0x285800518
- #endif
- msr TCR_EL1, x1
- isb
- /* Enable SError Exception for asynchronous abort */
- mrs x1,DAIF
- bic x1,x1,#(0x1<<8)
- msr DAIF,x1
-
- //; Enable MMU
- mov x1,#0x0
- orr x1, x1, #(1 << 18) // ; Set WFE non trapping
- orr x1, x1, #(1 << 17) // ; Set WFI non trapping
- orr x1, x1, #(1 << 5) // ; Set CP15 barrier enabled
- orr x1, x1, #(1 << 12) // ; Set I bit
- orr x1, x1, #(1 << 2) // ; Set C bit
- orr x1, x1, #(1 << 0) // ; Set M bit
- msr SCTLR_EL1, x1
- isb
-
- bl _startup //jump to start
-.else
- b error // present exception level and selected exception level mismatch
-.endif
-
-error: b error
-
-
-invalidate_dcaches:
-
- dmb ISH
- mrs x0, CLIDR_EL1 //; x0 = CLIDR
- ubfx w2, w0, #24, #3 //; w2 = CLIDR.LoC
- cmp w2, #0 //; LoC is 0?
- b.eq invalidateCaches_end //; No cleaning required and enable MMU
- mov w1, #0 //; w1 = level iterator
-
-invalidateCaches_flush_level:
- add w3, w1, w1, lsl #1 //; w3 = w1 * 3 (right-shift for cache type)
- lsr w3, w0, w3 //; w3 = w0 >> w3
- ubfx w3, w3, #0, #3 //; w3 = cache type of this level
- cmp w3, #2 //; No cache at this level?
- b.lt invalidateCaches_next_level
-
- lsl w4, w1, #1
- msr CSSELR_EL1, x4 //; Select current cache level in CSSELR
- isb //; ISB required to reflect new CSIDR
- mrs x4, CCSIDR_EL1 //; w4 = CSIDR
-
- ubfx w3, w4, #0, #3
- add w3, w3, #2 //; w3 = log2(line size)
- ubfx w5, w4, #13, #15
- ubfx w4, w4, #3, #10 //; w4 = Way number
- clz w6, w4 //; w6 = 32 - log2(number of ways)
-
-invalidateCaches_flush_set:
- mov w8, w4 //; w8 = Way number
-invalidateCaches_flush_way:
- lsl w7, w1, #1 //; Fill level field
- lsl w9, w5, w3
- orr w7, w7, w9 //; Fill index field
- lsl w9, w8, w6
- orr w7, w7, w9 //; Fill way field
- dc CISW, x7 //; Invalidate by set/way to point of coherency
- subs w8, w8, #1 //; Decrement way
- b.ge invalidateCaches_flush_way
- subs w5, w5, #1 //; Descrement set
- b.ge invalidateCaches_flush_set
-
-invalidateCaches_next_level:
- add w1, w1, #1 //; Next level
- cmp w2, w1
- b.gt invalidateCaches_flush_level
-
-invalidateCaches_end:
- ret
-
-.end
-/**
-* @} End of "addtogroup a53_64_boot_code".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/41/b14ace575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/41/b14ace575243001d18b399c1eb9b3628
deleted file mode 100644
index d039278..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/41/b14ace575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,267 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xdmaps_hw.h
-* @addtogroup dmaps_v2_8
-* @{
-*
-* This header file contains the hardware interface of an XDmaPs device.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ----------------------------------------------
-* 1.00a hbm 08/18/10 First Release
-* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
-* the maximum number of channels.
-* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
-* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
-* 1.02a sg 05/16/12 Made changes for doxygen
-* 1.06a kpc 07/10/13 Added function prototype
-*
-*
-******************************************************************************/
-
-#ifndef XDMAPS_HW_H /* prevent circular inclusions */
-#define XDMAPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets for the DMAC.
- * @{
- */
-
-#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */
-#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */
-#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */
-#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */
-#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register
- */
-#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */
-#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager
- * Register
- */
-#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register
- */
-#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */
-
-#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */
-/*
- * The offset for the rest of the FTC registers is calculated as
- * FTC0 + dev_chan_num * 4
- */
-#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4)
-
-#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */
-/*
- * The offset for the rest of the CS registers is calculated as
- * CS0 + * dev_chan_num * 0x08
- */
-#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8)
-
-#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA
- * Channel 0
- */
-/*
- * The offset for the rest of the CPC registers is calculated as
- * CPC0 + dev_chan_num * 0x08
- */
-#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8)
-
-#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA
- * Channel 0
- */
-/* The offset for the rest of the SA registers is calculated as
- * SA_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for
- * DMA Channel 0
- */
-/* The offset for the rest of the DA registers is calculated as
- * DA_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for
- * DMA Channel 0
- */
-/*
- * The offset for the rest of the CC registers is calculated as
- * CC_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */
-/*
- * The offset for the rest of the LC0 registers is calculated as
- * LC_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20)
-#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */
-/*
- * The offset for the rest of the LC1 registers is calculated as
- * LC_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */
-#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */
-#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */
-#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */
-
-#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */
-#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */
-#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */
-#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */
-#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */
-#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */
-
-#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification
- * Register 0
- */
-#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification
- * Register 1
- */
-#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification
- * Register 2
- */
-#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification
- * Register 3
- */
-#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification
- * Register 0
- */
-#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification
- * Register 1
- */
-#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification
- * Register 2
- */
-#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification
- * Register 3
- */
-
-/*
- * Some useful register masks
- */
-#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */
-#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */
-
-#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */
-
-#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask,
- * llast 3 bits of CS register
- */
-
-#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */
-
-
-/*
- * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register.
- * @b1: Instruction byte 1
- * @b0: Instruction byte 0
- * @ch: Channel number
- * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel
- */
-#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \
- (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1)))
-
-/* @} */
-
-/** @name Control Register
- *
- * The Control register (CR) controls the major functions of the device.
- *
- * Control Register Bit Definition
- */
-
-/* @}*/
-
-
-#define XDMAPS_CHANNELS_PER_DEV 8
-
-
-/** @name Mode Register
- *
- * The mode register (MR) defines the mode of transfer as well as the data
- * format. If this register is modified during transmission or reception,
- * data validity cannot be guaranteed.
- *
- * Mode Register Bit Definition
- * @{
- */
-
-/* @} */
-
-
-/** @name Interrupt Registers
- *
- * Interrupt control logic uses the interrupt enable register (IER) and the
- * interrupt disable register (IDR) to set the value of the bits in the
- * interrupt mask register (IMR). The IMR determines whether to pass an
- * interrupt to the interrupt status register (ISR).
- * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
- * interrupt. IMR and ISR are read only, and IER and IDR are write only.
- * Reading either IER or IDR returns 0x00.
- *
- * All four registers have the same bit definitions.
- *
- * @{
- */
-
-/* @} */
-#define XDMAPS_INTCLR_ALL_MASK 0xFF
-
-#define XDmaPs_ReadReg(BaseAddress, RegOffset) \
- Xil_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write a DMAC register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the base address of the device.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note
-* C-Style signature:
-* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u32 RegisterValue)
-******************************************************************************/
-#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes *****************************/
-/*
- * Perform reset operation to the dmaps interface
- */
-void XDmaPs_ResetHw(u32 BaseAddr);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/41/c0be4d595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/41/c0be4d595243001d18b399c1eb9b3628
deleted file mode 100644
index 0036459..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/41/c0be4d595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,14 +0,0 @@
-#include "xparameters.h"
-#include "xuartps_hw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-char inbyte(void);
-#ifdef __cplusplus
-}
-#endif
-
-char inbyte(void) {
- return XUartPs_RecvByte(STDIN_BASEADDRESS);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/42/237695595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/42/237695595243001d18b399c1eb9b3628
deleted file mode 100644
index 29be8d2..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/42/237695595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,73 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#ifndef XDEBUG
-#define XDEBUG
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(DEBUG) && !defined(NDEBUG)
-
-#ifndef XDEBUG_WARNING
-#define XDEBUG_WARNING
-#warning DEBUG is enabled
-#endif
-
-int printf(const char *format, ...);
-
-#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */
-#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */
-#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */
-
-#define XDBG_DEBUG_FIFO_REG 0x00000100U /* display register reads/writes */
-#define XDBG_DEBUG_FIFO_RX 0x00000101U /* receive debug messages */
-#define XDBG_DEBUG_FIFO_TX 0x00000102U /* transmit debug messages */
-#define XDBG_DEBUG_FIFO_ALL 0x0000010FU /* all fifo debug messages */
-
-#define XDBG_DEBUG_TEMAC_REG 0x00000400U /* display register reads/writes */
-#define XDBG_DEBUG_TEMAC_RX 0x00000401U /* receive debug messages */
-#define XDBG_DEBUG_TEMAC_TX 0x00000402U /* transmit debug messages */
-#define XDBG_DEBUG_TEMAC_ALL 0x0000040FU /* all temac debug messages */
-
-#define XDBG_DEBUG_TEMAC_ADPT_RX 0x00000800U /* receive debug messages */
-#define XDBG_DEBUG_TEMAC_ADPT_TX 0x00000801U /* transmit debug messages */
-#define XDBG_DEBUG_TEMAC_ADPT_IOCTL 0x00000802U /* ioctl debug messages */
-#define XDBG_DEBUG_TEMAC_ADPT_MISC 0x00000803U /* debug msg for other routines */
-#define XDBG_DEBUG_TEMAC_ADPT_ALL 0x0000080FU /* all temac adapter debug messages */
-
-
-#define xdbg_current_types (XDBG_DEBUG_GENERAL | XDBG_DEBUG_ERROR | XDBG_DEBUG_TEMAC_REG | XDBG_DEBUG_FIFO_RX | XDBG_DEBUG_FIFO_TX | XDBG_DEBUG_FIFO_REG)
-
-#define xdbg_stmnt(x) x
-
-/* In VxWorks, if _WRS_GNU_VAR_MACROS is defined, special syntax is needed for
- * macros that accept variable number of arguments
- */
-#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
-#define xdbg_printf(type, args...) (((type) & xdbg_current_types) ? printf (## args) : 0)
-#else /* ANSI Syntax */
-#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
-#endif
-
-#else /* defined(DEBUG) && !defined(NDEBUG) */
-
-#define xdbg_stmnt(x)
-
-/* See VxWorks comments above */
-#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
-#define xdbg_printf(type, args...)
-#else /* ANSI Syntax */
-#define xdbg_printf(...)
-#endif
-#endif /* defined(DEBUG) && !defined(NDEBUG) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XDEBUG */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/42/80be4b555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/42/80be4b555243001d18b399c1eb9b3628
deleted file mode 100644
index 03d84cd..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/42/80be4b555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * xen_console.h
- *
- * Created on: Sep 14, 2016
- * Author: jarvis
- */
-/*
-Copyright DornerWorks 2016
-
-Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-following conditions are met:
-1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
-following disclaimer.
-
-THIS SOFTWARE IS PROVIDED BY DORNERWORKS FOR USE ON THE CONTRACTED PROJECT, AND ANY EXPRESS OR IMPLIED WARRANTY
-IS LIMITED TO THIS USE. FOR ALL OTHER USES THIS SOFTWARE IS PROVIDED ''AS IS'' AND ANY EXPRESS OR IMPLIED
-WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL DORNERWORKS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-#ifndef _XEN_CONSOLE_H_
-
-typedef void (*callback_func)(char* data, int size);
-
-void printk(const char *fmt, ...);
-void init_console(void);
-void register_console_callback(callback_func fptr);
-int XPVXenConsole_Printf(const char *FormatPtr, ...);
-void XPVXenConsole_Init(void);
-int XPVXenConsole_Write(const char *BufferPtr);
-
-#define _XEN_CONSOLE_H_
-
-
-
-#endif /* _XEN_CONSOLE_H_ */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/42/80daf3545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/42/80daf3545243001d18b399c1eb9b3628
deleted file mode 100644
index 2782826..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/42/80daf3545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,342 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xsdps.h
-* @addtogroup sdps_v3_13
-* @{
-* @details
-*
-* This file contains the implementation of XSdPs driver.
-* This driver is used initialize read from and write to the SD card.
-* Features such as switching bus width to 4-bit and switching to high speed,
-* changing clock frequency, block size etc. are supported.
-* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
-* is done using 1-bit bus width and 400KHz clock frequency.
-* SD commands are classified as broadcast and addressed. Commands can be
-* those with response only (using only command line) or
-* response + data (using command and data lines).
-* Only one command can be sent at a time. During a data transfer however,
-* when dsta lines are in use, certain commands (which use only the command
-* line) can be sent, most often to obtain status.
-* This driver does not support multi card slots at present.
-*
-* Initialization:
-* This includes initialization on the host controller side to select
-* clock frequency, bus power and default transfer related parameters.
-* The default voltage is 3.3V.
-* On the SD card side, the initialization and identification state diagram is
-* implemented. This resets the card, gives it a unique address/ID and
-* identifies key card related specifications.
-*
-* Data transfer:
-* The SD card is put in transfer state to read from or write to it.
-* The default block size is 512 bytes and if supported,
-* default bus width is 4-bit and bus speed is High speed.
-* The read and write functions are implemented in polled mode using ADMA2.
-*
-* At any point, when key parameters such as block size or
-* clock/speed or bus width are modified, this driver takes care of
-* maintaining the same selection on host and card.
-* All error bits in host controller are monitored by the driver and in the
-* event one of them is set, driver will clear the interrupt status and
-* communicate failure to the upper layer.
-*
-* File system use:
-* This driver can be used with xilffs library to read and write files to SD.
-* (Please refer to procedure in diskio.c). The file system read/write example
-* in polled mode can used for reference.
-*
-* There is no example for using SD driver without file system at present.
-* However, the driver can be used without the file system. The glue layer
-* in filesystem can be used as reference for the same. The block count
-* passed to the read/write function in one call is limited by the ADMA2
-* descriptor table and hence care will have to be taken to call read/write
-* API's in a loop for large file sizes.
-*
-* Interrupt mode is not supported because it offers no improvement when used
-* with file system.
-*
-* eMMC support:
-* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
-* The features of eMMC supported by the driver will depend on those supported
-* by the host controller. The current driver supports read/write on eMMC card
-* using 4-bit and high speed mode currently.
-*
-* Features not supported include - card write protect, password setting,
-* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
-* 64-bit addressed ADMA2, erase/pre-erase commands.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a hk/sg 10/17/13 Initial release
-* 2.0 hk 03/07/14 Version number revised.
-* 2.1 hk 04/18/14 Increase sleep for eMMC switch command.
-* Add sleep for microblaze designs. CR# 781117.
-* 2.2 hk 07/28/14 Make changes to enable use of data cache.
-* 2.3 sk 09/23/14 Send command for relative card address
-* when re-initialization is done.CR# 819614.
-* Use XSdPs_Change_ClkFreq API whenever changing
-* clock.CR# 816586.
-* 2.4 sk 12/04/14 Added support for micro SD without
-* WP/CD. CR# 810655.
-* Checked for DAT Inhibit mask instead of CMD
-* Inhibit mask in Cmd Transfer API.
-* Added Support for SD Card v1.0
-* 2.5 sg 07/09/15 Added SD 3.0 features
-* kvn 07/15/15 Modified the code according to MISRAC-2012.
-* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
-* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
-* sk 12/10/15 Added support for MMC cards.
-* 01/08/16 Added workaround for issue in auto tuning mode
-* of SDR50, SDR104 and HS200.
-* sk 02/16/16 Corrected the Tuning logic.
-* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
-* 2.8 sk 04/20/16 Added new workaround for auto tuning.
-* 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
-* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
-* sk 07/16/16 Added support for UHS modes.
-* sk 07/07/16 Used usleep API for both arm and microblaze.
-* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
-* operating modes.
-* sk 08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
-* CR#956899.
-* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
-* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
-* sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
-* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
-* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value.
-* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
-* sk 02/01/17 Added HSD and DDR mode support for eMMC.
-* sk 02/01/17 Consider bus width parameter from design for switching
-* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
-* sk 03/20/17 Add support for EL1 non-secure mode.
-* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
-* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
-* mn 08/17/17 Enabled CCI support for A53 by adding cache coherency
-* information.
-* mn 09/06/17 Resolved compilation errors with IAR toolchain
-* 3.6 mn 08/01/18 Add support for using 64Bit DMA with 32-Bit Processor
-* 3.7 mn 02/01/19 Add support for idling of SDIO
-* 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
-* mn 09/17/19 Modified ADMA handling API for 32bit and 64bit addresses
-* 3.9 mn 03/03/20 Restructured the code for more readability and modularity
-* mn 03/16/20 Move XSdPs_Select_Card API to User APIs
-* 3.10 mn 06/05/20 Check Transfer completion separately from XSdPs_Read and
-* XSdPs_Write APIs
-* mn 06/05/20 Modified code for SD Non-Blocking Read support
-* 3.11 sk 12/01/20 Tap programming sequence updates like disable OTAPEN
-* always, write zero to tap register for zero tap value.
-* sk 12/07/20 Fix eMMC DDR52 mode write/read issue.
-* sk 12/17/20 Removed checking platform specific SD macros and used
-* Baseaddress instead.
-* 3.12 sk 01/28/21 Added support for non-blocking write.
-* sk 02/12/21 Fix the issue in reading CID and CSD.
-* sk 04/08/21 Fixed doxygen warnings in all source files.
-* sk 05/25/21 Fix the compilation issue in Cortex-A72 + EL1_NS by
-* removing the DLL reset logic (Dead code for Versal).
-* 3.13 sk 08/10/21 Limit the SD operating frequency to 19MHz for Versal.
-*
-*
-*
-******************************************************************************/
-
-
-#ifndef SDPS_H_
-#define SDPS_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xil_printf.h"
-#include "xil_cache.h"
-#include "xstatus.h"
-#include "xsdps_hw.h"
-#include "xplatform_info.h"
-#include "sleep.h"
-#include
-#if defined (XCLOCKING)
-#include "xil_clocking.h"
-#endif
-
-/************************** Constant Definitions *****************************/
-
-#define XSDPS_CT_ERROR 0x2L /**< Command timeout flag */
-#define MAX_TUNING_COUNT 40U /**< Maximum Tuning count */
-#define MAX_TIMEOUT 0x1FFFFFFFU /**< Maximum Timeout */
-#define XSDPS_CMD8_VOL_PATTERN 0x1AAU /**< CMD8 voltage pattern */
-#define XSDPS_RESPOCR_READY 0x80000000U /**< Ready response */
-#define XSDPS_ACMD41_HCS 0x40000000U /**< High Capacity Support */
-#define XSDPS_ACMD41_3V3 0x00300000U /**< 3.3 voltage support */
-#define XSDPS_CMD1_HIGH_VOL 0x00FF8000U /**< CMD1 for High voltage */
-#define XSDPS_CMD1_DUAL_VOL 0x00FF8010U /**< CMD1 for Dual voltage */
-#define HIGH_SPEED_SUPPORT 0x2U /**< High Speed support */
-#define UHS_SDR12_SUPPORT 0x1U /**< SDR12 support */
-#define UHS_SDR25_SUPPORT 0x2U /**< SDR25 support */
-#define UHS_SDR50_SUPPORT 0x4U /**< SDR50 support */
-#define UHS_SDR104_SUPPORT 0x8U /**< SDR104 support */
-#define UHS_DDR50_SUPPORT 0x10U /**< DDR50 support */
-#define WIDTH_4_BIT_SUPPORT 0x4U /**< 4-bit width support */
-#define SD_CLK_25_MHZ 25000000U /**< 25MHz clock */
-#define SD_CLK_19_MHZ 19000000U /**< 19MHz clock */
-#define SD_CLK_26_MHZ 26000000U /**< 26MHz clock */
-#define EXT_CSD_DEVICE_TYPE_BYTE 196U /**< CSD Device Type byte number */
-#define EXT_CSD_SEC_COUNT_BYTE1 212U /**< CSD Sector count byte 1 */
-#define EXT_CSD_SEC_COUNT_BYTE2 213U /**< CSD Sector count byte 2 */
-#define EXT_CSD_SEC_COUNT_BYTE3 214U /**< CSD Sector count byte 3 */
-#define EXT_CSD_SEC_COUNT_BYTE4 215U /**< CSD Sector count byte 4 */
-#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED 0x2U /**< CSD Device type HS */
-#define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED 0x4U /**< CSD Dev type DDR 1.8v speed */
-#define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED 0x8U /**< CSD Dev type DDR 1.2v speed */
-#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 0x10U /**< CSD SDR 1.8v HS200 */
-#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200 0x20U /**< CSD SDR 1.2v HS200 */
-#define CSD_SPEC_VER_3 0x3U /**< CSD card spec ver 3 */
-#define SCR_SPEC_VER_3 0x80U /**< SCR spec ver 3 */
-#define ADDRESS_BEYOND_32BIT 0x100000000U /**< Macro used for beyond 32-bit addr */
-
-#define XSDPS_ZYNQMP_SD0_BASE 0xFF160000U /**< ZynqMP SD0 Baseaddress */
-#define XSDPS_ZYNQMP_SD1_BASE 0xFF170000U /**< ZynqMP SD1 Baseaddress */
-#define XSDPS_VERSAL_SD0_BASE 0xF1040000U /**< Versal SD0 Baseaddress */
-#define XSDPS_VERSAL_SD1_BASE 0xF1050000U /**< Versal SD1 Baseaddress */
-
-/**************************** Type Definitions *******************************/
-
-/**
- * Function pointer for configuring the Tap delays.
- */
-typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of the device */
- u32 InputClockHz; /**< Input clock frequency */
- u32 CardDetect; /**< Card Detect */
- u32 WriteProtect; /**< Write Protect */
- u32 BusWidth; /**< Bus Width */
- u32 BankNumber; /**< MIO Bank selection for SD */
- u32 HasEMIO; /**< If SD is connected to EMIO */
- u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */
-#if defined (XCLOCKING)
- u32 RefClk; /**< Input clocks */
-#endif
-} XSdPs_Config;
-
-/**
- * ADMA2 32-Bit descriptor table
- */
-typedef struct {
- u16 Attribute; /**< Attributes of descriptor */
- u16 Length; /**< Length of current dma transfer */
- u32 Address; /**< Address of current dma transfer */
-#ifdef __ICCARM__
-#pragma data_alignment = 32
-} XSdPs_Adma2Descriptor32;
-#else
-} __attribute__((__packed__))XSdPs_Adma2Descriptor32;
-#endif
-
-/**
- * ADMA2 64-Bit descriptor table
- */
-typedef struct {
- u16 Attribute; /**< Attributes of descriptor */
- u16 Length; /**< Length of current dma transfer */
- u64 Address; /**< Address of current dma transfer */
-#ifdef __ICCARM__
-#pragma data_alignment = 32
-} XSdPs_Adma2Descriptor64;
-#else
-} __attribute__((__packed__))XSdPs_Adma2Descriptor64;
-#endif
-
-/**
- * The XSdPs driver instance data. The user is required to allocate a
- * variable of this type for every SD device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XSdPs_Config Config; /**< Configuration structure */
- u32 IsReady; /**< Device is initialized and ready */
- u32 Host_Caps; /**< Capabilities of host controller */
- u32 Host_CapsExt; /**< Extended Capabilities */
- u32 HCS; /**< High capacity support in card */
- u8 CardType; /**< Type of card - SD/MMC/eMMC */
- u8 Card_Version; /**< Card version */
- u8 HC_Version; /**< Host controller version */
- u8 BusWidth; /**< Current operating bus width */
- u32 BusSpeed; /**< Current operating bus speed */
- u8 Switch1v8; /**< 1.8V Switch support */
- u32 CardID[4]; /**< Card ID Register */
- u32 RelCardAddr; /**< Relative Card Address */
- u32 CardSpecData[4]; /**< Card Specific Data Register */
- u32 SectorCount; /**< Sector Count */
- u32 SdCardConfig; /**< Sd Card Configuration Register */
- u32 Mode; /**< Bus Speed Mode */
- u32 OTapDelay; /**< Output Tap Delay */
- u32 ITapDelay; /**< Input Tap Delay */
- u64 Dma64BitAddr; /**< 64 Bit DMA Address */
- u16 TransferMode; /**< Transfer Mode */
- u32 SlcrBaseAddr; /**< SLCR base address*/
- u8 IsBusy; /**< Busy Flag*/
- u32 BlkSize; /**< Block Size*/
-} XSdPs;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-/**
- * @name SD High Speed mode configuration options
- * @{
- */
-/**
- * User configuration option to enable or disable SD HS mode.
- * By default SD HS mode is disabled for Versal and enabled for
- * other platforms.
- */
-#ifdef versal
-#define SD_HS_MODE_ENABLE 0
-#else
-#define SD_HS_MODE_ENABLE 1
-#endif
-/** @} */
-
-/************************** Function Prototypes ******************************/
-XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
-s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
- u32 EffectiveAddr);
-s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
-s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
-s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
-s32 XSdPs_Idle(XSdPs *InstancePtr);
-
-s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr);
-s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq);
-s32 XSdPs_Pullup(XSdPs *InstancePtr);
-s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *ReadBuff);
-s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr);
-s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff);
-s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
-s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg);
-s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize);
-s32 XSdPs_Get_Status(XSdPs *InstancePtr, u8 *SdStatReg);
-s32 XSdPs_Select_Card(XSdPs *InstancePtr);
-s32 XSdPs_StartReadTransfer(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
-s32 XSdPs_CheckReadTransfer(XSdPs *InstancePtr);
-s32 XSdPs_StartWriteTransfer(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
-s32 XSdPs_CheckWriteTransfer(XSdPs *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SD_H_ */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/42/917ab3585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/42/917ab3585243001d18b399c1eb9b3628
deleted file mode 100644
index 1f20eea..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/42/917ab3585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,78 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/* read.c -- read bytes from a input device.
- */
-#ifndef UNDEFINE_FILE_OPS
-#include "xil_printf.h"
-#include "xparameters.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes);
-}
-#endif
-
-/*
- * read -- read bytes from the serial port. Ignore fd, since
- * we only have stdin.
- */
-__attribute__((weak)) s32
-read (s32 fd, char8* buf, s32 nbytes)
-{
-#ifdef STDIN_BASEADDRESS
- s32 i;
- s32 numbytes = 0;
- char8* LocalBuf = buf;
-
- (void)fd;
- if(LocalBuf != NULL) {
- for (i = 0; i < nbytes; i++) {
- numbytes++;
- *(LocalBuf + i) = inbyte();
- if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
- break;
- }
- }
- }
-
- return numbytes;
-#else
- (void)fd;
- (void)buf;
- (void)nbytes;
- return 0;
-#endif
-}
-
-__attribute__((weak)) s32
-_read (s32 fd, char8* buf, s32 nbytes)
-{
-#ifdef STDIN_BASEADDRESS
- s32 i;
- s32 numbytes = 0;
- char8* LocalBuf = buf;
-
- (void)fd;
- if(LocalBuf != NULL) {
- for (i = 0; i < nbytes; i++) {
- numbytes++;
- *(LocalBuf + i) = inbyte();
- if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
- break;
- }
- }
- }
-
- return numbytes;
-#else
- (void)fd;
- (void)buf;
- (void)nbytes;
- return 0;
-#endif
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/42/b12487565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/42/b12487565243001d18b399c1eb9b3628
deleted file mode 100644
index ab0423e..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/42/b12487565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,53 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-* @file microblaze_disable_interrupts.S
-*
-* @addtogroup microblaze_pseudo_asm_macro
-* @{
-*
microblaze_disable_interrupts.S
-* - API to disable Interrupts: void microblaze_disable_interrupts(void)
-*
-* This API Disables interrupts on the MicroBlaze processor. It can be
-* called when entering a critical section of code where a context switch is
-* undesirable.
-*
-*
-* File : microblaze_disable_interrupts.s
-* Date : 2002, March 20.
-* Company: Xilinx
-* Group : Emerging Software Technologies
-*
-* Summary:
-* Disable interrupts on the microblaze.
-*
-*
-******************************************************************************/
-
-#include "xparameters.h"
-
- .text
- .globl microblaze_disable_interrupts
- .ent microblaze_disable_interrupts
- .align 2
-microblaze_disable_interrupts:
-#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
- rtsd r15, 8
- msrclr r0, 0x2
-#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- #Read the MSR register
- mfs r12, rmsr
- #Clear the interrupt enable bit
- andi r12, r12, ~(0x2)
- #Save the MSR register
- mts rmsr, r12
- #Return
- rtsd r15, 8
- nop
-#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- .end microblaze_disable_interrupts
-/**
-* @} End of "addtogroup microblaze_pseudo_asm_macro".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/43/016329585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/43/016329585243001d18b399c1eb9b3628
deleted file mode 100644
index a46afa7..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/43/016329585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,66 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xscuwdt_sinit.c
-* @addtogroup scuwdt_v2_4
-* @{
-*
-* This file contains method for static initialization (compile-time) of the
-* driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 10/18/09 First release
-* 3.04a sdm 01/02/12 Remove redundant dsb in mcr instruction.
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-*
-******************************************************************************/
-#ifndef XPSEUDO_ASM_H
-#define XPSEUDO_ASM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xreg_cortexa9.h"
-#ifdef __GNUC__
- #include "xpseudo_asm_gcc.h"
-#elif defined (__ICCARM__)
- #include "xpseudo_asm_iccarm.h"
-#else
- #include "xpseudo_asm_rvct.h"
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XPSEUDO_ASM_H */
-/**
-* @} End of "addtogroup a9_specific".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/43/80456e565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/43/80456e565243001d18b399c1eb9b3628
deleted file mode 100644
index b3cd2ea..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/43/80456e565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,113 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xplatform_info.h
-*
-*
-* @addtogroup common_platform_info APIs to Get Platform Information
-*
-*
-* The xplatform_info.h file contains definitions for various available Xilinx®
-* platforms. Also, it contains prototype of APIs, which can be used to get the
-* platform information.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- --------- -------------------------------------------------------
-* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
-* function for PMUFW.
-* 7.2 adk 08/01/20 Added versal support for the XGetPSVersion_Info function.
-* 7.6 mus 08/23/21 Updated prototypes for functions which are not taking any
-* arguments with void keyword. This has been done to fix
-* compilation warnings with "-Wstrict-prototypes" flag.
-* It fixes CR#1108601.
-* 7.6 mus 08/30/21 Updated flag checking to fix compilation warnings
-* reported with "-Wundef" flag.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 08/25/09 First release
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xil_testio.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ****************************/
-/************************** Function Prototypes *****************************/
-
-
-
-/**
- *
- * Endian swap a 16-bit word.
- * @param Data is the 16-bit word to be swapped.
- * @return The endian swapped value.
- *
- */
-static u16 Swap16(u16 Data)
-{
- return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U);
-}
-
-/**
- *
- * Endian swap a 32-bit word.
- * @param Data is the 32-bit word to be swapped.
- * @return The endian swapped value.
- *
- */
-static u32 Swap32(u32 Data)
-{
- u16 Lo16;
- u16 Hi16;
-
- u16 Swap16Lo;
- u16 Swap16Hi;
-
- Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU);
- Lo16 = (u16)(Data & 0x0000FFFFU);
-
- Swap16Lo = Swap16(Lo16);
- Swap16Hi = Swap16(Hi16);
-
- return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi);
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 8-bit wide register IO test where the
-* register is accessed using Xil_Out8 and Xil_In8, and comparing
-* the written values by reading them back.
-*
-* @param Addr: a pointer to the region of memory to be tested.
-* @param Length: Length of the block.
-* @param Value: constant used for writing the memory.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-
-s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value)
-{
- u8 ValueIn;
- s32 Index;
- s32 Status = 0;
-
- for (Index = 0; Index < Length; Index++) {
- Xil_Out8((INTPTR)Addr, Value);
-
- ValueIn = Xil_In8((INTPTR)Addr);
-
- if ((Value != ValueIn) && (Status == 0)) {
- Status = -1;
- break;
- }
- }
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 16-bit wide register IO test. Each location
-* is tested by sequentially writing a 16-bit wide register, reading
-* the register, and comparing value. This function tests three kinds
-* of register IO functions, normal register IO, little-endian register
-* IO, and big-endian register IO. When testing little/big-endian IO,
-* the function performs the following sequence, Xil_Out16LE/Xil_Out16BE,
-* Xil_In16, Compare In-Out values, Xil_Out16, Xil_In16LE/Xil_In16BE,
-* Compare In-Out values. Whether to swap the read-in value before
-* comparing is controlled by the 5th argument.
-*
-* @param Addr: a pointer to the region of memory to be tested.
-* @param Length: Length of the block.
-* @param Value: constant used for writing the memory.
-* @param Kind: Type of test. Acceptable values are:
-* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
-* @param Swap: indicates whether to byte swap the read-in value.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-
-s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap)
-{
- u16 *TempAddr16;
- u16 ValueIn = 0U;
- s32 Index;
- TempAddr16 = Addr;
- Xil_AssertNonvoid(TempAddr16 != NULL);
-
- for (Index = 0; Index < Length; Index++) {
- switch (Kind) {
- case XIL_TESTIO_LE:
- Xil_Out16LE((INTPTR)TempAddr16, Value);
- break;
- case XIL_TESTIO_BE:
- Xil_Out16BE((INTPTR)TempAddr16, Value);
- break;
- default:
- Xil_Out16((INTPTR)TempAddr16, Value);
- break;
- }
-
- ValueIn = Xil_In16((INTPTR)TempAddr16);
-
- if ((Kind != 0) && (Swap != 0)) {
- ValueIn = Swap16(ValueIn);
- }
-
- if (Value != ValueIn) {
- return -1;
- }
-
- /* second round */
- Xil_Out16((INTPTR)TempAddr16, Value);
-
- switch (Kind) {
- case XIL_TESTIO_LE:
- ValueIn = Xil_In16LE((INTPTR)TempAddr16);
- break;
- case XIL_TESTIO_BE:
- ValueIn = Xil_In16BE((INTPTR)TempAddr16);
- break;
- default:
- ValueIn = Xil_In16((INTPTR)TempAddr16);
- break;
- }
-
-
- if ((Kind != 0) && (Swap != 0)) {
- ValueIn = Swap16(ValueIn);
- }
-
- if (Value != ValueIn) {
- return -1;
- }
- TempAddr16 += sizeof(u16);
- }
- return 0;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 32-bit wide register IO test. Each location
-* is tested by sequentially writing a 32-bit wide register, reading
-* the register, and comparing value. This function tests three kinds
-* of register IO functions, normal register IO, little-endian register IO,
-* and big-endian register IO. When testing little/big-endian IO,
-* the function perform the following sequence, Xil_Out32LE/
-* Xil_Out32BE, Xil_In32, Compare, Xil_Out32, Xil_In32LE/Xil_In32BE, Compare.
-* Whether to swap the read-in value *before comparing is controlled
-* by the 5th argument.
-* @param Addr: a pointer to the region of memory to be tested.
-* @param Length: Length of the block.
-* @param Value: constant used for writing the memory.
-* @param Kind: type of test. Acceptable values are:
-* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
-* @param Swap: indicates whether to byte swap the read-in value.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
-{
- u32 *TempAddr;
- u32 ValueIn = 0U;
- s32 Index;
- TempAddr = Addr;
- Xil_AssertNonvoid(TempAddr != NULL);
-
- for (Index = 0; Index < Length; Index++) {
- switch (Kind) {
- case XIL_TESTIO_LE:
- Xil_Out32LE((INTPTR)TempAddr, Value);
- break;
- case XIL_TESTIO_BE:
- Xil_Out32BE((INTPTR)TempAddr, Value);
- break;
- default:
- Xil_Out32((INTPTR)TempAddr, Value);
- break;
- }
-
- ValueIn = Xil_In32((INTPTR)TempAddr);
-
- if ((Kind != 0) && (Swap != 0)) {
- ValueIn = Swap32(ValueIn);
- }
-
- if (Value != ValueIn) {
- return -1;
- }
-
- /* second round */
- Xil_Out32((INTPTR)TempAddr, Value);
-
-
- switch (Kind) {
- case XIL_TESTIO_LE:
- ValueIn = Xil_In32LE((INTPTR)TempAddr);
- break;
- case XIL_TESTIO_BE:
- ValueIn = Xil_In32BE((INTPTR)TempAddr);
- break;
- default:
- ValueIn = Xil_In32((INTPTR)TempAddr);
- break;
- }
-
- if ((Kind != 0) && (Swap != 0)) {
- ValueIn = Swap32(ValueIn);
- }
-
- if (Value != ValueIn) {
- return -1;
- }
- TempAddr += sizeof(u32);
- }
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/43/f08928565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/43/f08928565243001d18b399c1eb9b3628
deleted file mode 100644
index eeac2b7..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/43/f08928565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,102 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************
-*
-* @file sleep.c
-*
-* This function supports user configurable sleep implementation.
-* This provides delay in seconds by using the Timer specified by
-* the user in the ARM Cortex R5 MP core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 02/20/14 First release
-* 5.04 pkp 02/19/16 sleep routine is modified to use TTC3 if present
-* else it will use set of assembly instructions to
-* provide the required delay
-* 5.04 pkp 03/09/16 Assembly routine for sleep is modified to avoid
-* disabling the interrupt
-* 5.04 pkp 03/11/16 Compare the counter value to previously read value
-* to detect the overflow for TTC3
-* 6.0 asa 08/15/16 Updated the sleep signature. Fix for CR#956899.
-* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
-* implementation. Now sleep routines will use TTC
-* instance specified by user.
-* 7.2 mus 01/29/20 Updated sleep routines to use CortexR5 PMU for delay
-* generation, in case TTC3/TTC2 instances are not
-* present in HW design. If user dont want to use PMU
-* counter for sleep routines, BSP needs to be compiled
-* with "DONT_USE_PMU_FOR_SLEEP_ROUTINES" flag. It fixes
-* CR#1051591.
-*
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "sleep.h"
-#include "xtime_l.h"
-#include "xparameters.h"
-#include "xil_sleeptimer.h"
-#include "xpm_counter.h"
-
-/*****************************************************************************/
-/*
-*
-* This API is used to provide delays in seconds.
-*
-* @param seconds requested
-*
-* @return 0 always
-*
-* @note By default, sleep is implemented using TTC3. Although user is
-* given an option to select other instances of TTC. When the user
-* selects other instances of TTC, sleep is implemented by that
-* specific TTC instance. If the user didn't select any other instance
-* of TTC specifically and when TTC3 is absent, sleep is implemented
-* using assembly instructions which is tested with instruction and
-* data caches enabled and it gives proper delay. It may give more
-* delay than exepcted when caches are disabled. If interrupt comes
-* when sleep using assembly instruction is being executed, the delay
-* may be greater than what is expected since once the interrupt is
-* served count resumes from where it was interrupted unlike the case
-* of TTC3 where counter keeps running while interrupt is being served.
-*
-****************************************************************************/
-
-unsigned sleep_R5(unsigned int seconds)
-{
-#if defined (SLEEP_TIMER_BASEADDR)
- Xil_SleepTTCCommon(seconds, COUNTS_PER_SECOND);
-#elif !defined (DONT_USE_PMU_FOR_SLEEP_ROUTINES)
- Xpm_SleepPerfCounter(seconds, COUNTS_PER_SECOND);
-#else
-#if defined (__GNUC__)
- __asm__ __volatile__ (
-#elif defined (__ICCARM__)
- __asm volatile (
-#endif
-
- "push {r0,r1,r3} \n"
- "mov r0, %[sec] \n"
- "mov r1, %[iter] \n"
- "1: \n"
- "mov r3, r1\n"
- "2: \n"
- "subs r3, r3, #0x1 \n"
- "bne 2b \n"
- "subs r0, r0, #0x1 \n"
- "bne 1b \n"
- "pop {r0,r1,r3} \n"
- ::[iter] "r" (ITERS_PER_SEC), [sec] "r" (seconds)
- );
-#endif
-
-return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/44/026329585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/44/026329585243001d18b399c1eb9b3628
deleted file mode 100644
index 5feeb49..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/44/026329585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,39 +0,0 @@
-DRIVER_LIB_VERSION = 1.0
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I$(INCLUDEDIR)
-
-SRCFILES:=$(wildcard *.c)
-
-OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
-
-libs: $(OBJECTS)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf $(DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/44/108521565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/44/108521565243001d18b399c1eb9b3628
deleted file mode 100644
index a5e2aa4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/44/108521565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,334 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xparameters_ps.h
-*
-* @addtogroup r5_peripheral_definitions Cortex R5 peripheral definitions
-*
-* The xparameters_ps.h file contains the canonical definitions and constant
-* declarations for peripherals within hardblock, attached to the ARM Cortex R5
-* core. These definitions can be used by drivers or applications to access the
-* peripherals.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 5.00 pkp 02/29/14 Initial version
-* 6.0 mus 08/18/16 Defined ARMR5 flag
-* 7.2 pm 03/25/20 Add wakeup Interrupt Id for usbpsu controller
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.1 nsk 11/07/16 First release.
-* 7.0 mus 01/07/19 Add cpp extern macro
-*
-*
-*
-*****************************************************************************/
-#ifndef XIL_MEM_H /* prevent circular inclusions */
-#define XIL_MEM_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Function Prototypes *****************************/
-
-void Xil_MemCpy(void* dst, const void* src, u32 cnt);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_MEM_H */
-/**
-* @} End of "addtogroup common_mem_operation_api".
-*/
\ No newline at end of file
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/44/91d160595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/44/91d160595243001d18b399c1eb9b3628
deleted file mode 100644
index b8b4805..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/44/91d160595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,51 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2008 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-*
-* microblaze_flush_dcache()
-*
-* Flush the L1 DCache
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-#include "microblaze_instructions.h"
-
-#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
-#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
-
-#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
-#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
-#endif
-
- .text
- .globl microblaze_flush_dcache
- .ent microblaze_flush_dcache
- .align 2
-
-microblaze_flush_dcache:
-#if (XPAR_MICROBLAZE_USE_DCACHE==1) && (XPAR_MICROBLAZE_ALLOW_DCACHE_WR==1)
- ADDIK r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Align to cache line */
- ADDIK r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */
-
-L_start:
- wdc.flush r5, r0 /* Flush the Cache */
-
- CMPU r18, r5, r6 /* Are we at the end? */
- BLEI r18, L_done
-
-#if defined (__arch64__ )
- addlik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the address by 4 */
- BRI L_start
-#else
- brid L_start /* Branch to the beginning of the loop */
- addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the address by 4 (delay slot) */
-#endif
-L_done:
-#endif
- rtsd r15, 8 /* Return */
- nop
- .end microblaze_flush_dcache
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/44/a1af16565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/44/a1af16565243001d18b399c1eb9b3628
deleted file mode 100644
index 48ec474..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/44/a1af16565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,342 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file boot.S
-*
-* @addtogroup r5_boot_code Cortex R5 Processor Boot Code
-* @{
-*
boot.S
-* The boot.S file contains a minimal set of code for transferring control from the processor
-* reset location of the processor to the start of the application.
-* The boot code performs minimum configuration which is required for an
-* application to run starting from reset state of the processor. Below is a
-* sequence illustrating what all configuration is performed before control
-* reaches to main function.
-*
-* 1. Program vector table base for exception handling
-* 2. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine,
-* abort, system)
-* 3. Disable instruction cache, data cache and MPU
-* 4. Invalidate instruction and data cache
-* 5. Configure MPU with short descriptor translation table format and program
-* base address of translation table
-* 6. Enable data cache, instruction cache and MPU
-* 7. Enable Floating point unit
-* 8. Transfer control to _start which clears BSS sections and jumping to main
-* application
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00 pkp 02/10/14 Initial version
-* 5.04 pkp 09/11/15 Disabled ACTLR.DBWR bit to avoid potential R5 deadlock
-* for errata 780125
-* 5.04 pkp 02/04/16 Enabled the fault log for lock-step mode
-* 5.04 pkp 02/25/16 Initialized the banked registers for various modes,
-* initialized floating point registers and enabled the
-* cache ECC check before enabling the fault log for
-* lock step mode
-* 5.04 pkp 03/24/16 Reset the dbg_lpd_reset before enabling the fault log
-* to avoid intervention for lock-step mode
-* 5.05 pkp 04/11/16 Enable the comparators for non-JTAG boot mode for
-* lock-step to avoid putting debug logic to reset
-* 6.02 pkp 02/13/17 Added support for hard float
-* 6.6 mus 02/23/17 Enable/Disable the debug logic in non-JTAG boot mode(when
-* processor is in lockstep configuration), based
-* on the mld parameter "lockstep_mode_debug".
-* 6.8 mus 09/20/18 Clear VINITHI field in RPU_0_CFG/RPU_1_CFG
-* registers to initialize CortexR5 core with LOVEC
-* on reset. It fixes CR#1010656.
-* 7.1 mus 03/27/19 Skip reading/writing to the RPU address space registers,
-* in case if processor is nonsecure and RPU
-* address space is secure. CR#1015725.
-* 7.2 mus 10/11/19 Resetting the r5_0 and r5_1 debug logic is sufficient
-* to avoid intervention for lock-step mode. So, removed
-* code which resets dbg_lpd_reset, to unblock debugger
-* access to LPD. Fix for CR#1027983.
-*
-*
-******************************************************************************/
-
-#include "xparameters.h"
-
-
-.global _prestart
-.global _boot
-.global __stack
-.global __irq_stack
-.global __supervisor_stack
-.global __abort_stack
-.global __fiq_stack
-.global __undef_stack
-.global _vector_table
-
-
-/* Stack Pointer locations for boot code */
-.set Undef_stack, __undef_stack
-.set FIQ_stack, __fiq_stack
-.set Abort_stack, __abort_stack
-.set SPV_stack, __supervisor_stack
-.set IRQ_stack, __irq_stack
-.set SYS_stack, __stack
-
-.set vector_base, _vector_table
-
-.set RPU_GLBL_CNTL, 0xFF9A0000
-.set RPU_ERR_INJ, 0xFF9A0020
-.set RPU_0_CFG, 0xFF9A0100
-.set RPU_1_CFG, 0xFF9A0200
-#if defined(versal)
-.set RST_LPD_DBG, 0xFF5E0338
-.set BOOT_MODE_USER, 0xF1260200
-#else
-.set RST_LPD_DBG, 0xFF5E0240
-.set BOOT_MODE_USER, 0xFF5E0200
-#endif
-.set fault_log_enable, 0x101
-
-/*
- * 0th bit of PROCESSOR_ACCESS_VALUE macro signifies trustzone
- * setting for RPU address space
- */
-#define RPU_TZ_MASK 0x1
-
-.section .boot,"axS"
-
-
-/* this initializes the various processor modes */
-
-_prestart:
-_boot:
-
-OKToRun:
-
-/* Initialize processor registers to 0 */
- mov r0,#0
- mov r1,#0
- mov r2,#0
- mov r3,#0
- mov r4,#0
- mov r5,#0
- mov r6,#0
- mov r7,#0
- mov r8,#0
- mov r9,#0
- mov r10,#0
- mov r11,#0
- mov r12,#0
-
-/* Initialize stack pointer and banked registers for various mode */
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the irq stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x12 /* IRQ mode */
- msr cpsr, r2
- ldr r13,=IRQ_stack /* IRQ stack pointer */
- mov r14,#0
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the supervisor stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x13 /* supervisor mode */
- msr cpsr, r2
- ldr r13,=SPV_stack /* Supervisor stack pointer */
- mov r14,#0
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the Abort stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x17 /* Abort mode */
- msr cpsr, r2
- ldr r13,=Abort_stack /* Abort stack pointer */
- mov r14,#0
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the FIQ stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x11 /* FIQ mode */
- msr cpsr, r2
- mov r8, #0
- mov r9, #0
- mov r10, #0
- mov r11, #0
- mov r12, #0
- ldr r13,=FIQ_stack /* FIQ stack pointer */
- mov r14,#0
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the Undefine stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x1b /* Undefine mode */
- msr cpsr, r2
- ldr r13,=Undef_stack /* Undefine stack pointer */
- mov r14,#0
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the system stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x1F /* SYS mode */
- msr cpsr, r2
- ldr r13,=SYS_stack /* SYS stack pointer */
- mov r14,#0
-
-/*
- * Enable access to VFP by enabling access to Coprocessors 10 and 11.
- * Enables Full Access i.e. in both privileged and non privileged modes
- */
- mrc p15, 0, r0, c1, c0, 2 /* Read Coprocessor Access Control Register (CPACR) */
- orr r0, r0, #(0xF << 20) /* Enable access to CP 10 & 11 */
- mcr p15, 0, r0, c1, c0, 2 /* Write Coprocessor Access Control Register (CPACR) */
- isb
-
-/* enable fpu access */
- vmrs r3, FPEXC
- orr r1, r3, #(1<<30)
- vmsr FPEXC, r1
-
-/* clear the floating point register*/
- mov r1,#0
- vmov d0,r1,r1
- vmov d1,r1,r1
- vmov d2,r1,r1
- vmov d3,r1,r1
- vmov d4,r1,r1
- vmov d5,r1,r1
- vmov d6,r1,r1
- vmov d7,r1,r1
- vmov d8,r1,r1
- vmov d9,r1,r1
- vmov d10,r1,r1
- vmov d11,r1,r1
- vmov d12,r1,r1
- vmov d13,r1,r1
- vmov d14,r1,r1
- vmov d15,r1,r1
-
-#ifdef __SOFTFP__
-/* Disable the FPU if SOFTFP is defined*/
- vmsr FPEXC,r3
-#endif
-
-/* Disable MPU and caches */
- mrc p15, 0, r0, c1, c0, 0 /* Read CP15 Control Register*/
- bic r0, r0, #0x05 /* Disable MPU (M bit) and data cache (C bit) */
- bic r0, r0, #0x1000 /* Disable instruction cache (I bit) */
- dsb /* Ensure all previous loads/stores have completed */
- mcr p15, 0, r0, c1, c0, 0 /* Write CP15 Control Register */
- isb /* Ensure subsequent insts execute wrt new MPU settings */
-
-/* Disable Branch prediction, TCM ECC checks */
- mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR */
- orr r0, r0, #(0x1 << 17) /* Enable RSDIS bit 17 to disable the return stack */
- orr r0, r0, #(0x1 << 16) /* Clear BP bit 15 and set BP bit 16:*/
- bic r0, r0, #(0x1 << 15) /* Branch always not taken and history table updates disabled*/
- orr r0, r0, #(0x1 << 27) /* Enable B1TCM ECC check */
- orr r0, r0, #(0x1 << 26) /* Enable B0TCM ECC check */
- orr r0, r0, #(0x1 << 25) /* Enable ATCM ECC check */
- bic r0, r0, #(0x1 << 5) /* Generate abort on parity errors, with [5:3]=b 000*/
- bic r0, r0, #(0x1 << 4)
- bic r0, r0, #(0x1 << 3)
- mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/
- dsb /* Complete all outstanding explicit memory operations*/
-
-/* Invalidate caches */
- mov r0,#0 /* r0 = 0 */
- dsb
- mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
- mcr p15, 0, r0, c15, c5, 0 /* Invalidate entire data cache*/
- isb
-#if LOCKSTEP_MODE_DEBUG == 0 && (PROCESSOR_ACCESS_VALUE & RPU_TZ_MASK)
-/* enable fault log for lock step */
- ldr r0,=RPU_GLBL_CNTL
- ldr r1, [r0]
- ands r1, r1, #0x8
-/* branch to initialization if split mode*/
- bne init
-/* check for boot mode if in lock step, branch to init if JTAG boot mode*/
- ldr r0,=BOOT_MODE_USER
- ldr r1, [r0]
- ands r1, r1, #0xF
- beq init
-/* reset the debug logic */
- ldr r0,=RST_LPD_DBG
- ldr r1, [r0]
- orr r1, r1, #(0x1 << 4)
- orr r1, r1, #(0x1 << 5)
- str r1, [r0]
-/* enable fault log */
- ldr r0,=RPU_ERR_INJ
- ldr r1,=fault_log_enable
- ldr r2, [r0]
- orr r2, r2, r1
- str r2, [r0]
- nop
- nop
-#endif
-
-init:
- bl Init_MPU /* Initialize MPU */
-
-/* Enable Branch prediction */
- mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/
- bic r0, r0, #(0x1 << 17) /* Clear RSDIS bit 17 to enable return stack*/
- bic r0, r0, #(0x1 << 16) /* Clear BP bit 15 and BP bit 16:*/
- bic r0, r0, #(0x1 << 15) /* Normal operation, BP is taken from the global history table.*/
- orr r0, r0, #(0x1 << 14) /* Disable DBWR for errata 780125 */
- mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/
-
-/* Enable icahce and dcache */
- mrc p15,0,r1,c1,c0,0
- ldr r0, =0x1005
- orr r1,r1,r0
- dsb
- mcr p15,0,r1,c1,c0,0 /* Enable cache */
- isb /* isb flush prefetch buffer */
-
-/* Warning message to be removed after 2016.1 */
-/* USEAMP was introduced in 2015.4 with ZynqMP and caused confusion with USE_AMP */
-#ifdef USEAMP
-#warning "-DUSEAMP=1 is deprecated, use -DVEC_TABLE_IN_OCM instead to set vector table in OCM"
-#endif
-
-/* Set vector table in TCM/LOVEC */
-#ifndef VEC_TABLE_IN_OCM
- mrc p15, 0, r0, c1, c0, 0
- mvn r1, #0x2000
- and r0, r0, r1
- mcr p15, 0, r0, c1, c0, 0
-
-/* Check if processor is having access to RPU address space */
-#if (PROCESSOR_ACCESS_VALUE & RPU_TZ_MASK)
-/* Clear VINITHI to enable LOVEC on reset */
-#if XPAR_CPU_ID == 0
- ldr r0, =RPU_0_CFG
-#else
- ldr r0, =RPU_1_CFG
-#endif
- ldr r1, [r0]
- bic r1, r1, #(0x1 << 2)
- str r1, [r0]
-#endif
-#endif
-/* enable asynchronous abort exception */
- mrs r0, cpsr
- bic r0, r0, #0x100
- msr cpsr_xsf, r0
-
- b _startup /* jump to C startup code */
-
-
-.Ldone: b .Ldone /* Paranoia: we should never get here */
-
-
-.end
-/**
-* @} End of "addtogroup r5_boot_code".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/44/b0059b575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/44/b0059b575243001d18b399c1eb9b3628
deleted file mode 100644
index ce4b290..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/44/b0059b575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,597 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xscugic.h
-* @addtogroup scugic_v4_6
-* @{
-* @details
-*
-* The generic interrupt controller driver component.
-*
-* The interrupt controller driver uses the idea of priority for the various
-* handlers. Priority is an integer within the range of 1 and 31 inclusive with
-* default of 1 being the highest priority interrupt source. The priorities
-* of the various sources can be dynamically altered as needed through
-* hardware configuration.
-*
-* The generic interrupt controller supports the following
-* features:
-*
-* - specific individual interrupt enabling/disabling
-* - specific individual interrupt acknowledging
-* - attaching specific callback function to handle interrupt source
-* - assigning desired priority to interrupt source if default is not
-* acceptable.
-*
-* Details about connecting the interrupt handler of the driver are contained
-* in the source file specific to interrupt processing, xscugic_intr.c.
-*
-* This driver is intended to be RTOS and processor independent. It works with
-* physical addresses only. Any needs for dynamic memory management, threads
-* or thread mutual exclusion, virtual memory, or cache control must be
-* satisfied by the layer above this driver.
-*
-* Interrupt Vector Tables
-*
-* The device ID of the interrupt controller device is used by the driver as a
-* direct index into the configuration data table. The user should populate the
-* vector table with handlers and callbacks at run-time using the
-* XScuGic_Connect() and XScuGic_Disconnect() functions.
-*
-* Each vector table entry corresponds to a device that can generate an
-* interrupt. Each entry contains an interrupt handler function and an
-* argument to be passed to the handler when an interrupt occurs. The
-* user must use XScuGic_Connect() when the interrupt handler takes an
-* argument other than the base address.
-*
-* Nested Interrupts Processing
-*
-* Nested interrupts are not supported by this driver.
-*
-* NOTE:
-* The generic interrupt controller is not a part of the snoop control unit
-* as indicated by the prefix "scu" in the name of the driver.
-* It is an independent module in APU.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------------
-* 1.00a drg 01/19/00 First release
-* 1.01a sdm 11/09/11 The XScuGic and XScuGic_Config structures have changed.
-* The HandlerTable (of type XScuGic_VectorTableEntry) is
-* moved to XScuGic_Config structure from XScuGic structure.
-*
-* The "Config" entry in XScuGic structure is made as
-* pointer for better efficiency.
-*
-* A new file named as xscugic_hw.c is now added. It is
-* to implement low level driver routines without using
-* any xscugic instance pointer. They are useful when the
-* user wants to use xscugic through device id or
-* base address. The driver routines provided are explained
-* below.
-* XScuGic_DeviceInitialize that takes device id as
-* argument and initializes the device (without calling
-* XScuGic_CfgInitialize).
-* XScuGic_DeviceInterruptHandler that takes device id
-* as argument and calls appropriate handlers from the
-* HandlerTable.
-* XScuGic_RegisterHandler that registers a new handler
-* by taking xscugic hardware base address as argument.
-* LookupConfigByBaseAddress is used to return the
-* corresponding config structure from XScuGic_ConfigTable
-* based on the scugic base address passed.
-* 1.02a sdm 12/20/11 Removed AckBeforeService from the XScuGic_Config
-* structure.
-* 1.03a srt 02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
-* *_hw.h
-* Added APIs
-* - XScuGic_SetPriTrigTypeByDistAddr()
-* - XScuGic_GetPriTrigTypeByDistAddr()
-* (CR 702687)
-* Added support to direct interrupts to the appropriate CPU. Earlier
-* interrupts were directed to CPU1 (hard coded). Now depending
-* upon the CPU selected by the user (xparameters.h), interrupts
-* will be directed to the relevant CPU. This fixes CR 699688.
-* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
-* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
-* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
-* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
-* This is fix for CR#705621.
-* 1.05a hk 06/26/13 Modified tcl to export external interrupts correctly to
-* xparameters.h. Fix for CR's 690505, 708928 & 719359.
-* 2.0 adk 12/10/13 Updated as per the New Tcl API's
-* 2.1 adk 25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.2 asa 02/29/16 Modified DistributorInit function for Zynq AMP case. The
-* distributor is left uninitialized for Zynq AMP. It is assumed
-* that the distributor will be initialized by Linux master. However
-* for CortexR5 case, the earlier code is left unchanged where the
-* the interrupt processor target registers in the distributor is
-* initialized with the corresponding CPU ID on which the application
-* built over the scugic driver runs.
-* These changes fix CR#937243.
-*
-* 3.4 asa 04/07/16 Created a new static function DoDistributorInit to simplify
-* the flow and avoid code duplication. Changes are made for
-* USE_AMP use case for R5. In a scenario (in R5 split mode) when
-* one R5 is operating with A53 in open amp config and other
-* R5 running baremetal app, the existing code
-* had the potential to stop the whole AMP solution to work (if
-* for some reason the R5 running the baremetal app tasked to
-* initialize the Distributor hangs or crashes before initializing).
-* Changes are made so that the R5 under AMP first checks if
-* the distributor is enabled or not and if not, it does the
-* standard Distributor initialization.
-* This fixes the CR#952962.
-* 3.6 ms 01/23/17 Modified xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* kvn 02/17/17 Add support for changing GIC CPU master at run time.
-* kvn 02/28/17 Make the CpuId as static variable and Added new
-* XScugiC_GetCpuId to access CpuId.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 3.7 ms 04/11/17 Modified tcl file to add suffix U for all macro
-* definitions of scugic in xparameters.h
-* 3.8 mus 07/05/17 Updated scugic.tcl to add support for interrupts connected
-* through util_reduced_vector IP(OR gate)
-* mus 07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize
-* the HandlerTable in XScuGic_ConfigTable to 0, it removes
-* the compilation warning in xscugic_g.c. Fix for CR#978736.
-* mus 07/25/17 Updated xdefine_gic_params proc to export correct canonical
-* definitions for pl to ps interrupts.Fix for CR#980534
-* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
-* XScuGic_InterruptUnmapFromCpu, These API's can be used
-* by applications to unmap specific/all interrupts from
-* target CPU.
-* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
-* 4.0 mus 11/22/18 Fixed bugs in software interrupt generation through
-* XScuGic_SoftwareIntr API
-* 4.1 asa 03/30/19 Made changes not to direct each interrupt to all
-* available CPUs by default. This was breaking AMP
-* behavior. Instead every time an interrupt enable
-* request is received, the interrupt was mapped to
-* the respective CPU. There were several other changes
-* made to implement this. This set of changes was to
-* fix CR-1024716.
-* 4.1 mus 06/19/19 Added API's XScuGic_MarkCoreAsleep and
-* XScuGic_MarkCoreAwake to mark processor core as
-* asleep or awake. Fix for CR#1027220.
-* 4.5 asa 03/07/21 Included a header file xil_spinlock.h to ensure that
-* GIC driver can use newly introduced spinlock
-* functionality.
-* 4.6 sk 08/05/21 Fix scugic misrac violations.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
-* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
-* APIs is words (32 bit) and not bytes.
-* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
-* to add information that 2 LSBs of the Source/Destination
-* address when equal to 2�b01 indicate the last DMA command
-* of an overall transfer.
-* Destination Address passed to this API for secure transfers
-* instead of using 0xFFFFFFFF for CR 662197. This issue was
-* resulting in the failure of secure transfers of
-* non-bitstream images.
-* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
-* set the mask instead of oring it with the
-* value read from the interrupt status register
-* Added defines for the PS Version bits,
-* removed the FIFO Flush bits from the
-* Miscellaneous Control Reg.
-* Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
-* and XDcfg_SelectPcapInterface APIs for CR 643295
-* The user has to call the XDcfg_SelectIcapInterface API
-* for the PL reconfiguration using AXI HwIcap.
-* Updated the XDcfg_Transfer API to clear the
-* QUARTER_PCAP_RATE_EN bit in the control register for
-* non secure writes for CR 675543.
-* 2.02a nm 01/31/13 Fixed CR# 679335.
-* Added Setting and Clearing the internal PCAP loopback.
-* Removed code for enabling/disabling AES engine as BootROM
-* locks down this setting.
-* Fixed CR# 681976.
-* Skip Checking the PCFG_INIT in case of non-secure DMA
-* loopback.
-* Fixed CR# 699558.
-* XDcfg_Transfer fails to transfer data in loopback mode.
-* Fixed CR# 701348.
-* Peripheral test fails with Running
-* DcfgSelfTestExample() in SECURE bootmode.
-* 2.03a nm 04/19/13 Fixed CR# 703728.
-* Updated the register definitions as per the latest TRM
-* version UG585 (v1.4) November 16, 2012.
-* 3.0 adk 10/12/13 Updated as per the New Tcl API's
-* 3.0 kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
-* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
-* updated driver code with != instead of ==,
-* while checking for Interrupt Status with DMA and
-* PCAP Done Mask
-* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
-* XDCFG_INT_STS_OFFSET) &
-* XDCFG_IXR_D_P_DONE_MASK) !=
-* XDCFG_IXR_D_P_DONE_MASK);
-* A new example has been added to read back the
-* configuration registers from the PL region.
-* xdevcfg_reg_readback_example.c
-* 3.3 sk 04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/10/17 Modified filename tag in interrupt and polled examples
-* to include them in doxygen examples.
-* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros
-* definitions of devcfg in xparameters.h
-* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
-*
-*
-******************************************************************************/
-#ifndef XDCFG_H /* prevent circular inclusions */
-#define XDCFG_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xdevcfg_hw.h"
-#include "xstatus.h"
-#include "xil_assert.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/* Types of PCAP transfers */
-
-#define XDCFG_NON_SECURE_PCAP_WRITE 1
-#define XDCFG_SECURE_PCAP_WRITE 2
-#define XDCFG_PCAP_READBACK 3
-#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4
-#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5
-
-
-/**************************** Type Definitions *******************************/
-/**
-* The handler data type allows the user to define a callback function to
-* respond to interrupt events in the system. This function is executed
-* in interrupt context, so amount of processing should be minimized.
-*
-* @param CallBackRef is the callback reference passed in by the upper
-* layer when setting the callback functions, and passed back to
-* the upper layer when the callback is invoked. Its type is
-* unimportant to the driver component, so it is a void pointer.
-* @param Status is the Interrupt status of the XDcfg device.
-*/
-typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddr; /**< Base address of the device */
-} XDcfg_Config;
-
-/**
- * The XDcfg driver instance data.
- */
-typedef struct {
- XDcfg_Config Config; /**< Hardware Configuration */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStarted; /**< Device Configuration Interface
- * is running
- */
- XDcfg_IntrHandler StatusHandler; /* Event handler function */
- void *CallBackRef; /* Callback reference for event handler */
-} XDcfg;
-
-/****************************************************************************/
-/**
-*
-* Unlock the Device Config Interface block.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_Unlock(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_Unlock(InstancePtr) \
- XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \
- XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
-
-
-
-/****************************************************************************/
-/**
-*
-* Get the version number of the PS from the Miscellaneous Control Register.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return Version of the PS.
-*
-* @note C-style signature:
-* void XDcfg_GetPsVersion(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_GetPsVersion(InstancePtr) \
- ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
- XDCFG_MCTRL_OFFSET)) & \
- XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \
- XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
-
-
-
-/****************************************************************************/
-/**
-*
-* Read the multiboot config register value.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_ReadMultiBootConfig(InstancePtr) \
- XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
- XDCFG_MULTIBOOT_ADDR_OFFSET)
-
-
-/****************************************************************************/
-/**
-*
-* Selects ICAP interface for reconfiguration after the initial configuration
-* of the PL.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_SelectIcapInterface(InstancePtr) \
- XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
- ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
- & ( ~XDCFG_CTRL_PCAP_PR_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Selects PCAP interface for reconfiguration after the initial configuration
-* of the PL.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_SelectPcapInterface(InstancePtr) \
- XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
- ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
- | XDCFG_CTRL_PCAP_PR_MASK))
-
-
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Lookup configuration in xdevcfg_sinit.c.
- */
-XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId);
-
-/*
- * Selftest function in xdevcfg_selftest.c
- */
-int XDcfg_SelfTest(XDcfg *InstancePtr);
-
-/*
- * Interface functions in xdevcfg.c
- */
-int XDcfg_CfgInitialize(XDcfg *InstancePtr,
- XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
-
-void XDcfg_EnablePCAP(XDcfg *InstancePtr);
-
-void XDcfg_DisablePCAP(XDcfg *InstancePtr);
-
-void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask);
-
-void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask);
-
-u32 XDcfg_GetControlRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetLockRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask);
-
-u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr);
-
-u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr);
-
-void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
- u32 SrcWordLength, u32 DestWordLength);
-
-u32 XDcfg_Transfer(XDcfg *InstancePtr,
- void *SourcePtr, u32 SrcWordLength,
- void *DestPtr, u32 DestWordLength,
- u32 TransferType);
-
-/*
- * Interrupt related function prototypes implemented in xdevcfg_intr.c
- */
-void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask);
-
-void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask);
-
-u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr);
-
-u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr);
-
-void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask);
-
-void XDcfg_InterruptHandler(XDcfg *InstancePtr);
-
-void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
- void *CallBackRef);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/45/706512525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/45/706512525243001d18b399c1eb9b3628
deleted file mode 100644
index 0ee2dcb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/45/706512525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,111 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include "xparameters.h"
-#include "xil_cache.h"
-
-#include "platform_config.h"
-
-/*
- * Uncomment one of the following two lines, depending on the target,
- * if ps7/psu init source files are added in the source directory for
- * compiling example outside of SDK.
- */
-/*#include "ps7_init.h"*/
-/*#include "psu_init.h"*/
-
-#ifdef STDOUT_IS_16550
- #include "xuartns550_l.h"
-
- #define UART_BAUD 9600
-#endif
-
-void
-enable_caches()
-{
-#ifdef __PPC__
- Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
- Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
-#elif __MICROBLAZE__
-#ifdef XPAR_MICROBLAZE_USE_ICACHE
- Xil_ICacheEnable();
-#endif
-#ifdef XPAR_MICROBLAZE_USE_DCACHE
- Xil_DCacheEnable();
-#endif
-#endif
-}
-
-void
-disable_caches()
-{
-#ifdef __MICROBLAZE__
-#ifdef XPAR_MICROBLAZE_USE_DCACHE
- Xil_DCacheDisable();
-#endif
-#ifdef XPAR_MICROBLAZE_USE_ICACHE
- Xil_ICacheDisable();
-#endif
-#endif
-}
-
-void
-init_uart()
-{
-#ifdef STDOUT_IS_16550
- XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
- XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
-#endif
- /* Bootrom/BSP configures PS7/PSU UART to 115200 bps */
-}
-
-void
-init_platform()
-{
- /*
- * If you want to run this example outside of SDK,
- * uncomment one of the following two lines and also #include "ps7_init.h"
- * or #include "ps7_init.h" at the top, depending on the target.
- * Make sure that the ps7/psu_init.c and ps7/psu_init.h files are included
- * along with this example source files for compilation.
- */
- /* ps7_init();*/
- /* psu_init();*/
- enable_caches();
- init_uart();
-}
-
-void
-cleanup_platform()
-{
- disable_caches();
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/45/90b6c7535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/45/90b6c7535243001d18b399c1eb9b3628
deleted file mode 100644
index 31156ee..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/45/90b6c7535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,96 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xl2cc_counter.h
-*
-* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions
-*
-* xl2cc_counter.h contains APIs for configuring and controlling the event
-* counters in PL310 L2 cache controller.
-* PL310 has two event counters which can be used to count variety of events
-* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions
-* for different configurations which can be used for the event counters to
-* count a set of events.
-*
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
-* inside the APIs
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.4 mmd 04/21/19 First release.
-* 6.5 kal 02/29/20 Added Xil_ConvertStringToHexBE API
-* 7.3 kal 06/30/20 Converted Xil_Ceil macro to API
-* rpo 08/19/20 Added function for read, modify and write
-* bsv 08/21/20 Added XSECURE_TEMPORAL_CHECK macro to add
-* redundancy in security critical functions, to avoid
-* glitches from altering the return values of security
-* critical functions. The macro requires a label to be
-* passed to "go to" in case of error.
-* kpt 09/03/20 Added XSECURE_TEMPORAL_IMPL macro for redundancy
-* kal 09/22/20 Changed the param type from const char to const char*
-* to avoid copying key onto stack
-* td 10/16/20 Added Xil_Strcpy, Xil_Strcat, Xil_SecureMemCpy and
-* Xil_MemCmp functions
-* am 10/13/20 Resolved Coverity warning
-* td 11/19/20 Updated XSECURE_TEMPORAL_CHECK and
-* XSECURE_TEMPORAL_IMPL to fix MISRA C Rule 15.3
-* 7.4 am 11/26/20 Added Xil_StrCpyRange function
-* 7.6 kpt 07/15/21 Added Xil_SecureZeroize function
-*
-*
-*
-*****************************************************************************/
-
-#ifndef XIL_UTIL_H_
-#define XIL_UTIL_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xstatus.h"
-
-/*************************** Constant Definitions *****************************/
-#define XIL_SIZE_OF_NIBBLE_IN_BITS 4U
-#define XIL_SIZE_OF_BYTE_IN_BITS 8U
-
-/* Maximum string length handled by Xil_ValidateHexStr function */
-#define XIL_MAX_HEX_STR_LEN 512U
-
-
-/****************** Macros (Inline Functions) Definitions *********************/
-#ifdef __GNUC__
-/******************************************************************************/
-/**
- *
- * Updates the return value of the called function into Var and VarTmp variables
- * for redundancy. This is to avoid glitches from altering the return values of
- * security critical functions.
- *
- * @param Var is the variable which holds the return value of function
- * executed
- * @param VarTmp is the variable which holds the value stored in Var
- * @param Function is the function to be executed
- * @param Other params are arguments to the called function
- *
- * @return None
- *
- ******************************************************************************/
-#define XSECURE_TEMPORAL_IMPL(Var, VarTmp, Function, ...) \
- { \
- Var = XST_FAILURE; \
- VarTmp = XST_FAILURE; \
- Var = Function(__VA_ARGS__); \
- VarTmp = Var; \
- }
-
-/******************************************************************************/
-/**
- *
- * Adds redundancy while checking the status of the called function.
- * This is to avoid glitches from altering the return values of security
- * critical functions. The macro requires a label to be passed to "go to"
- * in case of error.
- *
- * @param Label is the label defined in function and the control
- * will jump to the label in case of XST_FAILURE
- * @param Status is the variable which holds the return value of
- * function executed
- * @param Function is the function to be executed
- * @param Other params are arguments to the called function
- *
- * @return None
- *
- ******************************************************************************/
-#define XSECURE_TEMPORAL_CHECK(Label, Status, Function, ...) \
- { \
- volatile int StatusTmp = XST_FAILURE; \
- XSECURE_TEMPORAL_IMPL(Status, StatusTmp, Function, __VA_ARGS__); \
- if ((Status != XST_SUCCESS) || \
- (StatusTmp != XST_SUCCESS)) { \
- Status |= StatusTmp;\
- goto Label; \
- } \
- }
-#endif
-
-/*************************** Function Prototypes ******************************/
-/* Ceils the provided float value */
-int Xil_Ceil(float Value);
-
-/* Converts input character to nibble */
-u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num);
-
-/* Convert input hex string to array of 32-bits integers */
-u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len);
-
-/* Waits for specified event */
-u32 Xil_WaitForEvent(u32 RegAddr, u32 EventMask, u32 Event, u32 Timeout);
-
-/* Waits for specified events */
-u32 Xil_WaitForEvents(u32 EventsRegAddr, u32 EventsMask, u32 WaitEvents,
- u32 Timeout, u32* Events);
-
-/* Validate input hex character */
-u32 Xil_IsValidHexChar(const char *Ch);
-
-/* Validate the input string contains only hexadecimal characters */
-u32 Xil_ValidateHexStr(const char *HexStr);
-
-/* Convert string to hex numbers in little enidian format */
-u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len);
-
-/* Returns length of the input string */
-u32 Xil_Strnlen(const char *Str, u32 MaxLen);
-
-/* Convert string to hex numbers in big endian format */
-u32 Xil_ConvertStringToHexBE(const char * Str, u8 * Buf, u32 Len);
-
-/*Read, Modify and Write to an address*/
-void Xil_UtilRMW32(u32 Addr, u32 Mask, u32 Value);
-
-/* Copies source string to destination string */
-int Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size);
-
-/* Copies specified range from source string to destination string */
-int Xil_StrCpyRange(const u8 *Src, u8 *Dst, u32 From, u32 To, u32 MaxSrcLen,
- u32 MaxDstLen);
-
-/* Appends string2 to string1 */
-int Xil_Strcat(char* Str1Ptr, const char* Str2Ptr, const u32 Size);
-
-/* Copies Len bytes from source memory to destination memory */
-int Xil_SecureMemCpy(void * DestPtr, u32 DestPtrLen, const void * SrcPtr, u32 Len);
-
-/* Compares Len bytes from memory1 and memory2 */
-int Xil_MemCmp(const void * Buf1Ptr, const void * Buf2Ptr, u32 Len);
-
-/* Zeroizes the memory of given length */
-int Xil_SecureZeroize(u8 *DataPtr, const u32 Length);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_UTIL_H_ */
-/**
-* @} End of "addtogroup common_utilities".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/46/501ede565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/46/501ede565243001d18b399c1eb9b3628
deleted file mode 100644
index 853ef6b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/46/501ede565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,412 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_io.h
-*
-* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
-*
-* The xil_io.h file contains the interface for the general I/O component, which
-* encapsulates the Input/Output functions for the processors that do not
-* require any special I/O handling.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/29/14 First release
-* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
-* ARM processors
-* 7.20 har 01/03/20 Added Xil_SecureOut32 for avoiding blindwrite for
-* CR-1049218
-* 7.30 kpt 09/21/20 Moved Xil_EndianSwap16 and Xil_EndianSwap32 to
-* xil_io.h and made them as static inline
-* am 10/13/20 Changed the return type of Xil_SecureOut32 function
-* from u32 to int
-* 7.50 dp 02/12/21 Fix compilation error in Xil_EndianSwap32() that occur
-* when -Werror=conversion compiler flag is enabled
-* 7.5 mus 05/17/21 Update the functions with comments. It fixes CR#1067739.
-*
-*
-******************************************************************************/
-
-#ifndef XIL_IO_H /* prevent circular inclusions */
-#define XIL_IO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_printf.h"
-#include "xstatus.h"
-
-#if defined (__MICROBLAZE__)
-#include "mb_interface.h"
-#else
-#include "xpseudo_asm.h"
-#endif
-
-/************************** Function Prototypes ******************************/
-#ifdef ENABLE_SAFETY
-extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
-#endif
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#if defined __GNUC__
-#if defined (__MICROBLAZE__)
-# define INST_SYNC mbar(0)
-# define DATA_SYNC mbar(1)
-# else
-# define SYNCHRONIZE_IO dmb()
-# define INST_SYNC isb()
-# define DATA_SYNC dsb()
-# endif
-#else
-# define SYNCHRONIZE_IO
-# define INST_SYNC
-# define DATA_SYNC
-# define INST_SYNC
-# define DATA_SYNC
-#endif
-
-#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
-#define INLINE inline
-#else
-#define INLINE __inline
-#endif
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading
-* from the specified address and returning the 8 bit Value read from
-* that address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 8 bit Value read from the specified input address.
-
-*
-******************************************************************************/
-static INLINE u8 Xil_In8(UINTPTR Addr)
-{
- return *(volatile u8 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading from
-* the specified address and returning the 16 bit Value read from that
-* address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 16 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u16 Xil_In16(UINTPTR Addr)
-{
- return *(volatile u16 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by
-* reading from the specified address and returning the 32 bit Value
-* read from that address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 32 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u32 Xil_In32(UINTPTR Addr)
-{
- return *(volatile u32 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading the
-* 64 bit Value read from that address.
-*
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 64 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u64 Xil_In64(UINTPTR Addr)
-{
- return *(volatile u64 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for an memory location by
-* writing the 8 bit Value to the the specified address.
-*
-* @param Addr: contains the address to perform the output operation
-* @param Value: contains the 8 bit Value to be written at the specified
-* address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
-{
- /* write 8 bit value to specified address */
- volatile u8 *LocalAddr = (volatile u8 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 16 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains the Value to be written at the specified address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
-{
- /* write 16 bit value to specified address */
- volatile u16 *LocalAddr = (volatile u16 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 32 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains the 32 bit Value to be written at the specified
-* address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
-{
- /* write 32 bit value to specified address */
-#ifndef ENABLE_SAFETY
- volatile u32 *LocalAddr = (volatile u32 *)Addr;
- *LocalAddr = Value;
-#else
- XStl_RegUpdate(Addr, Value);
-#endif
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 64 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains 64 bit Value to be written at the specified address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
-{
- /* write 64 bit value to specified address */
- volatile u64 *LocalAddr = (volatile u64 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
- *
- * @brief Performs an output operation for a memory location by writing the
- * 32 bit Value to the the specified address and then reading it
- * back to verify the value written in the register.
- *
- * @param Addr contains the address to perform the output operation
- * @param Value contains 32 bit Value to be written at the specified address
- *
- * @return Returns Status
- * - XST_SUCCESS on success
- * - XST_FAILURE on failure
- *
- *****************************************************************************/
-static INLINE int Xil_SecureOut32(UINTPTR Addr, u32 Value)
-{
- int Status = XST_FAILURE;
- u32 ReadReg;
- u32 ReadRegTemp;
-
- /* writing 32 bit value to specified address */
- Xil_Out32(Addr, Value);
-
- /* verify value written to specified address with multiple reads */
- ReadReg = Xil_In32(Addr);
- ReadRegTemp = Xil_In32(Addr);
-
- if( (ReadReg == Value) && (ReadRegTemp == Value) ) {
- Status = XST_SUCCESS;
- }
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a 16-bit endian conversion.
-*
-* @param Data: 16 bit value to be converted
-*
-* @return 16 bit Data with converted endianness
-*
-******************************************************************************/
-static INLINE __attribute__((always_inline)) u16 Xil_EndianSwap16(u16 Data)
-{
- return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a 32-bit endian conversion.
-*
-* @param Data: 32 bit value to be converted
-*
-* @return 32 bit data with converted endianness
-*
-******************************************************************************/
-static INLINE __attribute__((always_inline)) u32 Xil_EndianSwap32(u32 Data)
-{
- u16 LoWord;
- u16 HiWord;
-
- /* get each of the half words from the 32 bit word */
-
- LoWord = (u16) (Data & 0x0000FFFFU);
- HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
-
- /* byte swap each of the 16 bit half words */
-
- LoWord = (u16)(((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
- HiWord = (u16)(((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
-
- /* swap the half words before returning the value */
-
- return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-# define Xil_In16LE Xil_In16
-# define Xil_In32LE Xil_In32
-# define Xil_Out16LE Xil_Out16
-# define Xil_Out32LE Xil_Out32
-# define Xil_Htons Xil_EndianSwap16
-# define Xil_Htonl Xil_EndianSwap32
-# define Xil_Ntohs Xil_EndianSwap16
-# define Xil_Ntohl Xil_EndianSwap32
-# else
-# define Xil_In16BE Xil_In16
-# define Xil_In32BE Xil_In32
-# define Xil_Out16BE Xil_Out16
-# define Xil_Out32BE Xil_Out32
-# define Xil_Htons(Data) (Data)
-# define Xil_Htonl(Data) (Data)
-# define Xil_Ntohs(Data) (Data)
-# define Xil_Ntohl(Data) (Data)
-#endif
-#else
-# define Xil_In16LE Xil_In16
-# define Xil_In32LE Xil_In32
-# define Xil_Out16LE Xil_Out16
-# define Xil_Out32LE Xil_Out32
-# define Xil_Htons Xil_EndianSwap16
-# define Xil_Htonl Xil_EndianSwap32
-# define Xil_Ntohs Xil_EndianSwap16
-# define Xil_Ntohl Xil_EndianSwap32
-#endif
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE u16 Xil_In16BE(UINTPTR Addr)
-#else
-static INLINE u16 Xil_In16LE(UINTPTR Addr)
-#endif
-#else
-static INLINE u16 Xil_In16BE(UINTPTR Addr)
-#endif
-{
- u16 value = Xil_In16(Addr);
- return Xil_EndianSwap16(value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE u32 Xil_In32BE(UINTPTR Addr)
-#else
-static INLINE u32 Xil_In32LE(UINTPTR Addr)
-#endif
-#else
-static INLINE u32 Xil_In32BE(UINTPTR Addr)
-#endif
-{
- u32 value = Xil_In32(Addr);
- return Xil_EndianSwap32(value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
-#else
-static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
-#endif
-#else
-static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
-#endif
-{
- Value = Xil_EndianSwap16(Value);
- Xil_Out16(Addr, Value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
-#else
-static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
-#endif
-#else
-static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
-#endif
-{
- Value = Xil_EndianSwap32(Value);
- Xil_Out32(Addr, Value);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_io_interfacing_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/46/612b18555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/46/612b18555243001d18b399c1eb9b3628
deleted file mode 100644
index 62a929e..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/46/612b18555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,124 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_mmu.c
-*
-* This file provides APIs for enabling/disabling MMU and setting the memory
-* attributes for sections, in the MMU translation table.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.2 pkp 28/05/15 First release
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-#include "xil_mmu.h"
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-extern u32 MMUTable;
-
-/************************** Function Prototypes ******************************/
-/*****************************************************************************/
-/**
-* @brief This function sets the memory attributes for a section covering 1MB
-* of memory in the translation table.
-*
-* @param Addr: 32-bit address for which the attributes need to be set.
-* @param attrib: Attributes for the specified memory region. xil_mmu.h
-* contains commonly used memory attributes definitions which can be
-* utilized for this function.
-*
-*
-* @return None.
-*
-* @note The MMU or D-cache does not need to be disabled before changing a
-* translation table entry.
-*
-******************************************************************************/
-void Xil_SetTlbAttributes(UINTPTR Addr, u32 attrib)
-{
- u32 *ptr;
- u32 section;
-
- section = Addr / 0x100000U;
- ptr = &MMUTable;
- ptr += section;
- if(ptr != NULL) {
- *ptr = (Addr & 0xFFF00000U) | attrib;
- }
-
- Xil_DCacheFlush();
-
- mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
- /* Invalidate all branch predictors */
- mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
-
- dsb(); /* ensure completion of the BP and TLB invalidation */
- isb(); /* synchronize context on this processor */
-}
-
-/*****************************************************************************/
-/**
-* @brief Enable MMU for Cortex-A53 processor in 32bit mode. This function
-* invalidates the instruction and data caches before enabling MMU.
-*
-* @return None.
-*
-******************************************************************************/
-void Xil_EnableMMU(void)
-{
- u32 Reg;
- Xil_DCacheInvalidate();
- Xil_ICacheInvalidate();
-
- Reg = mfcp(XREG_CP15_SYS_CONTROL);
- Reg |= (u32)0x05U;
- mtcp(XREG_CP15_SYS_CONTROL, Reg);
-
- dsb();
- isb();
-}
-
-/*****************************************************************************/
-/**
-* @brief Disable MMU for Cortex A53 processors in 32bit mode. This function
-* invalidates the TLBs, Branch Predictor Array and flushed the data
-* cache before disabling the MMU.
-*
-* @return None.
-*
-* @note When the MMU is disabled, all the memory accesses are treated as
-* strongly ordered.
-******************************************************************************/
-void Xil_DisableMMU(void)
-{
- u32 Reg;
-
- mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
- mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
- Xil_DCacheFlush();
- Reg = mfcp(XREG_CP15_SYS_CONTROL);
- Reg &= (u32)(~0x05U);
- mtcp(XREG_CP15_SYS_CONTROL, Reg);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/46/929ce3565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/46/929ce3565243001d18b399c1eb9b3628
deleted file mode 100644
index c52d476..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/46/929ce3565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,447 +0,0 @@
-/******************************************************************************
-* Copyright (c) 1995 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-*******************************************************************************/
-/*---------------------------------------------------*/
-/* Modified from : */
-/* Public Domain version of printf */
-/* Rud Merriam, Compsult, Inc. Houston, Tx. */
-/* For Embedded Systems Programming, 1991 */
-/* */
-/*---------------------------------------------------*/
-#include "xil_printf.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include
-#include
-#include
-
-static void padding( const s32 l_flag,const struct params_s *par);
-static void outs(const charptr lp, struct params_s *par);
-static s32 getnum( charptr* linep);
-
-typedef struct params_s {
- s32 len;
- s32 num1;
- s32 num2;
- char8 pad_character;
- s32 do_padding;
- s32 left_flag;
- s32 unsigned_flag;
-} params_t;
-
-
-/*---------------------------------------------------*/
-/* The purpose of this routine is to output data the */
-/* same as the standard printf function without the */
-/* overhead most run-time libraries involve. Usually */
-/* the printf brings in many kilobytes of code and */
-/* that is unacceptable in most embedded systems. */
-/*---------------------------------------------------*/
-
-
-/*---------------------------------------------------*/
-/* */
-/* This routine puts pad characters into the output */
-/* buffer. */
-/* */
-static void padding( const s32 l_flag, const struct params_s *par)
-{
- s32 i;
-
- if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) {
- i=(par->len);
- for (; i<(par->num1); i++) {
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( par->pad_character);
-#endif
- }
- }
-}
-
-/*---------------------------------------------------*/
-/* */
-/* This routine moves a string to the output buffer */
-/* as directed by the padding and positioning flags. */
-/* */
-static void outs(const charptr lp, struct params_s *par)
-{
- charptr LocalPtr;
- LocalPtr = lp;
- /* pad on left if needed */
- if(LocalPtr != NULL) {
- par->len = (s32)strlen( LocalPtr);
- padding( !(par->left_flag), par);
- /* Move string to the buffer */
- while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) {
- (par->num2)--;
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte(*LocalPtr);
-#endif
- LocalPtr += 1;
- }
-}
-
- /* Pad on right if needed */
- /* CR 439175 - elided next stmt. Seemed bogus. */
- /* par->len = strlen( lp) */
- padding( par->left_flag, par);
-}
-
-/*---------------------------------------------------*/
-/* */
-/* This routine moves a number to the output buffer */
-/* as directed by the padding and positioning flags. */
-/* */
-
-static void outnum( const s32 n, const s32 base, struct params_s *par)
-{
- s32 negative;
- s32 i;
- char8 outbuf[32];
- const char8 digits[] = "0123456789ABCDEF";
- u32 num;
- for(i = 0; i<32; i++) {
- outbuf[i] = '0';
- }
-
- /* Check if number is negative */
- if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
- negative = 1;
- num =(-(n));
- }
- else{
- num = n;
- negative = 0;
- }
-
- /* Build number (backwards) in outbuf */
- i = 0;
- do {
- outbuf[i] = digits[(num % base)];
- i++;
- num /= base;
- } while (num > 0);
-
- if (negative != 0) {
- outbuf[i] = '-';
- i++;
- }
-
- outbuf[i] = '\0';
- i--;
-
- /* Move the converted number to the buffer and */
- /* add in the padding where needed. */
- par->len = (s32)strlen(outbuf);
- padding( !(par->left_flag), par);
- while (&outbuf[i] >= outbuf) {
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( outbuf[i] );
-#endif
- i--;
-}
- padding( par->left_flag, par);
-}
-/*---------------------------------------------------*/
-/* */
-/* This routine moves a 64-bit number to the output */
-/* buffer as directed by the padding and positioning */
-/* flags. */
-/* */
-#if defined (__aarch64__) || defined (__arch64__)
-static void outnum1( const s64 n, const s32 base, params_t *par)
-{
- s32 negative;
- s32 i;
- char8 outbuf[64];
- const char8 digits[] = "0123456789ABCDEF";
- u64 num;
- for(i = 0; i<64; i++) {
- outbuf[i] = '0';
- }
-
- /* Check if number is negative */
- if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
- negative = 1;
- num =(-(n));
- }
- else{
- num = (n);
- negative = 0;
- }
-
- /* Build number (backwards) in outbuf */
- i = 0;
- do {
- outbuf[i] = digits[(num % base)];
- i++;
- num /= base;
- } while (num > 0);
-
- if (negative != 0) {
- outbuf[i] = '-';
- i++;
- }
-
- outbuf[i] = '\0';
- i--;
-
- /* Move the converted number to the buffer and */
- /* add in the padding where needed. */
- par->len = (s32)strlen(outbuf);
- padding( !(par->left_flag), par);
- while (&outbuf[i] >= outbuf) {
- outbyte( outbuf[i] );
- i--;
-}
- padding( par->left_flag, par);
-}
-#endif
-/*---------------------------------------------------*/
-/* */
-/* This routine gets a number from the format */
-/* string. */
-/* */
-static s32 getnum(charptr* linep)
-{
- s32 n = 0;
- s32 ResultIsDigit = 0;
- charptr cptr = *linep;
-
- while (cptr != NULL) {
- ResultIsDigit = isdigit(((s32)*cptr));
- if (ResultIsDigit == 0)
- break;
- n = ((n*10) + (((s32)*cptr) - (s32)'0'));
- cptr += 1;
- }
-
- *linep = ((charptr)(cptr));
- return(n);
-}
-
-/*---------------------------------------------------*/
-/* */
-/* This routine operates just like a printf/sprintf */
-/* routine. It outputs a set of data under the */
-/* control of a formatting string. Not all of the */
-/* standard C format control are supported. The ones */
-/* provided are primarily those needed for embedded */
-/* systems work. Primarily the floating point */
-/* routines are omitted. Other formats could be */
-/* added easily by following the examples shown for */
-/* the supported formats. */
-/* */
-
-/* void esp_printf( const func_ptr f_ptr,
- const charptr ctrl1, ...) */
-#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
-void xil_printf( const char8 *ctrl1, ...){
- XPVXenConsole_Printf(ctrl1);
-}
-#else
-void xil_printf( const char8 *ctrl1, ...)
-{
- va_list argp;
-
- va_start(argp, ctrl1);
-
- xil_vprintf(ctrl1, argp);
-
- va_end(argp);
-}
-#endif
-
-/* This routine is equivalent to vprintf routine */
-void xil_vprintf(const char8 *ctrl1, va_list argp)
-{
- s32 Check;
-#if defined (__aarch64__) || defined (__arch64__)
- s32 long_flag;
-#endif
- s32 dot_flag;
-
- params_t par;
-
- char8 ch;
- char8 *ctrl = (char8 *)ctrl1;
-
- while ((ctrl != NULL) && (*ctrl != (char8)0)) {
-
- /* move format string chars to buffer until a */
- /* format control is found. */
- if (*ctrl != '%') {
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte(*ctrl);
-#endif
- ctrl += 1;
- continue;
- }
-
- /* initialize all the flags for this format. */
- dot_flag = 0;
-#if defined (__aarch64__) || defined (__arch64__)
- long_flag = 0;
-#endif
- par.unsigned_flag = 0;
- par.left_flag = 0;
- par.do_padding = 0;
- par.pad_character = ' ';
- par.num2=32767;
- par.num1=0;
- par.len=0;
-
- try_next:
- if(ctrl != NULL) {
- ctrl += 1;
- }
- if(ctrl != NULL) {
- ch = *ctrl;
- } else {
- break;
- }
-
- if (isdigit((s32)ch) != 0) {
- if (dot_flag != 0) {
- par.num2 = getnum(&ctrl);
- }
- else {
- if (ch == '0') {
- par.pad_character = '0';
- }
- if(ctrl != NULL) {
- par.num1 = getnum(&ctrl);
- }
- par.do_padding = 1;
- }
- if(ctrl != NULL) {
- ctrl -= 1;
- }
- goto try_next;
- }
-
- switch (tolower((s32)ch)) {
- case '%':
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( '%');
-#endif
- Check = 1;
- break;
-
- case '-':
- par.left_flag = 1;
- Check = 0;
- break;
-
- case '.':
- dot_flag = 1;
- Check = 0;
- break;
-
- case 'l':
- #if defined (__aarch64__) || defined (__arch64__)
- long_flag = 1;
- #endif
- Check = 0;
- break;
-
- case 'u':
- par.unsigned_flag = 1;
- /* fall through */
- case 'i':
- case 'd':
- #if defined (__aarch64__) || defined (__arch64__)
- if (long_flag != 0){
- outnum1((s64)va_arg(argp, s64), 10L, &par);
- }
- else {
- outnum( va_arg(argp, s32), 10L, &par);
- }
- #else
- outnum( va_arg(argp, s32), 10L, &par);
- #endif
- Check = 1;
- break;
- case 'p':
- #if defined (__aarch64__) || defined (__arch64__)
- par.unsigned_flag = 1;
- outnum1((s64)va_arg(argp, s64), 16L, &par);
- Check = 1;
- break;
- #endif
- case 'X':
- case 'x':
- par.unsigned_flag = 1;
- #if defined (__aarch64__) || defined (__arch64__)
- if (long_flag != 0) {
- outnum1((s64)va_arg(argp, s64), 16L, &par);
- }
- else {
- outnum((s32)va_arg(argp, s32), 16L, &par);
- }
- #else
- outnum((s32)va_arg(argp, s32), 16L, &par);
- #endif
- Check = 1;
- break;
-
- case 's':
- outs( va_arg( argp, char *), &par);
- Check = 1;
- break;
-
- case 'c':
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( va_arg( argp, s32));
-#endif
- Check = 1;
- break;
-
- case '\\':
- switch (*ctrl) {
- case 'a':
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( ((char8)0x07));
-#endif
- break;
- case 'h':
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( ((char8)0x08));
-#endif
- break;
- case 'r':
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( ((char8)0x0D));
-#endif
- break;
- case 'n':
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( ((char8)0x0D));
- outbyte( ((char8)0x0A));
-#endif
- break;
- default:
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( *ctrl);
-#endif
- break;
- }
- ctrl += 1;
- Check = 0;
- break;
-
- default:
- Check = 1;
- break;
- }
- if(Check == 1) {
- if(ctrl != NULL) {
- ctrl += 1;
- }
- continue;
- }
- goto try_next;
- }
-}
-/*---------------------------------------------------*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/46/c1b3bd585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/46/c1b3bd585243001d18b399c1eb9b3628
deleted file mode 100644
index aeb2024..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/46/c1b3bd585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,22 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/*
- *
- * The "remove" function should remove the file named "filename". It
- * should return 0 on success and nonzero on failure.
- *
- */
-
-#include
-#include "xil_types.h"
-
-sint32 remove(const char8 * filename);
-
-sint32 remove(const char8 * filename)
-{
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/46/d0a704595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/46/d0a704595243001d18b399c1eb9b3628
deleted file mode 100644
index df70f9f..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/46/d0a704595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,154 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2020 - 2021 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: MIT
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm_armclang.h
-*
-* This header file contains macros for using inline assembler code. It is
-* written specifically for the GNU compiler.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 7.3 dp 06/25/20 Initial version for armclang
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
-* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler.
-* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.
-* 7.0 mus 01/03/19 Tweak Xil_ExceptionEnableMask and
-* Xil_ExceptionDisableMask macros to support legacy
-* examples for Cortexa72 EL3 exception level.
-* 7.3 mus 04/15/20 Added Xil_EnableNestedInterrupts and
-* Xil_DisableNestedInterrupts macros for ARMv8.
-* For Cortexa72, these macro's would not be supported
-* at EL3, as Cortexa72 is using GIC-500(GICv3), which
-* triggeres only FIQ at EL3. Fix for CR#1062506
-# 7.6 mus 09/17/21 Updated flag checking to fix warning reported with
-# -Wundef compiler option CR#1110261
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
-#define XIL_EXCEPTION_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#include "bspconfig.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions ****************************/
-
-#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
-#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
-#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
-
-#define XIL_EXCEPTION_ID_FIRST 0U
-#if defined (__aarch64__)
-#define XIL_EXCEPTION_ID_SYNC_INT 1U
-#define XIL_EXCEPTION_ID_IRQ_INT 2U
-#define XIL_EXCEPTION_ID_FIQ_INT 3U
-#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
-#define XIL_EXCEPTION_ID_LAST 5U
-#else
-#define XIL_EXCEPTION_ID_RESET 0U
-#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
-#define XIL_EXCEPTION_ID_SWI_INT 2U
-#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
-#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
-#define XIL_EXCEPTION_ID_IRQ_INT 5U
-#define XIL_EXCEPTION_ID_FIQ_INT 6U
-#define XIL_EXCEPTION_ID_LAST 6U
-#endif
-
-/*
- * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
- */
-#if defined (versal) && !defined(ARMR5) && EL3
-#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_FIQ_INT
-#else
-#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
-#endif
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef is the exception handler function.
- */
-typedef void (*Xil_ExceptionHandler)(void *data);
-typedef void (*Xil_InterruptHandler)(void *data);
-
-/**
-*@endcond
-*/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* @brief Enable Exceptions.
-*
-* @param Mask: Value for enabling the exceptions.
-*
-* @return None.
-*
-* @note If bit is 0, exception is enabled.
-* C-Style signature: void Xil_ExceptionEnableMask(Mask)
-*
-******************************************************************************/
-#if defined (versal) && !defined(ARMR5) && EL3
-/*
- * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
- * only FIQ at EL3. Hence, tweaking this macro to always enable FIQ
- * ignoring argument passed by user.
- */
-#define Xil_ExceptionEnableMask(Mask) \
- mtcpsr(mfcpsr() & ~ ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
-#elif defined (__GNUC__) || defined (__ICCARM__)
-#define Xil_ExceptionEnableMask(Mask) \
- mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
-#else
-#define Xil_ExceptionEnableMask(Mask) \
- { \
- register u32 Reg __asm("cpsr"); \
- mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
- }
-#endif
-/****************************************************************************/
-/**
-* @brief Enable the IRQ exception.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-#if defined (versal) && !defined(ARMR5) && EL3
-#define Xil_ExceptionEnable() \
- Xil_ExceptionEnableMask(XIL_EXCEPTION_FIQ)
-#else
-#define Xil_ExceptionEnable() \
- Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
-#endif
-
-/****************************************************************************/
-/**
-* @brief Disable Exceptions.
-*
-* @param Mask: Value for disabling the exceptions.
-*
-* @return None.
-*
-* @note If bit is 1, exception is disabled.
-* C-Style signature: Xil_ExceptionDisableMask(Mask)
-*
-******************************************************************************/
-#if defined (versal) && !defined(ARMR5) && EL3
-/*
- * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
- * only FIQ at EL3. Hence, tweaking this macro to always disable FIQ
- * ignoring argument passed by user.
- */
-#define Xil_ExceptionDisableMask(Mask) \
- mtcpsr(mfcpsr() | ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
-#elif defined (__GNUC__) || defined (__ICCARM__)
-#define Xil_ExceptionDisableMask(Mask) \
- mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
-#else
-#define Xil_ExceptionDisableMask(Mask) \
- { \
- register u32 Reg __asm("cpsr"); \
- mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
- }
-#endif
-/****************************************************************************/
-/**
-* Disable the IRQ exception.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_ExceptionDisable() \
- Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
-
-#if ( defined (PLATFORM_ZYNQMP) && defined (EL3) && (EL3==1) )
-/****************************************************************************/
-/**
-* @brief Enable nested interrupts by clearing the I bit in DAIF.This
-* macro is defined for Cortex-A53 64 bit mode BSP configured to run
-* at EL3.. However,it is not defined for Versal Cortex-A72 BSP
-* configured to run at EL3. Reason is, Cortex-A72 is coupled
-* with GIC-500(GICv3 specifications) and it triggers only FIQ at EL3.
-*
-* @return None.
-*
-* @note This macro is supposed to be used from interrupt handlers. In the
-* interrupt handler the interrupts are disabled by default (I bit
-* is set as 1). To allow nesting of interrupts, this macro should be
-* used. It clears the I bit. Once that bit is cleared and provided the
-* preemption of interrupt conditions are met in the GIC, nesting of
-* interrupts will start happening.
-* Caution: This macro must be used with caution. Before calling this
-* macro, the user must ensure that the source of the current IRQ
-* is appropriately cleared. Otherwise, as soon as we clear the I
-* bit, there can be an infinite loop of interrupts with an
-* eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
- __asm__ __volatile__ ("mrs X1, ELR_EL3"); \
- __asm__ __volatile__ ("mrs X2, SPSR_EL3"); \
- __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-/****************************************************************************/
-/**
-* @brief Disable the nested interrupts by setting the I bit in DAIF. This
-* macro is defined for Cortex-A53 64 bit mode BSP configured to run
-* at EL3.
-*
-* @return None.
-*
-* @note This macro is meant to be called in the interrupt service routines.
-* This macro cannot be used independently. It can only be used when
-* nesting of interrupts have been enabled by using the macro
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-* point. The user then must call this macro before exiting the interrupt
-* service routine. This macro puts the ARM back in IRQ mode and
-* hence sets back the I bit.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
- __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \
- __asm__ __volatile__ ("msr ELR_EL3, X1"); \
- __asm__ __volatile__ ("msr SPSR_EL3, X2"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-#elif (defined (EL1_NONSECURE) && (EL1_NONSECURE==1))
-/****************************************************************************/
-/**
-* @brief Enable nested interrupts by clearing the I bit in DAIF.This
-* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit
-* BSP configured to run at EL1 NON SECURE
-*
-* @return None.
-*
-* @note This macro is supposed to be used from interrupt handlers. In the
-* interrupt handler the interrupts are disabled by default (I bit
-* is set as 1). To allow nesting of interrupts, this macro should be
-* used. It clears the I bit. Once that bit is cleared and provided the
-* preemption of interrupt conditions are met in the GIC, nesting of
-* interrupts will start happening.
-* Caution: This macro must be used with caution. Before calling this
-* macro, the user must ensure that the source of the current IRQ
-* is appropriately cleared. Otherwise, as soon as we clear the I
-* bit, there can be an infinite loop of interrupts with an
-* eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
- __asm__ __volatile__ ("mrs X1, ELR_EL1"); \
- __asm__ __volatile__ ("mrs X2, SPSR_EL1"); \
- __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-/****************************************************************************/
-/**
-* @brief Disable the nested interrupts by setting the I bit in DAIF. This
-* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit
-* BSP configured to run at EL1 NON SECURE
-*
-* @return None.
-*
-* @note This macro is meant to be called in the interrupt service routines.
-* This macro cannot be used independently. It can only be used when
-* nesting of interrupts have been enabled by using the macro
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-* point. The user then must call this macro before exiting the interrupt
-* service routine. This macro puts the ARM back in IRQ mode and
-* hence sets back the I bit.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
- __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \
- __asm__ __volatile__ ("msr ELR_EL1, X1"); \
- __asm__ __volatile__ ("msr SPSR_EL1, X2"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-#elif (!defined (__aarch64__) && !defined (ARMA53_32))
-/****************************************************************************/
-/**
-* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This
-* API is defined for cortex-a9 and cortex-r5.
-*
-* @return None.
-*
-* @note This macro is supposed to be used from interrupt handlers. In the
-* interrupt handler the interrupts are disabled by default (I and F
-* are 1). To allow nesting of interrupts, this macro should be
-* used. It clears the I and F bits by changing the ARM mode to
-* system mode. Once these bits are cleared and provided the
-* preemption of interrupt conditions are met in the GIC, nesting of
-* interrupts will start happening.
-* Caution: This macro must be used with caution. Before calling this
-* macro, the user must ensure that the source of the current IRQ
-* is appropriately cleared. Otherwise, as soon as we clear the I and
-* F bits, there can be an infinite loop of interrupts with an
-* eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
- __asm__ __volatile__ ("stmfd sp!, {lr}"); \
- __asm__ __volatile__ ("mrs lr, spsr"); \
- __asm__ __volatile__ ("stmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
- __asm__ __volatile__ ("stmfd sp!, {lr}");
-/****************************************************************************/
-/**
-* @brief Disable the nested interrupts by setting the I and F bits. This API
-* is defined for cortex-a9 and cortex-r5.
-*
-* @return None.
-*
-* @note This macro is meant to be called in the interrupt service routines.
-* This macro cannot be used independently. It can only be used when
-* nesting of interrupts have been enabled by using the macro
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-* point. The user then must call this macro before exiting the interrupt
-* service routine. This macro puts the ARM back in IRQ/FIQ mode and
-* hence sets back the I and F bits.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr cpsr_c, #0x92"); \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr spsr_cxsf, lr"); \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
-
-#endif
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler Handler,
- void *Data);
-
-extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
-extern void Xil_GetExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler *Handler, void **Data);
-
-extern void Xil_ExceptionInit(void);
-#if defined (__aarch64__)
-void Xil_SyncAbortHandler(void *CallBackRef);
-void Xil_SErrorAbortHandler(void *CallBackRef);
-#else
-extern void Xil_DataAbortHandler(void *CallBackRef);
-extern void Xil_PrefetchAbortHandler(void *CallBackRef);
-extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
-#endif
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_EXCEPTION_H */
-/**
-* @} End of "addtogroup arm_exception_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/47/510e46545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/47/510e46545243001d18b399c1eb9b3628
deleted file mode 100644
index 60f4ba3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/47/510e46545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,53 +0,0 @@
-/******************************************************************************
-* Copyright (c) 1995 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-*******************************************************************************/
- #ifndef XIL_PRINTF_H
- #define XIL_PRINTF_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include
-#include
-#include
-#include "xil_types.h"
-#include "xparameters.h"
-#include "bspconfig.h"
-#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
-#include "xen_console.h"
-#endif
-
-/*----------------------------------------------------*/
-/* Use the following parameter passing structure to */
-/* make xil_printf re-entrant. */
-/*----------------------------------------------------*/
-
-struct params_s;
-
-
-/*---------------------------------------------------*/
-/* The purpose of this routine is to output data the */
-/* same as the standard printf function without the */
-/* overhead most run-time libraries involve. Usually */
-/* the printf brings in many kilobytes of code and */
-/* that is unacceptable in most embedded systems. */
-/*---------------------------------------------------*/
-
-typedef char8* charptr;
-typedef s32 (*func_ptr)(int c);
-
-/* */
-
-void xil_printf( const char8 *ctrl1, ...);
-void xil_vprintf(const char8 *ctrl1, va_list argp);
-void print( const char8 *ptr);
-extern void outbyte (char8 c);
-extern char8 inbyte(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/47/90c40c565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/47/90c40c565243001d18b399c1eb9b3628
deleted file mode 100644
index 9c6058d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/47/90c40c565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,9 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: MIT
-*
-******************************************************************************/
-
-/* Stub call for argv veneer */
-void __ARM_argv_veneer(void) {};
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/47/b0b548595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/47/b0b548595243001d18b399c1eb9b3628
deleted file mode 100644
index 2668199..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/47/b0b548595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,3 +0,0 @@
-LIBSOURCES = *.c *.S
-PROFILE_ARCH_OBJS = profile_mcount_arm.o
-LIBS = standalone_libs
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/48/00de59575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/48/00de59575243001d18b399c1eb9b3628
deleted file mode 100644
index b80c577..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/48/00de59575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,281 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#ifndef PROFILE_TIMER_HW_H
-#define PROFILE_TIMER_HW_H
-
-#include "profile.h"
-
-#ifdef PROC_PPC
-#if defined __GNUC__
-# define SYNCHRONIZE_IO __asm__ volatile ("eieio")
-#elif defined __DCC__
-# define SYNCHRONIZE_IO __asm volatile(" eieio")
-#else
-# define SYNCHRONIZE_IO
-#endif
-#endif
-
-#ifdef PROC_PPC
-#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
-#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
-#else
-#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
-#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
-#endif
-
-#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
- ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \
- (u32)(RegOffset)), (u32)(ValueToWrite))
-
-#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
- ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
-
-#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
- ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (RegisterValue))
-
-#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \
- ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
-
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef PROC_PPC
-#include "xexception_l.h"
-#include "xtime_l.h"
-#include "xpseudo_asm.h"
-#endif
-
-#ifdef TIMER_CONNECT_INTC
-#include "xintc_l.h"
-#include "xintc.h"
-#endif /* TIMER_CONNECT_INTC */
-
-#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
-#include "xtmrctr_l.h"
-#endif
-
-#ifdef PROC_CORTEXA9
-#include "xscutimer_hw.h"
-#include "xscugic.h"
-#endif
-
-extern u32 timer_clk_ticks ;
-
-/*--------------------------------------------------------------------
- * PowerPC Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_PPC
-
-#ifdef PPC_PIT_INTERRUPT
-u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */
-#endif
-
-#ifdef PROC_PPC440
-#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
-#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
-#define XREG_SPR_PIT XREG_SPR_DEC
-#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
-#endif
-
-/* --------------------------------------------------------------------
- * Disable the Timer - During Profiling
- *
- * For PIT Timer -
- * 1. XTime_PITDisableInterrupt() ;
- * 2. Store the remaining timer clk tick
- * 3. Stop the PIT Timer
- *-------------------------------------------------------------------- */
-
-#ifdef PPC_PIT_INTERRUPT
-#define disable_timer() \
- { \
- u32 val; \
- val=mfspr(XREG_SPR_TCR); \
- mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \
- timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
- mtspr(XREG_SPR_PIT, 0); \
- }
-#else
-#define disable_timer() \
- { \
- u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(addr); \
- tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
- ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
- }
-#endif
-
-
-
-/* --------------------------------------------------------------------
- * Enable the Timer
- *
- * For PIT Timer -
- * 1. Load the remaining timer clk ticks
- * 2. XTime_PITEnableInterrupt() ;
- *-------------------------------------------------------------------- */
-#ifdef PPC_PIT_INTERRUPT
-#define enable_timer() \
- { \
- u32 val; \
- val=mfspr(XREG_SPR_TCR); \
- mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
- mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
- }
-#else
-#define enable_timer() \
- { \
- u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(addr); \
- tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
- ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
- }
-#endif
-
-
-
-/* --------------------------------------------------------------------
- * Send Ack to Timer Interrupt
- *
- * For PIT Timer -
- * 1. Load the timer clk ticks
- * 2. Enable AutoReload and Interrupt
- * 3. Clear PIT Timer Status bits
- *-------------------------------------------------------------------- */
-#ifdef PPC_PIT_INTERRUPT
-#define timer_ack() \
- { \
- u32 val; \
- mtspr(XREG_SPR_PIT, timer_clk_ticks); \
- mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
- val=mfspr(XREG_SPR_TCR); \
- mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
- }
-#else
-#define timer_ack() \
- { \
- u32 csr; \
- csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
- ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
- }
-#endif
-
-/*-------------------------------------------------------------------- */
-#endif /* PROC_PPC */
-/* -------------------------------------------------------------------- */
-
-
-
-
-/* --------------------------------------------------------------------
- * MicroBlaze Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_MICROBLAZE
-
-/* --------------------------------------------------------------------
- * Disable the Timer during Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define disable_timer() \
- { \
- u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
- Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
- Addr += (u32)XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(Addr); \
- tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
- u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
- OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
- OutAddr += (u32)XTC_TCSR_OFFSET; \
- ProfIo_Out32(OutAddr, (u32)tmp_v); \
- }
-
-
-/* --------------------------------------------------------------------
- * Enable the Timer after Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define enable_timer() \
- { \
- u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
- Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
- Addr += (u32)XTC_TCSR_OFFSET; \
- u32 tmp_v = (u32)ProfIo_In32(Addr); \
- tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \
- ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
- }
-
-
-/* --------------------------------------------------------------------
- * Send Ack to Timer Interrupt
- *
- *-------------------------------------------------------------------- */
-#define timer_ack() \
- { \
- u32 csr; \
- csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \
- ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \
- }
-
-/*-------------------------------------------------------------------- */
-#endif /* PROC_MICROBLAZE */
-/*-------------------------------------------------------------------- */
-
-/* --------------------------------------------------------------------
- * Cortex A9 Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_CORTEXA9
-
-/* --------------------------------------------------------------------
- * Disable the Timer during Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define disable_timer() \
-{ \
- u32 Reg; \
- Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
- Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
- Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
-}
-
-
-/* --------------------------------------------------------------------
- * Enable the Timer after Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define enable_timer() \
-{ \
- u32 Reg; \
- Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
- Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
- Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
-}
-
-
-/* --------------------------------------------------------------------
- * Send Ack to Timer Interrupt
- *
- *-------------------------------------------------------------------- */
-#define timer_ack() \
-{ \
- Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
- (u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
-}
-
-/*-------------------------------------------------------------------- */
-#endif /* PROC_CORTEXA9 */
-/*-------------------------------------------------------------------- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/48/100578525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/48/100578525243001d18b399c1eb9b3628
deleted file mode 100644
index 6f009c6..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/48/100578525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,24 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 2021.2
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2022 Xilinx, Inc. All Rights Reserved.
-* SPDX-License-Identifier: MIT
-
-*
-* Description: Configurations for Standalone BSP
-*
-*******************************************************************/
-
-#ifndef BSPCONFIG_H /* prevent circular inclusions */
-#define BSPCONFIG_H /* by using protection macros */
-
-#define MICROBLAZE_PVR_NONE
-
-/* Definition for hard-float ABI */
-#define FPU_HARD_FLOAT_ABI_ENABLED 1
-
-#endif /*end of __BSPCONFIG_H_*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/48/922be1565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/48/922be1565243001d18b399c1eb9b3628
deleted file mode 100644
index 878d575..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/48/922be1565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,261 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_misc_psreset_api.h
-*
-* This file contains the various register definitions and function prototypes for
-* implementing the reset functionality of zynq ps devices
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00b kpc 03/07/13 First release.
-*
-*
-******************************************************************************/
-
-#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */
-#define XIL_MISC_RESET_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/**
- *@cond nocomments
- */
-
-#define XDDRC_CTRL_BASEADDR 0xF8006000U
-#define XSLCR_BASEADDR 0xF8000000U
-/**< OCM configuration register */
-#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U)
-/**< SLCR unlock register */
-#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U)
-/**< SLCR GEM0 rx clock control register */
-#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U)
-/**< SLCR GEM1 rx clock control register */
-#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU)
-/**< SLCR GEM0 clock control register */
-#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U)
-/**< SLCR GEM1 clock control register */
-#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U)
-/**< SLCR SMC clock control register */
-#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U)
-/**< SLCR GEM reset control register */
-#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)
-/**< SLCR USB0 clock control register */
-#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U)
-/**< SLCR USB1 clock control register */
-#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U)
-/**< SLCR USB1 reset control register */
-#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)
-/**< SLCR SMC reset control register */
-#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)
-/**< SLCR Level shifter enable register */
-#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U)
-/**< SLCR ARM pll control register */
-#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U)
-/**< SLCR DDR pll control register */
-#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U)
-/**< SLCR IO pll control register */
-#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U)
-/**< SLCR ARM pll configuration register */
-#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U)
-/**< SLCR DDR pll configuration register */
-#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U)
-/**< SLCR IO pll configuration register */
-#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U)
-/**< SLCR ARM clock control register */
-#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U)
-/**< SLCR DDR clock control register */
-#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U)
-/**< SLCR MIO pin address register */
-#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U)
-/**< SLCR DMAC reset control address register */
-#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU)
-/**< SLCR USB reset control address register */
-/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/
-/**< SLCR GEM reset control address register */
-/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/
-/**< SLCR SDIO reset control address register */
-#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U)
-/**< SLCR SPI reset control address register */
-#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU)
-/**< SLCR CAN reset control address register */
-#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U)
-/**< SLCR I2C reset control address register */
-#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U)
-/**< SLCR UART reset control address register */
-#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U)
-/**< SLCR GPIO reset control address register */
-#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU)
-/**< SLCR LQSPI reset control address register */
-#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U)
-/**< SLCR SMC reset control address register */
-/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/
-/**< SLCR OCM reset control address register */
-#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U)
-
-/**< SMC mem controller clear config register */
-#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU
-/**< SMC idlecount configuration register */
-#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U
-#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U
-/**< SMC ECC configuration register */
-#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U
-/**< SMC ECC command 1 register */
-#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U
-/**< SMC ECC command 2 register */
-#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U
-
-/**< SLCR unlock code */
-#define XSLCR_UNLOCK_CODE 0x0000DF0DU
-
-/**< SMC mem clear configuration mask */
-#define XSMC_MEMC_CLR_CONFIG_MASK 0x000005FU
-/**< SMC ECC memconfig 1 reset value */
-#define XSMC_ECC_MEMCFG1_RESET_VAL 0x0000043U
-/**< SMC ECC memcommand 1 reset value */
-#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U
-/**< SMC ECC memcommand 2 reset value */
-#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U
-
-/**< DDR controller reset bit mask */
-#define XDDRPS_CTRL_RESET_MASK 0x00000001U
-/**< SLCR OCM configuration reset value*/
-#define XSLCR_OCM_CFG_RESETVAL 0x00000008U
-/**< SLCR OCM bank selection mask*/
-#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU
-/**< SLCR level shifter enable mask*/
-#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU
-
-/**< SLCR PLL register reset values */
-#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U
-#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U
-#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U
-#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U
-#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U
-#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U
-#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U
-#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U
-
-/**< SLCR MIO register default values */
-#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U
-#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U
-
-/**< SLCR Reset control registers default values */
-#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U
-#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U
-#define XSLCR_USB_RST_CTRL_VAL 0x00000003U
-#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U
-#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU
-#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU
-#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U
-#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U
-#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U
-#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U
-#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U
-#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U
-
-/**
- *@endcond
- */
-
-/**************************** Type Definitions *******************************/
-
-/* the following data type is used to hold a null terminated version string
- * consisting of the following format, "X.YYX"
- */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-/*
- * Performs reset operation to the ddr interface
- */
-void XDdr_ResetHw(void);
-/*
- * Map the ocm region to post bootrom state
- */
-void XOcm_Remap(void);
-/*
- * Performs the smc interface reset
- */
-void XSmc_ResetHw(u32 BaseAddress);
-/*
- * updates the MIO registers with reset values
- */
-void XSlcr_MioWriteResetValues(void);
-/*
- * updates the PLL and clock registers with reset values
- */
-void XSlcr_PllWriteResetValues(void);
-/*
- * Disables the level shifters
- */
-void XSlcr_DisableLevelShifters(void);
-/*
- * provides softreset to the GPIO interface
- */
-void XSlcr_GpioPsReset(void);
-/*
- * provides softreset to the DMA interface
- */
-void XSlcr_DmaPsReset(void);
-/*
- * provides softreset to the SMC interface
- */
-void XSlcr_SmcPsReset(void);
-/*
- * provides softreset to the CAN interface
- */
-void XSlcr_CanPsReset(void);
-/*
- * provides softreset to the Uart interface
- */
-void XSlcr_UartPsReset(void);
-/*
- * provides softreset to the I2C interface
- */
-void XSlcr_I2cPsReset(void);
-/*
- * provides softreset to the SPI interface
- */
-void XSlcr_SpiPsReset(void);
-/*
- * provides softreset to the QSPI interface
- */
-void XSlcr_QspiPsReset(void);
-/*
- * provides softreset to the USB interface
- */
-void XSlcr_UsbPsReset(void);
-/*
- * provides softreset to the GEM interface
- */
-void XSlcr_EmacPsReset(void);
-/*
- * provides softreset to the OCM interface
- */
-void XSlcr_OcmReset(void);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_MISC_RESET_H */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/49/000a9a595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/49/000a9a595243001d18b399c1eb9b3628
deleted file mode 100644
index e8b87b5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/49/000a9a595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,176 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_assert.h
-*
-* @addtogroup common_assert_apis Assert APIs and Macros
-*
-* The xil_assert.h file contains assert related functions and macros.
-* Assert APIs/Macros specifies that a application program satisfies certain
-* conditions at particular points in its execution. These function can be
-* used by application programs to ensure that, application code is satisfying
-* certain conditions.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 First release
-* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_ASSERT_H /* prevent circular inclusions */
-#define XIL_ASSERT_H /* by using protection macros */
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-
-
-/************************** Constant Definitions *****************************/
-
-#define XIL_ASSERT_NONE 0U
-#define XIL_ASSERT_OCCURRED 1U
-#define XNULL NULL
-
-extern u32 Xil_AssertStatus;
-extern s32 Xil_AssertWait;
-extern void Xil_Assert(const char8 *File, s32 Line);
-/**
- *@endcond
- */
-void XNullHandler(void *NullParameter);
-
-/**
- * This data type defines a callback to be invoked when an
- * assert occurs. The callback is invoked only when asserts are enabled
- */
-typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#ifndef NDEBUG
-
-/*****************************************************************************/
-/**
-* @brief This assert macro is to be used for void functions. This in
-* conjunction with the Xil_AssertWait boolean can be used to
-* accommodate tests so that asserts which fail allow execution to
-* continue.
-*
-* @param Expression: expression to be evaluated. If it evaluates to
-* false, the assert occurs.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertVoid(Expression) \
-{ \
- if (Expression) { \
- Xil_AssertStatus = XIL_ASSERT_NONE; \
- } else { \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* @brief This assert macro is to be used for functions that do return a
-* value. This in conjunction with the Xil_AssertWait boolean can be
-* used to accommodate tests so that asserts which fail allow execution
-* to continue.
-*
-* @param Expression: expression to be evaluated. If it evaluates to false,
-* the assert occurs.
-*
-* @return Returns 0 unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertNonvoid(Expression) \
-{ \
- if (Expression) { \
- Xil_AssertStatus = XIL_ASSERT_NONE; \
- } else { \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return 0; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* @brief Always assert. This assert macro is to be used for void functions.
-* Use for instances where an assert should always occur.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertVoidAlways() \
-{ \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return; \
-}
-
-/*****************************************************************************/
-/**
-* @brief Always assert. This assert macro is to be used for functions that
-* do return a value. Use for instances where an assert should always
-* occur.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertNonvoidAlways() \
-{ \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return 0; \
-}
-
-
-#else
-
-#define Xil_AssertVoid(Expression)
-#define Xil_AssertVoidAlways()
-#define Xil_AssertNonvoid(Expression)
-#define Xil_AssertNonvoidAlways()
-
-#endif
-
-/************************** Function Prototypes ******************************/
-
-void Xil_AssertSetCallback(Xil_AssertCallback Routine);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_assert_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/49/005c3f585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/49/005c3f585243001d18b399c1eb9b3628
deleted file mode 100644
index b5a1ae7..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/49/005c3f585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,50 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file cpu_init.S
-*
-* This file contains CPU specific initialization. Invoked from main CRT
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 5.2 pkp 28/05/15 First release
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
- .text
- .global __cpu_init
- .align 2
-__cpu_init:
-
-/* Clear cp15 regs with unknown reset values */
- mov r0, #0x0
- mcr p15, 0, r0, c5, c0, 0 /* DFSR */
- mcr p15, 0, r0, c5, c0, 1 /* IFSR */
- mcr p15, 0, r0, c6, c0, 0 /* DFAR */
- mcr p15, 0, r0, c6, c0, 2 /* IFAR */
- mcr p15, 0, r0, c9, c13, 2 /* PMXEVCNTR */
- mcr p15, 0, r0, c13, c0, 2 /* TPIDRURW */
- mcr p15, 0, r0, c13, c0, 3 /* TPIDRURO */
-
-/* Reset and start Cycle Counter */
- mov r2, #0x80000000 /* clear overflow */
- mcr p15, 0, r2, c9, c12, 3
- mov r2, #0xd /* D, C, E */
- mcr p15, 0, r2, c9, c12, 0
- mov r2, #0x80000000 /* enable cycle counter */
- mcr p15, 0, r2, c9, c12, 1
-
- bx lr
-
-.end
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/49/406c15555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/49/406c15555243001d18b399c1eb9b3628
deleted file mode 100644
index 0fe994b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/49/406c15555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,60 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.h
-*
-* @addtogroup a53_32_cache_apis Cortex A53 32bit Processor Cache Functions
-*
-* Cache functions provide access to cache related operations such as flush
-* and invalidate for instruction and data caches. It gives option to perform
-* the cache operations on a single cacheline, a range of memory and an entire
-* cache.
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.2 pkp 28/05/15 First release
-*
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.00a wgr 10/10/10 First release
- *
- *
- *****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xstatus.h"
-#include "xusbps.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-extern XUsbPs_Config XUsbPs_ConfigTable[];
-
-/************************** Function Prototypes *****************************/
-
-/****************************************************************************/
-/**
-*
-* Looks up the controller configuration based on the unique controller ID. A
-* table contains the configuration info for each controller in the system.
-*
-* @param DeviceID is the ID of the controller to look up the
-* configuration for.
-*
-* @return
-* A pointer to the configuration found or NULL if the specified
-* controller ID was not found.
-*
-******************************************************************************/
-XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceID)
-{
- XUsbPs_Config *CfgPtr = NULL;
-
- int Index;
-
- for (Index = 0; Index < XPAR_XUSBPS_NUM_INSTANCES; Index++) {
- if (XUsbPs_ConfigTable[Index].DeviceID == DeviceID) {
- CfgPtr = &XUsbPs_ConfigTable[Index];
- break;
- }
- }
-
- return CfgPtr;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4a/11e940555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4a/11e940555243001d18b399c1eb9b3628
deleted file mode 100644
index ebc4030..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4a/11e940555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,84 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2017 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xil_smc.c
-*
-* This file contains function for initiating SMC call
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.2 pkp 02/16/17 First release
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xil_types.h"
-#include "xil_smc.h"
-
-#if EL1_NONSECURE
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Function Prototypes *****************************/
-
-/************************** Variable Definitions *****************************/
-XSmc_OutVar SmcResult;
-
-/*****************************************************************************/
-/**
-* @brief Initiate SMC call to EL3 secure monitor to request for secure
-* service. This function is only applicable for EL1 Non-secure bsp.
-*
-* @param FunctionID is the SMC identifier for a particular secure service
-* request
-* @param Arg1 to Arg6 is the arguments passed to EL3 secure monitor
-* @param Arg7 is Hypervisor Client ID register
-*
-* @return Result from secure payload service
-* @note FunctionID and Arg1-Arg7 should be as per SMC calling convention
-*
-******************************************************************************/
-XSmc_OutVar Xil_Smc(u64 FunctionID, u64 Arg1, u64 Arg2, u64 Arg3, u64 Arg4,
- u64 Arg5, u64 Arg6, u64 Arg7){
-
- /*
- * Since registers x8 to x17 are not saved by secure monitor during SMC
- * it must be preserved.
- */
- XSave_X8toX17();
-
- /* Moving to EL3 secure monitor with smc call. */
-
- __asm__ __volatile__ ("smc #0x0");
-
- /*
- * The result of the secure services are stored in x0 - x3. They are
- * moved to SmcResult to return the result.
- */
- __asm__ __volatile__("mov x8, x0");
- __asm__ __volatile__("mov x9, x1");
- __asm__ __volatile__("mov x10, x2");
- __asm__ __volatile__("mov x11, x3");
-
- __asm__ __volatile__("mov %0, x8" : "=r" (SmcResult.Arg0));
- __asm__ __volatile__("mov %0, x9" : "=r" (SmcResult.Arg1));
- __asm__ __volatile__("mov %0, x10" : "=r" (SmcResult.Arg2));
- __asm__ __volatile__("mov %0, x11" : "=r" (SmcResult.Arg3));
-
- XRestore_X8toX17();
-
- return SmcResult;
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4a/20e797595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4a/20e797595243001d18b399c1eb9b3628
deleted file mode 100644
index 25fc262..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4a/20e797595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,132 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xil-crt0.S
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 10/20/09 Initial version
-* 3.05a sdm 02/02/12 Added code for profiling
-* 3.06a sgd 05/16/12 Added global constructors and cleanup code
-* Uart initialization based on compiler flag
-* 3.07a sgd 07/05/12 Updated with reset and start Global Timer
-* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
-* 4.2 pkp 08/04/14 Removed PEEP board related code which contained
-* initialization of uart smc nor and sram
-* 5.3 pkp 10/07/15 Added support for OpenAMP by not initializing global
-* timer when USE_AMP flag is defined
-* 6.6 srm 10/18/17 Added timer configuration using XTime_StartTTCTimer API.
-* Now the TTC instance as specified by the user will be
-* started.
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#include "bspconfig.h"
-
- .file "xil-crt0.S"
- .section ".got2","aw"
- .align 2
-
- .text
-.Lsbss_start:
- .long __sbss_start
-
-.Lsbss_end:
- .long __sbss_end
-
-.Lbss_start:
- .long __bss_start
-
-.Lbss_end:
- .long __bss_end
-
-.Lstack:
- .long __stack
-
-
- .globl _start
-_start:
- bl __cpu_init /* Initialize the CPU first (BSP provides this) */
-
- mov r0, #0
-
- /* clear sbss */
- ldr r1,.Lsbss_start /* calculate beginning of the SBSS */
- ldr r2,.Lsbss_end /* calculate end of the SBSS */
-
-.Lloop_sbss:
- cmp r1,r2
- bge .Lenclsbss /* If no SBSS, no clearing required */
- str r0, [r1], #4
- b .Lloop_sbss
-
-.Lenclsbss:
- /* clear bss */
- ldr r1,.Lbss_start /* calculate beginning of the BSS */
- ldr r2,.Lbss_end /* calculate end of the BSS */
-
-.Lloop_bss:
- cmp r1,r2
- bge .Lenclbss /* If no BSS, no clearing required */
- str r0, [r1], #4
- b .Lloop_bss
-
-.Lenclbss:
-
- /* set stack pointer */
- ldr r13,.Lstack /* stack address */
-
- /* Reset and start Global Timer */
- mov r0, #0x0
- mov r1, #0x0
-
- /* Reset and start Triple Timer Counter */
- #if defined SLEEP_TIMER_BASEADDR
- bl XTime_StartTTCTimer
- #endif
-
-#if USE_AMP != 1
- bl XTime_SetTime
-#endif
-
-#ifdef PROFILING /* defined in Makefile */
- /* Setup profiling stuff */
- bl _profile_init
-#endif /* PROFILING */
-
- /* run global constructors */
- bl __libc_init_array
-
- /* make sure argc and argv are valid */
- mov r0, #0
- mov r1, #0
-
- /* Let her rip */
- bl main
-
- /* Cleanup global constructors */
- bl __libc_fini_array
-
-#ifdef PROFILING
- /* Cleanup profiling stuff */
- bl _profile_clean
-#endif /* PROFILING */
-
- /* All done */
- bl exit
-
-.Lexit: /* should never get here */
- b .Lexit
-
-.Lstart:
- .size _start,.Lstart-_start
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4a/229490595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4a/229490595243001d18b399c1eb9b3628
deleted file mode 100644
index 08af00b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4a/229490595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,93 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/*****************************************************************************/
-/**
-* @file sleep.h
-*
-* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep
-* related APIs.
-*
-*
-* MODIFICATION HISTORY :
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 6.6 srm 11/02/17 Added processor specific sleep routines
-* function prototypes.
-*
-*
-*
-******************************************************************************/
-
-#ifndef SLEEP_H
-#define SLEEP_H
-
-#include "xil_types.h"
-#include "xil_io.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*****************************************************************************/
-/**
-*
-* This macro polls an address periodically until a condition is met or till the
-* timeout occurs.
-* The minimum timeout for calling this macro is 100us. If the timeout is less
-* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
-* If the timeout is not a multiple of 100us, it waits for a timeout of
-* the next usec value which is a multiple of 100us.
-*
-* @param IO_func - accessor function to read the register contents.
-* Depends on the register width.
-* @param ADDR - Address to be polled
-* @param VALUE - variable to read the value
-* @param COND - Condition to checked (usually involves VALUE)
-* @param TIMEOUT_US - timeout in micro seconds
-*
-* @return 0 - when the condition is met
-* -1 - when the condition is not met till the timeout period
-*
-* @note none
-*
-*****************************************************************************/
-#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
- ( { \
- u64 timeout = TIMEOUT_US/100; \
- if(TIMEOUT_US%100!=0) \
- timeout++; \
- for(;;) { \
- VALUE = IO_func(ADDR); \
- if(COND) \
- break; \
- else { \
- usleep(100); \
- timeout--; \
- if(timeout==0) \
- break; \
- } \
- } \
- (timeout>0) ? 0 : -1; \
- } )
-
-void usleep(unsigned long useconds);
-void sleep(unsigned int seconds);
-int usleep_R5(unsigned long useconds);
-unsigned sleep_R5(unsigned int seconds);
-int usleep_MB(unsigned long useconds);
-unsigned sleep_MB(unsigned int seconds);
-int usleep_A53(unsigned long useconds);
-unsigned sleep_A53(unsigned int seconds);
-int usleep_A9(unsigned long useconds);
-unsigned sleep_A9(unsigned int seconds);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4a/50a1cb595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4a/50a1cb595243001d18b399c1eb9b3628
deleted file mode 100644
index faaa034..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4a/50a1cb595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,425 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xuartps_intr.c
-* @addtogroup uartps_v3_11
-* @{
-*
-* This file contains the functions for interrupt handling
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00 drg/jz 01/13/10 First Release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
-* 3.7 aru 08/17/18 Resolved MISRA-C mandatory violations.(CR#1007755)
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xuartps.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Function Prototypes *****************************/
-
-static void ReceiveDataHandler(XUartPs *InstancePtr);
-static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus);
-static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus);
-static void ReceiveTimeoutHandler(XUartPs *InstancePtr);
-static void ModemHandler(XUartPs *InstancePtr);
-
-
-/* Internal function prototypes implemented in xuartps.c */
-extern u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
-extern u32 XUartPs_SendBuffer(XUartPs *InstancePtr);
-
-/************************** Variable Definitions ****************************/
-
-typedef void (*Handler)(XUartPs *InstancePtr);
-
-/****************************************************************************/
-/**
-*
-* This function gets the interrupt mask
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-* The current interrupt mask. The mask indicates which interrupts
-* are enabled.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr)
-{
- /* Assert validates the input argument */
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /* Read the Interrupt Mask register */
- return (XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IMR_OFFSET));
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the interrupt mask.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-* @param Mask contains the interrupts to be enabled or disabled.
-* A '1' enables an interrupt, and a '0' disables.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask)
-{
- u32 TempMask = Mask;
- /* Assert validates the input arguments */
- Xil_AssertVoid(InstancePtr != NULL);
-
- TempMask &= (u32)XUARTPS_IXR_MASK;
-
- /* Write the mask to the IER Register */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IER_OFFSET, TempMask);
-
- /* Write the inverse of the Mask to the IDR register */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IDR_OFFSET, (~TempMask));
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the handler that will be called when an event (interrupt)
-* occurs that needs application's attention.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-* @param FuncPtr is the pointer to the callback function.
-* @param CallBackRef is the upper layer callback reference passed back
-* when the callback function is invoked.
-*
-* @return None.
-*
-* @note
-*
-* There is no assert on the CallBackRef since the driver doesn't know what it
-* is (nor should it)
-*
-*****************************************************************************/
-void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
- void *CallBackRef)
-{
- /*
- * Asserts validate the input arguments
- * CallBackRef not checked, no way to know what is valid
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(FuncPtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- InstancePtr->Handler = (XUartPs_Handler)FuncPtr;
- InstancePtr->CallBackRef = CallBackRef;
-}
-
-/****************************************************************************/
-/**
-*
-* This function is the interrupt handler for the driver.
-* It must be connected to an interrupt system by the application such that it
-* can be called when an interrupt occurs.
-*
-* @param InstancePtr contains a pointer to the driver instance
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XUartPs_InterruptHandler(XUartPs *InstancePtr)
-{
- u32 IsrStatus;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the interrupt ID register to determine which
- * interrupt is active
- */
- IsrStatus = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IMR_OFFSET);
-
- IsrStatus &= XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_ISR_OFFSET);
-
- /* Dispatch an appropriate handler. */
- if((IsrStatus & ((u32)XUARTPS_IXR_RXOVR | (u32)XUARTPS_IXR_RXEMPTY |
- (u32)XUARTPS_IXR_RXFULL)) != (u32)0) {
- /* Received data interrupt */
- ReceiveDataHandler(InstancePtr);
- }
-
- if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL))
- != (u32)0) {
- /* Transmit data interrupt */
- SendDataHandler(InstancePtr, IsrStatus);
- }
-
- /* XUARTPS_IXR_RBRK is applicable only for Zynq Ultrascale+ MP */
- if ((IsrStatus & ((u32)XUARTPS_IXR_OVER | (u32)XUARTPS_IXR_FRAMING |
- (u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK)) != (u32)0) {
- /* Received Error Status interrupt */
- ReceiveErrorHandler(InstancePtr, IsrStatus);
- }
-
- if((IsrStatus & ((u32)XUARTPS_IXR_TOUT)) != (u32)0) {
- /* Received Timeout interrupt */
- ReceiveTimeoutHandler(InstancePtr);
- }
-
- if((IsrStatus & ((u32)XUARTPS_IXR_DMS)) != (u32)0) {
- /* Modem status interrupt */
- ModemHandler(InstancePtr);
- }
-
- /* Clear the interrupt status. */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_ISR_OFFSET,
- IsrStatus);
-
-}
-
-/****************************************************************************/
-/*
-*
-* This function handles interrupts for receive errors which include
-* overrun errors, framing errors, parity errors, and the break interrupt.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus)
-{
- u32 EventData;
- u32 Event;
-
- InstancePtr->is_rxbs_error = 0;
-
- if ((InstancePtr->Platform == XPLAT_ZYNQ_ULTRA_MP) &&
- (IsrStatus & ((u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK
- | (u32)XUARTPS_IXR_FRAMING))) {
- InstancePtr->is_rxbs_error = 1;
- }
- /*
- * If there are bytes still to be received in the specified buffer
- * go ahead and receive them. Removing bytes from the RX FIFO will
- * clear the interrupt.
- */
-
- (void)XUartPs_ReceiveBuffer(InstancePtr);
-
- if (!(InstancePtr->is_rxbs_error)) {
- Event = XUARTPS_EVENT_RECV_ERROR;
- EventData = InstancePtr->ReceiveBuffer.RequestedBytes -
- InstancePtr->ReceiveBuffer.RemainingBytes;
-
- /*
- * Call the application handler to indicate that there is a receive
- * error or a break interrupt, if the application cares about the
- * error it call a function to get the last errors.
- */
- InstancePtr->Handler(InstancePtr->CallBackRef,
- Event,
- EventData);
- }
-}
-
-/****************************************************************************/
-/**
-*
-* This function handles the receive timeout interrupt. This interrupt occurs
-* whenever a number of bytes have been present in the RX FIFO and the receive
-* data line has been idle for at lease 4 or more character times, (the timeout
-* is set using XUartPs_SetrecvTimeout() function).
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-static void ReceiveTimeoutHandler(XUartPs *InstancePtr)
-{
- u32 Event;
-
- /*
- * If there are bytes still to be received in the specified buffer
- * go ahead and receive them. Removing bytes from the RX FIFO will
- * clear the interrupt.
- */
- if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
- (void)XUartPs_ReceiveBuffer(InstancePtr);
- }
-
- /*
- * If there are no more bytes to receive then indicate that this is
- * not a receive timeout but the end of the buffer reached, a timeout
- * normally occurs if # of bytes is not divisible by FIFO threshold,
- * don't rely on previous test of remaining bytes since receive
- * function updates it
- */
- if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
- Event = XUARTPS_EVENT_RECV_TOUT;
- } else {
- Event = XUARTPS_EVENT_RECV_DATA;
- }
-
- /*
- * Call the application handler to indicate that there is a receive
- * timeout or data event
- */
- InstancePtr->Handler(InstancePtr->CallBackRef, Event,
- InstancePtr->ReceiveBuffer.RequestedBytes -
- InstancePtr->ReceiveBuffer.RemainingBytes);
-
-}
-/****************************************************************************/
-/**
-*
-* This function handles the interrupt when data is in RX FIFO.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-static void ReceiveDataHandler(XUartPs *InstancePtr)
-{
- /*
- * If there are bytes still to be received in the specified buffer
- * go ahead and receive them. Removing bytes from the RX FIFO will
- * clear the interrupt.
- */
- if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
- (void)XUartPs_ReceiveBuffer(InstancePtr);
- }
-
- /* If the last byte of a message was received then call the application
- * handler, this code should not use an else from the previous check of
- * the number of bytes to receive because the call to receive the buffer
- * updates the bytes ramained
- */
- if (InstancePtr->ReceiveBuffer.RemainingBytes == (u32)0) {
- InstancePtr->Handler(InstancePtr->CallBackRef,
- XUARTPS_EVENT_RECV_DATA,
- (InstancePtr->ReceiveBuffer.RequestedBytes -
- InstancePtr->ReceiveBuffer.RemainingBytes));
- }
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function handles the interrupt when data has been sent, the transmit
-* FIFO is empty (transmitter holding register).
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-* @param IsrStatus is the register value for channel status register
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus)
-{
-
- /*
- * If there are not bytes to be sent from the specified buffer then disable
- * the transmit interrupt so it will stop interrupting as it interrupts
- * any time the FIFO is empty
- */
- if (InstancePtr->SendBuffer.RemainingBytes == (u32)0) {
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IDR_OFFSET,
- ((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL));
-
- /* Call the application handler to indicate the sending is done */
- InstancePtr->Handler(InstancePtr->CallBackRef,
- XUARTPS_EVENT_SENT_DATA,
- InstancePtr->SendBuffer.RequestedBytes -
- InstancePtr->SendBuffer.RemainingBytes);
- }
-
- /* If TX FIFO is empty, send more. */
- else if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY)) != (u32)0) {
- (void)XUartPs_SendBuffer(InstancePtr);
- }
- else {
- /* Else with dummy entry for MISRA-C Compliance.*/
- ;
- }
-}
-
-/****************************************************************************/
-/**
-*
-* This function handles modem interrupts. It does not do any processing
-* except to call the application handler to indicate a modem event.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-static void ModemHandler(XUartPs *InstancePtr)
-{
- u32 MsrRegister;
-
- /*
- * Read the modem status register so that the interrupt is acknowledged
- * and it can be passed to the callback handler with the event
- */
- MsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_MODEMSR_OFFSET);
-
- /*
- * Call the application handler to indicate the modem status changed,
- * passing the modem status and the event data in the call
- */
- InstancePtr->Handler(InstancePtr->CallBackRef,
- XUARTPS_EVENT_MODEM,
- MsrRegister);
-
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4a/909ce3565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4a/909ce3565243001d18b399c1eb9b3628
deleted file mode 100644
index 85a1af4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4a/909ce3565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,202 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2012 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_mmu.c
-*
-* This file provides APIs for enabling/disabling MMU and setting the memory
-* attributes for sections, in the MMU translation table.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 01/12/12 Initial version
-* 3.05a asa 03/10/12 Modified the Xil_EnableMMU to invalidate the caches
-* before enabling back.
-* 3.05a asa 04/15/12 Modified the Xil_SetTlbAttributes routine so that
-* translation table and branch predictor arrays are
-* invalidated, D-cache flushed before the attribute
-* change is applied. This is done so that the user
-* need not call Xil_DisableMMU before calling
-* Xil_SetTlbAttributes.
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-* 3.11a asa 09/23/13 Modified Xil_SetTlbAttributes to flush the complete
-* D cache after the translation table update. Removed the
-* redundant TLB invalidation in the same API at the beginning.
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-* It fixes CR#1008309.
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-#include "xil_mmu.h"
-#include "xil_errata.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-#define ARM_AR_MEM_TTB_SECT_SIZE 1024*1024
-#define ARM_AR_MEM_TTB_SECT_SIZE_MASK (~(ARM_AR_MEM_TTB_SECT_SIZE-1UL))
-/************************** Variable Definitions *****************************/
-
-extern u32 MMUTable;
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-* @brief This function sets the memory attributes for a section covering 1MB
-* of memory in the translation table.
-*
-* @param Addr: 32-bit address for which memory attributes need to be set.
-* @param attrib: Attribute for the given memory region. xil_mmu.h contains
-* definitions of commonly used memory attributes which can be
-* utilized for this function.
-*
-*
-* @return None.
-*
-* @note The MMU or D-cache does not need to be disabled before changing a
-* translation table entry.
-*
-******************************************************************************/
-void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib)
-{
- u32 *ptr;
- u32 section;
-
- section = Addr / 0x100000U;
- ptr = &MMUTable;
- ptr += section;
- if(ptr != NULL) {
- *ptr = (Addr & 0xFFF00000U) | attrib;
- }
-
- Xil_DCacheFlush();
-
- mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
- /* Invalidate all branch predictors */
- mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
-
- dsb(); /* ensure completion of the BP and TLB invalidation */
- isb(); /* synchronize context on this processor */
-}
-
-/*****************************************************************************/
-/**
-* @brief Enable MMU for cortex A9 processor. This function invalidates the
-* instruction and data caches, and then enables MMU.
-*
-* @return None.
-*
-******************************************************************************/
-void Xil_EnableMMU(void)
-{
- u32 Reg;
- Xil_DCacheInvalidate();
- Xil_ICacheInvalidate();
-
-#ifdef __GNUC__
- Reg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, Reg);
-#else
- { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
- Reg = Cp15Reg; }
-#endif
- Reg |= (u32)0x05U;
- mtcp(XREG_CP15_SYS_CONTROL, Reg);
-
- dsb();
- isb();
-}
-
-/*****************************************************************************/
-/**
-* @brief Disable MMU for Cortex A9 processors. This function invalidates
-* the TLBs, Branch Predictor Array and flushed the D Caches before
-* disabling the MMU.
-*
-* @return None.
-*
-* @note When the MMU is disabled, all the memory accesses are treated as
-* strongly ordered.
-******************************************************************************/
-void Xil_DisableMMU(void)
-{
- u32 Reg;
-
- mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
- mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
- Xil_DCacheFlush();
-
-#ifdef __GNUC__
- Reg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, Reg);
-#else
- { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
- Reg = Cp15Reg; }
-#endif
- Reg &= (u32)(~0x05U);
-#ifdef CONFIG_ARM_ERRATA_794073
- /* Disable Branch Prediction */
- Reg &= (u32)(~0x800U);
-#endif
- mtcp(XREG_CP15_SYS_CONTROL, Reg);
-}
-
-/*****************************************************************************/
-/**
-* @brief Memory mapping for Cortex A9 processor.
-*
-* @param PhysAddr is physical address.
-* @param size is size of region.
-* @param flags is flags used to set translation table.
-*
-* @return Pointer to virtual address.
-*
-* @note: Previously this was implemented in libmetal. Move to embeddedsw as this
-* functionality is specific to A9 processor.
-*
-******************************************************************************/
-void* Xil_MemMap(UINTPTR PhysAddr, size_t size, u32 flags)
-{
- u32 Sectionoffset;
- u32 Ttbaddr;
-
- if (!flags)
- return (void*)PhysAddr;
-
- /* Ensure alignment on a section boundary */
- PhysAddr &= ARM_AR_MEM_TTB_SECT_SIZE_MASK;
-
- /* Loop through entire region of memory (one MMU section at a time).
- Each section requires a TTB entry. */
- for (Sectionoffset = 0; Sectionoffset < size;
- Sectionoffset += ARM_AR_MEM_TTB_SECT_SIZE) {
- /* Calculate translation table entry for this memory section */
- Ttbaddr = (PhysAddr + Sectionoffset);
-
- /* Write translation table entry value to entry address */
- Xil_SetTlbAttributes(Ttbaddr, flags);
- }
- return (void*)PhysAddr;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4a/b1e0b5575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4a/b1e0b5575243001d18b399c1eb9b3628
deleted file mode 100644
index 5feeb49..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4a/b1e0b5575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,39 +0,0 @@
-DRIVER_LIB_VERSION = 1.0
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I$(INCLUDEDIR)
-
-SRCFILES:=$(wildcard *.c)
-
-OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
-
-libs: $(OBJECTS)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf $(DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4a/d1a4c0595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4a/d1a4c0595243001d18b399c1eb9b3628
deleted file mode 100644
index d986349..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4a/d1a4c0595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,240 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm_gcc.h
-*
-* This header file contains macros for using inline assembler code. It is
-* written specifically for the GNU compiler.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/21/14 First release
-* 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors
-* 7.2 asa 04/03/20 Renamed the str macro to strw.
-* 7.2 dp 04/30/20 Added clobber "cc" to mtcpsr for aarch32 processors
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-*
-******************************************************************************/
-
-/**
-*@cond nocomments
-*/
-
-#ifndef XPMCOUNTER_H /* prevent circular inclusions */
-#define XPMCOUNTER_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/************************** Constant Definitions ****************************/
-
-/* Number of performance counters */
-#define XPM_CTRCOUNT 6U
-
-/* The following constants define the Cortex-A9 Performance Monitor Events */
-
-/*
- * Software increment. The register is incremented only on writes to the
- * Software Increment Register
- */
-#define XPM_EVENT_SOFTINCR 0x00U
-
-/*
- * Instruction fetch that causes a refill at (at least) the lowest level(s) of
- * instruction or unified cache. Includes the speculative linefills in the
- * count
- */
-#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
-
-/*
- * Instruction fetch that causes a TLB refill at (at least) the lowest level of
- * TLB. Includes the speculative requests in the count
- */
-#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
-
-/*
- * Data read or write operation that causes a refill at (at least) the lowest
- * level(s)of data or unified cache. Counts the number of allocations performed
- * in the Data Cache due to a read or a write
- */
-#define XPM_EVENT_DATA_CACHEREFILL 0x03U
-
-/*
- * Data read or write operation that causes a cache access at (at least) the
- * lowest level(s) of data or unified cache. This includes speculative reads
- */
-#define XPM_EVENT_DATA_CACHEACCESS 0x04U
-
-/*
- * Data read or write operation that causes a TLB refill at (at least) the
- * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
- * CP15 Cache operation by MVA and CP15 VA to PA operations
- */
-#define XPM_EVENT_DATA_TLBREFILL 0x05U
-
-/*
- * Data read architecturally executed. Counts the number of data read
- * instructions accepted by the Load Store Unit. This includes counting the
- * speculative and aborted LDR/LDM, as well as the reads due to the SWP
- * instructions
- */
-#define XPM_EVENT_DATA_READS 0x06U
-
-/*
- * Data write architecturally executed. Counts the number of data write
- * instructions accepted by the Load Store Unit. This includes counting the
- * speculative and aborted STR/STM, as well as the writes due to the SWP
- * instructions
- */
-#define XPM_EVENT_DATA_WRITE 0x07U
-
-/* Exception taken. Counts the number of exceptions architecturally taken.*/
-#define XPM_EVENT_EXCEPTION 0x09U
-
-/* Exception return architecturally executed.*/
-#define XPM_EVENT_EXCEPRETURN 0x0AU
-
-/*
- * Change to ContextID retired. Counts the number of instructions
- * architecturally executed writing into the ContextID Register
- */
-#define XPM_EVENT_CHANGECONTEXT 0x0BU
-
-/*
- * Software change of PC, except by an exception, architecturally executed.
- * Count the number of PC changes architecturally executed, excluding the PC
- * changes due to taken exceptions
- */
-#define XPM_EVENT_SW_CHANGEPC 0x0CU
-
-/*
- * Immediate branch architecturally executed (taken or not taken). This includes
- * the branches which are flushed due to a previous load/store which aborts
- * late
- */
-#define XPM_EVENT_IMMEDBRANCH 0x0DU
-
-/*
- * Unaligned access architecturally executed. Counts the number of aborted
- * unaligned accessed architecturally executed, and the number of not-aborted
- * unaligned accesses, including the speculative ones
- */
-#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
-
-/*
- * Branch mispredicted/not predicted. Counts the number of mispredicted or
- * not-predicted branches executed. This includes the branches which are flushed
- * due to a previous load/store which aborts late
- */
-#define XPM_EVENT_BRANCHMISS 0x10U
-
-/*
- * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
- * event is not exported on the PMUEVENT bus
- */
-#define XPM_EVENT_CLOCKCYCLES 0x11U
-
-/*
- * Branches or other change in program flow that could have been predicted by
- * the branch prediction resources of the processor. This includes the branches
- * which are flushed due to a previous load/store which aborts late
- */
-#define XPM_EVENT_BRANCHPREDICT 0x12U
-
-/*
- * Java bytecode execute. Counts the number of Java bytecodes being decoded,
- * including speculative ones
- */
-#define XPM_EVENT_JAVABYTECODE 0x40U
-
-/*
- * Software Java bytecode executed. Counts the number of software java bytecodes
- * being decoded, including speculative ones
- */
-#define XPM_EVENT_SWJAVABYTECODE 0x41U
-
-/*
- * Jazelle backward branches executed. Counts the number of Jazelle taken
- * branches being executed. This includes the branches which are flushed due
- * to a previous load/store which aborts late
- */
-#define XPM_EVENT_JAVABACKBRANCH 0x42U
-
-/*
- * Coherent linefill miss Counts the number of coherent linefill requests
- * performed by the Cortex-A9 processor which also miss in all the other
- * Cortex-A9 processors, meaning that the request is sent to the external
- * memory
- */
-#define XPM_EVENT_COHERLINEMISS 0x50U
-
-/*
- * Coherent linefill hit. Counts the number of coherent linefill requests
- * performed by the Cortex-A9 processor which hit in another Cortex-A9
- * processor, meaning that the linefill data is fetched directly from the
- * relevant Cortex-A9 cache
- */
-#define XPM_EVENT_COHERLINEHIT 0x51U
-
-/*
- * Instruction cache dependent stall cycles. Counts the number of cycles where
- * the processor is ready to accept new instructions, but does not receive any
- * due to the instruction side not being able to provide any and the
- * instruction cache is currently performing at least one linefill
- */
-#define XPM_EVENT_INSTRSTALL 0x60U
-
-/*
- * Data cache dependent stall cycles. Counts the number of cycles where the core
- * has some instructions that it cannot issue to any pipeline, and the Load
- * Store unit has at least one pending linefill request, and no pending
- */
-#define XPM_EVENT_DATASTALL 0x61U
-
-/*
- * Main TLB miss stall cycles. Counts the number of cycles where the processor
- * is stalled waiting for the completion of translation table walks from the
- * main TLB. The processor stalls can be due to the instruction side not being
- * able to provide the instructions, or to the data side not being able to
- * provide the necessary data, due to them waiting for the main TLB translation
- * table walk to complete
- */
-#define XPM_EVENT_MAINTLBSTALL 0x62U
-
-/*
- * Counts the number of STREX instructions architecturally executed and
- * passed
- */
-#define XPM_EVENT_STREXPASS 0x63U
-
-/*
- * Counts the number of STREX instructions architecturally executed and
- * failed
- */
-#define XPM_EVENT_STREXFAIL 0x64U
-
-/*
- * Data eviction. Counts the number of eviction requests due to a linefill in
- * the data cache
- */
-#define XPM_EVENT_DATAEVICT 0x65U
-
-/*
- * Counts the number of cycles where the issue stage does not dispatch any
- * instruction because it is empty or cannot dispatch any instructions
- */
-#define XPM_EVENT_NODISPATCH 0x66U
-
-/*
- * Counts the number of cycles where the issue stage is empty
- */
-#define XPM_EVENT_ISSUEEMPTY 0x67U
-
-/*
- * Counts the number of instructions going through the Register Renaming stage.
- * This number is an approximate number of the total number of instructions
- * speculatively executed, and even more approximate of the total number of
- * instructions architecturally executed. The approximation depends mainly on
- * the branch misprediction rate.
- * The renaming stage can handle two instructions in the same cycle so the event
- * is two bits long:
- * - b00 no instructions renamed
- * - b01 one instruction renamed
- * - b10 two instructions renamed
- */
-#define XPM_EVENT_INSTRRENAME 0x68U
-
-/*
- * Counts the number of procedure returns whose condition codes do not fail,
- * excluding all returns from exception. This count includes procedure returns
- * which are flushed due to a previous load/store which aborts late.
- * Only the following instructions are reported:
- * - BX R14
- * - MOV PC LR
- * - POP {..,pc}
- * - LDR pc,[sp],#offset
- * The following instructions are not reported:
- * - LDMIA R9!,{..,PC} (ThumbEE state only)
- * - LDR PC,[R9],#offset (ThumbEE state only)
- * - BX R0 (Rm != R14)
- * - MOV PC,R0 (Rm != R14)
- * - LDM SP,{...,PC} (writeback not specified)
- * - LDR PC,[SP,#offset] (wrong addressing mode)
- */
-#define XPM_EVENT_PREDICTFUNCRET 0x6EU
-
-/*
- * Counts the number of instructions being executed in the main execution
- * pipeline of the processor, the multiply pipeline and arithmetic logic unit
- * pipeline. The counted instructions are still speculative
- */
-#define XPM_EVENT_MAINEXEC 0x70U
-
-/*
- * Counts the number of instructions being executed in the processor second
- * execution pipeline (ALU). The counted instructions are still speculative
- */
-#define XPM_EVENT_SECEXEC 0x71U
-
-/*
- * Counts the number of instructions being executed in the Load/Store unit. The
- * counted instructions are still speculative
- */
-#define XPM_EVENT_LDRSTR 0x72U
-
-/*
- * Counts the number of Floating-point instructions going through the Register
- * Rename stage. Instructions are still speculative in this stage.
- *Two floating-point instructions can be renamed in the same cycle so the event
- * is two bitslong:
- *0b00 no floating-point instruction renamed
- *0b01 one floating-point instruction renamed
- *0b10 two floating-point instructions renamed
- */
-#define XPM_EVENT_FLOATRENAME 0x73U
-
-/*
- * Counts the number of Neon instructions going through the Register Rename
- * stage.Instructions are still speculative in this stage.
- * Two NEON instructions can be renamed in the same cycle so the event is two
- * bits long:
- *0b00 no NEON instruction renamed
- *0b01 one NEON instruction renamed
- *0b10 two NEON instructions renamed
- */
-#define XPM_EVENT_NEONRENAME 0x74U
-
-/*
- * Counts the number of cycles where the processor is stalled because PLD slots
- * are all full
- */
-#define XPM_EVENT_PLDSTALL 0x80U
-
-/*
- * Counts the number of cycles when the processor is stalled and the data side
- * is stalled too because it is full and executing writes to the external
- * memory
- */
-#define XPM_EVENT_WRITESTALL 0x81U
-
-/*
- * Counts the number of stall cycles due to main TLB misses on requests issued
- * by the instruction side
- */
-#define XPM_EVENT_INSTRTLBSTALL 0x82U
-
-/*
- * Counts the number of stall cycles due to main TLB misses on requests issued
- * by the data side
- */
-#define XPM_EVENT_DATATLBSTALL 0x83U
-
-/*
- * Counts the number of stall cycles due to micro TLB misses on the instruction
- * side. This event does not include main TLB miss stall cycles that are already
- * counted in the corresponding main TLB event
- */
-#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
-
-/*
- * Counts the number of stall cycles due to micro TLB misses on the data side.
- * This event does not include main TLB miss stall cycles that are already
- * counted in the corresponding main TLB event
- */
-#define XPM_EVENT_DATA_uTLBSTALL 0x85U
-
-/*
- * Counts the number of stall cycles because of the execution of a DMB memory
- * barrier. This includes all DMB instructions being executed, even
- * speculatively
- */
-#define XPM_EVENT_DMB_STALL 0x86U
-
-/*
- * Counts the number of cycles during which the integer core clock is enabled
- */
-#define XPM_EVENT_INT_CLKEN 0x8AU
-
-/*
- * Counts the number of cycles during which the Data Engine clock is enabled
- */
-#define XPM_EVENT_DE_CLKEN 0x8BU
-
-/*
- * Counts the number of ISB instructions architecturally executed
- */
-#define XPM_EVENT_INSTRISB 0x90U
-
-/*
- * Counts the number of DSB instructions architecturally executed
- */
-#define XPM_EVENT_INSTRDSB 0x91U
-
-/*
- * Counts the number of DMB instructions speculatively executed
- */
-#define XPM_EVENT_INSTRDMB 0x92U
-
-/*
- * Counts the number of external interrupts executed by the processor
- */
-#define XPM_EVENT_EXTINT 0x93U
-
-/*
- * PLE cache line request completed
- */
-#define XPM_EVENT_PLE_LRC 0xA0U
-
-/*
- * PLE cache line request skipped
- */
-#define XPM_EVENT_PLE_LRS 0xA1U
-
-/*
- * PLE FIFO flush
- */
-#define XPM_EVENT_PLE_FLUSH 0xA2U
-
-/*
- * PLE request complete
- */
-#define XPM_EVENT_PLE_CMPL 0xA3U
-
-/*
- * PLE FIFO overflow
- */
-#define XPM_EVENT_PLE_OVFL 0xA4U
-
-/*
- * PLE request programmed
- */
-#define XPM_EVENT_PLE_PROG 0xA5U
-
-/*
- * The following constants define the configurations for Cortex-A9 Performance
- * Monitor Events. Each configuration configures the event counters for a set
- * of events.
- * -----------------------------------------------
- * Config PmCtr0... PmCtr5
- * -----------------------------------------------
- * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR,
- * XPM_EVENT_INSRFETCH_CACHEREFILL,
- * XPM_EVENT_INSTRFECT_TLBREFILL,
- * XPM_EVENT_DATA_CACHEREFILL,
- * XPM_EVENT_DATA_CACHEACCESS,
- * XPM_EVENT_DATA_TLBREFILL }
- *
- * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS,
- * XPM_EVENT_DATA_WRITE,
- * XPM_EVENT_EXCEPTION,
- * XPM_EVENT_EXCEPRETURN,
- * XPM_EVENT_CHANGECONTEXT,
- * XPM_EVENT_SW_CHANGEPC }
- *
- * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH,
- * XPM_EVENT_UNALIGNEDACCESS,
- * XPM_EVENT_BRANCHMISS,
- * XPM_EVENT_CLOCKCYCLES,
- * XPM_EVENT_BRANCHPREDICT,
- * XPM_EVENT_JAVABYTECODE }
- *
- * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE,
- * XPM_EVENT_JAVABACKBRANCH,
- * XPM_EVENT_COHERLINEMISS,
- * XPM_EVENT_COHERLINEHIT,
- * XPM_EVENT_INSTRSTALL,
- * XPM_EVENT_DATASTALL }
- *
- * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL,
- * XPM_EVENT_STREXPASS,
- * XPM_EVENT_STREXFAIL,
- * XPM_EVENT_DATAEVICT,
- * XPM_EVENT_NODISPATCH,
- * XPM_EVENT_ISSUEEMPTY }
- *
- * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME,
- * XPM_EVENT_PREDICTFUNCRET,
- * XPM_EVENT_MAINEXEC,
- * XPM_EVENT_SECEXEC,
- * XPM_EVENT_LDRSTR,
- * XPM_EVENT_FLOATRENAME }
- *
- * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME,
- * XPM_EVENT_PLDSTALL,
- * XPM_EVENT_WRITESTALL,
- * XPM_EVENT_INSTRTLBSTALL,
- * XPM_EVENT_DATATLBSTALL,
- * XPM_EVENT_INSTR_uTLBSTALL }
- *
- * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL,
- * XPM_EVENT_DMB_STALL,
- * XPM_EVENT_INT_CLKEN,
- * XPM_EVENT_DE_CLKEN,
- * XPM_EVENT_INSTRISB,
- * XPM_EVENT_INSTRDSB }
- *
- * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB,
- * XPM_EVENT_EXTINT,
- * XPM_EVENT_PLE_LRC,
- * XPM_EVENT_PLE_LRS,
- * XPM_EVENT_PLE_FLUSH,
- * XPM_EVENT_PLE_CMPL }
- *
- * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL,
- * XPM_EVENT_PLE_PROG,
- * XPM_EVENT_PLE_LRC,
- * XPM_EVENT_PLE_LRS,
- * XPM_EVENT_PLE_FLUSH,
- * XPM_EVENT_PLE_CMPL }
- *
- * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL,
- * XPM_EVENT_INSRFETCH_CACHEREFILL,
- * XPM_EVENT_INSTRFECT_TLBREFILL,
- * XPM_EVENT_DATA_CACHEREFILL,
- * XPM_EVENT_DATA_CACHEACCESS,
- * XPM_EVENT_DATA_TLBREFILL }
- */
-#define XPM_CNTRCFG1 0
-#define XPM_CNTRCFG2 1
-#define XPM_CNTRCFG3 2
-#define XPM_CNTRCFG4 3
-#define XPM_CNTRCFG5 4
-#define XPM_CNTRCFG6 5
-#define XPM_CNTRCFG7 6
-#define XPM_CNTRCFG8 7
-#define XPM_CNTRCFG9 8
-#define XPM_CNTRCFG10 9
-#define XPM_CNTRCFG11 10
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/**
-*@endcond
-*/
-
-/************************** Function Prototypes *****************************/
-
-/* Interface functions to access performance counters from abstraction layer */
-void Xpm_SetEvents(s32 PmcrCfg);
-void Xpm_GetEventCounters(u32 *PmCtrValue);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-* @} End of "addtogroup a9_event_counter_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4c/f0c953545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4c/f0c953545243001d18b399c1eb9b3628
deleted file mode 100644
index 6d07851..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4c/f0c953545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,60 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm.h
-*
-* @addtogroup a9_specific Cortex A9 Processor Specific Include Files
-*
-* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h.
-*
-* The xreg_cortexa9.h file contains definitions for inline assembler code.
-* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers,
-* co-processor registers and Debug registers.
-*
-* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
-* assembler instructions, available as macros. These can be very useful for
-* tasks such as setting or getting special purpose registers, synchronization,
-* or cache manipulation etc. These inline assembler instructions can be used
-* from drivers and user applications written in C.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 10/18/09 First release
-* 3.04a sdm 01/02/12 Remove redundant dsb in mcr instruction.
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-*
-******************************************************************************/
-#ifndef XPSEUDO_ASM_H
-#define XPSEUDO_ASM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xreg_cortexa9.h"
-#ifdef __GNUC__
- #include "xpseudo_asm_gcc.h"
-#elif defined (__ICCARM__)
- #include "xpseudo_asm_iccarm.h"
-#else
- #include "xpseudo_asm_rvct.h"
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XPSEUDO_ASM_H */
-/**
-* @} End of "addtogroup a9_specific".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4d/017350585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4d/017350585243001d18b399c1eb9b3628
deleted file mode 100644
index e811686..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4d/017350585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,394 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xreg_cortexa53.h
-*
-* This header file contains definitions for using inline assembler code. It is
-* written specifically for the GNU.
-*
-* All of the ARM Cortex A53 GPRs, SPRs, and Debug Registers are defined along
-* with the positions of the bits within the registers.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.2 pkp 28/05/15 First release
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 1.00a ecm/sdm 02/01/10 Initial version
-* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
-* driver tcl
-* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
-* 6.6 srm 10/18/17 Added ARMA9 macro to identify CortexA9
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a hk/sg 10/17/13 Initial release
-* kvn 07/15/15 Modified the code according to MISRAC-2012.
-* 3.7 aru 03/12/19 Modified the code according to MISRAC-2012.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xstatus.h"
-#include "xsdps.h"
-#include "xparameters.h"
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-/**
- * XSdPs Configuration Table
- */
-extern XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES];
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* Looks up the device configuration based on the unique device ID. A table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId contains the ID of the device to look up the
-* configuration for.
-*
-* @return
-*
-* A pointer to the configuration found or NULL if the specified device ID was
-* not found. See xsdps.h for the definition of XSdPs_Config.
-*
-* @note None.
-*
-******************************************************************************/
-XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId)
-{
- XSdPs_Config *CfgPtr = NULL;
- u32 Index;
-
- for (Index = 0U; Index < (u32)XPAR_XSDPS_NUM_INSTANCES; Index++) {
- if (XSdPs_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XSdPs_ConfigTable[Index];
- break;
- }
- }
- return (XSdPs_Config *)CfgPtr;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4d/80cee3575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4d/80cee3575243001d18b399c1eb9b3628
deleted file mode 100644
index e93e4d4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4d/80cee3575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,71 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xemacps_sinit.c
-* @addtogroup emacps_v3_15
-* @{
-*
-* This file contains lookup method by device ID when success, it returns
-* pointer to config table to be used to initialize the device.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 New
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xemacps.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-/*************************** Variable Definitions *****************************/
-extern XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES];
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-* Lookup the device configuration based on the unique device ID. The table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId is the unique device ID of the device being looked up.
-*
-* @return
-* A pointer to the configuration table entry corresponding to the given
-* device ID, or NULL if no match is found.
-*
-******************************************************************************/
-XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
-{
- XEmacPs_Config *CfgPtr = NULL;
- u32 i;
-
- for (i = 0U; i < (u32)XPAR_XEMACPS_NUM_INSTANCES; i++) {
- if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) {
- CfgPtr = &XEmacPs_ConfigTable[i];
- break;
- }
- }
-
- return (XEmacPs_Config *)(CfgPtr);
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4e/519d25595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4e/519d25595243001d18b399c1eb9b3628
deleted file mode 100644
index 1eb4d16..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4e/519d25595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,99 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xtime_l.h
-*
-* @addtogroup r5_time_apis Cortex R5 Time Functions
-* The xtime_l.h provides access to 32-bit TTC timer counter. These functions
-* can be used by applications to track the time.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 5.00 pkp 05/29/14 First release
-* 5.04 pkp 02/19/16 Added timer configuration register offset definitions
-* 5.04 pkp 03/11/16 Removed definitions for overflow interrupt register
-* and mask
-* 6.6 srm 10/22/17 Added a warning message for the user configurable sleep
-* implementation when default timer is selected by the user
-* 7.2 mus 01/29/20 Updated #defines to support PMU cycle counter for sleep
-* routines.
-* 7.5 dp 01/05/21 Updated COUNTS_PER_SECOND/USECOND and ITERS_PER_SEC/USEC
-* macros to round it off to nearest possible value so that
-* delta error in time calculations can be minimized.
-* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
-* displaying same warnings multiple times. It fixes CR#1090562.
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XTIME_H /* prevent circular inclusions */
-#define XTIME_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xparameters.h"
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Constant Definitions *****************************/
-
-#ifdef SLEEP_TIMER_BASEADDR
-
-#define COUNTS_PER_SECOND SLEEP_TIMER_FREQUENCY
-
-#else
-#define ITERS_PER_SEC ((XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ + 2)/ 4)
-#define ITERS_PER_USEC ((XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ + 2000000)/ 4000000)
-
-/*
- * These constants are applicable for the CortexR5 PMU cycle counter.
- * As boot code is setting up "D" bit in PMCR, cycle counter increments
- * on every 64th bit of processor cycle
- */
-
-#define COUNTS_PER_SECOND ((XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ + 32)/ 64)
-#endif
-
-#define COUNTS_PER_USECOND ((COUNTS_PER_SECOND + 500000) / 1000000)
-
-#define IRQ_FIQ_MASK 0xC0 /* Mask IRQ and FIQ interrupts in cpsr */
-
-/*
- * 1st bit of PROCESSOR_ACCESS_VALUE macro signifies trustzone
- * setting for IOU slcr address space
- */
-#define IOU_SLCR_TZ_MASK 0x2U
-/**************************** Type Definitions *******************************/
-
-typedef u32 XTime;
-
-/**
- *@endcond
- */
-
-void XTime_SetTime(XTime Xtime_Global);
-void XTime_GetTime(XTime *Xtime_Global);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XTIME_H */
-/**
-* @} End of "@addtogroup r5_time_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4e/60c696545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4e/60c696545243001d18b399c1eb9b3628
deleted file mode 100644
index dd2d4d3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4e/60c696545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,84 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xdmaps_selftest.c
-* @addtogroup dmaps_v2_8
-* @{
-*
-* This file contains the self-test functions for the XDmaPs driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00 hbm 03/29/2010 First Release
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xdmaps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/****************************************************************************/
-/**
-*
-* This function runs a self-test on the driver and hardware device. This self
-* test performs a local loopback and verifies data can be sent and received.
-*
-* The time for this test is proportional to the baud rate that has been set
-* prior to calling this function.
-*
-* The mode and control registers are restored before return.
-*
-* @param InstPtr is a pointer to the XDmaPs instance
-*
-* @return
-*
-* - XST_SUCCESS if the test was successful
-* - XST_FAILURE if the test failed
-*
-* @note
-*
-* This function can hang if the hardware is not functioning properly.
-*
-******************************************************************************/
-int XDmaPs_SelfTest(XDmaPs *InstPtr)
-{
- u32 BaseAddr = InstPtr->Config.BaseAddress;
- int i;
-
- if (XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
- & XDMAPS_DBGSTATUS_BUSY)
- return XST_FAILURE;
-
- for (i = 0; i < XDMAPS_CHANNELS_PER_DEV; i++) {
- if (XDmaPs_ReadReg(BaseAddr,
- XDmaPs_CSn_OFFSET(i)))
- return XST_FAILURE;
- }
- return XST_SUCCESS;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4e/b078f0575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4e/b078f0575243001d18b399c1eb9b3628
deleted file mode 100644
index fd7f472..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4e/b078f0575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,273 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xgpiops.h
-* @addtogroup gpiops_v3_9
-* @{
-* @details
-*
-* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
-* Controller.
-*
-* The GPIO Controller supports the following features:
-* - 4 banks
-* - Masked writes (There are no masked reads)
-* - Bypass mode
-* - Configurable Interrupts (Level/Edge)
-*
-* This driver is intended to be RTOS and processor independent. Any needs for
-* dynamic memory management, threads or thread mutual exclusion, virtual
-* memory, or cache control must be satisfied by the layer above this driver.
-
-* This driver supports all the features listed above, if applicable.
-*
-* Driver Description
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate to the GPIO.
-*
-* Interrupts
-*
-* The driver provides interrupt management functions and an interrupt handler.
-* Users of this driver need to provide callback functions. An interrupt handler
-* example is available with the driver.
-*
-* Threads
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* Asserts
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* Building the driver
-*
-* The XGpioPs driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sv 01/15/10 First Release
-* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
-* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
-* relevant to Zynq device.The interrupts are disabled
-* for output pins on all banks during initialization.
-* 1.02a hk 08/22/13 Added low level reset API
-* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
-* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
-* passed to APIs. CR# 822636
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/05/17 Added tabspace for return statements in functions of
-* gpiops examples for proper documentation while
-* generating doxygen.
-* 3.3 ms 04/17/17 Added notes about gpio input and output pin description
-* for zcu102 and zc702 boards in polled and interrupt
-* example, configured Interrupt pin to input pin for
-* proper functioning of interrupt example.
-* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
-* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
-* in safety mode and modified the code such as
-* Use of mixed mode arithmetic,Declared the pointer param
-* as Pointer to const,Casting operation to a pointer,
-* Literal value requires a U suffix.
-* 3.5 sne 03/14/19 Added Versal support.
-* 3.6 mus 04/05/19 Replaced XPLAT_versal macro with XPLAT_VERSAL, to be in
-* sync with standalone BSP
-* 3.6 sne 06/12/19 Fixed IAR compiler warning.
-* 3.6 sne 08/14/19 Added interrupt handler support on versal.
-* 3.7 sne 12/04/19 Reverted versal examples support.
-* 3.8 sne 08/28/20 Modify Makefile to support parallel make execution.
-* 3.8 sne 09/17/20 Added description for Versal PS and PMC GPIO pins.
-* 3.9 sne 03/15/21 Fixed MISRA-C violations.
-*
-*
-*
-******************************************************************************/
-#ifndef XGPIOPS_H /* prevent circular inclusions */
-#define XGPIOPS_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xgpiops_hw.h"
-#include "xplatform_info.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Interrupt types
- * @{
- * The following constants define the interrupt types that can be set for each
- * GPIO pin.
- */
-#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */
-#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */
-#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */
-#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */
-#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
-/** @}*/
-
-#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
-#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
-#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
-#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
-#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
-
-#ifdef XPAR_PSU_GPIO_0_BASEADDR
-#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */
-#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */
-#endif
-
-#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a
- * Zynq Ultrascale+ MP GPIO device
- */
-#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
-
-#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
- * Zynq Ultrascale+ MP GPIO device
- * 0 - 25, Bank 0
- * 26 - 51, Bank 1
- * 52 - 77, Bank 2
- * 78 - 109, Bank 3
- * 110 - 141, Bank 4
- * 142 - 173, Bank 5
- */
-#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device
- * 0 - 31, Bank 0
- * 32 - 53, Bank 1
- * 54 - 85, Bank 2
- * 86 - 117, Bank 3
- */
-
-/**************************** Type Definitions *******************************/
-
-/****************************************************************************/
-/**
- * This handler data type allows the user to define a callback function to
- * handle the interrupts for the GPIO device. The application using this
- * driver is expected to define a handler of this type, to support interrupt
- * driven mode. The handler executes in an interrupt context such that minimal
- * processing should be performed.
- *
- * @param CallBackRef is a callback reference passed in by the upper layer
- * when setting the callback functions for a GPIO bank. It is
- * passed back to the upper layer when the callback is invoked. Its
- * type is not important to the driver component, so it is a void
- * pointer.
- * @param Bank is the bank for which the interrupt status has changed.
- * @param Status is the Interrupt status of the GPIO bank.
- *
- *****************************************************************************/
-typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
-
-/**
- * This typedef contains configuration information for a device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- UINTPTR BaseAddr; /**< Register base address */
-} XGpioPs_Config;
-
-/**
- * The XGpioPs driver instance data. The user is required to allocate a
- * variable of this type for the GPIO device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XGpioPs_Config GpioConfig; /**< Device configuration */
- u32 IsReady; /**< Device is initialized and ready */
- XGpioPs_Handler Handler; /**< Status handlers for all banks */
- void *CallBackRef; /**< Callback ref for bank handlers */
- u32 Platform; /**< Platform data */
- u32 MaxPinNum; /**< Max pins in the GPIO device */
- u8 MaxBanks; /**< Max banks in a GPIO device */
- u32 PmcGpio; /**< Flag for accessing PS GPIO for versal*/
-} XGpioPs;
-
-/************************** Variable Definitions *****************************/
-extern XGpioPs_Config XGpioPs_ConfigTable[];
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/* Functions in xgpiops.c */
-s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
- u32 EffectiveAddr);
-
-/* Bank APIs in xgpiops.c */
-u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data);
-void XGpioPs_SetDirection(const XGpioPs *InstancePtr, u8 Bank, u32 Direction);
-u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_SetOutputEnable(const XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
-u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank);
-#ifdef versal
-void XGpioPs_GetBankPin(const XGpioPs *InstancePtr,u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank);
-#else
-void XGpioPs_GetBankPin(u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank);
-#endif
-
-/* Pin APIs in xgpiops.c */
-u32 XGpioPs_ReadPin(const XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_WritePin(const XGpioPs *InstancePtr, u32 Pin, u32 Data);
-void XGpioPs_SetDirectionPin(const XGpioPs *InstancePtr, u32 Pin, u32 Direction);
-u32 XGpioPs_GetDirectionPin(const XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
-u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin);
-
-/* Diagnostic functions in xgpiops_selftest.c */
-s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr);
-
-/* Functions in xgpiops_intr.c */
-/* Bank APIs in xgpiops_intr.c */
-void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
-void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
-u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank);
-u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
-void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
- u32 IntrPolarity, u32 IntrOnAny);
-void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
- u32 *IntrPolarity, u32 *IntrOnAny);
-void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
- XGpioPs_Handler FuncPointer);
-void XGpioPs_IntrHandler(const XGpioPs *InstancePtr);
-
-/* Pin APIs in xgpiops_intr.c */
-void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
-u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin);
-
-void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin);
-u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin);
-u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin);
-
-/* Functions in xgpiops_sinit.c */
-XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4e/d0f7c7595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4e/d0f7c7595243001d18b399c1eb9b3628
deleted file mode 100644
index bb3765d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4e/d0f7c7595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,504 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xuartps.h
-* @addtogroup uartps_v3_11
-* @{
-* @details
-*
-* This driver supports the following features:
-*
-* - Dynamic data format (baud rate, data bits, stop bits, parity)
-* - Polled mode
-* - Interrupt driven mode
-* - Transmit and receive FIFOs (32 byte FIFO depth)
-* - Access to the external modem control lines
-*
-* Initialization & Configuration
-*
-* The XUartPs_Config structure is used by the driver to configure itself.
-* Fields inside this structure are properties of XUartPs based on its hardware
-* build.
-*
-* To support multiple runtime loading and initialization strategies employed
-* by various operating systems, the driver instance can be initialized in the
-* following way:
-*
-* - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-* configuration structure provided by the caller. If running in a system
-* with address translation, the parameter EffectiveAddr should be the
-* virtual address.
-*
-* Baud Rate
-*
-* The UART has an internal baud rate generator, which furnishes the baud rate
-* clock for both the receiver and the transmitter. The input clock frequency
-* can be either the master clock or the master clock divided by 8, configured
-* through the mode register.
-*
-* Accompanied with the baud rate divider register, the baud rate is determined
-* by:
-*
-* where bgen is the value of the baud rate generator, and bdiv is the value of
-* baud rate divider.
-*
-* Interrupts
-*
-* The FIFOs are not flushed when the driver is initialized, but a function is
-* provided to allow the user to reset the FIFOs if desired.
-*
-* The driver defaults to no interrupts at initialization such that interrupts
-* must be enabled if desired. An interrupt is generated for one of the
-* following conditions.
-*
-* - A change in the modem signals
-* - Data in the receive FIFO for a configuable time without receiver activity
-* - A parity error
-* - A framing error
-* - An overrun error
-* - Transmit FIFO is full
-* - Transmit FIFO is empty
-* - Receive FIFO is full
-* - Receive FIFO is empty
-* - Data in the receive FIFO equal to the receive threshold
-*
-* The application can control which interrupts are enabled using the
-* XUartPs_SetInterruptMask() function.
-*
-* In order to use interrupts, it is necessary for the user to connect the
-* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
-* system of the application. A separate handler should be provided by the
-* application to communicate with the interrupt system, and conduct
-* application specific interrupt handling. An application registers its own
-* handler through the XUartPs_SetHandler() function.
-*
-* Data Transfer
-*
-* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
-* driver to allow data to be sent and received. They can be used in either
-* polled or interrupt mode.
-*
-* @note
-*
-* The default configuration for the UART after initialization is:
-*
-* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
-* - 8 data bits
-* - 1 stop bit
-* - no parity
-* - FIFO's are enabled with a receive threshold of 8 bytes
-* - The RX timeout is enabled with a timeout of 1 (4 char times)
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00a drg/jz 01/12/10 First Release
-* 1.00a sdm 09/27/11 Fixed compiler warnings and also a bug
-* in XUartPs_SetFlowDelay where the value was not
-* being written to the register.
-* 1.01a sdm 12/20/11 Removed the InputClockHz parameter from the XUartPs
-* instance structure and the driver is updated to use
-* InputClockHz parameter from the XUartPs_Config config
-* structure.
-* Added a parameter to XUartPs_Config structure which
-* specifies whether the user has selected Modem pins
-* to be connected to MIO or FMIO.
-* Added the tcl file to generate the xparameters.h
-* 1.02a sg 05/16/12 Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
-* 1.03a sg 07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
-* with the correct values for CR 666724
-* Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
-* and XUARTPS_IXR_TTRIG.
-* Modified the name of these defines
-* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
-* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
-* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
-* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
-* 1.05a hk 08/22/13 Added API for uart reset and related
-* constant definitions.
-* 2.0 hk 03/07/14 Version number revised.
-* 2.1 hk 04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
-* 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing
-* baud rate. CR# 804281.
-* 3.0 vm 12/09/14 Modified source code according to misrac guideline.
-* Support for Zynq Ultrascale Mp added.
-* 3.1 kvn 04/10/15 Modified code for latest RTL changes. Also added
-* platform variable in driver instance structure.
-* 3.1 adk 14/03/16 Include interrupt examples in the peripheral test when
-* uart is connected to a valid interrupt controller CR#946803.
-* 3.2 rk 07/20/16 Modified the logic for transmission break bit set
-* 3.4 ms 01/23/17 Added xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 3.6 ms 02/16/18 Updates the flow control mode offset value in modem
-* control register.
-* 3.7 aru 08/17/18 Resolved MISRA-C:2012 compliance mandatory violations.
-* 3.9 rna 12/03/19 Modified the XUARTPS_MAX_RATE macro.
-* 3.9 sd 02/06/20 Added clock support
-*
-*
-*
-*****************************************************************************/
-
-#ifndef XUARTPS_H /* prevent circular inclusions */
-#define XUARTPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xuartps_hw.h"
-#include "xplatform_info.h"
-#if defined (XCLOCKING)
-#include "xil_clocking.h"
-#endif
-
-/************************** Constant Definitions ****************************/
-
-/*
- * The following constants indicate the max and min baud rates and these
- * numbers are based only on the testing that has been done. The hardware
- * is capable of other baud rates.
- */
-#define XUARTPS_MAX_RATE 6240000U
-#define XUARTPS_MIN_RATE 110U
-
-#define XUARTPS_DFT_BAUDRATE 115200U /* Default baud rate */
-
-/** @name Configuration options
- * @{
- */
-/**
- * These constants specify the options that may be set or retrieved
- * with the driver, each is a unique bit mask such that multiple options
- * may be specified. These constants indicate the available options
- * in active state.
- *
- */
-
-#define XUARTPS_OPTION_SET_BREAK 0x0080U /**< Starts break transmission */
-#define XUARTPS_OPTION_STOP_BREAK 0x0040U /**< Stops break transmission */
-#define XUARTPS_OPTION_RESET_TMOUT 0x0020U /**< Reset the receive timeout */
-#define XUARTPS_OPTION_RESET_TX 0x0010U /**< Reset the transmitter */
-#define XUARTPS_OPTION_RESET_RX 0x0008U /**< Reset the receiver */
-#define XUARTPS_OPTION_ASSERT_RTS 0x0004U /**< Assert the RTS bit */
-#define XUARTPS_OPTION_ASSERT_DTR 0x0002U /**< Assert the DTR bit */
-#define XUARTPS_OPTION_SET_FCM 0x0001U /**< Turn on flow control mode */
-/*@}*/
-
-
-/** @name Channel Operational Mode
- *
- * The UART can operate in one of four modes: Normal, Local Loopback, Remote
- * Loopback, or automatic echo.
- *
- * @{
- */
-
-#define XUARTPS_OPER_MODE_NORMAL (u8)0x00U /**< Normal Mode */
-#define XUARTPS_OPER_MODE_AUTO_ECHO (u8)0x01U /**< Auto Echo Mode */
-#define XUARTPS_OPER_MODE_LOCAL_LOOP (u8)0x02U /**< Local Loopback Mode */
-#define XUARTPS_OPER_MODE_REMOTE_LOOP (u8)0x03U /**< Remote Loopback Mode */
-
-/* @} */
-
-/** @name Data format values
- *
- * These constants specify the data format that the driver supports.
- * The data format includes the number of data bits, the number of stop
- * bits and parity.
- *
- * @{
- */
-#define XUARTPS_FORMAT_8_BITS 0U /**< 8 data bits */
-#define XUARTPS_FORMAT_7_BITS 2U /**< 7 data bits */
-#define XUARTPS_FORMAT_6_BITS 3U /**< 6 data bits */
-
-#define XUARTPS_FORMAT_NO_PARITY 4U /**< No parity */
-#define XUARTPS_FORMAT_MARK_PARITY 3U /**< Mark parity */
-#define XUARTPS_FORMAT_SPACE_PARITY 2U /**< parity */
-#define XUARTPS_FORMAT_ODD_PARITY 1U /**< Odd parity */
-#define XUARTPS_FORMAT_EVEN_PARITY 0U /**< Even parity */
-
-#define XUARTPS_FORMAT_2_STOP_BIT 2U /**< 2 stop bits */
-#define XUARTPS_FORMAT_1_5_STOP_BIT 1U /**< 1.5 stop bits */
-#define XUARTPS_FORMAT_1_STOP_BIT 0U /**< 1 stop bit */
-/*@}*/
-
-/** @name Callback events
- *
- * These constants specify the handler events that an application can handle
- * using its specific handler function. Note that these constants are not bit
- * mask, so only one event can be passed to an application at a time.
- *
- * @{
- */
-#define XUARTPS_EVENT_RECV_DATA 1U /**< Data receiving done */
-#define XUARTPS_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */
-#define XUARTPS_EVENT_SENT_DATA 3U /**< Data transmission done */
-#define XUARTPS_EVENT_RECV_ERROR 4U /**< A receive error detected */
-#define XUARTPS_EVENT_MODEM 5U /**< Modem status changed */
-#define XUARTPS_EVENT_PARE_FRAME_BRKE 6U /**< A receive parity, frame, break
- * error detected */
-#define XUARTPS_EVENT_RECV_ORERR 7U /**< A receive overrun error detected */
-
-/*@}*/
-
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of device (IPIF) */
- u32 InputClockHz;/**< Input clock frequency */
- s32 ModemPinsConnected; /** Specifies whether modem pins are connected
- * to MIO or FMIO */
-#if defined (XCLOCKING)
- u32 RefClk; /**< Input clock frequency */
-#endif
-} XUartPs_Config;
-
-/* Keep track of state information about a data buffer in the interrupt mode. */
-typedef struct {
- u8 *NextBytePtr;
- u32 RequestedBytes;
- u32 RemainingBytes;
-} XUartPsBuffer;
-
-/**
- * Keep track of data format setting of a device.
- */
-typedef struct {
- u32 BaudRate; /**< In bps, ie 1200 */
- u32 DataBits; /**< Number of data bits */
- u32 Parity; /**< Parity */
- u8 StopBits; /**< Number of stop bits */
-} XUartPsFormat;
-
-/******************************************************************************/
-/**
- * This data type defines a handler that an application defines to communicate
- * with interrupt system to retrieve state information about an application.
- *
- * @param CallBackRef is a callback reference passed in by the upper layer
- * when setting the handler, and is passed back to the upper layer
- * when the handler is called. It is used to find the device driver
- * instance.
- * @param Event contains one of the event constants indicating events that
- * have occurred.
- * @param EventData contains the number of bytes sent or received at the
- * time of the call for send and receive events and contains the
- * modem status for modem events.
- *
- ******************************************************************************/
-typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
- u32 EventData);
-
-/**
- * The XUartPs driver instance data structure. A pointer to an instance data
- * structure is passed around by functions to refer to a specific driver
- * instance.
- */
-typedef struct {
- XUartPs_Config Config; /* Configuration data structure */
- u32 InputClockHz; /* Input clock frequency */
- u32 IsReady; /* Device is initialized and ready */
- u32 BaudRate; /* Current baud rate */
-
- XUartPsBuffer SendBuffer;
- XUartPsBuffer ReceiveBuffer;
-
- XUartPs_Handler Handler;
- void *CallBackRef; /* Callback reference for event handler */
- u32 Platform;
- u8 is_rxbs_error;
-} XUartPs;
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* Get the UART Channel Status Register.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_GetChannelStatus(InstancePtr) \
- Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
-
-/****************************************************************************/
-/**
-* Get the UART Mode Control Register.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XUartPs_GetControl(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_GetModeControl(InstancePtr) \
- Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
-
-/****************************************************************************/
-/**
-* Set the UART Mode Control Register.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
-*
-******************************************************************************/
-#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
- Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
- (u32)(RegisterValue))
-
-/****************************************************************************/
-/**
-* Enable the transmitter and receiver of the UART.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_EnableUart(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_EnableUart(InstancePtr) \
- Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
- ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
- (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
-
-/****************************************************************************/
-/**
-* Disable the transmitter and receiver of the UART.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_DisableUart(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_DisableUart(InstancePtr) \
- Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
- (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
- (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
-
-/****************************************************************************/
-/**
-* Determine if the transmitter FIFO is empty.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-* - TRUE if a byte can be sent
-* - FALSE if the Transmitter Fifo is not empty
-*
-* @note C-Style signature:
-* u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_IsTransmitEmpty(InstancePtr) \
- ((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
- (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
-
-
-/************************** Function Prototypes *****************************/
-
-/* Static lookup function implemented in xuartps_sinit.c */
-XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
-
-/* Interface functions implemented in xuartps.c */
-s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
- XUartPs_Config * Config, u32 EffectiveAddr);
-
-u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
- u32 NumBytes);
-
-u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
- u32 NumBytes);
-
-s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
-
-/* Options functions in xuartps_options.c */
-void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
-
-u16 XUartPs_GetOptions(XUartPs *InstancePtr);
-
-void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
-
-u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
-
-u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
-
-u32 XUartPs_IsSending(XUartPs *InstancePtr);
-
-u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
-
-void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
-
-u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
-
-void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
-
-u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
-
-void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
-
-s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
-
-void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
-
-/* interrupt functions in xuartps_intr.c */
-u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
-
-void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
-
-void XUartPs_InterruptHandler(XUartPs *InstancePtr);
-
-void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
- void *CallBackRef);
-
-/* self-test functions in xuartps_selftest.c */
-s32 XUartPs_SelfTest(XUartPs *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4f/2054f4585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4f/2054f4585243001d18b399c1eb9b3628
deleted file mode 100644
index 85a1af4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4f/2054f4585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,202 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2012 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_mmu.c
-*
-* This file provides APIs for enabling/disabling MMU and setting the memory
-* attributes for sections, in the MMU translation table.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 01/12/12 Initial version
-* 3.05a asa 03/10/12 Modified the Xil_EnableMMU to invalidate the caches
-* before enabling back.
-* 3.05a asa 04/15/12 Modified the Xil_SetTlbAttributes routine so that
-* translation table and branch predictor arrays are
-* invalidated, D-cache flushed before the attribute
-* change is applied. This is done so that the user
-* need not call Xil_DisableMMU before calling
-* Xil_SetTlbAttributes.
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-* 3.11a asa 09/23/13 Modified Xil_SetTlbAttributes to flush the complete
-* D cache after the translation table update. Removed the
-* redundant TLB invalidation in the same API at the beginning.
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-* It fixes CR#1008309.
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-#include "xil_mmu.h"
-#include "xil_errata.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-#define ARM_AR_MEM_TTB_SECT_SIZE 1024*1024
-#define ARM_AR_MEM_TTB_SECT_SIZE_MASK (~(ARM_AR_MEM_TTB_SECT_SIZE-1UL))
-/************************** Variable Definitions *****************************/
-
-extern u32 MMUTable;
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-* @brief This function sets the memory attributes for a section covering 1MB
-* of memory in the translation table.
-*
-* @param Addr: 32-bit address for which memory attributes need to be set.
-* @param attrib: Attribute for the given memory region. xil_mmu.h contains
-* definitions of commonly used memory attributes which can be
-* utilized for this function.
-*
-*
-* @return None.
-*
-* @note The MMU or D-cache does not need to be disabled before changing a
-* translation table entry.
-*
-******************************************************************************/
-void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib)
-{
- u32 *ptr;
- u32 section;
-
- section = Addr / 0x100000U;
- ptr = &MMUTable;
- ptr += section;
- if(ptr != NULL) {
- *ptr = (Addr & 0xFFF00000U) | attrib;
- }
-
- Xil_DCacheFlush();
-
- mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
- /* Invalidate all branch predictors */
- mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
-
- dsb(); /* ensure completion of the BP and TLB invalidation */
- isb(); /* synchronize context on this processor */
-}
-
-/*****************************************************************************/
-/**
-* @brief Enable MMU for cortex A9 processor. This function invalidates the
-* instruction and data caches, and then enables MMU.
-*
-* @return None.
-*
-******************************************************************************/
-void Xil_EnableMMU(void)
-{
- u32 Reg;
- Xil_DCacheInvalidate();
- Xil_ICacheInvalidate();
-
-#ifdef __GNUC__
- Reg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, Reg);
-#else
- { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
- Reg = Cp15Reg; }
-#endif
- Reg |= (u32)0x05U;
- mtcp(XREG_CP15_SYS_CONTROL, Reg);
-
- dsb();
- isb();
-}
-
-/*****************************************************************************/
-/**
-* @brief Disable MMU for Cortex A9 processors. This function invalidates
-* the TLBs, Branch Predictor Array and flushed the D Caches before
-* disabling the MMU.
-*
-* @return None.
-*
-* @note When the MMU is disabled, all the memory accesses are treated as
-* strongly ordered.
-******************************************************************************/
-void Xil_DisableMMU(void)
-{
- u32 Reg;
-
- mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
- mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
- Xil_DCacheFlush();
-
-#ifdef __GNUC__
- Reg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, Reg);
-#else
- { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
- Reg = Cp15Reg; }
-#endif
- Reg &= (u32)(~0x05U);
-#ifdef CONFIG_ARM_ERRATA_794073
- /* Disable Branch Prediction */
- Reg &= (u32)(~0x800U);
-#endif
- mtcp(XREG_CP15_SYS_CONTROL, Reg);
-}
-
-/*****************************************************************************/
-/**
-* @brief Memory mapping for Cortex A9 processor.
-*
-* @param PhysAddr is physical address.
-* @param size is size of region.
-* @param flags is flags used to set translation table.
-*
-* @return Pointer to virtual address.
-*
-* @note: Previously this was implemented in libmetal. Move to embeddedsw as this
-* functionality is specific to A9 processor.
-*
-******************************************************************************/
-void* Xil_MemMap(UINTPTR PhysAddr, size_t size, u32 flags)
-{
- u32 Sectionoffset;
- u32 Ttbaddr;
-
- if (!flags)
- return (void*)PhysAddr;
-
- /* Ensure alignment on a section boundary */
- PhysAddr &= ARM_AR_MEM_TTB_SECT_SIZE_MASK;
-
- /* Loop through entire region of memory (one MMU section at a time).
- Each section requires a TTB entry. */
- for (Sectionoffset = 0; Sectionoffset < size;
- Sectionoffset += ARM_AR_MEM_TTB_SECT_SIZE) {
- /* Calculate translation table entry for this memory section */
- Ttbaddr = (PhysAddr + Sectionoffset);
-
- /* Write translation table entry value to entry address */
- Xil_SetTlbAttributes(Ttbaddr, flags);
- }
- return (void*)PhysAddr;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4f/21e797595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4f/21e797595243001d18b399c1eb9b3628
deleted file mode 100644
index b3dd7e9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4f/21e797595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,126 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_assert.c
-* @addtogroup common_assert_apis Assert APIs and Macros
-* @{
-*
-* This file contains basic assert related functions for Xilinx software IP.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 Initial release
-* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/**
- * @brief This variable allows testing to be done easier with asserts. An assert
- * sets this variable such that a driver can evaluate this variable
- * to determine if an assert occurred.
- */
-u32 Xil_AssertStatus;
-
-/**
- * @brief This variable allows the assert functionality to be changed for testing
- * such that it does not wait infinitely. Use the debugger to disable the
- * waiting during testing of asserts.
- */
-s32 Xil_AssertWait = 1;
-
-/* The callback function to be invoked when an assert is taken */
-static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* @brief Implement assert. Currently, it calls a user-defined callback
-* function if one has been set. Then, it potentially enters an
-* infinite loop depending on the value of the Xil_AssertWait
-* variable.
-*
-* @param File: filename of the source
-* @param Line: linenumber within File
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void Xil_Assert(const char8 *File, s32 Line)
-{
- /* if the callback has been set then invoke it */
- if (Xil_AssertCallbackRoutine != 0) {
- (*Xil_AssertCallbackRoutine)(File, Line);
- }
-
- /* if specified, wait indefinitely such that the assert will show up
- * in testing
- */
- while (Xil_AssertWait != 0) {
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Set up a callback function to be invoked when an assert occurs.
-* If a callback is already installed, then it will be replaced.
-*
-* @param Routine: callback to be invoked when an assert is taken
-*
-* @return None.
-*
-* @note This function has no effect if NDEBUG is set
-*
-******************************************************************************/
-void Xil_AssertSetCallback(Xil_AssertCallback Routine)
-{
- Xil_AssertCallbackRoutine = Routine;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Null handler function. This follows the XInterruptHandler
-* signature for interrupt handlers. It can be used to assign a null
-* handler (a stub) to an interrupt controller vector table.
-*
-* @param NullParameter: arbitrary void pointer and not used.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XNullHandler(void *NullParameter)
-{
- (void) NullParameter;
-}
-/**
-* @} End of "addtogroup common_assert_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4f/309476545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4f/309476545243001d18b399c1eb9b3628
deleted file mode 100644
index 5feeb49..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4f/309476545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,39 +0,0 @@
-DRIVER_LIB_VERSION = 1.0
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I$(INCLUDEDIR)
-
-SRCFILES:=$(wildcard *.c)
-
-OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
-
-libs: $(OBJECTS)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf $(DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4f/40e401555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4f/40e401555243001d18b399c1eb9b3628
deleted file mode 100644
index 4c55bbd..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4f/40e401555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,18 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include "xil_types.h"
-
-/* _exit - Simple implementation. Does not return.
-*/
-__attribute__((weak)) void _exit (sint32 status)
-{
- (void)status;
- while (1) {
- ;
- }
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4f/60f9c0565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4f/60f9c0565243001d18b399c1eb9b3628
deleted file mode 100644
index 85fb264..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4f/60f9c0565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,37 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
- .globl dummy_f
-
-#ifdef PROC_MICROBLAZE
- .text
- .align 2
- .ent dummy_f
-
-dummy_f:
- nop
-
- .end dummy_f
-#endif
-
-#ifdef PROC_PPC
- .section .text
- .align 2
- .type dummy_f@function
-
-dummy_f:
- b dummy_f
-
-#endif
-
-#ifdef PROC_CORTEXA9
- .section .text
- .align 2
- .type dummy_f, %function
-
-dummy_f:
- b dummy_f
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4f/90fbdc585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4f/90fbdc585243001d18b399c1eb9b3628
deleted file mode 100644
index 072e779..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/4f/90fbdc585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,169 +0,0 @@
-;******************************************************************************
-; Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-; SPDX-License-Identifier: MIT
-;*****************************************************************************
-;****************************************************************************
-;**
-; @file translation_table.s
-;
-; This file contains the initialization for the MMU table in RAM
-; needed by the Cortex A9 processor
-;
-;
-; MODIFICATION HISTORY:
-;
-; Ver Who Date Changes
-; ----- ---- -------- ---------------------------------------------------
-; 1.00a ecm 10/20/09 Initial version
-; 3.07a sgd 07/05/2012 Configuring device address spaces as shareable device
-; instead of strongly-ordered.
-; 4.2 pkp 09/02/14 modified translation table entries according to address map
-; 4.2 pkp 09/11/14 modified translation table entries to resolve compilation
-; error for solving CR#822897
-; 6.1 pkp 07/11/16 Corrected comments for memory attributes
-;
-* The translation_table.S contains a static page table required by MMU for
-* cortex-A9. This translation table is flat mapped (input address = output
-* address) with default memory attributes defined for zynq architecture. It
-* utilizes short descriptor translation table format with each section defining
-* 1 MB of memory.
-*
-* The overview of translation table memory attributes is described below.
-*
-*| | Memory Range | Definition in Translation Table |
-*|-----------------------|-------------------------|-----------------------------------|
-*| DDR | 0x00000000 - 0x3FFFFFFF | Normal write-back Cacheable |
-*| PL | 0x40000000 - 0xBFFFFFFF | Strongly Ordered |
-*| Reserved | 0xC0000000 - 0xDFFFFFFF | Unassigned |
-*| Memory mapped devices | 0xE0000000 - 0xE02FFFFF | Device Memory |
-*| Reserved | 0xE0300000 - 0xE0FFFFFF | Unassigned |
-*| NAND, NOR | 0xE1000000 - 0xE3FFFFFF | Device memory |
-*| SRAM | 0xE4000000 - 0xE5FFFFFF | Normal write-back Cacheable |
-*| Reserved | 0xE6000000 - 0xF7FFFFFF | Unassigned |
-*| AMBA APB Peripherals | 0xF8000000 - 0xF8FFFFFF | Device Memory |
-*| Reserved | 0xF9000000 - 0xFBFFFFFF | Unassigned |
-*| Linear QSPI - XIP | 0xFC000000 - 0xFDFFFFFF | Normal write-through cacheable |
-*| Reserved | 0xFE000000 - 0xFFEFFFFF | Unassigned |
-*| OCM | 0xFFF00000 - 0xFFFFFFFF | Normal inner write-back cacheable |
-*
-* For region 0x00000000 - 0x3FFFFFFF, a system where DDR is less than 1 GB,
-* region after DDR and before PL is marked as undefined/reserved in translation
-* table. In 0xF8000000 - 0xF8FFFFFF, 0xF8000C00 - 0xF8000FFF, 0xF8010000 -
-* 0xF88FFFFF and 0xF8F03000 to 0xF8FFFFFF are reserved but due to granual size
-* of 1 MB, it is not possible to define separate regions for them. For region
-* 0xFFF00000 - 0xFFFFFFFF, 0xFFF00000 to 0xFFFB0000 is reserved but due to 1MB
-* granual size, it is not possible to define separate region for it.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 10/20/09 Initial version
-* 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
-* 3.07a sgd 07/05/2012 Configuring device address spaces as shareable device
-* instead of strongly-ordered.
-* 3.07a asa 07/17/2012 Changed the property of the ".mmu_tbl" section.
-* 4.2 pkp 09/02/2014 added entries for 0xfe000000 to 0xffefffff as reserved
-* and 0xe0000000 - 0xe1ffffff is broken down into
-* 0xe0000000 - 0xe02fffff (memory mapped divides)
-* 0xe0300000 - 0xe0ffffff (reserved) and
-* 0xe1000000 - 0xe1ffffff (NAND)
-* 5.2 pkp 06/08/2015 put a check for XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm
-* if DDR is present or not and accordingly generate the
-* translation table
-* 6.1 pkp 07/11/2016 Corrected comments for memory attributes
-* 6.8 mus 07/12/2018 Mark DDR memory as inner cacheable, if BSP is built
-* with the USE_AMP flag.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00 pkp 02/20/14 First release
-* 5.04 pkp 12/18/15 Updated MPU initialization as per the proper address map
-* 6.00 pkp 06/27/16 moving the Init_MPU code to .boot section since it is a
-* part of processor boot process
-* 6.2 mus 01/27/17 Updated to support IAR compiler
-* 7.1 mus 09/11/19 Added warning message if DDR size is not in power of 2.
-* Fix for CR#1038577.
-* 7.2 asa 04/08/20 Fix warning in the function Init_MPU.
-* 7.5 mus 01/13/21 Removed redundant declaration for Mpu_Config,
-* declaration is present in xil_mpu.h.
-* 7.5 asa 03/07/21 Ensure that Update_MpuConfig_Array stays in .boot section
-* as it is used only during bootup.
-* Add function header to Init_MPU function.
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_printf.h"
-#include "xreg_cortexr5.h"
-#include "xil_mpu.h"
-#include "xpseudo_asm.h"
-#include "xparameters.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-static const struct {
- u64 size;
- unsigned int encoding;
-}region_size[] = {
- { 0x20, REGION_32B },
- { 0x40, REGION_64B },
- { 0x80, REGION_128B },
- { 0x100, REGION_256B },
- { 0x200, REGION_512B },
- { 0x400, REGION_1K },
- { 0x800, REGION_2K },
- { 0x1000, REGION_4K },
- { 0x2000, REGION_8K },
- { 0x4000, REGION_16K },
- { 0x8000, REGION_32K },
- { 0x10000, REGION_64K },
- { 0x20000, REGION_128K },
- { 0x40000, REGION_256K },
- { 0x80000, REGION_512K },
- { 0x100000, REGION_1M },
- { 0x200000, REGION_2M },
- { 0x400000, REGION_4M },
- { 0x800000, REGION_8M },
- { 0x1000000, REGION_16M },
- { 0x2000000, REGION_32M },
- { 0x4000000, REGION_64M },
- { 0x8000000, REGION_128M },
- { 0x10000000, REGION_256M },
- { 0x20000000, REGION_512M },
- { 0x40000000, REGION_1G },
- { 0x80000000, REGION_2G },
- { 0x100000000, REGION_4G },
-};
-
-/************************** Function Prototypes ******************************/
-#if defined (__GNUC__)
-void Init_MPU(void) __attribute__((__section__(".boot")));
-static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib) __attribute__((__section__(".boot")));
-static void Xil_DisableMPURegions(void) __attribute__((__section__(".boot")));
-static inline void Update_MpuConfig_Array(u32 Addr,u32 RegSize,u32 RegNum, u32 Attrib) __attribute__((__section__(".boot")));
-#elif defined (__ICCARM__)
-#pragma default_function_attributes = @ ".boot"
-void Init_MPU(void);
-static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib);
-static void Xil_DisableMPURegions(void);
-#endif
-/*****************************************************************************
-*
-* Initialize MPU for a given address map and Enabled the background Region in
-* MPU with default memory attributes for rest of address range for Cortex R5
-* processor.
-*
-* @param None.
-*
-* @return None.
-*
-*
-******************************************************************************/
-static inline void Update_MpuConfig_Array(u32 Addr,u32 RegSize,u32 RegNum,
- u32 Attrib)
-{
- Mpu_Config[RegNum].RegionStatus = MPU_REG_ENABLED;
- Mpu_Config[RegNum].BaseAddress = Addr;
- Mpu_Config[RegNum].Size = RegSize;
- Mpu_Config[RegNum].Attribute = Attrib;
-}
-
-/*****************************************************************************
-*
-* Initialize MPU for during bootup with predefined region attributes.
-*
-* @param None.
-*
-* @return None.
-*
-*
-******************************************************************************/
-void Init_MPU(void)
-{
- u32 Addr;
- u32 RegSize = 0U;
- u32 Attrib;
- u32 RegNum = 0, i, Offset = 0;
- u64 size;
-
- Xil_DisableMPURegions();
-
- Addr = 0x00000000U;
-#ifdef XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR
- /* If the DDR is present, configure region as per DDR size */
- size = (XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR - XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR) + 1;
- if (size < 0x80000000) {
- /* Lookup the size. */
- for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) {
- if (size <= region_size[i].size) {
- RegSize = region_size[i].encoding;
-
- /* Check if DDR size is in power of 2*/
- if ( XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR == 0x100000)
- Offset = XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR;
- if (region_size[i].size > (size + Offset + 1)) {
- xil_printf ("WARNING: DDR size mapped to Cortexr5 processor is not \
- in power of 2. As processor allocates MPU regions size \
- in power of 2, address range %llx to %x has been \
- incorrectly mapped as normal memory \n", \
- region_size[i].size - 1, ((u32)XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR + 1));
- }
- break;
- }
- }
- } else {
- /* if the DDR size is > 2GB, truncate it to 2GB */
- RegSize = REGION_2G;
- }
-#else
- /* For DDRless system, configure region for TCM */
- RegSize = REGION_256K;
-#endif
- Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /*
- * 1G of strongly ordered memory from 0x80000000 to 0xBFFFFFFF for PL.
- * 512 MB - LPD-PL interface
- * 256 MB - FPD-PL (HPM0) interface
- * 256 MB - FPD-PL (HPM1) interface
- */
- Addr = 0x80000000;
- RegSize = REGION_1G;
- Attrib = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 512M of device memory from 0xC0000000 to 0xDFFFFFFF for QSPI */
- Addr = 0xC0000000U;
- RegSize = REGION_512M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 256M of device memory from 0xE0000000 to 0xEFFFFFFF for PCIe Low */
- Addr = 0xE0000000U;
- RegSize = REGION_256M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 16M of device memory from 0xF8000000 to 0xF8FFFFFF for STM_CORESIGHT */
- Addr = 0xF8000000U;
- RegSize = REGION_16M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 1M of device memory from 0xF9000000 to 0xF90FFFFF for RPU_A53_GIC */
- Addr = 0xF9000000U;
- RegSize = REGION_1M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 16M of device memory from 0xFD000000 to 0xFDFFFFFF for FPS slaves */
- Addr = 0xFD000000U;
- RegSize = REGION_16M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 16M of device memory from 0xFE000000 to 0xFEFFFFFF for Upper LPS slaves */
- Addr = 0xFE000000U;
- RegSize = REGION_16M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /*
- * 16M of device memory from 0xFF000000 to 0xFFFFFFFF for Lower LPS slaves,
- * CSU, PMU, TCM, OCM
- */
- Addr = 0xFF000000U;
- RegSize = REGION_16M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 256K of OCM RAM from 0xFFFC0000 to 0xFFFFFFFF marked as normal memory */
- Addr = 0xFFFC0000U;
- RegSize = REGION_256K;
- Attrib = NORM_NSHARED_WB_WA| PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
-
- /* A total of 10 MPU regions are allocated with another 6 being free for users */
-
-}
-
-/*****************************************************************************
-*
-* Set the memory attributes for a section of memory with starting address addr
-* of the region size defined by reg_size having attributes attrib of region number
-* reg_num
-*
-* @param addr is the address for which attributes are to be set.
-* @param attrib specifies the attributes for that memory region.
-* @param reg_size specifies the size for that memory region.
-* @param reg_num specifies the number for that memory region.
-* @return None.
-*
-*
-******************************************************************************/
-static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib)
-{
- u32 Local_reg_size = reg_size;
-
- Local_reg_size = Local_reg_size<<1U;
- Local_reg_size |= REGION_EN;
- dsb();
- mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num);
- isb();
- mtcp(XREG_CP15_MPU_REG_BASEADDR,addr); /* Set base address of a region */
- mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL,attrib); /* Set the control attribute */
- mtcp(XREG_CP15_MPU_REG_SIZE_EN,Local_reg_size); /* set the region size and enable it*/
- dsb();
- isb(); /* synchronize context on this processor */
-}
-
-
-/*****************************************************************************
-*
-* Disable all the MPU regions if any of them is enabled
-*
-* @param None.
-*
-* @return None.
-*
-*
-******************************************************************************/
-static void Xil_DisableMPURegions(void)
-{
- u32 Temp = 0U;
- u32 Index = 0U;
- for (Index = 0; Index <= 15; Index++) {
- mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index);
-#if defined (__GNUC__)
- Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
-#endif
- Temp &= (~REGION_EN);
- dsb();
- mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
- dsb();
- isb();
- }
-
-}
-
-#if defined (__ICCARM__)
-#pragma default_function_attributes =
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/50/c0ca5d565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/50/c0ca5d565243001d18b399c1eb9b3628
deleted file mode 100644
index d6bc637..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/50/c0ca5d565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,47 +0,0 @@
-/******************************************************************************/
-/**
-* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-* @file xil_mem.h
-*
-* @addtogroup common_mem_operation_api Customized APIs for Memory Operations
-*
-* The xil_mem.h file contains prototype for functions related
-* to memory operations. These APIs are applicable for all processors supported
-* by Xilinx.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.1 nsk 11/07/16 First release.
-* 7.0 mus 01/07/19 Add cpp extern macro
-*
-*
-*
-*****************************************************************************/
-#ifndef XIL_MEM_H /* prevent circular inclusions */
-#define XIL_MEM_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Function Prototypes *****************************/
-
-void Xil_MemCpy(void* dst, const void* src, u32 cnt);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_MEM_H */
-/**
-* @} End of "addtogroup common_mem_operation_api".
-*/
\ No newline at end of file
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/50/c29eff585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/50/c29eff585243001d18b399c1eb9b3628
deleted file mode 100644
index e9a9ace..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/50/c29eff585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,124 +0,0 @@
-;/******************************************************************************
-;* Copyright (c) 2020 - 2021 Xilinx, Inc. All rights reserved.
-;*
-;* SPDX-License-Identifier: MIT
-;*
-;******************************************************************************/
-;/*****************************************************************************/
-;/**
-;* @file asm_vectors.S
-;*
-;* This file contains the initial vector table for the Cortex R5 processor
-;* as per armclang compiler
-;*
-;*
-;* MODIFICATION HISTORY:
-;*
-;* Ver Who Date Changes
-;* ----- ------- -------- ---------------------------------------------------
-;* 7.3 dp 06/25/20 Initial version for armclang
-;*
-;*
-;* @note
-;*
-;* None.
-;*
-;******************************************************************************/
-
- EXPORT _vector_table
-
- IMPORT _boot
- IMPORT FIQInterrupt
- IMPORT IRQInterrupt
- IMPORT SWInterrupt
- IMPORT DataAbortInterrupt
- IMPORT PrefetchAbortInterrupt
- IMPORT UndefinedExceptionAddr
- IMPORT UndefinedException
- IMPORT DataAbortAddr
- IMPORT PrefetchAbortAddr
-
- EXPORT IRQHandler
-
- AREA |vectors|, CODE
- REQUIRE8 {TRUE}
- PRESERVE8 {TRUE}
- ENTRY ; Define this an entry point
-
-_vector_table
- ldr pc, =_boot
- ldr pc, =Undefined
- ldr pc, =SVCHandler
- ldr pc, =PrefetchAbortHandler
- ldr pc, =DataAbortHandler
- NOP ;Placeholder for address exception vector
- ldr pc, =IRQHandler
- ldr pc, =FIQHandler
-
-IRQHandler ;IRQ vector handler
- stmdb sp!,{r0-r3,r12,lr} ;state save from compiled code
-#ifndef __SOFTFP__
-
- vpush {d0-d7} ;Store floating point registers/
- vmrs r1, FPSCR
- push {r1}
- vmrs r1, FPEXC
- push {r1}
-#endif
- bl IRQInterrupt ;IRQ vector
-#ifndef __SOFTFP__
-
- pop {r1} ;Restore floating point registers
- vmsr FPEXC, r1
- pop {r1}
- vmsr FPSCR, r1
- vpop {d0-d7}
-#endif
- ldmia sp!,{r0-r3,r12,lr} ;state restore from compiled code
- subs pc, lr, #4 ;adjust return
-FIQHandler ;FIQ vector handler
- stmdb sp!,{r0-r3,r12,lr} ;state save from compiled code
-FIQLoop
- bl FIQInterrupt ;FIQ vector
- ldmia sp!,{r0-r3,r12,lr} ;state restore from compiled code
- subs pc, lr, #4 ;adjust return
-
-Undefined ;Undefined handler
- stmdb sp!,{r0-r3,r12,lr} ;state save from compiled code
- ldr r0, =UndefinedExceptionAddr
- sub r1, lr, #4
- str r1, [r0] ;Store address of instruction causing undefined exception
-
- bl UndefinedException ;UndefinedException: call C function here
- ldmia sp!,{r0-r3,r12,lr} ;state restore from compiled code
- movs pc, lr
-
-SVCHandler ;SWI handler
- stmdb sp!,{r0-r3,r12,lr} ;state save from compiled code
- tst r0, #0x20 ;check the T bit
- ldrneh r0, [lr,#-2] ;Thumb mode
- bicne r0, r0, #0xff00 ;Thumb mode
- ldreq r0, [lr,#-4] ;ARM mode
- biceq r0, r0, #0xff000000 ;ARM mode
- bl SWInterrupt ;SWInterrupt: call C function here
- ldmia sp!,{r0-r3,r12,lr} ;state restore from compiled code
- movs pc, lr ;adjust return
-
-DataAbortHandler ;Data Abort handler
- stmdb sp!,{r0-r3,r12,lr} ;state save from compiled code
- ldr r0, =DataAbortAddr
- sub r1, lr, #8
- str r1, [r0] ;Stores instruction causing data abort
- bl DataAbortInterrupt ;ataAbortInterrupt :call C function here
- ldmia sp!,{r0-r3,r12,lr} ;state restore from compiled code
- subs pc, lr, #8 ;adjust return
-
-PrefetchAbortHandler ;Prefetch Abort handler
- stmdb sp!,{r0-r3,r12,lr} ;state save from compiled code
- ldr r0, =PrefetchAbortAddr
- sub r1, lr, #4
- str r1, [r0] ;Stores instruction causing prefetch abort
- bl PrefetchAbortInterrupt ;PrefetchAbortInterrupt: call C function here
- ldmia sp!,{r0-r3,r12,lr} ;state restore from compiled code
- subs pc, lr, #4 ;adjust return
- END
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/51/402500575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/51/402500575243001d18b399c1eb9b3628
deleted file mode 100644
index 9d17f5c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/51/402500575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,86 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xtime_l.h
-* @addtogroup a9_time_apis Cortex A9 Time Functions
-*
-* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This
-* counter increases by one at every two processor cycles. These functions can
-* be used to get/set time in the global timer.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 1.00a rp/sdm 11/03/09 Initial release.
-* 3.06a sgd 05/15/12 Updated get/set time functions to make use Global Timer
-* 3.06a asa 06/17/12 Reverted back the changes to make use Global Timer.
-* 3.07a sgd 07/05/12 Updated get/set time functions to make use Global Timer
-* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep
-* implementation
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
-* displaying same warnings multiple times. It fixes CR#1090562.
-*
-*
-******************************************************************************/
-
-/**
-*@cond nocomments
-*/
-
-#ifndef XTIME_H /* prevent circular inclusions */
-#define XTIME_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xparameters.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-typedef u64 XTime;
-
-/************************** Constant Definitions *****************************/
-#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR
-#define GTIMER_COUNTER_LOWER_OFFSET 0x00U
-#define GTIMER_COUNTER_UPPER_OFFSET 0x04U
-#define GTIMER_CONTROL_OFFSET 0x08U
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY)
-#else
-/* Global Timer is always clocked at half of the CPU frequency */
-#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
-#endif
-/************************** Variable Definitions *****************************/
-
-/**
-*@endcond
-*/
-
-/************************** Function Prototypes ******************************/
-
-void XTime_SetTime(XTime Xtime_Global);
-void XTime_GetTime(XTime *Xtime_Global);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XTIME_H */
-/**
-* @} End of "addtogroup a9_time_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/51/616fcb585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/51/616fcb585243001d18b399c1eb9b3628
deleted file mode 100644
index e40988e..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/51/616fcb585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,366 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_spinlock.c
-*
-* Implements a spinlocking mechanism using ARM load-exclusive and
-* store-exclusive instructions.
-*
-* spinlocks in baremetal world are useful mainly for AMP kind of use cases
-* where different applications run in different CPUs in a CPU cluster and
-* they have a common resource to work with.
-* A simple yet common example is:
-* R5-0 and R5-1 have separate applications and at runtime they try to access a
-* shared register space (GIC) or shared memory space. Mutual exclusion is
-* really needed for such use cases.
-* Similar use case applies for Zynq CortexA9-0 and CortesA9-1.
-*
-* The spinlock mechanism provided with this file is very simple to cater to
-* baremetal world requirements.
-*
-* A) Unlike OS type of use cases, at any point of time, only a single lock
-* can be used. There is no way in BM world we can support multiple locks
-* at the same time.
-* B) The spinlocking is available for ARM v7 (Cortex-R5 and Cortex-A9).
-* C) Users need to provide a lock (essentially a shared address), and a flag
-* (also a shared address) for spinlocking to work. These shared addresses
-* must be agreed upon by apps running on both CPUs. Needless to say,
-* the linker scripts must change accordingly so that apps running on both
-* CPUs can have a shared DDR region from which address can be used for
-* spinlocking.
-* D) The address that is used for spinlocking and the address that is used
-* as flag address must be in a memory region that is strongly-ordered
-* or device memory.
-* E) Like any similar standard use cases, one application running in any
-* of the CPUs must create the spinlock address. It is advisable that the
-* the same application must destroy or release the spinlock address,
-* though nothing stops the other CPU in destroying and releasing the
-* spinlock addresses. There has to be understanding between applications
-* running on both the CPUs to ensure that correct ordering is followed.
-* Once a spinlock is released, it spinlock APIs cannot be used anymore.
-* F) Once a spinlock address is created it can be used any number of times
-* to protect critical sections as long as a certain set of rules are
-* followed and a certain set of sequences are followed. More about the
-* sequences later in this description.
-* G) To re-iterate, the spinlocking mechanism provided through this file is
-* pretty rudimentary. Users can always improvise. The use case that
-* the whole mechanism is trying to solve is: common register space
-* being accesses in an AMP scenario by independent applications running
-* at multiple CPUs.
-*
-* The usage of APIs provided in this file are summarized below.
-* A) Applications running at both the CPUs ensure that they allocate shared
-* memory space to be used for locking and flag maintenance.
-* B) The memory allocated as shared should be of minimum size 1 MB. This
-* limitation is because the way translation tables/memory map is setup
-* for R5 or A9. In future, this limitation can be brought down 4 KB.
-* C) The spinlock and the flag address must be uncached. Users need to c
-* all Xilinx provided API Xil_SetTlbAttributes to mark the shared
-* 1 MB memory space as strongly ordered or device memory.
-* D) Both the applications must call the API Xil_InitializeSpinLock with
-* the spinlock address, flag address and flag value to be used. Currently
-* only one flag value is supported (i.e. XIL_SPINLOCK_ENABLE with
-* a value of 1).
-* Only if the Xil_InitializeSpinLock returns success, should they
-* proceed to use Xil_SpinLock and Xil_SpinUnlock.
-* F) Afterwards applications can start using the APIs Xil_SpinLock() and
-* Xil_SpinUnlock() to protect the critical sections.
-* G) It is highly suggested to use Xil_IsSpinLockEnabled() as a check
-* before using Xil_SpinLock() or Xil_SpinUnlock(). Refer to the code
-* snippet below.
-* H) If spinlock is no more needed by an application, they can use the API
-* Xil_ReleaseSpinLock().
-* I) Once a spinlock is created it can be used as many numbers of time as
-* needed.
-*
-* A typical code snippet with R5 as an example and lock address falling
-* in the 1 MB memory region (0x300000 to 0x400000) is given below.
-*
-* Code snippet for R5-0 (that runs first):
-* int main()
-* {
-* u32 *sharedlockaddr = (int *)0x300008;
-* u32 *sharedlockflagaddr = int *)0x30000C;
-* Xil_SetTlbAttributes(0x300000,STRONG_ORDERD_SHARED | PRIV_RW_USER_RW);
-* Xil_InitializeSpinLock((UINTPTR)sharedlockaddr,(UINTPTR)sharedlockflagaddr,
-* XIL_SPINLOCK_ENABLE);
-* ....
-* ....
-* if (Xil_IsSpinLockEnabled())
-* Xil_SpinLock();
-* // Critical Section
-* ....
-* ....
-* if (Xil_IsSpinLockEnabled())
-* Xil_SpinUnlock();
-* .....
-* .....
-* Xil_ReleaseSpinLock();
-* } // End of main
-*
-* * Code snippet for R5-1 (that runs second):
-* int main()
-* {
-* u32 *sharedlockaddr = (int *)0x300008;
-* u32 *sharedlockflagaddr = int *)0x30000C;
-* Xil_SetTlbAttributes(0x300000,STRONG_ORDERD_SHARED | PRIV_RW_USER_RW);
-* Xil_InitializeSpinLock((UINTPTR)sharedlockaddr,(UINTPTR)sharedlockflagaddr,
-* XIL_SPINLOCK_ENABLE);
-* ....
-* if (Xil_IsSpinLockEnabled())
-* Xil_SpinLock();
-* // Critical Section
-* ....
-* ....
-* if (Xil_IsSpinLockEnabled())
-* Xil_SpinUnlock();
-* .....
-* .....
-* Xil_ReleaseSpinLock();
-* } // End of main
-*
-* Xil_SpinLock() and Xil_SpinLock() return XST_FAILURE if the spinlock
-* is initialized. Instead of calling Xil_IsSpinLockEnabled before using
-* Xil_SpinLock() or Xil_SpinLock(), users can also check the return
-* value of Xil_SpinLock and Xil_SpinLock. If a lock is not initialized,
-* Xil_SpinLock will just return failure and not perform load-exclusive
-* operations.
-*
-* Guidelines on when to use the spinlocking mechanism in Xilinx baremetal
-* environment:
-* A) Spinlocking mechanism can only be used for Cortex-R5s (split mode)
-* and Cortex-A9s (Zynq).
-* B) In Cortex-R5 split mode or Cortex-A9 cluster, applications running on
-* both the CPUs, by design should never be sharing the same peripheral.
-* It is impossible to support such use cases reliably.
-* Hence none of the peripheral drivers (except GIC driver) have
-* spinlocking support added into their APIs.
-* C) GIC register space is shared by both the CPUs (R5 split mode, A9s).
-* The GIC driver APIs have spinlocking mechanism added to the relevant
-* APIs. Users need to follow the guidelines stated earlier to enable
-* the spinlocks and use them.
-* It is really advisable to use spinlock mechanism for use cases where
-* applications running on multiple CPUs can simultaneously access
-* GIC register space through driver APIs.
-* D) The spinlock mechanism can be used to protect any critical region
-* implemented through shared memory space.
-*
-* IMPORTANT NOTE: Circular spinlocks are not allowed (as expected).
-* Use case where an application calls Xil_SpinLock back to back without
-* calling Xil_SpinUnlock in between will/may result in a deadlock
-* condition.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 7.5 asa 02/23/21 First release
-* 7.5 asa 04/28/21 Fixed bug Xil_IsSpinLockEnabled to avoid
-* dereferencing to address zero.
-*
-*
-******************************************************************************/
-
-
-/***************************** Include Files ********************************/
-#if !defined (__aarch64__) && defined(__GNUC__) && !defined(__clang__)
-#include "xil_spinlock.h"
-
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-
-/************************** Variable Definitions ****************************/
-static UINTPTR Xil_Spinlock_Addr = 0x0;
-static UINTPTR Xil_Spinlock_Flag_Addr = 0x0;
-
-/************************** Function Prototypes *****************************/
-
-/****************************************************************************/
-/**
-*
-* @brief Used at the beginning of a critical section. This API takes the
-* lock using load-exclusive and store-exclusive operations. In
-* case the lock is not available (being held by an application
-* running at the other CPU and doing operations inside the
-* critical section, the control will never go out from the API
-* till the other CPU releases the lock.
-*
-* @param None.
-*
-* @return XST_FAILURE: If spinlock is not properly initialized.
-* XST_SUCCESS: If the lock was successfully obtained.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 Xil_SpinLock(void)
-{
- UINTPTR lockaddr = Xil_Spinlock_Addr;
- u32 LockTempVar;
-
- if (Xil_Spinlock_Addr == 0) {
- return XST_FAILURE;
- }
-
- __asm__ __volatile__(
- "1: ldrex %0, [%1] \n"
- " teq %0, %3 \n"
- " strexeq %0, %2, [%1] \n"
- " teqeq %0, #0 \n"
- " bne 1b \n"
- " dmb \n"
- : "=&r" (LockTempVar)
- : "r" (lockaddr), "r"(XIL_SPINLOCK_LOCKVAL), "r"(XIL_SPINLOCK_RESETVAL)
- : "cc");
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* @brief Used to release a lock previously held by calling Xil_SpinLock.
-*
-* @param None.
-*
-* @return XST_FAILURE: If spinlock is not properly initialized.
-* XST_SUCCESS: If the lock was successfully obtained.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 Xil_SpinUnlock(void)
-{
- UINTPTR lockaddr = Xil_Spinlock_Addr;
-
- if (Xil_Spinlock_Addr == 0) {
- return XST_FAILURE;
- }
- __asm__ __volatile__(
- "dmb \n"
- "str %1, [%0] \n"
- :
- : "r" (lockaddr), "r" (XIL_SPINLOCK_RESETVAL)
- : "cc");
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-* @brief Used to initialize a spinlock.
-*
-* @param lockaddr: Address of the lock variable. The address must be in
-* a shared memory region.
-* lockflagaddr: Address of the flag variable. The address must be
-* in a shared memory region.
-* lockflag: The value of the flag. Currently only one value
-* is supported, which is XIL_SPINLOCK_ENABLE.
-*
-* @return XST_SUCCESS, if the initialization succeeded.
-* XST_FAILURE, if the initialization failed
-*
-* @note None.
-*
-*****************************************************************************/
-u32 Xil_InitializeSpinLock(UINTPTR lockaddr, UINTPTR lockflagaddr,
- u32 lockflag)
-{
- if (Xil_Spinlock_Flag_Addr == 0) {
- Xil_Spinlock_Flag_Addr = lockflagaddr;
- if (*(u32 *)Xil_Spinlock_Flag_Addr == XIL_SPINLOCK_ENABLED) {
- /*
- * spinlock is already initialized by one of the CPUs, just update
- * the local variable Xil_Spinlock_Addr with the passed address
- * and dont write to the lock value as it might be currently
- * getting used.
- */
- /*
- * Ensure to update the global variable Xil_Spinlock_Addr only
- * if it is zero. A non-zero value may mean that there is something
- * wrong.
- */
- if (Xil_Spinlock_Addr == 0) {
- Xil_Spinlock_Addr = lockaddr;
- } else {
- /*
- * May be spinlock is already initialized and the user has not
- * called Xil_ReleaseSpinLock before calling Xil_InitializeSpinLock.
- */
- return XST_FAILURE;
- }
- } else {
- /* All good, do the necessary initializations */
- Xil_Spinlock_Addr = lockaddr;
- *(u32 *)(Xil_Spinlock_Addr) = XIL_SPINLOCK_RESETVAL;
- *(u32 *)(Xil_Spinlock_Flag_Addr) = lockflag;
- }
- return XST_SUCCESS;
- } else {
- /*
- * Most probably spinlock is already initialized and the user has not
- * called Xil_ReleaseSpinLock before calling Xil_InitializeSpinLock.
- */
- return XST_FAILURE;
- }
-}
-
-
-/****************************************************************************/
-/**
-* @brief Used to release the spinlock. Typically called by the application
-* once spinlock feature is no more required.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void Xil_ReleaseSpinLock(void)
-{
- Xil_Spinlock_Addr = 0;
- Xil_Spinlock_Flag_Addr = 0;
-}
-
-/****************************************************************************/
-/**
-* @brief Used to know if the spinlock feature has been enabled. To ensure
-* that spinlock feature does not break use cases where lock is
-* not initialized, the application must call this API first to know
-* if it can use spinlock. If this API returns non-zero value, an
-* application should then use Xil_SpinLock or Xil_SpinUnlock.
-*
-* @param None
-*
-* @return Non-zero, if spinlock is already initialized and can be used.
-* Zero, if spinlock is not initialized.
-*
-* @note
-*
-*****************************************************************************/
-u32 Xil_IsSpinLockEnabled(void)
-{
- u32 retVal = FALSE;
-
- if (Xil_Spinlock_Flag_Addr != 0) {
- if (*(u32 *)(Xil_Spinlock_Flag_Addr) == XIL_SPINLOCK_ENABLED) {
- retVal = TRUE;
- }
- }
- return retVal;
-}
-#endif /* !(__aarch64__) && (__GNUC__) && !(__clang__)*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/51/71b86c595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/51/71b86c595243001d18b399c1eb9b3628
deleted file mode 100644
index 0014826..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/51/71b86c595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1088 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file microblaze_selftest.S
-*
-* @addtogroup microblaze_pseudo_asm_macro
-* @{
-*
microblaze_selftest.S
-*
-* This routine provides an internal self test of the MicroBlaze processor. The
-* register file and all integer execution units are tested. Long instructions
-* are also included if 64-bit mode is enabled. Currently FPU, MMU, BTC, data
-* and instruction caches, and GET/PUT instructions are not covered.
-*
-* The routine is not reentrant, and disables interrupts and exceptions during
-* execution. This can result in increased interrupt latency.
-*
-* Call this routine regularly from a timer interrupt.
-*
-* When called from C code the routine should be declared as:
-* extern int microblaze_selftest();
-*
-* @param None.
-*
-* @return
-* - 0 if self test was successful
-* - Error code if self test failed:
-* Bit 0: Register file test failed
-* Bit 1: ALU test failed
-* Bit 2: Shift unit test failed
-* Bit 3: Load-store test failed
-* Bit 4: Branch instruction test failed
-* Bit 5: Barrel shifter test failed
-* Bit 6: Multiplier test failed
-* Bit 7: Integer divide test failed
-* Bit 8: Pattern compare test failed
-* Bit 9: MSR instruction test failed
-* Bit 10: Reorder instruction test failed
-*
-* @note
-* This routine assumes that the processor is in privileged mode when it is
-* called, if the MMU is enabled.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/29/14 First release
-* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
-* ARM processors
-* 7.20 har 01/03/20 Added Xil_SecureOut32 for avoiding blindwrite for
-* CR-1049218
-* 7.30 kpt 09/21/20 Moved Xil_EndianSwap16 and Xil_EndianSwap32 to
-* xil_io.h and made them as static inline
-* am 10/13/20 Changed the return type of Xil_SecureOut32 function
-* from u32 to int
-* 7.50 dp 02/12/21 Fix compilation error in Xil_EndianSwap32() that occur
-* when -Werror=conversion compiler flag is enabled
-* 7.5 mus 05/17/21 Update the functions with comments. It fixes CR#1067739.
-*
-*
-******************************************************************************/
-
-#ifndef XIL_IO_H /* prevent circular inclusions */
-#define XIL_IO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_printf.h"
-#include "xstatus.h"
-
-#if defined (__MICROBLAZE__)
-#include "mb_interface.h"
-#else
-#include "xpseudo_asm.h"
-#endif
-
-/************************** Function Prototypes ******************************/
-#ifdef ENABLE_SAFETY
-extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
-#endif
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#if defined __GNUC__
-#if defined (__MICROBLAZE__)
-# define INST_SYNC mbar(0)
-# define DATA_SYNC mbar(1)
-# else
-# define SYNCHRONIZE_IO dmb()
-# define INST_SYNC isb()
-# define DATA_SYNC dsb()
-# endif
-#else
-# define SYNCHRONIZE_IO
-# define INST_SYNC
-# define DATA_SYNC
-# define INST_SYNC
-# define DATA_SYNC
-#endif
-
-#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
-#define INLINE inline
-#else
-#define INLINE __inline
-#endif
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading
-* from the specified address and returning the 8 bit Value read from
-* that address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 8 bit Value read from the specified input address.
-
-*
-******************************************************************************/
-static INLINE u8 Xil_In8(UINTPTR Addr)
-{
- return *(volatile u8 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading from
-* the specified address and returning the 16 bit Value read from that
-* address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 16 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u16 Xil_In16(UINTPTR Addr)
-{
- return *(volatile u16 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by
-* reading from the specified address and returning the 32 bit Value
-* read from that address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 32 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u32 Xil_In32(UINTPTR Addr)
-{
- return *(volatile u32 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading the
-* 64 bit Value read from that address.
-*
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 64 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u64 Xil_In64(UINTPTR Addr)
-{
- return *(volatile u64 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for an memory location by
-* writing the 8 bit Value to the the specified address.
-*
-* @param Addr: contains the address to perform the output operation
-* @param Value: contains the 8 bit Value to be written at the specified
-* address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
-{
- /* write 8 bit value to specified address */
- volatile u8 *LocalAddr = (volatile u8 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 16 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains the Value to be written at the specified address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
-{
- /* write 16 bit value to specified address */
- volatile u16 *LocalAddr = (volatile u16 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 32 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains the 32 bit Value to be written at the specified
-* address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
-{
- /* write 32 bit value to specified address */
-#ifndef ENABLE_SAFETY
- volatile u32 *LocalAddr = (volatile u32 *)Addr;
- *LocalAddr = Value;
-#else
- XStl_RegUpdate(Addr, Value);
-#endif
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 64 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains 64 bit Value to be written at the specified address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
-{
- /* write 64 bit value to specified address */
- volatile u64 *LocalAddr = (volatile u64 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
- *
- * @brief Performs an output operation for a memory location by writing the
- * 32 bit Value to the the specified address and then reading it
- * back to verify the value written in the register.
- *
- * @param Addr contains the address to perform the output operation
- * @param Value contains 32 bit Value to be written at the specified address
- *
- * @return Returns Status
- * - XST_SUCCESS on success
- * - XST_FAILURE on failure
- *
- *****************************************************************************/
-static INLINE int Xil_SecureOut32(UINTPTR Addr, u32 Value)
-{
- int Status = XST_FAILURE;
- u32 ReadReg;
- u32 ReadRegTemp;
-
- /* writing 32 bit value to specified address */
- Xil_Out32(Addr, Value);
-
- /* verify value written to specified address with multiple reads */
- ReadReg = Xil_In32(Addr);
- ReadRegTemp = Xil_In32(Addr);
-
- if( (ReadReg == Value) && (ReadRegTemp == Value) ) {
- Status = XST_SUCCESS;
- }
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a 16-bit endian conversion.
-*
-* @param Data: 16 bit value to be converted
-*
-* @return 16 bit Data with converted endianness
-*
-******************************************************************************/
-static INLINE __attribute__((always_inline)) u16 Xil_EndianSwap16(u16 Data)
-{
- return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a 32-bit endian conversion.
-*
-* @param Data: 32 bit value to be converted
-*
-* @return 32 bit data with converted endianness
-*
-******************************************************************************/
-static INLINE __attribute__((always_inline)) u32 Xil_EndianSwap32(u32 Data)
-{
- u16 LoWord;
- u16 HiWord;
-
- /* get each of the half words from the 32 bit word */
-
- LoWord = (u16) (Data & 0x0000FFFFU);
- HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
-
- /* byte swap each of the 16 bit half words */
-
- LoWord = (u16)(((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
- HiWord = (u16)(((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
-
- /* swap the half words before returning the value */
-
- return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-# define Xil_In16LE Xil_In16
-# define Xil_In32LE Xil_In32
-# define Xil_Out16LE Xil_Out16
-# define Xil_Out32LE Xil_Out32
-# define Xil_Htons Xil_EndianSwap16
-# define Xil_Htonl Xil_EndianSwap32
-# define Xil_Ntohs Xil_EndianSwap16
-# define Xil_Ntohl Xil_EndianSwap32
-# else
-# define Xil_In16BE Xil_In16
-# define Xil_In32BE Xil_In32
-# define Xil_Out16BE Xil_Out16
-# define Xil_Out32BE Xil_Out32
-# define Xil_Htons(Data) (Data)
-# define Xil_Htonl(Data) (Data)
-# define Xil_Ntohs(Data) (Data)
-# define Xil_Ntohl(Data) (Data)
-#endif
-#else
-# define Xil_In16LE Xil_In16
-# define Xil_In32LE Xil_In32
-# define Xil_Out16LE Xil_Out16
-# define Xil_Out32LE Xil_Out32
-# define Xil_Htons Xil_EndianSwap16
-# define Xil_Htonl Xil_EndianSwap32
-# define Xil_Ntohs Xil_EndianSwap16
-# define Xil_Ntohl Xil_EndianSwap32
-#endif
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE u16 Xil_In16BE(UINTPTR Addr)
-#else
-static INLINE u16 Xil_In16LE(UINTPTR Addr)
-#endif
-#else
-static INLINE u16 Xil_In16BE(UINTPTR Addr)
-#endif
-{
- u16 value = Xil_In16(Addr);
- return Xil_EndianSwap16(value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE u32 Xil_In32BE(UINTPTR Addr)
-#else
-static INLINE u32 Xil_In32LE(UINTPTR Addr)
-#endif
-#else
-static INLINE u32 Xil_In32BE(UINTPTR Addr)
-#endif
-{
- u32 value = Xil_In32(Addr);
- return Xil_EndianSwap32(value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
-#else
-static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
-#endif
-#else
-static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
-#endif
-{
- Value = Xil_EndianSwap16(Value);
- Xil_Out16(Addr, Value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
-#else
-static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
-#endif
-#else
-static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
-#endif
-{
- Value = Xil_EndianSwap32(Value);
- Xil_Out32(Addr, Value);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_io_interfacing_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/52/126bcc565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/52/126bcc565243001d18b399c1eb9b3628
deleted file mode 100644
index 125fe7f..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/52/126bcc565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,202 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file translation_table.S
-*
-* @addtogroup a9_boot_code
-* @{
-*
translation_table.S
-* The translation_table.S contains a static page table required by MMU for
-* cortex-A9. This translation table is flat mapped (input address = output
-* address) with default memory attributes defined for zynq architecture. It
-* utilizes short descriptor translation table format with each section defining
-* 1 MB of memory.
-*
-* The overview of translation table memory attributes is described below.
-*
-*| | Memory Range | Definition in Translation Table |
-*|-----------------------|-------------------------|-----------------------------------|
-*| DDR | 0x00000000 - 0x3FFFFFFF | Normal write-back Cacheable |
-*| PL | 0x40000000 - 0xBFFFFFFF | Strongly Ordered |
-*| Reserved | 0xC0000000 - 0xDFFFFFFF | Unassigned |
-*| Memory mapped devices | 0xE0000000 - 0xE02FFFFF | Device Memory |
-*| Reserved | 0xE0300000 - 0xE0FFFFFF | Unassigned |
-*| NAND, NOR | 0xE1000000 - 0xE3FFFFFF | Device memory |
-*| SRAM | 0xE4000000 - 0xE5FFFFFF | Normal write-back Cacheable |
-*| Reserved | 0xE6000000 - 0xF7FFFFFF | Unassigned |
-*| AMBA APB Peripherals | 0xF8000000 - 0xF8FFFFFF | Device Memory |
-*| Reserved | 0xF9000000 - 0xFBFFFFFF | Unassigned |
-*| Linear QSPI - XIP | 0xFC000000 - 0xFDFFFFFF | Normal write-through cacheable |
-*| Reserved | 0xFE000000 - 0xFFEFFFFF | Unassigned |
-*| OCM | 0xFFF00000 - 0xFFFFFFFF | Normal inner write-back cacheable |
-*
-* For region 0x00000000 - 0x3FFFFFFF, a system where DDR is less than 1 GB,
-* region after DDR and before PL is marked as undefined/reserved in translation
-* table. In 0xF8000000 - 0xF8FFFFFF, 0xF8000C00 - 0xF8000FFF, 0xF8010000 -
-* 0xF88FFFFF and 0xF8F03000 to 0xF8FFFFFF are reserved but due to granual size
-* of 1 MB, it is not possible to define separate regions for them. For region
-* 0xFFF00000 - 0xFFFFFFFF, 0xFFF00000 to 0xFFFB0000 is reserved but due to 1MB
-* granual size, it is not possible to define separate region for it.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 10/20/09 Initial version
-* 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
-* 3.07a sgd 07/05/2012 Configuring device address spaces as shareable device
-* instead of strongly-ordered.
-* 3.07a asa 07/17/2012 Changed the property of the ".mmu_tbl" section.
-* 4.2 pkp 09/02/2014 added entries for 0xfe000000 to 0xffefffff as reserved
-* and 0xe0000000 - 0xe1ffffff is broken down into
-* 0xe0000000 - 0xe02fffff (memory mapped divides)
-* 0xe0300000 - 0xe0ffffff (reserved) and
-* 0xe1000000 - 0xe1ffffff (NAND)
-* 5.2 pkp 06/08/2015 put a check for XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm
-* if DDR is present or not and accordingly generate the
-* translation table
-* 6.1 pkp 07/11/2016 Corrected comments for memory attributes
-* 6.8 mus 07/12/2018 Mark DDR memory as inner cacheable, if BSP is built
-* with the USE_AMP flag.
-*
-*
-*
-******************************************************************************/
-#include "xparameters.h"
- .globl MMUTable
-
- .section .mmu_tbl,"a"
-
-MMUTable:
- /* Each table entry occupies one 32-bit word and there are
- * 4096 entries, so the entire table takes up 16KB.
- * Each entry covers a 1MB section.
- */
-.set SECT, 0
-
-#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR
-.set DDR_START, XPAR_PS7_DDR_0_S_AXI_BASEADDR
-.set DDR_END, XPAR_PS7_DDR_0_S_AXI_HIGHADDR
-.set DDR_SIZE, (DDR_END - DDR_START)+1
-.set DDR_REG, DDR_SIZE/0x100000
-#else
-.set DDR_REG, 0
-#endif
-
-.set UNDEF_REG, 0x3FF - DDR_REG
-
-#ifndef USE_AMP
- /*0x00000000 - 0x00100000 (inner and outer cacheable )*/
-.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
-#else
- /*0x00000000 - 0x00100000 (inner cacheable )*/
-.word SECT + 0x14de6 /* S=b1 TEX=b100 AP=b11, Domain=b1111, C=b0, B=b1 */
-#endif
-.set SECT, SECT+0x100000
-
-.rept DDR_REG /* (DDR Cacheable) */
-.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept UNDEF_REG /* (unassigned/reserved).
- * Generates a translation fault if accessed */
-.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-
-.rept 0x0400 /* 0x40000000 - 0x7fffffff (FPGA slave0) */
-.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0400 /* 0x80000000 - 0xbfffffff (FPGA slave1) */
-.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0200 /* 0xc0000000 - 0xdfffffff (unassigned/reserved).
- * Generates a translation fault if accessed */
-.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x003 /* 0xe0000000 - 0xe02fffff (Memory mapped devices)
- * UART/USB/IIC/SPI/CAN/GEM/GPIO/QSPI/SD/NAND */
-.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0D /* 0xe0300000 - 0xe0ffffff (unassigned/reserved).
- * Generates a translation fault if accessed */
-.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0010 /* 0xe1000000 - 0xe1ffffff (NAND) */
-.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0020 /* 0xe2000000 - 0xe3ffffff (NOR) */
-.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0020 /* 0xe4000000 - 0xe5ffffff (SRAM) */
-.word SECT + 0xc0e /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0120 /* 0xe6000000 - 0xf7ffffff (unassigned/reserved).
- * Generates a translation fault if accessed */
-.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-/* 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and
- 0xf8f03000 to 0xf8ffffff are reserved but due to granual size of
- 1MB, it is not possible to define separate regions for them */
-
-.rept 0x0010 /* 0xf8000000 - 0xf8ffffff (AMBA APB Peripherals) */
-
-.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0030 /* 0xf9000000 - 0xfbffffff (unassigned/reserved).
- * Generates a translation fault if accessed */
-.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0020 /* 0xfc000000 - 0xfdffffff (Linear QSPI - XIP) */
-.word SECT + 0xc0a /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x001F /* 0xfe000000 - 0xffefffff (unassigned/reserved).
- * Generates a translation fault if accessed */
-.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-/* 0xfff00000 to 0xfffb0000 is reserved but due to granual size of
- 1MB, it is not possible to define separate region for it
-
- 0xfff00000 - 0xffffffff
- 256K OCM when mapped to high address space
- inner-cacheable */
-.word SECT + 0x4c0e /* S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 */
-.set SECT, SECT+0x100000
-
-.end
-/**
-* @} End of "addtogroup a9_boot_code".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/52/40b7b2585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/52/40b7b2585243001d18b399c1eb9b3628
deleted file mode 100644
index 88cb8db..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/52/40b7b2585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,35 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence);
-}
-#endif
-/*
- * lseek -- Since a serial port is non-seekable, we return an error.
- */
-__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence)
-{
- (void)fd;
- (void)offset;
- (void)whence;
- errno = ESPIPE;
- return ((off_t)-1);
-}
-
-__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence)
-{
- (void)fd;
- (void)offset;
- (void)whence;
- errno = ESPIPE;
- return ((off_t)-1);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/52/5041ff535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/52/5041ff535243001d18b399c1eb9b3628
deleted file mode 100644
index fdec0e9..0000000
Binary files a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/52/5041ff535243001d18b399c1eb9b3628 and /dev/null differ
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/52/81395e595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/52/81395e595243001d18b399c1eb9b3628
deleted file mode 100644
index 069dad9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/52/81395e595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,36 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file microblaze_exceptions_g.h
-*
-* This file contains the exception handling information for the MicroBlaze
-* processor. This file is usually generated by LibGen.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Date Changes
-* ----- -------- -----------------------------------------------
-* 1.00a 06/24/04 First release
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00b kpc 03/07/13 First release.
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */
-#define XIL_MISC_RESET_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-#define XDDRC_CTRL_BASEADDR 0xF8006000U
-#define XSLCR_BASEADDR 0xF8000000U
-/**< OCM configuration register */
-#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U)
-/**< SLCR unlock register */
-#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U)
-/**< SLCR GEM0 rx clock control register */
-#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U)
-/**< SLCR GEM1 rx clock control register */
-#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU)
-/**< SLCR GEM0 clock control register */
-#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U)
-/**< SLCR GEM1 clock control register */
-#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U)
-/**< SLCR SMC clock control register */
-#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U)
-/**< SLCR GEM reset control register */
-#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)
-/**< SLCR USB0 clock control register */
-#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U)
-/**< SLCR USB1 clock control register */
-#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U)
-/**< SLCR USB1 reset control register */
-#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)
-/**< SLCR SMC reset control register */
-#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)
-/**< SLCR Level shifter enable register */
-#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U)
-/**< SLCR ARM pll control register */
-#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U)
-/**< SLCR DDR pll control register */
-#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U)
-/**< SLCR IO pll control register */
-#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U)
-/**< SLCR ARM pll configuration register */
-#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U)
-/**< SLCR DDR pll configuration register */
-#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U)
-/**< SLCR IO pll configuration register */
-#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U)
-/**< SLCR ARM clock control register */
-#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U)
-/**< SLCR DDR clock control register */
-#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U)
-/**< SLCR MIO pin address register */
-#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U)
-/**< SLCR DMAC reset control address register */
-#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU)
-/**< SLCR USB reset control address register */
-/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/
-/**< SLCR GEM reset control address register */
-/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/
-/**< SLCR SDIO reset control address register */
-#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U)
-/**< SLCR SPI reset control address register */
-#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU)
-/**< SLCR CAN reset control address register */
-#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U)
-/**< SLCR I2C reset control address register */
-#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U)
-/**< SLCR UART reset control address register */
-#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U)
-/**< SLCR GPIO reset control address register */
-#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU)
-/**< SLCR LQSPI reset control address register */
-#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U)
-/**< SLCR SMC reset control address register */
-/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/
-/**< SLCR OCM reset control address register */
-#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U)
-
-/**< SMC mem controller clear config register */
-#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU
-/**< SMC idlecount configuration register */
-#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U
-#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U
-/**< SMC ECC configuration register */
-#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U
-/**< SMC ECC command 1 register */
-#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U
-/**< SMC ECC command 2 register */
-#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U
-
-/**< SLCR unlock code */
-#define XSLCR_UNLOCK_CODE 0x0000DF0DU
-
-/**< SMC mem clear configuration mask */
-#define XSMC_MEMC_CLR_CONFIG_MASK 0x0000005FU
-/**< SMC ECC memconfig 1 reset value */
-#define XSMC_ECC_MEMCFG1_RESET_VAL 0x00000043U
-/**< SMC ECC memcommand 1 reset value */
-#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U
-/**< SMC ECC memcommand 2 reset value */
-#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U
-
-/**< DDR controller reset bit mask */
-#define XDDRPS_CTRL_RESET_MASK 0x00000001U
-/**< SLCR OCM configuration reset value*/
-#define XSLCR_OCM_CFG_RESETVAL 0x00000008U
-/**< SLCR OCM bank selection mask*/
-#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU
-/**< SLCR level shifter enable mask*/
-#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU
-
-/**< SLCR PLL register reset values */
-#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U
-#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U
-#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U
-#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U
-#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U
-#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U
-#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U
-#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U
-
-/**< SLCR MIO register default values */
-#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U
-#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U
-
-/**< SLCR Reset control registers default values */
-#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U
-#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U
-#define XSLCR_USB_RST_CTRL_VAL 0x00000003U
-#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U
-#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU
-#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU
-#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U
-#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U
-#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U
-#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U
-#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U
-#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U
-
-/**
- *@endcond
- */
-
-/**************************** Type Definitions *******************************/
-
-/* the following data type is used to hold a null terminated version string
- * consisting of the following format, "X.YYX"
- */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-/*
- * Performs reset operation to the ddr interface
- */
-void XDdr_ResetHw(void);
-/*
- * Map the ocm region to post bootrom state
- */
-void XOcm_Remap(void);
-/*
- * Performs the smc interface reset
- */
-void XSmc_ResetHw(u32 BaseAddress);
-/*
- * updates the MIO registers with reset values
- */
-void XSlcr_MioWriteResetValues(void);
-/*
- * updates the PLL and clock registers with reset values
- */
-void XSlcr_PllWriteResetValues(void);
-/*
- * Disables the level shifters
- */
-void XSlcr_DisableLevelShifters(void);
-/*
- * provides softreset to the GPIO interface
- */
-void XSlcr_GpioPsReset(void);
-/*
- * provides softreset to the DMA interface
- */
-void XSlcr_DmaPsReset(void);
-/*
- * provides softreset to the SMC interface
- */
-void XSlcr_SmcPsReset(void);
-/*
- * provides softreset to the CAN interface
- */
-void XSlcr_CanPsReset(void);
-/*
- * provides softreset to the Uart interface
- */
-void XSlcr_UartPsReset(void);
-/*
- * provides softreset to the I2C interface
- */
-void XSlcr_I2cPsReset(void);
-/*
- * provides softreset to the SPI interface
- */
-void XSlcr_SpiPsReset(void);
-/*
- * provides softreset to the QSPI interface
- */
-void XSlcr_QspiPsReset(void);
-/*
- * provides softreset to the USB interface
- */
-void XSlcr_UsbPsReset(void);
-/*
- * provides softreset to the GEM interface
- */
-void XSlcr_EmacPsReset(void);
-/*
- * provides softreset to the OCM interface
- */
-void XSlcr_OcmReset(void);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_MISC_RESET_H */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/52/a0e14f595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/52/a0e14f595243001d18b399c1eb9b3628
deleted file mode 100644
index f673ff3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/52/a0e14f595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,34 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#include
-#include
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) int _kill(pid_t pid, int sig);
-}
-#endif
-
-/*
- * kill -- go out via exit...
- */
-
-__attribute__((weak)) int kill(pid_t pid, int sig)
-{
- if(pid == 1) {
- _exit(sig);
- }
- return 0;
-}
-
-__attribute__((weak)) int _kill(pid_t pid, int sig)
-{
- if(pid == 1) {
- _exit(sig);
- }
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/53/02905a595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/53/02905a595243001d18b399c1eb9b3628
deleted file mode 100644
index 62b8cf7..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/53/02905a595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,29 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-* Enable exceptions on microblaze.
-*
-*
-******************************************************************************/
-
-#include "xparameters.h"
-
- .text
- .globl microblaze_enable_exceptions
- .ent microblaze_enable_exceptions
- .align 2
-microblaze_enable_exceptions:
-#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
- rtsd r15, 8;
- msrset r0, 0x100
-#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- mfs r4, rmsr;
- ori r4, r4, 0x100; /* Turn ON the EE bit */
- mts rmsr, r4;
- rtsd r15, 8;
- nop;
-#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
-.end microblaze_enable_exceptions
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/53/7006dd595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/53/7006dd595243001d18b399c1eb9b3628
deleted file mode 100644
index e8eb9ee..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/53/7006dd595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1813 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xadcps.c
-* @addtogroup xadcps_v2_6
-* @{
-*
-* This file contains the driver API functions that can be used to access
-* the XADC device.
-*
-* Refer to the xadcps.h header file for more information about this driver.
-*
-* @note None.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
-* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
-* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
-* to fix CR #693371
-* 2.1 bss 08/05/14 Modified Assert for XAdcPs_SetSingleChParams to fix
-* CR #807563.
-* 2.2 bss 04/27/14 Modified to use correct Device Config base address
-* (CR#854437).
-* 2.3 mn 07/09/18 Fix Doxygen warning
-* 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors.
-*
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xadcps.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Function Prototypes *****************************/
-
-void XAdcPs_WriteInternalReg(XAdcPs *InstancePtr, u32 RegOffset, u32 Data);
-u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset);
-
-
-/************************** Variable Definitions ****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* This function initializes a specific XAdcPs device/instance. This function
-* must be called prior to using the XADC device.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param ConfigPtr points to the XAdcPs device configuration structure.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. If the address translation is not used then the
-* physical address is passed.
-* Unexpected errors may occur if the address mapping is changed
-* after this function is invoked.
-*
-* @return
-* - XST_SUCCESS if successful.
-*
-* @note The user needs to first call the XAdcPs_LookupConfig() API
-* which returns the Configuration structure pointer which is
-* passed as a parameter to the XAdcPs_CfgInitialize() API.
-*
-******************************************************************************/
-int XAdcPs_CfgInitialize(XAdcPs *InstancePtr, XAdcPs_Config *ConfigPtr,
- u32 EffectiveAddr)
-{
-
- u32 RegValue;
- /*
- * Assert the input arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
-
-
- /*
- * Set the values read from the device config and the base address.
- */
- InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
- InstancePtr->Config.BaseAddress = EffectiveAddr;
-
- /* Write Unlock value to Device Config Unlock register */
- XAdcPs_WriteReg(XPAR_XDCFG_0_BASEADDR,
- XADCPS_UNLK_OFFSET, XADCPS_UNLK_VALUE);
-
- /* Enable the PS access of xadc and set FIFO thresholds */
-
- RegValue = XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
- XADCPS_CFG_OFFSET);
-
- RegValue = RegValue | XADCPS_CFG_ENABLE_MASK |
- XADCPS_CFG_CFIFOTH_MASK | XADCPS_CFG_DFIFOTH_MASK;
-
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
- XADCPS_CFG_OFFSET, RegValue);
-
- /* Release xadc from reset */
-
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
- XADCPS_MCTL_OFFSET, 0x00);
-
- /*
- * Indicate the instance is now ready to use and
- * initialized without error.
- */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- return XST_SUCCESS;
-}
-
-
-/****************************************************************************/
-/**
-*
-* The functions sets the contents of the Config Register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Data is the 32 bit data to be written to the Register.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_SetConfigRegister(XAdcPs *InstancePtr, u32 Data)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
- XADCPS_CFG_OFFSET, Data);
-
-}
-
-
-/****************************************************************************/
-/**
-*
-* The functions reads the contents of the Config Register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return A 32-bit value representing the contents of the Config Register.
-* Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to
-* interpret the returned value.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XAdcPs_GetConfigRegister(XAdcPs *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Config Register and return the value.
- */
- return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
- XADCPS_CFG_OFFSET);
-}
-
-
-/****************************************************************************/
-/**
-*
-* The functions reads the contents of the Miscellaneous Status Register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return A 32-bit value representing the contents of the Miscellaneous
-* Status Register. Use the XADCPS_MSTS_*_MASK constants defined
-* in xadcps_hw.h to interpret the returned value.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XAdcPs_GetMiscStatus(XAdcPs *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Miscellaneous Status Register and return the value.
- */
- return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
- XADCPS_MSTS_OFFSET);
-}
-
-
-/****************************************************************************/
-/**
-*
-* The functions sets the contents of the Miscellaneous Control register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Data is the 32 bit data to be written to the Register.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_SetMiscCtrlRegister(XAdcPs *InstancePtr, u32 Data)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Write to the Miscellaneous control register Register.
- */
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
- XADCPS_MCTL_OFFSET, Data);
-}
-
-
-/****************************************************************************/
-/**
-*
-* The functions reads the contents of the Miscellaneous control register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return A 32-bit value representing the contents of the Config Register.
-* Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to
-* interpret the returned value.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XAdcPs_GetMiscCtrlRegister(XAdcPs *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Miscellaneous control register and return the value.
- */
- return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
- XADCPS_MCTL_OFFSET);
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This function resets the XADC Hard Macro in the device.
-*
-* @param InstancePtr is a pointer to the Xxadc instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XAdcPs_Reset(XAdcPs *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Generate the reset by Control
- * register and release from reset
- */
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
- XADCPS_MCTL_OFFSET, 0x10);
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
- XADCPS_MCTL_OFFSET, 0x00);
-}
-
-
-/****************************************************************************/
-/**
-*
-* Get the ADC converted data for the specified channel.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Channel is the channel number. Use the XADCPS_CH_* defined in
-* the file xadcps.h.
-* The valid channels are
-* - 0 to 6
-* - 13 to 31
-*
-* @return A 16-bit value representing the ADC converted data for the
-* specified channel. The XADC Monitor/ADC device guarantees
-* a 10 bit resolution for the ADC converted data and data is the
-* 10 MSB bits of the 16 data read from the device.
-*
-* @note The channels 7,8,9 are used for calibration of the device and
-* hence there is no associated data with this channel.
-*
-*****************************************************************************/
-u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel)
-{
-
- u32 RegData;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((Channel <= XADCPS_CH_VBRAM) ||
- ((Channel >= XADCPS_CH_VCCPINT) &&
- (Channel <= XADCPS_CH_AUX_MAX)));
-
- RegData = XAdcPs_ReadInternalReg(InstancePtr,
- (XADCPS_TEMP_OFFSET + (u32)Channel));
- return (u16) RegData;
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the calibration coefficient data for the specified
-* parameter.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param CoeffType specifies the calibration coefficient
-* to be read. Use XADCPS_CALIB_* constants defined in xadcps.h to
-* specify the calibration coefficient to be read.
-*
-* @return A 16-bit value representing the calibration coefficient.
-* The XADC device guarantees a 10 bit resolution for
-* the ADC converted data and data is the 10 MSB bits of the 16
-* data read from the device.
-*
-* @note None.
-*
-*****************************************************************************/
-u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType)
-{
- u32 RegData;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(CoeffType <= XADCPS_CALIB_GAIN_ERROR_COEFF);
-
- /*
- * Read the selected calibration coefficient.
- */
- RegData = XAdcPs_ReadInternalReg(InstancePtr,
- (XADCPS_ADC_A_SUPPLY_CALIB_OFFSET +
- (u32)CoeffType));
- return (u16) RegData;
-}
-
-/****************************************************************************/
-/**
-*
-* This function reads the Minimum/Maximum measurement for one of the
-* specified parameters. Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in
-* xadcps.h to specify the parameters (Temperature, VccInt, VccAux, VBram,
-* VccPInt, VccPAux and VccPDro).
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param MeasurementType specifies the parameter for which the
-* Minimum/Maximum measurement has to be read.
-* Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in xadcps.h to
-* specify the data to be read.
-*
-* @return A 16-bit value representing the maximum/minimum measurement for
-* specified parameter.
-* The XADC device guarantees a 10 bit resolution for
-* the ADC converted data and data is the 10 MSB bits of the 16
-* data read from the device.
-*
-* @note None.
-*
-*****************************************************************************/
-u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType)
-{
- u32 RegData;
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((MeasurementType <= XADCPS_MAX_VCCPDRO) ||
- ((MeasurementType >= XADCPS_MIN_VCCPINT) &&
- (MeasurementType <= XADCPS_MIN_VCCPDRO)))
-
- /*
- * Read and return the specified Minimum/Maximum measurement.
- */
- RegData = XAdcPs_ReadInternalReg(InstancePtr,
- (XADCPS_MAX_TEMP_OFFSET +
- (u32)MeasurementType));
- return (u16) RegData;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the number of samples of averaging that is to be done for
-* all the channels in both the single channel mode and sequence mode of
-* operations.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Average is the number of samples of averaging programmed to the
-* Configuration Register 0. Use the XADCPS_AVG_* definitions defined
-* in xadcps.h file :
-* - XADCPS_AVG_0_SAMPLES for no averaging
-* - XADCPS_AVG_16_SAMPLES for 16 samples of averaging
-* - XADCPS_AVG_64_SAMPLES for 64 samples of averaging
-* - XADCPS_AVG_256_SAMPLES for 256 samples of averaging
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average)
-{
- u32 RegData;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Average <= XADCPS_AVG_256_SAMPLES);
-
- /*
- * Write the averaging value into the Configuration Register 0.
- */
- RegData = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR0_OFFSET) &
- (~XADCPS_CFR0_AVG_VALID_MASK);
-
- RegData |= (((u32) Average << XADCPS_CFR0_AVG_SHIFT));
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
- RegData);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the number of samples of averaging configured for all
-* the channels in the Configuration Register 0.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return The averaging read from the Configuration Register 0 is
-* returned. Use the XADCPS_AVG_* bit definitions defined in
-* xadcps.h file to interpret the returned value :
-* - XADCPS_AVG_0_SAMPLES means no averaging
-* - XADCPS_AVG_16_SAMPLES means 16 samples of averaging
-* - XADCPS_AVG_64_SAMPLES means 64 samples of averaging
-* - XADCPS_AVG_256_SAMPLES means 256 samples of averaging
-*
-* @note None.
-*
-*****************************************************************************/
-u8 XAdcPs_GetAvg(XAdcPs *InstancePtr)
-{
- u32 Average;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the averaging value from the Configuration Register 0.
- */
- Average = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR0_OFFSET) & XADCPS_CFR0_AVG_VALID_MASK;
-
-
- return ((u8) (Average >> XADCPS_CFR0_AVG_SHIFT));
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the given parameters in the Configuration Register 0 in
-* the single channel mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Channel is the channel number for the singel channel mode.
-* The valid channels are 0 to 6, 8, and 13 to 31.
-* If the external Mux is used then this specifies the channel
-* oonnected to the external Mux. Please read the Device Spec
-* to know which channels are valid.
-* @param IncreaseAcqCycles is a boolean parameter which specifies whether
-* the Acquisition time for the external channels has to be
-* increased to 10 ADCCLK cycles (specify TRUE) or remain at the
-* default 4 ADCCLK cycles (specify FALSE). This parameter is
-* only valid for the external channels.
-* @param IsEventMode specifies whether the operation of the ADC is Event
-* driven or Continuous mode.
-* @param IsDifferentialMode is a boolean parameter which specifies
-* unipolar(specify FALSE) or differential mode (specify TRUE) for
-* the analog inputs. The input mode is only valid for the
-* external channels.
-*
-* @return
-* - XST_SUCCESS if the given values were written successfully to
-* the Configuration Register 0.
-* - XST_FAILURE if the channel sequencer is enabled or the input
-* parameters are not valid for the selected channel.
-*
-* @note
-* - The number of samples for the averaging for all the channels
-* is set by using the function XAdcPs_SetAvg.
-* - The calibration of the device is done by doing a ADC
-* conversion on the calibration channel(channel 8). The input
-* parameters IncreaseAcqCycles, IsDifferentialMode and
-* IsEventMode are not valid for this channel
-*
-*
-*****************************************************************************/
-int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
- u8 Channel,
- int IncreaseAcqCycles,
- int IsEventMode,
- int IsDifferentialMode)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((Channel <= XADCPS_CH_VBRAM) ||
- (Channel == XADCPS_CH_ADC_CALIB) ||
- ((Channel >= XADCPS_CH_VCCPINT) &&
- (Channel <= XADCPS_CH_AUX_MAX)));
- Xil_AssertNonvoid((IncreaseAcqCycles == 0x1) ||
- (IncreaseAcqCycles == 0x0));
- Xil_AssertNonvoid((IsEventMode == 0x1) || (IsEventMode == 0x0));
- Xil_AssertNonvoid((IsDifferentialMode == 0x1) ||
- (IsDifferentialMode == 0x0));
-
- /*
- * Check if the device is in single channel mode else return failure
- */
- if ((XAdcPs_GetSequencerMode(InstancePtr) !=
- XADCPS_SEQ_MODE_SINGCHAN)) {
- return XST_FAILURE;
- }
-
- /*
- * Read the Configuration Register 0.
- */
- RegValue = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR0_OFFSET) &
- XADCPS_CFR0_AVG_VALID_MASK;
-
- /*
- * Select the number of acquisition cycles. The acquisition cycles is
- * only valid for the external channels.
- */
- if (IncreaseAcqCycles == 0x1) {
- if (((Channel >= XADCPS_CH_AUX_MIN) &&
- (Channel <= XADCPS_CH_AUX_MAX)) ||
- (Channel == XADCPS_CH_VPVN)){
- RegValue |= XADCPS_CFR0_ACQ_MASK;
- } else {
- return XST_FAILURE;
- }
-
- }
-
- /*
- * Select the input mode. The input mode is only valid for the
- * external channels.
- */
- if (IsDifferentialMode == 0x1) {
-
- if ((Channel >= XADCPS_CH_AUX_MIN) ||
- (Channel == XADCPS_CH_VPVN)){
- RegValue |= XADCPS_CFR0_DU_MASK;
- } else {
- return XST_FAILURE;
- }
- }
-
- /*
- * Select the ADC mode.
- */
- if (IsEventMode == 0x1) {
- RegValue |= XADCPS_CFR0_EC_MASK;
- }
-
- /*
- * Write the given values into the Configuration Register 0.
- */
- RegValue |= ((u32)Channel & XADCPS_CFR0_CHANNEL_MASK);
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
- RegValue);
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* This function enables the alarm outputs for the specified alarms in the
-* Configuration Register 1.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param AlmEnableMask is the bit-mask of the alarm outputs to be enabled
-* in the Configuration Register 1.
-* Bit positions of 1 will be enabled. Bit positions of 0 will be
-* disabled. This mask is formed by OR'ing XADCPS_CFR1_ALM_*_MASK and
-* XADCPS_CFR1_OT_MASK masks defined in xadcps_hw.h.
-*
-* @return None.
-*
-* @note The implementation of the alarm enables in the Configuration
-* register 1 is such that the alarms for bit positions of 1 will
-* be disabled and alarms for bit positions of 0 will be enabled.
-* The alarm outputs specified by the AlmEnableMask are negated
-* before writing to the Configuration Register 1.
-*
-*
-*****************************************************************************/
-void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- RegValue = XAdcPs_ReadInternalReg(InstancePtr, XADCPS_CFR1_OFFSET);
-
- RegValue &= ~XADCPS_CFR1_ALM_ALL_MASK;
- RegValue |= (~(u32)AlmEnableMask & XADCPS_CFR1_ALM_ALL_MASK);
-
- /*
- * Enable/disables the alarm enables for the specified alarm bits in the
- * Configuration Register 1.
- */
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
- RegValue);
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the status of the alarm output enables in the
-* Configuration Register 1.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return This is the bit-mask of the enabled alarm outputs in the
-* Configuration Register 1. Use the masks XADCPS_CFR1_ALM*_* and
-* XADCPS_CFR1_OT_MASK defined in xadcps_hw.h to interpret the
-* returned value.
-* Bit positions of 1 indicate that the alarm output is enabled.
-* Bit positions of 0 indicate that the alarm output is disabled.
-*
-*
-* @note The implementation of the alarm enables in the Configuration
-* register 1 is such that alarms for the bit positions of 1 will
-* be disabled and alarms for bit positions of 0 will be enabled.
-* The enabled alarm outputs returned by this function is the
-* negated value of the the data read from the Configuration
-* Register 1.
-*
-*****************************************************************************/
-u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the status of alarm output enables from the Configuration
- * Register 1.
- */
- RegValue = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR1_OFFSET) & XADCPS_CFR1_ALM_ALL_MASK;
- return (u16) (~RegValue & XADCPS_CFR1_ALM_ALL_MASK);
-}
-
-/****************************************************************************/
-/**
-*
-* This function enables the specified calibration in the Configuration
-* Register 1 :
-*
-* - XADCPS_CFR1_CAL_ADC_OFFSET_MASK : Calibration 0 -ADC offset correction
-* - XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : Calibration 1 -ADC gain and offset
-* correction
-* - XADCPS_CFR1_CAL_PS_OFFSET_MASK : Calibration 2 -Power Supply sensor
-* offset correction
-* - XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Calibration 3 -Power Supply sensor
-* gain and offset correction
-* - XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Calibration is the Calibration to be applied.
-* Use XADCPS_CFR1_CAL*_* bits defined in xadcps_hw.h.
-* Multiple calibrations can be enabled at a time by oring the
-* XADCPS_CFR1_CAL_ADC_* and XADCPS_CFR1_CAL_PS_* bits.
-* Calibration can be disabled by specifying
- XADCPS_CFR1_CAL_DISABLE_MASK;
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(((Calibration >= XADCPS_CFR1_CAL_ADC_OFFSET_MASK) &&
- (Calibration <= XADCPS_CFR1_CAL_VALID_MASK)) ||
- (Calibration == XADCPS_CFR1_CAL_DISABLE_MASK));
-
- /*
- * Set the specified calibration in the Configuration Register 1.
- */
- RegValue = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR1_OFFSET);
-
- RegValue &= ~XADCPS_CFR1_CAL_VALID_MASK;
- RegValue |= ((u32)Calibration & XADCPS_CFR1_CAL_VALID_MASK);
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
- RegValue);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function reads the value of the calibration enables from the
-* Configuration Register 1.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return The value of the calibration enables in the Configuration
-* Register 1 :
-* - XADCPS_CFR1_CAL_ADC_OFFSET_MASK : ADC offset correction
-* - XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : ADC gain and offset
-* correction
-* - XADCPS_CFR1_CAL_PS_OFFSET_MASK : Power Supply sensor offset
-* correction
-* - XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Power Supply sensor
-* gain and offset correction
-* - XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration
-*
-* @note None.
-*
-*****************************************************************************/
-u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the calibration enables from the Configuration Register 1.
- */
- return (u16) XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR1_OFFSET) & XADCPS_CFR1_CAL_VALID_MASK;
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the specified Channel Sequencer Mode in the Configuration
-* Register 1 :
-* - Default safe mode (XADCPS_SEQ_MODE_SAFE)
-* - One pass through sequence (XADCPS_SEQ_MODE_ONEPASS)
-* - Continuous channel sequencing (XADCPS_SEQ_MODE_CONTINPASS)
-* - Single Channel/Sequencer off (XADCPS_SEQ_MODE_SINGCHAN)
-* - Simulataneous sampling mode (XADCPS_SEQ_MODE_SIMUL_SAMPLING)
-* - Independent mode (XADCPS_SEQ_MODE_INDEPENDENT)
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param SequencerMode is the sequencer mode to be set.
-* Use XADCPS_SEQ_MODE_* bits defined in xadcps.h.
-* @return None.
-*
-* @note Only one of the modes can be enabled at a time. Please
-* read the Spec of the XADC for further information about the
-* sequencer modes.
-*
-*
-*****************************************************************************/
-void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((SequencerMode <= XADCPS_SEQ_MODE_SIMUL_SAMPLING) ||
- (SequencerMode == XADCPS_SEQ_MODE_INDEPENDENT));
-
- /*
- * Set the specified sequencer mode in the Configuration Register 1.
- */
- RegValue = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR1_OFFSET);
- RegValue &= (~ XADCPS_CFR1_SEQ_VALID_MASK);
- RegValue |= (((u32)SequencerMode << XADCPS_CFR1_SEQ_SHIFT) &
- XADCPS_CFR1_SEQ_VALID_MASK);
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
- RegValue);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the channel sequencer mode from the Configuration
-* Register 1.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return The channel sequencer mode :
-* - XADCPS_SEQ_MODE_SAFE : Default safe mode
-* - XADCPS_SEQ_MODE_ONEPASS : One pass through sequence
-* - XADCPS_SEQ_MODE_CONTINPASS : Continuous channel sequencing
-* - XADCPS_SEQ_MODE_SINGCHAN : Single channel/Sequencer off
-* - XADCPS_SEQ_MODE_SIMUL_SAMPLING : Simulataneous sampling mode
-* - XADCPS_SEQ_MODE_INDEPENDENT : Independent mode
-*
-*
-* @note None.
-*
-*****************************************************************************/
-u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the channel sequencer mode from the Configuration Register 1.
- */
- return ((u8) ((XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR1_OFFSET) & XADCPS_CFR1_SEQ_VALID_MASK) >>
- XADCPS_CFR1_SEQ_SHIFT));
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the frequency of the ADCCLK by configuring the DCLK to
-* ADCCLK ratio in the Configuration Register #2
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Divisor is clock divisor used to derive ADCCLK from DCLK.
-* Valid values of the divisor are
-* - 0 to 255. Values 0, 1, 2 are all mapped to 2.
-* Refer to the device specification for more details
-*
-* @return None.
-*
-* @note - The ADCCLK is an internal clock used by the ADC and is
-* synchronized to the DCLK clock. The ADCCLK is equal to DCLK
-* divided by the user selection in the Configuration Register 2.
-* - There is no Assert on the minimum value of the Divisor.
-*
-*****************************************************************************/
-void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Write the divisor value into the Configuration Register #2.
- */
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET,
- ((u32)Divisor << XADCPS_CFR2_CD_SHIFT));
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function gets the ADCCLK divisor from the Configuration Register 2.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return The divisor read from the Configuration Register 2.
-*
-* @note The ADCCLK is an internal clock used by the ADC and is
-* synchronized to the DCLK clock. The ADCCLK is equal to DCLK
-* divided by the user selection in the Configuration Register 2.
-*
-*****************************************************************************/
-u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr)
-{
- u16 Divisor;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the divisor value from the Configuration Register 2.
- */
- Divisor = (u16) XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR2_OFFSET);
-
- return (u8) (Divisor >> XADCPS_CFR2_CD_SHIFT);
-}
-
-/****************************************************************************/
-/**
-*
-* This function enables the specified channels in the ADC Channel Selection
-* Sequencer Registers. The sequencer must be disabled before writing to these
-* regsiters.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param ChEnableMask is the bit mask of all the channels to be enabled.
-* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel
-* numbers. Bit masks of 1 will be enabled and bit mask of 0 will
-* be disabled.
-* The ChEnableMask is a 32 bit mask that is written to the two
-* 16 bit ADC Channel Selection Sequencer Registers.
-*
-* @return
-* - XST_SUCCESS if the given values were written successfully to
-* the ADC Channel Selection Sequencer Registers.
-* - XST_FAILURE if the channel sequencer is enabled.
-*
-* @note None
-*
-*****************************************************************************/
-int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * The sequencer must be disabled for writing any of these registers
- * Return XST_FAILURE if the channel sequencer is enabled.
- */
- if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
- return XST_FAILURE;
- }
-
- /*
- * Enable the specified channels in the ADC Channel Selection Sequencer
- * Registers.
- */
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_SEQ00_OFFSET,
- (ChEnableMask & XADCPS_SEQ00_CH_VALID_MASK));
-
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_SEQ01_OFFSET,
- (ChEnableMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
- XADCPS_SEQ01_CH_VALID_MASK);
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the channel enable bits status from the ADC Channel
-* Selection Sequencer Registers.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return Gets the channel enable bits. Use XADCPS_SEQ_CH__* defined in
-* xadcps_hw.h to interpret the Channel numbers. Bit masks of 1
-* are the channels that are enabled and bit mask of 0 are
-* the channels that are disabled.
-*
-* @return None
-*
-* @note None
-*
-*****************************************************************************/
-u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr)
-{
- u32 RegValEnable;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the channel enable bits for all the channels from the ADC
- * Channel Selection Register.
- */
- RegValEnable = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_SEQ00_OFFSET) &
- XADCPS_SEQ00_CH_VALID_MASK;
- RegValEnable |= (XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_SEQ01_OFFSET) &
- XADCPS_SEQ01_CH_VALID_MASK) <<
- XADCPS_SEQ_CH_AUX_SHIFT;
-
-
- return RegValEnable;
-}
-
-/****************************************************************************/
-/**
-*
-* This function enables the averaging for the specified channels in the ADC
-* Channel Averaging Enable Sequencer Registers. The sequencer must be disabled
-* before writing to these regsiters.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param AvgEnableChMask is the bit mask of all the channels for which
-* averaging is to be enabled. Use XADCPS_SEQ_CH__* defined in
-* xadcps_hw.h to specify the Channel numbers. Averaging will be
-* enabled for bit masks of 1 and disabled for bit mask of 0.
-* The AvgEnableChMask is a 32 bit mask that is written to the two
-* 16 bit ADC Channel Averaging Enable Sequencer Registers.
-*
-* @return
-* - XST_SUCCESS if the given values were written successfully to
-* the ADC Channel Averaging Enables Sequencer Registers.
-* - XST_FAILURE if the channel sequencer is enabled.
-*
-* @note None
-*
-*****************************************************************************/
-int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * The sequencer must be disabled for writing any of these registers
- * Return XST_FAILURE if the channel sequencer is enabled.
- */
- if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
- return XST_FAILURE;
- }
-
- /*
- * Enable/disable the averaging for the specified channels in the
- * ADC Channel Averaging Enables Sequencer Registers.
- */
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_SEQ02_OFFSET,
- (AvgEnableChMask & XADCPS_SEQ02_CH_VALID_MASK));
-
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_SEQ03_OFFSET,
- (AvgEnableChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
- XADCPS_SEQ03_CH_VALID_MASK);
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the channels for which the averaging has been enabled
-* in the ADC Channel Averaging Enables Sequencer Registers.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @returns The status of averaging (enabled/disabled) for all the channels.
-* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the
-* Channel numbers. Bit masks of 1 are the channels for which
-* averaging is enabled and bit mask of 0 are the channels for
-* averaging is disabled
-*
-* @note None
-*
-*****************************************************************************/
-u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr)
-{
- u32 RegValAvg;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the averaging enable status for all the channels from the
- * ADC Channel Averaging Enables Sequencer Registers.
- */
- RegValAvg = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_SEQ02_OFFSET) & XADCPS_SEQ02_CH_VALID_MASK;
- RegValAvg |= (XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_SEQ03_OFFSET) & XADCPS_SEQ03_CH_VALID_MASK) <<
- XADCPS_SEQ_CH_AUX_SHIFT;
-
- return RegValAvg;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the Analog input mode for the specified channels in the ADC
-* Channel Analog-Input Mode Sequencer Registers. The sequencer must be disabled
-* before writing to these regsiters.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param InputModeChMask is the bit mask of all the channels for which
-* the input mode is differential mode. Use XADCPS_SEQ_CH__* defined
-* in xadcps_hw.h to specify the channel numbers. Differential
-* input mode will be set for bit masks of 1 and unipolar input
-* mode for bit masks of 0.
-* The InputModeChMask is a 32 bit mask that is written to the two
-* 16 bit ADC Channel Analog-Input Mode Sequencer Registers.
-*
-* @return
-* - XST_SUCCESS if the given values were written successfully to
-* the ADC Channel Analog-Input Mode Sequencer Registers.
-* - XST_FAILURE if the channel sequencer is enabled.
-*
-* @note None
-*
-*****************************************************************************/
-int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * The sequencer must be disabled for writing any of these registers
- * Return XST_FAILURE if the channel sequencer is enabled.
- */
- if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
- return XST_FAILURE;
- }
-
- /*
- * Set the input mode for the specified channels in the ADC Channel
- * Analog-Input Mode Sequencer Registers.
- */
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_SEQ04_OFFSET,
- (InputModeChMask & XADCPS_SEQ04_CH_VALID_MASK));
-
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_SEQ05_OFFSET,
- (InputModeChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
- XADCPS_SEQ05_CH_VALID_MASK);
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the Analog input mode for all the channels from
-* the ADC Channel Analog-Input Mode Sequencer Registers.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @returns The input mode for all the channels.
-* Use XADCPS_SEQ_CH_* defined in xadcps_hw.h to interpret the
-* Channel numbers. Bit masks of 1 are the channels for which
-* input mode is differential and bit mask of 0 are the channels
-* for which input mode is unipolar.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr)
-{
- u32 InputMode;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Get the input mode for all the channels from the ADC Channel
- * Analog-Input Mode Sequencer Registers.
- */
- InputMode = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_SEQ04_OFFSET) &
- XADCPS_SEQ04_CH_VALID_MASK;
- InputMode |= (XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_SEQ05_OFFSET) &
- XADCPS_SEQ05_CH_VALID_MASK) <<
- XADCPS_SEQ_CH_AUX_SHIFT;
-
- return InputMode;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the number of Acquisition cycles in the ADC Channel
-* Acquisition Time Sequencer Registers. The sequencer must be disabled
-* before writing to these regsiters.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param AcqCyclesChMask is the bit mask of all the channels for which
-* the number of acquisition cycles is to be extended.
-* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel
-* numbers. Acquisition cycles will be extended to 10 ADCCLK cycles
-* for bit masks of 1 and will be the default 4 ADCCLK cycles for
-* bit masks of 0.
-* The AcqCyclesChMask is a 32 bit mask that is written to the two
-* 16 bit ADC Channel Acquisition Time Sequencer Registers.
-*
-* @return
-* - XST_SUCCESS if the given values were written successfully to
-* the Channel Sequencer Registers.
-* - XST_FAILURE if the channel sequencer is enabled.
-*
-* @note None.
-*
-*****************************************************************************/
-int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * The sequencer must be disabled for writing any of these registers
- * Return XST_FAILURE if the channel sequencer is enabled.
- */
- if ((XAdcPs_GetSequencerMode(InstancePtr) !=
- XADCPS_SEQ_MODE_SAFE)) {
- return XST_FAILURE;
- }
-
- /*
- * Set the Acquisition time for the specified channels in the
- * ADC Channel Acquisition Time Sequencer Registers.
- */
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_SEQ06_OFFSET,
- (AcqCyclesChMask & XADCPS_SEQ06_CH_VALID_MASK));
-
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_SEQ07_OFFSET,
- (AcqCyclesChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
- XADCPS_SEQ07_CH_VALID_MASK);
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the status of acquisition from the ADC Channel Acquisition
-* Time Sequencer Registers.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @returns The acquisition time for all the channels.
-* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the
-* Channel numbers. Bit masks of 1 are the channels for which
-* acquisition cycles are extended and bit mask of 0 are the
-* channels for which acquisition cycles are not extended.
-*
-* @note None
-*
-*****************************************************************************/
-u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr)
-{
- u32 RegValAcq;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Get the Acquisition cycles for the specified channels from the ADC
- * Channel Acquisition Time Sequencer Registers.
- */
- RegValAcq = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_SEQ06_OFFSET) &
- XADCPS_SEQ06_CH_VALID_MASK;
- RegValAcq |= (XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_SEQ07_OFFSET) &
- XADCPS_SEQ07_CH_VALID_MASK) <<
- XADCPS_SEQ_CH_AUX_SHIFT;
-
- return RegValAcq;
-}
-
-/****************************************************************************/
-/**
-*
-* This functions sets the contents of the given Alarm Threshold Register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param AlarmThrReg is the index of an Alarm Threshold Register to
-* be set. Use XADCPS_ATR_* constants defined in xadcps.h to
-* specify the index.
-* @param Value is the 16-bit threshold value to write into the register.
-*
-* @return None.
-*
-* @note Use XAdcPs_SetOverTemp() to set the Over Temperature upper
-* threshold value.
-*
-*****************************************************************************/
-void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value)
-{
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(AlarmThrReg <= XADCPS_ATR_VCCPDRO_LOWER);
-
- /*
- * Write the value into the specified Alarm Threshold Register.
- */
- XAdcPs_WriteInternalReg(InstancePtr, (XADCPS_ATR_TEMP_UPPER_OFFSET +
- (u32)AlarmThrReg), Value);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the contents of the specified Alarm Threshold Register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param AlarmThrReg is the index of an Alarm Threshold Register
-* to be read. Use XADCPS_ATR_* constants defined in xadcps_hw.h
-* to specify the index.
-*
-* @return A 16-bit value representing the contents of the selected Alarm
-* Threshold Register.
-*
-* @note None.
-*
-*****************************************************************************/
-u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg)
-{
- u32 RegData;
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(AlarmThrReg <= XADCPS_ATR_VCCPDRO_LOWER);
-
- /*
- * Read the specified Alarm Threshold Register and return
- * the value
- */
- RegData = XAdcPs_ReadInternalReg(InstancePtr,
- (XADCPS_ATR_TEMP_UPPER_OFFSET +
- (u32)AlarmThrReg));
-
- return (u16) RegData;
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function enables programming of the powerdown temperature for the
-* OverTemp signal in the OT Powerdown register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr)
-{
- u16 OtUpper;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the OT upper Alarm Threshold Register.
- */
- OtUpper = (u16)(XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_ATR_OT_UPPER_OFFSET));
- OtUpper &= ~((u16)XADCPS_ATR_OT_UPPER_ENB_MASK);
-
- /*
- * Preserve the powerdown value and write OT enable value the into the
- * OT Upper Alarm Threshold Register.
- */
- OtUpper |= XADCPS_ATR_OT_UPPER_ENB_VAL;
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_ATR_OT_UPPER_OFFSET, (u32)OtUpper);
-}
-
-/****************************************************************************/
-/**
-*
-* This function disables programming of the powerdown temperature for the
-* OverTemp signal in the OT Powerdown register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return None.
-*
-* @note None.
-*
-*
-*****************************************************************************/
-void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr)
-{
- u16 OtUpper;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the OT Upper Alarm Threshold Register.
- */
- OtUpper = (u16)(XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_ATR_OT_UPPER_OFFSET));
- OtUpper &= ~((u16)XADCPS_ATR_OT_UPPER_ENB_MASK);
-
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_ATR_OT_UPPER_OFFSET, (u32)OtUpper);
-}
-
-
-/****************************************************************************/
-/**
-*
-* The function enables the Event mode or Continuous mode in the sequencer mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param IsEventMode is a boolean parameter that specifies continuous
-* sampling (specify FALSE) or event driven sampling mode (specify
-* TRUE) for the given channel.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((IsEventMode == 0x1) || (IsEventMode == 0x0));
-
- /*
- * Read the Configuration Register 0.
- */
- RegValue = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR0_OFFSET) &
- (~XADCPS_CFR0_EC_MASK);
-
- /*
- * Set the ADC mode.
- */
- if (IsEventMode == 0x1) {
- RegValue |= XADCPS_CFR0_EC_MASK;
- } else {
- RegValue &= ~XADCPS_CFR0_EC_MASK;
- }
-
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
- RegValue);
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function returns the sampling mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return The sampling mode
-* - 0 specifies continuous sampling
-* - 1 specifies event driven sampling mode
-*
-* @note None.
-*
-*****************************************************************************/
-int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr)
-{
- u32 Mode;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the sampling mode from the Configuration Register 0.
- */
- Mode = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR0_OFFSET) &
- XADCPS_CFR0_EC_MASK;
- if (Mode > 0U) {
-
- return 1;
- }
-
- return (0);
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function sets the External Mux mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param MuxMode specifies whether External Mux is used
-* - FALSE specifies NO external MUX
-* - TRUE specifies External Mux is used
-* @param Channel specifies the channel to be used for the
-* external Mux. Please read the Device Spec for which
-* channels are valid for which mode.
-*
-* @return None.
-*
-* @note There is no Assert in this function for checking the channel
-* number if the external Mux is used. The user should provide a
-* valid channel number.
-*
-*****************************************************************************/
-void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((MuxMode == 0x1) || (MuxMode == 0x0));
-
- /*
- * Read the Configuration Register 0.
- */
- RegValue = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR0_OFFSET) &
- (~XADCPS_CFR0_MUX_MASK);
- /*
- * Select the Mux mode and the channel to be used.
- */
- if (MuxMode == 0x1) {
- RegValue |= XADCPS_CFR0_MUX_MASK;
- RegValue |= ((u32)Channel & XADCPS_CFR0_CHANNEL_MASK);
-
- }
-
- /*
- * Write the mux mode into the Configuration Register 0.
- */
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
- RegValue);
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function sets the Power Down mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Mode specifies the Power Down Mode
-* - XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and
-* ADC B are enabled)
-* - XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B
-* - XADCPS_PD_MODE_XADC specifies the Power Down of
-* both ADC A and ADC B.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Mode < XADCPS_PD_MODE_XADC);
-
-
- /*
- * Read the Configuration Register 2.
- */
- RegValue = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR2_OFFSET) &
- (~XADCPS_CFR2_PD_MASK);
- /*
- * Select the Power Down mode.
- */
- RegValue |= (Mode << XADCPS_CFR2_PD_SHIFT);
-
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET,
- RegValue);
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the Power Down mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return Mode specifies the Power Down Mode
-* - XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and
-* ADC B are enabled)
-* - XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B
-* - XADCPS_PD_MODE_XADC specifies the Power Down of
-* both ADC A and ADC B.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Power Down Mode.
- */
- RegValue = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR2_OFFSET) &
- (~XADCPS_CFR2_PD_MASK);
- /*
- * Return the Power Down mode.
- */
- return (RegValue >> XADCPS_CFR2_PD_SHIFT);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function is used for writing to XADC Registers using the command FIFO.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param RegOffset is the offset of the XADC register to be written.
-* @param Data is the data to be written.
-*
-* @return None.
-*
-* @note None.
-*
-*
-*****************************************************************************/
-void XAdcPs_WriteInternalReg(XAdcPs *InstancePtr, u32 RegOffset, u32 Data)
-{
- u32 RegData;
-
- /**
- * Write the Data into the FIFO Register.
- */
- RegData = (XADCPS_JTAG_CMD_WRITE_MASK) |
- ((RegOffset << XADCPS_JTAG_ADDR_SHIFT) & XADCPS_JTAG_ADDR_MASK) |
- (Data & XADCPS_JTAG_DATA_MASK);
-
- XAdcPs_WriteFifo(InstancePtr, RegData);
-
- /**
- * Read the Read FIFO after any write since for each write
- * one location of Read FIFO gets updated
- */
- XAdcPs_ReadFifo(InstancePtr);
-
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function is used for reading from the XADC Registers using the Data FIFO.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param RegOffset is the offset of the XADC register to be read.
-*
-* @return Data read from the FIFO
-*
-* @note None.
-*
-*
-*****************************************************************************/
-u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset)
-{
-
- u32 RegData;
-
- RegData = (XADCPS_JTAG_CMD_READ_MASK) |
- ((RegOffset << XADCPS_JTAG_ADDR_SHIFT) & XADCPS_JTAG_ADDR_MASK);
-
- /* Read cmd to FIFO*/
- XAdcPs_WriteFifo(InstancePtr, RegData);
-
- /* Do a Dummy read */
- RegData = XAdcPs_ReadFifo(InstancePtr);
-
- /* Do a Dummy write to get the actual read */
- XAdcPs_WriteFifo(InstancePtr, RegData);
-
- /* Do the Actual read */
- RegData = XAdcPs_ReadFifo(InstancePtr);
-
- return RegData;
-
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/53/729134595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/53/729134595243001d18b399c1eb9b3628
deleted file mode 100644
index 4b289a7..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/53/729134595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,43 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_hal.h
-*
-* Contains all the HAL header files.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/28/09 Initial release
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------------
-* 1.00a drg 01/19/00 First release
-* 1.01a sdm 11/09/11 The XScuGic and XScuGic_Config structures have changed.
-* The HandlerTable (of type XScuGic_VectorTableEntry) is
-* moved to XScuGic_Config structure from XScuGic structure.
-*
-* The "Config" entry in XScuGic structure is made as
-* pointer for better efficiency.
-*
-* A new file named as xscugic_hw.c is now added. It is
-* to implement low level driver routines without using
-* any xscugic instance pointer. They are useful when the
-* user wants to use xscugic through device id or
-* base address. The driver routines provided are explained
-* below.
-* XScuGic_DeviceInitialize that takes device id as
-* argument and initializes the device (without calling
-* XScuGic_CfgInitialize).
-* XScuGic_DeviceInterruptHandler that takes device id
-* as argument and calls appropriate handlers from the
-* HandlerTable.
-* XScuGic_RegisterHandler that registers a new handler
-* by taking xscugic hardware base address as argument.
-* LookupConfigByBaseAddress is used to return the
-* corresponding config structure from XScuGic_ConfigTable
-* based on the scugic base address passed.
-* 1.02a sdm 12/20/11 Removed AckBeforeService from the XScuGic_Config
-* structure.
-* 1.03a srt 02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
-* *_hw.h
-* Added APIs
-* - XScuGic_SetPriTrigTypeByDistAddr()
-* - XScuGic_GetPriTrigTypeByDistAddr()
-* (CR 702687)
-* Added support to direct interrupts to the appropriate CPU. Earlier
-* interrupts were directed to CPU1 (hard coded). Now depending
-* upon the CPU selected by the user (xparameters.h), interrupts
-* will be directed to the relevant CPU. This fixes CR 699688.
-* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
-* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
-* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
-* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
-* This is fix for CR#705621.
-* 1.05a hk 06/26/13 Modified tcl to export external interrupts correctly to
-* xparameters.h. Fix for CR's 690505, 708928 & 719359.
-* 2.0 adk 12/10/13 Updated as per the New Tcl API's
-* 2.1 adk 25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.2 asa 02/29/16 Modified DistributorInit function for Zynq AMP case. The
-* distributor is left uninitialized for Zynq AMP. It is assumed
-* that the distributor will be initialized by Linux master. However
-* for CortexR5 case, the earlier code is left unchanged where the
-* the interrupt processor target registers in the distributor is
-* initialized with the corresponding CPU ID on which the application
-* built over the scugic driver runs.
-* These changes fix CR#937243.
-*
-* 3.4 asa 04/07/16 Created a new static function DoDistributorInit to simplify
-* the flow and avoid code duplication. Changes are made for
-* USE_AMP use case for R5. In a scenario (in R5 split mode) when
-* one R5 is operating with A53 in open amp config and other
-* R5 running baremetal app, the existing code
-* had the potential to stop the whole AMP solution to work (if
-* for some reason the R5 running the baremetal app tasked to
-* initialize the Distributor hangs or crashes before initializing).
-* Changes are made so that the R5 under AMP first checks if
-* the distributor is enabled or not and if not, it does the
-* standard Distributor initialization.
-* This fixes the CR#952962.
-* 3.6 ms 01/23/17 Modified xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* kvn 02/17/17 Add support for changing GIC CPU master at run time.
-* kvn 02/28/17 Make the CpuId as static variable and Added new
-* XScugiC_GetCpuId to access CpuId.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 3.7 ms 04/11/17 Modified tcl file to add suffix U for all macro
-* definitions of scugic in xparameters.h
-* 3.8 mus 07/05/17 Updated scugic.tcl to add support for interrupts connected
-* through util_reduced_vector IP(OR gate)
-* mus 07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize
-* the HandlerTable in XScuGic_ConfigTable to 0, it removes
-* the compilation warning in xscugic_g.c. Fix for CR#978736.
-* mus 07/25/17 Updated xdefine_gic_params proc to export correct canonical
-* definitions for pl to ps interrupts.Fix for CR#980534
-* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
-* XScuGic_InterruptUnmapFromCpu, These API's can be used
-* by applications to unmap specific/all interrupts from
-* target CPU.
-* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
-* 4.0 mus 11/22/18 Fixed bugs in software interrupt generation through
-* XScuGic_SoftwareIntr API
-* 4.1 asa 03/30/19 Made changes not to direct each interrupt to all
-* available CPUs by default. This was breaking AMP
-* behavior. Instead every time an interrupt enable
-* request is received, the interrupt was mapped to
-* the respective CPU. There were several other changes
-* made to implement this. This set of changes was to
-* fix CR-1024716.
-* 4.1 mus 06/19/19 Added API's XScuGic_MarkCoreAsleep and
-* XScuGic_MarkCoreAwake to mark processor core as
-* asleep or awake. Fix for CR#1027220.
-* 4.5 asa 03/07/21 Included a header file xil_spinlock.h to ensure that
-* GIC driver can use newly introduced spinlock
-* functionality.
-* 4.6 sk 08/05/21 Fix scugic misrac violations.
-*
-*
-*
-******************************************************************************/
-
-#ifndef XSCUGIC_H /* prevent circular inclusions */
-#define XSCUGIC_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xil_io.h"
-#include "xscugic_hw.h"
-#include "xil_exception.h"
-#include "xil_spinlock.h"
-
-/************************** Constant Definitions *****************************/
-
-#define EFUSE_STATUS_OFFSET 0x10
-#define EFUSE_STATUS_CPU_MASK 0x80
-
-#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
-#define ARMA9
-#endif
-
-#define XSCUGIC500_DCTLR_ARE_NS_ENABLE 0x20
-#define XSCUGIC500_DCTLR_ARE_S_ENABLE 0x10
-/**************************** Type Definitions *******************************/
-
-/* The following data type defines each entry in an interrupt vector table.
- * The callback reference is the base address of the interrupting device
- * for the low level driver and an instance pointer for the high level driver.
- */
-typedef struct
-{
- Xil_InterruptHandler Handler;
- void *CallBackRef;
-} XScuGic_VectorTableEntry;
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct
-{
- u16 DeviceId; /**< Unique ID of device */
- u32 CpuBaseAddress; /**< CPU Interface Register base address */
- u32 DistBaseAddress; /**< Distributor Register base address */
- XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
- Vector table of interrupt handlers */
-} XScuGic_Config;
-
-/**
- * The XScuGic driver instance data. The user is required to allocate a
- * variable of this type for every intc device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct
-{
- XScuGic_Config *Config; /**< Configuration table entry */
- u32 IsReady; /**< Device is initialized and ready */
- u32 UnhandledInterrupts; /**< Intc Statistics */
-} XScuGic;
-
-/************************** Variable Definitions *****************************/
-
-extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Write the given CPU Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
- ((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given CPU Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
- (XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given Distributor Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
- ((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given Distributor Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
-(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given ReDistributor Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_ReDistWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress)+ \
- XSCUGIC_RDIST_OFFSET, (RegOffset), ((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given ReDistributor Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_ReDistReadReg(InstancePtr, RegOffset) \
-(XScuGic_ReadReg((((InstancePtr)->Config->DistBaseAddress)+ \
-XSCUGIC_RDIST_OFFSET), (RegOffset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given ReDistributor SGI PPI Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_ReDistSGIPPIWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress)+ \
- XSCUGIC_RDIST_SGI_PPI_OFFSET, (RegOffset), ((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given ReDistributor SGI PPI Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_ReDistSGIPPIReadReg(InstancePtr, RegOffset) \
-(XScuGic_ReadReg((((InstancePtr)->Config->DistBaseAddress)+ \
- XSCUGIC_RDIST_SGI_PPI_OFFSET), (RegOffset)))
-
-/****************************************************************************/
-/**
-* This function enables system register interface for GIC CPU Interface
-*
-* @param value to be written
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_Enable_SystemReg_CPU_Interface_EL3() mtcp(S3_6_C12_C12_5, 0xF);
-#define XScuGic_Enable_SystemReg_CPU_Interface_EL1() mtcp(S3_0_C12_C12_5, 0xF);
-/****************************************************************************/
-/**
-* This function enables Grou0 interrupts
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_Enable_Group0_Interrupts() mtcp(S3_0_C12_C12_6,0x1);
-/****************************************************************************/
-/**
-* This function enables Group1 interrupts
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#if defined (__aarch64__)
-#if EL1_NONSECURE
-#define XScuGic_Enable_Group1_Interrupts() \
- mtcp (S3_0_C12_C12_7, 0x1 | mfcp(S3_0_C12_C12_7) );
-#else
-#define XScuGic_Enable_Group1_Interrupts() \
- mtcp (S3_6_C12_C12_7, 0x1 | mfcp(S3_6_C12_C12_7) );
-#endif
-#endif
-/****************************************************************************/
-/**
-* This function writes to ICC_SGI0R_EL1
-*
-* @param value to be written
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_WriteICC_SGI0R_EL1(val) mtcp(S3_0_C12_C11_7,val)
-
-/****************************************************************************/
-/**
-* This function writes to ICC_SGI1R_EL1
-*
-* @param value to be written
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_WriteICC_SGI1R_EL1(val) mtcp(S3_0_C12_C11_5,val)
-
-/****************************************************************************/
-/**
-* This function reads ICC_SGI1R_EL1 register
-*
-* @param None
-*
-* @return Value of ICC_SGI1R_EL1 register
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_ReadICC_SGI1R_EL1() mfcp(S3_0_C12_C11_5)
-/****************************************************************************/
-/**
-* This function sets interrupt priority filter
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_set_priority_filter(val) __asm__ __volatile__("msr S3_0_C4_C6_0,%0" : : "r" (val))
-/****************************************************************************/
-/**
-* This function returns interrupt id of highest priority pending interrupt
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#if defined (__aarch64__)
-#if EL3
-#define XScuGic_get_IntID() mfcp(S3_0_C12_C8_0)
-#else
-#define XScuGic_get_IntID() mfcp(S3_0_C12_C12_0)
-#endif
-#endif
-/****************************************************************************/
-/**
-* This function acks the interrupt
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#if defined (__aarch64__)
-#if EL3
-#define XScuGic_ack_Int(val) mtcp(S3_0_C12_C8_1,val)
-#else
-#define XScuGic_ack_Int(val) mtcp(S3_0_C12_C12_1,val)
-#endif
-#endif
-/****************************************************************************/
-/**
-* This macro returns bit position for the specific interrupt's trigger type
-* configuration within GICR_ICFGR0/GICR_ICFGR1 register
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_Get_Rdist_Int_Trigger_Index(IntrId) (((Int_Id%16) & 0x1f) << 2) +1
-/************************** Function Prototypes ******************************/
-
-/*
- * Required functions in xscugic.c
- */
-
-s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
- Xil_InterruptHandler Handler, void *CallBackRef);
-void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id);
-
-void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id);
-void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id);
-
-s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr,
- u32 EffectiveAddr);
-
-s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Identifier);
-
-void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
- u8 *Priority, u8 *Trigger);
-void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
- u8 Priority, u8 Trigger);
-void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Identifier, u32 Int_Id);
-void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Identifier, u32 Int_Id);
-void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Identifier);
-void XScuGic_Stop(XScuGic *InstancePtr);
-void XScuGic_SetCpuID(u32 CpuCoreId);
-u32 XScuGic_GetCpuID(void);
-/*
- * Initialization functions in xscugic_sinit.c
- */
-XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
-
-/*
- * Interrupt functions in xscugic_intr.c
- */
-void XScuGic_InterruptHandler(XScuGic *InstancePtr);
-
-/*
- * Self-test functions in xscugic_selftest.c
- */
-s32 XScuGic_SelfTest(XScuGic *InstancePtr);
-
-#if defined (GICv3)
-void XScuGic_MarkCoreAsleep(XScuGic *InstancePtr);
-void XScuGic_MarkCoreAwake(XScuGic *InstancePtr);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/54/a13b41595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/54/a13b41595243001d18b399c1eb9b3628
deleted file mode 100644
index 7e29233..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/54/a13b41595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,165 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_testmem.h
-* @addtogroup common_test_utils Test Utilities for Memory and Caches
-*
-* - Cache test: xil_testcache.h contains utility functions to test cache.
-*
-* - I/O test: The Xil_testio.h file contains endian related memory IO functions. A
-* subset of the memory tests can be selected or all of the tests can be run in order.
-* If there is an error detected by a subtest, the test stops and the failure code is
-* returned. Further tests are not run even if all of the tests are selected.
-*
-* - Memory test: The xil_testmem.h file contains utility functions to test memory.
-* A subset of the memory tests can be selected or all of the tests can be run
-* in order. If there is an error detected by a subtest, the test stops and the
-* failure code is returned. Further tests are not run even if all of the tests are selected.
-*
-*
-* Following list describes the supported memory tests:
-*
-* - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
-*
-* - XIL_TESTMEM_INCREMENT: This test
-* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
-* test value for memory.
-*
-* - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
-* uses a walking '1' as the test value for memory.
-* @code
-* location 1 = 0x00000001
-* location 2 = 0x00000002
-* ...
-* @endcode
-*
-* - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
-* This test uses the inverse value of the walking ones test
-* as the test value for memory.
-* @code
-* location 1 = 0xFFFFFFFE
-* location 2 = 0xFFFFFFFD
-* ...
-*@endcode
-*
-* - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
-* This test uses the inverse of the address of the location under test
-* as the test value for memory.
-*
-* - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
-* This test uses the provided patters as the test value for memory.
-* If zero is provided as the pattern the test uses '0xDEADBEEF".
-*
-* @warning
-* The tests are DESTRUCTIVE. Run before any initialized memory spaces
-* have been set up.
-* The address provided to the memory tests is not checked for
-* validity except for the NULL case. It is possible to provide a code-space
-* pointer for this test to start with and ultimately destroy executable code
-* causing random failures.
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 08/25/09 First release
-* 7.5 mus 03/10/21 Added new set of Xil_TestMem32, Xil_TestMem16 and
-* Xil_TestMem8 APIs to support memory test for memory
-* regions mapped at extended addresses
-* (addresses > 4 GB). These new set of APIs would be
-* compiled only for 32 bit Microblaze processor, if
-* XPAR_MICROBLAZE_ADDR_SIZE is greater than 32.
-* It fixes CR#1089129.
-*
-*
-* @note
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "fsbl.h"
-#include "nor.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-extern u32 FlashReadBaseAddress;
-
-/******************************************************************************/
-/******************************************************************************/
-/**
-*
-* This function initializes the controller for the NOR FLASH interface.
-*
-* @param None
-*
-* @return None
-*
-* @note None.
-*
-****************************************************************************/
-void InitNor(void)
-{
-
- /*
- * Set up the base address for access
- */
- FlashReadBaseAddress = XPS_NOR_BASEADDR;
-}
-
-/******************************************************************************/
-/**
-*
-* This function provides the NOR FLASH interface for the Simplified header
-* functionality.
-*
-* @param SourceAddress is address in FLASH data space
-* @param DestinationAddress is address in OCM data space
-* @param LengthBytes is the data length to transfer in bytes
-*
-* @return
-* - XST_SUCCESS if the write completes correctly
-* - XST_FAILURE if the write fails to completes correctly
-*
-* @note None.
-*
-****************************************************************************/
-u32 NorAccess(u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
-{
- u32 Data;
- u32 Count;
- u32 *SourceAddr;
- u32 *DestAddr;
- u32 LengthWords;
-
- /*
- * check for non-word tail
- * add bytes to cover the end
- */
- if ((LengthBytes%4) != 0){
-
- LengthBytes += (4 - (LengthBytes & 0x00000003));
- }
-
- LengthWords = LengthBytes >> WORD_LENGTH_SHIFT;
-
- SourceAddr = (u32 *)(SourceAddress + FlashReadBaseAddress);
- DestAddr = (u32 *)(DestinationAddress);
-
- /*
- * Word transfers, endianism isn't an issue
- */
- for (Count=0; Count < LengthWords; Count++){
-
- Data = Xil_In32((u32)(SourceAddr++));
- Xil_Out32((u32)(DestAddr++), Data);
- }
-
- return XST_SUCCESS;
-}
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/54/f038e5585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/54/f038e5585243001d18b399c1eb9b3628
deleted file mode 100644
index 125fe7f..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/54/f038e5585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,202 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file translation_table.S
-*
-* @addtogroup a9_boot_code
-* @{
-*
translation_table.S
-* The translation_table.S contains a static page table required by MMU for
-* cortex-A9. This translation table is flat mapped (input address = output
-* address) with default memory attributes defined for zynq architecture. It
-* utilizes short descriptor translation table format with each section defining
-* 1 MB of memory.
-*
-* The overview of translation table memory attributes is described below.
-*
-*| | Memory Range | Definition in Translation Table |
-*|-----------------------|-------------------------|-----------------------------------|
-*| DDR | 0x00000000 - 0x3FFFFFFF | Normal write-back Cacheable |
-*| PL | 0x40000000 - 0xBFFFFFFF | Strongly Ordered |
-*| Reserved | 0xC0000000 - 0xDFFFFFFF | Unassigned |
-*| Memory mapped devices | 0xE0000000 - 0xE02FFFFF | Device Memory |
-*| Reserved | 0xE0300000 - 0xE0FFFFFF | Unassigned |
-*| NAND, NOR | 0xE1000000 - 0xE3FFFFFF | Device memory |
-*| SRAM | 0xE4000000 - 0xE5FFFFFF | Normal write-back Cacheable |
-*| Reserved | 0xE6000000 - 0xF7FFFFFF | Unassigned |
-*| AMBA APB Peripherals | 0xF8000000 - 0xF8FFFFFF | Device Memory |
-*| Reserved | 0xF9000000 - 0xFBFFFFFF | Unassigned |
-*| Linear QSPI - XIP | 0xFC000000 - 0xFDFFFFFF | Normal write-through cacheable |
-*| Reserved | 0xFE000000 - 0xFFEFFFFF | Unassigned |
-*| OCM | 0xFFF00000 - 0xFFFFFFFF | Normal inner write-back cacheable |
-*
-* For region 0x00000000 - 0x3FFFFFFF, a system where DDR is less than 1 GB,
-* region after DDR and before PL is marked as undefined/reserved in translation
-* table. In 0xF8000000 - 0xF8FFFFFF, 0xF8000C00 - 0xF8000FFF, 0xF8010000 -
-* 0xF88FFFFF and 0xF8F03000 to 0xF8FFFFFF are reserved but due to granual size
-* of 1 MB, it is not possible to define separate regions for them. For region
-* 0xFFF00000 - 0xFFFFFFFF, 0xFFF00000 to 0xFFFB0000 is reserved but due to 1MB
-* granual size, it is not possible to define separate region for it.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 10/20/09 Initial version
-* 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
-* 3.07a sgd 07/05/2012 Configuring device address spaces as shareable device
-* instead of strongly-ordered.
-* 3.07a asa 07/17/2012 Changed the property of the ".mmu_tbl" section.
-* 4.2 pkp 09/02/2014 added entries for 0xfe000000 to 0xffefffff as reserved
-* and 0xe0000000 - 0xe1ffffff is broken down into
-* 0xe0000000 - 0xe02fffff (memory mapped divides)
-* 0xe0300000 - 0xe0ffffff (reserved) and
-* 0xe1000000 - 0xe1ffffff (NAND)
-* 5.2 pkp 06/08/2015 put a check for XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm
-* if DDR is present or not and accordingly generate the
-* translation table
-* 6.1 pkp 07/11/2016 Corrected comments for memory attributes
-* 6.8 mus 07/12/2018 Mark DDR memory as inner cacheable, if BSP is built
-* with the USE_AMP flag.
-*
-*
-*
-******************************************************************************/
-#include "xparameters.h"
- .globl MMUTable
-
- .section .mmu_tbl,"a"
-
-MMUTable:
- /* Each table entry occupies one 32-bit word and there are
- * 4096 entries, so the entire table takes up 16KB.
- * Each entry covers a 1MB section.
- */
-.set SECT, 0
-
-#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR
-.set DDR_START, XPAR_PS7_DDR_0_S_AXI_BASEADDR
-.set DDR_END, XPAR_PS7_DDR_0_S_AXI_HIGHADDR
-.set DDR_SIZE, (DDR_END - DDR_START)+1
-.set DDR_REG, DDR_SIZE/0x100000
-#else
-.set DDR_REG, 0
-#endif
-
-.set UNDEF_REG, 0x3FF - DDR_REG
-
-#ifndef USE_AMP
- /*0x00000000 - 0x00100000 (inner and outer cacheable )*/
-.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
-#else
- /*0x00000000 - 0x00100000 (inner cacheable )*/
-.word SECT + 0x14de6 /* S=b1 TEX=b100 AP=b11, Domain=b1111, C=b0, B=b1 */
-#endif
-.set SECT, SECT+0x100000
-
-.rept DDR_REG /* (DDR Cacheable) */
-.word SECT + 0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept UNDEF_REG /* (unassigned/reserved).
- * Generates a translation fault if accessed */
-.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-
-.rept 0x0400 /* 0x40000000 - 0x7fffffff (FPGA slave0) */
-.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0400 /* 0x80000000 - 0xbfffffff (FPGA slave1) */
-.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0200 /* 0xc0000000 - 0xdfffffff (unassigned/reserved).
- * Generates a translation fault if accessed */
-.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x003 /* 0xe0000000 - 0xe02fffff (Memory mapped devices)
- * UART/USB/IIC/SPI/CAN/GEM/GPIO/QSPI/SD/NAND */
-.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0D /* 0xe0300000 - 0xe0ffffff (unassigned/reserved).
- * Generates a translation fault if accessed */
-.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0010 /* 0xe1000000 - 0xe1ffffff (NAND) */
-.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0020 /* 0xe2000000 - 0xe3ffffff (NOR) */
-.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0020 /* 0xe4000000 - 0xe5ffffff (SRAM) */
-.word SECT + 0xc0e /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0120 /* 0xe6000000 - 0xf7ffffff (unassigned/reserved).
- * Generates a translation fault if accessed */
-.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-/* 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and
- 0xf8f03000 to 0xf8ffffff are reserved but due to granual size of
- 1MB, it is not possible to define separate regions for them */
-
-.rept 0x0010 /* 0xf8000000 - 0xf8ffffff (AMBA APB Peripherals) */
-
-.word SECT + 0xc06 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0030 /* 0xf9000000 - 0xfbffffff (unassigned/reserved).
- * Generates a translation fault if accessed */
-.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x0020 /* 0xfc000000 - 0xfdffffff (Linear QSPI - XIP) */
-.word SECT + 0xc0a /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-.rept 0x001F /* 0xfe000000 - 0xffefffff (unassigned/reserved).
- * Generates a translation fault if accessed */
-.word SECT + 0x0 /* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
-.set SECT, SECT+0x100000
-.endr
-
-/* 0xfff00000 to 0xfffb0000 is reserved but due to granual size of
- 1MB, it is not possible to define separate region for it
-
- 0xfff00000 - 0xffffffff
- 256K OCM when mapped to high address space
- inner-cacheable */
-.word SECT + 0x4c0e /* S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 */
-.set SECT, SECT+0x100000
-
-.end
-/**
-* @} End of "addtogroup a9_boot_code".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/55/011457565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/55/011457565243001d18b399c1eb9b3628
deleted file mode 100644
index 4b289a7..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/55/011457565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,43 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_hal.h
-*
-* Contains all the HAL header files.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/28/09 Initial release
-*
-*
-*
-* @note
-*
-******************************************************************************/
-
-#ifndef XIL_HAL_H
-#define XIL_HAL_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xil_cache.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-#include "xil_exception.h"
-#include "xil_types.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/55/302e75575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/55/302e75575243001d18b399c1eb9b3628
deleted file mode 100644
index d8aef59..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/55/302e75575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,169 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xenv.h
-*
-* Defines common services that are typically found in a host operating.
-* environment. This include file simply includes an OS specific file based
-* on the compile-time constant BUILD_ENV_*, where * is the name of the target
-* environment.
-*
-* All services are defined as macros.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b ch 10/24/02 Added XENV_LINUX
-* 1.00a rmm 04/17/02 First release
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XENV_H /* prevent circular inclusions */
-#define XENV_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * Select which target environment we are operating under
- */
-
-/* VxWorks target environment */
-#if defined XENV_VXWORKS
-#include "xenv_vxworks.h"
-
-/* Linux target environment */
-#elif defined XENV_LINUX
-#include "xenv_linux.h"
-
-/* Unit test environment */
-#elif defined XENV_UNITTEST
-#include "ut_xenv.h"
-
-/* Integration test environment */
-#elif defined XENV_INTTEST
-#include "int_xenv.h"
-
-/* Standalone environment selected */
-#else
-#include "xenv_standalone.h"
-#endif
-
-
-/*
- * The following comments specify the types and macro wrappers that are
- * expected to be defined by the target specific header files
- */
-
-/**************************** Type Definitions *******************************/
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP
- *
- * A structure that contains a time stamp used by other time stamp macros
- * defined below. This structure is processor dependent.
- */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- *
- * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
- *
- * Copies a non-overlapping block of memory.
- *
- * @param DestPtr is the destination address to copy data to.
- * @param SrcPtr is the source address to copy data from.
- * @param Bytes is the number of bytes to copy.
- *
- * @return None
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
- *
- * Fills an area of memory with constant data.
- *
- * @param DestPtr is the destination address to set.
- * @param Data contains the value to set.
- * @param Bytes is the number of bytes to set.
- *
- * @return None
- */
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
- *
- * Samples the processor's or external timer's time base counter.
- *
- * @param StampPtr is the storage for the retrieved time stamp.
- *
- * @return None
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
- *
- * Computes the delta between the two time stamps.
- *
- * @param Stamp1Ptr - First sampled time stamp.
- * @param Stamp1Ptr - Sedond sampled time stamp.
- *
- * @return An unsigned int value with units of microseconds.
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
- *
- * Computes the delta between the two time stamps.
- *
- * @param Stamp1Ptr - First sampled time stamp.
- * @param Stamp1Ptr - Sedond sampled time stamp.
- *
- * @return An unsigned int value with units of milliseconds.
- */
-
-/*****************************************************************************//**
- *
- * XENV_USLEEP(unsigned delay)
- *
- * Delay the specified number of microseconds.
- *
- * @param delay is the number of microseconds to delay.
- *
- * @return None
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/55/44d5ad585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/55/44d5ad585243001d18b399c1eb9b3628
deleted file mode 100644
index 53eac10..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/55/44d5ad585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,25 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/* The errno variable is stored in the reentrancy structure. This
- function returns its address for use by the macro errno defined in
- errno.h. */
-
-#include
-#include
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) sint32 * __errno (void);
-}
-#endif
-
-__attribute__((weak)) sint32 *
-__errno (void)
-{
- return &_REENT->_errno;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/55/505e09555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/55/505e09555243001d18b399c1eb9b3628
deleted file mode 100644
index 517deea..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/55/505e09555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,277 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file boot.S
-*
-* @addtogroup a53_32_boot_code Cortex A53 32bit Processor Boot Code
-* @{
-*
boot.S
-* The boot.S file contains a minimal set of code for transferring control from the
-* processor reset location to the start of the application. The boot code performs
-* minimum configuration which is required for an application to run starting from
-* processor reset state of the processor. Below is a sequence illustrating what all
-* configuration is performed before control reaches to main function.
-*
-* 1. Program vector table base for exception handling
-* 2. Invalidate instruction cache, data cache and TLBs
-* 3. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine,
-* abort, system)
-* 4. Program counter frequency
-* 5. Configure MMU with short descriptor translation table format and program
-* base address of translation table
-* 6. Enable data cache, instruction cache and MMU
-* 7. Transfer control to _start which clears BSS sections and runs global
-* constructor before jumping to main application
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 5.4 pkp 09/11/15 Enable I-Cache and D-Cache in the initialization
-* 6.0 pkp 07/25/16 Program the counter frequency
-* 6.4 mus 07/25/17 Set VFP enable bit in FPEXC register, to support
-* hard floating point in BSP
-*
-*
-*
-******************************************************************************/
-
-#include "xparameters.h"
-
-
-.globl MMUTable
-.global _prestart
-.global _boot
-.global __stack
-.global __irq_stack
-.global __supervisor_stack
-.global __abort_stack
-.global __fiq_stack
-.global __undef_stack
-.global _vector_table
-
-.set PSS_L2CC_BASE_ADDR, 0xF8F02000
-.set PSS_SLCR_BASE_ADDR, 0xF8000000
-
-.set RESERVED, 0x0fffff00
-.set TblBase , MMUTable
-.set LRemap, 0xFE00000F /* set the base address of the peripheral block as not shared */
-
-.set CRValMmuCac, 0b01000000000001 /* Enable IDC, and MMU */
-.set counterfreq, XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ
-
-/* Stack Pointer locations for boot code */
-.set Undef_stack, __undef_stack
-.set FIQ_stack, __fiq_stack
-.set Abort_stack, __abort_stack
-.set SPV_stack, __supervisor_stack
-.set IRQ_stack, __irq_stack
-.set SYS_stack, __stack
-
-.set vector_base, _vector_table
-
-.set FPEXC_EN, 0x40000000 /* FPU enable bit, (1 << 30) */
-
-.section .boot,"ax"
-
-/* this initializes the various processor modes */
-
-_prestart:
-_boot:
-
-OKToRun:
- mrc p15, 0, r0, c0, c0, 0 /* Get the revision */
- and r5, r0, #0x00f00000
- and r6, r0, #0x0000000f
- orr r6, r6, r5, lsr #20-4
-
- /* set VBAR to the _vector_table address in linker script */
- ldr r0, =vector_base
- mcr p15, 0, r0, c12, c0, 0
-
- /* Invalidate caches and TLBs */
- mov r0,#0 /* r0 = 0 */
- mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
- mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
- mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */
- bl invalidate_dcache /* invalidate dcache */
-
- /* Disable MMU, if enabled */
- mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */
- bic r0, r0, #0x1 /* clear bit 0 */
- mcr p15, 0, r0, c1, c0, 0 /* write value back */
-
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the irq stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x12 /* IRQ mode */
- msr cpsr, r2
- ldr r13,=IRQ_stack /* IRQ stack pointer */
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the supervisor stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x13 /* supervisor mode */
- msr cpsr, r2
- ldr r13,=SPV_stack /* Supervisor stack pointer */
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the Abort stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x17 /* Abort mode */
- msr cpsr, r2
- ldr r13,=Abort_stack /* Abort stack pointer */
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the FIQ stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x11 /* FIQ mode */
- msr cpsr, r2
- ldr r13,=FIQ_stack /* FIQ stack pointer */
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the Undefine stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x1b /* Undefine mode */
- msr cpsr, r2
- ldr r13,=Undef_stack /* Undefine stack pointer */
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the system stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x1F /* SYS mode */
- msr cpsr, r2
- ldr r13,=SYS_stack /* SYS stack pointer */
-
- /* program the timer counter frequency */
- ldr r0,=counterfreq
- mcr 15,0,r0,c14,c0,0
-
- mov r0,#0
- mcr 15,0,r0,c2,c0,2 /* N = 0 to use ttbr0 */
-
- /* Write to ACTLR */
- mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR */
- orr r0, r0, #(1 << 0) /* Enable access to CPUECTLR */
- orr r0, r0, #(1 << 1)
- mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR */
-
- /* Write to CPUECTLR */
- mrrc p15, 1, r0, r1, c15 /* Read CPUECTLR */
- orr r0, r0, #(0x01 << 6) /* Set SMPEN bit */
- mcrr p15, 1, r0, r1, c15 /* Write CPUECTLR */
-
- /* enable MMU and cache */
- ldr r0,=TblBase /* Load MMU translation table base */
- orr r0, r0, #0x5B /* Outer-cacheable, WB */
- mcr 15, 0, r0, c2, c0, 0 /* TTB0 */
- mov r0,#0x5B
- mcr p15,0,r0,c2,c0,1
- mvn r0,#0 /* Load MMU domains -- all ones=manager */
- mcr p15,0,r0,c3,c0,0
-
- /* Enable mmu, icahce and dcache */
- mrc p15,0,r0,c1,c0,0
- bic r0, r0, #(0x1 << 13)
- orr r0, r0, #(0x1 << 12) /* enable I-cache */
- orr r0, r0, #(0x1 << 2) /* enable D-Cache */
- orr r0, r0, #0x1 /* enable MMU */
- dsb /* dsb allow the MMU to start up */
- mcr p15,0,r0,c1,c0,0 /* Enable cache and MMU */
- isb /* isb flush prefetch buffer */
-
- mov r0, r0
- mrc p15, 0, r1, c1, c0, 2 /* read cp access control register (CACR) into r1 */
- orr r1, r1, #(0xf << 20) /* enable full access for p10 & p11 */
- mcr p15, 0, r1, c1, c0, 2 /* write back into CACR */
-
- /* enable vfp */
- vmrs r1, FPEXC /* read the exception register */
- orr r1,r1, #FPEXC_EN /* set VFP enable bit, leave the others in orig state */
- vmsr FPEXC, r1 /* write back the exception register */
-
- mrc p15,0,r0,c1,c0,0 /* flow prediction enable */
- orr r0, r0, #(0x01 << 11) /* #0x8000 */
- mcr p15,0,r0,c1,c0,0
-
- mrc p15,0,r0,c1,c0,1 /* read Auxiliary Control Register */
- orr r0, r0, #(0x1 << 2) /* enable Dside prefetch */
- orr r0, r0, #(0x1 << 1) /* enable L2 Prefetch hint */
- mcr p15,0,r0,c1,c0,1 /* write Auxiliary Control Register */
-
- mrs r0, cpsr /* get the current PSR */
- bic r0, r0, #0x100 /* enable asynchronous abort exception */
- msr cpsr_xsf, r0
-
-
- b _startup /* jump to C startup code */
- and r0, r0, r0 /* no op */
-
-.Ldone: b .Ldone /* Paranoia: we should never get here */
-
-
-/*
- *************************************************************************
- *
- * invalidate_dcache - invalidate the entire d-cache by set/way
- *
- * Note: for Cortex-A53, there is no cp instruction for invalidating
- * the whole D-cache. Need to invalidate each line.
- *
- *************************************************************************
- */
-invalidate_dcache:
- mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */
- ands r3, r0, #0x7000000
- mov r3, r3, lsr #23 /* cache level value (naturally aligned) */
- beq finished
- mov r10, #0 /* start with level 0 */
-loop1:
- add r2, r10, r10, lsr #1 /* work out 3xcachelevel */
- mov r1, r0, lsr r2 /* bottom 3 bits are the Cache type for this level */
- and r1, r1, #7 /* get those 3 bits alone */
- cmp r1, #2
- blt skip /* no cache or only instruction cache at this level */
- mcr p15, 2, r10, c0, c0, 0 /* write the Cache Size selection register */
- isb /* isb to sync the change to the CacheSizeID reg */
- mrc p15, 1, r1, c0, c0, 0 /* reads current Cache Size ID register */
- and r2, r1, #7 /* extract the line length field */
- add r2, r2, #4 /* add 4 for the line length offset (log2 16 bytes) */
- ldr r4, =0x3ff
- ands r4, r4, r1, lsr #3 /* r4 is the max number on the way size (right aligned) */
- clz r5, r4 /* r5 is the bit position of the way size increment */
- ldr r7, =0x7fff
- ands r7, r7, r1, lsr #13 /* r7 is the max number of the index size (right aligned) */
-loop2:
- mov r9, r4 /* r9 working copy of the max way size (right aligned) */
-loop3:
- orr r11, r10, r9, lsl r5 /* factor in the way number and cache number into r11 */
- orr r11, r11, r7, lsl r2 /* factor in the index number */
- mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */
- subs r9, r9, #1 /* decrement the way number */
- bge loop3
- subs r7, r7, #1 /* decrement the index */
- bge loop2
-skip:
- add r10, r10, #2 /* increment the cache number */
- cmp r3, r10
- bgt loop1
-
-finished:
- mov r10, #0 /* switch back to cache level 0 */
- mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
- dsb
- isb
-
- bx lr
-
-.end
-/**
-* @} End of "addtogroup a53_32_boot_code".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/55/80ffd8545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/55/80ffd8545243001d18b399c1eb9b3628
deleted file mode 100644
index dfcb19f..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/55/80ffd8545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,80 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xscugic_sinit.c
-* @addtogroup scugic_v4_6
-* @{
-*
-* Contains static init functions for the XScuGic driver for the Interrupt
-* Controller. See xscugic.h for a detailed description of the driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- --------------------------------------------------------
-* 1.00a drg 01/19/10 First release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.10 mus 07/17/18 Updated file to fix the various coding style issues
-* reported by checkpatch. It fixes CR#1006344.
-* 4.6 sk 08/05/21 Remove XScuGic_Config variable definition to fix
-* misrac violation.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xparameters.h"
-#include "xscugic.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* Looks up the device configuration based on the unique device ID. A table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId is the unique identifier for a device.
-*
-* @return A pointer to the XScuGic configuration structure for the
-* specified device, or NULL if the device was not found.
-*
-* @note None.
-*
-******************************************************************************/
-XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId)
-{
- XScuGic_Config *CfgPtr = NULL;
- u32 Index;
-
- for (Index = 0U; Index < (u32)XPAR_SCUGIC_NUM_INSTANCES; Index++) {
- if (XScuGic_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XScuGic_ConfigTable[Index];
- break;
- }
- }
-
- return (XScuGic_Config *)CfgPtr;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/55/81f1e6595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/55/81f1e6595243001d18b399c1eb9b3628
deleted file mode 100644
index 9df330f..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/55/81f1e6595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,171 +0,0 @@
-/*------------------------------------------------------------------------*/
-/* Sample Code of OS Dependent Functions for FatFs */
-/* (C)ChaN, 2017 */
-/*------------------------------------------------------------------------*/
-
-
-#include "ff.h"
-
-
-
-#if FF_USE_LFN == 3 /* Dynamic memory allocation */
-
-/*------------------------------------------------------------------------*/
-/* Allocate a memory block */
-/*------------------------------------------------------------------------*/
-
-void* ff_memalloc ( /* Returns pointer to the allocated memory block (null on not enough core) */
- UINT msize /* Number of bytes to allocate */
-)
-{
- return malloc(msize); /* Allocate a new memory block with POSIX API */
-}
-
-
-/*------------------------------------------------------------------------*/
-/* Free a memory block */
-/*------------------------------------------------------------------------*/
-
-void ff_memfree (
- void* mblock /* Pointer to the memory block to free (nothing to do for null) */
-)
-{
- free(mblock); /* Free the memory block with POSIX API */
-}
-
-#endif
-
-
-
-#if FF_FS_REENTRANT /* Mutal exclusion */
-
-/*------------------------------------------------------------------------*/
-/* Create a Synchronization Object */
-/*------------------------------------------------------------------------*/
-/* This function is called in f_mount() function to create a new
-/ synchronization object for the volume, such as semaphore and mutex.
-/ When a 0 is returned, the f_mount() function fails with FR_INT_ERR.
-*/
-
-//const osMutexDef_t Mutex[FF_VOLUMES]; /* CMSIS-RTOS */
-
-
-int ff_cre_syncobj ( /* 1:Function succeeded, 0:Could not create the sync object */
- BYTE vol, /* Corresponding volume (logical drive number) */
- FF_SYNC_t* sobj /* Pointer to return the created sync object */
-)
-{
- /* Win32 */
- *sobj = CreateMutex(NULL, FALSE, NULL);
- return (int)(*sobj != INVALID_HANDLE_VALUE);
-
- /* uITRON */
-// T_CSEM csem = {TA_TPRI,1,1};
-// *sobj = acre_sem(&csem);
-// return (int)(*sobj > 0);
-
- /* uC/OS-II */
-// OS_ERR err;
-// *sobj = OSMutexCreate(0, &err);
-// return (int)(err == OS_NO_ERR);
-
- /* FreeRTOS */
-// *sobj = xSemaphoreCreateMutex();
-// return (int)(*sobj != NULL);
-
- /* CMSIS-RTOS */
-// *sobj = osMutexCreate(Mutex + vol);
-// return (int)(*sobj != NULL);
-}
-
-
-/*------------------------------------------------------------------------*/
-/* Delete a Synchronization Object */
-/*------------------------------------------------------------------------*/
-/* This function is called in f_mount() function to delete a synchronization
-/ object that created with ff_cre_syncobj() function. When a 0 is returned,
-/ the f_mount() function fails with FR_INT_ERR.
-*/
-
-int ff_del_syncobj ( /* 1:Function succeeded, 0:Could not delete due to an error */
- FF_SYNC_t sobj /* Sync object tied to the logical drive to be deleted */
-)
-{
- /* Win32 */
- return (int)CloseHandle(sobj);
-
- /* uITRON */
-// return (int)(del_sem(sobj) == E_OK);
-
- /* uC/OS-II */
-// OS_ERR err;
-// OSMutexDel(sobj, OS_DEL_ALWAYS, &err);
-// return (int)(err == OS_NO_ERR);
-
- /* FreeRTOS */
-// vSemaphoreDelete(sobj);
-// return 1;
-
- /* CMSIS-RTOS */
-// return (int)(osMutexDelete(sobj) == osOK);
-}
-
-
-/*------------------------------------------------------------------------*/
-/* Request Grant to Access the Volume */
-/*------------------------------------------------------------------------*/
-/* This function is called on entering file functions to lock the volume.
-/ When a 0 is returned, the file function fails with FR_TIMEOUT.
-*/
-
-int ff_req_grant ( /* 1:Got a grant to access the volume, 0:Could not get a grant */
- FF_SYNC_t sobj /* Sync object to wait */
-)
-{
- /* Win32 */
- return (int)(WaitForSingleObject(sobj, FF_FS_TIMEOUT) == WAIT_OBJECT_0);
-
- /* uITRON */
-// return (int)(wai_sem(sobj) == E_OK);
-
- /* uC/OS-II */
-// OS_ERR err;
-// OSMutexPend(sobj, FF_FS_TIMEOUT, &err));
-// return (int)(err == OS_NO_ERR);
-
- /* FreeRTOS */
-// return (int)(xSemaphoreTake(sobj, FF_FS_TIMEOUT) == pdTRUE);
-
- /* CMSIS-RTOS */
-// return (int)(osMutexWait(sobj, FF_FS_TIMEOUT) == osOK);
-}
-
-
-/*------------------------------------------------------------------------*/
-/* Release Grant to Access the Volume */
-/*------------------------------------------------------------------------*/
-/* This function is called on leaving file functions to unlock the volume.
-*/
-
-void ff_rel_grant (
- FF_SYNC_t sobj /* Sync object to be signaled */
-)
-{
- /* Win32 */
- ReleaseMutex(sobj);
-
- /* uITRON */
-// sig_sem(sobj);
-
- /* uC/OS-II */
-// OSMutexPost(sobj);
-
- /* FreeRTOS */
-// xSemaphoreGive(sobj);
-
- /* CMSIS-RTOS */
-// osMutexRelease(sobj);
-}
-
-#endif
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/55/90fb6b565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/55/90fb6b565243001d18b399c1eb9b3628
deleted file mode 100644
index 14446f4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/55/90fb6b565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,143 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xplatform_info.c
-* @addtogroup common_platform_info Hardware Platform Information
-* @{
-* This file contains information about hardware for which the code is built
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 5.00 pkp 12/15/14 Initial release
-* 5.04 pkp 01/12/16 Added platform information support for Cortex-A53 32bit
-* mode
-* 6.00 mus 17/08/16 Removed unused variable from XGetPlatform_Info
-* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
-* function for PMUFW.
-* ms 06/13/17 Added PSU_PMU macro to provide support of
-* XGetPlatform_Info function for PMUFW.
-* mus 08/17/17 Add EL1 NS mode support for
-* XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info
-* APIs.
-* 7.0 aru 03/15/19 Check for versal before aarch64 and armr5
-* in XGetPlatform_Info()
-* 7.2 adk 08/01/20 Added versal support for the XGetPSVersion_Info function.
-* 7.6 mus 08/23/21 Updated prototypes for functions which are not taking any
-* arguments with void keyword. This has been done to fix
-* compilation warnings with "-Wstrict-prototypes" flag.
-* It fixes CR#1108601.
-* 7.6 mus 08/30/21 Updated flag checking to fix compilation warnings
-* reported with "-Wundef" flag. It fixes CR#1108601.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xplatform_info.h"
-#if defined (__aarch64__)
-#include "bspconfig.h"
-#include "xil_smc.h"
-#endif
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* @brief This API is used to provide information about platform
-*
-* @return The information about platform defined in xplatform_info.h
-*
-******************************************************************************/
-u32 XGetPlatform_Info(void)
-{
-#if defined (versal)
- return XPLAT_VERSAL;
-#elif defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU)
- return XPLAT_ZYNQ_ULTRA_MP;
-#elif defined (__microblaze__)
- return XPLAT_MICROBLAZE;
-#else
- return XPLAT_ZYNQ;
-#endif
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief This API is used to provide information about zynq ultrascale MP platform
-*
-* @return The information about zynq ultrascale MP platform defined in
-* xplatform_info.h
-*
-******************************************************************************/
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
-u32 XGet_Zynq_UltraMp_Platform_info(void)
-{
-#if EL1_NONSECURE
- XSmc_OutVar reg;
- /*
- * This SMC call will return,
- * idcode - upper 32 bits of reg.Arg0
- * version - lower 32 bits of reg.Arg1
- */
- reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
- return (u32)((reg.Arg1 >> XPLAT_INFO_SHIFT) & XPLAT_INFO_MASK);
-#else
- u32 reg;
- reg = ((Xil_In32(XPLAT_PS_VERSION_ADDRESS) >> XPLAT_INFO_SHIFT )
- & XPLAT_INFO_MASK);
- return reg;
-#endif
-}
-#endif
-
-/*****************************************************************************/
-/**
-*
-* @brief This API is used to provide information about PS Silicon version
-*
-* @return The information about PS Silicon version.
-*
-******************************************************************************/
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU) || defined (versal)
-u32 XGetPSVersion_Info(void)
-{
-#if EL1_NONSECURE
- /*
- * This SMC call will return,
- * idcode - upper 32 bits of reg.Arg0
- * version - lower 32 bits of reg.Arg1
- */
- XSmc_OutVar reg;
- reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
- return (u32)((reg.Arg1 & XPS_VERSION_INFO_MASK) >>
- XPS_VERSION_INFO_SHIFT);
-#else
- u32 reg;
- reg = (Xil_In32(XPLAT_PS_VERSION_ADDRESS)
- & XPS_VERSION_INFO_MASK);
- return (reg >> XPS_VERSION_INFO_SHIFT);
-#endif
-}
-#endif
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/55/b1a4bf575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/55/b1a4bf575243001d18b399c1eb9b3628
deleted file mode 100644
index 5bac22a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/55/b1a4bf575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,919 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xdevcfg.c
-* @addtogroup devcfg_v3_7
-* @{
-*
-* This file contains the implementation of the interface functions for XDcfg
-* driver. Refer to the header file xdevcfg.h for more detailed information.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
-* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
-* APIs is words (32 bit) and not bytes.
-* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
-* to add information that 2 LSBs of the Source/Destination
-* address when equal to 2�b01 indicate the last DMA command
-* of an overall transfer.
-* Updated the XDcfg_Transfer function to use the
-* Destination Address passed to this API for secure transfers
-* instead of using 0xFFFFFFFF for CR 662197. This issue was
-* resulting in the failure of secure transfers of
-* non-bitstream images.
-* 2.01a nm 08/27/12 Updated the XDcfg_Transfer API to clear the
-* QUARTER_PCAP_RATE_EN bit in the control register for
-* non secure writes for CR 675543.
-* 2.02a nm 01/31/13 Fixed CR# 679335.
-* Added Setting and Clearing the internal PCAP loopback.
-* Removed code for enabling/disabling AES engine as BootROM
-* locks down this setting.
-* Fixed CR# 681976.
-* Skip Checking the PCFG_INIT in case of non-secure DMA
-* loopback.
-* Fixed CR# 699558.
-* XDcfg_Transfer fails to transfer data in loopback mode.
-* 2.03a nm 04/19/13 Fixed CR# 703728.
-* Updated the register definitions as per the latest TRM
-* version UG585 (v1.4) November 16, 2012.
-* 3.0 kpc 21/02/14 Implemented new function XDcfg_ClearControlRegister
-* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
-* updated driver code with != instead of ==,
-* while checking for Interrupt Status with DMA and
-* PCAP Done Mask
-* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
-* XDCFG_INT_STS_OFFSET) &
-* XDCFG_IXR_D_P_DONE_MASK) !=
-* XDCFG_IXR_D_P_DONE_MASK);
-*
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xdevcfg.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/****************************************************************************/
-/**
-*
-* Initialize the Device Config Interface driver. This function
-* must be called before other functions of the driver are called.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param ConfigPtr is the config structure.
-* @param EffectiveAddress is the base address for the device. It could be
-* a virtual address if address translation is supported in the
-* system, otherwise it is the physical address.
-*
-* @return
-* - XST_SUCCESS if initialization was successful.
-* - XST_DEVICE_IS_STARTED if the device has already been started.
-*
-* @note The very first APB access to the Device Configuration Interface
-* block needs to be a write to the UNLOCK register with the value
-* of 0x757BDF0D. This step is to be done once after reset, any
-* other APB access has to come after this. The APB access is
-* considered illegal if the step is not done or if it is done
-* incorrectly. Furthermore, if any of efuse_sec_cfg[5:0] is high,
-* the following additional actions would be carried out.
-* In other words, if all bits are low, the following steps are not
-* done.
-* 1. AES is disabled
-* 2. All APB writes disabled
-* 3. SoC debug fully enabled
-*
-******************************************************************************/
-int XDcfg_CfgInitialize(XDcfg *InstancePtr,
- XDcfg_Config *ConfigPtr, u32 EffectiveAddress)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
-
- /*
- * If the device is started, disallow the initialize and return a
- * status indicating it is started. This allows the user to stop the
- * device and reinitialize, but prevents a user from inadvertently
- * initializing.
- */
- if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
- return XST_DEVICE_IS_STARTED;
- }
-
- /*
- * Copy configuration into instance.
- */
- InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
-
- /*
- * Save the base address pointer such that the registers of the block
- * can be accessed and indicate it has not been started yet.
- */
- InstancePtr->Config.BaseAddr = EffectiveAddress;
- InstancePtr->IsStarted = 0;
-
-
- /* Unlock the Device Configuration Interface */
- XDcfg_Unlock(InstancePtr);
-
- /*
- * Indicate the instance is ready to use, successfully initialized.
- */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* The functions enables the PCAP interface by setting the PCAP mode bit in the
-* control register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return None.
-*
-* @note Enable FPGA programming from PCAP interface. Enabling this bit
-* disables all the external interfaces from programming of FPGA
-* except for ICAP. The user needs to ensure that the FPGA is
-* programmed through either PCAP or ICAP.
-*
-*****************************************************************************/
-void XDcfg_EnablePCAP(XDcfg *InstancePtr)
-{
- u32 CtrlReg;
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
- (CtrlReg | XDCFG_CTRL_PCAP_MODE_MASK));
-
-}
-
-/****************************************************************************/
-/**
-*
-* The functions disables the PCAP interface by clearing the PCAP mode bit in
-* the control register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_DisablePCAP(XDcfg *InstancePtr)
-{
- u32 CtrlReg;
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
- (CtrlReg & ( ~XDCFG_CTRL_PCAP_MODE_MASK)));
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the contents of the Control Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Mask is the 32 bit mask data to be written to the Register.
-* The mask definitions are defined in the xdevcfg_hw.h file.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask)
-{
- u32 CtrlReg;
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
- (CtrlReg | Mask));
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function Clears the specified bit positions of the Control Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Mask is the 32 bit value which holds the bit positions to be cleared.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask)
-{
- u32 CtrlReg;
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
- (CtrlReg & ~Mask));
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function reads the contents of the Control Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return A 32-bit value representing the contents of the Control
-* Register.
-* Use the XDCFG_CTRL_*_MASK constants defined in xdevcfg_hw.h to
-* interpret the returned value.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XDcfg_GetControlRegister(XDcfg *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Control Register and return the value.
- */
- return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the contents of the Lock Register. These bits
-* can only be set to a 1. They will be cleared after a Power On Reset.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Data is the 32 bit data to be written to the Register.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET, Data);
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function reads the contents of the Lock Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return A 32-bit value representing the contents of the Lock
-* Register.
-* Use the XDCFG_CR_*_MASK constants defined in xdevcfg_hw.h to
-* interpret the returned value.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XDcfg_GetLockRegister(XDcfg *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Lock Register and return the value.
- */
- return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the contents of the Configuration Register with the
-* given value.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Data is the 32 bit data to be written to the Register.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET, Data);
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function reads the contents of the Configuration Register with the
-* given value.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return A 32-bit value representing the contents of the Config
-* Register.
-* Use the XDCFG_CFG_*_MASK constants defined in xdevcfg_hw.h to
-* interpret the returned value.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET);
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the contents of the Status Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Data is the 32 bit data to be written to the Register.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET, Data);
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function reads the contents of the Status Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return A 32-bit value representing the contents of the Status
-* Register.
-* Use the XDCFG_STATUS_*_MASK constants defined in
-* xdevcfg_hw.h to interpret the returned value.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Status Register and return the value.
- */
- return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the contents of the ROM Shadow Control Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Data is the 32 bit data to be written to the Register.
-*
-* @return None.
-*
-* @note This register is can only be written and is used to control the
-* RAM shadow of 32 bit 4K page ROM pages in user mode
-*
-*****************************************************************************/
-void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_ROM_SHADOW_OFFSET,
- Data);
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function reads the contents of the Software ID Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return 32 Bit boot software ID.
-*
-* @note This register is locked for write once the system enters
-* usermode. Hence API for reading the register only is provided.
-*
-*****************************************************************************/
-u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Software ID Register and return the value.
- */
- return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_SW_ID_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the bit mask for the feature in Miscellaneous Control
-* Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Mask is the bit-mask of the feature to be set.
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask)
-{
- u32 RegData;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET,
- (RegData | Mask));
-}
-
-/****************************************************************************/
-/**
-*
-* The function reads the contents of the Miscellaneous Control Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return 32 Bit boot software ID.
-*
-* @note This register is locked for write once the system enters
-* usermode. Hence API to reading the register only is provided.
-*
-*****************************************************************************/
-u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Miscellaneous Control Register and return the value.
- */
- return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET);
-}
-
-/******************************************************************************/
-/**
-*
-* This function checks if DMA command queue is full.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return XST_SUCCESS is the DMA is busy
-* XST_FAILURE if the DMA is idle
-*
-* @note The DMA queue has a depth of two.
-*
-****************************************************************************/
-u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr)
-{
-
- u32 RegData;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Read the PCAP status register for DMA status */
- RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_STATUS_OFFSET);
-
- if ((RegData & XDCFG_STATUS_DMA_CMD_Q_F_MASK) ==
- XDCFG_STATUS_DMA_CMD_Q_F_MASK){
- return XST_SUCCESS;
- }
-
- return XST_FAILURE;
-}
-
-/******************************************************************************/
-/**
-*
-* This function initiates the DMA transfer.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param SourcePtr contains a pointer to the source memory where the data
-* is to be transferred from.
-* @param SrcWordLength is the number of words (32 bit) to be transferred
-* for the source transfer.
-* @param DestPtr contains a pointer to the destination memory
-* where the data is to be transferred to.
-* @param DestWordLength is the number of words (32 bit) to be transferred
-* for the Destination transfer.
-*
-* @return None.
-*
-* @note It is the responsibility of the caller function to ensure that
-* correct values are passed to this function.
-*
-* The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination)
-* address when equal to 2�b01 indicates the last DMA command of
-* an overall transfer.
-*
-****************************************************************************/
-void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
- u32 SrcWordLength, u32 DestWordLength)
-{
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_DMA_SRC_ADDR_OFFSET,
- SourcePtr);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_DMA_DEST_ADDR_OFFSET,
- DestPtr);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_DMA_SRC_LEN_OFFSET,
- SrcWordLength);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_DMA_DEST_LEN_OFFSET,
- DestWordLength);
-}
-
-/******************************************************************************/
-/**
-*
-* This function Implements the DMA Read Command. This command is used to
-* transfer the image data from FPGA to the external memory.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param SourcePtr contains a pointer to the source memory where the data
-* is to be transferred from.
-* @param SrcWordLength is the number of words (32 bit) to be transferred
-* for the source transfer.
-* @param DestPtr contains a pointer to the destination memory
-* where the data is to be transferred to.
-* @param DestWordLength is the number of words (32 bit) to be transferred
-* for the Destination transfer.
-*
-* @return - XST_INVALID_PARAM if source address/length is invalid.
-* - XST_SUCCESS if DMA transfer initiated properly.
-*
-* @note None.
-*
-****************************************************************************/
-static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr,
- u32 SrcWordLength, u32 DestPtr,
- u32 DestWordLength)
-{
- u32 IntrReg;
-
- /*
- * Send READ Frame command to FPGA
- */
- XDcfg_InitiateDma(InstancePtr, SourcePtr, XDCFG_DMA_INVALID_ADDRESS,
- SrcWordLength, 0);
-
- /*
- * Store the enabled interrupts to enable before the actual read
- * transfer is initiated and Disable all the interrupts temporarily.
- */
- IntrReg = XDcfg_IntrGetEnabled(InstancePtr);
- XDcfg_IntrDisable(InstancePtr, XDCFG_IXR_ALL_MASK);
-
- /*
- * Wait till you get the DMA done for the read command sent
- */
- while ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_STS_OFFSET) &
- XDCFG_IXR_D_P_DONE_MASK) !=
- XDCFG_IXR_D_P_DONE_MASK);
- /*
- * Enable the previously stored Interrupts .
- */
- XDcfg_IntrEnable(InstancePtr, IntrReg);
-
- /*
- * Initiate the DMA write command.
- */
- XDcfg_InitiateDma(InstancePtr, XDCFG_DMA_INVALID_ADDRESS, (u32)DestPtr,
- 0, DestWordLength);
-
- return XST_SUCCESS;
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function starts the DMA transfer. This function only starts the
-* operation and returns before the operation may be completed.
-* If the interrupt is enabled, an interrupt will be generated when the
-* operation is completed, otherwise it is necessary to poll the Status register
-* to determine when it is completed. It is the responsibility of the caller to
-* determine when the operation is completed by handling the generated interrupt
-* or polling the Status Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param SourcePtr contains a pointer to the source memory where the data
-* is to be transferred from.
-* @param SrcWordLength is the number of words (32 bit) to be transferred
-* for the source transfer.
-* @param DestPtr contains a pointer to the destination memory
-* where the data is to be transferred to.
-* @param DestWordLength is the number of words (32 bit) to be transferred
-* for the Destination transfer.
-* @param TransferType contains the type of PCAP transfer being requested.
-* The definitions can be found in the xdevcfg.h file.
-* @return
-* - XST_SUCCESS.if DMA transfer initiated successfully
-* - XST_DEVICE_BUSY if DMA is busy
-* - XST_INVALID_PARAM if invalid Source / Destination address
-* is sent or an invalid Source / Destination length is
-* sent
-*
-* @note It is the responsibility of the caller to ensure that the cache
-* is flushed and invalidated both before the DMA operation is
-* started and after the DMA operation completes if the memory
-* pointed to is cached. The caller must also ensure that the
-* pointers contain physical address rather than a virtual address
-* if address translation is being used.
-*
-* The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination)
-* address when equal to 2�b01 indicates the last DMA command of
-* an overall transfer.
-*
-*****************************************************************************/
-u32 XDcfg_Transfer(XDcfg *InstancePtr,
- void *SourcePtr, u32 SrcWordLength,
- void *DestPtr, u32 DestWordLength,
- u32 TransferType)
-{
-
- u32 CtrlReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- if (XDcfg_IsDmaBusy(InstancePtr) == XST_SUCCESS) {
- return XST_DEVICE_BUSY;
- }
-
- /*
- * Check whether the fabric is in initialized state
- */
- if ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET)
- & XDCFG_STATUS_PCFG_INIT_MASK) == 0) {
- /*
- * We don't need to check PCFG_INIT to be high for
- * non-encrypted loopback transfers.
- */
- if (TransferType != XDCFG_CONCURRENT_NONSEC_READ_WRITE) {
- return XST_FAILURE;
- }
- }
-
- if ((TransferType == XDCFG_SECURE_PCAP_WRITE) ||
- (TransferType == XDCFG_NON_SECURE_PCAP_WRITE)) {
-
- /* Check for valid source pointer and length */
- if ((!SourcePtr) || (SrcWordLength == 0)) {
- return XST_INVALID_PARAM;
- }
-
- /* Clear internal PCAP loopback */
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET);
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET, (CtrlReg &
- ~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
-
- if (TransferType == XDCFG_NON_SECURE_PCAP_WRITE) {
- /*
- * Clear QUARTER_PCAP_RATE_EN bit
- * so that the PCAP data is transmitted every clock
- */
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET, (CtrlReg &
- ~XDCFG_CTRL_PCAP_RATE_EN_MASK));
-
- }
- if (TransferType == XDCFG_SECURE_PCAP_WRITE) {
- /*
- * AES engine handles only 8 bit data every clock cycle.
- * Hence, Encrypted PCAP data which is 32 bit data can
- * only be sent in every 4 clock cycles. Set the control
- * register QUARTER_PCAP_RATE_EN bit to achieve this
- * operation.
- */
- XDcfg_SetControlRegister(InstancePtr,
- XDCFG_CTRL_PCAP_RATE_EN_MASK);
- }
-
- XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr,
- (u32)DestPtr, SrcWordLength, DestWordLength);
-
- }
-
- if (TransferType == XDCFG_PCAP_READBACK) {
-
- if ((!DestPtr) || (DestWordLength == 0)) {
-
- return XST_INVALID_PARAM;
- }
-
- /* Clear internal PCAP loopback */
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET);
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET, (CtrlReg &
- ~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
-
- /*
- * For PCAP readback of FPGA configuration register or memory,
- * the read command is first sent (written) to the FPGA fabric
- * which responds by returning the required read data. Read data
- * from the FPGA is captured if pcap_radata_v is active.A DMA
- * read transfer is required to obtain the readback command,
- * which is then sent to the FPGA, followed by a DMA write
- * transfer to support this mode of operation.
- */
- return XDcfg_PcapReadback(InstancePtr,
- (u32)SourcePtr, SrcWordLength,
- (u32)DestPtr, DestWordLength);
- }
-
-
- if ((TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) ||
- (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE)) {
-
- if ((!SourcePtr) || (SrcWordLength == 0) ||
- (!DestPtr) || (DestWordLength == 0)) {
- return XST_INVALID_PARAM;
- }
-
- if (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE) {
- /* Enable internal PCAP loopback */
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET);
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET, (CtrlReg |
- XDCFG_MCTRL_PCAP_LPBK_MASK));
-
- /*
- * Clear QUARTER_PCAP_RATE_EN bit
- * so that the PCAP data is transmitted every clock
- */
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET, (CtrlReg &
- ~XDCFG_CTRL_PCAP_RATE_EN_MASK));
-
- }
- if (TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) {
- /* Clear internal PCAP loopback */
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET);
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET, (CtrlReg &
- ~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
-
- /*
- * Set the QUARTER_PCAP_RATE_EN bit
- * so that the PCAP data is transmitted every 4 clock
- * cycles, this is required for encrypted data.
- */
- XDcfg_SetControlRegister(InstancePtr,
- XDCFG_CTRL_PCAP_RATE_EN_MASK);
- }
-
- XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr,
- (u32)DestPtr, SrcWordLength, DestWordLength);
- }
-
- return XST_SUCCESS;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/56/10e940555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/56/10e940555243001d18b399c1eb9b3628
deleted file mode 100644
index 396a0ab..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/56/10e940555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,94 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_mmu.h
-*
-* @addtogroup a53_64_mmu_apis Cortex A53 64bit Processor MMU Handling
-*
-* MMU function equip users to modify default memory attributes of MMU table as
-* per the need.
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00 pkp 05/29/14 First release
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#ifndef XIL_MMU_H
-#define XIL_MMU_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/**
- *@cond nocomments
- */
-
-/* Memory type */
-#define NORM_NONCACHE 0x401UL /* Normal Non-cacheable*/
-#define STRONG_ORDERED 0x409UL /* Strongly ordered (Device-nGnRnE)*/
-#define DEVICE_MEMORY 0x40DUL /* Device memory (Device-nGnRE)*/
-#define RESERVED 0x0UL /* reserved memory*/
-
-/* Normal write-through cacheable inner shareable*/
-#define NORM_WT_CACHE 0x711UL
-
-/* Normal write back cacheable inner-shareable */
-#define NORM_WB_CACHE 0x705UL
-
-/*
- * shareability attribute only applicable to
- * normal cacheable memory
- */
-#define INNER_SHAREABLE (0x3 << 8)
-#define OUTER_SHAREABLE (0x2 << 8)
-#define NON_SHAREABLE (~(0x3 << 8))
-
-/* Execution type */
-#define EXECUTE_NEVER ((0x1 << 53) | (0x1 << 54))
-
-/* Security type */
-#define NON_SECURE (0x1 << 5)
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-/**
- *@endcond
- */
-
-void Xil_SetTlbAttributes(UINTPTR Addr, u64 attrib);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_MMU_H */
-/**
-* @} End of "addtogroup a53_64_mmu_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/56/136bcc565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/56/136bcc565243001d18b399c1eb9b3628
deleted file mode 100644
index 82dd34a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/56/136bcc565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,24 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) sint32 unlink(char8 *path);
-}
-#endif
-/*
- * unlink -- since we have no file system,
- * we just return an error.
- */
-__attribute__((weak)) sint32 unlink(char8 *path)
-{
- (void) path;
- errno = EIO;
- return (-1);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/56/414137545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/56/414137545243001d18b399c1eb9b3628
deleted file mode 100644
index fd80a0d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/56/414137545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,62 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_clocking.h
-*
-* The xil_clocking.h file contains clocking related functions and macros.
-* certain conditions.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 7.2 sd 12/11/19 First release
-* 7.2 sd 03/20/20 Added checking for isolation case
-*
-*
-******************************************************************************/
-
-#ifndef XIL_CLOCKING_H /* prevent circular inclusions */
-#define XIL_CLOCKING_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xdebug.h"
-#include "xil_printf.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xparameters.h"
-#include "xstatus.h"
-#if defined (XPAR_XCRPSU_0_DEVICE_ID)
-#include "xclockps.h"
-#else
-typedef u32 XClock_OutputClks;
-typedef u64 XClockRate;
-#endif
-
-/***************************** Include Files *********************************/
-
-
-/************************** Constant Definitions *****************************/
-
-
-XStatus Xil_ClockDisable(XClock_OutputClks ClockId);
-XStatus Xil_ClockEnable(XClock_OutputClks ClockId);
-XStatus Xil_ClockInit(void);
-XStatus Xil_ClockGet(void);
-XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate, XClockRate *SetRate);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/56/41e472575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/56/41e472575243001d18b399c1eb9b3628
deleted file mode 100644
index ee6ac60..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/56/41e472575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,646 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xemacps_hw.h
-* @addtogroup emacps_v3_15
-* @{
-*
-* This header file contains identifiers and low-level driver functions (or
-* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
-* High-level driver functions are defined in xemacps.h.
-*
-* @note
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 First release.
-* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration.
-* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype
-* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
-* to 0x1fff. This fixes the CR#744902.
-* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
-* 3.0 kvn 12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
-* XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
-* 3.0 kpc 1/23/15 Corrected the extended descriptor macro values.
-* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.0 hk 03/18/15 Added support for jumbo frames.
-* Remove "used bit set" from TX error interrupt masks.
-* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
-* 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
-* 3.8 hk 09/17/18 Fix PTP interrupt masks.
-* 3.9 hk 01/23/19 Add RX watermark support
-* 3.10 hk 05/16/19 Clear status registers properly in reset
-*
-*
-******************************************************************************/
-
-#ifndef XEMACPS_HW_H /* prevent circular inclusions */
-#define XEMACPS_HW_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address
- supported */
-#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */
-
-#ifdef __aarch64__
-#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment
- on the local bus */
-#else
-
-#define XEMACPS_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment
- on the local bus */
-#endif
-#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using
- options that impose alignment
- restrictions on the buffer data on
- the local bus */
-
-/** @name Direction identifiers
- *
- * These are used by several functions and callbacks that need
- * to specify whether an operation specifies a send or receive channel.
- * @{
- */
-#define XEMACPS_SEND 1U /**< send direction */
-#define XEMACPS_RECV 2U /**< receive direction */
-/*@}*/
-
-/** @name MDC clock division
- * currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
- * @{
- */
-typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
- MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
-} XEmacPs_MdcDiv;
-
-/*@}*/
-
-#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
- bytes, 64, 128, ... 10240 */
-#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
-
-#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a
- unit, this is HW setup */
-
-#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */
-#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */
-
-#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
-
-/* Register offset definitions. Unless otherwise noted, register access is
- * 32 bit. Names are self explained here.
- */
-
-#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */
-#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */
-#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */
-
-#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */
-#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */
-#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */
-#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */
-#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */
-
-#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */
-#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */
-#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */
-#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */
-
-#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */
-#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */
-#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */
-
-#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */
-
-#define XEMACPS_RXWATERMARK_OFFSET 0x0000007CU /**< RX watermark reg */
-
-#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */
-#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */
-
-#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */
-#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */
-#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */
-#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */
-#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */
-#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */
-#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */
-#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */
-
-#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */
-#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */
-#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */
-#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */
-
-#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */
-
-#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low
- reg */
-#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High
- reg */
-
-#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes
- transmitted counter */
-#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast
- Frames counter*/
-#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast
- Frame counter */
-#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted
- Counter */
-#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames
- Transmitted counter */
-#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte
- Frames Transmitted
- counter */
-#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte
- Frames Transmitted
- counter*/
-#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte
- Frames transmitted
- counter */
-#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte
- Frames transmitted
- counter */
-#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte
- Frames transmitted
- counter */
-#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than
- 1519 byte Frames
- transmitted counter */
-#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error
- counter */
-
-#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame
- Counter */
-#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame
- Counter */
-#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
- Counter */
-#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame
- Counter */
-#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission
- Frame Counter */
-#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense
- Error Counter */
-
-#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register
- Low */
-#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register
- High */
-
-#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames
- Received Counter */
-#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast
- Frames Received Counter */
-#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast
- Frames Received Counter */
-#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames
- Received Counter */
-#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames
- Received Counter */
-#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte
- Frames Received Counter */
-#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte
- Frames Received Counter */
-#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte
- Frames Received Counter */
-#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte
- Frames Received Counter */
-#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte
- Frames Received Counter */
-#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte
- Frames Received Counter */
-#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received
- Counter */
-#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received
- Counter */
-#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received
- Counter */
-#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence
- Error Counter */
-#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error
- Counter */
-#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */
-#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */
-#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error
- Counter */
-#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */
-#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error
- Counter */
-#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error
- Counter */
-#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error
- Counter */
-#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter
- offset, for clearing */
-
-#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */
-#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */
-#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond
- adjustment counter */
-#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond
- increment counter */
-#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second
- counter */
-#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
- nanosecond counter */
-#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second
- counter */
-#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
- nanosecond counter */
-#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit
- second counter */
-#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
- nanosecond counter */
-#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive
- second counter */
-#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
- nanosecond counter */
-
-#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status
- reg */
-#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address
- reg */
-#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address
- reg */
-#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base
- reg */
-#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base
- reg */
-#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable
- reg */
-#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable
- reg */
-#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask
- reg */
-
-/* Define some bit positions for registers. */
-
-/** @name network control register bit definitions
- * @{
- */
-#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from
- Rx SRAM */
-#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
- pause frame */
-#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */
-#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission
- after current frame */
-#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */
-
-#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to
- stat counters */
-#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic
- registers */
-#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic
- registers */
-#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */
-#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */
-#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */
-#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */
-/*@}*/
-
-/** @name network configuration register bit definitions
- * @{
- */
-#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
- non-standard preamble */
-#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */
-#define XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U /**< SGMII Enable */
-#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of
- FCS error */
-#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */
-#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum
- offload */
-#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
- Frames to memory */
-#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */
-#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */
-#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */
-#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from
- received frames */
-#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
-/**< RX length error discard */
-#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */
-#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */
-#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
-#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
-/**< External address match enable */
-#define XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U /**< PCS Select */
-#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */
-#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte
- frames reception */
-#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
- frames */
-#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
- frames */
-#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive
- broadcast frames */
-#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */
-#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */
-#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN
- frames */
-#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */
-#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */
-#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */
-/*@}*/
-
-/** @name network status register bit definitaions
- * @{
- */
-#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */
-#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */
-/*@}*/
-
-
-/** @name MAC address register word 1 mask
- * @{
- */
-#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32]
- bit[31:0] are in BOTTOM */
-/*@}*/
-
-
-/** @name DMA control register bit definitions
- * @{
- */
-#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */
-#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */
-#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */
-#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer
- size */
-#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer
- size */
-#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX
- checksum offload */
-#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */
-#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */
-#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */
-#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */
-#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */
-#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */
-#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */
-#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */
-/*@}*/
-
-/** @name transmit status register bit definitions
- * @{
- */
-#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */
-#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */
-#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */
-#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted
- mid frame */
-#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */
-#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */
-#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */
-#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */
-
-#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
- (u32)XEMACPS_TXSR_URUN_MASK | \
- (u32)XEMACPS_TXSR_BUFEXH_MASK | \
- (u32)XEMACPS_TXSR_RXOVR_MASK | \
- (u32)XEMACPS_TXSR_FRAMERX_MASK | \
- (u32)XEMACPS_TXSR_USEDREAD_MASK)
-/*@}*/
-
-/**
- * @name receive status register bit definitions
- * @{
- */
-#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */
-#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */
-#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */
-#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */
-
-#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
- (u32)XEMACPS_RXSR_RXOVR_MASK | \
- (u32)XEMACPS_RXSR_BUFFNA_MASK)
-
-#define XEMACPS_SR_ALL_MASK 0xFFFFFFFFU /**< Mask for full register */
-
-/*@}*/
-
-/**
- * @name Interrupt Q1 status register bit definitions
- * @{
- */
-#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */
-#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */
-
-#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
- (u32)XEMACPS_INTQ1SR_TXERR_MASK)
-
-/*@}*/
-
-/**
- * @name interrupts bit definitions
- * Bits definitions are same in XEMACPS_ISR_OFFSET,
- * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
- * @{
- */
-#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Pdelay_resp TXed */
-#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req TXed */
-#define XEMACPS_IXR_PTPPSRX_MASK 0x00800000U /**< PTP Pdelay_resp RXed */
-#define XEMACPS_IXR_PTPPDRRX_MASK 0x00400000U /**< PTP Pdelay_req RXed */
-
-#define XEMACPS_IXR_PTPSTX_MASK 0x00200000U /**< PTP Sync TXed */
-#define XEMACPS_IXR_PTPDRTX_MASK 0x00100000U /**< PTP Delay_req TXed */
-#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync RXed */
-#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req RXed */
-
-#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */
-#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached
- zero */
-#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
-#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */
-#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */
-#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */
-#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or
- no buffers*/
-#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */
-#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */
-#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */
-#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */
-#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */
-#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */
-#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */
-
-#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \
- (u32)XEMACPS_IXR_RETRY_MASK | \
- (u32)XEMACPS_IXR_URUN_MASK)
-
-
-#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \
- (u32)XEMACPS_IXR_RXUSED_MASK | \
- (u32)XEMACPS_IXR_RXOVR_MASK)
-
-/*@}*/
-
-/** @name PHY Maintenance bit definitions
- * @{
- */
-#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */
-#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */
-#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */
-#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */
-#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */
-#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */
-#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */
-#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */
-/*@}*/
-
-/** @name RX watermark bit definitions
- * @{
- */
-#define XEMACPS_RXWM_HIGH_MASK 0x0000FFFFU /**< RXWM high mask */
-#define XEMACPS_RXWM_LOW_MASK 0xFFFF0000U /**< RXWM low mask */
-#define XEMACPS_RXWM_LOW_SHFT_MSK 16U /**< Shift for RXWM low */
-/*@}*/
-
-/* Transmit buffer descriptor status words offset
- * @{
- */
-#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */
-#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */
-#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */
-
-/*
- * @}
- */
-
-/* Transmit buffer descriptor status words bit positions.
- * Transmit buffer descriptor consists of two 32-bit registers,
- * the first - word0 contains a 32-bit address pointing to the location of
- * the transmit data.
- * The following register - word1, consists of various information to control
- * the XEmacPs transmit process. After transmit, this is updated with status
- * information, whether the frame was transmitted OK or why it had failed.
- * @{
- */
-#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */
-#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */
-#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
-#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */
-#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */
-#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */
-#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
-#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */
-#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */
-/*
- * @}
- */
-
-/* Receive buffer descriptor status words bit positions.
- * Receive buffer descriptor consists of two 32-bit registers,
- * the first - word0 contains a 32-bit word aligned address pointing to the
- * address of the buffer. The lower two bits make up the wrap bit indicating
- * the last descriptor and the ownership bit to indicate it has been used by
- * the XEmacPs.
- * The following register - word1, contains status information regarding why
- * the frame was received (the filter match condition) as well as other
- * useful info.
- * @{
- */
-#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */
-#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
-#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */
-#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */
-#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address
- matched */
-#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */
-#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */
-#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */
-#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */
-#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */
-#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */
-#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */
-#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */
-#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */
-#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
-
-#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */
-#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */
-#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */
-/*
- * @}
- */
-
-/*
- * Define appropriate I/O access method to memory mapped I/O or other
- * interface if necessary.
- */
-
-#define XEmacPs_In32 Xil_In32
-#define XEmacPs_Out32 Xil_Out32
-
-
-/****************************************************************************/
-/**
-*
-* Read the given register.
-*
-* @param BaseAddress is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
- XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
-
-
-/****************************************************************************/
-/**
-*
-* Write the given register.
-*
-* @param BaseAddress is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
-* u32 Data)
-*
-*****************************************************************************/
-#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
- XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
-
-/************************** Function Prototypes *****************************/
-/*
- * Perform reset operation to the emacps interface
- */
-void XEmacPs_ResetHw(u32 BaseAddr);
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/56/b0600c545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/56/b0600c545243001d18b399c1eb9b3628
deleted file mode 100644
index 5b03910..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/56/b0600c545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,131 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010-2020
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, see
-*
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init_gpl.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 666666687
-#define DDR_FREQ 533333374
-#define DCI_FREQ 10158730
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 125000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 100000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 111111115
-#define WDT_FREQ 111111115
-#define TTC_FREQ 50000000
-#define CAN_FREQ 10000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 50000000
-#define FPGA1_FREQ 10000000
-#define FPGA2_FREQ 10000000
-#define FPGA3_FREQ 10000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/56/d12b72585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/56/d12b72585243001d18b399c1eb9b3628
deleted file mode 100644
index e8ae20f..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/56/d12b72585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
-Copyright DornerWorks 2016
-
-Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-following conditions are met:
-1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
-following disclaimer.
-
-THIS SOFTWARE IS PROVIDED BY DORNERWORKS FOR USE ON THE CONTRACTED PROJECT, AND ANY EXPRESS OR IMPLIED WARRANTY
-IS LIMITED TO THIS USE. FOR ALL OTHER USES THIS SOFTWARE IS PROVIDED ''AS IS'' AND ANY EXPRESS OR IMPLIED
-WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL DORNERWORKS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#include "xen.h"
-#include "hypercall.h"
-#include "arm64_ops.h"
-#include "xen_events.h"
-#include "xen_console.h"
-
-#define VA_TO_GUEST_PAGE(x) ((u64)x >> PAGE_SHIFT) //BMC set up a direct VA:PA mapping
-
-#define active_evtchns(cpu,sh,idx) \
- ((sh)->evtchn_pending[idx] & \
- ~(sh)->evtchn_mask[idx])
-
-// Structure for going about sharing a page with Xen
-struct xen_add_to_physmap
-{
- /* Which domain to change the mapping for. */
- u16 domid;
-
- /* Number of pages to go through for gmfn_range */
- u16 size;
-
- unsigned int space; /* => enum phys_map_space */
-
- /* Index into space being mapped. */
- u64 idx;
-
- /* GPFN in domid where the source mapping page should appear. */
- u64 gpfn;
-};
-typedef struct xen_add_to_physmap xen_add_to_physmap_t;
-
-struct vcpu_info {
- u8 evtchn_upcall_pending;
- u8 pad0;
- u64 evtchn_pending_sel;
- u8 pad[30];
-}; /* 64 bytes (x86) */
-typedef struct vcpu_info vcpu_info_t;
-
-struct shared_info
-{
- vcpu_info_t vcpu_info[1];
- u64 evtchn_pending[sizeof(u64) * 8];
- u64 evtchn_mask[sizeof(u64) * 8];
-};
-typedef struct shared_info shared_info_t;
-
-struct event_handler
-{
- u32 evtch_id;
- void (*handler_fptr)(void);
-};
-typedef struct event_handler event_handler_t;
-
-static event_handler_t event_handler_table[1] = {{0}};
-static __attribute__((aligned(0x1000))) u8 shared_info_page[1<vcpu_info[0];
-
- synch_clear_bit(port, &s->evtchn_mask[0]);
-
- /*
- * The following is basically the equivalent of 'hw_resend_irq'. Just like
- * a real IO-APIC we 'lose the interrupt edge' if the channel is masked.
- */
- if ( synch_test_bit (port, &s->evtchn_pending[0]) &&
- !synch_test_and_set_bit(port / (sizeof(unsigned long) * 8),
- &vcpu_info->evtchn_pending_sel) )
- {
- vcpu_info->evtchn_upcall_pending = 1;
-#ifdef XEN_HAVE_PV_UPCALL_MASK
- if ( !vcpu_info->evtchn_upcall_mask )
-#endif
- // force_evtchn_callback(); //todo, figure if this is needed
- }
-}
-
-// Clears the event flag so Xen can raise it again later
-static inline void clear_evtchn(uint32_t port)
-{
- shared_info_t *s = shared_info;
- synch_clear_bit(port, &s->evtchn_pending[0]);
-}
-
-// This is where we would call the handler for the specific event, but for now only supporting 1 event
-static int do_event(u32 port)
-{
- clear_evtchn(port);
-
- /* call the handler */
- if(port == event_handler_table[0].evtch_id)
- {
- event_handler_table[0].handler_fptr();
- }
-
- return 1;
-}
-
-// The IRQ handler for the interrupt that Xen uses for events (IRQ 31).
-void handle_event_irq(void* data)
-{
- unsigned long l1, l2, l1i, l2i;
- unsigned int port;
- int cpu = 0;
- shared_info_t *s = shared_info;
- vcpu_info_t *vcpu_info = &s->vcpu_info[cpu];
-
- vcpu_info->evtchn_upcall_pending = 0;
- wmb();
-
- l1 = xchg(&vcpu_info->evtchn_pending_sel, 0);
- while ( l1 != 0 )
- {
- l1i = __ffs(l1);
- l1 &= ~(1UL << l1i);
- while ( (l2 = active_evtchns(cpu, s, l1i)) != 0 )
- {
- l2i = __ffs(l2);
- l2 &= ~(1UL << l2i);
-
- port = (l1i * (sizeof(unsigned long) * 8)) + l2i;
- do_event(port);
-
- }
- }
-}
-
-// Initialize the guest's event framework
-void init_events(void)
-{
- xen_add_to_physmap_t xatp;
-
- /* Map shared_info page */
- xatp.domid = DOMID_SELF;
- xatp.idx = 0;
- xatp.space = XENMAPSPACE_shared_info;
- xatp.gpfn = VA_TO_GUEST_PAGE(shared_info_page);
-
- if(0 != HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp))
- {
- printk("ERROR setting up shared memory!\r\n");
- }
-
- shared_info = (struct shared_info *)shared_info_page;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/56/e0e786545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/56/e0e786545243001d18b399c1eb9b3628
deleted file mode 100644
index 9e7a741..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/56/e0e786545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,284 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xdevcfg_intr.c
-* @addtogroup devcfg_v3_7
-* @{
-*
-* Contains the implementation of interrupt related functions of the XDcfg
-* driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
-* set the mask instead of oring it with the
-* value read from the interrupt status register
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xdevcfg.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/****************************************************************************/
-/**
-*
-* This function enables the specified interrupts in the device.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Mask is the bit-mask of the interrupts to be enabled.
-* Bit positions of 1 will be enabled. Bit positions of 0 will
-* keep the previous setting. This mask is formed by OR'ing
-* XDCFG_INT_* bits defined in xdevcfg_hw.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Enable the specified interrupts in the Interrupt Mask Register.
- */
- RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_MASK_OFFSET);
- RegValue &= ~(Mask & XDCFG_IXR_ALL_MASK);
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_MASK_OFFSET,
- RegValue);
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function disables the specified interrupts in the device.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Mask is the bit-mask of the interrupts to be disabled.
-* Bit positions of 1 will be disabled. Bit positions of 0 will
-* keep the previous setting. This mask is formed by OR'ing
-* XDCFG_INT_* bits defined in xdevcfg_hw.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Disable the specified interrupts in the Interrupt Mask Register.
- */
- RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_MASK_OFFSET);
- RegValue |= (Mask & XDCFG_IXR_ALL_MASK);
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_MASK_OFFSET,
- RegValue);
-}
-/****************************************************************************/
-/**
-*
-* This function returns the enabled interrupts read from the Interrupt Mask
-* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h
-* to interpret the returned value.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return A 32-bit value representing the contents of the IMR.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Return the value read from the Interrupt Mask Register.
- */
- return (~ XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_MASK_OFFSET));
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the interrupt status read from Interrupt Status
-* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h
-* to interpret the returned value.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return A 32-bit value representing the contents of the Interrupt
-* Status register.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Return the value read from the Interrupt Status register.
- */
- return XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_STS_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* This function clears the specified interrupts in the Interrupt Status
-* Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Mask is the bit-mask of the interrupts to be cleared.
-* Bit positions of 1 will be cleared. Bit positions of 0 will not
-* change the previous interrupt status. This mask is formed by
-* OR'ing XDCFG_INT_* bits which are defined in xdevcfg_hw.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_STS_OFFSET,
- Mask);
-
-}
-
-/*****************************************************************************/
-/**
-* The interrupt handler for the Device Config Interface.
-*
-* Events are signaled to upper layer for proper handling.
-*
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XDcfg_InterruptHandler(XDcfg *InstancePtr)
-{
- u32 IntrStatusReg;
-
- /*
- * Assert validates the input arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Interrupt status register.
- */
- IntrStatusReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_STS_OFFSET);
-
- /*
- * Write the status back to clear the interrupts so that no
- * subsequent interrupts are missed while processing this interrupt.
- * This also does the DMA acknowledgment automatically.
- */
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_STS_OFFSET, IntrStatusReg);
-
- /*
- * Signal application that there are events to handle.
- */
- InstancePtr->StatusHandler(InstancePtr->CallBackRef,
- IntrStatusReg);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the handler that will be called when an event (interrupt)
-* occurs that needs application's attention.
-*
-* @param InstancePtr is a pointer to the XDcfg instance
-* @param CallBackFunc is the address of the callback function.
-* @param CallBackRef is a user data item that will be passed to the
-* callback function when it is invoked.
-*
-* @return None.
-*
-* @note None.
-*
-*
-*****************************************************************************/
-void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
- void *CallBackRef)
-{
- /*
- * Asserts validate the input arguments
- * CallBackRef not checked, no way to know what is valid
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(CallBackFunc != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- InstancePtr->StatusHandler = (XDcfg_IntrHandler) CallBackFunc;
- InstancePtr->CallBackRef = CallBackRef;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/57/622b18555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/57/622b18555243001d18b399c1eb9b3628
deleted file mode 100644
index df332c7..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/57/622b18555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,77 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_mmu.h
-*
-* @addtogroup a53_32_mmu_apis Cortex A53 32bit Processor MMU Handling
-* @{
-* MMU functions equip users to enable MMU, disable MMU and modify default
-* memory attributes of MMU table as per the need.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 7.1 mus 30/07/19 Added constant definitions for memory attributes.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.1 nsk 11/07/16 First release.
-* 7.0 mus 01/07/19 Add cpp extern macro
-*
-*
-*
-*****************************************************************************/
-#ifndef XIL_MEM_H /* prevent circular inclusions */
-#define XIL_MEM_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Function Prototypes *****************************/
-
-void Xil_MemCpy(void* dst, const void* src, u32 cnt);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_MEM_H */
-/**
-* @} End of "addtogroup common_mem_operation_api".
-*/
\ No newline at end of file
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/58/80c4b5585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/58/80c4b5585243001d18b399c1eb9b3628
deleted file mode 100644
index 82dd34a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/58/80c4b5585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,24 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) sint32 unlink(char8 *path);
-}
-#endif
-/*
- * unlink -- since we have no file system,
- * we just return an error.
- */
-__attribute__((weak)) sint32 unlink(char8 *path)
-{
- (void) path;
- errno = EIO;
- return (-1);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/58/82192e545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/58/82192e545243001d18b399c1eb9b3628
deleted file mode 100644
index 9d33a6c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/58/82192e545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,193 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xgpio.h
-* @addtogroup gpio_v4_8
-* @{
-* @details
-*
-* This file contains the software API definition of the Xilinx General Purpose
-* I/O (XGpio) device driver.
-*
-* The Xilinx GPIO controller is a soft IP core designed for Xilinx FPGAs and
-* contains the following general features:
-* - Support for up to 32 I/O discretes for each channel (64 bits total).
-* - Each of the discretes can be configured for input or output.
-* - Configurable support for dual channels and interrupt generation.
-*
-* The driver provides interrupt management functions. Implementation of
-* interrupt handlers is left to the user. Refer to the provided interrupt
-* example in the examples directory for details.
-*
-* This driver is intended to be RTOS and processor independent. Any needs for
-* dynamic memory management, threads or thread mutual exclusion, virtual
-* memory, or cache control must be satisfied by the layer above this driver.
-*
-* Initialization & Configuration
-*
-* The XGpio_Config structure is used by the driver to configure itself. This
-* configuration structure is typically created by the tool-chain based on HW
-* build properties.
-*
-* To support multiple runtime loading and initialization strategies employed
-* by various operating systems, the driver instance can be initialized in one
-* of the following ways:
-*
-* - XGpio_Initialize(InstancePtr, DeviceId) - The driver looks up its own
-* configuration structure created by the tool-chain based on an ID provided
-* by the tool-chain.
-*
-* - XGpio_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-* configuration structure provided by the caller. If running in a system
-* with address translation, the provided virtual memory base address
-* replaces the physical address present in the configuration structure.
-*
-* @note
-*
-* This API utilizes 32 bit I/O to the GPIO registers. With less than 32 bits,
-* the unused bits from registers are read as zero and written as don't cares.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 03/13/02 First release
-* 2.00a jhl 11/26/03 Added support for dual channels and interrupts
-* 2.01a jvb 12/14/05 I separated dependency on the static config table and
-* xparameters.h from the driver initialization by moving
-* _Initialize and _LookupConfig to _sinit.c. I also added
-* the new _CfgInitialize routine.
-* 2.11a mta 03/21/07 Updated to new coding style, added GetDataDirection
-* 2.12a sv 11/21/07 Updated driver to support access through DCR bus
-* 2.12a sv 06/05/08 Updated driver to fix the XGpio_InterruptDisable function
-* to properly update the Interrupt Enable register
-* 2.13a sdm 08/22/08 Removed support for static interrupt handlers from the MDD
-* file
-* 3.00a sv 11/21/09 Updated to use HAL Processor APIs.
-* Renamed the macros XGpio_mWriteReg to XGpio_WriteReg and
-* XGpio_mReadReg to XGpio_ReadReg. Removed the macros
-* XGpio_mSetDataDirection, XGpio_mGetDataReg and
-* XGpio_mSetDataReg. Users should use XGpio_WriteReg and
-* XGpio_ReadReg to achieve the same functionality.
-* 3.01a bss 04/18/13 Updated driver tcl to generate Canonical params in
-* xparameters.h. CR#698589
-* 4.0 adk 19/12/13 Updated as per the New Tcl API's
-* 4.1 lks 11/18/15 Updated to use canonical xparameters in examples and
-* clean up of the comments, removed support for DCR bridge
-* and removed xgpio_intr_example for CR 900381
-* 4.2 sk 08/16/16 Used UINTPTR instead of u32 for Baseaddress as part of
-* adding 64 bit support. CR# 867425.
-* Changed the prototype of XGpio_CfgInitialize API.
-* 4.3 sk 09/29/16 Modified the example to make it work when LED_bits are
-* configured as an output. CR# 958644
-* ms 01/23/17 Added xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 4.4 sne 04/25/19 Updated Makefile for IAR compier (CR-1029421).
-* 4.5 sne 06/14/19 Fixed IAR compiler warnings on example files.
-* 4.6 sne 08/11/19 Fixed compilation error of armcc compiler.
-* 4.7 sne 08/28/20 Modify Makefile to support parallel make execution.
-* 4.8 sne 02/10/21 Fixed doxygen warnings.
-*
-*
-*****************************************************************************/
-
-#ifndef XGPIO_H /* prevent circular inclusions */
-#define XGPIO_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xgpio_l.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- UINTPTR BaseAddress; /**< Device base address */
- int InterruptPresent; /**< Are interrupts supported in h/w */
- int IsDual; /**< Are 2 channels supported in h/w */
-} XGpio_Config;
-
-/**
- * The XGpio driver instance data. The user is required to allocate a
- * variable of this type for every GPIO device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- UINTPTR BaseAddress; /**< Device base address */
- u32 IsReady; /**< Device is initialized and ready */
- int InterruptPresent; /**< Are interrupts supported in h/w */
- int IsDual; /**< Are 2 channels supported in h/w */
-} XGpio;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Function Prototypes *****************************/
-
-/*
- * Initialization functions in xgpio_sinit.c
- */
-int XGpio_Initialize(XGpio *InstancePtr, u16 DeviceId);
-XGpio_Config *XGpio_LookupConfig(u16 DeviceId);
-
-/*
- * API Basic functions implemented in xgpio.c
- */
-int XGpio_CfgInitialize(XGpio *InstancePtr, XGpio_Config * Config,
- UINTPTR EffectiveAddr);
-void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
- u32 DirectionMask);
-u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel);
-u32 XGpio_DiscreteRead(XGpio *InstancePtr, unsigned Channel);
-void XGpio_DiscreteWrite(XGpio *InstancePtr, unsigned Channel, u32 Mask);
-
-
-/*
- * API Functions implemented in xgpio_extra.c
- */
-void XGpio_DiscreteSet(XGpio *InstancePtr, unsigned Channel, u32 Mask);
-void XGpio_DiscreteClear(XGpio *InstancePtr, unsigned Channel, u32 Mask);
-
-/*
- * API Functions implemented in xgpio_selftest.c
- */
-int XGpio_SelfTest(XGpio *InstancePtr);
-
-/*
- * API Functions implemented in xgpio_intr.c
- */
-void XGpio_InterruptGlobalEnable(XGpio *InstancePtr);
-void XGpio_InterruptGlobalDisable(XGpio *InstancePtr);
-void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask);
-void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask);
-void XGpio_InterruptClear(XGpio *InstancePtr, u32 Mask);
-u32 XGpio_InterruptGetEnabled(XGpio *InstancePtr);
-u32 XGpio_InterruptGetStatus(XGpio *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/58/a013a7575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/58/a013a7575243001d18b399c1eb9b3628
deleted file mode 100644
index 2de567a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/58/a013a7575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1410 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xsdps_hw.h
-* @addtogroup sdps_v3_13
-* @{
-*
-* This header file contains the identifiers and basic HW access driver
-* functions (or macros) that can be used to access the device. Other driver
-* functions are defined in xsdps.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a hk/sg 10/17/13 Initial release
-* 2.5 sg 07/09/15 Added SD 3.0 features
-* kvn 07/15/15 Modified the code according to MISRAC-2012.
-* 2.7 sk 12/10/15 Added support for MMC cards.
-* sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
-* 2.8 sk 04/20/16 Added new workaround for auto tuning.
-* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
-* sk 07/16/16 Added support for UHS modes.
-* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
-* operating modes.
-* 3.1 sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
-* 3.2 sk 03/20/17 Add support for EL1 non-secure mode.
-* 3.3 mn 08/22/17 Updated for Word Access System support
-* mn 09/06/17 Added support for ARMCC toolchain
-* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
-* 3.6 mn 07/06/18 Fix Doxygen warnings for sdps driver
-* 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
-* mn 05/21/19 Set correct tap delays for Versal
-* mn 05/21/19 Disable DLL Reset code for Versal
-* mn 07/03/19 Update Input Tap Delays for Versal
-* 3.9 mn 03/03/20 Restructured the code for more readability and modularity
-*
-*
-*
-******************************************************************************/
-
-#ifndef SD_HW_H_
-#define SD_HW_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets from the base address of an SD device.
- * @{
- */
-
-#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address
- Register */
-#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET
- /**< SDMA System Address
- Low Register */
-#define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */
-#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address
- High Register */
-#define XSDPS_ARGMT2_HI_OFFSET 0x02U /**< Argument2 High Register */
-
-#define XSDPS_BLK_SIZE_OFFSET 0x04U /**< Block Size Register */
-#define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */
-#define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */
-#define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET
- /**< Argument1 Register */
-#define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */
-
-#define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */
-#define XSDPS_CMD_OFFSET 0x0EU /**< Command Register */
-#define XSDPS_RESP0_OFFSET 0x10U /**< Response0 Register */
-#define XSDPS_RESP1_OFFSET 0x14U /**< Response1 Register */
-#define XSDPS_RESP2_OFFSET 0x18U /**< Response2 Register */
-#define XSDPS_RESP3_OFFSET 0x1CU /**< Response3 Register */
-#define XSDPS_BUF_DAT_PORT_OFFSET 0x20U /**< Buffer Data Port */
-#define XSDPS_PRES_STATE_OFFSET 0x24U /**< Present State */
-#define XSDPS_HOST_CTRL1_OFFSET 0x28U /**< Host Control 1 */
-#define XSDPS_POWER_CTRL_OFFSET 0x29U /**< Power Control */
-#define XSDPS_BLK_GAP_CTRL_OFFSET 0x2AU /**< Block Gap Control */
-#define XSDPS_WAKE_UP_CTRL_OFFSET 0x2BU /**< Wake Up Control */
-#define XSDPS_CLK_CTRL_OFFSET 0x2CU /**< Clock Control */
-#define XSDPS_TIMEOUT_CTRL_OFFSET 0x2EU /**< Timeout Control */
-#define XSDPS_SW_RST_OFFSET 0x2FU /**< Software Reset */
-#define XSDPS_NORM_INTR_STS_OFFSET 0x30U /**< Normal Interrupt
- Status Register */
-#define XSDPS_ERR_INTR_STS_OFFSET 0x32U /**< Error Interrupt
- Status Register */
-#define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34U /**< Normal Interrupt
- Status Enable Register */
-#define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36U /**< Error Interrupt
- Status Enable Register */
-#define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38U /**< Normal Interrupt
- Signal Enable Register */
-#define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3AU /**< Error Interrupt
- Signal Enable Register */
-
-#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3CU /**< Auto CMD12 Error Status
- Register */
-#define XSDPS_HOST_CTRL2_OFFSET 0x3EU /**< Host Control2 Register */
-#define XSDPS_CAPS_OFFSET 0x40U /**< Capabilities Register */
-#define XSDPS_CAPS_EXT_OFFSET 0x44U /**< Capabilities Extended */
-#define XSDPS_MAX_CURR_CAPS_OFFSET 0x48U /**< Maximum Current
- Capabilities Register */
-#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4CU /**< Maximum Current
- Capabilities Ext Register */
-#define XSDPS_FE_ERR_INT_STS_OFFSET 0x52U /**< Force Event for
- Error Interrupt Status */
-#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50U /**< Auto CM12 Error Interrupt
- Status Register */
-#define XSDPS_ADMA_ERR_STS_OFFSET 0x54U /**< ADMA Error Status
- Register */
-#define XSDPS_ADMA_SAR_OFFSET 0x58U /**< ADMA System Address
- Register */
-#define XSDPS_ADMA_SAR_EXT_OFFSET 0x5CU /**< ADMA System Address
- Extended Register */
-#define XSDPS_PRE_VAL_1_OFFSET 0x60U /**< Preset Value Register */
-#define XSDPS_PRE_VAL_2_OFFSET 0x64U /**< Preset Value Register */
-#define XSDPS_PRE_VAL_3_OFFSET 0x68U /**< Preset Value Register */
-#define XSDPS_PRE_VAL_4_OFFSET 0x6CU /**< Preset Value Register */
-#define XSDPS_BOOT_TOUT_CTRL_OFFSET 0x70U /**< Boot timeout control
- register */
-
-#define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0U /**< Shared Bus Control
- Register */
-#define XSDPS_SLOT_INTR_STS_OFFSET 0xFCU /**< Slot Interrupt Status
- Register */
-#define XSDPS_HOST_CTRL_VER_OFFSET 0xFEU /**< Host Controller Version
- Register */
-
-/** @} */
-
-/** @name Control Register - Host control, Power control,
- * Block Gap control and Wakeup control
- *
- * This register contains bits for various configuration options of
- * the SD host controller. Read/Write apart from the reserved bits.
- * @{
- */
-
-#define XSDPS_HC_LED_MASK 0x00000001U /**< LED Control */
-#define XSDPS_HC_WIDTH_MASK 0x00000002U /**< Bus width */
-#define XSDPS_HC_BUS_WIDTH_4 0x00000002U
-#define XSDPS_HC_SPEED_MASK 0x00000004U /**< High Speed */
-#define XSDPS_HC_DMA_MASK 0x00000018U /**< DMA Mode Select */
-#define XSDPS_HC_DMA_SDMA_MASK 0x00000000U /**< SDMA Mode */
-#define XSDPS_HC_DMA_ADMA1_MASK 0x00000008U /**< ADMA1 Mode */
-#define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010U /**< ADMA2 Mode - 32 bit */
-#define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018U /**< ADMA2 Mode - 64 bit */
-#define XSDPS_HC_EXT_BUS_WIDTH 0x00000020U /**< Bus width - 8 bit */
-#define XSDPS_HC_CARD_DET_TL_MASK 0x00000040U /**< Card Detect Tst Lvl */
-#define XSDPS_HC_CARD_DET_SD_MASK 0x00000080U /**< Card Detect Sig Det */
-
-#define XSDPS_PC_BUS_PWR_MASK 0x00000001U /**< Bus Power Control */
-#define XSDPS_PC_BUS_VSEL_MASK 0x0000000EU /**< Bus Voltage Select */
-#define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000EU /**< Bus Voltage 3.3V */
-#define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000CU /**< Bus Voltage 3.0V */
-#define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000AU /**< Bus Voltage 1.8V */
-#define XSDPS_PC_EMMC_HW_RST_MASK 0x00000010U /**< HW reset for eMMC */
-
-#define XSDPS_BGC_STP_REQ_MASK 0x00000001U /**< Block Gap Stop Req */
-#define XSDPS_BGC_CNT_REQ_MASK 0x00000002U /**< Block Gap Cont Req */
-#define XSDPS_BGC_RWC_MASK 0x00000004U /**< Block Gap Rd Wait */
-#define XSDPS_BGC_INTR_MASK 0x00000008U /**< Block Gap Intr */
-#define XSDPS_BGC_SPI_MODE_MASK 0x00000010U /**< Block Gap SPI Mode */
-#define XSDPS_BGC_BOOT_EN_MASK 0x00000020U /**< Block Gap Boot Enb */
-#define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040U /**< Block Gap Alt BootEn */
-#define XSDPS_BGC_BOOT_ACK_MASK 0x00000080U /**< Block Gap Boot Ack */
-
-#define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001U /**< Wakeup Card Intr */
-#define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002U /**< Wakeup Card Insert */
-#define XSDPS_WC_WUP_ON_REM_MASK 0x00000004U /**< Wakeup Card Removal */
-
-/** @} */
-
-/** @name Control Register - Clock control, Timeout control & Software reset
- *
- * This register contains bits for configuration options of clock, timeout and
- * software reset.
- * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
- * @{
- */
-
-#define XSDPS_CC_INT_CLK_EN_MASK 0x00000001U /**< INT clk enable */
-#define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002U /**< INT clk stable */
-#define XSDPS_CC_SD_CLK_EN_MASK 0x00000004U /**< SD clk enable */
-#define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020U /**< SD clk gen selection */
-#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x00000003U /**< SD clk freq sel upper */
-#define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x000000FFU /**< SD clk freq sel */
-#define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000U /**< Divider 256 */
-#define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000U /**< Divider 128 */
-#define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000U /**< Divider 64 */
-#define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000U /**< Divider 32 */
-#define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800U /**< Divider 16 */
-#define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400U /**< Divider 8 */
-#define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200U /**< Divider 4 */
-#define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100U /**< Divider 2 */
-#define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000U /**< Base clock */
-#define XSDPS_CC_MAX_DIV_CNT 256U /**< Max divider count */
-#define XSDPS_CC_EXT_MAX_DIV_CNT 2046U /**< Max extended divider count */
-#define XSDPS_CC_EXT_DIV_SHIFT 6U /**< Ext divider shift */
-
-#define XSDPS_TC_CNTR_VAL_MASK 0x0000000FU /**< Data timeout counter */
-
-#define XSDPS_SWRST_ALL_MASK 0x00000001U /**< Software Reset All */
-#define XSDPS_SWRST_CMD_LINE_MASK 0x00000002U /**< Software reset for CMD line */
-#define XSDPS_SWRST_DAT_LINE_MASK 0x00000004U /**< Software reset for DAT line */
-
-#define XSDPS_CC_MAX_NUM_OF_DIV 9U /**< Max number of Clock dividers */
-#define XSDPS_CC_DIV_SHIFT 8U /**< Clock Divider shift */
-
-/** @} */
-
-/** @name SD Interrupt Registers
- *
- * Normal and Error Interrupt Status Register
- * This register shows the normal and error interrupt status.
- * Status enable register affects reads of this register.
- * If Signal enable register is set and the corresponding status bit is set,
- * interrupt is generated.
- * Write to clear except
- * Error_interrupt and Card_Interrupt bits - Read only
- *
- * Normal and Error Interrupt Status Enable Register
- * Setting this register bits enables Interrupt status.
- * Read/Write except Fixed_to_0 bit (Read only)
- *
- * Normal and Error Interrupt Signal Enable Register
- * This register is used to select which interrupt status is
- * indicated to the Host System as the interrupt.
- * Read/Write except Fixed_to_0 bit (Read only)
- *
- * All three registers have same bit definitions
- * @{
- */
-
-#define XSDPS_INTR_CC_MASK 0x00000001U /**< Command Complete */
-#define XSDPS_INTR_TC_MASK 0x00000002U /**< Transfer Complete */
-#define XSDPS_INTR_BGE_MASK 0x00000004U /**< Block Gap Event */
-#define XSDPS_INTR_DMA_MASK 0x00000008U /**< DMA Interrupt */
-#define XSDPS_INTR_BWR_MASK 0x00000010U /**< Buffer Write Ready */
-#define XSDPS_INTR_BRR_MASK 0x00000020U /**< Buffer Read Ready */
-#define XSDPS_INTR_CARD_INSRT_MASK 0x00000040U /**< Card Insert */
-#define XSDPS_INTR_CARD_REM_MASK 0x00000080U /**< Card Remove */
-#define XSDPS_INTR_CARD_MASK 0x00000100U /**< Card Interrupt */
-#define XSDPS_INTR_INT_A_MASK 0x00000200U /**< INT A Interrupt */
-#define XSDPS_INTR_INT_B_MASK 0x00000400U /**< INT B Interrupt */
-#define XSDPS_INTR_INT_C_MASK 0x00000800U /**< INT C Interrupt */
-#define XSDPS_INTR_RE_TUNING_MASK 0x00001000U /**< Re-Tuning Interrupt */
-#define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00002000U /**< Boot Ack Recv
- Interrupt */
-#define XSDPS_INTR_BOOT_TERM_MASK 0x00004000U /**< Boot Terminate
- Interrupt */
-#define XSDPS_INTR_ERR_MASK 0x00008000U /**< Error Interrupt */
-#define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFFU
-
-#define XSDPS_INTR_ERR_CT_MASK 0x00000001U /**< Command Timeout
- Error */
-#define XSDPS_INTR_ERR_CCRC_MASK 0x00000002U /**< Command CRC Error */
-#define XSDPS_INTR_ERR_CEB_MASK 0x00000004U /**< Command End Bit
- Error */
-#define XSDPS_INTR_ERR_CI_MASK 0x00000008U /**< Command Index Error */
-#define XSDPS_INTR_ERR_DT_MASK 0x00000010U /**< Data Timeout Error */
-#define XSDPS_INTR_ERR_DCRC_MASK 0x00000020U /**< Data CRC Error */
-#define XSDPS_INTR_ERR_DEB_MASK 0x00000040U /**< Data End Bit Error */
-#define XSDPS_INTR_ERR_CUR_LMT_MASK 0x00000080U /**< Current Limit Error */
-#define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100U /**< Auto CMD12 Error */
-#define XSDPS_INTR_ERR_ADMA_MASK 0x00000200U /**< ADMA Error */
-#define XSDPS_INTR_ERR_TR_MASK 0x00001000U /**< Tuning Error */
-#define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000U /**< Vendor Specific
- Error */
-#define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FFU /**< Mask for error bits */
-/** @} */
-
-/** @name Block Size and Block Count Register
- *
- * This register contains the block count for current transfer,
- * block size and SDMA buffer size.
- * Read/Write except for reserved bits.
- * @{
- */
-
-#define XSDPS_BLK_SIZE_MASK 0x00000FFFU /**< Transfer Block Size */
-#define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000U /**< Host SDMA Buffer Size */
-#define XSDPS_BLK_SIZE_1024 0x400U
-#define XSDPS_BLK_SIZE_2048 0x800U
-#define XSDPS_BLK_CNT_MASK 0x0000FFFFU /**< Block Count for
- Current Transfer */
-
-/** @} */
-
-/** @name Transfer Mode and Command Register
- *
- * The Transfer Mode register is used to control the data transfers and
- * Command register is used for command generation
- * Read/Write except for reserved bits.
- * @{
- */
-
-#define XSDPS_TM_DMA_EN_MASK 0x00000001U /**< DMA Enable */
-#define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002U /**< Block Count Enable */
-#define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004U /**< Auto CMD12 Enable */
-#define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010U /**< Data Transfer
- Direction Select */
-#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020U /**< Multi/Single
- Block Select */
-
-#define XSDPS_CMD_RESP_SEL_MASK 0x00000003U /**< Response Type
- Select */
-#define XSDPS_CMD_RESP_NONE_MASK 0x00000000U /**< No Response */
-#define XSDPS_CMD_RESP_L136_MASK 0x00000001U /**< Response length 138 */
-#define XSDPS_CMD_RESP_L48_MASK 0x00000002U /**< Response length 48 */
-#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003U /**< Response length 48 &
- check busy after
- response */
-#define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008U /**< Command CRC Check
- Enable */
-#define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010U /**< Command Index Check
- Enable */
-#define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020U /**< Data Present Select */
-#define XSDPS_CMD_TYPE_MASK 0x000000C0U /**< Command Type */
-#define XSDPS_CMD_TYPE_NORM_MASK 0x00000000U /**< CMD Type - Normal */
-#define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040U /**< CMD Type - Suspend */
-#define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080U /**< CMD Type - Resume */
-#define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0U /**< CMD Type - Abort */
-#define XSDPS_CMD_MASK 0x00003F00U /**< Command Index Mask -
- Set to CMD0-63,
- AMCD0-63 */
-
-/** @} */
-
-/** @name Auto CMD Error Status Register
- *
- * This register is read only register which contains
- * information about the error status of Auto CMD 12 and 23.
- * Read Only
- * @{
- */
-#define XSDPS_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
- executed */
-#define XSDPS_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
- Error */
-#define XSDPS_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
-#define XSDPS_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
- Error */
-#define XSDPS_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
-#define XSDPS_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
- Auto CMD12 Error */
-/** @} */
-
-/** @name Host Control2 Register
- *
- * This register contains extended configuration bits.
- * Read Write
- * @{
- */
-#define XSDPS_HC2_UHS_MODE_MASK 0x0007U /**< UHS Mode select bits */
-#define XSDPS_HC2_UHS_MODE_SDR12_MASK 0x0000U /**< SDR12 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_SDR25_MASK 0x0001U /**< SDR25 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_SDR50_MASK 0x0002U /**< SDR50 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_SDR104_MASK 0x0003U /**< SDR104 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_DDR50_MASK 0x0004U /**< DDR50 UHS Mode */
-#define XSDPS_HC2_1V8_EN_MASK 0x0008U /**< 1.8V Signal Enable */
-#define XSDPS_HC2_DRV_STR_SEL_MASK 0x0030U /**< Driver Strength
- Selection */
-#define XSDPS_HC2_DRV_STR_B_MASK 0x0000U /**< Driver Strength B */
-#define XSDPS_HC2_DRV_STR_A_MASK 0x0010U /**< Driver Strength A */
-#define XSDPS_HC2_DRV_STR_C_MASK 0x0020U /**< Driver Strength C */
-#define XSDPS_HC2_DRV_STR_D_MASK 0x0030U /**< Driver Strength D */
-#define XSDPS_HC2_EXEC_TNG_MASK 0x0040U /**< Execute Tuning */
-#define XSDPS_HC2_SAMP_CLK_SEL_MASK 0x0080U /**< Sampling Clock
- Selection */
-#define XSDPS_HC2_ASYNC_INTR_EN_MASK 0x4000U /**< Asynchronous Interrupt
- Enable */
-#define XSDPS_HC2_PRE_VAL_EN_MASK 0x8000U /**< Preset Value Enable */
-
-/** @} */
-
-/** @name Capabilities Register
- *
- * Capabilities register is a read only register which contains
- * information about the host controller.
- * Sufficient if read once after power on.
- * Read Only
- * @{
- */
-#define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003FU /**< Timeout clock freq
- select */
-#define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080U /**< Timeout clock unit -
- MHz/KHz */
-#define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000U /**< Max block length */
-#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000U /**< Max block 512 bytes */
-#define XSDPS_CAP_MAX_BL_LN_1024_MASK 0x00010000U /**< Max block 1024 bytes */
-#define XSDPS_CAP_MAX_BL_LN_2048_MASK 0x00020000U /**< Max block 2048 bytes */
-#define XSDPS_CAP_MAX_BL_LN_4096_MASK 0x00030000U /**< Max block 4096 bytes */
-
-#define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000U /**< Extended media bus */
-#define XSDPS_CAP_ADMA2_MASK 0x00080000U /**< ADMA2 support */
-#define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000U /**< High speed support */
-#define XSDPS_CAP_SDMA_MASK 0x00400000U /**< SDMA support */
-#define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000U /**< Suspend/Resume
- support */
-#define XSDPS_CAP_VOLT_3V3_MASK 0x01000000U /**< 3.3V support */
-#define XSDPS_CAP_VOLT_3V0_MASK 0x02000000U /**< 3.0V support */
-#define XSDPS_CAP_VOLT_1V8_MASK 0x04000000U /**< 1.8V support */
-
-#define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000U /**< 64 bit system bus
- support */
-/* Spec 2.0 */
-#define XSDPS_CAP_INTR_MODE_MASK 0x08000000U /**< Interrupt mode
- support */
-#define XSDPS_CAP_SPI_MODE_MASK 0x20000000U /**< SPI mode */
-#define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x40000000U /**< SPI block mode */
-
-
-/* Spec 3.0 */
-#define XSDPS_CAPS_ASYNC_INTR_MASK 0x20000000U /**< Async Interrupt
- support */
-#define XSDPS_CAPS_SLOT_TYPE_MASK 0xC0000000U /**< Slot Type */
-#define XSDPS_CAPS_REM_CARD 0x00000000U /**< Removable Slot */
-#define XSDPS_CAPS_EMB_SLOT 0x40000000U /**< Embedded Slot */
-#define XSDPS_CAPS_SHR_BUS 0x80000000U /**< Shared Bus Slot */
-
-#define XSDPS_ECAPS_SDR50_MASK 0x00000001U /**< SDR50 Mode support */
-#define XSDPS_ECAPS_SDR104_MASK 0x00000002U /**< SDR104 Mode support */
-#define XSDPS_ECAPS_DDR50_MASK 0x00000004U /**< DDR50 Mode support */
-#define XSDPS_ECAPS_DRV_TYPE_A_MASK 0x00000010U /**< DriverType A support */
-#define XSDPS_ECAPS_DRV_TYPE_C_MASK 0x00000020U /**< DriverType C support */
-#define XSDPS_ECAPS_DRV_TYPE_D_MASK 0x00000040U /**< DriverType D support */
-#define XSDPS_ECAPS_TMR_CNT_MASK 0x00000F00U /**< Timer Count for
- Re-tuning */
-#define XSDPS_ECAPS_USE_TNG_SDR50_MASK 0x00002000U /**< SDR50 Mode needs
- tuning */
-#define XSDPS_ECAPS_RE_TNG_MODES_MASK 0x0000C000U /**< Re-tuning modes
- support */
-#define XSDPS_ECAPS_RE_TNG_MODE1_MASK 0x00000000U /**< Re-tuning mode 1 */
-#define XSDPS_ECAPS_RE_TNG_MODE2_MASK 0x00004000U /**< Re-tuning mode 2 */
-#define XSDPS_ECAPS_RE_TNG_MODE3_MASK 0x00008000U /**< Re-tuning mode 3 */
-#define XSDPS_ECAPS_CLK_MULT_MASK 0x00FF0000U /**< Clock Multiplier value
- for Programmable clock
- mode */
-#define XSDPS_ECAPS_SPI_MODE_MASK 0x01000000U /**< SPI mode */
-#define XSDPS_ECAPS_SPI_BLK_MODE_MASK 0x02000000U /**< SPI block mode */
-
-/** @} */
-
-/** @name Present State Register
- *
- * Gives the current status of the host controller
- * Read Only
- * @{
- */
-
-#define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001U /**< Command inhibit - CMD */
-#define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002U /**< Command Inhibit - DAT */
-#define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004U /**< DAT line active */
-#define XSDPS_PSR_RE_TUNING_REQ_MASK 0x00000008U /**< Re-tuning request */
-#define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100U /**< Write transfer active */
-#define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200U /**< Read transfer active */
-#define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400U /**< Buffer write enable */
-#define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800U /**< Buffer read enable */
-#define XSDPS_PSR_CARD_INSRT_MASK 0x00010000U /**< Card inserted */
-#define XSDPS_PSR_CARD_STABLE_MASK 0x00020000U /**< Card state stable */
-#define XSDPS_PSR_CARD_DPL_MASK 0x00040000U /**< Card detect pin level */
-#define XSDPS_PSR_WPS_PL_MASK 0x00080000U /**< Write protect switch
- pin level */
-#define XSDPS_PSR_DAT30_SG_LVL_MASK 0x00F00000U /**< Data 3:0 signal lvl */
-#define XSDPS_PSR_CMD_SG_LVL_MASK 0x01000000U /**< Cmd Line signal lvl */
-#define XSDPS_PSR_DAT74_SG_LVL_MASK 0x1E000000U /**< Data 7:4 signal lvl */
-
-/** @} */
-
-/** @name Maximum Current Capabilities Register
- *
- * This register is read only register which contains
- * information about current capabilities at each voltage levels.
- * Read Only
- * @{
- */
-#define XSDPS_MAX_CUR_CAPS_1V8_MASK 0x00000F00U /**< Maximum Current
- Capability at 1.8V */
-#define XSDPS_MAX_CUR_CAPS_3V0_MASK 0x000000F0U /**< Maximum Current
- Capability at 3.0V */
-#define XSDPS_MAX_CUR_CAPS_3V3_MASK 0x0000000FU /**< Maximum Current
- Capability at 3.3V */
-/** @} */
-
-
-/** @name Force Event for Auto CMD Error Status Register
- *
- * This register is write only register which contains
- * control bits to generate events for Auto CMD error status.
- * Write Only
- * @{
- */
-#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
- executed */
-#define XSDPS_FE_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
- Error */
-#define XSDPS_FE_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
-#define XSDPS_FE_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
- Error */
-#define XSDPS_FE_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
-#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
- Auto CMD12 Error */
-/** @} */
-
-
-
-/** @name Force Event for Error Interrupt Status Register
- *
- * This register is write only register which contains
- * control bits to generate events of error interrupt status register.
- * Write Only
- * @{
- */
-#define XSDPS_FE_INTR_ERR_CT_MASK 0x0001U /**< Command Timeout
- Error */
-#define XSDPS_FE_INTR_ERR_CCRC_MASK 0x0002U /**< Command CRC Error */
-#define XSDPS_FE_INTR_ERR_CEB_MASK 0x0004U /**< Command End Bit
- Error */
-#define XSDPS_FE_INTR_ERR_CI_MASK 0x0008U /**< Command Index Error */
-#define XSDPS_FE_INTR_ERR_DT_MASK 0x0010U /**< Data Timeout Error */
-#define XSDPS_FE_INTR_ERR_DCRC_MASK 0x0020U /**< Data CRC Error */
-#define XSDPS_FE_INTR_ERR_DEB_MASK 0x0040U /**< Data End Bit Error */
-#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK 0x0080U /**< Current Limit Error */
-#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK 0x0100U /**< Auto CMD Error */
-#define XSDPS_FE_INTR_ERR_ADMA_MASK 0x0200U /**< ADMA Error */
-#define XSDPS_FE_INTR_ERR_TR_MASK 0x1000U /**< Target Response */
-#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK 0xE000U /**< Vendor Specific
- Error */
-
-/** @} */
-
-/** @name ADMA Error Status Register
- *
- * This register is read only register which contains
- * status information about ADMA errors.
- * Read Only
- * @{
- */
-#define XSDPS_ADMA_ERR_MM_LEN_MASK 0x04U /**< ADMA Length Mismatch
- Error */
-#define XSDPS_ADMA_ERR_STATE_MASK 0x03U /**< ADMA Error State */
-#define XSDPS_ADMA_ERR_STATE_STOP_MASK 0x00U /**< ADMA Error State
- STOP */
-#define XSDPS_ADMA_ERR_STATE_FDS_MASK 0x01U /**< ADMA Error State
- FDS */
-#define XSDPS_ADMA_ERR_STATE_TFR_MASK 0x03U /**< ADMA Error State
- TFR */
-/** @} */
-
-/** @name Preset Values Register
- *
- * This register is read only register which contains
- * preset values for each of speed modes.
- * Read Only
- * @{
- */
-#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK 0x03FFU /**< SDCLK Frequency
- Select Value */
-#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK 0x0400U /**< Clock Generator
- Mode Select */
-#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK 0xC000U /**< Driver Strength
- Select Value */
-
-/** @} */
-
-/** @name Slot Interrupt Status Register
- *
- * This register is read only register which contains
- * interrupt slot signal for each slot.
- * Read Only
- * @{
- */
-#define XSDPS_SLOT_INTR_STS_INT_MASK 0x0007U /**< Interrupt Signal
- mask */
-
-/** @} */
-
-/** @name Host Controller Version Register
- *
- * This register is read only register which contains
- * Host Controller and Vendor Specific version.
- * Read Only
- * @{
- */
-#define XSDPS_HC_VENDOR_VER 0xFF00U /**< Vendor
- Specification
- version mask */
-#define XSDPS_HC_SPEC_VER_MASK 0x00FFU /**< Host
- Specification
- version mask */
-#define XSDPS_HC_SPEC_V3 0x0002U /**< HC spec version 3 */
-#define XSDPS_HC_SPEC_V2 0x0001U /**< HC spec version 2 */
-#define XSDPS_HC_SPEC_V1 0x0000U /**< HC spec version 1 */
-/** @} */
-
-/** @name Block size mask for 512 bytes
- *
- * Block size mask for 512 bytes - This is the default block size.
- * @{
- */
-
-#define XSDPS_BLK_SIZE_512_MASK 0x200U /**< Blk Size 512 */
-
-/** @} */
-
-/** @name Commands
- *
- * Constant definitions for commands and response related to SD
- * @{
- */
-/**
- * Command/Response related to SD/eMMC
- */
-
-#define XSDPS_APP_CMD_PREFIX 0x8000U
-#define CMD0 0x0000U
-#define CMD1 0x0100U
-#define CMD2 0x0200U
-#define CMD3 0x0300U
-#define CMD4 0x0400U
-#define CMD5 0x0500U
-#define CMD6 0x0600U
-#define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600U)
-#define CMD7 0x0700U
-#define CMD8 0x0800U
-#define CMD9 0x0900U
-#define CMD10 0x0A00U
-#define CMD11 0x0B00U
-#define CMD12 0x0C00U
-#define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00U)
-#define CMD16 0x1000U
-#define CMD17 0x1100U
-#define CMD18 0x1200U
-#define CMD19 0x1300U
-#define CMD21 0x1500U
-#define CMD23 0x1700U
-#define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700U)
-#define CMD24 0x1800U
-#define CMD25 0x1900U
-#define CMD41 0x2900U
-#define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900U)
-#define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00U)
-#define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300U)
-#define CMD52 0x3400U
-#define CMD55 0x3700U
-#define CMD58 0x3A00U
-
-#define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK
-#define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
- (u32)XSDPS_CMD_INX_CHK_EN_MASK
-
-#define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
- (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
-
-#define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
-#define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK
-
-#define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
- (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
-
-/** @} */
-
-/**
- * @name Card Interface
- * @{
- */
-/**
- * Card Interface Conditions Definitions
- */
-#define XSDPS_CIC_CHK_PATTERN 0xAAU
-#define XSDPS_CIC_VOLT_MASK (0xFU<<8)
-#define XSDPS_CIC_VOLT_2V7_3V6 (1U<<8)
-#define XSDPS_CIC_VOLT_LOW (1U<<9)
-/** @} */
-
-/**
- * @name OCR
- * @{
- */
-/**
- * Operation Conditions Register Definitions
- */
-#define XSDPS_OCR_PWRUP_STS (1U<<31)
-#define XSDPS_OCR_CC_STS (1U<<30)
-#define XSDPS_OCR_S18 (1U<<24)
-#define XSDPS_OCR_3V5_3V6 (1U<<23)
-#define XSDPS_OCR_3V4_3V5 (1U<<22)
-#define XSDPS_OCR_3V3_3V4 (1U<<21)
-#define XSDPS_OCR_3V2_3V3 (1U<<20)
-#define XSDPS_OCR_3V1_3V2 (1U<<19)
-#define XSDPS_OCR_3V0_3V1 (1U<<18)
-#define XSDPS_OCR_2V9_3V0 (1U<<17)
-#define XSDPS_OCR_2V8_2V9 (1U<<16)
-#define XSDPS_OCR_2V7_2V8 (1U<<15)
-#define XSDPS_OCR_1V7_1V95 (1U<<7)
-#define XSDPS_OCR_HIGH_VOL 0x00FF8000U
-#define XSDPS_OCR_LOW_VOL 0x00000080U
-/** @} */
-
-/**
- * @name Card Configuration
- * @{
- */
-/**
- * SD Card Configuration Register Definitions
- */
-#define XSDPS_SCR_REG_LEN 8U
-#define XSDPS_SCR_STRUCT_MASK (0xFU<<28)
-#define XSDPS_SCR_SPEC_MASK (0xFU<<24)
-#define XSDPS_SCR_SPEC_1V0 0U
-#define XSDPS_SCR_SPEC_1V1 (1U<<24)
-#define XSDPS_SCR_SPEC_2V0_3V0 (2U<<24)
-#define XSDPS_SCR_MEM_VAL_AF_ERASE (1U<<23)
-#define XSDPS_SCR_SEC_SUPP_MASK (7U<<20)
-#define XSDPS_SCR_SEC_SUPP_NONE 0U
-#define XSDPS_SCR_SEC_SUPP_1V1 (2U<<20)
-#define XSDPS_SCR_SEC_SUPP_2V0 (3U<<20)
-#define XSDPS_SCR_SEC_SUPP_3V0 (4U<<20)
-#define XSDPS_SCR_BUS_WIDTH_MASK (0xFU<<16)
-#define XSDPS_SCR_BUS_WIDTH_1 (1U<<16)
-#define XSDPS_SCR_BUS_WIDTH_4 (4U<<16)
-#define XSDPS_SCR_SPEC3_MASK (1U<<12)
-#define XSDPS_SCR_SPEC3_2V0 0U
-#define XSDPS_SCR_SPEC3_3V0 (1U<<12)
-#define XSDPS_SCR_CMD_SUPP_MASK 0x3U
-#define XSDPS_SCR_CMD23_SUPP (1U<<1)
-#define XSDPS_SCR_CMD20_SUPP (1U<<0)
-/** @} */
-
-/**
- * @name Card Status
- * @{
- */
-/**
- * Card Status Register Definitions
- */
-#define XSDPS_CD_STS_OUT_OF_RANGE (1U<<31)
-#define XSDPS_CD_STS_ADDR_ERR (1U<<30)
-#define XSDPS_CD_STS_BLK_LEN_ERR (1U<<29)
-#define XSDPS_CD_STS_ER_SEQ_ERR (1U<<28)
-#define XSDPS_CD_STS_ER_PRM_ERR (1U<<27)
-#define XSDPS_CD_STS_WP_VIO (1U<<26)
-#define XSDPS_CD_STS_IS_LOCKED (1U<<25)
-#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL (1U<<24)
-#define XSDPS_CD_STS_CMD_CRC_ERR (1U<<23)
-#define XSDPS_CD_STS_ILGL_CMD (1U<<22)
-#define XSDPS_CD_STS_CARD_ECC_FAIL (1U<<21)
-#define XSDPS_CD_STS_CC_ERR (1U<<20)
-#define XSDPS_CD_STS_ERR (1U<<19)
-#define XSDPS_CD_STS_CSD_OVRWR (1U<<16)
-#define XSDPS_CD_STS_WP_ER_SKIP (1U<<15)
-#define XSDPS_CD_STS_CARD_ECC_DIS (1U<<14)
-#define XSDPS_CD_STS_ER_RST (1U<<13)
-#define XSDPS_CD_STS_CUR_STATE (0xFU<<9)
-#define XSDPS_CD_STS_RDY_FOR_DATA (1U<<8)
-#define XSDPS_CD_STS_APP_CMD (1U<<5)
-#define XSDPS_CD_STS_AKE_SEQ_ERR (1U<<2)
-/** @} */
-
-/**
- * @name Switch function
- * @{
- */
-/**
- * Switch Function Definitions CMD6
- */
-#define XSDPS_SWITCH_SD_RESP_LEN 64U
-
-#define XSDPS_SWITCH_FUNC_SWITCH (1U<<31)
-#define XSDPS_SWITCH_FUNC_CHECK 0U
-/** @} */
-
-/**
- * @name Mode Function
- * @{
- */
-/**
- * Mode function groups definitions.
- */
-#define XSDPS_MODE_FUNC_GRP1 1U
-#define XSDPS_MODE_FUNC_GRP2 2U
-#define XSDPS_MODE_FUNC_GRP3 3U
-#define XSDPS_MODE_FUNC_GRP4 4U
-#define XSDPS_MODE_FUNC_GRP5 5U
-#define XSDPS_MODE_FUNC_GRP6 6U
-
-#define XSDPS_FUNC_GRP_DEF_VAL 0xFU
-#define XSDPS_FUNC_ALL_GRP_DEF_VAL 0xFFFFFFU
-/** @} */
-
-/**
- * @name Operating modes
- * @{
- */
-/**
- * SD operating modes in UHS.
- */
-#define XSDPS_ACC_MODE_DEF_SDR12 0U
-#define XSDPS_ACC_MODE_HS_SDR25 1U
-#define XSDPS_ACC_MODE_SDR50 2U
-#define XSDPS_ACC_MODE_SDR104 3U
-#define XSDPS_ACC_MODE_DDR50 4U
-/** @} */
-
-/**
- * @name General definitions
- * @{
- */
-/**
- * Definitions related to Driver strength, Current limit and
- * CSD specific data.
- */
-#define XSDPS_CMD_SYS_ARG_SHIFT 4U
-#define XSDPS_CMD_SYS_DEF 0U
-#define XSDPS_CMD_SYS_eC 1U
-#define XSDPS_CMD_SYS_OTP 3U
-#define XSDPS_CMD_SYS_ASSD 4U
-#define XSDPS_CMD_SYS_VEND 5U
-
-#define XSDPS_DRV_TYPE_ARG_SHIFT 8U
-#define XSDPS_DRV_TYPE_B 0U
-#define XSDPS_DRV_TYPE_A 1U
-#define XSDPS_DRV_TYPE_C 2U
-#define XSDPS_DRV_TYPE_D 3U
-
-#define XSDPS_CUR_LIM_ARG_SHIFT 12U
-#define XSDPS_CUR_LIM_200 0U
-#define XSDPS_CUR_LIM_400 1U
-#define XSDPS_CUR_LIM_600 2U
-#define XSDPS_CUR_LIM_800 3U
-
-#define CSD_SPEC_VER_MASK 0x3C0000U
-#define READ_BLK_LEN_MASK 0x00000F00U
-#define C_SIZE_MULT_MASK 0x00000380U
-#define C_SIZE_LOWER_MASK 0xFFC00000U
-#define C_SIZE_UPPER_MASK 0x00000003U
-#define CSD_STRUCT_MASK 0x00C00000U
-#define CSD_V2_C_SIZE_MASK 0x3FFFFF00U
-/** @} */
-
-/**
- * @name Extended Card Specific Data
- * @{
- */
-/**
- * EXT_CSD field definitions
- */
-#define XSDPS_EXT_CSD_SIZE 512U
-
-#define EXT_CSD_WR_REL_PARAM_EN (1U<<2)
-
-#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40U)
-#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10U)
-#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04U)
-#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01U)
-
-#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7U)
-#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1U)
-#define EXT_CSD_PART_CONFIG_ACC_BOOT1 (0x2U)
-#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U)
-#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U)
-#define EXT_CSD_PART_CONFIG_BYTE (179U)
-#define XSDPS_MMC_PART_CFG_0_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
- | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
- | ((u32)(0U) << 8U))
-
-#define XSDPS_MMC_PART_CFG_1_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
- | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
- | ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT0 << 8U))
-
-#define XSDPS_MMC_PART_CFG_2_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
- | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
- | ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT1 << 8U))
-
-#define EXT_CSD_PART_SUPPORT_PART_EN (0x1U)
-
-#define EXT_CSD_CMD_SET_NORMAL (1U<<0)
-#define EXT_CSD_CMD_SET_SECURE (1U<<1)
-#define EXT_CSD_CMD_SET_CPSECURE (1U<<2)
-
-#define EXT_CSD_CARD_TYPE_26 (1U<<0) /* Card can run at 26MHz */
-#define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */
-#define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */
-#define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */
- /* DDR mode @1.8V or 3V I/O */
-#define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */
- /* DDR mode @1.2V I/O */
-#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
- | EXT_CSD_CARD_TYPE_DDR_1_2V)
-#define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */
-#define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */
- /* SDR mode @1.2V I/O */
-#define EXT_CSD_BUS_WIDTH_BYTE 183U
-#define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */
-#define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */
-#define EXT_CSD_BUS_WIDTH_8_BIT 2U /* Card is in 8 bit mode */
-#define EXT_CSD_BUS_WIDTH_DDR_4_BIT 5U /* Card is in 4 bit DDR mode */
-#define EXT_CSD_BUS_WIDTH_DDR_8_BIT 6U /* Card is in 8 bit DDR mode */
-
-#define EXT_CSD_HS_TIMING_BYTE 185U
-#define EXT_CSD_HS_TIMING_DEF 0U
-#define EXT_CSD_HS_TIMING_HIGH 1U /* Card is in high speed mode */
-#define EXT_CSD_HS_TIMING_HS200 2U /* Card is in HS200 mode */
-
-#define EXT_CSD_RST_N_FUN_BYTE 162U
-#define EXT_CSD_RST_N_FUN_TEMP_DIS 0U /* RST_n signal is temporarily disabled */
-#define EXT_CSD_RST_N_FUN_PERM_EN 1U /* RST_n signal is permanently enabled */
-#define EXT_CSD_RST_N_FUN_PERM_DIS 2U /* RST_n signal is permanently disabled */
-
-#define XSDPS_EXT_CSD_CMD_SET 0U
-#define XSDPS_EXT_CSD_SET_BITS 1U
-#define XSDPS_EXT_CSD_CLR_BITS 2U
-#define XSDPS_EXT_CSD_WRITE_BYTE 3U
-/** @} */
-
-/**
- * @name SD/eMMC Bus Speed and Bus Width Arguments
- * @{
- */
-/**
- * SD/MMC Arguments for Bus Speed and Bus Width.
- */
-#define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
- | ((u32)EXT_CSD_HS_TIMING_DEF << 8))
-
-#define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
- | ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
-
-#define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
- | ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
-
-#define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8))
-
-#define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
-
-#define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
-
-#define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
-
-#define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
-
-#define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
- | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
-
-#define XSDPS_MMC_DELAY_FOR_SWITCH 1000U
-
-/** @} */
-
-/**
- * @name General Delay definitions
- * @{
- */
-/**
- * @400KHz, in usec
- */
-#define XSDPS_74CLK_DELAY 2960U
-#define XSDPS_100CLK_DELAY 4000U
-#define XSDPS_INIT_DELAY 10000U
-/** @} */
-
-#define XSDPS_DEF_VOLT_LVL XSDPS_PC_BUS_VSEL_3V0_MASK /**< Default voltage level */
-#define XSDPS_CARD_DEF_ADDR 0x1234U /**< Card Default address */
-
-#define XSDPS_CARD_SD 1U /**< SD card */
-#define XSDPS_CARD_MMC 2U /**< MMC card */
-#define XSDPS_CARD_SDIO 3U /**< SDIO card */
-#define XSDPS_CARD_SDCOMBO 4U /**< SDCOMBO card */
-#define XSDPS_CHIP_EMMC 5U /**< EMMC chip */
-
-
-/**
- *@name ADMA2 Descriptor related definitions
- * @{
- */
-/**
- * ADMA2 Descriptor related definitions
- */
-#define XSDPS_DESC_MAX_LENGTH 65536U
-
-#define XSDPS_DESC_VALID (0x1U << 0)
-#define XSDPS_DESC_END (0x1U << 1)
-#define XSDPS_DESC_INT (0x1U << 2)
-#define XSDPS_DESC_TRAN (0x2U << 4)
-
-/** @} */
-
-/* For changing clock frequencies */
-#define XSDPS_CLK_400_KHZ 400000U /**< 400 KHZ */
-#define XSDPS_CLK_50_MHZ 50000000U /**< 50 MHZ */
-#define XSDPS_CLK_52_MHZ 52000000U /**< 52 MHZ */
-#define XSDPS_SD_VER_1_0 0x1U /**< SD ver 1 */
-#define XSDPS_SD_VER_2_0 0x2U /**< SD ver 2 */
-#define XSDPS_SCR_BLKCNT 1U /**< SCR Block Count */
-#define XSDPS_SCR_BLKSIZE 8U /**< SCR Block Size */
-#define XSDPS_1_BIT_WIDTH 0x1U /**< Bus Width 1 */
-#define XSDPS_4_BIT_WIDTH 0x2U /**< Bus Width 4 */
-#define XSDPS_8_BIT_WIDTH 0x3U /**< Bus Width 8 */
-#define XSDPS_UHS_SPEED_MODE_SDR12 0x0U /**< SDR12 mode */
-#define XSDPS_UHS_SPEED_MODE_SDR25 0x1U /**< SDR25 mode */
-#define XSDPS_UHS_SPEED_MODE_SDR50 0x2U /**< SDR50 mode */
-#define XSDPS_UHS_SPEED_MODE_SDR104 0x3U /**< SDR104 mode */
-#define XSDPS_UHS_SPEED_MODE_DDR50 0x4U /**< DDR50 mode */
-#define XSDPS_HIGH_SPEED_MODE 0x5U /**< High Speed mode */
-#define XSDPS_DEFAULT_SPEED_MODE 0x6U /**< Default speed mode */
-#define XSDPS_HS200_MODE 0x7U /**< eMMC HS200 mode */
-#define XSDPS_DDR52_MODE 0x4U /**< eMMC DDR52 mode */
-#define XSDPS_SWITCH_CMD_BLKCNT 1U /**< Blk cnt for SWITCH cmd */
-#define XSDPS_SWITCH_CMD_BLKSIZE 64U /**< Blk sz for SWITCH cmd */
-#define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U /**< SWITCH cmd to Get HS */
-#define XSDPS_SWITCH_CMD_HS_SET 0x80FFFFF1U /**< SWITCH cmd to Set HS */
-#define XSDPS_SWITCH_CMD_SDR12_SET 0x80FFFFF0U /**< SWITCH cmd to Set SDR12 */
-#define XSDPS_SWITCH_CMD_SDR25_SET 0x80FFFFF1U /**< SWITCH cmd to Set SDR25 */
-#define XSDPS_SWITCH_CMD_SDR50_SET 0x80FFFFF2U /**< SWITCH cmd to Set SDR50 */
-#define XSDPS_SWITCH_CMD_SDR104_SET 0x80FFFFF3U /**< SWITCH cmd to Set SDR104 */
-#define XSDPS_SWITCH_CMD_DDR50_SET 0x80FFFFF4U /**< SWITCH cmd to Set DDR50 */
-#define XSDPS_EXT_CSD_CMD_BLKCNT 1U /**< Blk Cnt for EXT CSD */
-#define XSDPS_EXT_CSD_CMD_BLKSIZE 512U /**< Blk Sz for EXT CSD */
-#define XSDPS_TUNING_CMD_BLKCNT 1U /**< Blk Cnt for Tuning cmd */
-#define XSDPS_TUNING_CMD_BLKSIZE 64U /**< Blk Sz for Tuning cmd */
-#define XSDPS_SD_STATUS_BLKCNT 1U /**< Blk Cnt for SD status */
-#define XSDPS_SD_STATUS_BLKSIZE 64U /**< Blk Sz for SD status */
-
-#define XSDPS_HIGH_SPEED_MAX_CLK 50000000U /**< Max clk for HS mode */
-#define XSDPS_UHS_SDR104_MAX_CLK 208000000U /**< Max clk for SDR104 mode */
-#define XSDPS_UHS_SDR50_MAX_CLK 100000000U /**< Max clk for SDR50 mode */
-#define XSDPS_UHS_DDR50_MAX_CLK 50000000U /**< Max clk for DDR50 mode */
-#define XSDPS_UHS_SDR25_MAX_CLK 50000000U /**< Max clk for SDR25 mode */
-#define XSDPS_UHS_SDR12_MAX_CLK 25000000U /**< Max clk for SDR12 mode */
-
-#define SD_DRIVER_TYPE_B 0x01U /**< Driver Type B */
-#define SD_DRIVER_TYPE_A 0x02U /**< Driver Type A */
-#define SD_DRIVER_TYPE_C 0x04U /**< Driver Type C */
-#define SD_DRIVER_TYPE_D 0x08U /**< Driver Type D */
-#define SD_SET_CURRENT_LIMIT_200 0U /**< Current limit 200mA */
-#define SD_SET_CURRENT_LIMIT_400 1U /**< Current limit 400mA */
-#define SD_SET_CURRENT_LIMIT_600 2U /**< Current limit 600mA */
-#define SD_SET_CURRENT_LIMIT_800 3U /**< Current limit 800mA */
-
-#define SD_MAX_CURRENT_200 (1U << SD_SET_CURRENT_LIMIT_200) /**< Current limit 200mA Arg */
-#define SD_MAX_CURRENT_400 (1U << SD_SET_CURRENT_LIMIT_400) /**< Current limit 400mA Arg */
-#define SD_MAX_CURRENT_600 (1U << SD_SET_CURRENT_LIMIT_600) /**< Current limit 600mA Arg */
-#define SD_MAX_CURRENT_800 (1U << SD_SET_CURRENT_LIMIT_800) /**< Current limit 800mA Arg */
-
-#define XSDPS_SD_SDR12_MAX_CLK 25000000U /**< Max clk for SDR12 mode */
-#define XSDPS_SD_SDR25_MAX_CLK 50000000U /**< Max clk for SDR25 mode */
-#define XSDPS_SD_SDR50_MAX_CLK 100000000U /**< Max clk for SDR50 mode */
-#define XSDPS_SD_DDR50_MAX_CLK 50000000U /**< Max clk for DDR50 mode */
-#define XSDPS_SD_SDR104_MAX_CLK 208000000U /**< Max clk for SDR104 mode */
-/**
- * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller
- * than the clock value coming from the core. This value is kept to safely
- * switch to SDR104 mode if the SD card supports it.
- */
-#define XSDPS_SD_INPUT_MAX_CLK 175000000U
-
-#define XSDPS_MMC_HS200_MAX_CLK 200000000U /**< Max clk for MMC HS200 mode */
-#define XSDPS_MMC_HSD_MAX_CLK 52000000U /**< Max clk for MMC HSD mode */
-#define XSDPS_MMC_DDR_MAX_CLK 52000000U /**< Max clk for MMC DDR52 mode */
-
-/**
- * @name Card states
- * @{
- */
-/**
- * Definition for Card state.
- */
-#define XSDPS_CARD_STATE_IDLE 0U
-#define XSDPS_CARD_STATE_RDY 1U
-#define XSDPS_CARD_STATE_IDEN 2U
-#define XSDPS_CARD_STATE_STBY 3U
-#define XSDPS_CARD_STATE_TRAN 4U
-#define XSDPS_CARD_STATE_DATA 5U
-#define XSDPS_CARD_STATE_RCV 6U
-#define XSDPS_CARD_STATE_PROG 7U
-#define XSDPS_CARD_STATE_DIS 8U
-#define XSDPS_CARD_STATE_BTST 9U
-#define XSDPS_CARD_STATE_SLP 10U
-/** @} */
-
-#define XSDPS_SLOT_REM 0U /**< Removable slot */
-#define XSDPS_SLOT_EMB 1U /**< Embedded slot */
-
-#define XSDPS_WIDTH_8 8U /**< Bus width 8 */
-#define XSDPS_WIDTH_4 4U /**< Bus width 4 */
-
-/**
- * @name Tap delays
- * @{
- */
-/**
- * SD/eMMC ITAP and OTAP delays for different operating modes
- * for both Versal and ZynqMP platforms.
- */
-#ifdef versal
-#define SD_ITAPDLY_SEL_MASK 0x000000FFU
-#define SD_OTAPDLY_SEL_MASK 0x0000003FU
-#define SD_ITAPDLY 0x0000F0F8U
-#define SD_OTAPDLY 0x0000F0FCU
-#define SD0_DLL_CTRL 0x00000448U
-#define SD1_DLL_CTRL 0x000004C8U
-#define SD_DLL_RST 0x00000004U
-#define SD_ITAPCHGWIN 0x00000200U
-#define SD_ITAPDLYENA 0x00000100U
-#define SD_OTAPDLYENA 0x00000040U
-#define SD_OTAPDLYSEL_HS200_B0 0x00000002U
-#define SD_OTAPDLYSEL_HS200_B2 0x00000002U
-#define SD_ITAPDLYSEL_SD50 0x0000000EU
-#define SD_OTAPDLYSEL_SD50 0x00000003U
-#define SD_ITAPDLYSEL_SD_DDR50 0x00000036U
-#define SD_ITAPDLYSEL_EMMC_DDR50 0x0000001EU
-#define SD_OTAPDLYSEL_SD_DDR50 0x00000003U
-#define SD_OTAPDLYSEL_EMMC_DDR50 0x00000005U
-#define SD_ITAPDLYSEL_HSD 0x0000002CU
-#define SD_OTAPDLYSEL_SD_HSD 0x00000004U
-#define SD_OTAPDLYSEL_EMMC_HSD 0x00000005U
-#else
-#define SD0_ITAPDLY_SEL_MASK 0x000000FFU
-#define SD0_OTAPDLY_SEL_MASK 0x0000003FU
-#define SD1_ITAPDLY_SEL_MASK 0x00FF0000U
-#define SD1_OTAPDLY_SEL_MASK 0x003F0000U
-#define SD_DLL_CTRL 0x00000358U
-#define SD_ITAPDLY 0x00000314U
-#define SD_OTAPDLY 0x00000318U
-#define SD0_DLL_RST 0x00000004U
-#define SD1_DLL_RST 0x00040000U
-#define SD0_ITAPCHGWIN 0x00000200U
-#define SD0_ITAPDLYENA 0x00000100U
-#define SD0_OTAPDLYENA 0x00000040U
-#define SD1_ITAPCHGWIN 0x02000000U
-#define SD1_ITAPDLYENA 0x01000000U
-#define SD1_OTAPDLYENA 0x00400000U
-#define SD_OTAPDLYSEL_HS200_B0 0x00000003U
-#define SD_OTAPDLYSEL_HS200_B2 0x00000002U
-#define SD_ITAPDLYSEL_SD50 0x00000014U
-#define SD_OTAPDLYSEL_SD50 0x00000003U
-#define SD_ITAPDLYSEL_SD_DDR50 0x0000003DU
-#define SD_ITAPDLYSEL_EMMC_DDR50 0x00000012U
-#define SD_OTAPDLYSEL_SD_DDR50 0x00000004U
-#define SD_OTAPDLYSEL_EMMC_DDR50 0x00000006U
-#define SD_ITAPDLYSEL_HSD 0x00000015U
-#define SD_OTAPDLYSEL_SD_HSD 0x00000005U
-#define SD_OTAPDLYSEL_EMMC_HSD 0x00000006U
-#endif
-/** @} */
-
-#ifdef __MICROBLAZE__
-#define XPS_SYS_CTRL_BASEADDR 0xFF180000U /**< System controller Baseaddress */
-#endif
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#define XSdPs_In64 Xil_In64 /**< Low level 64-bit data read */
-#define XSdPs_Out64 Xil_Out64 /**< Low level 64-bit data write */
-
-#define XSdPs_In32 Xil_In32 /**< Low level 32-bit data read */
-#define XSdPs_Out32 Xil_Out32 /**< Low level 32-bit data write */
-
-#define XSdPs_In16 Xil_In16 /**< Low level 16-bit data read */
-#define XSdPs_Out16 Xil_Out16 /**< Low level 16-bit data write */
-
-#define XSdPs_In8 Xil_In8 /**< Low level 8-bit data read */
-#define XSdPs_Out8 Xil_Out8 /**< Low level 8-bit data write */
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param InstancePtr is the pointer to the sdps instance.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
-*
-******************************************************************************/
-#define XSdPs_ReadReg64(InstancePtr, RegOffset) \
- XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset)
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param InstancePtr is the pointer to the sdps instance.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
-* u64 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
- XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
- (RegisterValue))
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-#define XSdPs_ReadReg(BaseAddress, RegOffset) \
- XSdPs_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u32 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg >>= ((RegOffset & 0x3)*8);
- return (u16)Reg;
-#else
- return XSdPs_In16((BaseAddress) + (RegOffset));
-#endif
-}
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u16 RegisterValue)
-*
-******************************************************************************/
-
-static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg &= ~(0xFFFFU<<((RegOffset & 0x3)*8));
- Reg |= RegisterValue <<((RegOffset & 0x3)*8);
- XSdPs_Out32(BaseAddress, Reg);
-#else
- XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue));
-#endif
-}
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg >>= ((RegOffset & 0x3)*8);
- return (u8)Reg;
-#else
- return XSdPs_In8((BaseAddress) + (RegOffset));
-#endif
-}
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u8 RegisterValue)
-*
-******************************************************************************/
-static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg &= ~(0xFFU<<((RegOffset & 0x3)*8));
- Reg |= RegisterValue <<((RegOffset & 0x3)*8);
- XSdPs_Out32(BaseAddress, Reg);
-#else
- XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue));
-#endif
-}
-/***************************************************************************/
-/**
-* Macro to get present status register
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u8 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_GetPresentStatusReg(BaseAddress) \
- XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SD_HW_H_ */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/58/b0d01d555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/58/b0d01d555243001d18b399c1eb9b3628
deleted file mode 100644
index e811686..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/58/b0d01d555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,394 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xreg_cortexa53.h
-*
-* This header file contains definitions for using inline assembler code. It is
-* written specifically for the GNU.
-*
-* All of the ARM Cortex A53 GPRs, SPRs, and Debug Registers are defined along
-* with the positions of the bits within the registers.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.2 pkp 28/05/15 First release
-*
-* where bgen is the value of the baud rate generator, and bdiv is the value of
-* baud rate divider.
-*
-* Interrupts
-*
-* The FIFOs are not flushed when the driver is initialized, but a function is
-* provided to allow the user to reset the FIFOs if desired.
-*
-* The driver defaults to no interrupts at initialization such that interrupts
-* must be enabled if desired. An interrupt is generated for one of the
-* following conditions.
-*
-* - A change in the modem signals
-* - Data in the receive FIFO for a configuable time without receiver activity
-* - A parity error
-* - A framing error
-* - An overrun error
-* - Transmit FIFO is full
-* - Transmit FIFO is empty
-* - Receive FIFO is full
-* - Receive FIFO is empty
-* - Data in the receive FIFO equal to the receive threshold
-*
-* The application can control which interrupts are enabled using the
-* XUartPs_SetInterruptMask() function.
-*
-* In order to use interrupts, it is necessary for the user to connect the
-* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
-* system of the application. A separate handler should be provided by the
-* application to communicate with the interrupt system, and conduct
-* application specific interrupt handling. An application registers its own
-* handler through the XUartPs_SetHandler() function.
-*
-* Data Transfer
-*
-* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
-* driver to allow data to be sent and received. They can be used in either
-* polled or interrupt mode.
-*
-* @note
-*
-* The default configuration for the UART after initialization is:
-*
-* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
-* - 8 data bits
-* - 1 stop bit
-* - no parity
-* - FIFO's are enabled with a receive threshold of 8 bytes
-* - The RX timeout is enabled with a timeout of 1 (4 char times)
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00a drg/jz 01/12/10 First Release
-* 1.00a sdm 09/27/11 Fixed compiler warnings and also a bug
-* in XUartPs_SetFlowDelay where the value was not
-* being written to the register.
-* 1.01a sdm 12/20/11 Removed the InputClockHz parameter from the XUartPs
-* instance structure and the driver is updated to use
-* InputClockHz parameter from the XUartPs_Config config
-* structure.
-* Added a parameter to XUartPs_Config structure which
-* specifies whether the user has selected Modem pins
-* to be connected to MIO or FMIO.
-* Added the tcl file to generate the xparameters.h
-* 1.02a sg 05/16/12 Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
-* 1.03a sg 07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
-* with the correct values for CR 666724
-* Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
-* and XUARTPS_IXR_TTRIG.
-* Modified the name of these defines
-* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
-* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
-* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
-* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
-* 1.05a hk 08/22/13 Added API for uart reset and related
-* constant definitions.
-* 2.0 hk 03/07/14 Version number revised.
-* 2.1 hk 04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
-* 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing
-* baud rate. CR# 804281.
-* 3.0 vm 12/09/14 Modified source code according to misrac guideline.
-* Support for Zynq Ultrascale Mp added.
-* 3.1 kvn 04/10/15 Modified code for latest RTL changes. Also added
-* platform variable in driver instance structure.
-* 3.1 adk 14/03/16 Include interrupt examples in the peripheral test when
-* uart is connected to a valid interrupt controller CR#946803.
-* 3.2 rk 07/20/16 Modified the logic for transmission break bit set
-* 3.4 ms 01/23/17 Added xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 3.6 ms 02/16/18 Updates the flow control mode offset value in modem
-* control register.
-* 3.7 aru 08/17/18 Resolved MISRA-C:2012 compliance mandatory violations.
-* 3.9 rna 12/03/19 Modified the XUARTPS_MAX_RATE macro.
-* 3.9 sd 02/06/20 Added clock support
-*
-*
-*
-*****************************************************************************/
-
-#ifndef XUARTPS_H /* prevent circular inclusions */
-#define XUARTPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xuartps_hw.h"
-#include "xplatform_info.h"
-#if defined (XCLOCKING)
-#include "xil_clocking.h"
-#endif
-
-/************************** Constant Definitions ****************************/
-
-/*
- * The following constants indicate the max and min baud rates and these
- * numbers are based only on the testing that has been done. The hardware
- * is capable of other baud rates.
- */
-#define XUARTPS_MAX_RATE 6240000U
-#define XUARTPS_MIN_RATE 110U
-
-#define XUARTPS_DFT_BAUDRATE 115200U /* Default baud rate */
-
-/** @name Configuration options
- * @{
- */
-/**
- * These constants specify the options that may be set or retrieved
- * with the driver, each is a unique bit mask such that multiple options
- * may be specified. These constants indicate the available options
- * in active state.
- *
- */
-
-#define XUARTPS_OPTION_SET_BREAK 0x0080U /**< Starts break transmission */
-#define XUARTPS_OPTION_STOP_BREAK 0x0040U /**< Stops break transmission */
-#define XUARTPS_OPTION_RESET_TMOUT 0x0020U /**< Reset the receive timeout */
-#define XUARTPS_OPTION_RESET_TX 0x0010U /**< Reset the transmitter */
-#define XUARTPS_OPTION_RESET_RX 0x0008U /**< Reset the receiver */
-#define XUARTPS_OPTION_ASSERT_RTS 0x0004U /**< Assert the RTS bit */
-#define XUARTPS_OPTION_ASSERT_DTR 0x0002U /**< Assert the DTR bit */
-#define XUARTPS_OPTION_SET_FCM 0x0001U /**< Turn on flow control mode */
-/*@}*/
-
-
-/** @name Channel Operational Mode
- *
- * The UART can operate in one of four modes: Normal, Local Loopback, Remote
- * Loopback, or automatic echo.
- *
- * @{
- */
-
-#define XUARTPS_OPER_MODE_NORMAL (u8)0x00U /**< Normal Mode */
-#define XUARTPS_OPER_MODE_AUTO_ECHO (u8)0x01U /**< Auto Echo Mode */
-#define XUARTPS_OPER_MODE_LOCAL_LOOP (u8)0x02U /**< Local Loopback Mode */
-#define XUARTPS_OPER_MODE_REMOTE_LOOP (u8)0x03U /**< Remote Loopback Mode */
-
-/* @} */
-
-/** @name Data format values
- *
- * These constants specify the data format that the driver supports.
- * The data format includes the number of data bits, the number of stop
- * bits and parity.
- *
- * @{
- */
-#define XUARTPS_FORMAT_8_BITS 0U /**< 8 data bits */
-#define XUARTPS_FORMAT_7_BITS 2U /**< 7 data bits */
-#define XUARTPS_FORMAT_6_BITS 3U /**< 6 data bits */
-
-#define XUARTPS_FORMAT_NO_PARITY 4U /**< No parity */
-#define XUARTPS_FORMAT_MARK_PARITY 3U /**< Mark parity */
-#define XUARTPS_FORMAT_SPACE_PARITY 2U /**< parity */
-#define XUARTPS_FORMAT_ODD_PARITY 1U /**< Odd parity */
-#define XUARTPS_FORMAT_EVEN_PARITY 0U /**< Even parity */
-
-#define XUARTPS_FORMAT_2_STOP_BIT 2U /**< 2 stop bits */
-#define XUARTPS_FORMAT_1_5_STOP_BIT 1U /**< 1.5 stop bits */
-#define XUARTPS_FORMAT_1_STOP_BIT 0U /**< 1 stop bit */
-/*@}*/
-
-/** @name Callback events
- *
- * These constants specify the handler events that an application can handle
- * using its specific handler function. Note that these constants are not bit
- * mask, so only one event can be passed to an application at a time.
- *
- * @{
- */
-#define XUARTPS_EVENT_RECV_DATA 1U /**< Data receiving done */
-#define XUARTPS_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */
-#define XUARTPS_EVENT_SENT_DATA 3U /**< Data transmission done */
-#define XUARTPS_EVENT_RECV_ERROR 4U /**< A receive error detected */
-#define XUARTPS_EVENT_MODEM 5U /**< Modem status changed */
-#define XUARTPS_EVENT_PARE_FRAME_BRKE 6U /**< A receive parity, frame, break
- * error detected */
-#define XUARTPS_EVENT_RECV_ORERR 7U /**< A receive overrun error detected */
-
-/*@}*/
-
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of device (IPIF) */
- u32 InputClockHz;/**< Input clock frequency */
- s32 ModemPinsConnected; /** Specifies whether modem pins are connected
- * to MIO or FMIO */
-#if defined (XCLOCKING)
- u32 RefClk; /**< Input clock frequency */
-#endif
-} XUartPs_Config;
-
-/* Keep track of state information about a data buffer in the interrupt mode. */
-typedef struct {
- u8 *NextBytePtr;
- u32 RequestedBytes;
- u32 RemainingBytes;
-} XUartPsBuffer;
-
-/**
- * Keep track of data format setting of a device.
- */
-typedef struct {
- u32 BaudRate; /**< In bps, ie 1200 */
- u32 DataBits; /**< Number of data bits */
- u32 Parity; /**< Parity */
- u8 StopBits; /**< Number of stop bits */
-} XUartPsFormat;
-
-/******************************************************************************/
-/**
- * This data type defines a handler that an application defines to communicate
- * with interrupt system to retrieve state information about an application.
- *
- * @param CallBackRef is a callback reference passed in by the upper layer
- * when setting the handler, and is passed back to the upper layer
- * when the handler is called. It is used to find the device driver
- * instance.
- * @param Event contains one of the event constants indicating events that
- * have occurred.
- * @param EventData contains the number of bytes sent or received at the
- * time of the call for send and receive events and contains the
- * modem status for modem events.
- *
- ******************************************************************************/
-typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
- u32 EventData);
-
-/**
- * The XUartPs driver instance data structure. A pointer to an instance data
- * structure is passed around by functions to refer to a specific driver
- * instance.
- */
-typedef struct {
- XUartPs_Config Config; /* Configuration data structure */
- u32 InputClockHz; /* Input clock frequency */
- u32 IsReady; /* Device is initialized and ready */
- u32 BaudRate; /* Current baud rate */
-
- XUartPsBuffer SendBuffer;
- XUartPsBuffer ReceiveBuffer;
-
- XUartPs_Handler Handler;
- void *CallBackRef; /* Callback reference for event handler */
- u32 Platform;
- u8 is_rxbs_error;
-} XUartPs;
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* Get the UART Channel Status Register.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_GetChannelStatus(InstancePtr) \
- Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
-
-/****************************************************************************/
-/**
-* Get the UART Mode Control Register.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XUartPs_GetControl(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_GetModeControl(InstancePtr) \
- Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
-
-/****************************************************************************/
-/**
-* Set the UART Mode Control Register.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
-*
-******************************************************************************/
-#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
- Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
- (u32)(RegisterValue))
-
-/****************************************************************************/
-/**
-* Enable the transmitter and receiver of the UART.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_EnableUart(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_EnableUart(InstancePtr) \
- Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
- ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
- (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
-
-/****************************************************************************/
-/**
-* Disable the transmitter and receiver of the UART.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_DisableUart(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_DisableUart(InstancePtr) \
- Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
- (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
- (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
-
-/****************************************************************************/
-/**
-* Determine if the transmitter FIFO is empty.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-* - TRUE if a byte can be sent
-* - FALSE if the Transmitter Fifo is not empty
-*
-* @note C-Style signature:
-* u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_IsTransmitEmpty(InstancePtr) \
- ((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
- (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
-
-
-/************************** Function Prototypes *****************************/
-
-/* Static lookup function implemented in xuartps_sinit.c */
-XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
-
-/* Interface functions implemented in xuartps.c */
-s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
- XUartPs_Config * Config, u32 EffectiveAddr);
-
-u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
- u32 NumBytes);
-
-u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
- u32 NumBytes);
-
-s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
-
-/* Options functions in xuartps_options.c */
-void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
-
-u16 XUartPs_GetOptions(XUartPs *InstancePtr);
-
-void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
-
-u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
-
-u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
-
-u32 XUartPs_IsSending(XUartPs *InstancePtr);
-
-u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
-
-void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
-
-u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
-
-void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
-
-u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
-
-void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
-
-s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
-
-void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
-
-/* interrupt functions in xuartps_intr.c */
-u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
-
-void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
-
-void XUartPs_InterruptHandler(XUartPs *InstancePtr);
-
-void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
- void *CallBackRef);
-
-/* self-test functions in xuartps_selftest.c */
-s32 XUartPs_SelfTest(XUartPs *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/58/d01807595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/58/d01807595243001d18b399c1eb9b3628
deleted file mode 100644
index eb5eb30..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/58/d01807595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,117 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file asm_vectors.S
-*
-* This file contains the initial vector table for the Cortex R5 processor
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 5.00 pkp 02/10/14 Initial version
-* 6.0 mus 27/07/16 Added UndefinedException handler
-* 6.3 pkp 02/13/17 Added support for hard float
-*
-*
-******************************************************************************/
-.org 0
-.text
-
-.globl _boot
-.globl _vector_table
-
-.globl FIQInterrupt
-.globl IRQInterrupt
-.globl SWInterrupt
-.globl DataAbortInterrupt
-.globl PrefetchAbortInterrupt
-
-.globl IRQHandler
-.globl prof_pc
-
-.section .vectors, "a"
-_vector_table:
- ldr pc,=_boot
- ldr pc,=Undefined
- ldr pc,=SVCHandler
- ldr pc,=PrefetchAbortHandler
- ldr pc,=DataAbortHandler
- NOP /* Placeholder for address exception vector*/
- ldr pc,=IRQHandler
- ldr pc,=FIQHandler
-
-.text
-IRQHandler: /* IRQ vector handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/
-#ifndef __SOFTFP__
-
- vpush {d0-d7} /* Store floating point registers */
- vmrs r1, FPSCR
- push {r1}
- vmrs r1, FPEXC
- push {r1}
-#endif
- bl IRQInterrupt /* IRQ vector */
-#ifndef __SOFTFP__
-
- pop {r1} /* Restore floating point registers */
- vmsr FPEXC, r1
- pop {r1}
- vmsr FPSCR, r1
- vpop {d0-d7}
-#endif
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
- subs pc, lr, #4 /* adjust return */
-FIQHandler: /* FIQ vector handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
-FIQLoop:
- bl FIQInterrupt /* FIQ vector */
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
- subs pc, lr, #4 /* adjust return */
-
-Undefined: /* Undefined handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- ldr r0, =UndefinedExceptionAddr
- sub r1, lr, #4
- str r1, [r0] /* Store address of instruction causing undefined exception */
-
- bl UndefinedException /* UndefinedException: call C function here */
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
- movs pc, lr
-
-SVCHandler: /* SWI handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- tst r0, #0x20 /* check the T bit */
- ldrneh r0, [lr,#-2] /* Thumb mode */
- bicne r0, r0, #0xff00 /* Thumb mode */
- ldreq r0, [lr,#-4] /* ARM mode */
- biceq r0, r0, #0xff000000 /* ARM mode */
- bl SWInterrupt /* SWInterrupt: call C function here */
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
- movs pc, lr /* adjust return */
-
-DataAbortHandler: /* Data Abort handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- ldr r0, =DataAbortAddr
- sub r1, lr, #8
- str r1, [r0] /* Stores instruction causing data abort */
- bl DataAbortInterrupt /*DataAbortInterrupt :call C function here */
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
- subs pc, lr, #8 /* adjust return */
-
-PrefetchAbortHandler: /* Prefetch Abort handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- ldr r0, =PrefetchAbortAddr
- sub r1, lr, #4
- str r1, [r0] /* Stores instruction causing prefetch abort */
- bl PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
- subs pc, lr, #4 /* adjust return */
-
-
-.end
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/58/d047a9555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/58/d047a9555243001d18b399c1eb9b3628
deleted file mode 100644
index 76a4904..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/58/d047a9555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,16 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include
-#include "xil_types.h"
-
-void exit(sint32 arg)
-{
- while(1) {
- ;
- }
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/58/f0d290545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/58/f0d290545243001d18b399c1eb9b3628
deleted file mode 100644
index 179c840..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/58/f0d290545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,329 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xdmaps.h
-* @addtogroup dmaps_v2_8
-* @{
-* @details
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00 hbm 08/19/10 First Release
-* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
-* the maximum number of channels.
-* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
-* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
-* Added the tcl file to automatically generate the
-* xparameters.h
-* 1.02a sg 05/16/12 Made changes for doxygen and moved some function
-* header from the xdmaps.h file to xdmaps.c file
-* Other cleanup for coding guidelines and CR 657109
-* and CR 657898
-* The xdmaps_example_no_intr.c example is removed
-* as it is using interrupts and is similar to
-* the interrupt example - CR 652477
-* 1.03a sg 07/16/2012 changed inline to __inline for CR665681
-* 1.04a nm 10/22/2012 Fixed CR# 681671.
-* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled
-* with -Wall and -Wextra option in bsp.
-* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
-* function description.
-* Fixed CR# 704396. Removed unused variables
-* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
-* function.
-* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc.
-* Removed the PDBG prints. By default they were always
-* defined out and never used. The PDBG is non-standard for
-* Xilinx drivers and no other driver does something similar.
-* Since there is no easy way to fix compilation issues with
-* the IARCC compiler around PDBG, it is better to remove it.
-* Users can always use xil_printfs if they want to debug.
-* 2.0 adk 10/12/13 Updated as per the New Tcl API's
-* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
-* 2.2 mus 08/12/16 Declared all inline functions in xdmaps.c as extern, to avoid
-* linker error for IAR compiler
-* 2.3 ms 01/23/17 Modified xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 2.4 adk 13/08/18 Fixed armcc compiler warnings in the driver CR-1008310.
-* 2.8 sk 05/18/21 Modify all inline functions declarations from extern inline
-* to static inline to avoid the linkage conflict for IAR compiler.
-*
-*
-*****************************************************************************/
-
-#ifndef XDMAPS_H /* prevent circular inclusions */
-#define XDMAPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xparameters.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-
-#include "xdmaps_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of device (IPIF) */
-} XDmaPs_Config;
-
-
-/** DMA channle control structure. It's for AXI bus transaction.
- * This struct will be translated into a 32-bit channel control register value.
- */
-typedef struct {
- unsigned int EndianSwapSize; /**< Endian swap size. */
- unsigned int DstCacheCtrl; /**< Destination cache control */
- unsigned int DstProtCtrl; /**< Destination protection control */
- unsigned int DstBurstLen; /**< Destination burst length */
- unsigned int DstBurstSize; /**< Destination burst size */
- unsigned int DstInc; /**< Destination incrementing or fixed
- * address */
- unsigned int SrcCacheCtrl; /**< Source cache control */
- unsigned int SrcProtCtrl; /**< Source protection control */
- unsigned int SrcBurstLen; /**< Source burst length */
- unsigned int SrcBurstSize; /**< Source burst size */
- unsigned int SrcInc; /**< Source incrementing or fixed
- * address */
-} XDmaPs_ChanCtrl;
-
-/** DMA block descriptor stucture.
- */
-typedef struct {
- u32 SrcAddr; /**< Source starting address */
- u32 DstAddr; /**< Destination starting address */
- unsigned int Length; /**< Number of bytes for the block */
-} XDmaPs_BD;
-
-/**
- * A DMA command consisits of a channel control struct, a block descriptor,
- * a user defined program, a pointer pointing to generated DMA program, and
- * execution result.
- *
- */
-typedef struct {
- XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */
- XDmaPs_BD BD; /**< Together with SgLength field,
- * it's a scatter-gather list.
- */
- void *UserDmaProg; /**< If user wants the driver to
- * execute their own DMA program,
- * this field points to the DMA
- * program.
- */
- int UserDmaProgLength; /**< The length of user defined
- * DMA program.
- */
-
- void *GeneratedDmaProg; /**< The DMA program genreated
- * by the driver. This field will be
- * set if a user invokes the DMA
- * program generation function. Or
- * the DMA command is finished and
- * a user informs the driver not to
- * release the program buffer.
- * This field has two purposes, one
- * is to ask the driver to generate
- * a DMA program while the DMAC is
- * performaning DMA transactions. The
- * other purpose is to debug the
- * driver.
- */
- int GeneratedDmaProgLength; /**< The length of the DMA program
- * generated by the driver
- */
- int DmaStatus; /**< 0 on success, otherwise error code
- */
- u32 ChanFaultType; /**< Channel fault type in case of fault
- */
- u32 ChanFaultPCAddr; /**< Channel fault PC address
- */
-} XDmaPs_Cmd;
-
-/**
- * It's the done handler a user can set for a channel
- */
-typedef void (*XDmaPsDoneHandler) (unsigned int Channel,
- XDmaPs_Cmd *DmaCmd,
- void *CallbackRef);
-
-/**
- * It's the fault handler a user can set for a channel
- */
-typedef void (*XDmaPsFaultHandler) (unsigned int Channel,
- XDmaPs_Cmd *DmaCmd,
- void *CallbackRef);
-
-#define XDMAPS_MAX_CHAN_BUFS 2
-#define XDMAPS_CHAN_BUF_LEN 128
-
-/**
- * The XDmaPs_ProgBuf is the struct for a DMA program buffer.
- */
-typedef struct {
- char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the
- * content */
- unsigned Len; /**< The actual length of the DMA
- * program in bytes. */
- int Allocated; /**< A tag indicating whether the
- * buffer is allocated or not */
-} XDmaPs_ProgBuf;
-
-/**
- * The XDmaPs_ChannelData is a struct to book keep individual channel of
- * the DMAC.
- */
-typedef struct {
- unsigned DevId; /**< Device id indicating which DMAC */
- unsigned ChanId; /**< Channel number of the DMAC */
- XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of
- program buffers*/
- XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */
- void *DoneRef; /**< Done interrupt callback data */
- XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */
- XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished.
- * This field is for debugging purpose
- */
- int HoldDmaProg; /**< A tag indicating whether to hold the
- * DMA program after the DMA is done.
- */
-
-} XDmaPs_ChannelData;
-
-/**
- * The XDmaPs driver instance data structure. A pointer to an instance data
- * structure is passed around by functions to refer to a specific driver
- * instance.
- */
-typedef struct {
- XDmaPs_Config Config; /**< Configuration data structure */
- int IsReady; /**< Device is Ready */
- int CacheLength; /**< icache length */
- XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */
- void *FaultRef; /**< fault call back data */
- XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV];
- /**<
- * channel data
- */
-} XDmaPs;
-
-/*
- * Functions implemented in xdmaps.c
- */
-int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
- XDmaPs_Config *Config,
- u32 EffectiveAddr);
-
-int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
- XDmaPs_Cmd *Cmd,
- int HoldDmaProg);
-
-int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel);
-int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel,
- XDmaPs_Cmd *Cmd);
-int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel,
- XDmaPs_Cmd *Cmd);
-void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
-
-
-int XDmaPs_ResetManager(XDmaPs *InstPtr);
-int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel);
-
-
-int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
- unsigned Channel,
- XDmaPsDoneHandler DoneHandler,
- void *CallbackRef);
-
-int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
- XDmaPsFaultHandler FaultHandler,
- void *CallbackRef);
-
-void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
-int XDmaPs_Instr_DMARMB(char *DmaProg);
-int XDmaPs_Instr_DMAWMB(char *DmaProg);
-
-/**
- * To avoid linkage error,modify all inline functions from extern
- * inline to static inline for IAR compiler
- */
-#ifdef __ICCARM__
-static INLINE int XDmaPs_Instr_DMAEND(char *DmaProg);
-static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src);
-static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
- u32 Imm, unsigned int Ns);
-static INLINE int XDmaPs_Instr_DMALD(char *DmaProg);
-static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
- unsigned LoopIterations);
-static INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc);
-static INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm);
-static INLINE int XDmaPs_Instr_DMANOP(char *DmaProg);
-static INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber);
-static INLINE int XDmaPs_Instr_DMAST(char *DmaProg);
-static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize);
-static INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize);
-#endif
-
-/**
- * Driver done interrupt service routines for the channels.
- * We need this done ISR mainly because the driver needs to release the
- * DMA program buffer. This is the one that connects the GIC
- */
-void XDmaPs_DoneISR_0(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_1(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_2(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_3(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_4(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_5(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_6(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_7(XDmaPs *InstPtr);
-
-/**
- * Driver fault interrupt service routine
- */
-void XDmaPs_FaultISR(XDmaPs *InstPtr);
-
-
-/*
- * Static loopup function implemented in xdmaps_sinit.c
- */
-XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId);
-
-
-/*
- * self-test functions in xdmaps_selftest.c
- */
-int XDmaPs_SelfTest(XDmaPs *InstPtr);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/59/402087525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/59/402087525243001d18b399c1eb9b3628
deleted file mode 100644
index 980f394..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/59/402087525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,571 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xadcps.h
-* @addtogroup xadcps_v2_6
-* @{
-* @details
-*
-* The XAdcPs driver supports the Xilinx XADC/ADC device.
-*
-* The XADC/ADC device has the following features:
-* - 10-bit, 200-KSPS (kilo samples per second)
-* Analog-to-Digital Converter (ADC)
-* - Monitoring of on-chip supply voltages and temperature
-* - 1 dedicated differential analog-input pair and
-* 16 auxiliary differential analog-input pairs
-* - Automatic alarms based on user defined limits for the on-chip
-* supply voltages and temperature
-* - Automatic Channel Sequencer, programmable averaging, programmable
-* acquisition time for the external inputs, unipolar or differential
-* input selection for the external inputs
-* - Inbuilt Calibration
-* - Optional interrupt request generation
-*
-*
-* The user should refer to the hardware device specification for detailed
-* information about the device.
-*
-* This header file contains the prototypes of driver functions that can
-* be used to access the XADC/ADC device.
-*
-*
-* XADC Channel Sequencer Modes
-*
-* The XADC Channel Sequencer supports the following operating modes:
-*
-* - Default : This is the default mode after power up.
-* In this mode of operation the XADC operates in
-* a sequence mode, monitoring the on chip sensors:
-* Temperature, VCCINT, and VCCAUX.
-* - One pass through sequence : In this mode the XADC
-* converts the channels enabled in the Sequencer Channel Enable
-* registers for a single pass and then stops.
-* - Continuous cycling of sequence : In this mode the XADC
-* converts the channels enabled in the Sequencer Channel Enable
-* registers continuously.
-* - Single channel mode: In this mode the XADC Channel
-* Sequencer is disabled and the XADC operates in a
-* Single Channel Mode.
-* The XADC can operate either in a Continuous or Event
-* driven sampling mode in the single channel mode.
-* - Simultaneous Sampling Mode: In this mode the XADC Channel
-* Sequencer will automatically sequence through eight fixed pairs
-* of auxiliary analog input channels for simulataneous conversion.
-* - Independent ADC mode: In this mode the first ADC (A) is used to
-* is used to implement a fixed monitoring mode similar to the
-* default mode but the alarm fucntions ar eenabled.
-* The second ADC (B) is available to be used with external analog
-* input channels only.
-*
-* Read the XADC spec for more information about the sequencer modes.
-*
-* Initialization and Configuration
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate to the XADC/ADC device.
-*
-* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC
-* device. The user needs to first call the XAdcPs_LookupConfig() API which
-* returns the Configuration structure pointer which is passed as a parameter to
-* the XAdcPs_CfgInitialize() API.
-*
-*
-* Interrupts
-*
-* The XADC/ADC device supports interrupt driven mode and the default
-* operation mode is polling mode.
-*
-* The interrupt mode is available only if hardware is configured to support
-* interrupts.
-*
-* This driver does not provide a Interrupt Service Routine (ISR) for the device.
-* It is the responsibility of the application to provide one if needed. Refer to
-* the interrupt example provided with this driver for details on using the
-* device in interrupt mode.
-*
-*
-* Virtual Memory
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-*
-* Threads
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-*
-* Asserts
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-*
-* Building the driver
-*
-* The XAdcPs driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-* Limitations of the driver
-*
-* XADC/ADC device can be accessed through the JTAG port and the PLB
-* interface. The driver implementation does not support the simultaneous access
-* of the device by both these interfaces. The user has to care of this situation
-* in the user application code.
-*
-*
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
-* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
-* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
-* in xadcps.c to fix CR #693371
-* 1.03a bss 11/01/13 Modified xadcps_hw.h to use correct Register offsets
-* CR#749687
-* 2.1 bss 08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
-* XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
-* XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
-* functions.
-* Modified Assert for XAdcPs_SetSingleChParams in
-* xadcps.c to fix CR #807563.
-* 2.2 bss 04/27/14 Modified to use correct Device Config base address in
-* xadcps.c (CR#854437).
-* ms 01/23/17 Added xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/05/17 Modified Comment lines in functions of xadcps
-* examples to recognize it as documentation block
-* for doxygen generation.
-* 2.3 mn 07/09/18 Fix Doxygen warning
-* 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors.
-* aad 12/17/20 Added missing function declarations and removed
-* functions with no definitions.
-*
-*
-*
-*****************************************************************************/
-#ifndef XADCPS_H /* Prevent circular inclusions */
-#define XADCPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xadcps_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**
- * @name Indexes for the different channels.
- * @{
- */
-#define XADCPS_CH_TEMP 0x0U /**< On Chip Temperature */
-#define XADCPS_CH_VCCINT 0x1U /**< VCCINT */
-#define XADCPS_CH_VCCAUX 0x2U /**< VCCAUX */
-#define XADCPS_CH_VPVN 0x3U /**< VP/VN Dedicated analog inputs */
-#define XADCPS_CH_VREFP 0x4U /**< VREFP */
-#define XADCPS_CH_VREFN 0x5U /**< VREFN */
-#define XADCPS_CH_VBRAM 0x6U /**< On-chip VBRAM Data Reg, 7 series */
-#define XADCPS_CH_SUPPLY_CALIB 0x07U /**< Supply Calib Data Reg */
-#define XADCPS_CH_ADC_CALIB 0x08U /**< ADC Offset Channel Reg */
-#define XADCPS_CH_GAINERR_CALIB 0x09U /**< Gain Error Channel Reg */
-#define XADCPS_CH_VCCPINT 0x0DU /**< On-chip PS VCCPINT Channel , Zynq */
-#define XADCPS_CH_VCCPAUX 0x0EU /**< On-chip PS VCCPAUX Channel , Zynq */
-#define XADCPS_CH_VCCPDRO 0x0FU /**< On-chip PS VCCPDRO Channel , Zynq */
-#define XADCPS_CH_AUX_MIN 16U /**< Channel number for 1st Aux Channel */
-#define XADCPS_CH_AUX_MAX 31U /**< Channel number for Last Aux channel */
-
-/*@}*/
-
-
-/**
- * @name Indexes for reading the Calibration Coefficient Data.
- * @{
- */
-#define XADCPS_CALIB_SUPPLY_COEFF 0U /**< Supply Offset Calib Coefficient */
-#define XADCPS_CALIB_ADC_COEFF 1U /**< ADC Offset Calib Coefficient */
-#define XADCPS_CALIB_GAIN_ERROR_COEFF 2U /**< Gain Error Calib Coefficient*/
-/*@}*/
-
-
-/**
- * @name Indexes for reading the Minimum/Maximum Measurement Data.
- * @{
- */
-#define XADCPS_MAX_TEMP 0U /**< Maximum Temperature Data */
-#define XADCPS_MAX_VCCINT 1U /**< Maximum VCCINT Data */
-#define XADCPS_MAX_VCCAUX 2U /**< Maximum VCCAUX Data */
-#define XADCPS_MAX_VBRAM 3U /**< Maximum VBRAM Data */
-#define XADCPS_MIN_TEMP 4U /**< Minimum Temperature Data */
-#define XADCPS_MIN_VCCINT 5U /**< Minimum VCCINT Data */
-#define XADCPS_MIN_VCCAUX 6U /**< Minimum VCCAUX Data */
-#define XADCPS_MIN_VBRAM 7U /**< Minimum VBRAM Data */
-#define XADCPS_MAX_VCCPINT 8U /**< Maximum VCCPINT Register , Zynq */
-#define XADCPS_MAX_VCCPAUX 9U /**< Maximum VCCPAUX Register , Zynq */
-#define XADCPS_MAX_VCCPDRO 0xAU /**< Maximum VCCPDRO Register , Zynq */
-#define XADCPS_MIN_VCCPINT 0xCU /**< Minimum VCCPINT Register , Zynq */
-#define XADCPS_MIN_VCCPAUX 0xDU /**< Minimum VCCPAUX Register , Zynq */
-#define XADCPS_MIN_VCCPDRO 0xEU /**< Minimum VCCPDRO Register , Zynq */
-
-/*@}*/
-
-
-/**
- * @name Alarm Threshold(Limit) Register (ATR) indexes.
- * @{
- */
-#define XADCPS_ATR_TEMP_UPPER 0U /**< High user Temperature */
-#define XADCPS_ATR_VCCINT_UPPER 1U /**< VCCINT high voltage limit register */
-#define XADCPS_ATR_VCCAUX_UPPER 2U /**< VCCAUX high voltage limit register */
-#define XADCPS_ATR_OT_UPPER 3U /**< VCCAUX high voltage limit register */
-#define XADCPS_ATR_TEMP_LOWER 4U /**< Upper Over Temperature limit Reg */
-#define XADCPS_ATR_VCCINT_LOWER 5U /**< VCCINT high voltage limit register */
-#define XADCPS_ATR_VCCAUX_LOWER 6U /**< VCCAUX low voltage limit register */
-#define XADCPS_ATR_OT_LOWER 7U /**< Lower Over Temperature limit */
-#define XADCPS_ATR_VBRAM_UPPER_ 8U /**< VRBAM Upper Alarm Reg, 7 Series */
-#define XADCPS_ATR_VCCPINT_UPPER 9U /**< VCCPINT Upper Alarm Reg, Zynq */
-#define XADCPS_ATR_VCCPAUX_UPPER 0xAU /**< VCCPAUX Upper Alarm Reg, Zynq */
-#define XADCPS_ATR_VCCPDRO_UPPER 0xBU /**< VCCPDRO Upper Alarm Reg, Zynq */
-#define XADCPS_ATR_VBRAM_LOWER 0xCU /**< VRBAM Lower Alarm Reg, 7 Series */
-#define XADCPS_ATR_VCCPINT_LOWER 0xDU /**< VCCPINT Lower Alarm Reg , Zynq */
-#define XADCPS_ATR_VCCPAUX_LOWER 0xEU /**< VCCPAUX Lower Alarm Reg , Zynq */
-#define XADCPS_ATR_VCCPDRO_LOWER 0xFU /**< VCCPDRO Lower Alarm Reg , Zynq */
-
-/*@}*/
-
-
-/**
- * @name Averaging to be done for the channels.
- * @{
- */
-#define XADCPS_AVG_0_SAMPLES 0U /**< No Averaging */
-#define XADCPS_AVG_16_SAMPLES 1U /**< Average 16 samples */
-#define XADCPS_AVG_64_SAMPLES 2U /**< Average 64 samples */
-#define XADCPS_AVG_256_SAMPLES 3U /**< Average 256 samples */
-
-/*@}*/
-
-
-/**
- * @name Channel Sequencer Modes of operation
- * @{
- */
-#define XADCPS_SEQ_MODE_SAFE 0U /**< Default Safe Mode */
-#define XADCPS_SEQ_MODE_ONEPASS 1U /**< Onepass through Sequencer */
-#define XADCPS_SEQ_MODE_CONTINPASS 2U /**< Continuous Cycling Sequencer */
-#define XADCPS_SEQ_MODE_SINGCHAN 3U /**< Single channel -No Sequencing */
-#define XADCPS_SEQ_MODE_SIMUL_SAMPLING 4U /**< Simultaneous sampling */
-#define XADCPS_SEQ_MODE_INDEPENDENT 8U /**< Independent mode */
-
-/*@}*/
-
-
-
-/**
- * @name Power Down Modes
- * @{
- */
-#define XADCPS_PD_MODE_NONE 0U /**< No Power Down */
-#define XADCPS_PD_MODE_ADCB 1U /**< Power Down ADC B */
-#define XADCPS_PD_MODE_XADC 2U /**< Power Down ADC A and ADC B */
-/*@}*/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the XADC/ADC
- * device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Device base address */
-} XAdcPs_Config;
-
-
-/**
- * The driver's instance data. The user is required to allocate a variable
- * of this type for every XADC/ADC device in the system. A pointer to
- * a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XAdcPs_Config Config; /**< XAdcPs_Config of current device */
- u32 IsReady; /**< Device is initialized and ready */
-
-} XAdcPs;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-*
-* This macro checks if the XADC device is in Event Sampling mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return
-* - TRUE if the device is in Event Sampling Mode.
-* - FALSE if the device is in Continuous Sampling Mode.
-*
-* @note C-Style signature:
-* int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);
-*
-*****************************************************************************/
-#define XAdcPs_IsEventSamplingModeSet(InstancePtr) \
- (((XAdcPs_ReadInternalReg(InstancePtr, \
- XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ? \
- TRUE : FALSE))
-
-
-/****************************************************************************/
-/**
-*
-* This macro checks if the XADC device is in External Mux mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return
-* - TRUE if the device is in External Mux Mode.
-* - FALSE if the device is NOT in External Mux Mode.
-*
-* @note C-Style signature:
-* int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);
-*
-*****************************************************************************/
-#define XAdcPs_IsExternalMuxModeSet(InstancePtr) \
- (((XAdcPs_ReadInternalReg(InstancePtr, \
- XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ? \
- TRUE : FALSE))
-
-/****************************************************************************/
-/**
-*
-* This macro converts XADC Raw Data to Temperature(centigrades).
-*
-* @param AdcData is the Raw ADC Data from XADC.
-*
-* @return The Temperature in centigrades.
-*
-* @note C-Style signature:
-* float XAdcPs_RawToTemperature(u32 AdcData);
-*
-*****************************************************************************/
-#define XAdcPs_RawToTemperature(AdcData) \
- ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
-
-/****************************************************************************/
-/**
-*
-* This macro converts XADC/ADC Raw Data to Voltage(volts).
-*
-* @param AdcData is the XADC/ADC Raw Data.
-*
-* @return The Voltage in volts.
-*
-* @note C-Style signature:
-* float XAdcPs_RawToVoltage(u32 AdcData);
-*
-*****************************************************************************/
-#define XAdcPs_RawToVoltage(AdcData) \
- ((((float)(AdcData))* (3.0f))/65536.0f)
-
-/****************************************************************************/
-/**
-*
-* This macro converts Temperature in centigrades to XADC/ADC Raw Data.
-*
-* @param Temperature is the Temperature in centigrades to be
-* converted to XADC/ADC Raw Data.
-*
-* @return The XADC/ADC Raw Data.
-*
-* @note C-Style signature:
-* int XAdcPs_TemperatureToRaw(float Temperature);
-*
-*****************************************************************************/
-#define XAdcPs_TemperatureToRaw(Temperature) \
- ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
-
-/****************************************************************************/
-/**
-*
-* This macro converts Voltage in Volts to XADC/ADC Raw Data.
-*
-* @param Voltage is the Voltage in volts to be converted to
-* XADC/ADC Raw Data.
-*
-* @return The XADC/ADC Raw Data.
-*
-* @note C-Style signature:
-* int XAdcPs_VoltageToRaw(float Voltage);
-*
-*****************************************************************************/
-#define XAdcPs_VoltageToRaw(Voltage) \
- ((int)((Voltage)*65536.0f/3.0f))
-
-
-/****************************************************************************/
-/**
-*
-* This macro is used for writing to the XADC Registers using the
-* command FIFO.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Data is the value to be written to XADC register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);
-*
-*****************************************************************************/
-#define XAdcPs_WriteFifo(InstancePtr, Data) \
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XADCPS_CMDFIFO_OFFSET, Data);
-
-
-/****************************************************************************/
-/**
-*
-* This macro is used for reading from the XADC Registers using the
-* data FIFO.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return Data read from the FIFO
-*
-* @note C-Style signature:
-* u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);
-*
-*****************************************************************************/
-#define XAdcPs_ReadFifo(InstancePtr) \
- XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XADCPS_RDFIFO_OFFSET);
-
-
-/************************** Function Prototypes *****************************/
-
-
-
-/**
- * Functions in xadcps_sinit.c
- */
-XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
-
-/**
- * Functions in xadcps.c
- */
-int XAdcPs_CfgInitialize(XAdcPs *InstancePtr,
- XAdcPs_Config *ConfigPtr,
- u32 EffectiveAddr);
-
-void XAdcPs_SetConfigRegister(XAdcPs *InstancePtr, u32 Data);
-u32 XAdcPs_GetConfigRegister(XAdcPs *InstancePtr);
-
-u32 XAdcPs_GetMiscStatus(XAdcPs *InstancePtr);
-
-void XAdcPs_SetMiscCtrlRegister(XAdcPs *InstancePtr, u32 Data);
-u32 XAdcPs_GetMiscCtrlRegister(XAdcPs *InstancePtr);
-
-void XAdcPs_Reset(XAdcPs *InstancePtr);
-
-u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel);
-
-u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType);
-
-u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType);
-
-void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average);
-u8 XAdcPs_GetAvg(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
- u8 Channel,
- int IncreaseAcqCycles,
- int IsEventMode,
- int IsDifferentialMode);
-
-
-void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask);
-u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr);
-
-void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration);
-u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr);
-
-void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode);
-u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr);
-
-void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor);
-u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask);
-u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask);
-u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask);
-u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask);
-u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr);
-
-void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value);
-u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg);
-
-void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr);
-void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr);
-
-void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode);
-
-int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr);
-
-void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel);
-
-void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode);
-
-u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr);
-
-/**
- * Functions in xadcps_selftest.c
- */
-int XAdcPs_SelfTest(XAdcPs *InstancePtr);
-
-/**
- * Functions in xadcps_intr.c
- */
-void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask);
-void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask);
-u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr);
-
-u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr);
-void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* End of protection macro. */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/59/502557545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/59/502557545243001d18b399c1eb9b3628
deleted file mode 100644
index a3d5ae4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/59/502557545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,399 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xqspips_hw.h
-* @addtogroup qspips_v3_9
-* @{
-*
-* This header file contains the identifiers and basic HW access driver
-* functions (or macros) that can be used to access the device. Other driver
-* functions are defined in xqspips.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00 sdm 11/25/10 First release
-* 2.00a ka 07/25/12 Added a few register defines for CR 670297
-* and removed some defines of reserved fields for
-* CR 671468
-* Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
-* bit in Configuration register.
-* 2.01a sg 02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
-* which need write to clear. Removed Read zeros mask from
-* LQSPI Config register.
-* 2.03a hk 08/22/13 Added prototypes of API's for QSPI reset and
-* linear mode initialization for boot. Added related
-* constant definitions.
-* 3.1 hk 08/13/14 Changed definition of CR reset value masks to set/reset
-* required bits leaving reserved bits untouched. CR# 796813.
-* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
-* controller does not update FIFO status flags as expected
-* when thresholds are used.
-* 3.6 akm 03/28/19 Fixed memory leak issue while reading from qspi.(CR#1016357)
-*
-*
-*
-******************************************************************************/
-#ifndef XQSPIPS_HW_H /* prevent circular inclusions */
-#define XQSPIPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets from the base address of an QSPI device.
- * @{
- */
-#define XQSPIPS_CR_OFFSET 0x00 /**< Configuration Register */
-#define XQSPIPS_SR_OFFSET 0x04 /**< Interrupt Status */
-#define XQSPIPS_IER_OFFSET 0x08 /**< Interrupt Enable */
-#define XQSPIPS_IDR_OFFSET 0x0c /**< Interrupt Disable */
-#define XQSPIPS_IMR_OFFSET 0x10 /**< Interrupt Enabled Mask */
-#define XQSPIPS_ER_OFFSET 0x14 /**< Enable/Disable Register */
-#define XQSPIPS_DR_OFFSET 0x18 /**< Delay Register */
-#define XQSPIPS_TXD_00_OFFSET 0x1C /**< Transmit 4-byte inst/data */
-#define XQSPIPS_RXD_OFFSET 0x20 /**< Data Receive Register */
-#define XQSPIPS_SICR_OFFSET 0x24 /**< Slave Idle Count */
-#define XQSPIPS_TXWR_OFFSET 0x28 /**< Transmit FIFO Watermark */
-#define XQSPIPS_RXWR_OFFSET 0x2C /**< Receive FIFO Watermark */
-#define XQSPIPS_GPIO_OFFSET 0x30 /**< GPIO Register */
-#define XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38 /**< Loopback Delay Adjust Reg */
-#define XQSPIPS_TXD_01_OFFSET 0x80 /**< Transmit 1-byte inst */
-#define XQSPIPS_TXD_10_OFFSET 0x84 /**< Transmit 2-byte inst */
-#define XQSPIPS_TXD_11_OFFSET 0x88 /**< Transmit 3-byte inst */
-#define XQSPIPS_LQSPI_CR_OFFSET 0xA0 /**< Linear QSPI config register */
-#define XQSPIPS_LQSPI_SR_OFFSET 0xA4 /**< Linear QSPI status register */
-#define XQSPIPS_MOD_ID_OFFSET 0xFC /**< Module ID register */
-
-/* @} */
-
-/** @name Configuration Register
- *
- * This register contains various control bits that
- * affect the operation of the QSPI device. Read/Write.
- * @{
- */
-
-#define XQSPIPS_CR_IFMODE_MASK 0x80000000 /**< Flash mem interface mode */
-#define XQSPIPS_CR_ENDIAN_MASK 0x04000000 /**< Tx/Rx FIFO endianness */
-#define XQSPIPS_CR_MANSTRT_MASK 0x00010000 /**< Manual Transmission Start */
-#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start
- Enable */
-#define XQSPIPS_CR_SSFORCE_MASK 0x00004000 /**< Force Slave Select */
-#define XQSPIPS_CR_SSCTRL_MASK 0x00000400 /**< Slave Select Decode */
-#define XQSPIPS_CR_SSCTRL_SHIFT 10 /**< Slave Select Decode shift */
-#define XQSPIPS_CR_DATA_SZ_MASK 0x000000C0 /**< Size of word to be
- transferred */
-#define XQSPIPS_CR_PRESC_MASK 0x00000038 /**< Prescaler Setting */
-#define XQSPIPS_CR_PRESC_SHIFT 3 /**< Prescaler shift */
-#define XQSPIPS_CR_PRESC_MAXIMUM 0x07 /**< Prescaler maximum value */
-
-#define XQSPIPS_CR_CPHA_MASK 0x00000004 /**< Phase Configuration */
-#define XQSPIPS_CR_CPOL_MASK 0x00000002 /**< Polarity Configuration */
-
-#define XQSPIPS_CR_MSTREN_MASK 0x00000001 /**< Master Mode Enable */
-
-#define XQSPIPS_CR_HOLD_B_MASK 0x00080000 /**< HOLD_B Pin Drive Enable */
-
-#define XQSPIPS_CR_REF_CLK_MASK 0x00000100 /**< Ref clk bit - should be 0 */
-
-/* Deselect the Slave select line and set the transfer size to 32 at reset */
-#define XQSPIPS_CR_RESET_MASK_SET XQSPIPS_CR_IFMODE_MASK | \
- XQSPIPS_CR_SSCTRL_MASK | \
- XQSPIPS_CR_DATA_SZ_MASK | \
- XQSPIPS_CR_MSTREN_MASK | \
- XQSPIPS_CR_SSFORCE_MASK | \
- XQSPIPS_CR_HOLD_B_MASK
-#define XQSPIPS_CR_RESET_MASK_CLR XQSPIPS_CR_CPOL_MASK | \
- XQSPIPS_CR_CPHA_MASK | \
- XQSPIPS_CR_PRESC_MASK | \
- XQSPIPS_CR_MANSTRTEN_MASK | \
- XQSPIPS_CR_MANSTRT_MASK | \
- XQSPIPS_CR_ENDIAN_MASK | \
- XQSPIPS_CR_REF_CLK_MASK
-/* @} */
-
-
-/** @name QSPI Interrupt Registers
- *
- * QSPI Status Register
- *
- * This register holds the interrupt status flags for an QSPI device. Some
- * of the flags are level triggered, which means that they are set as long
- * as the interrupt condition exists. Other flags are edge triggered,
- * which means they are set once the interrupt condition occurs and remain
- * set until they are cleared by software. The interrupts are cleared by
- * writing a '1' to the interrupt bit position in the Status Register.
- * Read/Write.
- *
- * QSPI Interrupt Enable Register
- *
- * This register is used to enable chosen interrupts for an QSPI device.
- * Writing a '1' to a bit in this register sets the corresponding bit in the
- * QSPI Interrupt Mask register. Write only.
- *
- * QSPI Interrupt Disable Register
- *
- * This register is used to disable chosen interrupts for an QSPI device.
- * Writing a '1' to a bit in this register clears the corresponding bit in the
- * QSPI Interrupt Mask register. Write only.
- *
- * QSPI Interrupt Mask Register
- *
- * This register shows the enabled/disabled interrupts of an QSPI device.
- * Read only.
- *
- * All four registers have the same bit definitions. They are only defined once
- * for each of the Interrupt Enable Register, Interrupt Disable Register,
- * Interrupt Mask Register, and Channel Interrupt Status Register
- * @{
- */
-
-#define XQSPIPS_IXR_TXUF_MASK 0x00000040 /**< QSPI Tx FIFO Underflow */
-#define XQSPIPS_IXR_RXFULL_MASK 0x00000020 /**< QSPI Rx FIFO Full */
-#define XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010 /**< QSPI Rx FIFO Not Empty */
-#define XQSPIPS_IXR_TXFULL_MASK 0x00000008 /**< QSPI Tx FIFO Full */
-#define XQSPIPS_IXR_TXOW_MASK 0x00000004 /**< QSPI Tx FIFO Overwater */
-#define XQSPIPS_IXR_RXOVR_MASK 0x00000001 /**< QSPI Rx FIFO Overrun */
-#define XQSPIPS_IXR_DFLT_MASK 0x00000025 /**< QSPI default interrupts
- mask */
-#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041 /**< Interrupts which
- need write to clear */
-#define XQSPIPS_ISR_RESET_STATE 0x00000004 /**< Default to tx/rx empty */
-#define XQSPIPS_IXR_DISABLE_ALL 0x0000007D /**< Disable all interrupts */
-/* @} */
-
-
-/** @name Enable Register
- *
- * This register is used to enable or disable an QSPI device.
- * Read/Write
- * @{
- */
-#define XQSPIPS_ER_ENABLE_MASK 0x00000001 /**< QSPI Enable Bit Mask */
-/* @} */
-
-
-/** @name Delay Register
- *
- * This register is used to program timing delays in
- * slave mode. Read/Write
- * @{
- */
-#define XQSPIPS_DR_NSS_MASK 0xFF000000 /**< Delay to de-assert slave select
- between two words mask */
-#define XQSPIPS_DR_NSS_SHIFT 24 /**< Delay to de-assert slave select
- between two words shift */
-#define XQSPIPS_DR_BTWN_MASK 0x00FF0000 /**< Delay Between Transfers
- mask */
-#define XQSPIPS_DR_BTWN_SHIFT 16 /**< Delay Between Transfers shift */
-#define XQSPIPS_DR_AFTER_MASK 0x0000FF00 /**< Delay After Transfers mask */
-#define XQSPIPS_DR_AFTER_SHIFT 8 /**< Delay After Transfers shift */
-#define XQSPIPS_DR_INIT_MASK 0x000000FF /**< Delay Initially mask */
-/* @} */
-
-/** @name Slave Idle Count Registers
- *
- * This register defines the number of pclk cycles the slave waits for a the
- * QSPI clock to become stable in quiescent state before it can detect the start
- * of the next transfer in CPHA = 1 mode.
- * Read/Write
- *
- * @{
- */
-#define XQSPIPS_SICR_MASK 0x000000FF /**< Slave Idle Count Mask */
-/* @} */
-
-
-/** @name Transmit FIFO Watermark Register
- *
- * This register defines the watermark setting for the Transmit FIFO.
- *
- * @{
- */
-#define XQSPIPS_TXWR_MASK 0x0000003F /**< Transmit Watermark Mask */
-#define XQSPIPS_TXWR_RESET_VALUE 0x00000001 /**< Transmit Watermark
- * register reset value */
-
-/* @} */
-
-/** @name Receive FIFO Watermark Register
- *
- * This register defines the watermark setting for the Receive FIFO.
- *
- * @{
- */
-#define XQSPIPS_RXWR_MASK 0x0000003F /**< Receive Watermark Mask */
-#define XQSPIPS_RXWR_RESET_VALUE 0x00000001 /**< Receive Watermark
- * register reset value */
-
-/* @} */
-
-/** @name FIFO Depth
- *
- * This macro provides the depth of transmit FIFO and receive FIFO.
- *
- * @{
- */
-#define XQSPIPS_FIFO_DEPTH 63 /**< FIFO depth (words) */
-/* @} */
-
-
-/** @name Linear QSPI Configuration Register
- *
- * This register contains various control bits that
- * affect the operation of the Linear QSPI controller. Read/Write.
- *
- * @{
- */
-#define XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */
-#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */
-#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Separate memory bus */
-#define XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */
-#define XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */
-#define XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */
-#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O
- or quad I/O */
-#define XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700 /**< Number of dummy bytes
- between addr and return
- read data */
-#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */
-#define XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B /**< Default CR value */
-/* @} */
-
-/** @name Linear QSPI Status Register
- *
- * This register contains various status bits of the Linear QSPI controller.
- * Read/Write.
- *
- * @{
- */
-#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004 /**< AXI Data FSM Error
- received */
-#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002 /**< AXI write command
- received */
-/* @} */
-
-
-/** @name Loopback Delay Adjust Register
- *
- * This register contains various bit masks of Loopback Delay Adjust Register.
- *
- * @{
- */
-
-#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */
-
-/* @} */
-
-
-/** @name SLCR Register
- *
- * Register offsets from SLCR base address.
- *
- * @{
- */
-
-#define SLCR_LOCK 0x00000004 /**< SLCR Write Protection Lock */
-#define SLCR_UNLOCK 0x00000008 /**< SLCR Write Protection Unlock */
-#define LQSPI_RST_CTRL 0x00000230 /**< Quad SPI Software Reset Control */
-#define SLCR_LOCKSTA 0x0000000C /**< SLCR Write Protection status */
-
-/* @} */
-
-
-/** @name SLCR Register
- *
- * Bit Masks of above SLCR Registers .
- *
- * @{
- */
-
-#ifndef XPAR_XSLCR_0_BASEADDR
-#define XPAR_XSLCR_0_BASEADDR 0xF8000000
-#endif
-#define SLCR_LOCK_MASK 0x767B /**< Write Protection Lock mask*/
-#define SLCR_UNLOCK_MASK 0xDF0D /**< SLCR Write Protection Unlock */
-#define LQSPI_RST_CTRL_MASK 0x3 /**< Quad SPI Software Reset Control */
-
-/* @} */
-
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XQspiPs_In32 Xil_In32
-#define XQspiPs_Out32 Xil_Out32
-#define XQSPIPS_DUMMY_TX_DATA 0xFFFFFFFF
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-#define XQspiPs_ReadReg(BaseAddress, RegOffset) \
- XQspiPs_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u32 RegisterValue)
-*
-******************************************************************************/
-#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Functions implemented in xqspips_hw.c
- */
-void XQspiPs_ResetHw(u32 BaseAddress);
-void XQspiPs_LinearInit(u32 BaseAddress);
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/59/b068c9575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/59/b068c9575243001d18b399c1eb9b3628
deleted file mode 100644
index 27dffb9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/59/b068c9575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1961 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xdmaps.c
-* @addtogroup dmaps_v2_8
-* @{
-*
-* This file contains the implementation of the interface functions for XDmaPs
-* driver. Refer to the header file xdmaps.h for more detailed information.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00 hbm 08/19/2010 First Release
-* 1.00 nm 05/25/2011 Updated for minor doxygen corrections
-* 1.02a sg 05/16/2012 Made changes for doxygen and moved some function
-* header from the xdmaps.h file to xdmaps.c file
-* Other cleanup for coding guidelines and CR 657109
-* and CR 657898
-* 1.03a sg 07/16/2012 changed inline to __inline for CR665681
-* 1.04a nm 10/22/2012 Fixed CR# 681671.
-* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled
-* with -Wall and -Wextra option in bsp.
-* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
-* function description.
-* Fixed CR# 704396. Removed unused variables
-* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
-* function.
-* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc.
-* Removed the PDBG prints. By default they were always
-* defined out and never used. The PDBG is non-standard for
-* Xilinx drivers and no other driver does something similar.
-* Since there is no easy way to fix compilation issues with
-* the IARCC compiler around PDBG, it is better to remove it.
-* Users can always use xil_printfs if they want to debug.
-* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
-* 2.2 mus 12/08/16 Remove definition of INLINE macro to avoid re-definition,
-* since it is being defined in xil_io.h
-* 2.3 kpc 14/10/16 Fixed the compiler error when optimization O0 is used.
-* 2.5 hk 08/16/19 Add a memory barrier before DMASEV as per specification.
-* 2.6 hk 02/14/20 Correct boundary check for Channel.
-*
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include
-
-#include "xstatus.h"
-#include "xdmaps.h"
-#include "xil_io.h"
-#include "xil_cache.h"
-
-#include "xil_printf.h"
-
-
-/************************** Constant Definitions ****************************/
-
-/* The following constant defines the amount of error that is allowed for
- * a specified baud rate. This error is the difference between the actual
- * baud rate that will be generated using the specified clock and the
- * desired baud rate.
- */
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Function Prototypes *****************************/
-static int XDmaPs_Exec_DMAKILL(u32 BaseAddr,
- unsigned int Channel,
- unsigned int Thread);
-
-static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf);
-
-static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg);
-
-static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel);
-static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool);
-static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
- unsigned CacheLength);
-
-static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length);
-
-
-
-/************************** Variable Definitions ****************************/
-
-/****************************************************************************/
-/**
-*
-* Initializes a specific XDmaPs instance such that it is ready to be used.
-* The data format of the device is setup for 8 data bits, 1 stop bit, and no
-* parity by default. The baud rate is set to a default value specified by
-* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The
-* receive FIFO threshold is set for 8 bytes. The default operating mode of the
-* driver is polled mode.
-*
-* @param InstPtr is a pointer to the XDmaPs instance.
-* @param Config is a reference to a structure containing information
-* about a specific XDmaPs driver.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. The caller is responsible for keeping the
-* address mapping from EffectiveAddr to the device physical base
-* address unchanged once this function is invoked. Unexpected
-* errors may occur if the address mapping changes after this
-* function is called. If address translation is not used, pass in
-* the physical address instead.
-*
-* @return
-*
-* - XST_SUCCESS on initialization completion
-*
-* @note None.
-*
-*****************************************************************************/
-int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
- XDmaPs_Config *Config,
- u32 EffectiveAddr)
-{
- int Status = XST_SUCCESS;
- unsigned int CacheLength = 0;
- u32 CfgReg;
- unsigned Channel;
- XDmaPs_ChannelData *ChanData;
-
- /*
- * Assert validates the input arguments
- */
- Xil_AssertNonvoid(InstPtr != NULL);
- Xil_AssertNonvoid(Config != NULL);
-
- /*
- * Setup the driver instance using passed in parameters
- */
- InstPtr->Config.DeviceId = Config->DeviceId;
- InstPtr->Config.BaseAddress = EffectiveAddr;
-
- CfgReg = XDmaPs_ReadReg(EffectiveAddr, XDMAPS_CR1_OFFSET);
- CacheLength = CfgReg & XDMAPS_CR1_I_CACHE_LEN_MASK;
- if (CacheLength < 2 || CacheLength > 5)
- CacheLength = 0;
- else
- CacheLength = 1 << CacheLength;
-
- InstPtr->CacheLength = CacheLength;
-
- memset(InstPtr->Chans, 0,
- sizeof(XDmaPs_ChannelData[XDMAPS_CHANNELS_PER_DEV]));
-
- for (Channel = 0; Channel < XDMAPS_CHANNELS_PER_DEV; Channel++) {
- ChanData = InstPtr->Chans + Channel;
- ChanData->ChanId = Channel;
- ChanData->DevId = Config->DeviceId;
- }
-
- InstPtr->IsReady = 1;
-
- return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* Reset the DMA Manager.
-*
-* @param InstPtr is the DMA instance.
-*
-* @return 0 on success, -1 on time out
-*
-* @note None.
-*
-*****************************************************************************/
-int XDmaPs_ResetManager(XDmaPs *InstPtr)
-{
- int Status;
- Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress,
- 0, 0);
-
- return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* Reset the specified DMA Channel.
-*
-* @param InstPtr is the DMA instance.
-* @param Channel is the channel to be reset.
-*
-* @return 0 on success, -1 on time out
-*
-* @note None.
-*
-*****************************************************************************/
-int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel)
-{
- int Status;
- Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress,
- Channel, 1);
-
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* Driver fault interrupt service routine
-* This is the one that connects the GIC
-*
-* @param InstPtr is the DMA instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XDmaPs_FaultISR(XDmaPs *InstPtr)
-{
-
- void *DmaProgBuf;
- u32 Fsm; /* Fault status DMA manager register value */
- u32 Fsc; /* Fault status DMA channel register value */
- u32 FaultType; /* Fault type DMA manager register value */
-
- u32 BaseAddr = InstPtr->Config.BaseAddress;
-
- u32 Pc; /* DMA Pc or channel Pc */
- XDmaPs_ChannelData *ChanData;
-
- unsigned Chan;
- unsigned DevId;
-
- XDmaPs_Cmd *DmaCmd;
-
- Fsm = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSM_OFFSET) & 0x01;
- Fsc = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSC_OFFSET) & 0xFF;
-
-
- DevId = InstPtr->Config.DeviceId;
-
- if (Fsm) {
- /*
- * if DMA manager is fault
- */
- FaultType = XDmaPs_ReadReg(BaseAddr, XDMAPS_FTM_OFFSET);
- Pc = XDmaPs_ReadReg(BaseAddr, XDMAPS_DPC_OFFSET);
-
- xil_printf("PL330 device %d fault with type: %x at Pc %x\n",
- DevId,
- FaultType, Pc);
-
- /* kill the DMA manager thread */
- /* Should we disable interrupt?*/
- XDmaPs_Exec_DMAKILL(BaseAddr, 0, 0);
- }
-
- /*
- * check which channel faults and kill the channel thread
- */
- for (Chan = 0;
- Chan < XDMAPS_CHANNELS_PER_DEV;
- Chan++) {
- if (Fsc & (0x01 << Chan)) {
- FaultType =
- XDmaPs_ReadReg(BaseAddr,
- XDmaPs_FTCn_OFFSET(Chan));
- Pc = XDmaPs_ReadReg(BaseAddr,
- XDmaPs_CPCn_OFFSET(Chan));
-
- /* kill the channel thread */
- /* Should we disable interrupt? */
- XDmaPs_Exec_DMAKILL(BaseAddr, Chan, 1);
-
- /*
- * get the fault type and fault Pc and invoke the
- * fault callback.
- */
- ChanData = InstPtr->Chans + Chan;
-
- DmaCmd = ChanData->DmaCmdToHw;
-
- /* Should we check DmaCmd is not null */
- DmaCmd->DmaStatus = -1;
- DmaCmd->ChanFaultType = FaultType;
- DmaCmd->ChanFaultPCAddr = Pc;
- ChanData->DmaCmdFromHw = DmaCmd;
- ChanData->DmaCmdToHw = NULL;
-
- if (!ChanData->HoldDmaProg) {
- DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg;
- if (DmaProgBuf)
- XDmaPs_BufPool_Free(ChanData->ProgBufPool,
- DmaProgBuf);
- DmaCmd->GeneratedDmaProg = NULL;
- }
-
- if (InstPtr->FaultHandler)
- InstPtr->FaultHandler(Chan,
- DmaCmd,
- InstPtr->FaultRef);
-
- }
- }
-
-}
-
-/*****************************************************************************/
-/**
-*
-* Set the done handler for a channel.
-*
-* @param InstPtr is the DMA instance.
-* @param Channel is the channel number.
-* @param DoneHandler is the done interrupt handler.
-* @param CallbackRef is the callback reference data.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
- unsigned Channel,
- XDmaPsDoneHandler DoneHandler,
- void *CallbackRef)
-{
- XDmaPs_ChannelData *ChanData;
-
- Xil_AssertNonvoid(InstPtr != NULL);
-
- if (Channel >= XDMAPS_CHANNELS_PER_DEV)
- return XST_FAILURE;
-
-
- ChanData = InstPtr->Chans + Channel;
-
- ChanData->DoneHandler = DoneHandler;
- ChanData->DoneRef = CallbackRef;
-
- return 0;
-}
-
-/*****************************************************************************/
-/**
-*
-* Set the fault handler for a channel.
-*
-* @param InstPtr is the DMA instance.
-* @param FaultHandler is the fault interrupt handler.
-* @param CallbackRef is the callback reference data.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
- XDmaPsFaultHandler FaultHandler,
- void *CallbackRef)
-{
- Xil_AssertNonvoid(InstPtr != NULL);
-
- InstPtr->FaultHandler = FaultHandler;
- InstPtr->FaultRef = CallbackRef;
-
- return XST_SUCCESS;
-}
-
-
-
-/****************************************************************************/
-/**
-* Construction function for DMAEND instruction. This function fills the program
-* buffer with the constructed instruction.
-*
-* @param DmaProg the DMA program buffer, it's the starting address for
-* the instruction being constructed
-*
-* @return The number of bytes for this instruction which is 1.
-*
-* @note None.
-*
-*****************************************************************************/
-static INLINE int XDmaPs_Instr_DMAEND(char *DmaProg)
-{
- /*
- * DMAEND encoding:
- * 7 6 5 4 3 2 1 0
- * 0 0 0 0 0 0 0 0
- */
- *DmaProg = 0x0;
-
- return 1;
-}
-
-static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src)
-{
- *Dst = *Src;
- *(Dst + 1) = *(Src + 1);
- *(Dst + 2) = *(Src + 2);
- *(Dst + 3) = *(Src + 3);
-}
-
-/****************************************************************************/
-/**
-*
-* Construction function for DMAGO instruction. This function fills the program
-* buffer with the constructed instruction.
-*
-* @param DmaProg is the DMA program buffer, it's the starting address
-* for the instruction being constructed
-* @param Cn is the Channel number, 0 - 7
-* @param Imm is 32-bit immediate number written to the Channel Program
-* Counter.
-* @param Ns is Non-secure flag. If Ns is 1, the DMA channel operates in
-* the Non-secure state. If Ns is 0, the execution depends on the
-* security state of the DMA manager:
-* DMA manager is in the Secure state, DMA channel operates in the
-* Secure state.
-* DMA manager is in the Non-secure state, DMAC aborts.
-*
-* @return The number of bytes for this instruction which is 6.
-*
-* @note None
-*
-*****************************************************************************/
-static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
- u32 Imm, unsigned int Ns)
-{
- /*
- * DMAGO encoding:
- * 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
- * 0 0 0 0 0 |cn[2:0]| 1 0 1 0 0 0 ns 0
- *
- * 47 ... 16
- * imm[32:0]
- */
- *DmaProg = 0xA0 | ((Ns << 1) & 0x02);
-
- *(DmaProg + 1) = (u8)(Cn & 0x07);
-
- // *((u32 *)(DmaProg + 2)) = Imm;
- XDmaPs_Memcpy4(DmaProg + 2, (char *)&Imm);
-
- /* success */
- return 6;
-}
-
-/****************************************************************************/
-/**
-*
-* Construction function for DMALD instruction. This function fills the program
-* buffer with the constructed instruction.
-*
-* @param DmaProg the DMA program buffer, it's the starting address for the
-* instruction being constructed
-*
-* @return The number of bytes for this instruction which is 1.
-*
-* @note None.
-*
-*****************************************************************************/
-static INLINE int XDmaPs_Instr_DMALD(char *DmaProg)
-{
- /*
- * DMALD encoding
- * 7 6 5 4 3 2 1 0
- * 0 0 0 0 0 1 bs x
- *
- * Note: this driver doesn't support conditional load or store,
- * so the bs bit is 0 and x bit is 0.
- */
- *DmaProg = 0x04;
- return 1;
-}
-
-/****************************************************************************/
-/**
-*
-* Construction function for DMALP instruction. This function fills the program
-* buffer with the constructed instruction.
-*
-* @param DmaProg is the DMA program buffer, it's the starting address
-* for the instruction being constructed
-* @param Lc is the Loop counter register, can either be 0 or 1.
-* @param LoopIterations: the number of interations, LoopInterations - 1
-* will be encoded in the DMALP instruction.
-*
-* @return The number of bytes for this instruction which is 2.
-*
-* @note None.
-*
-*****************************************************************************/
-static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
- unsigned LoopIterations)
-{
- /*
- * DMALP encoding
- * 15 ... 8 7 6 5 4 3 2 1 0
- * | iter[7:0] |0 0 1 0 0 0 lc 0
- */
- *DmaProg = (u8)(0x20 | ((Lc & 1) << 1));
- *(DmaProg + 1) = (u8)(LoopIterations - 1);
- return 2;
-}
-
-/****************************************************************************/
-/**
-*
-* Construction function for DMALPEND instruction. This function fills the
-* program buffer with the constructed instruction.
-*
-* @param DmaProg is the DMA program buffer, it's the starting address
-* for the instruction being constructed
-* @param BodyStart is the starting address of the loop body. It is used
-* to calculate the bytes of backward jump.
-* @param Lc is the Loop counter register, can either be 0 or 1.
-*
-* @return The number of bytes for this instruction which is 2.
-*
-* @note None.
-*
-*****************************************************************************/
-static INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc)
-{
- /*
- * DMALPEND encoding
- * 15 ... 8 7 6 5 4 3 2 1 0
- * | backward_jump[7:0] |0 0 1 nf 1 lc bs x
- *
- * lc: loop counter
- * nf is for loop forever. The driver does not support loop forever,
- * so nf is 1.
- * The driver does not support conditional LPEND, so bs is 0, x is 0.
- */
- *DmaProg = 0x38 | ((Lc & 1) << 2);
- *(DmaProg + 1) = (u8)(DmaProg - BodyStart);
-
- return 2;
-}
-
-/*
- * Register number for the DMAMOV instruction
- */
-#define XDMAPS_MOV_SAR 0x0
-#define XDMAPS_MOV_CCR 0x1
-#define XDMAPS_MOV_DAR 0x2
-
-/****************************************************************************/
-/**
-*
-* Construction function for DMAMOV instruction. This function fills the
-* program buffer with the constructed instruction.
-*
-* @param DmaProg is the DMA program buffer, it's the starting address
-* for the instruction being constructed
-* @param Rd is the register id, 0 for SAR, 1 for CCR, and 2 for DAR
-* @param Imm is the 32-bit immediate number
-*
-* @return The number of bytes for this instruction which is 6.
-*
-* @note None.
-*
-*****************************************************************************/
-static INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm)
-{
- /*
- * DMAMOV encoding
- * 15 4 3 2 1 10 ... 8 7 6 5 4 3 2 1 0
- * 0 0 0 0 0 |rd[2:0]|1 0 1 1 1 1 0 0
- *
- * 47 ... 16
- * imm[32:0]
- *
- * rd: b000 for SAR, b001 CCR, b010 DAR
- */
- *DmaProg = 0xBC;
- *(DmaProg + 1) = Rd & 0x7;
- // *((u32 *)(DmaProg + 2)) = Imm;
- XDmaPs_Memcpy4(DmaProg + 2, (char *)&Imm);
-
- return 6;
-}
-
-/****************************************************************************/
-/**
-*
-* Construction function for DMANOP instruction. This function fills the
-* program buffer with the constructed instruction.
-*
-* @param DmaProg is the DMA program buffer, it's the starting address
-* for the instruction being constructed
-* @return The number of bytes for this instruction which is 1.
-*
-* @note None.
-*
-*****************************************************************************/
-static INLINE int XDmaPs_Instr_DMANOP(char *DmaProg)
-{
- /*
- * DMANOP encoding
- * 7 6 5 4 3 2 1 0
- * 0 0 0 1 1 0 0 0
- */
- *DmaProg = 0x18;
- return 1;
-}
-
-/****************************************************************************/
-/**
-*
-* Construction function for DMARMB instruction. This function fills the
-* program buffer with the constructed instruction.
-*
-* @param DmaProg is the DMA program buffer, it's the starting address
-* for the instruction being constructed
-*
-* @return The number of bytes for this instruction which is 1.
-*
-* @note None.
-*
-*****************************************************************************/
-int XDmaPs_Instr_DMARMB(char *DmaProg)
-{
- /*
- * DMARMB encoding
- * 7 6 5 4 3 2 1 0
- * 0 0 0 1 0 0 1 0
- */
- *DmaProg = 0x12;
- return 1;
-}
-
-/****************************************************************************/
-/**
-*
-* Construction function for DMASEV instruction. This function fills the
-* program buffer with the constructed instruction.
-*
-* @param DmaProg is the DMA program buffer, it's the starting address
-* for the instruction being constructed
-* @param EventNumber is the Event number to signal.
-*
-* @return The number of bytes for this instruction which is 2.
-*
-* @note None.
-*
-*****************************************************************************/
-static INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber)
-{
- /*
- * DMASEV encoding
- * 15 4 3 2 1 10 9 8 7 6 5 4 3 2 1 0
- * |event[4:0]| 0 0 0 0 0 1 1 0 1 0 0
- */
- *DmaProg = 0x34;
- *(DmaProg + 1) = (u8)(EventNumber << 3);
-
- return 2;
-}
-
-
-/****************************************************************************/
-/**
-*
-* Construction function for DMAST instruction. This function fills the
-* program buffer with the constructed instruction.
-*
-* @param DmaProg is the DMA program buffer, it's the starting address
-* for the instruction being constructed
-*
-* @return The number of bytes for this instruction which is 1.
-*
-* @note None.
-*
-*****************************************************************************/
-static INLINE int XDmaPs_Instr_DMAST(char *DmaProg)
-{
- /*
- * DMAST encoding
- * 7 6 5 4 3 2 1 0
- * 0 0 0 0 1 0 bs x
- *
- * Note: this driver doesn't support conditional load or store,
- * so the bs bit is 0 and x bit is 0.
- */
- *DmaProg = 0x08;
- return 1;
-}
-
-
-/****************************************************************************/
-/**
-*
-* Construction function for DMAWMB instruction. This function fills the
-* program buffer with the constructed instruction.
-*
-* @param DmaProg is the DMA program buffer, it's the starting address
-* for the instruction being constructed
-*
-* @return The number of bytes for this instruction which is 1.
-*
-* @note None.
-*
-*****************************************************************************/
-int XDmaPs_Instr_DMAWMB(char *DmaProg)
-{
- /*
- * DMAWMB encoding
- * 7 6 5 4 3 2 1 0
- * 0 0 0 1 0 0 1 0
- */
- *DmaProg = 0x13;
- return 1;
-}
-
-/****************************************************************************/
-/**
-*
-* Conversion function from the endian swap size to the bit encoding of the CCR
-*
-* @param EndianSwapSize is the endian swap size, in terms of bits, it
-* could be 8, 16, 32, 64, or 128(We are using DMA assembly syntax)
-*
-* @return The endian swap size bit encoding for the CCR.
-*
-* @note None.
-*
-*****************************************************************************/
-static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize)
-{
- switch (EndianSwapSize) {
- case 0:
- case 8:
- return 0;
- case 16:
- return 1;
- case 32:
- return 2;
- case 64:
- return 3;
- case 128:
- return 4;
- default:
- return 0;
- }
-
-}
-
-/****************************************************************************/
-/**
-*
-* Conversion function from the burst size to the bit encoding of the CCR
-*
-* @param BurstSize is the burst size. It's the data width.
-* In terms of bytes, it could be 1, 2, 4, 8, 16, 32, 64, or 128.
-* It must be no larger than the bus width.
-* (We are using DMA assembly syntax.)
-*
-* @note None.
-*
-*****************************************************************************/
-static INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize)
-{
- switch (BurstSize) {
- case 1:
- return 0;
- case 2:
- return 1;
- case 4:
- return 2;
- case 8:
- return 3;
- case 16:
- return 4;
- case 32:
- return 5;
- case 64:
- return 6;
- case 128:
- return 7;
- default:
- return 0;
- }
-}
-
-
-/****************************************************************************/
-/**
-*
-* Conversion function from PL330 bus transfer descriptors to CCR value. All the
-* values passed to the functions are in terms of assembly languages, not in
-* terms of the register bit encoding.
-*
-* @param ChanCtrl is the Instance of XDmaPs_ChanCtrl.
-*
-* @return The 32-bit CCR value.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XDmaPs_ToCCRValue(XDmaPs_ChanCtrl *ChanCtrl)
-{
- /*
- * Channel Control Register encoding
- * [31:28] - endian_swap_size
- * [27:25] - dst_cache_ctrl
- * [24:22] - dst_prot_ctrl
- * [21:18] - dst_burst_len
- * [17:15] - dst_burst_size
- * [14] - dst_inc
- * [13:11] - src_cache_ctrl
- * [10:8] - src_prot_ctrl
- * [7:4] - src_burst_len
- * [3:1] - src_burst_size
- * [0] - src_inc
- */
-
- unsigned es =
- XDmaPs_ToEndianSwapSizeBits(ChanCtrl->EndianSwapSize);
-
- unsigned dst_burst_size =
- XDmaPs_ToBurstSizeBits(ChanCtrl->DstBurstSize);
- unsigned dst_burst_len = (ChanCtrl->DstBurstLen - 1) & 0x0F;
- unsigned dst_cache_ctrl = (ChanCtrl->DstCacheCtrl & 0x03)
- | ((ChanCtrl->DstCacheCtrl & 0x08) >> 1);
- unsigned dst_prot_ctrl = ChanCtrl->DstProtCtrl & 0x07;
- unsigned dst_inc_bit = ChanCtrl->DstInc & 1;
-
- unsigned src_burst_size =
- XDmaPs_ToBurstSizeBits(ChanCtrl->SrcBurstSize);
- unsigned src_burst_len = (ChanCtrl->SrcBurstLen - 1) & 0x0F;
- unsigned src_cache_ctrl = (ChanCtrl->SrcCacheCtrl & 0x03)
- | ((ChanCtrl->SrcCacheCtrl & 0x08) >> 1);
- unsigned src_prot_ctrl = ChanCtrl->SrcProtCtrl & 0x07;
- unsigned src_inc_bit = ChanCtrl->SrcInc & 1;
-
- u32 ccr_value = (es << 28)
- | (dst_cache_ctrl << 25)
- | (dst_prot_ctrl << 22)
- | (dst_burst_len << 18)
- | (dst_burst_size << 15)
- | (dst_inc_bit << 14)
- | (src_cache_ctrl << 11)
- | (src_prot_ctrl << 8)
- | (src_burst_len << 4)
- | (src_burst_size << 1)
- | (src_inc_bit);
-
- return ccr_value;
-}
-
-/****************************************************************************/
-/**
-* Construct a loop with only DMALD and DMAST as the body using loop counter 0.
-* The function also makes sure the loop body and the lpend is in the same
-* cache line.
-*
-* @param DmaProgStart is the very start address of the DMA program.
-* This is used to calculate whether the loop is in a cache line.
-* @param CacheLength is the icache line length, in terms of bytes.
-* If it's zero, the performance enhancement feature will be
-* turned off.
-* @param DmaProgLoopStart The starting address of the loop (DMALP).
-* @param LoopCount The inner loop count. Loop count - 1 will be used to
-* initialize the loop counter.
-*
-* @return The number of bytes the loop has.
-*
-* @note None.
-*
-*****************************************************************************/
-int XDmaPs_ConstructSingleLoop(char *DmaProgStart,
- int CacheLength,
- char *DmaProgLoopStart,
- int LoopCount)
-{
- int CacheStartOffset;
- int CacheEndOffset;
- int NumNops;
- char *DmaProgBuf = DmaProgLoopStart;
-
- DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 0, LoopCount);
-
- if (CacheLength > 0) {
- /*
- * the CacheLength > 0 switch is ued to turn on/off nop
- * insertion
- */
- CacheStartOffset = DmaProgBuf - DmaProgStart;
- CacheEndOffset = CacheStartOffset + 3;
-
- /*
- * check whether the body and lpend fit in one cache line
- */
- if (CacheStartOffset / CacheLength
- != CacheEndOffset / CacheLength) {
- /* insert the nops */
- NumNops = CacheLength
- - CacheStartOffset % CacheLength;
- while (NumNops--) {
- DmaProgBuf +=
- XDmaPs_Instr_DMANOP(DmaProgBuf);
- }
- }
- }
-
- DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
- DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf);
- DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
- DmaProgBuf - 2, 0);
-
- return DmaProgBuf - DmaProgLoopStart;
-}
-
-/****************************************************************************/
-/**
-* Construct a nested loop with only DMALD and DMAST in the inner loop body.
-* It uses loop counter 1 for the outer loop and loop counter 0 for the
-* inner loop.
-*
-* @param DmaProgStart is the very start address of the DMA program.
-* This is used to calculate whether the loop is in a cache line.
-* @param CacheLength is the icache line length, in terms of bytes.
-* If it's zero, the performance enhancement feature will be
-* turned off.
-* @param DmaProgLoopStart The starting address of the loop (DMALP).
-* @param LoopCountOuter The outer loop count. Loop count - 1 will be
-* used to initialize the loop counter.
-* @param LoopCountInner The inner loop count. Loop count - 1 will be
-* used to initialize the loop counter.
-*
-* @return The number byes the nested loop program has.
-*
-* @note None.
-*
-*****************************************************************************/
-int XDmaPs_ConstructNestedLoop(char *DmaProgStart,
- int CacheLength,
- char *DmaProgLoopStart,
- unsigned int LoopCountOuter,
- unsigned int LoopCountInner)
-{
- int CacheStartOffset;
- int CacheEndOffset;
- int NumNops;
- char *InnerLoopStart;
- char *DmaProgBuf = DmaProgLoopStart;
-
- DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 1, LoopCountOuter);
- InnerLoopStart = DmaProgBuf;
-
- if (CacheLength > 0) {
- /*
- * the CacheLength > 0 switch is ued to turn on/off nop
- * insertion
- */
- if (CacheLength < 8) {
- /*
- * if the cache line is too small to fit both loops
- * just align the inner loop
- */
- DmaProgBuf +=
- XDmaPs_ConstructSingleLoop(DmaProgStart,
- CacheLength,
- DmaProgBuf,
- LoopCountInner);
- /* outer loop end */
- DmaProgBuf +=
- XDmaPs_Instr_DMALPEND(DmaProgBuf,
- InnerLoopStart,
- 1);
-
- /*
- * the nested loop is constructed for
- * smaller cache line
- */
- return DmaProgBuf - DmaProgLoopStart;
- }
-
- /*
- * Now let's handle the case where a cache line can
- * fit the nested loops.
- */
- CacheStartOffset = DmaProgBuf - DmaProgStart;
- CacheEndOffset = CacheStartOffset + 7;
-
- /*
- * check whether the body and lpend fit in one cache line
- */
- if (CacheStartOffset / CacheLength
- != CacheEndOffset / CacheLength) {
- /* insert the nops */
- NumNops = CacheLength
- - CacheStartOffset % CacheLength;
- while (NumNops--) {
- DmaProgBuf +=
- XDmaPs_Instr_DMANOP(DmaProgBuf);
- }
- }
- }
-
- /* insert the inner DMALP */
- DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 0, LoopCountInner);
-
- /* DMALD and DMAST instructions */
- DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
- DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf);
-
- /* inner DMALPEND */
- DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
- DmaProgBuf - 2, 0);
- /* outer DMALPEND */
- DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf,
- InnerLoopStart, 1);
-
- /* return the number of bytes */
- return DmaProgBuf - DmaProgLoopStart;
-}
-
-/*
- * [31:28] endian_swap_size b0000
- * [27:25] dst_cache_ctrl b000
- * [24:22] dst_prot_ctrl b000
- * [21:18] dst_burst_len b0000
- * [17:15] dst_burst_size b000
- * [14] dst_inc b0
- * [27:25] src_cache_ctrl b000
- * [24:22] src_prot_ctrl b000
- * [21:18] src_burst_len b0000
- * [17:15] src_burst_size b000
- * [14] src_inc b0
- */
-#define XDMAPS_CCR_SINGLE_BYTE (0x0)
-#define XDMAPS_CCR_M2M_SINGLE_BYTE ((0x1 << 14) | 0x1)
-
-
-/****************************************************************************/
-/**
-*
-* Construct the DMA program based on the descriptions of the DMA transfer.
-* The function handles memory to memory DMA transfers.
-* It also handles unalgined head and small amount of residue tail.
-*
-* @param Channel DMA channel number
-* @param Cmd is the DMA command.
-* @param CacheLength is the icache line length, in terms of bytes.
-* If it's zero, the performance enhancement feature will be
-* turned off.
-*
-* @returns The number of bytes for the program.
-*
-* @note None.
-*
-*****************************************************************************/
-static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd,
- unsigned CacheLength)
-{
- /*
- * unpack arguments
- */
- char *DmaProgBuf = (char *)Cmd->GeneratedDmaProg;
- unsigned DevChan = Channel;
- unsigned long DmaLength = Cmd->BD.Length;
- u32 SrcAddr = Cmd->BD.SrcAddr;
-
- unsigned SrcInc = Cmd->ChanCtrl.SrcInc;
- u32 DstAddr = Cmd->BD.DstAddr;
- unsigned DstInc = Cmd->ChanCtrl.DstInc;
-
- char *DmaProgStart = DmaProgBuf;
-
- unsigned int BurstBytes;
- unsigned int LoopCount;
- unsigned int LoopCount1 = 0;
- unsigned int LoopResidue = 0;
- unsigned int TailBytes;
- unsigned int TailWords;
- int DmaProgBytes;
- u32 CCRValue;
- unsigned int Unaligned;
- unsigned int UnalignedCount;
- unsigned int MemBurstSize = 1;
- u32 MemAddr = 0;
- unsigned int Index;
- unsigned int SrcUnaligned = 0;
- unsigned int DstUnaligned = 0;
-
- XDmaPs_ChanCtrl *ChanCtrl;
- XDmaPs_ChanCtrl WordChanCtrl;
- static XDmaPs_ChanCtrl Mem2MemByteCC;
-
- Mem2MemByteCC.EndianSwapSize = 0;
- Mem2MemByteCC.DstCacheCtrl = 0;
- Mem2MemByteCC.DstProtCtrl = 0;
- Mem2MemByteCC.DstBurstLen = 1;
- Mem2MemByteCC.DstBurstSize = 1;
- Mem2MemByteCC.DstInc = 1;
- Mem2MemByteCC.SrcCacheCtrl = 0;
- Mem2MemByteCC.SrcProtCtrl = 0;
- Mem2MemByteCC.SrcBurstLen = 1;
- Mem2MemByteCC.SrcBurstSize = 1;
- Mem2MemByteCC.SrcInc = 1;
-
- ChanCtrl = &Cmd->ChanCtrl;
-
- /* insert DMAMOV for SAR and DAR */
- DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
- XDMAPS_MOV_SAR,
- SrcAddr);
- DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
- XDMAPS_MOV_DAR,
- DstAddr);
-
-
- if (ChanCtrl->SrcInc)
- SrcUnaligned = SrcAddr % ChanCtrl->SrcBurstSize;
-
- if (ChanCtrl->DstInc)
- DstUnaligned = DstAddr % ChanCtrl->DstBurstSize;
-
- if ((SrcUnaligned && DstInc) || (DstUnaligned && SrcInc)) {
- ChanCtrl = &Mem2MemByteCC;
- }
-
- if (ChanCtrl->SrcInc) {
- MemBurstSize = ChanCtrl->SrcBurstSize;
- MemAddr = SrcAddr;
-
- } else if (ChanCtrl->DstInc) {
- MemBurstSize = ChanCtrl->DstBurstSize;
- MemAddr = DstAddr;
- }
-
- /* check whether the head is aligned or not */
- Unaligned = MemAddr % MemBurstSize;
-
- if (Unaligned) {
- /* if head is unaligned, transfer head in bytes */
- UnalignedCount = MemBurstSize - Unaligned;
- CCRValue = XDMAPS_CCR_SINGLE_BYTE
- | (SrcInc & 1)
- | ((DstInc & 1) << 14);
-
- DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
- XDMAPS_MOV_CCR,
- CCRValue);
-
- for (Index = 0; Index < UnalignedCount; Index++) {
- DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf);
- DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf);
- }
-
- DmaLength -= UnalignedCount;
- }
-
- /* now the burst transfer part */
- CCRValue = XDmaPs_ToCCRValue(ChanCtrl);
- DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf,
- XDMAPS_MOV_CCR,
- CCRValue);
-
- BurstBytes = ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen;
-
- LoopCount = DmaLength / BurstBytes;
- TailBytes = DmaLength % BurstBytes;
-
- /*
- * the loop count register is 8-bit wide, so if we need
- * a larger loop, we need to have nested loops
- */
- if (LoopCount > 256) {
- LoopCount1 = LoopCount / 256;
- if (LoopCount1 > 256) {
- xil_printf("DMA operation cannot fit in a 2-level "
- "loop for channel %d, please reduce the "
- "DMA length or increase the burst size or "
- "length",
- Channel);
- return 0;
- }
- LoopResidue = LoopCount % 256;
-
- if (LoopCount1 > 1)
- DmaProgBuf +=
- XDmaPs_ConstructNestedLoop(DmaProgStart,
- CacheLength,
- DmaProgBuf,
- LoopCount1,
- 256);
- else
- DmaProgBuf +=
- XDmaPs_ConstructSingleLoop(DmaProgStart,
- CacheLength,
- DmaProgBuf,
- 256);
-
- /* there will be some that cannot be covered by
- * nested loops
- */
- LoopCount = LoopResidue;
- }
-
- if (LoopCount > 0) {
- DmaProgBuf += XDmaPs_ConstructSingleLoop(DmaProgStart,
- CacheLength,
- DmaProgBuf,
- LoopCount);
- }
-
- if (TailBytes) {
- /* handle the tail */
- TailWords = TailBytes / MemBurstSize;
- TailBytes = TailBytes % MemBurstSize;
-
- if (TailWords) {
- WordChanCtrl = *ChanCtrl;
- /*
- * if we can transfer the tail in words, we will
- * transfer words as much as possible
- */
- WordChanCtrl.SrcBurstSize = MemBurstSize;
- WordChanCtrl.SrcBurstLen = 1;
- WordChanCtrl.DstBurstSize = MemBurstSize;
- WordChanCtrl.DstBurstLen = 1;
-
-
- /*
- * the burst length is 1
- */
- CCRValue = XDmaPs_ToCCRValue(&WordChanCtrl);
-
- DmaProgBuf +=
- XDmaPs_Instr_DMAMOV(DmaProgBuf,
- XDMAPS_MOV_CCR,
- CCRValue);
- DmaProgBuf +=
- XDmaPs_ConstructSingleLoop(DmaProgStart,
- CacheLength,
- DmaProgBuf,
- TailWords);
-
- }
-
- if (TailBytes) {
- /*
- * for the rest, we'll tranfer in bytes
- */
- /*
- * So far just to be safe, the tail bytes
- * are transfered in a loop. We can optimize a little
- * to perform a burst.
- */
- CCRValue = XDMAPS_CCR_SINGLE_BYTE
- | (SrcInc & 1)
- | ((DstInc & 1) << 14);
-
- DmaProgBuf +=
- XDmaPs_Instr_DMAMOV(DmaProgBuf,
- XDMAPS_MOV_CCR,
- CCRValue);
-
- DmaProgBuf +=
- XDmaPs_ConstructSingleLoop(DmaProgStart,
- CacheLength,
- DmaProgBuf,
- TailBytes);
-
- }
- }
-
- /* Add a memory barrier before DMASSEV as recommended by spec */
- DmaProgBuf += XDmaPs_Instr_DMAWMB(DmaProgBuf);
- DmaProgBuf += XDmaPs_Instr_DMASEV(DmaProgBuf, DevChan);
- DmaProgBuf += XDmaPs_Instr_DMAEND(DmaProgBuf);
-
- DmaProgBytes = DmaProgBuf - DmaProgStart;
-
- Xil_DCacheFlushRange((u32)DmaProgStart, DmaProgBytes);
-
- return DmaProgBytes;
-
-}
-
-
-/****************************************************************************/
-/**
-*
-* Generate a DMA program based for the DMA command, the buffer will be pointed
-* by the GeneratedDmaProg field of the command.
-*
-* @param InstPtr is then DMA instance.
-* @param Channel is the DMA channel number.
-* @param Cmd is the DMA command.
-*
-* @return - XST_SUCCESS on success.
-* - XST_FAILURE if it fails
-*
-* @note None.
-*
-*****************************************************************************/
-int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd)
-{
- void *Buf;
- int ProgLen;
- XDmaPs_ChannelData *ChanData;
- XDmaPs_ChanCtrl *ChanCtrl;
-
- Xil_AssertNonvoid(InstPtr != NULL);
- Xil_AssertNonvoid(Cmd != NULL);
-
-
- if (Channel > XDMAPS_CHANNELS_PER_DEV)
- return XST_FAILURE;
-
- ChanData = InstPtr->Chans + Channel;
- ChanCtrl = &Cmd->ChanCtrl;
-
- if (ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen
- != ChanCtrl->DstBurstSize * ChanCtrl->DstBurstLen) {
- return XST_FAILURE;
- }
-
-
- /*
- * unaligned fixed address is not supported
- */
- if (!ChanCtrl->SrcInc && Cmd->BD.SrcAddr % ChanCtrl->SrcBurstSize) {
- return XST_FAILURE;
- }
-
- if (!ChanCtrl->DstInc && Cmd->BD.DstAddr % ChanCtrl->DstBurstSize) {
- return XST_FAILURE;
- }
-
- Buf = XDmaPs_BufPool_Allocate(ChanData->ProgBufPool);
- if (Buf == NULL) {
- return XST_FAILURE;
- }
-
- Cmd->GeneratedDmaProg = Buf;
- ProgLen = XDmaPs_BuildDmaProg(Channel, Cmd,
- InstPtr->CacheLength);
- Cmd->GeneratedDmaProgLength = ProgLen;
-
-
-#ifdef XDMAPS_DEBUG
- XDmaPs_Print_DmaProg(Cmd);
-#endif
-
- if (ProgLen <= 0) {
- /* something wrong, release the buffer */
- XDmaPs_BufPool_Free(ChanData->ProgBufPool, Buf);
- Cmd->GeneratedDmaProgLength = 0;
- Cmd->GeneratedDmaProg = NULL;
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/****************************************************************************/
-/**
- * Free the DMA program buffer that is pointed by the GeneratedDmaProg field
- * of the command.
- *
- * @param InstPtr is then DMA instance.
- * @param Channel is the DMA channel number.
- * @param Cmd is the DMA command.
- *
- * @return XST_SUCCESS on success.
- * XST_FAILURE if there is any error.
- *
- * @note None.
- *
- ****************************************************************************/
-int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd)
-{
-
- void *Buf;
- XDmaPs_ChannelData *ChanData;
-
- Xil_AssertNonvoid(InstPtr != NULL);
- Xil_AssertNonvoid(Cmd != NULL);
-
- if (Channel > XDMAPS_CHANNELS_PER_DEV)
- return XST_FAILURE;
-
- Buf = (void *)Cmd->GeneratedDmaProg;
- ChanData = InstPtr->Chans + Channel;
-
- if (Buf) {
- XDmaPs_BufPool_Free(ChanData->ProgBufPool, Buf);
- Cmd->GeneratedDmaProg = 0;
- Cmd->GeneratedDmaProgLength = 0;
- }
-
- return XST_SUCCESS;
-}
-
-
-/****************************************************************************/
-/**
-*
-* Start a DMA command. The command can only be invoked when the channel
-* is idle. The driver takes the command, generates DMA program if needed,
-* then pass the program to DMAC to execute.
-*
-* @param InstPtr is then DMA instance.
-* @param Channel is the DMA channel number.
-* @param Cmd is the DMA command.
-* @param HoldDmaProg is tag indicating whether the driver can release
-* the allocated DMA buffer or not. If a user wants to examine the
-* generated DMA program, the flag should be set to 1. After the
-* DMA program is finished, a user needs to explicity free the
-* buffer.
-*
-* @return
-* - XST_SUCCESS on success
-* - XST_DEVICE_BUSY if DMA is busy
-* - XST_FAILURE on other failures
-*
-* @note None.
-*
-****************************************************************************/
-int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
- XDmaPs_Cmd *Cmd,
- int HoldDmaProg)
-{
- int Status;
- u32 DmaProg = 0;
- u32 Inten;
-
- Xil_AssertNonvoid(InstPtr != NULL);
- Xil_AssertNonvoid(Cmd != NULL);
-
-
- Cmd->DmaStatus = XST_FAILURE;
-
- if (XDmaPs_IsActive(InstPtr, Channel))
- return XST_DEVICE_BUSY;
-
- if (!Cmd->UserDmaProg && !Cmd->GeneratedDmaProg) {
- Status = XDmaPs_GenDmaProg(InstPtr, Channel, Cmd);
- if (Status)
- return XST_FAILURE;
- }
-
- InstPtr->Chans[Channel].HoldDmaProg = HoldDmaProg;
-
- if (Cmd->UserDmaProg)
- DmaProg = (u32)Cmd->UserDmaProg;
- else if (Cmd->GeneratedDmaProg)
- DmaProg = (u32)Cmd->GeneratedDmaProg;
-
- if (DmaProg) {
- /* enable the interrupt */
- Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
- XDMAPS_INTEN_OFFSET);
- Inten |= 0x01 << Channel; /* set the correpsonding bit */
- XDmaPs_WriteReg(InstPtr->Config.BaseAddress,
- XDMAPS_INTEN_OFFSET,
- Inten);
- Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
- XDMAPS_INTEN_OFFSET);
-
- InstPtr->Chans[Channel].DmaCmdToHw = Cmd;
-
- if (Cmd->ChanCtrl.SrcInc) {
- Xil_DCacheFlushRange(Cmd->BD.SrcAddr, Cmd->BD.Length);
- }
- if (Cmd->ChanCtrl.DstInc) {
- Xil_DCacheInvalidateRange(Cmd->BD.DstAddr,
- Cmd->BD.Length);
- }
-
- Status = XDmaPs_Exec_DMAGO(InstPtr->Config.BaseAddress,
- Channel, DmaProg);
- }
- else {
- InstPtr->Chans[Channel].DmaCmdToHw = NULL;
- Status = XST_FAILURE;
- }
-
- return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* Checks whether the DMA channel is active or idle.
-*
-* @param InstPtr is the DMA instance.
-* @param Channel is the DMA channel number.
-*
-* @return 0: if the channel is idle
-* 1: otherwise
-*
-* @note None.
-*
-*****************************************************************************/
-int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel)
-{
- Xil_AssertNonvoid(InstPtr != NULL);
-
- /* Need to assert Channel is in range */
- if (Channel >= XDMAPS_CHANNELS_PER_DEV)
- return XST_FAILURE;
-
- return InstPtr->Chans[Channel].DmaCmdToHw != NULL;
-}
-
-
-
-/****************************************************************************/
-/**
-*
-* Allocate a buffer of the DMA program buffer from the pool.
-*
-* @param Pool the DMA program pool.
-*
-* @return The allocated buffer, NULL if there is any error.
-*
-* @note None.
-*
-*****************************************************************************/
-static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool)
-{
- int Index;
-
- Xil_AssertNonvoid(Pool != NULL);
-
- for (Index = 0; Index < XDMAPS_MAX_CHAN_BUFS; Index++) {
- if (!Pool[Index].Allocated) {
- Pool[Index].Allocated = 1;
- return Pool[Index].Buf;
- }
- }
-
- return NULL;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* Driver done interrupt service routine for channel 0. We need this done ISR
-* mainly because the driver needs to release the DMA program buffer.
-* This is the one that connects the GIC
-*
-* @param InstPtr is the DMA instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XDmaPs_DoneISR_0(XDmaPs *InstPtr)
-{
- XDmaPs_DoneISR_n(InstPtr, 0);
-}
-
-/*****************************************************************************/
-/**
-*
-* Driver done interrupt service routine for channel 1. We need this done ISR
-* mainly because the driver needs to release the DMA program buffer.
-* This is the one that connects the GIC
-*
-* @param InstPtr is the DMA instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XDmaPs_DoneISR_1(XDmaPs *InstPtr)
-{
- XDmaPs_DoneISR_n(InstPtr, 1);
-}
-
-/*****************************************************************************/
-/**
-*
-* Driver done interrupt service routine for channel 2. We need this done ISR
-* mainly because the driver needs to release the DMA program buffer.
-* This is the one that connects the GIC
-*
-* @param InstPtr is the DMA instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XDmaPs_DoneISR_2(XDmaPs *InstPtr)
-{
- XDmaPs_DoneISR_n(InstPtr, 2);
-}
-
-/*****************************************************************************/
-/**
-*
-* Driver done interrupt service routine for channel 3. We need this done ISR
-* mainly because the driver needs to release the DMA program buffer.
-* This is the one that connects the GIC
-*
-* @param InstPtr is the DMA instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XDmaPs_DoneISR_3(XDmaPs *InstPtr)
-{
- XDmaPs_DoneISR_n(InstPtr, 3);
-}
-
-/*****************************************************************************/
-/**
-*
-* Driver done interrupt service routine for channel 4. We need this done ISR
-* mainly because the driver needs to release the DMA program buffer.
-* This is the one that connects the GIC
-*
-* @param InstPtr is the DMA instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XDmaPs_DoneISR_4(XDmaPs *InstPtr)
-{
- XDmaPs_DoneISR_n(InstPtr, 4);
-}
-
-/*****************************************************************************/
-/**
-*
-* Driver done interrupt service routine for channel 5. We need this done ISR
-* mainly because the driver needs to release the DMA program buffer.
-* This is the one that connects the GIC
-*
-* @param InstPtr is the DMA instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XDmaPs_DoneISR_5(XDmaPs *InstPtr)
-{
- XDmaPs_DoneISR_n(InstPtr, 5);
-}
-
-/*****************************************************************************/
-/**
-*
-* Driver done interrupt service routine for channel 6. We need this done ISR
-* mainly because the driver needs to release the DMA program buffer.
-* This is the one that connects the GIC
-*
-* @param InstPtr is the DMA instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XDmaPs_DoneISR_6(XDmaPs *InstPtr)
-{
- XDmaPs_DoneISR_n(InstPtr, 6);
-}
-
-/*****************************************************************************/
-/**
-*
-* Driver done interrupt service routine for channel 7. We need this done ISR
-* mainly because the driver needs to release the DMA program buffer.
-* This is the one that connects the GIC
-*
-* @param InstPtr is the DMA instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XDmaPs_DoneISR_7(XDmaPs *InstPtr)
-{
- XDmaPs_DoneISR_n(InstPtr, 7);
-}
-
-#ifndef XDMAPS_MAX_WAIT
-#define XDMAPS_MAX_WAIT 4000
-#endif
-
-/****************************************************************************/
-/**
-* Use the debug registers to kill the DMA thread.
-*
-* @param BaseAddr is DMA device base address.
-* @param Channel is the DMA channel number.
-* @param Thread is Debug thread encoding.
-* 0: DMA manager thread, 1: DMA channel.
-*
-* @return 0 on success, -1 on time out
-*
-* @note None.
-*
-*****************************************************************************/
-static int XDmaPs_Exec_DMAKILL(u32 BaseAddr,
- unsigned int Channel,
- unsigned int Thread)
-{
- u32 DbgInst0;
- int WaitCount;
-
- DbgInst0 = XDmaPs_DBGINST0(0, 0x01, Channel, Thread);
-
- /* wait while debug status is busy */
- WaitCount = 0;
- while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
- & XDMAPS_DBGSTATUS_BUSY)
- && (WaitCount < XDMAPS_MAX_WAIT))
- WaitCount++;
-
- if (WaitCount >= XDMAPS_MAX_WAIT) {
- /* wait time out */
- xil_printf("PL330 device at %x debug status busy time out\n",
- BaseAddr);
-
- return -1;
- }
-
- /* write debug instruction 0 */
- XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST0_OFFSET, DbgInst0);
-
- XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST1_OFFSET, 0);
-
-
- /* run the command in DbgInst0 and DbgInst1 */
- XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGCMD_OFFSET, 0);
-
- return 0;
-}
-
-/****************************************************************************/
-/**
-*
-*
-* Free a buffer of the DMA program buffer.
-* @param Pool the DMA program pool.
-* @param Buf the DMA program buffer to be release.
-*
-* @return None
-*
-* @note None.
-*
-*****************************************************************************/
-static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf)
-{
- int Index;
- Xil_AssertVoid(Pool != NULL);
-
- for (Index = 0; Index < XDMAPS_MAX_CHAN_BUFS; Index++) {
- if (Pool[Index].Buf == Buf) {
- if (Pool[Index].Allocated) {
- Pool[Index].Allocated = 0;
- }
- }
- }
-}
-
-/*****************************************************************************/
-/**
-* XDmaPs_Exec_DMAGO - Execute the DMAGO to start a channel.
-*
-* @param BaseAddr PL330 device base address
-* @param Channel Channel number for the device
-* @param DmaProg DMA program starting address, this should be DMA address
-*
-* @return 0 on success, -1 on time out
-*
-* @note None.
-*
-****************************************************************************/
-static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg)
-{
- char DmaGoProg[8];
- u32 DbgInst0;
- u32 DbgInst1;
-
- int WaitCount;
-
- XDmaPs_Instr_DMAGO(DmaGoProg, Channel, DmaProg, 0);
-
- DbgInst0 = XDmaPs_DBGINST0(*(DmaGoProg + 1), *DmaGoProg, 0, 0);
- DbgInst1 = (u32)DmaProg;
-
- /* wait while debug status is busy */
- WaitCount = 0;
- while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET)
- & XDMAPS_DBGSTATUS_BUSY)
- && (WaitCount < XDMAPS_MAX_WAIT)) {
-
- WaitCount++;
- }
-
- if (WaitCount >= XDMAPS_MAX_WAIT) {
- xil_printf("PL330 device at %x debug status busy time out\r\n",
- BaseAddr);
- return -1;
- }
-
- /* write debug instruction 0 */
- XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST0_OFFSET, DbgInst0);
- /* write debug instruction 1 */
- XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST1_OFFSET, DbgInst1);
-
-
- /* wait while the DMA Manager is busy */
- WaitCount = 0;
- while ((XDmaPs_ReadReg(BaseAddr,
- XDMAPS_DS_OFFSET) & XDMAPS_DS_DMA_STATUS)
- != XDMAPS_DS_DMA_STATUS_STOPPED
- && WaitCount <= XDMAPS_MAX_WAIT) {
- WaitCount++;
- }
-
- if (WaitCount >= XDMAPS_MAX_WAIT) {
- xil_printf("PL330 device at %x debug status busy time out\r\n",
- BaseAddr);
- return -1;
- }
-
- /* run the command in DbgInst0 and DbgInst1 */
- XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGCMD_OFFSET, 0);
-
- return 0;
-}
-
-
-/****************************************************************************/
-/**
-*
-* It's the generic Done ISR.
-* @param InstPtr is the DMA instance.
-* @param Channel is the DMA channel numer.
-*
-* @return None.*
-*
-* @note None.
-*
-*****************************************************************************/
-static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel)
-{
-
- void *DmaProgBuf;
- XDmaPs_ChannelData *ChanData;
- XDmaPs_Cmd *DmaCmd;
- //u32 Value;
-
- ChanData = InstPtr->Chans + Channel;
-
- /*Value = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
- XDMAPS_INTSTATUS_OFFSET);*/
-
- /* clear the interrupt status */
- XDmaPs_WriteReg(InstPtr->Config.BaseAddress,
- XDMAPS_INTCLR_OFFSET,
- 1 << ChanData->ChanId);
-
- /*Value = XDmaPs_ReadReg(InstPtr->Config.BaseAddress,
- XDMAPS_INTSTATUS_OFFSET);*/
-
-
- DmaCmd = ChanData->DmaCmdToHw;
- if (DmaCmd) {
- if (!ChanData->HoldDmaProg) {
- DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg;
- if (DmaProgBuf)
- XDmaPs_BufPool_Free(ChanData->ProgBufPool,
- DmaProgBuf);
- DmaCmd->GeneratedDmaProg = NULL;
- }
-
- DmaCmd->DmaStatus = 0;
- ChanData->DmaCmdToHw = NULL;
- ChanData->DmaCmdFromHw = DmaCmd;
-
- if (ChanData->DoneHandler)
- ChanData->DoneHandler(Channel, DmaCmd,
- ChanData->DoneRef);
- }
-
-}
-
-
-/****************************************************************************/
-/**
-* Prints the content of the buffer in bytes
-* @param Buf is the buffer.
-* @param Length is the length of the DMA program.
-*
-* @return None.
-*
-* @note None.
-****************************************************************************/
-static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length)
-{
- int Index;
- for (Index = 0; Index < Length; Index++)
- xil_printf("[%x] %x\r\n", Index, Buf[Index]);
-
-}
-/****************************************************************************/
-/**
-* Print the Dma Prog Contents.
-*
-* @param Cmd is the command buffer.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
- void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd)
-{
- if (Cmd->GeneratedDmaProg && Cmd->GeneratedDmaProgLength) {
- xil_printf("Generated DMA program (%d):\r\n",
- Cmd->GeneratedDmaProgLength);
- XDmaPs_Print_DmaProgBuf((char *)Cmd->GeneratedDmaProg,
- Cmd->GeneratedDmaProgLength);
- }
-
- if (Cmd->UserDmaProg && Cmd->UserDmaProgLength) {
- xil_printf("User defined DMA program (%d):\r\n",
- Cmd->UserDmaProgLength);
- XDmaPs_Print_DmaProgBuf((char *)Cmd->UserDmaProg,
- Cmd->UserDmaProgLength);
- }
-}
-
-
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/59/d0f4a1555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/59/d0f4a1555243001d18b399c1eb9b3628
deleted file mode 100644
index e3e7962..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/59/d0f4a1555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,95 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/* write.c -- write bytes to an output device.
- */
-#ifndef UNDEFINE_FILE_OPS
-#include "xil_printf.h"
-#include "xparameters.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) sint32 _write (sint32 fd, char8* buf, sint32 nbytes);
-}
-#endif
-
-/*
- * write -- write bytes to the serial port. Ignore fd, since
- * stdout and stderr are the same. Since we have no filesystem,
- * open will only return an error.
- */
-__attribute__((weak)) sint32
-write (sint32 fd, char8* buf, sint32 nbytes)
-
-{
-#ifdef STDOUT_BASEADDRESS
- s32 i;
- char8* LocalBuf = buf;
-
- (void)fd;
- for (i = 0; i < nbytes; i++) {
- if(LocalBuf != NULL) {
- LocalBuf += i;
- }
- if(LocalBuf != NULL) {
- if (*LocalBuf == '\n') {
- outbyte ('\r');
- }
- outbyte (*LocalBuf);
- }
- if(LocalBuf != NULL) {
- LocalBuf -= i;
- }
- }
- return (nbytes);
-#else
- (void)fd;
- (void)buf;
- (void)nbytes;
- return 0;
-#endif
-}
-
-__attribute__((weak)) sint32
-_write (sint32 fd, char8* buf, sint32 nbytes)
-{
-#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
- sint32 length;
-
- (void)fd;
- (void)nbytes;
- length = XPVXenConsole_Write(buf);
- return length;
-#else
-#ifdef STDOUT_BASEADDRESS
- s32 i;
- char8* LocalBuf = buf;
-
- (void)fd;
- for (i = 0; i < nbytes; i++) {
- if(LocalBuf != NULL) {
- LocalBuf += i;
- }
- if(LocalBuf != NULL) {
- if (*LocalBuf == '\n') {
- outbyte ('\r');
- }
- outbyte (*LocalBuf);
- }
- if(LocalBuf != NULL) {
- LocalBuf -= i;
- }
- }
- return (nbytes);
-#else
- (void)fd;
- (void)buf;
- (void)nbytes;
- return 0;
-#endif
-#endif
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5a/702032595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5a/702032595243001d18b399c1eb9b3628
deleted file mode 100644
index d8aef59..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5a/702032595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,169 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xenv.h
-*
-* Defines common services that are typically found in a host operating.
-* environment. This include file simply includes an OS specific file based
-* on the compile-time constant BUILD_ENV_*, where * is the name of the target
-* environment.
-*
-* All services are defined as macros.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b ch 10/24/02 Added XENV_LINUX
-* 1.00a rmm 04/17/02 First release
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XENV_H /* prevent circular inclusions */
-#define XENV_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * Select which target environment we are operating under
- */
-
-/* VxWorks target environment */
-#if defined XENV_VXWORKS
-#include "xenv_vxworks.h"
-
-/* Linux target environment */
-#elif defined XENV_LINUX
-#include "xenv_linux.h"
-
-/* Unit test environment */
-#elif defined XENV_UNITTEST
-#include "ut_xenv.h"
-
-/* Integration test environment */
-#elif defined XENV_INTTEST
-#include "int_xenv.h"
-
-/* Standalone environment selected */
-#else
-#include "xenv_standalone.h"
-#endif
-
-
-/*
- * The following comments specify the types and macro wrappers that are
- * expected to be defined by the target specific header files
- */
-
-/**************************** Type Definitions *******************************/
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP
- *
- * A structure that contains a time stamp used by other time stamp macros
- * defined below. This structure is processor dependent.
- */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- *
- * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
- *
- * Copies a non-overlapping block of memory.
- *
- * @param DestPtr is the destination address to copy data to.
- * @param SrcPtr is the source address to copy data from.
- * @param Bytes is the number of bytes to copy.
- *
- * @return None
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
- *
- * Fills an area of memory with constant data.
- *
- * @param DestPtr is the destination address to set.
- * @param Data contains the value to set.
- * @param Bytes is the number of bytes to set.
- *
- * @return None
- */
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
- *
- * Samples the processor's or external timer's time base counter.
- *
- * @param StampPtr is the storage for the retrieved time stamp.
- *
- * @return None
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
- *
- * Computes the delta between the two time stamps.
- *
- * @param Stamp1Ptr - First sampled time stamp.
- * @param Stamp1Ptr - Sedond sampled time stamp.
- *
- * @return An unsigned int value with units of microseconds.
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
- *
- * Computes the delta between the two time stamps.
- *
- * @param Stamp1Ptr - First sampled time stamp.
- * @param Stamp1Ptr - Sedond sampled time stamp.
- *
- * @return An unsigned int value with units of milliseconds.
- */
-
-/*****************************************************************************//**
- *
- * XENV_USLEEP(unsigned delay)
- *
- * Delay the specified number of microseconds.
- *
- * @param delay is the number of microseconds to delay.
- *
- * @return None
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5a/702305565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5a/702305565243001d18b399c1eb9b3628
deleted file mode 100644
index 1befce1..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5a/702305565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,255 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpm_counter.c
-*
-* This file contains APIs for configuring and controlling the Cortex-A9
-* Performance Monitor Events. For more information about the event counters,
-* see xpm_counter.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 4.2 pkp 07/21/14 Corrected reset value of event counter in function
-* Xpm_ResetEventCounters to fix CR#796275
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xpm_counter.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-typedef const u32 PmcrEventCfg32[XPM_CTRCOUNT];
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void Xpm_DisableEventCounters(void);
-void Xpm_EnableEventCounters (void);
-void Xpm_ResetEventCounters (void);
-
-/******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @brief This function disables the Cortex A9 event counters.
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_DisableEventCounters(void)
-{
- /* Disable the event counters */
- mtcp(XREG_CP15_COUNT_ENABLE_CLR, 0x3f);
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function enables the Cortex A9 event counters.
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_EnableEventCounters(void)
-{
- /* Enable the event counters */
- mtcp(XREG_CP15_COUNT_ENABLE_SET, 0x3f);
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function resets the Cortex A9 event counters.
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_ResetEventCounters(void)
-{
- u32 Reg;
-#ifdef __GNUC__
- Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
-#else
- { register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL);
- Reg = C15Reg; }
-#endif
- Reg |= (1U << 1U); /* reset event counters */
- mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
-
-}
-
-/****************************************************************************/
-/**
-* @brief This function configures the Cortex A9 event counters controller,
-* with the event codes, in a configuration selected by the user and
-* enables the counters.
-*
-* @param PmcrCfg: Configuration value based on which the event counters
-* are configured. XPM_CNTRCFG* values defined in xpm_counter.h can
-* be utilized for setting configuration.
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_SetEvents(s32 PmcrCfg)
-{
- u32 Counter;
- static PmcrEventCfg32 PmcrEvents[] = {
- {
- XPM_EVENT_SOFTINCR,
- XPM_EVENT_INSRFETCH_CACHEREFILL,
- XPM_EVENT_INSTRFECT_TLBREFILL,
- XPM_EVENT_DATA_CACHEREFILL,
- XPM_EVENT_DATA_CACHEACCESS,
- XPM_EVENT_DATA_TLBREFILL
- },
- {
- XPM_EVENT_DATA_READS,
- XPM_EVENT_DATA_WRITE,
- XPM_EVENT_EXCEPTION,
- XPM_EVENT_EXCEPRETURN,
- XPM_EVENT_CHANGECONTEXT,
- XPM_EVENT_SW_CHANGEPC
- },
- {
- XPM_EVENT_IMMEDBRANCH,
- XPM_EVENT_UNALIGNEDACCESS,
- XPM_EVENT_BRANCHMISS,
- XPM_EVENT_CLOCKCYCLES,
- XPM_EVENT_BRANCHPREDICT,
- XPM_EVENT_JAVABYTECODE
- },
- {
- XPM_EVENT_SWJAVABYTECODE,
- XPM_EVENT_JAVABACKBRANCH,
- XPM_EVENT_COHERLINEMISS,
- XPM_EVENT_COHERLINEHIT,
- XPM_EVENT_INSTRSTALL,
- XPM_EVENT_DATASTALL
- },
- {
- XPM_EVENT_MAINTLBSTALL,
- XPM_EVENT_STREXPASS,
- XPM_EVENT_STREXFAIL,
- XPM_EVENT_DATAEVICT,
- XPM_EVENT_NODISPATCH,
- XPM_EVENT_ISSUEEMPTY
- },
- {
- XPM_EVENT_INSTRRENAME,
- XPM_EVENT_PREDICTFUNCRET,
- XPM_EVENT_MAINEXEC,
- XPM_EVENT_SECEXEC,
- XPM_EVENT_LDRSTR,
- XPM_EVENT_FLOATRENAME
- },
- {
- XPM_EVENT_NEONRENAME,
- XPM_EVENT_PLDSTALL,
- XPM_EVENT_WRITESTALL,
- XPM_EVENT_INSTRTLBSTALL,
- XPM_EVENT_DATATLBSTALL,
- XPM_EVENT_INSTR_uTLBSTALL
- },
- {
- XPM_EVENT_DATA_uTLBSTALL,
- XPM_EVENT_DMB_STALL,
- XPM_EVENT_INT_CLKEN,
- XPM_EVENT_DE_CLKEN,
- XPM_EVENT_INSTRISB,
- XPM_EVENT_INSTRDSB
- },
- {
- XPM_EVENT_INSTRDMB,
- XPM_EVENT_EXTINT,
- XPM_EVENT_PLE_LRC,
- XPM_EVENT_PLE_LRS,
- XPM_EVENT_PLE_FLUSH,
- XPM_EVENT_PLE_CMPL
- },
- {
- XPM_EVENT_PLE_OVFL,
- XPM_EVENT_PLE_PROG,
- XPM_EVENT_PLE_LRC,
- XPM_EVENT_PLE_LRS,
- XPM_EVENT_PLE_FLUSH,
- XPM_EVENT_PLE_CMPL
- },
- {
- XPM_EVENT_DATASTALL,
- XPM_EVENT_INSRFETCH_CACHEREFILL,
- XPM_EVENT_INSTRFECT_TLBREFILL,
- XPM_EVENT_DATA_CACHEREFILL,
- XPM_EVENT_DATA_CACHEACCESS,
- XPM_EVENT_DATA_TLBREFILL
- },
- };
- const u32 *ptr = PmcrEvents[PmcrCfg];
-
- Xpm_DisableEventCounters();
-
- for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
-
- /* Selecet event counter */
- mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
-
- /* Set the event */
- mtcp(XREG_CP15_EVENT_TYPE_SEL, ptr[Counter]);
- }
-
- Xpm_ResetEventCounters();
- Xpm_EnableEventCounters();
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function disables the event counters and returns the counter
-* values.
-*
-* @param PmCtrValue: Pointer to an array of type u32 PmCtrValue[6].
-* It is an output parameter which is used to return the PM
-* counter values.
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_GetEventCounters(u32 *PmCtrValue)
-{
- u32 Counter;
-
- Xpm_DisableEventCounters();
-
- for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
-
- mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
-#ifdef __GNUC__
- PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_PERF_MONITOR_COUNT, PmCtrValue[Counter]);
-#else
- { register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT);
- PmCtrValue[Counter] = Cp15Reg; }
-#endif
- }
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5a/819edf595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5a/819edf595243001d18b399c1eb9b3628
deleted file mode 100644
index 51cc7c5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5a/819edf595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,477 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xadcps_hw.h
-* @addtogroup xadcps_v2_6
-* @{
-*
-* This header file contains identifiers and basic driver functions (or
-* macros) that can be used to access the XADC device through the Device
-* Config Interface of the Zynq.
-*
-*
-* Refer to the device specification for more information about this driver.
-*
-* @note None.
-*
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a bss 12/22/11 First release based on the XPS/AXI xadc driver
-* 1.03a bss 11/01/13 Modified macros to use correct Register offsets
-* CR#749687
-* 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors.
-*
-*
-*
-*****************************************************************************/
-#ifndef XADCPS_HW_H /* Prevent circular inclusions */
-#define XADCPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**@name Register offsets of XADC in the Device Config
- *
- * The following constants provide access to each of the registers of the
- * XADC device.
- * @{
- */
-
-#define XADCPS_CFG_OFFSET 0x00U /**< Configuration Register */
-#define XADCPS_INT_STS_OFFSET 0x04U /**< Interrupt Status Register */
-#define XADCPS_INT_MASK_OFFSET 0x08U /**< Interrupt Mask Register */
-#define XADCPS_MSTS_OFFSET 0x0CU /**< Misc status register */
-#define XADCPS_CMDFIFO_OFFSET 0x10U /**< Command FIFO Register */
-#define XADCPS_RDFIFO_OFFSET 0x14U /**< Read FIFO Register */
-#define XADCPS_MCTL_OFFSET 0x18U /**< Misc control register */
-
-/* @} */
-
-
-
-
-
-/** @name XADC Config Register Bit definitions
- * @{
- */
-#define XADCPS_CFG_ENABLE_MASK 0x80000000U /**< Enable access from PS mask */
-#define XADCPS_CFG_CFIFOTH_MASK 0x00F00000U /**< Command FIFO Threshold mask */
-#define XADCPS_CFG_DFIFOTH_MASK 0x000F0000U /**< Data FIFO Threshold mask */
-#define XADCPS_CFG_WEDGE_MASK 0x00002000U /**< Write Edge Mask */
-#define XADCPS_CFG_REDGE_MASK 0x00001000U /**< Read Edge Mask */
-#define XADCPS_CFG_TCKRATE_MASK 0x00000300U /**< Clock freq control */
-#define XADCPS_CFG_IGAP_MASK 0x0000001FU /**< Idle Gap between
- * successive commands */
-/* @} */
-
-
-/** @name XADC Interrupt Status/Mask Register Bit definitions
- *
- * The definitions are same for the Interrupt Status Register and
- * Interrupt Mask Register. They are defined only once.
- * @{
- */
-#define XADCPS_INTX_ALL_MASK 0x000003FFU /**< Alarm Signals Mask */
-#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200U /**< CMD FIFO less than threshold */
-#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100U /**< Data FIFO greater than threshold */
-#define XADCPS_INTX_OT_MASK 0x00000080U /**< Over temperature Alarm Status */
-#define XADCPS_INTX_ALM_ALL_MASK 0x0000007FU /**< Alarm Signals Mask */
-#define XADCPS_INTX_ALM6_MASK 0x00000040U /**< Alarm 6 Mask */
-#define XADCPS_INTX_ALM5_MASK 0x00000020U /**< Alarm 5 Mask */
-#define XADCPS_INTX_ALM4_MASK 0x00000010U /**< Alarm 4 Mask */
-#define XADCPS_INTX_ALM3_MASK 0x00000008U /**< Alarm 3 Mask */
-#define XADCPS_INTX_ALM2_MASK 0x00000004U /**< Alarm 2 Mask */
-#define XADCPS_INTX_ALM1_MASK 0x00000002U /**< Alarm 1 Mask */
-#define XADCPS_INTX_ALM0_MASK 0x00000001U /**< Alarm 0 Mask */
-
-/* @} */
-
-
-/** @name XADC Miscellaneous Register Bit definitions
- * @{
- */
-#define XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000U /**< Command FIFO Level mask */
-#define XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000U /**< Data FIFO Level Mask */
-#define XADCPS_MSTS_CFIFOF_MASK 0x00000800U /**< Command FIFO Full Mask */
-#define XADCPS_MSTS_CFIFOE_MASK 0x00000400U /**< Command FIFO Empty Mask */
-#define XADCPS_MSTS_DFIFOF_MASK 0x00000200U /**< Data FIFO Full Mask */
-#define XADCPS_MSTS_DFIFOE_MASK 0x00000100U /**< Data FIFO Empty Mask */
-#define XADCPS_MSTS_OT_MASK 0x00000080U /**< Over Temperature Mask */
-#define XADCPS_MSTS_ALM_MASK 0x0000007FU /**< Alarms Mask */
-/* @} */
-
-
-/** @name XADC Miscellaneous Control Register Bit definitions
- * @{
- */
-#define XADCPS_MCTL_RESET_MASK 0x00000010U /**< Reset XADC */
-#define XADCPS_MCTL_FLUSH_MASK 0x00000001U /**< Flush the FIFOs */
-/* @} */
-
-
-/**@name Internal Register offsets of the XADC
- *
- * The following constants provide access to each of the internal registers of
- * the XADC device.
- * @{
- */
-
-/*
- * XADC Internal Channel Registers
- */
-#define XADCPS_TEMP_OFFSET 0x00U /**< On-chip Temperature Reg */
-#define XADCPS_VCCINT_OFFSET 0x01U /**< On-chip VCCINT Data Reg */
-#define XADCPS_VCCAUX_OFFSET 0x02U /**< On-chip VCCAUX Data Reg */
-#define XADCPS_VPVN_OFFSET 0x03U /**< ADC out of VP/VN */
-#define XADCPS_VREFP_OFFSET 0x04U /**< On-chip VREFP Data Reg */
-#define XADCPS_VREFN_OFFSET 0x05U /**< On-chip VREFN Data Reg */
-#define XADCPS_VBRAM_OFFSET 0x06U /**< On-chip VBRAM , 7 Series */
-#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08U /**< ADC A Supply Offset Reg */
-#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09U /**< ADC A Offset Data Reg */
-#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0AU /**< ADC A Gain Error Reg */
-#define XADCPS_VCCPINT_OFFSET 0x0DU /**< On-chip VCCPINT Reg, Zynq */
-#define XADCPS_VCCPAUX_OFFSET 0x0EU /**< On-chip VCCPAUX Reg, Zynq */
-#define XADCPS_VCCPDRO_OFFSET 0x0FU /**< On-chip VCCPDRO Reg, Zynq */
-
-/*
- * XADC External Channel Registers
- */
-#define XADCPS_AUX00_OFFSET 0x10U /**< ADC out of VAUXP0/VAUXN0 */
-#define XADCPS_AUX01_OFFSET 0x11U /**< ADC out of VAUXP1/VAUXN1 */
-#define XADCPS_AUX02_OFFSET 0x12U /**< ADC out of VAUXP2/VAUXN2 */
-#define XADCPS_AUX03_OFFSET 0x13U /**< ADC out of VAUXP3/VAUXN3 */
-#define XADCPS_AUX04_OFFSET 0x14U /**< ADC out of VAUXP4/VAUXN4 */
-#define XADCPS_AUX05_OFFSET 0x15U /**< ADC out of VAUXP5/VAUXN5 */
-#define XADCPS_AUX06_OFFSET 0x16U /**< ADC out of VAUXP6/VAUXN6 */
-#define XADCPS_AUX07_OFFSET 0x17U /**< ADC out of VAUXP7/VAUXN7 */
-#define XADCPS_AUX08_OFFSET 0x18U /**< ADC out of VAUXP8/VAUXN8 */
-#define XADCPS_AUX09_OFFSET 0x19U /**< ADC out of VAUXP9/VAUXN9 */
-#define XADCPS_AUX10_OFFSET 0x1AU /**< ADC out of VAUXP10/VAUXN10 */
-#define XADCPS_AUX11_OFFSET 0x1BU /**< ADC out of VAUXP11/VAUXN11 */
-#define XADCPS_AUX12_OFFSET 0x1CU /**< ADC out of VAUXP12/VAUXN12 */
-#define XADCPS_AUX13_OFFSET 0x1DU /**< ADC out of VAUXP13/VAUXN13 */
-#define XADCPS_AUX14_OFFSET 0x1EU /**< ADC out of VAUXP14/VAUXN14 */
-#define XADCPS_AUX15_OFFSET 0x1FU /**< ADC out of VAUXP15/VAUXN15 */
-
-/*
- * XADC Registers for Maximum/Minimum data captured for the
- * on chip Temperature/VCCINT/VCCAUX data.
- */
-#define XADCPS_MAX_TEMP_OFFSET 0x20U /**< Max Temperature Reg */
-#define XADCPS_MAX_VCCINT_OFFSET 0x21U /**< Max VCCINT Register */
-#define XADCPS_MAX_VCCAUX_OFFSET 0x22U /**< Max VCCAUX Register */
-#define XADCPS_MAX_VCCBRAM_OFFSET 0x23U /**< Max BRAM Register, 7 series */
-#define XADCPS_MIN_TEMP_OFFSET 0x24U /**< Min Temperature Reg */
-#define XADCPS_MIN_VCCINT_OFFSET 0x25U /**< Min VCCINT Register */
-#define XADCPS_MIN_VCCAUX_OFFSET 0x26U /**< Min VCCAUX Register */
-#define XADCPS_MIN_VCCBRAM_OFFSET 0x27U /**< Min BRAM Register, 7 series */
-#define XADCPS_MAX_VCCPINT_OFFSET 0x28U /**< Max VCCPINT Register, Zynq */
-#define XADCPS_MAX_VCCPAUX_OFFSET 0x29U /**< Max VCCPAUX Register, Zynq */
-#define XADCPS_MAX_VCCPDRO_OFFSET 0x2AU /**< Max VCCPDRO Register, Zynq */
-#define XADCPS_MIN_VCCPINT_OFFSET 0x2CU /**< Min VCCPINT Register, Zynq */
-#define XADCPS_MIN_VCCPAUX_OFFSET 0x2DU /**< Min VCCPAUX Register, Zynq */
-#define XADCPS_MIN_VCCPDRO_OFFSET 0x2EU /**< Min VCCPDRO Register,Zynq */
- /* Undefined 0x2F to 0x3E */
-#define XADCPS_FLAG_OFFSET 0x3FU /**< Flag Register */
-
-/*
- * XADC Configuration Registers
- */
-#define XADCPS_CFR0_OFFSET 0x40U /**< Configuration Register 0 */
-#define XADCPS_CFR1_OFFSET 0x41U /**< Configuration Register 1 */
-#define XADCPS_CFR2_OFFSET 0x42U /**< Configuration Register 2 */
-
-/* Test Registers 0x43 to 0x47 */
-
-/*
- * XADC Sequence Registers
- */
-#define XADCPS_SEQ00_OFFSET 0x48U /**< Seq Reg 00 Adc Channel Selection */
-#define XADCPS_SEQ01_OFFSET 0x49U /**< Seq Reg 01 Adc Channel Selection */
-#define XADCPS_SEQ02_OFFSET 0x4AU /**< Seq Reg 02 Adc Average Enable */
-#define XADCPS_SEQ03_OFFSET 0x4BU /**< Seq Reg 03 Adc Average Enable */
-#define XADCPS_SEQ04_OFFSET 0x4CU /**< Seq Reg 04 Adc Input Mode Select */
-#define XADCPS_SEQ05_OFFSET 0x4DU /**< Seq Reg 05 Adc Input Mode Select */
-#define XADCPS_SEQ06_OFFSET 0x4EU /**< Seq Reg 06 Adc Acquisition Select */
-#define XADCPS_SEQ07_OFFSET 0x4FU /**< Seq Reg 07 Adc Acquisition Select */
-
-/*
- * XADC Alarm Threshold/Limit Registers (ATR)
- */
-#define XADCPS_ATR_TEMP_UPPER_OFFSET 0x50U /**< Temp Upper Alarm Register */
-#define XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51U /**< VCCINT Upper Alarm Reg */
-#define XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52U /**< VCCAUX Upper Alarm Reg */
-#define XADCPS_ATR_OT_UPPER_OFFSET 0x53U /**< Over Temp Upper Alarm Reg */
-#define XADCPS_ATR_TEMP_LOWER_OFFSET 0x54U /**< Temp Lower Alarm Register */
-#define XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55U /**< VCCINT Lower Alarm Reg */
-#define XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56U /**< VCCAUX Lower Alarm Reg */
-#define XADCPS_ATR_OT_LOWER_OFFSET 0x57U /**< Over Temp Lower Alarm Reg */
-#define XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58U /**< VBRAM Upper Alarm, 7 series */
-#define XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59U /**< VCCPINT Upper Alarm, Zynq */
-#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5AU /**< VCCPAUX Upper Alarm, Zynq */
-#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5BU /**< VCCPDRO Upper Alarm, Zynq */
-#define XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5CU /**< VRBAM Lower Alarm, 7 Series */
-#define XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5DU /**< VCCPINT Lower Alarm, Zynq */
-#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5EU /**< VCCPAUX Lower Alarm, Zynq */
-#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5FU /**< VCCPDRO Lower Alarm, Zynq */
-
-/* Undefined 0x60 to 0x7F */
-
-/*@}*/
-
-
-
-/**
- * @name Configuration Register 0 (CFR0) mask(s)
- * @{
- */
-#define XADCPS_CFR0_CAL_AVG_MASK 0x00008000U /**< Averaging enable Mask */
-#define XADCPS_CFR0_AVG_VALID_MASK 0x00003000U /**< Averaging bit Mask */
-#define XADCPS_CFR0_AVG1_MASK 0x00000000U /**< No Averaging */
-#define XADCPS_CFR0_AVG16_MASK 0x00001000U /**< Average 16 samples */
-#define XADCPS_CFR0_AVG64_MASK 0x00002000U /**< Average 64 samples */
-#define XADCPS_CFR0_AVG256_MASK 0x00003000U /**< Average 256 samples */
-#define XADCPS_CFR0_AVG_SHIFT 12U /**< Averaging bits shift */
-#define XADCPS_CFR0_MUX_MASK 0x00000800U /**< External Mask Enable */
-#define XADCPS_CFR0_DU_MASK 0x00000400U /**< Bipolar/Unipolar mode */
-#define XADCPS_CFR0_EC_MASK 0x00000200U /**< Event driven/
- * Continuous mode selection
- */
-#define XADCPS_CFR0_ACQ_MASK 0x00000100U /**< Add acquisition by 6 ADCCLK */
-#define XADCPS_CFR0_CHANNEL_MASK 0x0000001FU /**< Channel number bit Mask */
-
-/*@}*/
-
-/**
- * @name Configuration Register 1 (CFR1) mask(s)
- * @{
- */
-#define XADCPS_CFR1_SEQ_VALID_MASK 0x0000F000U /**< Sequence bit Mask */
-#define XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x00000000U /**< Default Safe Mode */
-#define XADCPS_CFR1_SEQ_ONEPASS_MASK 0x00001000U /**< Onepass through Seq */
-#define XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x00002000U /**< Continuous Cycling Seq */
-#define XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x00003000U /**< Single channel - No Seq */
-#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x00004000U /**< Simulataneous Sampling Mask */
-#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x00008000U /**< Independent Mode */
-#define XADCPS_CFR1_SEQ_SHIFT 12U /**< Sequence bit shift */
-#define XADCPS_CFR1_ALM_VCCPDRO_MASK 0x00000800U /**< Alm 6 - VCCPDRO, Zynq */
-#define XADCPS_CFR1_ALM_VCCPAUX_MASK 0x00000400U /**< Alm 5 - VCCPAUX, Zynq */
-#define XADCPS_CFR1_ALM_VCCPINT_MASK 0x00000200U /**< Alm 4 - VCCPINT, Zynq */
-#define XADCPS_CFR1_ALM_VBRAM_MASK 0x00000100U /**< Alm 3 - VBRAM, 7 series */
-#define XADCPS_CFR1_CAL_VALID_MASK 0x000000F0U /**< Valid Calibration Mask */
-#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x00000080U /**< Calibration 3 -Power
- Supply Gain/Offset
- Enable */
-#define XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x00000040U /**< Calibration 2 -Power
- Supply Offset Enable */
-#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x00000020U /**< Calibration 1 -ADC Gain
- Offset Enable */
-#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x00000010U /**< Calibration 0 -ADC Offset
- Enable */
-#define XADCPS_CFR1_CAL_DISABLE_MASK 0x00000000U /**< No Calibration */
-#define XADCPS_CFR1_ALM_ALL_MASK 0x00000F0FU /**< Mask for all alarms */
-#define XADCPS_CFR1_ALM_VCCAUX_MASK 0x00000008U /**< Alarm 2 - VCCAUX Enable */
-#define XADCPS_CFR1_ALM_VCCINT_MASK 0x00000004U /**< Alarm 1 - VCCINT Enable */
-#define XADCPS_CFR1_ALM_TEMP_MASK 0x00000002U /**< Alarm 0 - Temperature */
-#define XADCPS_CFR1_OT_MASK 0x00000001U /**< Over Temperature Enable */
-
-/*@}*/
-
-/**
- * @name Configuration Register 2 (CFR2) mask(s)
- * @{
- */
-#define XADCPS_CFR2_CD_VALID_MASK 0xFF00U /**
-
-
-
-
-
-
-
-
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5c/10ba2d565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5c/10ba2d565243001d18b399c1eb9b3628
deleted file mode 100644
index 7754298..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5c/10ba2d565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,54 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_mmu.h
-* This file only includes xil_mpu.h which contains Xil_SetTlbAttributes API
-* defined for MPU in R5. R5 does not have mmu and for usage of similar API
-* the file has been created.
-*
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.0 pkp 2/12/15 Initial version
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#ifndef XIL_MMU_H
-#define XIL_MMU_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/***************************** Include Files *********************************/
-
-#include "xil_mpu.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_MMU_H */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5c/310c63545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5c/310c63545243001d18b399c1eb9b3628
deleted file mode 100644
index 8d11ff8..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5c/310c63545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,365 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xscuwdt.h
-* @addtogroup scuwdt_v2_4
-* @{
-* @details
-*
-* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private
-* watchdog timer hardware.
-*
-* The XScuWdt driver supports the following features:
-* - Watchdog mode
-* - Timer mode
-* - Auto reload (timer mode only)
-*
-* The watchdog counter register is a down counter and starts decrementing when
-* the watchdog is started.
-* In watchdog mode, when the counter reaches 0, the Reset flag is set in the
-* Reset status register and the WDRESETREQ pin is asserted, causing a system
-* reset. The Reset flag is not reset by normal processor reset and is cleared
-* when written with a value of 1. This enables the user to differentiate a
-* normal reset and a reset caused by watchdog time-out. The user needs to call
-* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out.
-*
-* The IsWdtExpired function can be used to check if the watchdog was the cause
-* of the last reset. In this situation, call Initialize then call IsWdtExpired.
-* If the result is true, watchdog timeout caused the last system reset. The
-* application then needs to clear the Reset flag.
-*
-* In timer mode, when the counter reaches 0, the Event flag is set in the
-* Interrupt status register and if interrupts are enabled, interrupt ID 30 is
-* set as pending in the interrupt distributor. The IsTimerExpired function
-* is used to check if the watchdog counter has decremented to 0 in timer mode.
-* If auto-reload mode is enabled, the Counter register is automatically reloaded
-* from the Load register.
-*
-* Initialization and Configuration
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate with the Watchdog Timer.
-*
-* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The
-* user needs to first call the XScuWdt_LookupConfig() API which returns
-* the Configuration structure pointer which is passed as a parameter to
-* the XScuWdt_CfgInitialize() API.
-*
-* Interrupts
-*
-* The SCU Watchdog Timer supports interrupts in Timer mode.
-*
-* This driver does not provide a Interrupt Service Routine (ISR) for the device.
-* It is the responsibility of the application to provide one if needed. Refer to
-* the interrupt example provided with this driver for details on using the
-* Timer in interrupt mode.
-*
-* Virtual Memory
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-* Threads
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* Asserts
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* Building the driver
-*
-* The XScuWdt driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-*
-*
-* NOTE:
-* The watchdog timer is not a part of the snoop control unit as indicated
-* by the prefix "scu" in the name of the driver.
-* It is an independent module in APU.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 2.3 mus 08/31/20 Updated makefile to support parallel make and
-* incremental builds. It would help to reduce compilaton
-* time.
-* 2.3 sne 09/16/20 Fixed MISRA-C violations.
-* 2.4 sne 02/04/21 Fixed Doxygen warnings.
-*
-*
-******************************************************************************/
-#ifndef XSCUWDT_H /**< prevent circular inclusions */
-#define XSCUWDT_H /**< by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xscuwdt_hw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddr; /**< Base address of the device */
-} XScuWdt_Config;
-
-/**
- * The XScuWdt driver instance data. The user is required to allocate a
- * variable of this type for every watchdog/timer device in the system.
- * A pointer to a variable of this type is then passed to the driver API
- * functions.
- */
-typedef struct {
- XScuWdt_Config Config;/**< Hardware Configuration */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStarted; /**< Device watchdog timer is running */
-} XScuWdt;
-
-/************************** Variable Definitions *****************************/
-extern XScuWdt_Config XScuWdt_ConfigTable[];
-
-/***************** Macros (Inline Functions) Definitions *********************/
-/****************************************************************************/
-/**
-*
-* This function is used to check if the watchdog has timed-out and the last
-* reset was caused by the watchdog reset.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return
-* - TRUE if the watchdog has expired.
-* - FALSE if the watchdog has not expired.
-*
-* @note C-style signature:
-* int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_IsWdtExpired(InstancePtr) \
- ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_RST_STS_OFFSET) & \
- XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
-
-/****************************************************************************/
-/**
-*
-* This function is used to check if the watchdog counter has reached 0 in timer
-* mode.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return
-* - TRUE if the watchdog has expired.
-* - FALSE if the watchdog has not expired.
-*
-* @note C-style signature:
-* int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_IsTimerExpired(InstancePtr) \
- ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_ISR_OFFSET) & \
- XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
-
-/****************************************************************************/
-/**
-*
-* Re-start the watchdog timer. This macro will read the watchdog load register
-* and write the same value to load register to update the counter register.
-* An application needs to call this function periodically to keep the watchdog
-* from asserting the WDRESETREQ reset request output pin.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_RestartWdt(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_RestartWdt(InstancePtr) \
- XScuWdt_LoadWdt((InstancePtr), \
- (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_LOAD_OFFSET)))
-
-/****************************************************************************/
-/**
-*
-* Write to the watchdog timer load register. This will also update the
-* watchdog counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-* @param Value is the value to be written to the Watchdog Load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value)
-*
-******************************************************************************/
-#define XScuWdt_LoadWdt(InstancePtr, Value) \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_LOAD_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the
-* Watchdog control register.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_SetWdMode(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_SetWdMode(InstancePtr) \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET, \
- (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET) | \
- (XSCUWDT_CONTROL_WD_MODE_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321
-* successively to the Watchdog Disable Register.
-* The software must write 0x12345678 and 0x87654321 successively to the
-* Watchdog Disable Register so that the watchdog mode bit in the Watchdog
-* Control Register is set to zero.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_SetTimerMode(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_SetTimerMode(InstancePtr) \
-{ \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_DISABLE_OFFSET, \
- XSCUWDT_DISABLE_VALUE1); \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_DISABLE_OFFSET, \
- XSCUWDT_DISABLE_VALUE2); \
-}
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the watchdog control register.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return Contents of the watchdog control register.
-*
-* @note C-style signature:
- u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_GetControlReg(InstancePtr) \
- XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the watchdog control register.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-* @param ControlReg is the value to be written to the watchdog control
-* register.
-*
-* @return None.
-*
-* @note C-style signature:
- void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg)
-*
-******************************************************************************/
-#define XScuWdt_SetControlReg(InstancePtr, ControlReg) \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET, (ControlReg))
-
-/****************************************************************************/
-/**
-*
-* Enable auto-reload mode.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_EnableAutoReload(InstancePtr) \
- XScuWdt_SetControlReg((InstancePtr), \
- (XScuWdt_GetControlReg(InstancePtr) | \
- XSCUWDT_CONTROL_AUTO_RELOAD_MASK))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Lookup configuration in xscuwdt_sinit.c.
- */
-XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId);
-
-/*
- * Selftest function in xscuwdt_selftest.c
- */
-s32 XScuWdt_SelfTest(XScuWdt *InstancePtr);
-
-/*
- * Interface functions in xscuwdt.c
- */
-s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
- XScuWdt_Config *ConfigPtr, u32 EffectiveAddress);
-
-void XScuWdt_Start(XScuWdt *InstancePtr);
-
-void XScuWdt_Stop(XScuWdt *InstancePtr);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5c/4123ad565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5c/4123ad565243001d18b399c1eb9b3628
deleted file mode 100644
index c3813e7..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5c/4123ad565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,524 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2006 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file pvr.h
-*
-* @addtogroup microblaze_pvr_macros Microblaze PVR access routines and macros
-*
-* MicroBlaze processor v5.00.a and later versions have configurable
-* Processor Version Registers (PVRs). The contents of the PVR are captured
-* using the pvr_t data structure, which is defined as an array of 32-bit words,
-* with each word corresponding to a PVR register on hardware. The number of PVR
-* words is determined by the number of PVRs configured in the hardware. You should
-* not attempt to access PVR registers that are not present in hardware, as the
-* pvr_t data structure is resized to hold only as many PVRs as are present in
-* hardware.
-* To access information in the PVR:
-* 1. Use the microblaze_get_pvr() function to populate the PVR data into a pvr_t
-* data structure.
-* 2. In subsequent steps, you can use any one of the PVR access macros list to
-* get individual data stored in the PVR.
-* 3. pvr.h header file must be included to source to use PVR macros.
-*
-* @{
-*
-******************************************************************************/
-/**
- *@cond nocomments
- */
-
-#ifndef _PVR_H
-#define _PVR_H
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xparameters.h"
-#include "mb_interface.h"
-#include "bspconfig.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Defs */
-typedef struct pvr_s {
-#ifdef MICROBLAZE_PVR_FULL
- unsigned int pvr[16];
-#else
- unsigned int pvr[1];
-#endif
-} pvr_t;
-
-
-#define getpvr(pvrid, val) asm volatile ("mfs\t%0,rpvr" stringify(pvrid) "\n\t" : "=d" (val))
-
-/* Basic PVR mask */
-#define MICROBLAZE_PVR0_PVR_FULL_MASK 0x80000000
-#define MICROBLAZE_PVR0_USE_BARREL_MASK 0x40000000
-#define MICROBLAZE_PVR0_USE_DIV_MASK 0x20000000
-#define MICROBLAZE_PVR0_USE_HW_MUL_MASK 0x10000000
-#define MICROBLAZE_PVR0_USE_FPU_MASK 0x08000000
-#define MICROBLAZE_PVR0_USE_EXCEPTION_MASK 0x04000000
-#define MICROBLAZE_PVR0_USE_ICACHE_MASK 0x02000000
-#define MICROBLAZE_PVR0_USE_DCACHE_MASK 0x01000000
-#define MICROBLAZE_PVR0_USE_MMU_MASK 0x00800000
-#define MICROBLAZE_PVR0_USE_BTC_MASK 0x00400000
-#define MICROBLAZE_PVR0_ENDIANNESS_MASK 0x00200000
-#define MICROBLAZE_PVR0_FAULT_TOLERANT_MASK 0x00100000
-#define MICROBLAZE_PVR0_STACK_PROTECTION_MASK 0x00080000
-#define MICROBLAZE_PVR0_MICROBLAZE_VERSION_MASK 0x0000FF00
-#define MICROBLAZE_PVR0_USER1_MASK 0x000000FF
-
-/* User 2 PVR mask */
-#define MICROBLAZE_PVR1_USER2_MASK 0xFFFFFFFF
-
-/* Configuration PVR masks */
-#define MICROBLAZE_PVR2_D_AXI_MASK 0x80000000
-#define MICROBLAZE_PVR2_D_LMB_MASK 0x40000000
-#define MICROBLAZE_PVR2_D_PLB_MASK 0x02000000
-#define MICROBLAZE_PVR2_I_AXI_MASK 0x20000000
-#define MICROBLAZE_PVR2_I_LMB_MASK 0x10000000
-#define MICROBLAZE_PVR2_I_PLB_MASK 0x01000000
-#define MICROBLAZE_PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
-#define MICROBLAZE_PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
-#define MICROBLAZE_PVR2_INTERCONNECT_MASK 0x00800000
-#define MICROBLAZE_PVR2_STREAM_INTERCONNECT_MASK 0x00400000
-#define MICROBLAZE_PVR2_USE_EXTENDED_FSL_INSTR_MASK 0x00080000
-#define MICROBLAZE_PVR2_USE_MSR_INSTR_MASK 0x00020000
-#define MICROBLAZE_PVR2_USE_PCMP_INSTR_MASK 0x00010000
-#define MICROBLAZE_PVR2_AREA_OPTIMIZED_MASK 0x00008000
-#define MICROBLAZE_PVR2_USE_BARREL_MASK 0x00004000
-#define MICROBLAZE_PVR2_USE_DIV_MASK 0x00002000
-#define MICROBLAZE_PVR2_USE_HW_MUL_MASK 0x00001000
-#define MICROBLAZE_PVR2_USE_FPU_MASK 0x00000800
-#define MICROBLAZE_PVR2_USE_FPU2_MASK 0x00000200
-#define MICROBLAZE_PVR2_USE_MUL64_MASK 0x00000400
-#define MICROBLAZE_PVR2_OPCODE_0x0_ILLEGAL_MASK 0x00000040
-#define MICROBLAZE_PVR2_UNALIGNED_EXCEPTION_MASK 0x00000020
-#define MICROBLAZE_PVR2_ILL_OPCODE_EXCEPTION_MASK 0x00000010
-#define MICROBLAZE_PVR2_M_AXI_I_BUS_EXCEPTION_MASK 0x00000008
-#define MICROBLAZE_PVR2_M_AXI_D_BUS_EXCEPTION_MASK 0x00000004
-#define MICROBLAZE_PVR2_IPLB_BUS_EXCEPTION_MASK 0x00000100
-#define MICROBLAZE_PVR2_DPLB_BUS_EXCEPTION_MASK 0x00000080
-#define MICROBLAZE_PVR2_DIV_ZERO_EXCEPTION_MASK 0x00000002
-#define MICROBLAZE_PVR2_FPU_EXCEPTION_MASK 0x00000001
-#define MICROBLAZE_PVR2_FSL_EXCEPTION_MASK 0x00040000
-
-/* Debug and exception PVR masks */
-#define MICROBLAZE_PVR3_DEBUG_ENABLED_MASK 0x80000000
-#define MICROBLAZE_PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
-#define MICROBLAZE_PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
-#define MICROBLAZE_PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
-#define MICROBLAZE_PVR3_FSL_LINKS_MASK 0x00000380
-#define MICROBLAZE_PVR3_BTC_SIZE_MASK 0x00000007
-
-/* ICache config PVR masks */
-#define MICROBLAZE_PVR4_USE_ICACHE_MASK 0x80000000
-#define MICROBLAZE_PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
-#define MICROBLAZE_PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
-#define MICROBLAZE_PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
-#define MICROBLAZE_PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
-#define MICROBLAZE_PVR4_ICACHE_ALWAYS_USED_MASK 0x00008000
-#define MICROBLAZE_PVR4_ICACHE_INTERFACE_MASK 0x00002000
-#define MICROBLAZE_PVR4_ICACHE_VICTIMS_MASK 0x00001C00
-#define MICROBLAZE_PVR4_ICACHE_STREAMS_MASK 0x00000300
-#define MICROBLAZE_PVR4_ICACHE_FORCE_TAG_LUTRAM_MASK 0x00000080
-#define MICROBLAZE_PVR4_ICACHE_DATA_WIDTH_MASK 0x00000040
-
-/* DCache config PVR masks */
-#define MICROBLAZE_PVR5_USE_DCACHE_MASK 0x80000000
-#define MICROBLAZE_PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
-#define MICROBLAZE_PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
-#define MICROBLAZE_PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
-#define MICROBLAZE_PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
-#define MICROBLAZE_PVR5_DCACHE_ALWAYS_USED_MASK 0x00008000
-#define MICROBLAZE_PVR5_DCACHE_USE_WRITEBACK_MASK 0x00004000
-#define MICROBLAZE_PVR5_DCACHE_INTERFACE_MASK 0x00002000
-#define MICROBLAZE_PVR5_DCACHE_VICTIMS_MASK 0x00001C00
-#define MICROBLAZE_PVR5_DCACHE_FORCE_TAG_LUTRAM_MASK 0x00000080
-#define MICROBLAZE_PVR5_DCACHE_DATA_WIDTH_MASK 0x00000040
-
-#if defined(__arch64__)
-/* ICache base address PVR mask */
-#define MICROBLAZE_PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFFFFFFFFFF
-
-/* ICache high address PVR mask */
-#define MICROBLAZE_PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFFFFFFFFFF
-
-/* DCache base address PVR mask */
-#define MICROBLAZE_PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFFFFFFFFFF
-
-/* DCache high address PVR mask */
-#define MICROBLAZE_PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFFFFFFFFFF
-
-#else
-/* ICache base address PVR mask */
-#define MICROBLAZE_PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
-
-/* ICache high address PVR mask */
-#define MICROBLAZE_PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
-
-/* DCache base address PVR mask */
-#define MICROBLAZE_PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
-
-/* DCache high address PVR mask */
-#define MICROBLAZE_PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
-#endif
-
-/* Target family PVR mask */
-#define MICROBLAZE_PVR10_TARGET_FAMILY_MASK 0xFF000000
-
-/* MSR Reset value PVR mask */
-#define MICROBLAZE_PVR11_MSR_RESET_VALUE_MASK 0x000007FF
-
-/* MMU value PVR mask */
-#define MICROBLAZE_PVR11_MMU_MASK 0xC0000000
-#define MICROBLAZE_PVR11_MMU_ITLB_SIZE_MASK 0x38000000
-#define MICROBLAZE_PVR11_MMU_DTLB_SIZE_MASK 0x07000000
-#define MICROBLAZE_PVR11_MMU_TLB_ACCESS_MASK 0x00C00000
-#define MICROBLAZE_PVR11_MMU_ZONES_MASK 0x003E0000
-#define MICROBLAZE_PVR11_MMU_PRIVILEGED_INSTR_MASK 0x00010000
-
-/**
- *@endcond
- */
-/* PVR access macros */
-
-/**
-Return non-zero integer if PVR is of type FULL, 0 if basic
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_IS_FULL(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_PVR_FULL_MASK)
-/**
-Return non-zero integer if hardware barrel shifter present.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_USE_BARREL(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_BARREL_MASK)
-/**
-Return non-zero integer if hardware divider present.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_USE_DIV(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_DIV_MASK)
-/**
-Return non-zero integer if hardware multiplier present.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_USE_HW_MUL(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_HW_MUL_MASK)
-/**
-Return non-zero integer if hardware floating point unit (FPU) present.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_USE_FPU(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_FPU_MASK)
-/**
-Return non-zero integer if I-cache present.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_USE_ICACHE(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_ICACHE_MASK)
-/**
-Return non-zero integer if D-cache present.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_USE_DCACHE(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_DCACHE_MASK)
-
-/**
- *@cond nocomments
- */
-#define MICROBLAZE_PVR_USE_MMU(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_MMU_MASK)
-#define MICROBLAZE_PVR_USE_BTC(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_BTC_MASK)
-#define MICROBLAZE_PVR_ENDIANNESS(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_ENDIANNESS_MASK)
-#define MICROBLAZE_PVR_FAULT_TOLERANT(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_FAULT_TOLERANT_MASK)
-#define MICROBLAZE_PVR_STACK_PROTECTION(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_STACK_PROTECTION_MASK)
-/**
-Return MicroBlaze processor version encoding. Refer to the MicroBlaze Processor
-Reference Guide (UG081) for mappings from encodings to actual hardware versions.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_MICROBLAZE_VERSION(_pvr) ((_pvr.pvr[0] & MICROBLAZE_PVR0_MICROBLAZE_VERSION_MASK) >> 8)
-/**
-Return the USER1 field stored in the PVR.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_USER1(_pvr) (_pvr.pvr[0] & MICROBLAZE_PVR0_USER1_MASK)
-
-/**
-Return the USER2 field stored in the PVR.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_USER2(_pvr) (_pvr.pvr[1] & MICROBLAZE_PVR1_USER2_MASK)
-
-#define MICROBLAZE_PVR_D_AXI(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_D_AXI_MASK)
-
-/**
-Return non-zero integer if Data Side PLB
-interface is present.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_D_LMB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_D_LMB_MASK)
-
-/**
-Return non-zero integer if Data Side PLB interface is present.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_D_PLB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_D_PLB_MASK)
-
-#define MICROBLAZE_PVR_I_AXI(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_I_AXI_MASK)
-
-/**
-Return non-zero integer if Instruction Side Local Memory Bus (LMB) interface present.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_I_LMB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_I_LMB_MASK)
-
-/**
-Return non-zero integer if Instruction Side PLB interface present.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_I_PLB(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_I_PLB_MASK)
-
-/**
-Return non-zero integer if interrupts are configured as edge-triggered.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_INTERRUPT_IS_EDGE(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_INTERRUPT_IS_EDGE_MASK)
-
-/**
-Return non-zero integer if interrupts are configured as positive edge triggered.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_EDGE_IS_POSITIVE(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_EDGE_IS_POSITIVE_MASK)
-
-/**
-Return non-zero if MicroBlaze processor has PLB interconnect; otherwise return zero.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_INTERCONNECT(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_INTERCONNECT_MASK)
-
-#define MICROBLAZE_PVR_STREAM_INTERCONNECT(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_STREAM_INTERCONNECT_MASK)
-#define MICROBLAZE_PVR_USE_EXTENDED_FSL_INSTR(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_EXTENDED_FSL_INSTR_MASK)
-#define MICROBLAZE_PVR_USE_MSR_INSTR(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_MSR_INSTR_MASK)
-#define MICROBLAZE_PVR_USE_PCMP_INSTR(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_PCMP_INSTR_MASK)
-#define MICROBLAZE_PVR_AREA_OPTIMIZED(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_AREA_OPTIMIZED_MASK)
-
-/**
-Return non-zero integer if MicroBlaze processor supports 64-bit products for
-multiplies.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_USE_MUL64(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_MUL64_MASK)
-
-/**
-Return non-zero integer if opcode 0x0 is treated as an illegal opcode.
-multiplies.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_OPCODE_0x0_ILLEGAL(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_OPCODE_0x0_ILLEGAL_MASK)
-
-/**
-Return non-zero integer if unaligned exceptions are supported.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_UNALIGNED_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_UNALIGNED_EXCEPTION_MASK)
-
-/**
-Return non-zero integer if illegal opcode exceptions are supported.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_ILL_OPCODE_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_ILL_OPCODE_EXCEPTION_MASK)
-
-#define MICROBLAZE_PVR_M_AXI_I_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_M_AXI_I_BUS_EXCEPTION_MASK)
-
-/**
-Return non-zero integer if I-PLB exceptions are supported.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_IPLB_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_IPLB_BUS_EXCEPTION_MASK)
-
-#define MICROBLAZE_PVR_M_AXI_D_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_M_AXI_D_BUS_EXCEPTION_MASK)
-
-/**
-Return non-zero integer if I-PLB exceptions are supported.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_DPLB_BUS_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_DPLB_BUS_EXCEPTION_MASK)
-
-/**
-Return non-zero integer if divide by zero exceptions are supported.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_DIV_ZERO_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_DIV_ZERO_EXCEPTION_MASK)
-
-/**
-Return non-zero integer if FPU exceptions are supported.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_FPU_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_FPU_EXCEPTION_MASK)
-
-/**
-Return non-zero integer if FSL exceptions are present.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_FSL_EXCEPTION(_pvr) (_pvr.pvr[2] & MICROBLAZE_PVR2_FSL_EXCEPTION_MASK)
-
-/**
-Return non-zero integer if debug is enabled.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_DEBUG_ENABLED(_pvr) (_pvr.pvr[3] & MICROBLAZE_PVR3_DEBUG_ENABLED_MASK)
-
-/**
-Return the number of hardware PC breakpoints available.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_NUMBER_OF_PC_BRK(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_PC_BRK_MASK) >> 25)
-
-/**
-Return the number of read address hardware watchpoints supported.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_NUMBER_OF_RD_ADDR_BRK(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19)
-
-/**
-Return the number of write address hardware watchpoints supported.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_NUMBER_OF_WR_ADDR_BRK(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13)
-
-/**
-Return the number of FSL links present.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_FSL_LINKS(_pvr) ((_pvr.pvr[3] & MICROBLAZE_PVR3_FSL_LINKS_MASK) >> 7)
-#define MICROBLAZE_PVR_BTC_SIZE(_pvr) (_pvr.pvr[3] & MICROBLAZE_PVR3_BTC_SIZE_MASK)
-
-/**
-Return the number of address tag bits for the I-cache.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_ICACHE_ADDR_TAG_BITS(_pvr) ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26)
-
-/**
-Return non-zero if writes to I-caches are allowed.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_ICACHE_ALLOW_WR(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ALLOW_WR_MASK)
-
-/**
-Return the length of each I-cache line in bytes.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_ICACHE_LINE_LEN(_pvr) (1 << ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_LINE_LEN_MASK) >> 21))
-
-/**
-Return the size of the D-cache in bytes.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_ICACHE_BYTE_SIZE(_pvr) (1 << ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_BYTE_SIZE_MASK) >> 16))
-
-#define MICROBLAZE_PVR_ICACHE_ALWAYS_USED(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ALWAYS_USED_MASK)
-#define MICROBLAZE_PVR_ICACHE_INTERFACE(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_INTERFACE_MASK)
-#define MICROBLAZE_PVR_ICACHE_VICTIMS(_pvr) ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_VICTIMS_MASK) >> 10)
-#define MICROBLAZE_PVR_ICACHE_STREAMS(_pvr) ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_STREAMS_MASK) >> 8)
-#define MICROBLAZE_PVR_ICACHE_FORCE_TAG_LUTRAM(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_FORCE_TAG_LUTRAM_MASK)
-#define MICROBLAZE_PVR_ICACHE_DATA_WIDTH(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_DATA_WIDTH_MASK)
-
-/**
-Return the number of address tag bits for the D-cache.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_DCACHE_ADDR_TAG_BITS(_pvr) ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26)
-
-/**
-Return non-zero if writes to D-cache are allowed.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_DCACHE_ALLOW_WR(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ALLOW_WR_MASK)
-
-/**
-Return the length of each line in the D-cache in bytes.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_DCACHE_LINE_LEN(_pvr) (1 << ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_LINE_LEN_MASK) >> 21))
-
-/**
-Return the size of the D-cache in bytes.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_DCACHE_BYTE_SIZE(_pvr) (1 << ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
-
-
-#define MICROBLAZE_PVR_DCACHE_ALWAYS_USED(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ALWAYS_USED_MASK)
-#define MICROBLAZE_PVR_DCACHE_USE_WRITEBACK(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_USE_WRITEBACK_MASK)
-#define MICROBLAZE_PVR_DCACHE_INTERFACE(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_INTERFACE_MASK)
-#define MICROBLAZE_PVR_DCACHE_VICTIMS(_pvr) ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_VICTIMS_MASK) >> 10)
-#define MICROBLAZE_PVR_DCACHE_FORCE_TAG_LUTRAM(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_FORCE_TAG_LUTRAM_MASK)
-#define MICROBLAZE_PVR_DCACHE_DATA_WIDTH(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_DATA_WIDTH_MASK)
-
-/**
-Return the base address of the I-cache.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_ICACHE_BASEADDR(_pvr) (_pvr.pvr[6] & MICROBLAZE_PVR6_ICACHE_BASEADDR_MASK)
-
-/**
-Return the high address of the I-cache.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_ICACHE_HIGHADDR(_pvr) (_pvr.pvr[7] & MICROBLAZE_PVR7_ICACHE_HIGHADDR_MASK)
-
-/**
-Return the base address of the D-cache.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_DCACHE_BASEADDR(_pvr) (_pvr.pvr[8] & MICROBLAZE_PVR8_DCACHE_BASEADDR_MASK)
-
-/**
-Return the high address of the D-cache.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_DCACHE_HIGHADDR(_pvr) (_pvr.pvr[9] & MICROBLAZE_PVR9_DCACHE_HIGHADDR_MASK)
-
-/**
-Return the encoded target family identifier.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_TARGET_FAMILY(_pvr) ((_pvr.pvr[10] & MICROBLAZE_PVR10_TARGET_FAMILY_MASK) >> 24)
-
-/**
-Refer to the MicroBlaze Processor Reference Guide (UG081) for mappings from encodings
-to target family name strings.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_MSR_RESET_VALUE(_pvr) (_pvr.pvr[11] & MICROBLAZE_PVR11_MSR_RESET_VALUE_MASK)
-
-/**
-Returns the value of C_USE_MMU. Refer to the MicroBlaze Processor Reference Guide
-(UG081) for mappings from MMU type values to MMU function.
-@param _pvr pvr data structure
-*/
-#define MICROBLAZE_PVR_MMU_TYPE(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_MASK) >> 30)
-#define MICROBLAZE_PVR_MMU_ITLB_SIZE(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_ITLB_SIZE_MASK) >> 27)
-#define MICROBLAZE_PVR_MMU_DTLB_SIZE(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_DTLB_SIZE_MASK) >> 24)
-#define MICROBLAZE_PVR_MMU_TLB_ACCESS(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_TLB_ACCESS_MASK) >> 22)
-#define MICROBLAZE_PVR_MMU_ZONES(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_ZONES_MASK) >> 17)
-#define MICROBLAZE_PVR_MMU_PRIVILEGED_INSTR(_pvr) ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_PRIVILEGED_INSTR_MASK) >> 16)
-
-/* Protos */
-/**
- *@endcond
- */
-int microblaze_get_pvr (pvr_t *pvr);
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* _PVR_H */
-
-/**
-* @} End of "addtogroup microblaze_pvr_macros".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5c/80b670565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5c/80b670565243001d18b399c1eb9b3628
deleted file mode 100644
index 2668199..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5c/80b670565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,3 +0,0 @@
-LIBSOURCES = *.c *.S
-PROFILE_ARCH_OBJS = profile_mcount_arm.o
-LIBS = standalone_libs
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5c/819a39595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5c/819a39595243001d18b399c1eb9b3628
deleted file mode 100644
index d6bc637..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5c/819a39595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,47 +0,0 @@
-/******************************************************************************/
-/**
-* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-* @file xil_mem.h
-*
-* @addtogroup common_mem_operation_api Customized APIs for Memory Operations
-*
-* The xil_mem.h file contains prototype for functions related
-* to memory operations. These APIs are applicable for all processors supported
-* by Xilinx.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.1 nsk 11/07/16 First release.
-* 7.0 mus 01/07/19 Add cpp extern macro
-*
-*
-*
-*****************************************************************************/
-#ifndef XIL_MEM_H /* prevent circular inclusions */
-#define XIL_MEM_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Function Prototypes *****************************/
-
-void Xil_MemCpy(void* dst, const void* src, u32 cnt);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_MEM_H */
-/**
-* @} End of "addtogroup common_mem_operation_api".
-*/
\ No newline at end of file
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5c/b225e9575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5c/b225e9575243001d18b399c1eb9b3628
deleted file mode 100644
index 9397afc..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5c/b225e9575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,61 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/******************************************************************************/
-/**
-* @file xgpio_i.h
-* @addtogroup gpio_v4_8
-* @{
-*
-* This header file contains internal identifiers, which are those shared
-* between the files of the driver. It is intended for internal use only.
-*
-* NOTES:
-*
-* None.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 03/13/02 First release
-* 2.11a mta 03/21/07 Updated to new coding style
-*
-******************************************************************************/
-
-#ifndef XGPIO_I_H /* prevent circular inclusions */
-#define XGPIO_I_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xgpio.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions ****************************/
-
-extern XGpio_Config XGpio_ConfigTable[];
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5d/003252565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5d/003252565243001d18b399c1eb9b3628
deleted file mode 100644
index 29be8d2..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5d/003252565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,73 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#ifndef XDEBUG
-#define XDEBUG
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(DEBUG) && !defined(NDEBUG)
-
-#ifndef XDEBUG_WARNING
-#define XDEBUG_WARNING
-#warning DEBUG is enabled
-#endif
-
-int printf(const char *format, ...);
-
-#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */
-#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */
-#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */
-
-#define XDBG_DEBUG_FIFO_REG 0x00000100U /* display register reads/writes */
-#define XDBG_DEBUG_FIFO_RX 0x00000101U /* receive debug messages */
-#define XDBG_DEBUG_FIFO_TX 0x00000102U /* transmit debug messages */
-#define XDBG_DEBUG_FIFO_ALL 0x0000010FU /* all fifo debug messages */
-
-#define XDBG_DEBUG_TEMAC_REG 0x00000400U /* display register reads/writes */
-#define XDBG_DEBUG_TEMAC_RX 0x00000401U /* receive debug messages */
-#define XDBG_DEBUG_TEMAC_TX 0x00000402U /* transmit debug messages */
-#define XDBG_DEBUG_TEMAC_ALL 0x0000040FU /* all temac debug messages */
-
-#define XDBG_DEBUG_TEMAC_ADPT_RX 0x00000800U /* receive debug messages */
-#define XDBG_DEBUG_TEMAC_ADPT_TX 0x00000801U /* transmit debug messages */
-#define XDBG_DEBUG_TEMAC_ADPT_IOCTL 0x00000802U /* ioctl debug messages */
-#define XDBG_DEBUG_TEMAC_ADPT_MISC 0x00000803U /* debug msg for other routines */
-#define XDBG_DEBUG_TEMAC_ADPT_ALL 0x0000080FU /* all temac adapter debug messages */
-
-
-#define xdbg_current_types (XDBG_DEBUG_GENERAL | XDBG_DEBUG_ERROR | XDBG_DEBUG_TEMAC_REG | XDBG_DEBUG_FIFO_RX | XDBG_DEBUG_FIFO_TX | XDBG_DEBUG_FIFO_REG)
-
-#define xdbg_stmnt(x) x
-
-/* In VxWorks, if _WRS_GNU_VAR_MACROS is defined, special syntax is needed for
- * macros that accept variable number of arguments
- */
-#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
-#define xdbg_printf(type, args...) (((type) & xdbg_current_types) ? printf (## args) : 0)
-#else /* ANSI Syntax */
-#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
-#endif
-
-#else /* defined(DEBUG) && !defined(NDEBUG) */
-
-#define xdbg_stmnt(x)
-
-/* See VxWorks comments above */
-#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
-#define xdbg_printf(type, args...)
-#else /* ANSI Syntax */
-#define xdbg_printf(...)
-#endif
-#endif /* defined(DEBUG) && !defined(NDEBUG) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XDEBUG */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5d/318b39545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5d/318b39545243001d18b399c1eb9b3628
deleted file mode 100644
index a146f83..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5d/318b39545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,387 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_exception.h
-*
-* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
-* For exception related functions that can be used across all Xilinx supported
-* processors, please use xil_exception.h.
-*
-* @addtogroup arm_exception_apis ARM Processor Exception Handling
-* @{
-* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
-* utilized for enabling/disabling IRQ, registering/removing handler for
-* exceptions or initializing exception vector table with null handler.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
-* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler.
-* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.
-* 7.0 mus 01/03/19 Tweak Xil_ExceptionEnableMask and
-* Xil_ExceptionDisableMask macros to support legacy
-* examples for Cortexa72 EL3 exception level.
-* 7.3 mus 04/15/20 Added Xil_EnableNestedInterrupts and
-* Xil_DisableNestedInterrupts macros for ARMv8.
-* For Cortexa72, these macro's would not be supported
-* at EL3, as Cortexa72 is using GIC-500(GICv3), which
-* triggeres only FIQ at EL3. Fix for CR#1062506
-# 7.6 mus 09/17/21 Updated flag checking to fix warning reported with
-# -Wundef compiler option CR#1110261
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
-#define XIL_EXCEPTION_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#include "bspconfig.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions ****************************/
-
-#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
-#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
-#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
-
-#define XIL_EXCEPTION_ID_FIRST 0U
-#if defined (__aarch64__)
-#define XIL_EXCEPTION_ID_SYNC_INT 1U
-#define XIL_EXCEPTION_ID_IRQ_INT 2U
-#define XIL_EXCEPTION_ID_FIQ_INT 3U
-#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
-#define XIL_EXCEPTION_ID_LAST 5U
-#else
-#define XIL_EXCEPTION_ID_RESET 0U
-#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
-#define XIL_EXCEPTION_ID_SWI_INT 2U
-#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
-#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
-#define XIL_EXCEPTION_ID_IRQ_INT 5U
-#define XIL_EXCEPTION_ID_FIQ_INT 6U
-#define XIL_EXCEPTION_ID_LAST 6U
-#endif
-
-/*
- * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
- */
-#if defined (versal) && !defined(ARMR5) && EL3
-#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_FIQ_INT
-#else
-#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
-#endif
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef is the exception handler function.
- */
-typedef void (*Xil_ExceptionHandler)(void *data);
-typedef void (*Xil_InterruptHandler)(void *data);
-
-/**
-*@endcond
-*/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* @brief Enable Exceptions.
-*
-* @param Mask: Value for enabling the exceptions.
-*
-* @return None.
-*
-* @note If bit is 0, exception is enabled.
-* C-Style signature: void Xil_ExceptionEnableMask(Mask)
-*
-******************************************************************************/
-#if defined (versal) && !defined(ARMR5) && EL3
-/*
- * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
- * only FIQ at EL3. Hence, tweaking this macro to always enable FIQ
- * ignoring argument passed by user.
- */
-#define Xil_ExceptionEnableMask(Mask) \
- mtcpsr(mfcpsr() & ~ ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
-#elif defined (__GNUC__) || defined (__ICCARM__)
-#define Xil_ExceptionEnableMask(Mask) \
- mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
-#else
-#define Xil_ExceptionEnableMask(Mask) \
- { \
- register u32 Reg __asm("cpsr"); \
- mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
- }
-#endif
-/****************************************************************************/
-/**
-* @brief Enable the IRQ exception.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-#if defined (versal) && !defined(ARMR5) && EL3
-#define Xil_ExceptionEnable() \
- Xil_ExceptionEnableMask(XIL_EXCEPTION_FIQ)
-#else
-#define Xil_ExceptionEnable() \
- Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
-#endif
-
-/****************************************************************************/
-/**
-* @brief Disable Exceptions.
-*
-* @param Mask: Value for disabling the exceptions.
-*
-* @return None.
-*
-* @note If bit is 1, exception is disabled.
-* C-Style signature: Xil_ExceptionDisableMask(Mask)
-*
-******************************************************************************/
-#if defined (versal) && !defined(ARMR5) && EL3
-/*
- * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
- * only FIQ at EL3. Hence, tweaking this macro to always disable FIQ
- * ignoring argument passed by user.
- */
-#define Xil_ExceptionDisableMask(Mask) \
- mtcpsr(mfcpsr() | ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
-#elif defined (__GNUC__) || defined (__ICCARM__)
-#define Xil_ExceptionDisableMask(Mask) \
- mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
-#else
-#define Xil_ExceptionDisableMask(Mask) \
- { \
- register u32 Reg __asm("cpsr"); \
- mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
- }
-#endif
-/****************************************************************************/
-/**
-* Disable the IRQ exception.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_ExceptionDisable() \
- Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
-
-#if ( defined (PLATFORM_ZYNQMP) && defined (EL3) && (EL3==1) )
-/****************************************************************************/
-/**
-* @brief Enable nested interrupts by clearing the I bit in DAIF.This
-* macro is defined for Cortex-A53 64 bit mode BSP configured to run
-* at EL3.. However,it is not defined for Versal Cortex-A72 BSP
-* configured to run at EL3. Reason is, Cortex-A72 is coupled
-* with GIC-500(GICv3 specifications) and it triggers only FIQ at EL3.
-*
-* @return None.
-*
-* @note This macro is supposed to be used from interrupt handlers. In the
-* interrupt handler the interrupts are disabled by default (I bit
-* is set as 1). To allow nesting of interrupts, this macro should be
-* used. It clears the I bit. Once that bit is cleared and provided the
-* preemption of interrupt conditions are met in the GIC, nesting of
-* interrupts will start happening.
-* Caution: This macro must be used with caution. Before calling this
-* macro, the user must ensure that the source of the current IRQ
-* is appropriately cleared. Otherwise, as soon as we clear the I
-* bit, there can be an infinite loop of interrupts with an
-* eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
- __asm__ __volatile__ ("mrs X1, ELR_EL3"); \
- __asm__ __volatile__ ("mrs X2, SPSR_EL3"); \
- __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-/****************************************************************************/
-/**
-* @brief Disable the nested interrupts by setting the I bit in DAIF. This
-* macro is defined for Cortex-A53 64 bit mode BSP configured to run
-* at EL3.
-*
-* @return None.
-*
-* @note This macro is meant to be called in the interrupt service routines.
-* This macro cannot be used independently. It can only be used when
-* nesting of interrupts have been enabled by using the macro
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-* point. The user then must call this macro before exiting the interrupt
-* service routine. This macro puts the ARM back in IRQ mode and
-* hence sets back the I bit.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
- __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \
- __asm__ __volatile__ ("msr ELR_EL3, X1"); \
- __asm__ __volatile__ ("msr SPSR_EL3, X2"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-#elif (defined (EL1_NONSECURE) && (EL1_NONSECURE==1))
-/****************************************************************************/
-/**
-* @brief Enable nested interrupts by clearing the I bit in DAIF.This
-* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit
-* BSP configured to run at EL1 NON SECURE
-*
-* @return None.
-*
-* @note This macro is supposed to be used from interrupt handlers. In the
-* interrupt handler the interrupts are disabled by default (I bit
-* is set as 1). To allow nesting of interrupts, this macro should be
-* used. It clears the I bit. Once that bit is cleared and provided the
-* preemption of interrupt conditions are met in the GIC, nesting of
-* interrupts will start happening.
-* Caution: This macro must be used with caution. Before calling this
-* macro, the user must ensure that the source of the current IRQ
-* is appropriately cleared. Otherwise, as soon as we clear the I
-* bit, there can be an infinite loop of interrupts with an
-* eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
- __asm__ __volatile__ ("mrs X1, ELR_EL1"); \
- __asm__ __volatile__ ("mrs X2, SPSR_EL1"); \
- __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-/****************************************************************************/
-/**
-* @brief Disable the nested interrupts by setting the I bit in DAIF. This
-* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit
-* BSP configured to run at EL1 NON SECURE
-*
-* @return None.
-*
-* @note This macro is meant to be called in the interrupt service routines.
-* This macro cannot be used independently. It can only be used when
-* nesting of interrupts have been enabled by using the macro
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-* point. The user then must call this macro before exiting the interrupt
-* service routine. This macro puts the ARM back in IRQ mode and
-* hence sets back the I bit.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
- __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \
- __asm__ __volatile__ ("msr ELR_EL1, X1"); \
- __asm__ __volatile__ ("msr SPSR_EL1, X2"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-#elif (!defined (__aarch64__) && !defined (ARMA53_32))
-/****************************************************************************/
-/**
-* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This
-* API is defined for cortex-a9 and cortex-r5.
-*
-* @return None.
-*
-* @note This macro is supposed to be used from interrupt handlers. In the
-* interrupt handler the interrupts are disabled by default (I and F
-* are 1). To allow nesting of interrupts, this macro should be
-* used. It clears the I and F bits by changing the ARM mode to
-* system mode. Once these bits are cleared and provided the
-* preemption of interrupt conditions are met in the GIC, nesting of
-* interrupts will start happening.
-* Caution: This macro must be used with caution. Before calling this
-* macro, the user must ensure that the source of the current IRQ
-* is appropriately cleared. Otherwise, as soon as we clear the I and
-* F bits, there can be an infinite loop of interrupts with an
-* eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
- __asm__ __volatile__ ("stmfd sp!, {lr}"); \
- __asm__ __volatile__ ("mrs lr, spsr"); \
- __asm__ __volatile__ ("stmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
- __asm__ __volatile__ ("stmfd sp!, {lr}");
-/****************************************************************************/
-/**
-* @brief Disable the nested interrupts by setting the I and F bits. This API
-* is defined for cortex-a9 and cortex-r5.
-*
-* @return None.
-*
-* @note This macro is meant to be called in the interrupt service routines.
-* This macro cannot be used independently. It can only be used when
-* nesting of interrupts have been enabled by using the macro
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-* point. The user then must call this macro before exiting the interrupt
-* service routine. This macro puts the ARM back in IRQ/FIQ mode and
-* hence sets back the I and F bits.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr cpsr_c, #0x92"); \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr spsr_cxsf, lr"); \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
-
-#endif
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler Handler,
- void *Data);
-
-extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
-extern void Xil_GetExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler *Handler, void **Data);
-
-extern void Xil_ExceptionInit(void);
-#if defined (__aarch64__)
-void Xil_SyncAbortHandler(void *CallBackRef);
-void Xil_SErrorAbortHandler(void *CallBackRef);
-#else
-extern void Xil_DataAbortHandler(void *CallBackRef);
-extern void Xil_PrefetchAbortHandler(void *CallBackRef);
-extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
-#endif
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_EXCEPTION_H */
-/**
-* @} End of "addtogroup arm_exception_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5d/9026bb595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5d/9026bb595243001d18b399c1eb9b3628
deleted file mode 100644
index 379023c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5d/9026bb595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,154 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xl2cc.h
-*
-* This file contains the address definitions for the PL310 Level-2 Cache
-* Controller.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 02/01/10 Initial version
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef _XL2CC_H_
-#define _XL2CC_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-/* L2CC Register Offsets */
-#define XPS_L2CC_ID_OFFSET 0x0000U
-#define XPS_L2CC_TYPE_OFFSET 0x0004U
-#define XPS_L2CC_CNTRL_OFFSET 0x0100U
-#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104U
-#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108U
-#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010CU
-
-#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200U
-#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204U
-#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208U
-#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020CU
-#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210U
-
-#define XPS_L2CC_IER_OFFSET 0x0214U /* Interrupt Mask */
-#define XPS_L2CC_IPR_OFFSET 0x0218U /* Masked interrupt status */
-#define XPS_L2CC_ISR_OFFSET 0x021CU /* Raw Interrupt Status */
-#define XPS_L2CC_IAR_OFFSET 0x0220U /* Interrupt Clear */
-
-#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730U /* Cache Sync */
-#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740U /* Dummy Register for Cache Sync */
-#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770U /* Cache Invalid by PA */
-#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077CU /* Cache Invalid by Way */
-#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0U /* Cache Clean by PA */
-#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8U /* Cache Clean by Index */
-#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BCU /* Cache Clean by Way */
-#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0U /* Cache Invalidate and Clean by PA */
-#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8U /* Cache Invalidate and Clean by Index */
-#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FCU /* Cache Invalidate and Clean by Way */
-
-#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900U /* Cache Data Lockdown 0 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904U /* Cache Instruction Lockdown 0 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908U /* Cache Data Lockdown 1 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090CU /* Cache Instruction Lockdown 1 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910U /* Cache Data Lockdown 2 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914U /* Cache Instruction Lockdown 2 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918U /* Cache Data Lockdown 3 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091CU /* Cache Instruction Lockdown 3 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920U /* Cache Data Lockdown 4 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924U /* Cache Instruction Lockdown 4 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928U /* Cache Data Lockdown 5 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092CU /* Cache Instruction Lockdown 5 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930U /* Cache Data Lockdown 6 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934U /* Cache Instruction Lockdown 6 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938U /* Cache Data Lockdown 7 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093CU /* Cache Instruction Lockdown 7 by Way */
-
-#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U /* Cache Lockdown Line Enable */
-#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954U /* Cache Unlock All Lines by Way */
-
-#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00U /* Start of address filtering */
-#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04U /* Start of address filtering */
-
-#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40U /* Debug Control Register */
-
-/* XPS_L2CC_CNTRL_OFFSET bit masks */
-#define XPS_L2CC_ENABLE_MASK 0x00000001U /* enables the L2CC */
-
-/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */
-#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000U /* Early BRESP Enable */
-#define XPS_L2CC_AUX_IPFE_MASK 0x20000000U /* Instruction Prefetch Enable */
-#define XPS_L2CC_AUX_DPFE_MASK 0x10000000U /* Data Prefetch Enable */
-#define XPS_L2CC_AUX_NSIC_MASK 0x08000000U /* Non-secure interrupt access control */
-#define XPS_L2CC_AUX_NSLE_MASK 0x04000000U /* Non-secure lockdown enable */
-#define XPS_L2CC_AUX_CRP_MASK 0x02000000U /* Cache replacement policy */
-#define XPS_L2CC_AUX_FWE_MASK 0x01800000U /* Force write allocate */
-#define XPS_L2CC_AUX_SAOE_MASK 0x00400000U /* Shared attribute override enable */
-#define XPS_L2CC_AUX_PE_MASK 0x00200000U /* Parity enable */
-#define XPS_L2CC_AUX_EMBE_MASK 0x00100000U /* Event monitor bus enable */
-#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000U /* Way-size */
-#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000U /* Associativity */
-#define XPS_L2CC_AUX_SAIE_MASK 0x00002000U /* Shared attribute invalidate enable */
-#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000U /* Exclusive cache configuration */
-#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800U /* Store buffer device limitation Enable */
-#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400U /* High Priority for SO and Dev Reads Enable */
-#define XPS_L2CC_AUX_FLZE_MASK 0x00000001U /* Full line of zero enable */
-
-#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000U /* Enable all prefetching, */
- /* Cache replacement policy, Parity enable, */
- /* Event monitor bus enable and Way Size (64 KB) */
-#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFFU /* */
-
-#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111U /* latency for TAG RAM */
-#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121U /* latency for DATA RAM */
-
-/* Interrupt bit masks */
-#define XPS_L2CC_IXR_DECERR_MASK 0x00000100U /* DECERR from L3 */
-#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080U /* SLVERR from L3 */
-#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040U /* Error on L2 data RAM (Read) */
-#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020U /* Error on L2 tag RAM (Read) */
-#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010U /* Error on L2 data RAM (Write) */
-#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008U /* Error on L2 tag RAM (Write) */
-#define XPS_L2CC_IXR_PARRD_MASK 0x00000004U /* Parity Error on L2 data RAM (Read) */
-#define XPS_L2CC_IXR_PARRT_MASK 0x00000002U /* Parity Error on L2 tag RAM (Read) */
-#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001U /* Event Counter1/0 Overflow Increment */
-
-/* Address filtering mask and enable bit */
-#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000U /* Address filtering valid bits*/
-#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U /* Address filtering enable bit*/
-
-/* Debug control bits */
-#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004U /* Debug SPIDEN bit */
-#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002U /* Debug DWB bit, forces write through */
-#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002U /* Debug DCL bit, disables cache line fill */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* protection macro */
-
-/**
- *@endcond
- */
\ No newline at end of file
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5d/a042ba565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5d/a042ba565243001d18b399c1eb9b3628
deleted file mode 100644
index 926da80..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5d/a042ba565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,21 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include "profile.h"
-#include "_profile_timer_hw.h"
-#include "xil_exception.h"
-
-void _profile_clean( void );
-
-/*
- * This function is the exit routine and is called by the crtinit, when the
- * program terminates. The name needs to be changed later..
- */
-void _profile_clean( void )
-{
- Xil_ExceptionDisable();
- disable_timer();
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5d/d086c5595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5d/d086c5595243001d18b399c1eb9b3628
deleted file mode 100644
index 5feeb49..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5d/d086c5595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,39 +0,0 @@
-DRIVER_LIB_VERSION = 1.0
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I$(INCLUDEDIR)
-
-SRCFILES:=$(wildcard *.c)
-
-OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
-
-libs: $(OBJECTS)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf $(DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5d/f06a3c575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5d/f06a3c575243001d18b399c1eb9b3628
deleted file mode 100644
index f91ffce..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5d/f06a3c575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,135 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file image_mover.h
-*
-* This file contains the interface for moving the image from FLASH to OCM
-
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a jz 03/04/11 Initial release
-* 2.00a jz 06/04/11 partition header expands to 12 words
-* 5.00a kc 07/30/13 Added defines for image header information
-* 8.00a kc 01/16/13 Added defines for partition owner attribute
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 3.00a np/mb 10/08/12 Initial release
-* Corrected the prototype
-*
-*
-*
-* @note
-*
-******************************************************************************/
-#ifndef FSBL_HOOKS_H_
-#define FSBL_HOOKS_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "fsbl.h"
-
-
-/************************** Function Prototypes ******************************/
-
-/* FSBL hook function which is called before bitstream download */
-u32 FsblHookBeforeBitstreamDload(void);
-
-/* FSBL hook function which is called after bitstream download */
-u32 FsblHookAfterBitstreamDload(void);
-
-/* FSBL hook function which is called before handoff to the application */
-u32 FsblHookBeforeHandoff(void);
-
-/* FSBL hook function which is called in FSBL fallback */
-void FsblHookFallback(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5e/007b9c595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5e/007b9c595243001d18b399c1eb9b3628
deleted file mode 100644
index 77e1f3d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5e/007b9c595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,74 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache_vxworks.h
-*
-* Contains the cache related functions for VxWorks that is wrapped by
-* xil_cache.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 12/11/09 Initial release
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 01/12/12 Initial version
-* 4.2 pkp 07/21/14 Included xil_types.h file which contains definition for
-* u32 which resolves issue of CR#805869
-* 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-*
-*
-******************************************************************************/
-
-/**
-*@cond nocomments
-*/
-
-#ifndef XIL_MMU_H
-#define XIL_MMU_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/* Memory type */
-#define NORM_NONCACHE 0x11DE2 /* Normal Non-cacheable */
-#define STRONG_ORDERED 0xC02 /* Strongly ordered */
-#define DEVICE_MEMORY 0xC06 /* Device memory */
-#define RESERVED 0x0 /* reserved memory */
-
-/* Normal write-through cacheable shareable */
-#define NORM_WT_CACHE 0x16DEA
-
-/* Normal write back cacheable shareable */
-#define NORM_WB_CACHE 0x15DE6
-
-/* shareability attribute */
-#define SHAREABLE (0x1 << 16)
-#define NON_SHAREABLE (~(0x1 << 16))
-
-/* Execution type */
-#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0))
-
-/**
-*@endcond
-*/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
-void Xil_EnableMMU(void);
-void Xil_DisableMMU(void);
-void* Xil_MemMap(UINTPTR PhysAddr, size_t size, u32 flags);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_MMU_H */
-/**
-* @} End of "addtogroup a9_mmu_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5e/b04446595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5e/b04446595243001d18b399c1eb9b3628
deleted file mode 100644
index 14446f4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5e/b04446595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,143 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xplatform_info.c
-* @addtogroup common_platform_info Hardware Platform Information
-* @{
-* This file contains information about hardware for which the code is built
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 5.00 pkp 12/15/14 Initial release
-* 5.04 pkp 01/12/16 Added platform information support for Cortex-A53 32bit
-* mode
-* 6.00 mus 17/08/16 Removed unused variable from XGetPlatform_Info
-* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
-* function for PMUFW.
-* ms 06/13/17 Added PSU_PMU macro to provide support of
-* XGetPlatform_Info function for PMUFW.
-* mus 08/17/17 Add EL1 NS mode support for
-* XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info
-* APIs.
-* 7.0 aru 03/15/19 Check for versal before aarch64 and armr5
-* in XGetPlatform_Info()
-* 7.2 adk 08/01/20 Added versal support for the XGetPSVersion_Info function.
-* 7.6 mus 08/23/21 Updated prototypes for functions which are not taking any
-* arguments with void keyword. This has been done to fix
-* compilation warnings with "-Wstrict-prototypes" flag.
-* It fixes CR#1108601.
-* 7.6 mus 08/30/21 Updated flag checking to fix compilation warnings
-* reported with "-Wundef" flag. It fixes CR#1108601.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xplatform_info.h"
-#if defined (__aarch64__)
-#include "bspconfig.h"
-#include "xil_smc.h"
-#endif
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* @brief This API is used to provide information about platform
-*
-* @return The information about platform defined in xplatform_info.h
-*
-******************************************************************************/
-u32 XGetPlatform_Info(void)
-{
-#if defined (versal)
- return XPLAT_VERSAL;
-#elif defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU)
- return XPLAT_ZYNQ_ULTRA_MP;
-#elif defined (__microblaze__)
- return XPLAT_MICROBLAZE;
-#else
- return XPLAT_ZYNQ;
-#endif
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief This API is used to provide information about zynq ultrascale MP platform
-*
-* @return The information about zynq ultrascale MP platform defined in
-* xplatform_info.h
-*
-******************************************************************************/
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
-u32 XGet_Zynq_UltraMp_Platform_info(void)
-{
-#if EL1_NONSECURE
- XSmc_OutVar reg;
- /*
- * This SMC call will return,
- * idcode - upper 32 bits of reg.Arg0
- * version - lower 32 bits of reg.Arg1
- */
- reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
- return (u32)((reg.Arg1 >> XPLAT_INFO_SHIFT) & XPLAT_INFO_MASK);
-#else
- u32 reg;
- reg = ((Xil_In32(XPLAT_PS_VERSION_ADDRESS) >> XPLAT_INFO_SHIFT )
- & XPLAT_INFO_MASK);
- return reg;
-#endif
-}
-#endif
-
-/*****************************************************************************/
-/**
-*
-* @brief This API is used to provide information about PS Silicon version
-*
-* @return The information about PS Silicon version.
-*
-******************************************************************************/
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU) || defined (versal)
-u32 XGetPSVersion_Info(void)
-{
-#if EL1_NONSECURE
- /*
- * This SMC call will return,
- * idcode - upper 32 bits of reg.Arg0
- * version - lower 32 bits of reg.Arg1
- */
- XSmc_OutVar reg;
- reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
- return (u32)((reg.Arg1 & XPS_VERSION_INFO_MASK) >>
- XPS_VERSION_INFO_SHIFT);
-#else
- u32 reg;
- reg = (Xil_In32(XPLAT_PS_VERSION_ADDRESS)
- & XPS_VERSION_INFO_MASK);
- return (reg >> XPS_VERSION_INFO_SHIFT);
-#endif
-}
-#endif
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5e/e00dce555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5e/e00dce555243001d18b399c1eb9b3628
deleted file mode 100644
index ab16593..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5e/e00dce555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,11 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#include "xil_types.h"
-/* Stuv for close() sys-call */
-__weak s32 _sys_close(s32 fh)
-{
- return -1;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5e/f1a9e7585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5e/f1a9e7585243001d18b399c1eb9b3628
deleted file mode 100644
index 1c41991..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5e/f1a9e7585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,134 +0,0 @@
-;******************************************************************************
-; Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-; SPDX-License-Identifier: MIT
-;*****************************************************************************
-;****************************************************************************
-;**
-; @file asm_vectors.s
-;
-; This file contains the initial vector table for the Cortex A9 processor
-;
-;
-; MODIFICATION HISTORY:
-;
-; Ver Who Date Changes
-; ----- ------- -------- ---------------------------------------------------
-; 1.00a Initial version
-; 4.2 pkp 06/27/14 Modified return addresses for interrupt
-; handlers
-; 5.1 pkp 05/13/15 Saved the addresses of instruction causing data
-; abort and prefetch abort into DataAbortAddr and
-; PrefetchAbortAddr for further use to fix CR#854523
-;
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.4 mmd 04/21/19 First release.
-* 7.2 nava 08/01/20 Updated Xil_WaitForEvent() and Xil_WaitForEvents(()
-* API to use microsecond timeout instead of a free
-* counter.
-* 7.3 kal 06/30/20 Converted Xil_Ceil macro to API.
-* rpo 08/19/20 Added function for read,modify,write
-* kal 09/22/20 Changed the param type from const char to const char*
-* to avoid copying key onto stack
-* td 10/16/20 Added Xil_Strcpy, Xil_Strcat, Xil_SecureMemCpy and
-* Xil_MemCmp functions
-* 7.4 am 11/26/20 Added Xil_StrCpyRange function
-* 7.6 kpt 07/15/21 Added Xil_SecureZeroize function
-*
-*
-*
-*****************************************************************************/
-
-/****************************** Include Files *********************************/
-#include "xil_util.h"
-#include "sleep.h"
-
-/************************** Constant Definitions ****************************/
-#define MAX_NIBBLES 8U
-
-/************************** Function Prototypes *****************************/
-
-/******************************************************************************/
-/**
-* This API ceils the provided float value.
-*
-* @param Value is a float variable which has to ceiled to nearest
-* integer.
-*
-* @return Returns ceiled value.
-*
-*******************************************************************************/
-int Xil_Ceil(float Value)
-{
- int Result = Value;
-
- if (Value > Result) {
- Result = Result + 1;
- }
-
- return Result;
-}
-
-/****************************************************************************/
-/**
- * Converts the char into the equivalent nibble.
- * Ex: 'a' -> 0xa, 'A' -> 0xa, '9'->0x9
- *
- * @param InChar - Input character to be converted to nibble.
- * Valid characters are between 0-9, a-f, A-F
- * @param Num - Memory location where nibble is to be stored
- *
- * @return
- * XST_SUCCESS - Character converted to nibble
- * XST_FAILURE - Invalid input character
- *
- * @note None.
- *
- *****************************************************************************/
-
-u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num)
-{
- u32 Status;
-
- /* Convert the char to nibble */
- if ((InChar >= (u8)'0') && (InChar <= (u8)'9')) {
- *Num = InChar - (u8)'0';
- Status = XST_SUCCESS;
- }
- else if ((InChar >= (u8)'a') && (InChar <= (u8)'f')) {
- *Num = InChar - (u8)'a' + 10U;
- Status = XST_SUCCESS;
- }
- else if ((InChar >= (u8)'A') && (InChar <= (u8)'F')) {
- *Num = InChar - (u8)'A' + 10U;
- Status = XST_SUCCESS;
- }
- else {
- Status = XST_FAILURE;
- }
-
- return Status;
-}
-
-/****************************************************************************/
-/*
- * Converts the string into the equivalent Hex buffer.
- * Ex: "abc123" -> {0xab, 0xc1, 0x23}
- *
- * @param Str - Pointer to string to be converted to Hex.
- * Accepted characters in string are between 0-9, a-f and A-F
- * @param Buf - Pointer to memory location where converted hex values are to
- * be stored.
- * @param Len - Length of input string
- *
- * @return
- * XST_SUCCESS - Input string is converted to hex
- * XST_FAILURE - Invalid character in inpit string
- *
- * @note None.
- *
- *****************************************************************************/
-u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len)
-{
- u32 Status = XST_FAILURE;
- u8 ConvertedLen = 0U, index = 0U;
- u8 Nibble[MAX_NIBBLES] = {0U};
- u8 i;
-
- while (ConvertedLen < Len) {
- for (i = 0U; i < MAX_NIBBLES; i++) {
- Status = Xil_ConvertCharToNibble(Str[ConvertedLen],
- &Nibble[i]);
- ConvertedLen = ConvertedLen +1U;
- if (Status != XST_SUCCESS) {
- /* Error converting char to nibble */
- goto END;
- }
- }
-
- buf[index] = ((Nibble[0] << (u8)28U) | (Nibble[1] << (u8)24U) |
- (Nibble[2] << (u8)20U) | (Nibble[3] << (u8)16U) |
- (Nibble[4] << (u8)12U) | (Nibble[5] << (u8)8U) |
- (Nibble[6] << (u8)4U) | (u32)Nibble[7]);
- index++;
- }
-END:
- return Status;
-}
-
-/****************************************************************************/
-/*
- * Waits for the event
- *
- * @param RegAddr - Address of register to be checked for event(s) occurrence
- * @param EventMask - Mask indicating event(s) to be checked
- * @param Event - Specific event(s) value to be checked
- * @param Timeout - Max number of microseconds to wait for an event(s).
- *
- * @return
- * XST_SUCCESS - On occurrence of the event(s).
- * XST_FAILURE - Event did not occur before counter reaches 0
- *
- * @note None.
- *
- *****************************************************************************/
-u32 Xil_WaitForEvent(u32 RegAddr, u32 EventMask, u32 Event, u32 Timeout)
-{
- u32 EventStatus;
- u32 PollCount = Timeout;
- u32 Status = XST_FAILURE;
-
- while(PollCount > 0) {
- EventStatus = Xil_In32(RegAddr) & EventMask;
- if (EventStatus == Event) {
- Status = XST_SUCCESS;
- break;
- }
- PollCount--;
- usleep(1U);
- }
-
- return Status;
-}
-
-
-/******************************************************************************/
-/**
- * Waits for the events. Returns on occurrence of first event / timeout.
- *
- * @param EventsRegAddr - Address of register to be checked for event(s)
- * occurrence
- * @param EventsMask - Mask indicating event(s) to be checked
- * @param WaitEvents - Specific event(s) to be checked
- * @param Timeout - Max number of microseconds to wait for an event(s).
- * @param Events - Mask of Events occurred returned in memory pointed by
- * this variable
- *
- * @return
- * XST_SUCCESS - On occurrence of the event(s).
- * XST_FAILURE - Event did not occur before counter reaches 0
- *
- ******************************************************************************/
-u32 Xil_WaitForEvents(u32 EventsRegAddr, u32 EventsMask, u32 WaitEvents,
- u32 Timeout, u32* Events)
-{
- u32 EventStatus;
- u32 PollCount = Timeout;
- u32 Status = XST_TIMEOUT;
-
- *Events = 0x00;
- do {
- EventStatus = Xil_In32(EventsRegAddr);
- EventStatus &= EventsMask;
- if(EventStatus & WaitEvents) {
- Status = XST_SUCCESS;
- *Events = EventStatus;
- break;
- }
- PollCount--;
- usleep(1U);
- }
- while(PollCount > 0);
-
- return Status;
-}
-
-/******************************************************************************/
-/**
- * Checks whether the passed character is a valid hex digit
- *
- * @param Ch - Pointer to the input character
- *
- * @return
- * XST_SUCCESS - on valid hex digit
- * XST_FAILURE - on invalid hex digit
- *
- * @note None.
- *
- ******************************************************************************/
-u32 Xil_IsValidHexChar(const char *Ch)
-{
- u32 Status = XST_FAILURE;
-
- if(NULL == Ch) {
- goto END;
- }
- if ((*Ch >= '0' && *Ch <='9')||
- (*Ch >= 'a' && *Ch <='f')||
- (*Ch >= 'A' && *Ch <='F')) {
-
- Status = XST_SUCCESS;
- }
-END:
- return Status;
-}
-
-/******************************************************************************/
-/**
- * Validate the input string contains only hexadecimal characters
- *
- * @param HexStr - Pointer to string to be validated
- *
- * @return
- * XST_SUCCESS - On valid input hex string
- * XST_INVALID_PARAM - On invalid length of the input string
- * XST_FAILURE - On non hexadecimal character in string
- *
- * @note None
- *
- ******************************************************************************/
-u32 Xil_ValidateHexStr(const char *HexStr)
-{
- u32 Idx;
- u32 Len;
- u32 Status = XST_INVALID_PARAM;
-
- if(NULL == HexStr) {
- goto END;
- }
-
- Len = Xil_Strnlen(HexStr, XIL_MAX_HEX_STR_LEN + 1U);
- if (Len > XIL_MAX_HEX_STR_LEN) {
- goto END;
- }
-
- for (Idx = 0U; Idx < Len; Idx++) {
- Status = Xil_IsValidHexChar(&HexStr[Idx]);
- if (Status != XST_SUCCESS) {
- break;
- }
- }
-
-END:
- return Status;
-}
-
-/****************************************************************************/
-/**
- * Converts the string into the equivalent Hex buffer.
- * Ex: "abc123" -> {0xab, 0xc1, 0x23}
- *
- * @param Str is a Input String. Will support the lower and upper case values.
- * Value should be between 0-9, a-f and A-F
- * @param Buf is Output buffer.
- * @param Len of the input string. Should have even values
- *
- * @return
- * - XST_SUCCESS no errors occurred.
- * - XST_FAILURE an error when input parameters are not valid
- * - an error when input buffer has invalid values
- *
- * TDD Test Cases:
- * ---Initialization---
- * Len is odd
- * Len is zero
- * Str is NULL
- * Buf is NULL
- * ---Functionality---
- * Str input with only numbers
- * Str input with All values in A-F
- * Str input with All values in a-f
- * Str input with values in a-f, 0-9, A-F
- * Str input with values in a-z, 0-9, A-Z
- * Boundary Cases
- * Memory Bounds of buffer checking
- * ****************************************************************************/
-u32 Xil_ConvertStringToHexBE(const char *Str, u8 *Buf, u32 Len)
-{
- u32 ConvertedLen;
- u8 LowerNibble = 0U;
- u8 UpperNibble = 0U;
- u32 Status = (u32)XST_FAILURE;
-
- if ((Str == NULL) || (Buf == NULL)) {
- Status = (u32)XST_INVALID_PARAM;
- goto END;
- }
-
- if ((Len == 0U) || ((Len % XIL_SIZE_OF_BYTE_IN_BITS) != 0U)) {
- Status = (u32)XST_INVALID_PARAM;
- goto END;
- }
-
- if(Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) {
- Status = (u32)XST_INVALID_PARAM;
- goto END;
- }
-
- ConvertedLen = 0U;
- while (ConvertedLen < (Len / XIL_SIZE_OF_NIBBLE_IN_BITS)) {
- if (Xil_ConvertCharToNibble(Str[ConvertedLen],&UpperNibble)
- == (u32)XST_SUCCESS) {
- if (Xil_ConvertCharToNibble(Str[ConvertedLen+1],
- &LowerNibble) == (u32)XST_SUCCESS) {
- Buf[ConvertedLen/2] =
- (UpperNibble << XIL_SIZE_OF_NIBBLE_IN_BITS) |
- LowerNibble;
- }
- else {
- Status = (u32)XST_INVALID_PARAM;
- goto END;
- }
- }
- else {
- Status = (u32)XST_INVALID_PARAM;
- goto END;
- }
- ConvertedLen += 2U;
- }
- Status = (u32)XST_SUCCESS;
-END:
- return Status;
-}
-
-/******************************************************************************/
-/**
- * Converts the string into the equivalent Hex buffer.
- * Ex: "abc123" -> {0x23, 0xc1, 0xab}
- *
- * @param Str - Input String to be converted to hex number in little
- * endian format. Valid characters of input strin are between
- * 0-9, a-f and A-F
- * @param Buf - Pointer to memory location where converted hex numbers are to
- * be stored.
- * @param Len - Expected number of output bits
- *
- * @return
- * XST_SUCCESS - Input string is converted to hex number(s)
- * XST_FAILURE - Invalid input character detected in input string
- *
- * @note
- *
- ******************************************************************************/
-u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len)
-{
- u32 ConvertedLen;
- u8 LowerNibble = 0U;
- u8 UpperNibble = 0U;
- u32 StrIndex;
- u32 Status = XST_FAILURE;
-
- if ((NULL == Str) || (NULL == Buf)) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- if ((Len == 0U) || ((Len % XIL_SIZE_OF_BYTE_IN_BITS) != 0U)) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- if(Len != (strlen(Str) * XIL_SIZE_OF_NIBBLE_IN_BITS)) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- StrIndex = (Len / XIL_SIZE_OF_BYTE_IN_BITS) - 1U;
- ConvertedLen = 0U;
- while (ConvertedLen < (Len / XIL_SIZE_OF_NIBBLE_IN_BITS)) {
- Status = Xil_ConvertCharToNibble(Str[ConvertedLen],
- &UpperNibble);
- if (XST_SUCCESS == Status) {
- Status = Xil_ConvertCharToNibble(Str[ConvertedLen + 1],
- &LowerNibble);
- if (XST_SUCCESS == Status) {
- Buf[StrIndex] =
- (UpperNibble << XIL_SIZE_OF_NIBBLE_IN_BITS) |
- LowerNibble;
- StrIndex = StrIndex - 1U;
- }
- else {
- Status = XST_INVALID_PARAM;
- goto END;
- }
- }
- else {
- Status = XST_INVALID_PARAM;
- goto END;
- }
- ConvertedLen += 2U;
- }
-
- Status = XST_SUCCESS;
-END:
- return Status;
-}
-
-/******************************************************************************/
-/**
- * Returns the length of input string.
- *
- * @param Str - Input string
- * @param MaxLen - Maximum expected length of the input string
- *
- * @return
- * Returns length of the input string if length is less than MaxLen.
- * Returns MaxLen if the length of the input string is >= MaxLen.
- *
- * @note
- *
- ******************************************************************************/
-u32 Xil_Strnlen(const char *Str, u32 MaxLen)
-{
- const char *InStr = Str;
- u32 StrLen = 0U;
-
- if (NULL == Str) {
- goto END;
- }
-
- while(StrLen < MaxLen) {
- if ('\0' == *InStr) {
- break;
- }
- StrLen++;
- InStr++;
- }
-
-END:
- return StrLen;
-}
-
-/*****************************************************************************/
-/**
- * @brief This function will Read, Modify and Write to an address.
- *
- * @param Addr denotes Address
- * @param Mask denotes the bits to be modified
- * @param Value is the value to be written to the address
- *
- * @return None
- *
- *****************************************************************************/
-void Xil_UtilRMW32(u32 Addr, u32 Mask, u32 Value)
-{
- u32 Val;
-
- Val = Xil_In32(Addr);
- Val = (Val & (~Mask)) | (Mask & Value);
- Xil_Out32(Addr, Val);
-}
-
-/*****************************************************************************/
-/**
- * @brief This functions copies source string to destination string. This
- * function is a safe version of strcpy
- *
- * @param DestPtr is pointer to destination string
- * @param SrcPtr is pointer to source string
- * @param Size is the maximum number of bytes of the source string
- * to be copied
- *
- * @return XST_SUCCESS on success and error code on failure
- *
- ******************************************************************************/
-int Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size)
-{
- int Status = XST_FAILURE;
- u32 Count;
-
- if ((SrcPtr == NULL) || (DestPtr == NULL) || (Size == 0U)) {
- goto END;
- }
-
- for (Count = 0U; (SrcPtr[Count] != '\0') && (Count < Size); ++Count) {
- DestPtr[Count] = SrcPtr[Count];
- }
- if (Count == Size) {
- DestPtr[0U] = '\0';
- goto END;
- }
- DestPtr[Count] = '\0';
- Status = XST_SUCCESS;
-
-END:
- return Status;
-}
-
-/****************************************************************************/
-/**
- * @brief Copies specified range from source string to destination string
- *
- * @param Src is a pointer to source string
- * @param Dst is a pointer to destination string
- * @param From is 0 based index from where string copy starts
- * @param To is 0 based index till which string is copied
- * @param MaxSrcLen is the maximum length of source string
- * @param MaxDstLen is the maximum length of destination string
- *
- * @return XST_SUCCESS on success
- * XST_FAILURE on failure
- *
- * @note None
- *
- ****************************************************************************/
-int Xil_StrCpyRange(const u8 *Src, u8 *Dst, u32 From, u32 To, u32 MaxSrcLen,
- u32 MaxDstLen)
-{
- int Status = XST_FAILURE;
- u32 SrcLength;
- u32 Index;
-
- if ((Src == NULL) || (Dst == NULL)) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- if ((To >= MaxSrcLen) || (To < From)) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- if ((To - From + 1U) >= MaxDstLen) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- SrcLength = Xil_Strnlen((const char *)Src, MaxSrcLen);
- if (To >= SrcLength) {
- Status = XST_INVALID_PARAM;
- goto END;
- }
-
- for (Index = From; Index <= To && Src[Index]!= '\0'; Index++) {
- Dst[Index - From] = Src[Index];
- }
-
- Dst[Index - From] = '\0';
- Status = XST_SUCCESS;
-
-END:
- return Status;
-}
-
-/*****************************************************************************/
-/**
- * @brief This function appends string2 to string1. This function is a safe
- * version of strcat
- *
- * @param Str1Ptr is pointer to string1
- * @param Str2Ptr is pointer to string2
- * @param Size is the maximum number of bytes Str1 can hold
- *
- * @return XST_SUCCESS on success and error code on failure
- *
- ******************************************************************************/
-int Xil_Strcat(char* Str1Ptr, const char* Str2Ptr, const u32 Size)
-{
- int Status = XST_FAILURE;
- u32 Count = 0U;
- u32 CountTmp = 0U;
-
- if ((Str1Ptr == NULL) || (Str2Ptr == NULL) || (Size == 0U)) {
- goto END;
- }
-
- while ((Count < Size) && (Str1Ptr[Count] != '\0')) {
- Count++;
- }
-
- while ((Str2Ptr[CountTmp] != '\0') && (Count < Size)) {
- Str1Ptr[Count++] = Str2Ptr[CountTmp++];
- }
- if (Count == Size) {
- Str1Ptr[0U] = '\0';
- goto END;
- }
- Str1Ptr[Count] = '\0';
- Status = XST_SUCCESS;
-
-END:
- return Status;
-}
-
-/*****************************************************************************/
-/**
- * @brief This function copies Len bytes from source memory to destination
- * memory. If Len is greater than DestPtrLen, then DestPtr is also
- * filled with 0s till DestPtrLen bytes and is considered as a failure.
- * This function is a secure implementation of memcpy
- *
- * @param DestPtr is pointer to destination address
- * @param DestPtrLen is the memory alloted to the destination buffer
- * @param SrcPtr is pointer to source address
- * @param Len is number of bytes to be copied
- *
- * @return XST_SUCCESS on success and error code on failure
- *
- ******************************************************************************/
-int Xil_SecureMemCpy(void * DestPtr, u32 DestPtrLen, const void * SrcPtr, u32 Len)
-{
- int Status = XST_FAILURE;
- u8 *Dest = (u8 *)DestPtr;
- const u8 *Src = (const u8 *)SrcPtr;
-
- if ((DestPtr == NULL) || (SrcPtr == NULL)) {
- goto END;
- }
-
- if (Len > DestPtrLen) {
- while (DestPtrLen != 0U) {
- *Dest = 0U;
- Dest++;
- DestPtrLen--;
- }
- goto END;
- }
-
- /* Loop and copy. */
- while (Len != 0U) {
- *Dest = *Src;
- Dest++;
- Src++;
- Len--;
- }
- Status = XST_SUCCESS;
-
-END:
- return Status;
-}
-
-/*****************************************************************************/
-/**
- * @brief This function compares Len bytes from memory1 and memory2. This
- * function is a secure implementation of memcmp
- *
- * @param Buf1Ptr is pointer to memory1
- * @param Buf2Ptr is pointer to memory2
- * @param Len is number of byets to be compared
- *
- * @return 0 if contents of both the memory regions are same,
- * -1 if first non-matching character has lower value in Buf1Ptr
- * 1 if first non-matching character is greater value in Buf1Ptr
- *
- ******************************************************************************/
-int Xil_MemCmp(const void * Buf1Ptr, const void * Buf2Ptr, u32 Len)
-{
- volatile int RetVal = 1;
- const u8 *Buf1 = Buf1Ptr;
- const u8 *Buf2 = Buf2Ptr;
- u32 Size = Len;
-
- /* Assert validates the input arguments */
- if ((Buf1 == NULL) || (Buf2 == NULL) || (Len == 0x0U)) {
- goto END;
- }
-
- /* Loop and compare */
- while (Size != 0U) {
- if (*Buf1 > *Buf2) {
- RetVal = 1;
- goto END;
- } else if (*Buf1 < *Buf2) {
- RetVal = -1;
- goto END;
- } else {
- Buf1++;
- Buf2++;
- Size--;
- }
- }
-
- /* Make sure size is zero to know the whole of data is compared */
- if (Size == 0U) {
- RetVal = 0;
- }
-
-END:
- return RetVal;
-}
-
-/*****************************************************************************/
-/**
- * @brief This function is used to zeroize the memory
- *
- * @param DataPtr Pointer to the memory which need to be zeroized.
- * @param Length Length of the data in bytes.
- *
- * @return
- * - XST_SUCCESS: If Zeroization is successful.
- * - XST_FAILURE: If Zeroization is not successful.
- ********************************************************************************/
-int Xil_SecureZeroize(u8 *DataPtr, const u32 Length)
-{
- u32 Index;
- int Status = XST_FAILURE;
-
- /* Clear the data */
- (void)memset(DataPtr, 0, Length);
-
- /* Read it back to verify */
- for (Index = 0U; Index < Length; Index++) {
- if (DataPtr[Index] != 0x00U) {
- goto END;
- }
- }
- if (Index == Length) {
- Status = XST_SUCCESS;
- }
-
-END:
- return Status;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5f/c0a234575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5f/c0a234575243001d18b399c1eb9b3628
deleted file mode 100644
index 7cbfe44..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/5f/c0a234575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,537 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2012 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file fsbl.h
-*
-* Contains the function prototypes, defines and macros for the
-* First Stage Boot Loader (FSBL) functionality
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a jz 03/04/11 Initial release
-* 2.00a mb 06/06/12 Removed the qspi define, will be picked from
-* xparameters.h file
-* 3.00a np/mb 08/08/12 Added the error codes for the FSBL hook errors.
-* Added the debug levels
-* 4.00a sgd 02/28/13 Removed DDR initialization check
-* Removed DDR ECC initialization code
-* Modified hand off address check to 1MB
-* Added RSA authentication support
-* Removed LPBK_DLY_ADJ register setting code as we use
-* divisor 8
-* Removed check for Fabric is already initialized
-*
-* CR's fixed and description
-* 689026: FSBL doesn't hold PL resets active during
-* bit download
-* Resolution: PL resets are released just before
-* handoff
-*
-* 689077: FSBL hangs at Handoff clearing the
-* TX UART buffer
-* Resolution: STDOUT_BASEADDRESS macro value changes
-* based UART select, hence used STDOUT_BASEADDRESS
-* as UART base address
-*
-* 695578: FSBL failed to load standalone application
-* in secure bootmode
-* Resolution: Application will be placed at load address
-* instead of DDR temporary address
-*
-* 699475: FSBL functionality is broken and its
-* not able to boot in QSPI/NAND bootmode
-* Resolution: New flags are added DevCfg driver
-* for handling loopback
-* XDCFG_CONCURRENT_NONSEC_READ_WRITE
-* XDCFG_CONCURRENT_SECURE_READ_WRITE
-*
-* 683145: Define stack area for FIQ, UNDEF modes
-* in linker file
-* Resolution: FSBL linker modified to create stack area
-* for FIQ, UNDEF
-*
-* 705664: FSBL fails to decrypt the bitstream when
-* the image is AES encrypted using non-zero key value
-* Resolution: Fabric cleaning will not be done
-* for AES-E-Fuse encryption
-*
-* Watchdog disabled for AES E-Fuse encryption
-*
-* 5.00a sgd 05/17/13 Fallback support for E-Fuse encryption
-* Added QSPI Flash Size > 128Mbit support
-* QSPI Dual Stack support
-* Added Md5 checksum support
-*
-* CR's fixed and description
-* 692045 FSBL: Linker script of FSBL has PHDR workaround,
-* this needs to be fixed
-* Resolution: Removed PHDR from Linker file
-*
-* 704287 FSBL: fsbl.h file has a few error codes that
-* are not used by FSBL, that needs to be removed
-* Resolution: Removed unused error codes
-*
-* 704379 FSBL: Check if DDR is in proper state before
-* handoff
-* Resolution: Added DDR initialization check
-*
-* 709077 If FSBL_DEBUG and FSBL_DEBUG_INFO are defined,
-* the debug level is FSBL_DEBUG only.
-*
-* 710128 FSBL: Linux boot failing without load attribute
-* set for Linux partitions in BIF
-* Resolution: FSBL will load partitions with valid load
-* address and stop loading if any invalid load address
-*
-* 708728 Issues seen while making HP interconnect
-* 32 bit wide
-* Resolution: ps7_post_config function generated by PCW
-* will be called after Bit stream download
-* Added MMC support
-* 6.00a kc 07/31/2013 CR's fixed and description
-* 724166 FSBL doesn’t use PPK authenticated by Boot ROM
-* for authenticating the Partition images
-* Resolution: FSBL now uses the PPK left by Boot ROM in
-* OCM for authencating the SPK
-*
-* 724165 Partition Header used by FSBL is not
-* authenticated
-* Resolution: FSBL now authenticates the partition header
-*
-* 691150 ps7_init does not check for peripheral
-* initialization failures or timeout on polls
-* Resolution: Return value of ps7_init() is now checked
-* by FSBL and prints the error string
-*
-* 708316 PS7_init.tcl file should have Error mechanism
-* for all mask_poll
-* Resolution: Return value of ps7_init() is now checked
-* by FSBL and prints the error string
-*
-* 732062 FSBL fails to build if UART not available
-* Resolution: Added define to call xil_printf only
-* if uart is defined
-*
-* 722979 Provide customer-friendly changelogs in FSBL
-* Resolution: Added CR description for all the files
-*
-* 732865 Backward compatibility for ps7_init function
-* Resolution: Added a new define for ps7_init success
-* and value is defined based on ps7_init define
-*
-* Fix for CR#739711 - FSBL not able to read Large
-* QSPI (512M) in IO Mode
-* Resolution: Modified the address calculation
-* algorithm in dual parallel mode for QSPI
-*
-* 7.00a kc 10/18/13 Integrated SD/MMC driver
-* 10/23/13 Support for armcc compiler added
-* 741003 FSBL has to check the HMAC error status after
-* decryption
-* Resolution: Added code for checking the error status
-* after PCAP completion
-* 739968 FSBL should do the QSPI config settings for
-* Dual parallel configuration in IO mode
-* Resolution: Added QSPI config settings in qspi.c
-* 724620 FSBL: How to handle PCAP_MODE after bitstream
-* configuration.
-* Resolution: PCAP_MODE and PCAP_PR bits are now cleared
-* after PCAP transfer completion
-* 726178 In the 14.6 FSBL function FabricInit() PROG_B
-* is kept active for 5mS.
-* Resolution: PROG_B is now kept active for 5ms only in case
-* if efuse is the aes key source.
-* 755245 FSBL does not load partition if eMMC has only
-* one partition
-* Resolution: Changed the if condition for MMC
-* 12/04/13 764382 FSBL: How to handle PCAP_MODE after bitstream
-* configuration
-* Resolution: Reverted back the changes of 724620. PCAP_MODE
-* and PCAP_PR bits are not changed
-* 8.00a kc 01/16/13 767798 Fsbl MD5 Checksum failiure for encrypted images
-* Resolution: For checksum enabled partitions, total
-* total partition image length is copied now.
-* 761895 FSBL should authenticate image only if
-* partition owner was not set to u-boot
-* Resolution: Partition owner check added in
-* image_mover.c
-* 02/20/14 775631 - FSBL: FsblGetGlobalTimer() is not proper
-* Resolution: Function argument is updated from value
-* to pointer to reflect updated value
-* 9.00a kc 04/16/14 773866 - SetPpk() will fail on secure fallback
-* unless FSBL* and FSBL are identical in length
-* Resolution: PPK is set only once now.
-* 785778 - FSBL takes 8 seconds to
-* authenticate (RSA) a bitstream on zc706
-* Resolution: Data Caches are enabled only for
-* authentication.
-* 791245 - Use of xilrsa in fsbl
-* Resolution: Rsa library is removed from fsbl source
-* and xilrsa is used from BSP
-* 10.00a kc 07/15/14 804595 Zynq FSBL - Issues with
-* fallback image offset handling using MD5
-* Resolution: Updated the checksum offset to add with
-* image base address
-* 782309 Fallback support for AES
-* encryption with E-Fuse - Enhancement
-* Resolution: Same as 773866
-* 809336 Minor code cleanup
-* Resolution Minor code changes
-* kc 08/27/14 820356 - FSBL compilation fails with IAR compiler
-* Resolution: Change of __asm__ to __asm
-* 11.00a kv 10/08/14 826030 - FSBL:LinearBootDeviceFlag is not initialized
-* in IO mode case.Due to which the variable is
-* remaining in unknown state.
-* Resolution: LinearBootDeviceFlag is initialized 0
-* in main.c
-* 12.00a ssc 12/11/14 839182 - FSBL -In the file sd.c, f_mount is called with
-* two arguments but f_mount is expecting the 3 arguments
-* from build 2015.1_1210_1, causing compilation error.
-* Resolution: Arguments for f_mount in InitSD() are
-* changed as per new signature.
-* 13.00a ssc 04/10/15 846899 - FSBL -In the file pcap.c, to clear DMA done
-* count, devcfg.INT_STS register is written to, which is
-* not correct.
-* Resolution: Corresponding fields in the devcfg.STATUS
-* register are written to, for clearing DMA done count.
-* 14.00a gan 01/13/16 869081 -(2016.1)FSBL -In qspi.c, FSBL picks the qspi
-* read command from LQSPI_CFG register instead of hard
-* coded read command (0x6B).
-* 15.00a gan 07/21/16 953654 -(2016.3)FSBL -In pcap.c/pcap.h/main.c,
-* Fabric Initialization sequence is modified to check
-* the PL power before sequence starts and checking INIT_B
-* reset status twice in case of failure.
-* 16.00a gan 08/02/16 Fix for CR# 955897 -(2016.3)FSBL -
-* In pcap.c, check pl power through MCTRL register
-* for 3.0 and later versions of silicon.
-* 17.00a bsv 27/03/18 Fix for CR# 996973 Add code under JTAG_ENABLE_LEVEL_SHIFTERS macro
-* to enable level shifters in jtag boot mode.
-* 18.00a ka 10/29/18 Fix for CR# 1006294 Added macro for FORCE_USE_AES_EXCLUDE
-*
-*
-*
-*
-*
-* @note
-*
-* Flags in FSBL
-*
-* FSBL_PERF
-*
-* This Flag can be set at compilation time. This flag is set for
-* measuring the performance of FSBL.That is the time taken to execute is
-* measured.when this flag is set.Execution time with reference to
-* global timer is taken here
-*
-* Total Execution time is the time taken for executing FSBL till handoff
-* to any application .
-* If there is a bitstream in the partition header then the
-* execution time includes the copying of the bitstream to DDR
-* (in case of SD/NAND bootmode)
-* and programming the devcfg dma is accounted.
-*
-* FSBL provides two debug levels
-* DEBUG GENERAL - fsbl_printf under this category will appear only when the
-* FSBL_DEBUG flag is set during compilation
-* DEBUG_INFO - fsbl_printf under this category will appear when the
-* FSBL_DEBUG_INFO flag is set during compilation
-* For a more detailed output log can be used.
-* FSBL_DEBUG_RSA - Define this macro to print more detailed values used in
-* RSA functions
-* These macros are input to the fsbl_printf function
-*
-* DEBUG LEVELS
-* FSBL_DEBUG level is level 1, when this flag is set all the fsbl_prints
-* that are with the DEBUG_GENERAL argument are shown
-* FSBL_DEBUG_INFO is level 2, when this flag is set during the
-* compilation , the fsbl_printf with DEBUG_INFO will appear on the com port
-*
-* DEFAULT LEVEL
-* By default no print messages will appear.
-*
-* NON_PS_INSTANTIATED_BITSTREAM
-*
-* FSBL will not enable the level shifters for a NON PS instantiated
-* Bitstream.This flag can be set during compilation for a NON PS instantiated
-* bitstream
-*
-* ECC_ENABLE
-* This flag will be defined in the ps7_init.h file when ECC is enabled
-* in the DDR configuration (XPS GUI)
-*
-* RSA_SUPPORT
-* This flag is used to enable authentication feature
-* Default this macro disabled, reason to avoid increase in code size
-*
-* MMC_SUPPORT
-* This flag is used to enable MMC support feature
-*
-* JTAG_ENABLE_LEVEL_SHIFTERS
-* FSBL will not enable the level shifters for jtag boot mode. This flag can be
-* set during compilation for jtag boot mode to enable level shifters.
-*
-* FORCE_USE_AES_EXCLUDE
-* Defining this flag will exclude the feature, forcing every partition to be
-* encrypted when EFUSE_SEC_EN bit is set.
-* This flag can be set/unset during compilation.
-* By default this flag is unset/undefined which enables the above feature
-* Note : Changing the default behaviour is not recommended from
-* Security perspective.
-*
-*******************************************************************************/
-#ifndef XIL_FSBL_H
-#define XIL_FSBL_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_io.h"
-#include "xparameters.h"
-#include "xpseudo_asm.h"
-#include "xil_printf.h"
-#include "pcap.h"
-#include "fsbl_debug.h"
-#include "ps7_init.h"
-#ifdef FSBL_PERF
-#include "xtime_l.h"
-#include
-#endif
-
-
-/************************** Constant Definitions *****************************/
-/*
- * SDK release version
- */
-#define SDK_RELEASE_YEAR 2021
-#define SDK_RELEASE_QUARTER 2
-
-#define WORD_LENGTH_SHIFT 2
-
-/*
- * On a Successful handoff to an application FSBL sets this SUCCESS code
- */
-#define SUCCESSFUL_HANDOFF 0x1 /* Successful Handoff */
-
-/*
- * Backward compatibility for ps7_init
- */
-#ifdef NEW_PS7_ERR_CODE
-#define FSBL_PS7_INIT_SUCCESS PS7_INIT_SUCCESS
-#else
-#define FSBL_PS7_INIT_SUCCESS (1)
-#endif
-
-/*
- * ERROR CODES
- * The following are the Error codes that FSBL uses
- * If the Debug prints are enabled only then the error codes will be
- * seen on the com port.Without the debug prints enabled no error codes will
- * be visible.There are not saved in any register
- * Boot Mode States used for error and status output
- * Error codes are defined below
- */
-#define ILLEGAL_BOOT_MODE 0xA000 /**< Illegal boot mode */
-#define ILLEGAL_RETURN 0xA001 /**< Illegal return */
-#define PCAP_INIT_FAIL 0xA002 /**< Pcap driver Init Failed */
-#define DECRYPTION_FAIL 0xA003 /**< Decryption Failed */
-#define BITSTREAM_DOWNLOAD_FAIL 0xA004 /**< Bitstream download fail */
-#define DMA_TRANSFER_FAIL 0xA005 /**< DMA Transfer Fail */
-#define INVALID_FLASH_ADDRESS 0xA006 /**< Invalid Flash Address */
-#define DDR_INIT_FAIL 0xA007 /**< DDR Init Fail */
-#define NO_DDR 0xA008 /**< DDR missing */
-#define SD_INIT_FAIL 0xA009 /**< SD Init fail */
-#define NAND_INIT_FAIL 0xA00A /**< Nand Init Fail */
-#define PARTITION_MOVE_FAIL 0xA00B /**< Partition move fail */
-#define AUTHENTICATION_FAIL 0xA00C /**< Authentication fail */
-#define INVALID_HEADER_FAIL 0xA00D /**< Invalid header fail */
-#define GET_HEADER_INFO_FAIL 0xA00E /**< Get header fail */
-#define INVALID_LOAD_ADDRESS_FAIL 0xA00F /**< Invalid load address fail */
-#define PARTITION_CHECKSUM_FAIL 0xA010 /**< Partition checksum fail */
-#define RSA_SUPPORT_NOT_ENABLED_FAIL 0xA011 /**< RSA not enabled fail */
-#define PS7_INIT_FAIL 0xA012 /**< ps7 Init Fail */
-#define PARTITION_LOAD_FAIL 0xA013 /**< Partition load fail*/
-/*
- * FSBL Exception error codes
- */
-#define EXCEPTION_ID_UNDEFINED_INT 0xA301 /**< Undefined INT Exception */
-#define EXCEPTION_ID_SWI_INT 0xA302 /**< SWI INT Exception */
-#define EXCEPTION_ID_PREFETCH_ABORT_INT 0xA303 /**< Prefetch Abort xception */
-#define EXCEPTION_ID_DATA_ABORT_INT 0xA304 /**< Data Abort Exception */
-#define EXCEPTION_ID_IRQ_INT 0xA305 /**< IRQ Exception Occurred */
-#define EXCEPTION_ID_FIQ_INT 0xA306 /**< FIQ Exception Occurred */
-
-/*
- * FSBL hook routine failures
- */
-#define FSBL_HANDOFF_HOOK_FAIL 0xA401 /**< FSBL handoff hook failed */
-#define FSBL_BEFORE_BSTREAM_HOOK_FAIL 0xA402 /**< FSBL before bit stream
- download hook failed */
-#define FSBL_AFTER_BSTREAM_HOOK_FAIL 0xA403 /**< FSBL after bitstream
- download hook failed */
-
-/*
- * Watchdog related Error codes
- */
-#define WDT_RESET_OCCURED 0xA501 /**< WDT Reset happened in FSBL */
-#define WDT_INIT_FAIL 0xA502 /**< WDT driver INIT failed */
-
-/*
- * SLCR Registers
- */
-#define PS_RST_CTRL_REG (XPS_SYS_CTRL_BASEADDR + 0x200)
-#define FPGA_RESET_REG (XPS_SYS_CTRL_BASEADDR + 0x240)
-#define RESET_REASON_REG (XPS_SYS_CTRL_BASEADDR + 0x250)
-#define RESET_REASON_CLR (XPS_SYS_CTRL_BASEADDR + 0x254)
-#define REBOOT_STATUS_REG (XPS_SYS_CTRL_BASEADDR + 0x258)
-#define BOOT_MODE_REG (XPS_SYS_CTRL_BASEADDR + 0x25C)
-#define PS_LVL_SHFTR_EN (XPS_SYS_CTRL_BASEADDR + 0x900)
-
-/*
- * Efuse Status Register
- */
-#define EFUSE_STATUS_REG (0xF800D010) /**< Efuse Status Register */
-#define EFUSE_STATUS_RSA_ENABLE_MASK (0x400) /**< Status of RSA enable */
-
-/*
- * PS reset control register define
- */
-#define PS_RST_MASK 0x1 /**< PS software reset */
-
-/*
- * SLCR BOOT Mode Register defines
- */
-#define BOOT_MODES_MASK 0x00000007 /**< FLASH types */
-
-/*
- * Boot Modes
- */
-#define JTAG_MODE 0x00000000 /**< JTAG Boot Mode */
-#define QSPI_MODE 0x00000001 /**< QSPI Boot Mode */
-#define NOR_FLASH_MODE 0x00000002 /**< NOR Boot Mode */
-#define NAND_FLASH_MODE 0x00000004 /**< NAND Boot Mode */
-#define SD_MODE 0x00000005 /**< SD Boot Mode */
-#define MMC_MODE 0x00000006 /**< MMC Boot Device */
-
-#define RESET_REASON_SRST 0x00000020 /**< Reason for reset is SRST */
-#define RESET_REASON_SWDT 0x00000001 /**< Reason for reset is SWDT */
-
-/*
- * Golden image offset
- */
-#define GOLDEN_IMAGE_OFFSET 0x8000
-
-/*
- * Silicon Version
- */
-#define SILICON_VERSION_1 0
-#define SILICON_VERSION_2 1
-#define SILICON_VERSION_3 2
-#define SILICON_VERSION_3_1 3
-
-/*
- * DDR start address for storing the data temporarily(1M)
- * Need to finalize correct logic
- */
-#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR
-#define DDR_START_ADDR XPAR_PS7_DDR_0_S_AXI_BASEADDR
-#define DDR_END_ADDR XPAR_PS7_DDR_0_S_AXI_HIGHADDR
-#else
-/*
- * In case of PL DDR, this macros defined based PL DDR address
- */
-#define DDR_START_ADDR 0x00
-#define DDR_END_ADDR 0x00
-#endif
-
-#define DDR_TEMP_START_ADDR DDR_START_ADDR
-/*
- * DDR test pattern
- */
-#define DDR_TEST_PATTERN 0xAA55AA55
-#define DDR_TEST_OFFSET 0x100000
-/*
- *
- */
-#define QSPI_DUAL_FLASH_SIZE 0x2000000; /*32MB*/
-#define QSPI_SINGLE_FLASH_SIZE 0x1000000; /*16MB*/
-#define NAND_FLASH_SIZE 0x8000000; /*128MB*/
-#define NOR_FLASH_SIZE 0x2000000; /*32MB*/
-#define LQSPI_CFG_OFFSET 0xA0
-#define LQSPI_CFG_DUAL_FLASH_MASK 0x40000000
-
-/*
- * These are the SLCR lock and unlock macros
- */
-#define SlcrUnlock() Xil_Out32(XPS_SYS_CTRL_BASEADDR + 0x08, 0xDF0DDF0D)
-#define SlcrLock() Xil_Out32(XPS_SYS_CTRL_BASEADDR + 0x04, 0x767B767B)
-
-#define IMAGE_HEADER_CHECKSUM_COUNT 10
-
-/* Boot ROM Image defines */
-#define IMAGE_WIDTH_CHECK_OFFSET (0x020) /**< 0xaa995566 Width Detection word */
-#define IMAGE_IDENT_OFFSET (0x024) /**< 0x584C4E58 "XLNX" */
-#define IMAGE_ENC_FLAG_OFFSET (0x028) /**< 0xA5C3C5A3 */
-#define IMAGE_USR_DEF_OFFSET (0x02C) /**< undefined could be used as */
-#define IMAGE_SOURCE_ADDR_OFFSET (0x030) /**< start address of image */
-#define IMAGE_BYTE_LEN_OFFSET (0x034) /**< length of image> in bytes */
-#define IMAGE_DEST_ADDR_OFFSET (0x038) /**< destination address in OCM */
-#define IMAGE_EXECUTE_ADDR_OFFSET (0x03c) /**< address to start executing at */
-#define IMAGE_TOT_BYTE_LEN_OFFSET (0x040) /**< total length of image in bytes */
-#define IMAGE_QSPI_CFG_WORD_OFFSET (0x044) /**< QSPI configuration data */
-#define IMAGE_CHECKSUM_OFFSET (0x048) /**< Header Checksum offset */
-#define IMAGE_IDENT (0x584C4E58) /**< XLNX pattern */
-
-/* Reboot status register defines:
- * 0xF0000000 for FSBL fallback mask to notify Boot Rom
- * 0x60000000 for FSBL to mark that FSBL has not handoff yet
- * 0x00FFFFFF for user application to use across soft reset
- */
-#define FSBL_FAIL_MASK 0xF0000000
-#define FSBL_IN_MASK 0x60000000
-
-/* The address that holds the base address for the image Boot ROM found */
-#define BASEADDR_HOLDER 0xFFFFFFF8
-
-/**************************** Type Definitions *******************************/
-
-/************************** Function Prototypes ******************************/
-
-void OutputStatus(u32 State);
-void FsblFallback(void);
-
-int FsblSetNextPartition(int Num);
-void *(memcpy_rom)(void * s1, const void * s2, u32 n);
-char *strcpy_rom(char *Dest, const char *Src);
-
-void ClearFSBLIn(void);
-void MarkFSBLIn(void);
-void FsblHandoff(u32 FsblStartAddr);
-u32 GetResetReason(void);
-
-#ifdef FSBL_PERF
-void FsblGetGlobalTime (XTime * tCur);
-void FsblMeasurePerfTime (XTime tCur, XTime tEnd);
-#endif
-void GetSiliconVersion(void);
-void FsblHandoffExit(u32 FsblStartAddr);
-void FsblHandoffJtagExit();
-/************************** Variable Definitions *****************************/
-extern int SkipPartition;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6/60172d595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6/60172d595243001d18b399c1eb9b3628
deleted file mode 100644
index fd80a0d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6/60172d595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,62 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_clocking.h
-*
-* The xil_clocking.h file contains clocking related functions and macros.
-* certain conditions.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 7.2 sd 12/11/19 First release
-* 7.2 sd 03/20/20 Added checking for isolation case
-*
-*
-******************************************************************************/
-
-#ifndef XIL_CLOCKING_H /* prevent circular inclusions */
-#define XIL_CLOCKING_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xdebug.h"
-#include "xil_printf.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xparameters.h"
-#include "xstatus.h"
-#if defined (XPAR_XCRPSU_0_DEVICE_ID)
-#include "xclockps.h"
-#else
-typedef u32 XClock_OutputClks;
-typedef u64 XClockRate;
-#endif
-
-/***************************** Include Files *********************************/
-
-
-/************************** Constant Definitions *****************************/
-
-
-XStatus Xil_ClockDisable(XClock_OutputClks ClockId);
-XStatus Xil_ClockEnable(XClock_OutputClks ClockId);
-XStatus Xil_ClockInit(void);
-XStatus Xil_ClockGet(void);
-XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate, XClockRate *SetRate);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6/924263595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6/924263595243001d18b399c1eb9b3628
deleted file mode 100644
index 3373b83..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6/924263595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,149 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2018 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file microblaze_instructions.h
-*
-* It provides wrapper macros to call 32/64 bit variant of specific
-* arithmetic/logical instructions, based on the processor in execution.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.8 mus 10/09/18 First release
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 6.0 mus 27/07/16 Consolidated exceptions for a53,a9 and r5
-* processors and added Xil_UndefinedExceptionHandler
-* for a53 32 bit and r5 as well.
-* 6.4 mus 08/06/17 Updated debug prints to replace %x with the %lx, to
-* fix the warnings.
-* 6.7 mna 26/04/18 Add an API to obtain a corresponding
-* Xil_ExceptionHandler entry from XExc_VectorTable.
-* 6.7 asa 18/05/18 Fix bugs in the API Xil_GetExceptionRegisterHandler.
-* 7.0 mus 07/03/19 Tweak Xil_ExceptionRegisterHandler and
-* Xil_GetExceptionRegisterHandler to support legacy
-* examples for Cortexa72 EL3 exception level.
-* 7.3 mus 07/27/20 Updated Xil_ExceptionRegisterHandler and
-* Xil_GetExceptionRegisterHandler to ignore
-* Exception_id, only if its pointing to IRQ.
-* It fixes CR#1069524
-*
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_exception.h"
-#include "xpseudo_asm.h"
-#include "xdebug.h"
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-typedef struct {
- Xil_ExceptionHandler Handler;
- void *Data;
-} XExc_VectorTableEntry;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Function Prototypes *****************************/
-static void Xil_ExceptionNullHandler(void *Data);
-/************************** Variable Definitions *****************************/
-/*
- * Exception vector table to store handlers for each exception vector.
- */
-#if defined (__aarch64__)
-XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
-{
- {Xil_ExceptionNullHandler, NULL},
- {Xil_SyncAbortHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
- {Xil_SErrorAbortHandler, NULL},
-
-};
-#else
-XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
-{
- {Xil_ExceptionNullHandler, NULL},
- {Xil_UndefinedExceptionHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
- {Xil_PrefetchAbortHandler, NULL},
- {Xil_DataAbortHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
-};
-#endif
-#if !defined (__aarch64__)
-u32 DataAbortAddr; /* Address of instruction causing data abort */
-u32 PrefetchAbortAddr; /* Address of instruction causing prefetch abort */
-u32 UndefinedExceptionAddr; /* Address of instruction causing Undefined
- exception */
-#endif
-
-/*****************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* This function is a stub Handler that is the default Handler that gets called
-* if the application has not setup a Handler for a specific exception. The
-* function interface has to match the interface specified for a Handler even
-* though none of the arguments are used.
-*
-* @param Data is unused by this function.
-*
-* @return None.
-*
-*****************************************************************************/
-static void Xil_ExceptionNullHandler(void *Data)
-{
- (void) Data;
-DieLoop: goto DieLoop;
-}
-
-/****************************************************************************/
-/**
-* @brief The function is a common API used to initialize exception handlers
-* across all supported arm processors. For ARM Cortex-A53, Cortex-R5,
-* and Cortex-A9, the exception handlers are being initialized
-* statically and this function does not do anything.
-* However, it is still present to take care of backward compatibility
-* issues (in earlier versions of BSPs, this API was being used to
-* initialize exception handlers).
-*
-* @return None.
-*
-*****************************************************************************/
-void Xil_ExceptionInit(void)
-{
- return;
-}
-
-/*****************************************************************************/
-/**
-* @brief Register a handler for a specific exception. This handler is being
-* called when the processor encounters the specified exception.
-*
-* @param Exception_id contains the ID of the exception source and should
-* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
-* See xil_exception.h for further information.
-* @param Handler to the Handler for that exception.
-* @param Data is a reference to Data that will be passed to the
-* Handler when it gets called.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler Handler,
- void *Data)
-{
-#if defined (versal) && !defined(ARMR5) && EL3
- if ( XIL_EXCEPTION_ID_IRQ_INT == Exception_id )
- {
- /*
- * Cortexa72 processor in versal is coupled with GIC-500, and
- * GIC-500 supports only FIQ at EL3. Hence, tweaking this API
- * to act on IRQ, if Exception_id is pointing to IRQ
- */
- Exception_id = XIL_EXCEPTION_ID_FIQ_INT;
- }
-#endif
- XExc_VectorTable[Exception_id].Handler = Handler;
- XExc_VectorTable[Exception_id].Data = Data;
-}
-
-/*****************************************************************************/
-/**
-* @brief Get a handler for a specific exception. This handler is being
-* called when the processor encounters the specified exception.
-*
-* @param Exception_id contains the ID of the exception source and should
-* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
-* See xil_exception.h for further information.
-* @param Handler to the Handler for that exception.
-* @param Data is a reference to Data that will be passed to the
-* Handler when it gets called.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_GetExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler *Handler,
- void **Data)
-{
-#if defined (versal) && !defined(ARMR5) && EL3
- if ( XIL_EXCEPTION_ID_IRQ_INT == Exception_id )
- {
- /*
- * Cortexa72 processor in versal is coupled with GIC-500, and
- * GIC-500 supports only FIQ at EL3. Hence, tweaking this API
- * to act on IRQ, if Exception_id is pointing to IRQ
- */
-
- Exception_id = XIL_EXCEPTION_ID_FIQ_INT;
- }
-#endif
-
- *Handler = XExc_VectorTable[Exception_id].Handler;
- *Data = XExc_VectorTable[Exception_id].Data;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Removes the Handler for a specific exception Id. The stub Handler
-* is then registered for this exception Id.
-*
-* @param Exception_id contains the ID of the exception source and should
-* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
-* See xil_exception.h for further information.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ExceptionRemoveHandler(u32 Exception_id)
-{
- Xil_ExceptionRegisterHandler(Exception_id,
- Xil_ExceptionNullHandler,
- NULL);
-}
-
-#if defined (__aarch64__)
-/*****************************************************************************/
-/**
-*
-* Default Synchronous abort handler which prints a debug message on console if
-* Debug flag is enabled
-*
-* @return None.
-*
-****************************************************************************/
-
-void Xil_SyncAbortHandler(void *CallBackRef){
- (void) CallBackRef;
- xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
- while(1) {
- ;
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Default SError abort handler which prints a debug message on console if
-* Debug flag is enabled
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_SErrorAbortHandler(void *CallBackRef){
- (void) CallBackRef;
- xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
- while(1) {
- ;
- }
-}
-#else
-/*****************************************************************************/
-/**
-*
-* Default Data abort handler which prints data fault status register through
-* which information about data fault can be acquired
-*
-* @return None.
-*
-****************************************************************************/
-
-void Xil_DataAbortHandler(void *CallBackRef){
- (void) CallBackRef;
-#ifdef DEBUG
- u32 FaultStatus;
-
- xdbg_printf(XDBG_DEBUG_ERROR, "Data abort \n");
- #ifdef __GNUC__
- FaultStatus = mfcp(XREG_CP15_DATA_FAULT_STATUS);
- #elif defined (__ICCARM__)
- mfcp(XREG_CP15_DATA_FAULT_STATUS,FaultStatus);
- #else
- { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS);
- FaultStatus = Reg; }
- #endif
- xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register %lx\n",FaultStatus);
- xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Data abort %lx\n",DataAbortAddr);
-#endif
- while(1) {
- ;
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Default Prefetch abort handler which prints prefetch fault status register through
-* which information about instruction prefetch fault can be acquired
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_PrefetchAbortHandler(void *CallBackRef){
- (void) CallBackRef;
-#ifdef DEBUG
- u32 FaultStatus;
-
- xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort \n");
- #ifdef __GNUC__
- FaultStatus = mfcp(XREG_CP15_INST_FAULT_STATUS);
- #elif defined (__ICCARM__)
- mfcp(XREG_CP15_INST_FAULT_STATUS,FaultStatus);
- #else
- { volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS);
- FaultStatus = Reg; }
- #endif
- xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register %lx\n",FaultStatus);
- xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Prefetch abort %lx\n",PrefetchAbortAddr);
-#endif
- while(1) {
- ;
- }
-}
-/*****************************************************************************/
-/**
-*
-* Default undefined exception handler which prints address of the undefined
-* instruction if debug prints are enabled
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_UndefinedExceptionHandler(void *CallBackRef){
- (void) CallBackRef;
- xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %lx\n",UndefinedExceptionAddr);
- while(1) {
- ;
- }
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/60/003a2d555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/60/003a2d555243001d18b399c1eb9b3628
deleted file mode 100644
index 9df2cc9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/60/003a2d555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,122 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2014 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xil-crt0.S
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00 pkp 05/21/14 Initial version
-* 5.04 pkp 12/18/15 Initialized global constructor for C++ applications
-* 5.04 pkp 01/05/16 Set the reset vector register RVBAR equivalent to
-* vector table base address
-* 6.02 pkp 01/22/17 Added support for EL1 non-secure
-* 6.6 srm 10/18/17 Added timer configuration using XTime_StartTTCTimer API.
-* Now the TTC instance as specified by the user will be
-* started.
-* 6.6 mus 01/29/18 Initialized the xen PV console for Cortexa53 64 bit
-* EL1 NS BSP.
-* 7.2 sd 02/23/20 Clock Init is called
-* 7.2 sd 02/23/20 Clock code added under XCLOCKING flag
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#include "xparameters.h"
-#include "bspconfig.h"
- .file "xil-crt0.S"
- .section ".got2","aw"
- .align 2
-
- .text
-.Lsbss_start:
- .quad __sbss_start
-
-.Lsbss_end:
- .quad __sbss_end
-
-.Lbss_start:
- .quad __bss_start__
-
-.Lbss_end:
- .quad __bss_end__
-
-
-.set APU_PWRCTL, 0xFD5C0090
-
- .globl _startup
-_startup:
-
- mov x0, #0
-.if (EL3 == 1)
- /* Check whether the clearing of bss sections shall be skipped */
- ldr x10, =APU_PWRCTL /* Load PWRCTRL address */
- ldr w11, [x10] /* Read PWRCTRL register */
- mrs x2, MPIDR_EL1 /* Read MPIDR_EL1 */
- ubfx x2, x2, #0, #8 /* Extract CPU ID (affinity level 0) */
- mov w1, #1
- lsl w2, w1, w2 /* Shift CPU ID to get one-hot ID */
- ands w11, w11, w2 /* Get PWRCTRL bit for this core */
- bne .Lenclbss /* Skip BSS and SBSS clearing */
-.endif
- /* clear sbss */
- ldr x1,.Lsbss_start /* calculate beginning of the SBSS */
- ldr x2,.Lsbss_end /* calculate end of the SBSS */
-
-.Lloop_sbss:
- cmp x1,x2
- bge .Lenclsbss /* If no SBSS, no clearing required */
- str x0, [x1], #8
- b .Lloop_sbss
-
-.Lenclsbss:
- /* clear bss */
- ldr x1,.Lbss_start /* calculate beginning of the BSS */
- ldr x2,.Lbss_end /* calculate end of the BSS */
-
-.Lloop_bss:
- cmp x1,x2
- bge .Lenclbss /* If no BSS, no clearing required */
- str x0, [x1], #8
- b .Lloop_bss
-
-.Lenclbss:
- /* run global constructors */
- bl __libc_init_array
-
- /* Reset and start Triple Timer Counter */
- #if defined (SLEEP_TIMER_BASEADDR)
- bl XTime_StartTTCTimer
- #endif
-
- .if (EL1_NONSECURE == 1 && HYP_GUEST == 1 && \
- XEN_USE_PV_CONSOLE == 1)
- bl XPVXenConsole_Init
- .endif
- /* make sure argc and argv are valid */
- mov x0, #0
- mov x1, #0
-
-#ifdef XCLOCKING
- bl Xil_ClockInit
-#endif
- bl main /* Jump to main C code */
-
- /* Cleanup global constructors */
- bl __libc_fini_array
-
- bl exit
-
-.Lexit: /* should never get here */
- b .Lexit
-
-.Lstart:
- .size _startup,.Lstart-_startup
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/60/3004f9575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/60/3004f9575243001d18b399c1eb9b3628
deleted file mode 100644
index 5feeb49..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/60/3004f9575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,39 +0,0 @@
-DRIVER_LIB_VERSION = 1.0
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I$(INCLUDEDIR)
-
-SRCFILES:=$(wildcard *.c)
-
-OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
-
-libs: $(OBJECTS)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf $(DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/60/30afbc525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/60/30afbc525243001d18b399c1eb9b3628
deleted file mode 100644
index 878d575..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/60/30afbc525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,261 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_misc_psreset_api.h
-*
-* This file contains the various register definitions and function prototypes for
-* implementing the reset functionality of zynq ps devices
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00b kpc 03/07/13 First release.
-*
-*
-******************************************************************************/
-
-#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */
-#define XIL_MISC_RESET_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/**
- *@cond nocomments
- */
-
-#define XDDRC_CTRL_BASEADDR 0xF8006000U
-#define XSLCR_BASEADDR 0xF8000000U
-/**< OCM configuration register */
-#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U)
-/**< SLCR unlock register */
-#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U)
-/**< SLCR GEM0 rx clock control register */
-#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U)
-/**< SLCR GEM1 rx clock control register */
-#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU)
-/**< SLCR GEM0 clock control register */
-#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U)
-/**< SLCR GEM1 clock control register */
-#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U)
-/**< SLCR SMC clock control register */
-#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U)
-/**< SLCR GEM reset control register */
-#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)
-/**< SLCR USB0 clock control register */
-#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U)
-/**< SLCR USB1 clock control register */
-#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U)
-/**< SLCR USB1 reset control register */
-#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)
-/**< SLCR SMC reset control register */
-#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)
-/**< SLCR Level shifter enable register */
-#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U)
-/**< SLCR ARM pll control register */
-#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U)
-/**< SLCR DDR pll control register */
-#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U)
-/**< SLCR IO pll control register */
-#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U)
-/**< SLCR ARM pll configuration register */
-#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U)
-/**< SLCR DDR pll configuration register */
-#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U)
-/**< SLCR IO pll configuration register */
-#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U)
-/**< SLCR ARM clock control register */
-#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U)
-/**< SLCR DDR clock control register */
-#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U)
-/**< SLCR MIO pin address register */
-#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U)
-/**< SLCR DMAC reset control address register */
-#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU)
-/**< SLCR USB reset control address register */
-/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/
-/**< SLCR GEM reset control address register */
-/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/
-/**< SLCR SDIO reset control address register */
-#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U)
-/**< SLCR SPI reset control address register */
-#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU)
-/**< SLCR CAN reset control address register */
-#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U)
-/**< SLCR I2C reset control address register */
-#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U)
-/**< SLCR UART reset control address register */
-#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U)
-/**< SLCR GPIO reset control address register */
-#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU)
-/**< SLCR LQSPI reset control address register */
-#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U)
-/**< SLCR SMC reset control address register */
-/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/
-/**< SLCR OCM reset control address register */
-#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U)
-
-/**< SMC mem controller clear config register */
-#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU
-/**< SMC idlecount configuration register */
-#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U
-#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U
-/**< SMC ECC configuration register */
-#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U
-/**< SMC ECC command 1 register */
-#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U
-/**< SMC ECC command 2 register */
-#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U
-
-/**< SLCR unlock code */
-#define XSLCR_UNLOCK_CODE 0x0000DF0DU
-
-/**< SMC mem clear configuration mask */
-#define XSMC_MEMC_CLR_CONFIG_MASK 0x000005FU
-/**< SMC ECC memconfig 1 reset value */
-#define XSMC_ECC_MEMCFG1_RESET_VAL 0x0000043U
-/**< SMC ECC memcommand 1 reset value */
-#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U
-/**< SMC ECC memcommand 2 reset value */
-#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U
-
-/**< DDR controller reset bit mask */
-#define XDDRPS_CTRL_RESET_MASK 0x00000001U
-/**< SLCR OCM configuration reset value*/
-#define XSLCR_OCM_CFG_RESETVAL 0x00000008U
-/**< SLCR OCM bank selection mask*/
-#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU
-/**< SLCR level shifter enable mask*/
-#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU
-
-/**< SLCR PLL register reset values */
-#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U
-#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U
-#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U
-#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U
-#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U
-#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U
-#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U
-#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U
-
-/**< SLCR MIO register default values */
-#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U
-#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U
-
-/**< SLCR Reset control registers default values */
-#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U
-#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U
-#define XSLCR_USB_RST_CTRL_VAL 0x00000003U
-#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U
-#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU
-#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU
-#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U
-#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U
-#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U
-#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U
-#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U
-#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U
-
-/**
- *@endcond
- */
-
-/**************************** Type Definitions *******************************/
-
-/* the following data type is used to hold a null terminated version string
- * consisting of the following format, "X.YYX"
- */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-/*
- * Performs reset operation to the ddr interface
- */
-void XDdr_ResetHw(void);
-/*
- * Map the ocm region to post bootrom state
- */
-void XOcm_Remap(void);
-/*
- * Performs the smc interface reset
- */
-void XSmc_ResetHw(u32 BaseAddress);
-/*
- * updates the MIO registers with reset values
- */
-void XSlcr_MioWriteResetValues(void);
-/*
- * updates the PLL and clock registers with reset values
- */
-void XSlcr_PllWriteResetValues(void);
-/*
- * Disables the level shifters
- */
-void XSlcr_DisableLevelShifters(void);
-/*
- * provides softreset to the GPIO interface
- */
-void XSlcr_GpioPsReset(void);
-/*
- * provides softreset to the DMA interface
- */
-void XSlcr_DmaPsReset(void);
-/*
- * provides softreset to the SMC interface
- */
-void XSlcr_SmcPsReset(void);
-/*
- * provides softreset to the CAN interface
- */
-void XSlcr_CanPsReset(void);
-/*
- * provides softreset to the Uart interface
- */
-void XSlcr_UartPsReset(void);
-/*
- * provides softreset to the I2C interface
- */
-void XSlcr_I2cPsReset(void);
-/*
- * provides softreset to the SPI interface
- */
-void XSlcr_SpiPsReset(void);
-/*
- * provides softreset to the QSPI interface
- */
-void XSlcr_QspiPsReset(void);
-/*
- * provides softreset to the USB interface
- */
-void XSlcr_UsbPsReset(void);
-/*
- * provides softreset to the GEM interface
- */
-void XSlcr_EmacPsReset(void);
-/*
- * provides softreset to the OCM interface
- */
-void XSlcr_OcmReset(void);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_MISC_RESET_H */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/60/6139ce595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/60/6139ce595243001d18b399c1eb9b3628
deleted file mode 100644
index 99727bc..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/60/6139ce595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,147 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xuartps_selftest.c
-* @addtogroup uartps_v3_11
-* @{
-*
-* This file contains the self-test functions for the XUartPs driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00 drg/jz 01/13/10 First Release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.9 sd 02/06/20 Added clock support
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xuartps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XUARTPS_TOTAL_BYTES (u8)32
-
-/************************** Variable Definitions *****************************/
-
-static u8 TestString[XUARTPS_TOTAL_BYTES]="abcdefghABCDEFGH012345677654321";
-static u8 ReturnString[XUARTPS_TOTAL_BYTES];
-
-/************************** Function Prototypes ******************************/
-
-
-/****************************************************************************/
-/**
-*
-* This function runs a self-test on the driver and hardware device. This self
-* test performs a local loopback and verifies data can be sent and received.
-*
-* The time for this test is proportional to the baud rate that has been set
-* prior to calling this function.
-*
-* The mode and control registers are restored before return.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-*
-* @return
-* - XST_SUCCESS if the test was successful
-* - XST_UART_TEST_FAIL if the test failed looping back the data
-*
-* @note
-*
-* This function can hang if the hardware is not functioning properly.
-*
-******************************************************************************/
-s32 XUartPs_SelfTest(XUartPs *InstancePtr)
-{
- s32 Status = XST_SUCCESS;
- u32 IntrRegister;
- u32 ModeRegister;
- u8 Index;
- u32 ReceiveDataResult;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-#if defined (XCLOCKING)
- Xil_ClockEnable(InstancePtr->Config.RefClk);
-#endif
-
- /* Disable all interrupts in the interrupt disable register */
- IntrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IMR_OFFSET);
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
- XUARTPS_IXR_MASK);
-
- /* Setup for local loopback */
- ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_MR_OFFSET);
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
- ((ModeRegister & (u32)(~XUARTPS_MR_CHMODE_MASK)) |
- (u32)XUARTPS_MR_CHMODE_L_LOOP));
-
- /* Send a number of bytes and receive them, one at a time. */
- for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
- /*
- * Send out the byte and if it was not sent then the failure
- * will be caught in the comparison at the end
- */
- (void)XUartPs_Send(InstancePtr, &TestString[Index], 1U);
-
- /*
- * Wait until the byte is received. This can hang if the HW
- * is broken. Watch for the FIFO empty flag to be false.
- */
- ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
- XUARTPS_SR_RXEMPTY;
- while (ReceiveDataResult == XUARTPS_SR_RXEMPTY ) {
- ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
- XUARTPS_SR_RXEMPTY;
- }
-
- /* Receive the byte */
- (void)XUartPs_Recv(InstancePtr, &ReturnString[Index], 1U);
- }
-
- /*
- * Compare the bytes received to the bytes sent to verify the exact data
- * was received
- */
- for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
- if (TestString[Index] != ReturnString[Index]) {
- Status = XST_UART_TEST_FAIL;
- }
- }
-
- /*
- * Restore the registers which were altered to put into polling and
- * loopback modes so that this test is not destructive
- */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
- IntrRegister);
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
- ModeRegister);
-
-#if defined (XCLOCKING)
- Xil_ClockDisable(InstancePtr->Config.RefClk);
-#endif
- return Status;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/60/80395e595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/60/80395e595243001d18b399c1eb9b3628
deleted file mode 100644
index fccfe4d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/60/80395e595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,67 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/*****************************************************************************/
-/**
-*
-* @file microblaze_exception_handler.c
-*
-* This file contains exception handler registration routines for
-* the MicroBlaze processor.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Date Changes
-* ----- -------- -----------------------------------------------
-* 1.00b 06/24/04 First release
-*
-*
-******************************************************************************/
-
-
-/***************************** Include Files *********************************/
-#include "microblaze_exceptions_i.h"
-#include "microblaze_exceptions_g.h"
-
-#ifdef MICROBLAZE_EXCEPTIONS_ENABLED /* If exceptions are enabled in the processor */
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-extern MB_ExceptionVectorTableEntry MB_ExceptionVectorTable[];
-/****************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* Registers an exception handler for the MicroBlaze. The
-* argument provided in this call as the DataPtr is used as the argument
-* for the handler when it is called.
-*
-* @param ExceptionId is the id of the exception to register this handler
-* for.
-* @param Top level handler.
-* @param DataPtr is a reference to data that will be passed to the handler
-* when it gets called.
-* @return None.
-*
-****************************************************************************/
-void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr)
-{
- MB_ExceptionVectorTable[ExceptionId].Handler = Handler;
- MB_ExceptionVectorTable[ExceptionId].CallBackRef = DataPtr;
-}
-
-#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/60/8093fc515243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/60/8093fc515243001d18b399c1eb9b3628
deleted file mode 100644
index 65e1ec0..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/60/8093fc515243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,3 +0,0 @@
-{
- "makefile.extensionOutputFolder": "./.vscode"
-}
\ No newline at end of file
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/61/61172d595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/61/61172d595243001d18b399c1eb9b3628
deleted file mode 100644
index 811d2b0..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/61/61172d595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,23 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#ifndef UNDEFINE_FILE_OPS
-#include "xil_types.h"
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) s32 _close(s32 fd);
-}
-#endif
-
-/*
- * close -- We don't need to do anything, but pretend we did.
- */
-
-__attribute__((weak)) s32 _close(s32 fd)
-{
- (void)fd;
- return (0);
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/62/508fe0565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/62/508fe0565243001d18b399c1eb9b3628
deleted file mode 100644
index 1f57654..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/62/508fe0565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,64 +0,0 @@
-/******************************************************************************/
-/**
-* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-* @file xil_mem.c
-*
-* This file contains xil mem copy function to use in case of word aligned
-* data copies.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.1 nsk 11/07/16 First release.
-*
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-
-/***************** Inline Functions Definitions ********************/
-/*****************************************************************************/
-/**
-* @brief This function copies memory from once location to other.
-*
-* @param dst: pointer pointing to destination memory
-*
-* @param src: pointer pointing to source memory
-*
-* @param cnt: 32 bit length of bytes to be copied
-*
-*****************************************************************************/
-void Xil_MemCpy(void* dst, const void* src, u32 cnt)
-{
- char *d = (char*)(void *)dst;
- const char *s = src;
-
- while (cnt >= sizeof (int)) {
- *(int*)d = *(int*)s;
- d += sizeof (int);
- s += sizeof (int);
- cnt -= sizeof (int);
- }
- while (cnt >= sizeof (u16)) {
- *(u16*)d = *(u16*)s;
- d += sizeof (u16);
- s += sizeof (u16);
- cnt -= sizeof (u16);
- }
- while ((cnt) > 0U){
- *d = *s;
- d += 1U;
- s += 1U;
- cnt -= 1U;
- }
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/62/70c5de575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/62/70c5de575243001d18b399c1eb9b3628
deleted file mode 100644
index a4e6192..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/62/70c5de575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,97 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xemacps_hw.c
-* @addtogroup emacps_v3_15
-* @{
-*
-* This file contains the implementation of the ethernet interface reset sequence
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.05a kpc 28/06/13 First release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xemacps_hw.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-* This function perform the reset sequence to the given emacps interface by
-* configuring the appropriate control bits in the emacps specific registers.
-* the emacps reset sequence involves the following steps
-* Disable all the interuupts
-* Clear the status registers
-* Disable Rx and Tx engines
-* Update the Tx and Rx descriptor queue registers with reset values
-* Update the other relevant control registers with reset value
-*
-* @param BaseAddr of the interface
-*
-* @return N/A
-*
-* @note
-* This function will not modify the slcr registers that are relevant for
-* emacps controller
-******************************************************************************/
-void XEmacPs_ResetHw(u32 BaseAddr)
-{
- u32 RegVal;
-
- /* Disable the interrupts */
- XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0U);
-
- /* Stop transmission,disable loopback and Stop tx and Rx engines */
- RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET);
- RegVal &= ~((u32)XEMACPS_NWCTRL_TXEN_MASK|
- (u32)XEMACPS_NWCTRL_RXEN_MASK|
- (u32)XEMACPS_NWCTRL_HALTTX_MASK|
- (u32)XEMACPS_NWCTRL_LOOPEN_MASK);
- /* Clear the statistic registers, flush the packets in DPRAM*/
- RegVal |= (XEMACPS_NWCTRL_STATCLR_MASK|
- XEMACPS_NWCTRL_FLUSH_DPRAM_MASK);
- XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCTRL_OFFSET,RegVal);
- /* Clear the interrupt status */
- XEmacPs_WriteReg(BaseAddr,XEMACPS_ISR_OFFSET,XEMACPS_IXR_ALL_MASK);
- /* Clear the tx status */
- XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,(XEMACPS_TXSR_ERROR_MASK|
- (u32)XEMACPS_TXSR_TXCOMPL_MASK|
- (u32)XEMACPS_TXSR_TXGO_MASK));
- /* Clear the rx status */
- XEmacPs_WriteReg(BaseAddr,XEMACPS_RXSR_OFFSET,
- XEMACPS_RXSR_FRAMERX_MASK);
- /* Clear the tx base address */
- XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0U);
- /* Clear the rx base address */
- XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0U);
- /* Update the network config register with reset value */
- XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCFG_OFFSET,XEMACPS_NWCFG_RESET_MASK);
- /* Update the hash address registers with reset value */
- XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0U);
- XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHH_OFFSET,0x0U);
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/62/808a12595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/62/808a12595243001d18b399c1eb9b3628
deleted file mode 100644
index 3438d96..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/62/808a12595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1 +0,0 @@
-collect (PROJECT_LIB_HEADERS xparameters_ps.h)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/62/b157cf535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/62/b157cf535243001d18b399c1eb9b3628
deleted file mode 100644
index d986349..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/62/b157cf535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,240 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm_gcc.h
-*
-* This header file contains macros for using inline assembler code. It is
-* written specifically for the GNU compiler.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/21/14 First release
-* 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors
-* 7.2 asa 04/03/20 Renamed the str macro to strw.
-* 7.2 dp 04/30/20 Added clobber "cc" to mtcpsr for aarch32 processors
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00 sdm 11/25/10 First release
-* 2.00a ka 07/25/12 Added a few register defines for CR 670297
-* and removed some defines of reserved fields for
-* CR 671468
-* Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
-* bit in Configuration register.
-* 2.01a sg 02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
-* which need write to clear. Removed Read zeros mask from
-* LQSPI Config register.
-* 2.03a hk 08/22/13 Added prototypes of API's for QSPI reset and
-* linear mode initialization for boot. Added related
-* constant definitions.
-* 3.1 hk 08/13/14 Changed definition of CR reset value masks to set/reset
-* required bits leaving reserved bits untouched. CR# 796813.
-* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
-* controller does not update FIFO status flags as expected
-* when thresholds are used.
-* 3.6 akm 03/28/19 Fixed memory leak issue while reading from qspi.(CR#1016357)
-*
-*
-*
-******************************************************************************/
-#ifndef XQSPIPS_HW_H /* prevent circular inclusions */
-#define XQSPIPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets from the base address of an QSPI device.
- * @{
- */
-#define XQSPIPS_CR_OFFSET 0x00 /**< Configuration Register */
-#define XQSPIPS_SR_OFFSET 0x04 /**< Interrupt Status */
-#define XQSPIPS_IER_OFFSET 0x08 /**< Interrupt Enable */
-#define XQSPIPS_IDR_OFFSET 0x0c /**< Interrupt Disable */
-#define XQSPIPS_IMR_OFFSET 0x10 /**< Interrupt Enabled Mask */
-#define XQSPIPS_ER_OFFSET 0x14 /**< Enable/Disable Register */
-#define XQSPIPS_DR_OFFSET 0x18 /**< Delay Register */
-#define XQSPIPS_TXD_00_OFFSET 0x1C /**< Transmit 4-byte inst/data */
-#define XQSPIPS_RXD_OFFSET 0x20 /**< Data Receive Register */
-#define XQSPIPS_SICR_OFFSET 0x24 /**< Slave Idle Count */
-#define XQSPIPS_TXWR_OFFSET 0x28 /**< Transmit FIFO Watermark */
-#define XQSPIPS_RXWR_OFFSET 0x2C /**< Receive FIFO Watermark */
-#define XQSPIPS_GPIO_OFFSET 0x30 /**< GPIO Register */
-#define XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38 /**< Loopback Delay Adjust Reg */
-#define XQSPIPS_TXD_01_OFFSET 0x80 /**< Transmit 1-byte inst */
-#define XQSPIPS_TXD_10_OFFSET 0x84 /**< Transmit 2-byte inst */
-#define XQSPIPS_TXD_11_OFFSET 0x88 /**< Transmit 3-byte inst */
-#define XQSPIPS_LQSPI_CR_OFFSET 0xA0 /**< Linear QSPI config register */
-#define XQSPIPS_LQSPI_SR_OFFSET 0xA4 /**< Linear QSPI status register */
-#define XQSPIPS_MOD_ID_OFFSET 0xFC /**< Module ID register */
-
-/* @} */
-
-/** @name Configuration Register
- *
- * This register contains various control bits that
- * affect the operation of the QSPI device. Read/Write.
- * @{
- */
-
-#define XQSPIPS_CR_IFMODE_MASK 0x80000000 /**< Flash mem interface mode */
-#define XQSPIPS_CR_ENDIAN_MASK 0x04000000 /**< Tx/Rx FIFO endianness */
-#define XQSPIPS_CR_MANSTRT_MASK 0x00010000 /**< Manual Transmission Start */
-#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start
- Enable */
-#define XQSPIPS_CR_SSFORCE_MASK 0x00004000 /**< Force Slave Select */
-#define XQSPIPS_CR_SSCTRL_MASK 0x00000400 /**< Slave Select Decode */
-#define XQSPIPS_CR_SSCTRL_SHIFT 10 /**< Slave Select Decode shift */
-#define XQSPIPS_CR_DATA_SZ_MASK 0x000000C0 /**< Size of word to be
- transferred */
-#define XQSPIPS_CR_PRESC_MASK 0x00000038 /**< Prescaler Setting */
-#define XQSPIPS_CR_PRESC_SHIFT 3 /**< Prescaler shift */
-#define XQSPIPS_CR_PRESC_MAXIMUM 0x07 /**< Prescaler maximum value */
-
-#define XQSPIPS_CR_CPHA_MASK 0x00000004 /**< Phase Configuration */
-#define XQSPIPS_CR_CPOL_MASK 0x00000002 /**< Polarity Configuration */
-
-#define XQSPIPS_CR_MSTREN_MASK 0x00000001 /**< Master Mode Enable */
-
-#define XQSPIPS_CR_HOLD_B_MASK 0x00080000 /**< HOLD_B Pin Drive Enable */
-
-#define XQSPIPS_CR_REF_CLK_MASK 0x00000100 /**< Ref clk bit - should be 0 */
-
-/* Deselect the Slave select line and set the transfer size to 32 at reset */
-#define XQSPIPS_CR_RESET_MASK_SET XQSPIPS_CR_IFMODE_MASK | \
- XQSPIPS_CR_SSCTRL_MASK | \
- XQSPIPS_CR_DATA_SZ_MASK | \
- XQSPIPS_CR_MSTREN_MASK | \
- XQSPIPS_CR_SSFORCE_MASK | \
- XQSPIPS_CR_HOLD_B_MASK
-#define XQSPIPS_CR_RESET_MASK_CLR XQSPIPS_CR_CPOL_MASK | \
- XQSPIPS_CR_CPHA_MASK | \
- XQSPIPS_CR_PRESC_MASK | \
- XQSPIPS_CR_MANSTRTEN_MASK | \
- XQSPIPS_CR_MANSTRT_MASK | \
- XQSPIPS_CR_ENDIAN_MASK | \
- XQSPIPS_CR_REF_CLK_MASK
-/* @} */
-
-
-/** @name QSPI Interrupt Registers
- *
- * QSPI Status Register
- *
- * This register holds the interrupt status flags for an QSPI device. Some
- * of the flags are level triggered, which means that they are set as long
- * as the interrupt condition exists. Other flags are edge triggered,
- * which means they are set once the interrupt condition occurs and remain
- * set until they are cleared by software. The interrupts are cleared by
- * writing a '1' to the interrupt bit position in the Status Register.
- * Read/Write.
- *
- * QSPI Interrupt Enable Register
- *
- * This register is used to enable chosen interrupts for an QSPI device.
- * Writing a '1' to a bit in this register sets the corresponding bit in the
- * QSPI Interrupt Mask register. Write only.
- *
- * QSPI Interrupt Disable Register
- *
- * This register is used to disable chosen interrupts for an QSPI device.
- * Writing a '1' to a bit in this register clears the corresponding bit in the
- * QSPI Interrupt Mask register. Write only.
- *
- * QSPI Interrupt Mask Register
- *
- * This register shows the enabled/disabled interrupts of an QSPI device.
- * Read only.
- *
- * All four registers have the same bit definitions. They are only defined once
- * for each of the Interrupt Enable Register, Interrupt Disable Register,
- * Interrupt Mask Register, and Channel Interrupt Status Register
- * @{
- */
-
-#define XQSPIPS_IXR_TXUF_MASK 0x00000040 /**< QSPI Tx FIFO Underflow */
-#define XQSPIPS_IXR_RXFULL_MASK 0x00000020 /**< QSPI Rx FIFO Full */
-#define XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010 /**< QSPI Rx FIFO Not Empty */
-#define XQSPIPS_IXR_TXFULL_MASK 0x00000008 /**< QSPI Tx FIFO Full */
-#define XQSPIPS_IXR_TXOW_MASK 0x00000004 /**< QSPI Tx FIFO Overwater */
-#define XQSPIPS_IXR_RXOVR_MASK 0x00000001 /**< QSPI Rx FIFO Overrun */
-#define XQSPIPS_IXR_DFLT_MASK 0x00000025 /**< QSPI default interrupts
- mask */
-#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041 /**< Interrupts which
- need write to clear */
-#define XQSPIPS_ISR_RESET_STATE 0x00000004 /**< Default to tx/rx empty */
-#define XQSPIPS_IXR_DISABLE_ALL 0x0000007D /**< Disable all interrupts */
-/* @} */
-
-
-/** @name Enable Register
- *
- * This register is used to enable or disable an QSPI device.
- * Read/Write
- * @{
- */
-#define XQSPIPS_ER_ENABLE_MASK 0x00000001 /**< QSPI Enable Bit Mask */
-/* @} */
-
-
-/** @name Delay Register
- *
- * This register is used to program timing delays in
- * slave mode. Read/Write
- * @{
- */
-#define XQSPIPS_DR_NSS_MASK 0xFF000000 /**< Delay to de-assert slave select
- between two words mask */
-#define XQSPIPS_DR_NSS_SHIFT 24 /**< Delay to de-assert slave select
- between two words shift */
-#define XQSPIPS_DR_BTWN_MASK 0x00FF0000 /**< Delay Between Transfers
- mask */
-#define XQSPIPS_DR_BTWN_SHIFT 16 /**< Delay Between Transfers shift */
-#define XQSPIPS_DR_AFTER_MASK 0x0000FF00 /**< Delay After Transfers mask */
-#define XQSPIPS_DR_AFTER_SHIFT 8 /**< Delay After Transfers shift */
-#define XQSPIPS_DR_INIT_MASK 0x000000FF /**< Delay Initially mask */
-/* @} */
-
-/** @name Slave Idle Count Registers
- *
- * This register defines the number of pclk cycles the slave waits for a the
- * QSPI clock to become stable in quiescent state before it can detect the start
- * of the next transfer in CPHA = 1 mode.
- * Read/Write
- *
- * @{
- */
-#define XQSPIPS_SICR_MASK 0x000000FF /**< Slave Idle Count Mask */
-/* @} */
-
-
-/** @name Transmit FIFO Watermark Register
- *
- * This register defines the watermark setting for the Transmit FIFO.
- *
- * @{
- */
-#define XQSPIPS_TXWR_MASK 0x0000003F /**< Transmit Watermark Mask */
-#define XQSPIPS_TXWR_RESET_VALUE 0x00000001 /**< Transmit Watermark
- * register reset value */
-
-/* @} */
-
-/** @name Receive FIFO Watermark Register
- *
- * This register defines the watermark setting for the Receive FIFO.
- *
- * @{
- */
-#define XQSPIPS_RXWR_MASK 0x0000003F /**< Receive Watermark Mask */
-#define XQSPIPS_RXWR_RESET_VALUE 0x00000001 /**< Receive Watermark
- * register reset value */
-
-/* @} */
-
-/** @name FIFO Depth
- *
- * This macro provides the depth of transmit FIFO and receive FIFO.
- *
- * @{
- */
-#define XQSPIPS_FIFO_DEPTH 63 /**< FIFO depth (words) */
-/* @} */
-
-
-/** @name Linear QSPI Configuration Register
- *
- * This register contains various control bits that
- * affect the operation of the Linear QSPI controller. Read/Write.
- *
- * @{
- */
-#define XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */
-#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */
-#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Separate memory bus */
-#define XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */
-#define XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */
-#define XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */
-#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O
- or quad I/O */
-#define XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700 /**< Number of dummy bytes
- between addr and return
- read data */
-#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */
-#define XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B /**< Default CR value */
-/* @} */
-
-/** @name Linear QSPI Status Register
- *
- * This register contains various status bits of the Linear QSPI controller.
- * Read/Write.
- *
- * @{
- */
-#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004 /**< AXI Data FSM Error
- received */
-#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002 /**< AXI write command
- received */
-/* @} */
-
-
-/** @name Loopback Delay Adjust Register
- *
- * This register contains various bit masks of Loopback Delay Adjust Register.
- *
- * @{
- */
-
-#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */
-
-/* @} */
-
-
-/** @name SLCR Register
- *
- * Register offsets from SLCR base address.
- *
- * @{
- */
-
-#define SLCR_LOCK 0x00000004 /**< SLCR Write Protection Lock */
-#define SLCR_UNLOCK 0x00000008 /**< SLCR Write Protection Unlock */
-#define LQSPI_RST_CTRL 0x00000230 /**< Quad SPI Software Reset Control */
-#define SLCR_LOCKSTA 0x0000000C /**< SLCR Write Protection status */
-
-/* @} */
-
-
-/** @name SLCR Register
- *
- * Bit Masks of above SLCR Registers .
- *
- * @{
- */
-
-#ifndef XPAR_XSLCR_0_BASEADDR
-#define XPAR_XSLCR_0_BASEADDR 0xF8000000
-#endif
-#define SLCR_LOCK_MASK 0x767B /**< Write Protection Lock mask*/
-#define SLCR_UNLOCK_MASK 0xDF0D /**< SLCR Write Protection Unlock */
-#define LQSPI_RST_CTRL_MASK 0x3 /**< Quad SPI Software Reset Control */
-
-/* @} */
-
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XQspiPs_In32 Xil_In32
-#define XQspiPs_Out32 Xil_Out32
-#define XQSPIPS_DUMMY_TX_DATA 0xFFFFFFFF
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-#define XQspiPs_ReadReg(BaseAddress, RegOffset) \
- XQspiPs_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u32 RegisterValue)
-*
-******************************************************************************/
-#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Functions implemented in xqspips_hw.c
- */
-void XQspiPs_ResetHw(u32 BaseAddress);
-void XQspiPs_LinearInit(u32 BaseAddress);
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/63/b125e9575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/63/b125e9575243001d18b399c1eb9b3628
deleted file mode 100644
index 6c47453..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/63/b125e9575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,99 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 2021.2
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2022 Xilinx, Inc. All Rights Reserved.
-* SPDX-License-Identifier: MIT
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xgpio.h"
-
-/*
-* The configuration table for devices
-*/
-
-XGpio_Config XGpio_ConfigTable[XPAR_XGPIO_NUM_INSTANCES] =
-{
- {
- XPAR_AXI_GPIO_0_DEVICE_ID,
- XPAR_AXI_GPIO_0_BASEADDR,
- XPAR_AXI_GPIO_0_INTERRUPT_PRESENT,
- XPAR_AXI_GPIO_0_IS_DUAL
- },
- {
- XPAR_AXI_GPIO_1_DEVICE_ID,
- XPAR_AXI_GPIO_1_BASEADDR,
- XPAR_AXI_GPIO_1_INTERRUPT_PRESENT,
- XPAR_AXI_GPIO_1_IS_DUAL
- },
- {
- XPAR_HIER_0_AXI_GPIO_0_DEVICE_ID,
- XPAR_HIER_0_AXI_GPIO_0_BASEADDR,
- XPAR_HIER_0_AXI_GPIO_0_INTERRUPT_PRESENT,
- XPAR_HIER_0_AXI_GPIO_0_IS_DUAL
- },
- {
- XPAR_HIER_1_AXI_GPIO_0_DEVICE_ID,
- XPAR_HIER_1_AXI_GPIO_0_BASEADDR,
- XPAR_HIER_1_AXI_GPIO_0_INTERRUPT_PRESENT,
- XPAR_HIER_1_AXI_GPIO_0_IS_DUAL
- },
- {
- XPAR_HIER_2_AXI_GPIO_0_DEVICE_ID,
- XPAR_HIER_2_AXI_GPIO_0_BASEADDR,
- XPAR_HIER_2_AXI_GPIO_0_INTERRUPT_PRESENT,
- XPAR_HIER_2_AXI_GPIO_0_IS_DUAL
- },
- {
- XPAR_HIER_3_AXI_GPIO_0_DEVICE_ID,
- XPAR_HIER_3_AXI_GPIO_0_BASEADDR,
- XPAR_HIER_3_AXI_GPIO_0_INTERRUPT_PRESENT,
- XPAR_HIER_3_AXI_GPIO_0_IS_DUAL
- },
- {
- XPAR_HIER_4_AXI_GPIO_0_DEVICE_ID,
- XPAR_HIER_4_AXI_GPIO_0_BASEADDR,
- XPAR_HIER_4_AXI_GPIO_0_INTERRUPT_PRESENT,
- XPAR_HIER_4_AXI_GPIO_0_IS_DUAL
- },
- {
- XPAR_HIER_5_AXI_GPIO_0_DEVICE_ID,
- XPAR_HIER_5_AXI_GPIO_0_BASEADDR,
- XPAR_HIER_5_AXI_GPIO_0_INTERRUPT_PRESENT,
- XPAR_HIER_5_AXI_GPIO_0_IS_DUAL
- },
- {
- XPAR_HIER_6_AXI_GPIO_0_DEVICE_ID,
- XPAR_HIER_6_AXI_GPIO_0_BASEADDR,
- XPAR_HIER_6_AXI_GPIO_0_INTERRUPT_PRESENT,
- XPAR_HIER_6_AXI_GPIO_0_IS_DUAL
- },
- {
- XPAR_HIER_7_AXI_GPIO_0_DEVICE_ID,
- XPAR_HIER_7_AXI_GPIO_0_BASEADDR,
- XPAR_HIER_7_AXI_GPIO_0_INTERRUPT_PRESENT,
- XPAR_HIER_7_AXI_GPIO_0_IS_DUAL
- },
- {
- XPAR_HIER_8_AXI_GPIO_0_DEVICE_ID,
- XPAR_HIER_8_AXI_GPIO_0_BASEADDR,
- XPAR_HIER_8_AXI_GPIO_0_INTERRUPT_PRESENT,
- XPAR_HIER_8_AXI_GPIO_0_IS_DUAL
- },
- {
- XPAR_HIER_9_AXI_GPIO_0_DEVICE_ID,
- XPAR_HIER_9_AXI_GPIO_0_BASEADDR,
- XPAR_HIER_9_AXI_GPIO_0_INTERRUPT_PRESENT,
- XPAR_HIER_9_AXI_GPIO_0_IS_DUAL
- }
-};
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/64/30a934545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/64/30a934545243001d18b399c1eb9b3628
deleted file mode 100644
index e8b87b5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/64/30a934545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,176 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_assert.h
-*
-* @addtogroup common_assert_apis Assert APIs and Macros
-*
-* The xil_assert.h file contains assert related functions and macros.
-* Assert APIs/Macros specifies that a application program satisfies certain
-* conditions at particular points in its execution. These function can be
-* used by application programs to ensure that, application code is satisfying
-* certain conditions.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 First release
-* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_ASSERT_H /* prevent circular inclusions */
-#define XIL_ASSERT_H /* by using protection macros */
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-
-
-/************************** Constant Definitions *****************************/
-
-#define XIL_ASSERT_NONE 0U
-#define XIL_ASSERT_OCCURRED 1U
-#define XNULL NULL
-
-extern u32 Xil_AssertStatus;
-extern s32 Xil_AssertWait;
-extern void Xil_Assert(const char8 *File, s32 Line);
-/**
- *@endcond
- */
-void XNullHandler(void *NullParameter);
-
-/**
- * This data type defines a callback to be invoked when an
- * assert occurs. The callback is invoked only when asserts are enabled
- */
-typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#ifndef NDEBUG
-
-/*****************************************************************************/
-/**
-* @brief This assert macro is to be used for void functions. This in
-* conjunction with the Xil_AssertWait boolean can be used to
-* accommodate tests so that asserts which fail allow execution to
-* continue.
-*
-* @param Expression: expression to be evaluated. If it evaluates to
-* false, the assert occurs.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertVoid(Expression) \
-{ \
- if (Expression) { \
- Xil_AssertStatus = XIL_ASSERT_NONE; \
- } else { \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* @brief This assert macro is to be used for functions that do return a
-* value. This in conjunction with the Xil_AssertWait boolean can be
-* used to accommodate tests so that asserts which fail allow execution
-* to continue.
-*
-* @param Expression: expression to be evaluated. If it evaluates to false,
-* the assert occurs.
-*
-* @return Returns 0 unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertNonvoid(Expression) \
-{ \
- if (Expression) { \
- Xil_AssertStatus = XIL_ASSERT_NONE; \
- } else { \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return 0; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* @brief Always assert. This assert macro is to be used for void functions.
-* Use for instances where an assert should always occur.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertVoidAlways() \
-{ \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return; \
-}
-
-/*****************************************************************************/
-/**
-* @brief Always assert. This assert macro is to be used for functions that
-* do return a value. Use for instances where an assert should always
-* occur.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertNonvoidAlways() \
-{ \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return 0; \
-}
-
-
-#else
-
-#define Xil_AssertVoid(Expression)
-#define Xil_AssertVoidAlways()
-#define Xil_AssertNonvoid(Expression)
-#define Xil_AssertNonvoidAlways()
-
-#endif
-
-/************************** Function Prototypes ******************************/
-
-void Xil_AssertSetCallback(Xil_AssertCallback Routine);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_assert_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/64/41e401555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/64/41e401555243001d18b399c1eb9b3628
deleted file mode 100644
index f2d44ce..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/64/41e401555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,28 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#ifndef UNDEFINE_FILE_OPS
-#include
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode);
-}
-#endif
-
-/*
- * _open -- open a file descriptor. We don't have a filesystem, so
- * we return an error.
- */
-__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode)
-{
- (void)buf;
- (void)flags;
- (void)mode;
- errno = EIO;
- return (-1);
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/64/a0449c545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/64/a0449c545243001d18b399c1eb9b3628
deleted file mode 100644
index df92a53..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/64/a0449c545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,487 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xemacps.c
-* @addtogroup emacps_v3_15
-* @{
-*
-* The XEmacPs driver. Functions in this file are the minimum required functions
-* for this driver. See xemacps.h for a detailed description of the driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 First release
-* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and
-* 64-bit changes.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.0 hk 02/20/15 Added support for jumbo frames. Increase AHB burst.
-* Disable extended mode. Perform all 64 bit changes under
-* check for arch64.
-* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr registers
-* 3.5 hk 08/14/17 Update cache coherency information of the interface in
-* its config structure.
-* 3.8 hk 09/17/18 Cleanup stale comments.
-* 3.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
-* 3.10 hk 05/16/19 Clear status registers properly in reset
-* 3.11 sd 02/14/20 Add clock support
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xemacps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-void XEmacPs_StubHandler(void); /* Default handler routine */
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-* Initialize a specific XEmacPs instance/driver. The initialization entails:
-* - Initialize fields of the XEmacPs instance structure
-* - Reset hardware and apply default options
-* - Configure the DMA channels
-*
-* The PHY is setup independently from the device. Use the MII or whatever other
-* interface may be present for setup.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param CfgPtr is the device configuration structure containing required
-* hardware build data.
-* @param EffectiveAddress is the base address of the device. If address
-* translation is not utilized, this parameter can be passed in using
-* CfgPtr->Config.BaseAddress to specify the physical base address.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-*
-******************************************************************************/
-LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
- UINTPTR EffectiveAddress)
-{
- /* Verify arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(CfgPtr != NULL);
-
- /* Set device base address and ID */
- InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
- InstancePtr->Config.BaseAddress = EffectiveAddress;
- InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent;
-#if defined (XCLOCKING)
- InstancePtr->Config.RefClk = CfgPtr->RefClk;
-#endif
-
- InstancePtr->Config.S1GDiv0 = CfgPtr->S1GDiv0;
- InstancePtr->Config.S1GDiv1 = CfgPtr->S1GDiv1;
- InstancePtr->Config.S100MDiv0 = CfgPtr->S100MDiv0;
- InstancePtr->Config.S100MDiv1 = CfgPtr->S100MDiv1;
- InstancePtr->Config.S10MDiv0 = CfgPtr->S10MDiv0;
- InstancePtr->Config.S10MDiv1 = CfgPtr->S10MDiv1;
-
- /* Set callbacks to an initial stub routine */
- InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler));
- InstancePtr->RecvHandler = ((XEmacPs_Handler)(void*)XEmacPs_StubHandler);
- InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void*)XEmacPs_StubHandler);
-
- /* Reset the hardware and set default options */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
- XEmacPs_Reset(InstancePtr);
-
- return (LONG)(XST_SUCCESS);
-}
-
-
-/*****************************************************************************/
-/**
-* Start the Ethernet controller as follows:
-* - Enable transmitter if XTE_TRANSMIT_ENABLE_OPTION is set
-* - Enable receiver if XTE_RECEIVER_ENABLE_OPTION is set
-* - Start the SG DMA send and receive channels and enable the device
-* interrupt
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return N/A
-*
-* @note
-* Hardware is configured with scatter-gather DMA, the driver expects to start
-* the scatter-gather channels and expects that the user has previously set up
-* the buffer descriptor lists.
-*
-* This function makes use of internal resources that are shared between the
-* Start, Stop, and Set/ClearOptions functions. So if one task might be setting
-* device options while another is trying to start the device, the user is
-* required to provide protection of this shared data (typically using a
-* semaphore).
-*
-* This function must not be preempted by an interrupt that may service the
-* device.
-*
-******************************************************************************/
-void XEmacPs_Start(XEmacPs *InstancePtr)
-{
- u32 Reg;
-
- /* Assert bad arguments and conditions */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-#if defined (XCLOCKING)
- if (InstancePtr->IsStarted != (u32)XIL_COMPONENT_IS_STARTED) {
- Xil_ClockEnable(InstancePtr->Config.RefClk);
- }
-#endif
-
- /* Start DMA */
- /* When starting the DMA channels, both transmit and receive sides
- * need an initialized BD list.
- */
- if (InstancePtr->Version == 2) {
- Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0);
- Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_RXQBASE_OFFSET,
- InstancePtr->RxBdRing.BaseBdAddr);
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_TXQBASE_OFFSET,
- InstancePtr->TxBdRing.BaseBdAddr);
- }
-
- /* clear any existed int status */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
- XEMACPS_IXR_ALL_MASK);
-
- /* Enable transmitter if not already enabled */
- if ((InstancePtr->Options & (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION)!=0x00000000U) {
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET);
- if ((!(Reg & XEMACPS_NWCTRL_TXEN_MASK))==TRUE) {
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET,
- Reg | (u32)XEMACPS_NWCTRL_TXEN_MASK);
- }
- }
-
- /* Enable receiver if not already enabled */
- if ((InstancePtr->Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET);
- if ((!(Reg & XEMACPS_NWCTRL_RXEN_MASK))==TRUE) {
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET,
- Reg | (u32)XEMACPS_NWCTRL_RXEN_MASK);
- }
- }
-
- /* Enable TX and RX interrupts */
- XEmacPs_IntEnable(InstancePtr, (XEMACPS_IXR_TX_ERR_MASK |
- XEMACPS_IXR_RX_ERR_MASK | (u32)XEMACPS_IXR_FRAMERX_MASK |
- (u32)XEMACPS_IXR_TXCOMPL_MASK));
-
- /* Enable TX Q1 Interrupts */
- if (InstancePtr->Version > 2)
- XEmacPs_IntQ1Enable(InstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK);
-
- /* Mark as started */
- InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
-
- return;
-}
-
-
-/*****************************************************************************/
-/**
-* Gracefully stop the Ethernet MAC as follows:
-* - Disable all interrupts from this device
-* - Stop DMA channels
-* - Disable the tansmitter and receiver
-*
-* Device options currently in effect are not changed.
-*
-* This function will disable all interrupts. Default interrupts settings that
-* had been enabled will be restored when XEmacPs_Start() is called.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @note
-* This function makes use of internal resources that are shared between the
-* Start, Stop, SetOptions, and ClearOptions functions. So if one task might be
-* setting device options while another is trying to start the device, the user
-* is required to provide protection of this shared data (typically using a
-* semaphore).
-*
-* Stopping the DMA channels causes this function to block until the DMA
-* operation is complete.
-*
-******************************************************************************/
-void XEmacPs_Stop(XEmacPs *InstancePtr)
-{
- u32 Reg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- /* Disable all interrupts */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
- XEMACPS_IXR_ALL_MASK);
-
- /* Disable the receiver & transmitter */
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET);
- Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
- Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET, Reg);
-
- /* Mark as stopped */
- InstancePtr->IsStarted = 0U;
-#if defined (XCLOCKING)
- Xil_ClockDisable(InstancePtr->Config.RefClk);
-#endif
-}
-
-
-/*****************************************************************************/
-/**
-* Perform a graceful reset of the Ethernet MAC. Resets the DMA channels, the
-* transmitter, and the receiver.
-*
-* Steps to reset
-* - Stops transmit and receive channels
-* - Stops DMA
-* - Configure transmit and receive buffer size to default
-* - Clear transmit and receive status register and counters
-* - Clear all interrupt sources
-* - Clear phy (if there is any previously detected) address
-* - Clear MAC addresses (1-4) as well as Type IDs and hash value
-*
-* All options are placed in their default state. Any frames in the
-* descriptor lists will remain in the lists. The side effect of doing
-* this is that after a reset and following a restart of the device, frames
-* were in the list before the reset may be transmitted or received.
-*
-* The upper layer software is responsible for re-configuring (if necessary)
-* and restarting the MAC after the reset. Note also that driver statistics
-* are not cleared on reset. It is up to the upper layer software to clear the
-* statistics if needed.
-*
-* When a reset is required, the driver notifies the upper layer software of
-* this need through the ErrorHandler callback and specific status codes.
-* The upper layer software is responsible for calling this Reset function
-* and then re-configuring the device.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-******************************************************************************/
-void XEmacPs_Reset(XEmacPs *InstancePtr)
-{
- u32 Reg;
- u8 i;
- s8 EmacPs_zero_MAC[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- /* Stop the device and reset hardware */
- XEmacPs_Stop(InstancePtr);
- InstancePtr->Options = XEMACPS_DEFAULT_OPTIONS;
-
- InstancePtr->Version = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, 0xFC);
-
- InstancePtr->Version = (InstancePtr->Version >> 16) & 0xFFF;
-
- InstancePtr->MaxMtuSize = XEMACPS_MTU;
- InstancePtr->MaxFrameSize = XEMACPS_MTU + XEMACPS_HDR_SIZE +
- XEMACPS_TRL_SIZE;
- InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
- XEMACPS_HDR_VLAN_SIZE;
- InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
-
- /* Setup hardware with default values */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET,
- (XEMACPS_NWCTRL_STATCLR_MASK |
- XEMACPS_NWCTRL_MDEN_MASK) &
- (u32)(~XEMACPS_NWCTRL_LOOPEN_MASK));
-
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCFG_OFFSET);
- Reg &= XEMACPS_NWCFG_MDCCLKDIV_MASK;
-
- Reg = Reg | (u32)XEMACPS_NWCFG_100_MASK |
- (u32)XEMACPS_NWCFG_FDEN_MASK |
- (u32)XEMACPS_NWCFG_UCASTHASHEN_MASK;
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCFG_OFFSET, Reg);
- if (InstancePtr->Version > 2) {
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET,
- (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET) |
- XEMACPS_NWCFG_DWIDTH_64_MASK));
- }
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_DMACR_OFFSET,
- (((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
- (((((u32)XEMACPS_RX_BUF_SIZE %
- (u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
- (u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
- (u32)(XEMACPS_DMACR_RXBUF_MASK)) |
- (u32)XEMACPS_DMACR_RXSIZE_MASK |
- (u32)XEMACPS_DMACR_TXSIZE_MASK);
-
-
- if (InstancePtr->Version > 2) {
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
- (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) |
-#if defined(__aarch64__) || defined(__arch64__)
- (u32)XEMACPS_DMACR_ADDR_WIDTH_64 |
-#endif
- (u32)XEMACPS_DMACR_INCR16_AHB_BURST));
- }
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_TXSR_OFFSET, XEMACPS_SR_ALL_MASK);
-
- XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_SEND);
- if (InstancePtr->Version > 2)
- XEmacPs_SetQueuePtr(InstancePtr, 0, 0x01U, (u16)XEMACPS_SEND);
- XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_RECV);
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_RXSR_OFFSET, XEMACPS_SR_ALL_MASK);
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
- XEMACPS_IXR_ALL_MASK);
-
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_ISR_OFFSET);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
- Reg);
-
- XEmacPs_ClearHash(InstancePtr);
-
- for (i = 1U; i < 5U; i++) {
- (void)XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i);
- (void)XEmacPs_SetTypeIdCheck(InstancePtr, 0x00000000U, i);
- }
-
- /* clear all counters */
- for (i = 0U; i < (u8)((XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4U);
- i++) {
- (void)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_OCTTXL_OFFSET + (u32)(((u32)i) * ((u32)4)));
- }
-
- /* Disable the receiver */
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET);
- Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET, Reg);
-
- /* Sync default options with hardware but leave receiver and
- * transmitter disabled. They get enabled with XEmacPs_Start() if
- * XEMACPS_TRANSMITTER_ENABLE_OPTION and
- * XEMACPS_RECEIVER_ENABLE_OPTION are set.
- */
- (void)XEmacPs_SetOptions(InstancePtr, InstancePtr->Options &
- ~((u32)XEMACPS_TRANSMITTER_ENABLE_OPTION |
- (u32)XEMACPS_RECEIVER_ENABLE_OPTION));
-
- (void)XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options);
-}
-
-
-/******************************************************************************/
-/**
- * This is a stub for the asynchronous callbacks. The stub is here in case the
- * upper layer forgot to set the handler(s). On initialization, all handlers are
- * set to this callback. It is considered an error for this handler to be
- * invoked.
- *
- ******************************************************************************/
-void XEmacPs_StubHandler(void)
-{
- Xil_AssertVoidAlways();
-}
-
-/*****************************************************************************/
-/**
-* This function sets the start address of the transmit/receive buffer queue.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param QPtr is the address of the Queue to be written
-* @param QueueNum is the Buffer Queue Index
-* @param Direction indicates Transmit/Receive
-*
-* @note
-* The buffer queue addresses has to be set before starting the transfer, so
-* this function has to be called in prior to XEmacPs_Start()
-*
-******************************************************************************/
-void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
- u16 Direction)
-{
- /* Assert bad arguments and conditions */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- /* If already started, then there is nothing to do */
- if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
- return;
- }
-
- if (QueueNum == 0x00U) {
- if (Direction == XEMACPS_SEND) {
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_TXQBASE_OFFSET,
- (QPtr & ULONG64_LO_MASK));
- } else {
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_RXQBASE_OFFSET,
- (QPtr & ULONG64_LO_MASK));
- }
- }
- else {
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_TXQ1BASE_OFFSET,
- (QPtr & ULONG64_LO_MASK));
- }
-#ifdef __aarch64__
- if (Direction == XEMACPS_SEND) {
- /* Set the MSB of TX Queue start address */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_MSBBUF_TXQBASE_OFFSET,
- (u32)((QPtr & ULONG64_HI_MASK) >> 32U));
- } else {
- /* Set the MSB of RX Queue start address */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_MSBBUF_RXQBASE_OFFSET,
- (u32)((QPtr & ULONG64_HI_MASK) >> 32U));
- }
-#endif
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/64/f0e246525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/64/f0e246525243001d18b399c1eb9b3628
deleted file mode 100644
index df9a66a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/64/f0e246525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,655 +0,0 @@
-2022-07-31T18:23:51.933756 0 0 255 - 18:23:51 **** Build of project phased_array_platform ****
- 0 0 0 - buildplatform.sh 35709 phased_array_platform
- 0 0 0 - XSDB Server Channel: tcfchan#1
- 0 0 0 - Reading the platform : "phased_array_platform"
- 0 0 0 - Building the zynq_fsbl application.
- 0 0 0 - make: Entering directory '/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp'
- 0 0 0 -
- 0 0 0 - make --no-print-directory seq_libs
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_9/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/gpiops_v3_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
- 0 0 0 - -as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
- 0 0 0 - nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/sdps_v3_13/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/sdps_v3_13/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
- 0 0 0 - as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
- 0 0 0 - ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_4/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/scuwdt_v2_4/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
- 0 0 0 - -as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
- 0 0 0 - nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_7/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/devcfg_v3_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
- 0 0 0 - -as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
- 0 0 0 - nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/scugic_v4_6/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/scugic_v4_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
- 0 0 0 - -as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
- 0 0 0 - nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/xilrsa_v1_6/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/xilrsa_v1_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
- 0 0 0 - -as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
- 0 0 0 - nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/xilffs_v4_6/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/xilffs_v4_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
- 0 0 0 - -as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
- 0 0 0 - nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_11/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/uartps_v3_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab
- 0 0 0 - i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
- 0 0 0 - -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/gpio_v4_8/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/gpio_v4_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a
- 0 0 0 - s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no
- 0 0 0 - startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/standalone_v7_6/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/standalone_v7_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-
- 0 0 0 - eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha
- 0 0 0 - rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_15/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/emacps_v3_15/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab
- 0 0 0 - i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
- 0 0 0 - -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/usbps_v2_7/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/usbps_v2_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
- 0 0 0 - as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
- 0 0 0 - ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-
- 0 0 0 - none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-a
- 0 0 0 - bi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_2/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
- 0 0 0 - as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
- 0 0 0 - ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_6/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/xadcps_v2_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
- 0 0 0 - -as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
- 0 0 0 - nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-no
- 0 0 0 - ne-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi
- 0 0 0 - =hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_9/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/qspips_v3_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
- 0 0 0 - -as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
- 0 0 0 - nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_8/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/dmaps_v2_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
- 0 0 0 - as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
- 0 0 0 - ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_3/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/scutimer_v2_3/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-ea
- 0 0 0 - bi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
- 0 0 0 - -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/xilrsa_v1_6/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/xilrsa_v1_6/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
- 0 0 0 - " "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
- 0 0 0 - tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Finished building libraries sequentially.
- 0 0 0 -
- 0 0 0 - make -j 6 --no-print-directory par_libs
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_9/src
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/sdps_v3_13/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/gpiops_v3_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
- 0 0 0 - -as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
- 0 0 0 - nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_4/src
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_7/src
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/scugic_v4_6/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/sdps_v3_13/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
- 0 0 0 - as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
- 0 0 0 - ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/xilrsa_v1_6/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/scuwdt_v2_4/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
- 0 0 0 - -as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
- 0 0 0 - nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/devcfg_v3_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
- 0 0 0 - -as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
- 0 0 0 - nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/scugic_v4_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
- 0 0 0 - -as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
- 0 0 0 - nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/xilrsa_v1_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
- 0 0 0 - -as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
- 0 0 0 - nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_11/src
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/xilffs_v4_6/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/xilffs_v4_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
- 0 0 0 - -as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
- 0 0 0 - nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/gpio_v4_8/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/uartps_v3_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab
- 0 0 0 - i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
- 0 0 0 - -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/gpio_v4_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a
- 0 0 0 - s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no
- 0 0 0 - startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/standalone_v7_6/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/standalone_v7_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-
- 0 0 0 - eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha
- 0 0 0 - rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_15/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/emacps_v3_15/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab
- 0 0 0 - i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
- 0 0 0 - -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/usbps_v2_7/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/usbps_v2_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
- 0 0 0 - as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
- 0 0 0 - ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-
- 0 0 0 - none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-a
- 0 0 0 - bi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_2/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
- 0 0 0 - as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
- 0 0 0 - ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_6/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/xadcps_v2_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
- 0 0 0 - -as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
- 0 0 0 - nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-no
- 0 0 0 - ne-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi
- 0 0 0 - =hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_9/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/qspips_v3_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
- 0 0 0 - -as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
- 0 0 0 - nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_8/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/dmaps_v2_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
- 0 0 0 - as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
- 0 0 0 - ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_3/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/scutimer_v2_3/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-ea
- 0 0 0 - bi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
- 0 0 0 - -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/gpiops_v3_9/src
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/sdps_v3_13/src
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/scuwdt_v2_4/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/gpiops_v3_9/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
- 0 0 0 - " "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
- 0 0 0 - tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/sdps_v3_13/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
- 0 0 0 - "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost
- 0 0 0 - artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/scuwdt_v2_4/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
- 0 0 0 - " "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
- 0 0 0 - tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/scugic_v4_6/src
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/devcfg_v3_7/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/scugic_v4_6/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
- 0 0 0 - " "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
- 0 0 0 - tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/devcfg_v3_7/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
- 0 0 0 - " "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
- 0 0 0 - tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/xilffs_v4_6/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/xilffs_v4_6/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
- 0 0 0 - " "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
- 0 0 0 - tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/uartps_v3_11/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/uartps_v3_11/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a
- 0 0 0 - s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no
- 0 0 0 - startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/gpio_v4_8/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/gpio_v4_8/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
- 0 0 0 - "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta
- 0 0 0 - rtfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/standalone_v7_6/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/standalone_v7_6/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab
- 0 0 0 - i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
- 0 0 0 - -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/emacps_v3_15/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/emacps_v3_15/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a
- 0 0 0 - s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no
- 0 0 0 - startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/usbps_v2_7/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/usbps_v2_7/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
- 0 0 0 - "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost
- 0 0 0 - artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-non
- 0 0 0 - e-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=
- 0 0 0 - hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/ddrps_v1_2/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
- 0 0 0 - "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost
- 0 0 0 - artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/xadcps_v2_6/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/xadcps_v2_6/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
- 0 0 0 - " "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
- 0 0 0 - tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-
- 0 0 0 - eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha
- 0 0 0 - rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/qspips_v3_9/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/qspips_v3_9/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
- 0 0 0 - " "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
- 0 0 0 - tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/dmaps_v2_8/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/dmaps_v2_8/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
- 0 0 0 - "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost
- 0 0 0 - artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/scutimer_v2_3/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/scutimer_v2_3/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
- 0 0 0 - as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
- 0 0 0 - ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Finished building libraries parallelly.
- 0 0 0 -
- 0 0 0 - make --no-print-directory archive
- 0 0 0 -
- 0 0 0 - arm-none-eabi-ar -r ps7_cortexa9_0/lib/libxil.a ps7_cortexa9_0/lib/open.o ps7_cortexa9_0/lib/xemacps_control.o ps7_cortexa9_0/
- 0 0 0 - lib/xgpio.o ps7_cortexa9_0/lib/xil_exception.o ps7_cortexa9_0/lib/xqspips_selftest.o ps7_cortexa9_0/lib/xdevcfg_sinit.o ps7_cor
- 0 0 0 - texa9_0/lib/lseek.o ps7_cortexa9_0/lib/xsdps_sinit.o ps7_cortexa9_0/lib/xusbps_endpoint.o ps7_cortexa9_0/lib/xusbps.o ps7_corte
- 0 0 0 - xa9_0/lib/xqspips_g.o ps7_cortexa9_0/lib/xemacps_sinit.o ps7_cortexa9_0/lib/_sbrk.o ps7_cortexa9_0/lib/xpm_counter.o ps7_cortex
- 0 0 0 - a9_0/lib/xcoresightpsdcc.o ps7_cortexa9_0/lib/xscutimer.o ps7_cortexa9_0/lib/xemacps_hw.o ps7_cortexa9_0/lib/getpid.o ps7_corte
- 0 0 0 - xa9_0/lib/xscugic_intr.o ps7_cortexa9_0/lib/abort.o ps7_cortexa9_0/lib/usleep.o ps7_cortexa9_0/lib/asm_vectors.o ps7_cortexa9_0
- 0 0 0 - /lib/xl2cc_counter.o ps7_cortexa9_0/lib/xgpiops.o ps7_cortexa9_0/lib/xil_testmem.o ps7_cortexa9_0/lib/xgpiops_hw.o ps7_cortexa9
- 0 0 0 - _0/lib/outbyte.o ps7_cortexa9_0/lib/xuartps_selftest.o ps7_cortexa9_0/lib/xuartps_sinit.o ps7_cortexa9_0/lib/xadcps.o ps7_corte
- 0 0 0 - xa9_0/lib/xuartps_g.o ps7_cortexa9_0/lib/kill.o ps7_cortexa9_0/lib/xil_printf.o ps7_cortexa9_0/lib/time.o ps7_cortexa9_0/lib/xg
- 0 0 0 - pio_sinit.o ps7_cortexa9_0/lib/xil_clocking.o ps7_cortexa9_0/lib/xscuwdt.o ps7_cortexa9_0/lib/xgpio_g.o ps7_cortexa9_0/lib/xgpi
- 0 0 0 - ops_selftest.o ps7_cortexa9_0/lib/xgpiops_sinit.o ps7_cortexa9_0/lib/xemacps_g.o ps7_cortexa9_0/lib/close.o ps7_cortexa9_0/lib/
- 0 0 0 - xsdps.o ps7_cortexa9_0/lib/xusbps_g.o ps7_cortexa9_0/lib/xadcps_intr.o ps7_cortexa9_0/lib/xscutimer_selftest.o ps7_cortexa9_0/l
- 0 0 0 - ib/xdmaps_selftest.o ps7_cortexa9_0/lib/inbyte.o ps7_cortexa9_0/lib/xscutimer_sinit.o ps7_cortexa9_0/lib/xdmaps_sinit.o ps7_cor
- 0 0 0 - texa9_0/lib/xil_misc_psreset_api.o ps7_cortexa9_0/lib/xsdps_options.o ps7_cortexa9_0/lib/xscutimer_g.o ps7_cortexa9_0/lib/xdmap
- 0 0 0 - s_g.o ps7_cortexa9_0/lib/xqspips_options.o ps7_cortexa9_0/lib/xil_sleeptimer.o ps7_cortexa9_0/lib/xdevcfg_hw.o ps7_cortexa9_0/l
- 0 0 0 - ib/unlink.o ps7_cortexa9_0/lib/xusbps_sinit.o ps7_cortexa9_0/lib/sleep.o ps7_cortexa9_0/lib/xil_mem.o ps7_cortexa9_0/lib/xplatf
- 0 0 0 - orm_info.o ps7_cortexa9_0/lib/xadcps_selftest.o ps7_cortexa9_0/lib/xil_testcache.o ps7_cortexa9_0/lib/xgpio_selftest.o ps7_cort
- 0 0 0 - exa9_0/lib/xil_mmu.o ps7_cortexa9_0/lib/xadcps_sinit.o ps7_cortexa9_0/lib/xqspips_sinit.o ps7_cortexa9_0/lib/xgpiops_g.o ps7_co
- 0 0 0 - rtexa9_0/lib/xadcps_g.o ps7_cortexa9_0/lib/xscugic.o ps7_cortexa9_0/lib/xil-crt0.o ps7_cortexa9_0/lib/isatty.o ps7_cortexa9_0/l
- 0 0 0 - ib/xgpio_extra.o ps7_cortexa9_0/lib/xscuwdt_selftest.o ps7_cortexa9_0/lib/xemacps_intr.o ps7_cortexa9_0/lib/_exit.o ps7_cortexa
- 0 0 0 - 9_0/lib/xscuwdt_g.o ps7_cortexa9_0/lib/vectors.o ps7_cortexa9_0/lib/xsdps_g.o ps7_cortexa9_0/lib/xuartps_options.o ps7_cortexa9
- 0 0 0 - _0/lib/xdevcfg_intr.o ps7_cortexa9_0/lib/errno.o ps7_cortexa9_0/lib/xqspips_hw.o ps7_cortexa9_0/lib/fstat.o ps7_cortexa9_0/lib/
- 0 0 0 - xusbps_hw.o ps7_cortexa9_0/lib/sbrk.o ps7_cortexa9_0/lib/xdmaps_hw.o ps7_cortexa9_0/lib/xsdps_card.o ps7_cortexa9_0/lib/xuartps
- 0 0 0 - _intr.o ps7_cortexa9_0/lib/xil_util.o ps7_cortexa9_0/lib/xscugic_selftest.o ps7_cortexa9_0/lib/xdmaps.o ps7_cortexa9_0/lib/xtim
- 0 0 0 - e_l.o ps7_cortexa9_0/lib/read.o ps7_cortexa9_0/lib/xgpio_intr.o ps7_cortexa9_0/lib/xscuwdt_sinit.o ps7_cortexa9_0/lib/putnum.o
- 0 0 0 - ps7_cortexa9_0/lib/xdevcfg_g.o ps7_cortexa9_0/lib/xscugic_sinit.o ps7_cortexa9_0/lib/xgpiops_intr.o ps7_cortexa9_0/lib/xscugic_
- 0 0 0 - g.o ps7_cortexa9_0/lib/xil_sleepcommon.o ps7_cortexa9_0/lib/cpu_init.o ps7_cortexa9_0/lib/xemacps_bdring.o ps7_cortexa9_0/lib/b
- 0 0 0 - oot.o ps7_cortexa9_0/lib/write.o ps7_cortexa9_0/lib/translation_table.o ps7_cortexa9_0/lib/xil_spinlock.o ps7_cortexa9_0/lib/xq
- 0 0 0 - spips.o ps7_cortexa9_0/lib/xil_testio.o ps7_cortexa9_0/lib/xil_cache.o ps7_cortexa9_0/lib/xemacps.o ps7_cortexa9_0/lib/xdevcfg_
- 0 0 0 - selftest.o ps7_cortexa9_0/lib/xdevcfg.o ps7_cortexa9_0/lib/xuartps_hw.o ps7_cortexa9_0/lib/print.o ps7_cortexa9_0/lib/fcntl.o p
- 0 0 0 - s7_cortexa9_0/lib/_open.o ps7_cortexa9_0/lib/cpputest_time.o ps7_cortexa9_0/lib/xuartps.o ps7_cortexa9_0/lib/xscugic_hw.o ps7_c
- 0 0 0 - ortexa9_0/lib/xsdps_host.o ps7_cortexa9_0/lib/xusbps_intr.o ps7_cortexa9_0/lib/xil_assert.o
- 0 0 0 -
- 0 0 0 - Finished building libraries
- 0 0 0 -
- 0 0 0 - make: Leaving directory '/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp'
- 0 0 0 -
- 0 0 0 - arm-none-eabi-gcc -o fsbl.elf fsbl_handoff.o fsbl_hooks.o image_mover.o main.o md5.o nand.o nor.o pcap.o ps7_init.o qspi.o rsa.
- 0 0 0 - o sd.o -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id
- 0 0 0 - =none -specs=Xilinx.spec -lrsa -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilffs,-lxil,-lgcc,-lc,--end-
- 0 0 0 - group -Wl,--start-group,-lrsa,-lxil,-lgcc,-lc,--end-group -Wl,--gc-sections -Lzyn
- 0 0 0 - q_fsbl_bsp/ps7_cortexa9_0/lib -L./ -Tlscript.ld
- 0 0 0 -
- 0 0 0 - Building the BSP Library for domain - standalone_domain on processor ps7_cortexa9_0
- 0 0 0 - make --no-print-directory seq_libs
- 0 0 0 -
- 0 0 0 - Finished building libraries sequentially.
- 0 0 0 -
- 0 0 0 - make -j 6 --no-print-directory par_libs
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_9/src
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/sdps_v3_13/src
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_4/src
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_7/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/gpiops_v3_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
- 0 0 0 - -as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
- 0 0 0 - nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/sdps_v3_13/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
- 0 0 0 - as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
- 0 0 0 - ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/scuwdt_v2_4/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
- 0 0 0 - -as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
- 0 0 0 - nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/scugic_v4_6/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/devcfg_v3_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
- 0 0 0 - -as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
- 0 0 0 - nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_15/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/scugic_v4_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
- 0 0 0 - -as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
- 0 0 0 - nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/emacps_v3_15/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab
- 0 0 0 - i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
- 0 0 0 - -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_11/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/uartps_v3_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab
- 0 0 0 - i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
- 0 0 0 - -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/gpio_v4_8/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/gpio_v4_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a
- 0 0 0 - s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no
- 0 0 0 - startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/standalone_v7_6/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/standalone_v7_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-
- 0 0 0 - eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha
- 0 0 0 - rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-
- 0 0 0 - none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-a
- 0 0 0 - bi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/usbps_v2_7/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/usbps_v2_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
- 0 0 0 - as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
- 0 0 0 - ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_2/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
- 0 0 0 - as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
- 0 0 0 - ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_6/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/xadcps_v2_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
- 0 0 0 - -as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
- 0 0 0 - nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-no
- 0 0 0 - ne-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi
- 0 0 0 - =hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_9/src
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_8/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/qspips_v3_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
- 0 0 0 - -as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
- 0 0 0 - nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/dmaps_v2_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
- 0 0 0 - as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
- 0 0 0 - ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_3/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/scutimer_v2_3/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-ea
- 0 0 0 - bi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
- 0 0 0 - -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/gpiops_v3_9/src
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/sdps_v3_13/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/gpiops_v3_9/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
- 0 0 0 - " "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
- 0 0 0 - tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/scuwdt_v2_4/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/scuwdt_v2_4/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
- 0 0 0 - " "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
- 0 0 0 - tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/devcfg_v3_7/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/sdps_v3_13/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
- 0 0 0 - "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost
- 0 0 0 - artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/devcfg_v3_7/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
- 0 0 0 - " "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
- 0 0 0 - tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/emacps_v3_15/src
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/scugic_v4_6/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/scugic_v4_6/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
- 0 0 0 - " "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
- 0 0 0 - tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/emacps_v3_15/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a
- 0 0 0 - s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no
- 0 0 0 - startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/uartps_v3_11/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/uartps_v3_11/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a
- 0 0 0 - s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no
- 0 0 0 - startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/gpio_v4_8/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/gpio_v4_8/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
- 0 0 0 - "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta
- 0 0 0 - rtfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/standalone_v7_6/src
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/usbps_v2_7/src
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/ddrps_v1_2/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/standalone_v7_6/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab
- 0 0 0 - i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
- 0 0 0 - -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/usbps_v2_7/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
- 0 0 0 - "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost
- 0 0 0 - artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-non
- 0 0 0 - e-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=
- 0 0 0 - hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
- 0 0 0 - "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost
- 0 0 0 - artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/xadcps_v2_6/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/xadcps_v2_6/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
- 0 0 0 - " "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
- 0 0 0 - tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/qspips_v3_9/src
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/qspips_v3_9/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
- 0 0 0 - " "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
- 0 0 0 - tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-
- 0 0 0 - eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha
- 0 0 0 - rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/dmaps_v2_8/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/dmaps_v2_8/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
- 0 0 0 - "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost
- 0 0 0 - artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Running Make libs in ps7_cortexa9_0/libsrc/scutimer_v2_3/src
- 0 0 0 -
- 0 0 0 - make -C ps7_cortexa9_0/libsrc/scutimer_v2_3/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
- 0 0 0 - as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
- 0 0 0 - ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
- 0 0 0 -
- 0 0 0 - Finished building libraries parallelly.
- 0 0 0 -
- 0 0 0 - make --no-print-directory archive
- 0 0 0 -
- 0 0 0 - arm-none-eabi-ar -r ps7_cortexa9_0/lib/libxil.a ps7_cortexa9_0/lib/open.o ps7_cortexa9_0/lib/xemacps_control.o ps7_cortexa9_0/
- 0 0 0 - lib/xgpio.o ps7_cortexa9_0/lib/xil_exception.o ps7_cortexa9_0/lib/xqspips_selftest.o ps7_cortexa9_0/lib/xdevcfg_sinit.o ps7_cor
- 0 0 0 - texa9_0/lib/lseek.o ps7_cortexa9_0/lib/xsdps_sinit.o ps7_cortexa9_0/lib/xusbps_endpoint.o ps7_cortexa9_0/lib/xusbps.o ps7_corte
- 0 0 0 - xa9_0/lib/xqspips_g.o ps7_cortexa9_0/lib/xemacps_sinit.o ps7_cortexa9_0/lib/_sbrk.o ps7_cortexa9_0/lib/xpm_counter.o ps7_cortex
- 0 0 0 - a9_0/lib/xcoresightpsdcc.o ps7_cortexa9_0/lib/xscutimer.o ps7_cortexa9_0/lib/xemacps_hw.o ps7_cortexa9_0/lib/getpid.o ps7_corte
- 0 0 0 - xa9_0/lib/xscugic_intr.o ps7_cortexa9_0/lib/abort.o ps7_cortexa9_0/lib/usleep.o ps7_cortexa9_0/lib/asm_vectors.o ps7_cortexa9_0
- 0 0 0 - /lib/xl2cc_counter.o ps7_cortexa9_0/lib/xgpiops.o ps7_cortexa9_0/lib/xil_testmem.o ps7_cortexa9_0/lib/xgpiops_hw.o ps7_cortexa9
- 0 0 0 - _0/lib/xuartps_selftest.o ps7_cortexa9_0/lib/xuartps_sinit.o ps7_cortexa9_0/lib/xadcps.o ps7_cortexa9_0/lib/xuartps_g.o ps7_cor
- 0 0 0 - texa9_0/lib/kill.o ps7_cortexa9_0/lib/xil_printf.o ps7_cortexa9_0/lib/time.o ps7_cortexa9_0/lib/xgpio_sinit.o ps7_cortexa9_0/li
- 0 0 0 - b/xil_clocking.o ps7_cortexa9_0/lib/xscuwdt.o ps7_cortexa9_0/lib/xgpio_g.o ps7_cortexa9_0/lib/xgpiops_selftest.o ps7_cortexa9_0
- 0 0 0 - /lib/xgpiops_sinit.o ps7_cortexa9_0/lib/xemacps_g.o ps7_cortexa9_0/lib/close.o ps7_cortexa9_0/lib/xsdps.o ps7_cortexa9_0/lib/xu
- 0 0 0 - sbps_g.o ps7_cortexa9_0/lib/xadcps_intr.o ps7_cortexa9_0/lib/putnum.o ps7_cortexa9_0/lib/xscutimer_selftest.o ps7_cortexa9_0/li
- 0 0 0 - b/xdmaps_selftest.o ps7_cortexa9_0/lib/inbyte.o ps7_cortexa9_0/lib/xscutimer_sinit.o ps7_cortexa9_0/lib/xdmaps_sinit.o ps7_cort
- 0 0 0 - exa9_0/lib/xil_misc_psreset_api.o ps7_cortexa9_0/lib/xsdps_options.o ps7_cortexa9_0/lib/xscutimer_g.o ps7_cortexa9_0/lib/xdmaps
- 0 0 0 - _g.o ps7_cortexa9_0/lib/xqspips_options.o ps7_cortexa9_0/lib/xil_sleeptimer.o ps7_cortexa9_0/lib/xdevcfg_hw.o ps7_cortexa9_0/li
- 0 0 0 - b/unlink.o ps7_cortexa9_0/lib/xusbps_sinit.o ps7_cortexa9_0/lib/sleep.o ps7_cortexa9_0/lib/xil_mem.o ps7_cortexa9_0/lib/xplatfo
- 0 0 0 - rm_info.o ps7_cortexa9_0/lib/xadcps_selftest.o ps7_cortexa9_0/lib/xil_testcache.o ps7_cortexa9_0/lib/xgpio_selftest.o ps7_corte
- 0 0 0 - xa9_0/lib/xil_mmu.o ps7_cortexa9_0/lib/xadcps_sinit.o ps7_cortexa9_0/lib/xqspips_sinit.o ps7_cortexa9_0/lib/xgpiops_g.o ps7_cor
- 0 0 0 - texa9_0/lib/xadcps_g.o ps7_cortexa9_0/lib/xscugic.o ps7_cortexa9_0/lib/xil-crt0.o ps7_cortexa9_0/lib/isatty.o ps7_cortexa9_0/li
- 0 0 0 - b/xgpio_extra.o ps7_cortexa9_0/lib/xscuwdt_selftest.o ps7_cortexa9_0/lib/xemacps_intr.o ps7_cortexa9_0/lib/_exit.o ps7_cortexa9
- 0 0 0 - _0/lib/xscuwdt_g.o ps7_cortexa9_0/lib/vectors.o ps7_cortexa9_0/lib/xsdps_g.o ps7_cortexa9_0/lib/xuartps_options.o ps7_cortexa9_
- 0 0 0 - 0/lib/xdevcfg_intr.o ps7_cortexa9_0/lib/errno.o ps7_cortexa9_0/lib/xqspips_hw.o ps7_cortexa9_0/lib/fstat.o ps7_cortexa9_0/lib/x
- 0 0 0 - usbps_hw.o ps7_cortexa9_0/lib/sbrk.o ps7_cortexa9_0/lib/xdmaps_hw.o ps7_cortexa9_0/lib/xsdps_card.o ps7_cortexa9_0/lib/xuartps_
- 0 0 0 - intr.o ps7_cortexa9_0/lib/xil_util.o ps7_cortexa9_0/lib/xscugic_selftest.o ps7_cortexa9_0/lib/xdmaps.o ps7_cortexa9_0/lib/xtime
- 0 0 0 - _l.o ps7_cortexa9_0/lib/read.o ps7_cortexa9_0/lib/xgpio_intr.o ps7_cortexa9_0/lib/xscuwdt_sinit.o ps7_cortexa9_0/lib/outbyte.o
- 0 0 0 - ps7_cortexa9_0/lib/xdevcfg_g.o ps7_cortexa9_0/lib/xscugic_sinit.o ps7_cortexa9_0/lib/xgpiops_intr.o ps7_cortexa9_0/lib/xscugic_
- 0 0 0 - g.o ps7_cortexa9_0/lib/xil_sleepcommon.o ps7_cortexa9_0/lib/cpu_init.o ps7_cortexa9_0/lib/xemacps_bdring.o ps7_cortexa9_0/lib/b
- 0 0 0 - oot.o ps7_cortexa9_0/lib/write.o ps7_cortexa9_0/lib/translation_table.o ps7_cortexa9_0/lib/xil_spinlock.o ps7_cortexa9_0/lib/xq
- 0 0 0 - spips.o ps7_cortexa9_0/lib/xil_testio.o ps7_cortexa9_0/lib/xil_cache.o ps7_cortexa9_0/lib/xemacps.o ps7_cortexa9_0/lib/xdevcfg_
- 0 0 0 - selftest.o ps7_cortexa9_0/lib/xdevcfg.o ps7_cortexa9_0/lib/xuartps_hw.o ps7_cortexa9_0/lib/print.o ps7_cortexa9_0/lib/fcntl.o p
- 0 0 0 - s7_cortexa9_0/lib/_open.o ps7_cortexa9_0/lib/cpputest_time.o ps7_cortexa9_0/lib/xuartps.o ps7_cortexa9_0/lib/xscugic_hw.o ps7_c
- 0 0 0 - ortexa9_0/lib/xsdps_host.o ps7_cortexa9_0/lib/xusbps_intr.o ps7_cortexa9_0/lib/xil_assert.o
- 0 0 0 -
- 0 0 0 - Finished building libraries
- 0 0 0 -
- 0 0 255 -
-18:24:04 Build Finished (took 12s.694ms)
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/65/110900585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/65/110900585243001d18b399c1eb9b3628
deleted file mode 100644
index a3e2069..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/65/110900585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,198 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xqspips_hw.c
-* @addtogroup qspips_v3_9
-* @{
-*
-* Contains low level functions, primarily reset related.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 2.03a hk 09/17/13 First release
-* 3.1 hk 06/19/14 When writing to the configuration register, set/reset
-* required bits leaving reserved bits untouched. CR# 796813.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xqspips_hw.h"
-#include "xqspips.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Pre-scaler value for divided by 4
- *
- * Pre-scaler value for divided by 4
- *
- * @{
- */
-#define XQSPIPS_CR_PRESC_DIV_BY_4 0x01
-/* @} */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Resets QSPI by disabling the device and bringing it to reset state through
-* register writes.
-*
-* @param BaseAddress
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XQspiPs_ResetHw(u32 BaseAddress)
-{
- u32 ConfigReg;
-
- /*
- * Disable interrupts
- */
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_IDR_OFFSET,
- XQSPIPS_IXR_DISABLE_ALL);
-
- /*
- * Disable device
- */
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
- 0);
-
- /*
- * De-assert slave select lines.
- */
- ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
- ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
-
- /*
- * Write default value to RX and TX threshold registers
- * RX threshold should be set to 1 here because the corresponding
- * status bit is used next to clear the RXFIFO
- */
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_TXWR_OFFSET,
- (XQSPIPS_TXWR_RESET_VALUE & XQSPIPS_TXWR_MASK));
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_RXWR_OFFSET,
- (XQSPIPS_RXWR_RESET_VALUE & XQSPIPS_RXWR_MASK));
-
- /*
- * Clear RXFIFO
- */
- while ((XQspiPs_ReadReg(BaseAddress,XQSPIPS_SR_OFFSET) &
- XQSPIPS_IXR_RXNEMPTY_MASK) != 0) {
- XQspiPs_ReadReg(BaseAddress, XQSPIPS_RXD_OFFSET);
- }
-
- /*
- * Clear status register by reading register and
- * writing 1 to clear the write to clear bits
- */
- XQspiPs_ReadReg(BaseAddress, XQSPIPS_SR_OFFSET);
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_SR_OFFSET,
- XQSPIPS_IXR_WR_TO_CLR_MASK);
-
- /*
- * Write default value to configuration register
- */
- ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_RESET_MASK_SET;
- ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR;
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
-
- /*
- * De-select linear mode
- */
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
- 0x0);
-
-}
-
-/*****************************************************************************/
-/**
-*
-* Initializes QSPI to Linear mode with default QSPI boot settings.
-*
-* @param BaseAddress
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XQspiPs_LinearInit(u32 BaseAddress)
-{
- u32 BaudRateDiv;
- u32 LinearCfg;
- u32 ConfigReg;
-
- /*
- * Baud rate divisor for dividing by 4. Value of CR bits [5:3]
- * should be set to 0x001; hence shift the value and use the mask.
- */
- BaudRateDiv = ( (XQSPIPS_CR_PRESC_DIV_BY_4) <<
- XQSPIPS_CR_PRESC_SHIFT) & XQSPIPS_CR_PRESC_MASK;
- /*
- * Write configuration register with default values, slave selected &
- * pre-scaler value for divide by 4
- */
- ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
- ConfigReg |= (XQSPIPS_CR_RESET_MASK_SET | BaudRateDiv);
- ConfigReg &= ~(XQSPIPS_CR_RESET_MASK_CLR | XQSPIPS_CR_SSCTRL_MASK);
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
-
- /*
- * Write linear configuration register with default value -
- * enable linear mode and use fast read.
- */
-
- if(XPAR_XQSPIPS_0_QSPI_MODE == XQSPIPS_CONNECTION_MODE_SINGLE){
-
- LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE;
-
- }else if(XPAR_XQSPIPS_0_QSPI_MODE ==
- XQSPIPS_CONNECTION_MODE_STACKED){
-
- LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
- XQSPIPS_LQSPI_CR_TWO_MEM_MASK;
-
- }else if(XPAR_XQSPIPS_0_QSPI_MODE ==
- XQSPIPS_CONNECTION_MODE_PARALLEL){
-
- LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
- XQSPIPS_LQSPI_CR_TWO_MEM_MASK |
- XQSPIPS_LQSPI_CR_SEP_BUS_MASK;
-
- }
-
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
- LinearCfg);
-
- /*
- * Enable device
- */
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
- XQSPIPS_ER_ENABLE_MASK);
-
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/65/50a40f595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/65/50a40f595243001d18b399c1eb9b3628
deleted file mode 100644
index 316f648..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/65/50a40f595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1 +0,0 @@
-add_subdirectory(${MACHINE})
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/65/90084f575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/65/90084f575243001d18b399c1eb9b3628
deleted file mode 100644
index 82c5fcd..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/65/90084f575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,115 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file qspi.h
-*
-* This file contains the interface for the QSPI FLASH functionality
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 01/10/10 Initial release
-* 3.00a mb 01/09/12 Added the Delay Values defines for qspi
-* 5.00a sgd 05/17/13 Added Flash Size > 128Mbit support
-* Dual Stack support
-* 6.00a bsv 09/04/20 Added support for 2Gb flash parts
-*
-*
-* @note
-*
-******************************************************************************/
-#ifndef ___QSPI_H___
-#define ___QSPI_H___
-
-#include "fsbl.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "fsbl.h"
-
-/************************** Constant Definitions *****************************/
-#define SINGLE_FLASH_CONNECTION 0
-#define DUAL_STACK_CONNECTION 1
-#define DUAL_PARALLEL_CONNECTION 2
-#define FLASH_SIZE_16MB 0x1000000
-
-/*
- * Bank mask
- */
-#define BANKMASK 0xF000000
-
-/*
- * Identification of Flash
- * Micron:
- * Byte 0 is Manufacturer ID;
- * Byte 1 is first byte of Device ID - 0xBB or 0xBA
- * Byte 2 is second byte of Device ID describes flash size:
- * 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20
- * Spansion:
- * Byte 0 is Manufacturer ID;
- * Byte 1 is Device ID - Memory Interface type - 0x20 or 0x02
- * Byte 2 is second byte of Device ID describes flash size:
- * 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20
- */
-
-#define MICRON_ID 0x20
-#define SPANSION_ID 0x01
-#define WINBOND_ID 0xEF
-#define MACRONIX_ID 0xC2
-#define ISSI_ID 0x9D
-
-#define FLASH_SIZE_ID_8M 0x14
-#define FLASH_SIZE_ID_16M 0x15
-#define FLASH_SIZE_ID_32M 0x16
-#define FLASH_SIZE_ID_64M 0x17
-#define FLASH_SIZE_ID_128M 0x18
-#define FLASH_SIZE_ID_256M 0x19
-#define FLASH_SIZE_ID_512M 0x20
-#define FLASH_SIZE_ID_1G 0x21
-#define FLASH_SIZE_ID_2G 0x22
-/* Macronix size constants are different for 512M and 1G */
-#define MACRONIX_FLASH_SIZE_ID_512M 0x1A
-#define MACRONIX_FLASH_SIZE_ID_1G 0x1B
-#define MACRONIX_FLASH_SIZE_ID_2G 0x1C
-#define MACRONIX_FLASH_1_8_V_MX66_ID_512 (0x3A)
-/*
- * Size in bytes
- */
-#define FLASH_SIZE_8M 0x0100000
-#define FLASH_SIZE_16M 0x0200000
-#define FLASH_SIZE_32M 0x0400000
-#define FLASH_SIZE_64M 0x0800000
-#define FLASH_SIZE_128M 0x1000000
-#define FLASH_SIZE_256M 0x2000000
-#define FLASH_SIZE_512M 0x4000000
-#define FLASH_SIZE_1G 0x8000000
-#define FLASH_SIZE_2G 0x10000000
-
-/************************** Function Prototypes ******************************/
-u32 InitQspi(void);
-
-u32 QspiAccess( u32 SourceAddress,
- u32 DestinationAddress,
- u32 LengthBytes);
-
-u32 FlashReadID(void);
-u32 SendBankSelect(u8 BankSel);
-/************************** Variable Definitions *****************************/
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* ___QSPI_H___ */
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/65/c048d2545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/65/c048d2545243001d18b399c1eb9b3628
deleted file mode 100644
index a270af6..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/65/c048d2545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,691 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xscugic_hw.h
-* @addtogroup scugic_v4_6
-* @{
-*
-* This header file contains identifiers and HW access functions (or
-* macros) that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-* The driver functions/APIs are defined in xscugic.h.
-*
-* This GIC device has two parts, a distributor and CPU interface(s). Each part
-* has separate register definition sections.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------------
-* 1.00a drg 01/19/10 First release
-* 1.01a sdm 11/09/11 "xil_exception.h" added as include.
-* Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
-* added to enable or disable interrupts based on
-* Distributor Register base address. Normally users use
-* XScuGic instance and call XScuGic_Enable or
-* XScuGic_Disable to enable/disable interrupts. These
-* new macros are provided when user does not want to
-* use an instance pointer but still wants to enable or
-* disable interrupts.
-* Function prototypes for functions (present in newly
-* added file xscugic_hw.c) are added.
-* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
-* 702687).
-* 1.04a hk 05/04/13 Fix for CR#705621. Moved function prototypes
-* XScuGic_SetPriTrigTypeByDistAddr and
-* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
-* 3.0 pkp 12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
-* Zynq Ultrascale Mp
-* 3.0 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
-* 3.2 pkp 11/09/15 Corrected the interrupt processsor target mask value
-* for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
-* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
-* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
-* API's can be used by applications to unmap specific/all
-* interrupts from target CPU. It fixes CR#992490.
-* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
-* 4.1 asa 03/30/19 Removed macros for XScuGic_EnableIntr, and
-* XScuGic_DisableIntr. These are now C functions. This
-* change was to fix CR-1024716.
-* 4.1 mus 06/12/19 Updated XSCUGIC_MAX_NUM_INTR_INPUTS for Versal.
-* 4.6 sk 06/07/21 Delete the commented macro code to fix the MISRA-C warning.
-* 4.6 sk 08/05/21 Fix Scugic Misrac violations.
-*
-*
-*
-******************************************************************************/
-
-#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
-#define XSCUGIC_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xil_exception.h"
-#include "bspconfig.h"
-
-/************************** Constant Definitions *****************************/
-#if defined (versal) && !defined(ARMR5)
-#define GICv3
-#endif
-
-/*
- * The maximum number of interrupts supported by the hardware.
- */
-#ifdef PLATFORM_ZYNQ
-#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */
-#elif defined (versal)
-#define XSCUGIC_MAX_NUM_INTR_INPUTS 192U
-#else
-#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
-#endif
-
-/*
- * First Interrupt Id for SPI interrupts.
- */
-#define XSCUGIC_SPI_INT_ID_START 0x20
-/*
- * The maximum priority value that can be used in the GIC.
- */
-#define XSCUGIC_MAX_INTR_PRIO_VAL 248U
-#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U
-
-/** @name Distributor Interface Register Map
- *
- * Define the offsets from the base address for all Distributor registers of
- * the interrupt controller, some registers may be reserved in the hardware
- * device.
- * @{
- */
-#define XSCUGIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable
- Register */
-#define XSCUGIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller
- Type Register */
-#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID
- Register */
-#define XSCUGIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security
- Register */
-#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set
- Register */
-#define XSCUGIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */
-#define XSCUGIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set
- Register */
-#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear
- Register */
-#define XSCUGIC_ACTIVE_OFFSET 0x00000300U /**< Active Status Register */
-#define XSCUGIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */
-#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target
- Register 0x800-0x8FB */
-#define XSCUGIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration
- Register 0xC00-0xCFC */
-#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */
-#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register
- 0xd04-0xd7C */
-#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration
- Register */
-#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered
- Interrupt Register */
-#define XSCUGIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */
-#if defined (GICv3)
-#define XSCUGIC_PCELLID_OFFSET 0x0000FFF0U /**< Pcell ID Register */
-#else
-#define XSCUGIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */
-#endif
-/* @} */
-
-/** @name Distributor Enable Register
- * Controls if the distributor response to external interrupt inputs.
- * @{
- */
-#if defined (GICv3)
-#define XSCUGIC_EN_INT_MASK 0x00000003U /**< Interrupt In Enable */
-#else
-#define XSCUGIC_EN_INT_MASK 0x00000001U /**< Interrupt In Enable */
-#endif
-/* @} */
-
-/** @name Interrupt Controller Type Register
- * @{
- */
-#define XSCUGIC_LSPI_MASK 0x0000F800U /**< Number of Lockable
- Shared Peripheral
- Interrupts*/
-#define XSCUGIC_DOMAIN_MASK 0x00000400U /**< Number os Security domains*/
-#define XSCUGIC_CPU_NUM_MASK 0x000000E0U /**< Number of CPU Interfaces */
-#define XSCUGIC_NUM_INT_MASK 0x0000001FU /**< Number of Interrupt IDs */
-/* @} */
-
-/** @name Implementor ID Register
- * Implementor and revision information.
- * @{
- */
-#define XSCUGIC_REV_MASK 0x00FFF000U /**< Revision Number */
-#define XSCUGIC_IMPL_MASK 0x00000FFFU /**< Implementor */
-/* @} */
-
-/** @name Interrupt Security Registers
- * Each bit controls the security level of an interrupt, either secure or non
- * secure. These registers can only be accessed using secure read and write.
- * There are registers for each of the CPU interfaces at offset 0x080. A
- * register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x084.
- * @{
- */
-#define XSCUGIC_INT_NS_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Enable Set Register
- * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
- * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
- * bit to 0.
- * There are registers for each of the CPU interfaces at offset 0x100. With up
- * to 8 registers aliased to the same address. A register set for the SPI
- * interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x104.
- * @{
- */
-#define XSCUGIC_INT_EN_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Enable Clear Register
- * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
- * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
- * sets the corresponding bit to 0.
- * There are registers for each of the CPU interfaces at offset 0x180. With up
- * to 8 registers aliased to the same address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x184.
- * @{
- */
-#define XSCUGIC_INT_CLR_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Pending Set Register
- * Each bit controls the Pending or Active and Pending state of an interrupt, a
- * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
- * an interrupt to the pending state.
- * There are registers for each of the CPU interfaces at offset 0x200. With up
- * to 8 registers aliased to the same address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x204.
- * @{
- */
-#define XSCUGIC_PEND_SET_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Pending Clear Register
- * Each bit can clear the Pending or Active and Pending state of an interrupt, a
- * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
- * clears the pending state of an interrupt.
- * There are registers for each of the CPU interfaces at offset 0x280. With up
- * to 8 registers aliased to the same address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x284.
- * @{
- */
-#define XSCUGIC_PEND_CLR_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Active Status Register
- * Each bit provides the Active status of an interrupt, a
- * 0 is not Active, a 1 is Active. This is a read only register.
- * There are registers for each of the CPU interfaces at offset 0x300. With up
- * to 8 registers aliased to each address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x380.
- * @{
- */
-#define XSCUGIC_ACTIVE_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Priority Level Register
- * Each byte in a Priority Level Register sets the priority level of an
- * interrupt. Reading the register provides the priority level of an interrupt.
- * There are registers for each of the CPU interfaces at offset 0x400 through
- * 0x41C. With up to 8 registers aliased to each address.
- * 0 is highest priority, 0xFF is lowest.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 255 of these registers staring at location 0x420.
- * @{
- */
-#define XSCUGIC_PRIORITY_MASK 0x000000FFU /**< Each Byte corresponds to an
- INT_ID */
-#define XSCUGIC_PRIORITY_MAX 0x000000FFU /**< Highest value of a priority
- actually the lowest priority*/
-/* @} */
-
-/** @name SPI Target Register 0x800-0x8FB
- * Each byte references a separate SPI and programs which of the up to 8 CPU
- * interfaces are sent a Pending interrupt.
- * There are registers for each of the CPU interfaces at offset 0x800 through
- * 0x81C. With up to 8 registers aliased to each address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 255 of these registers staring at location 0x820.
- *
- * This driver does not support multiple CPU interfaces. These are included
- * for complete documentation.
- * @{
- */
-#define XSCUGIC_SPI_CPU7_MASK 0x00000080U /**< CPU 7 Mask*/
-#define XSCUGIC_SPI_CPU6_MASK 0x00000040U /**< CPU 6 Mask*/
-#define XSCUGIC_SPI_CPU5_MASK 0x00000020U /**< CPU 5 Mask*/
-#define XSCUGIC_SPI_CPU4_MASK 0x00000010U /**< CPU 4 Mask*/
-#define XSCUGIC_SPI_CPU3_MASK 0x00000008U /**< CPU 3 Mask*/
-#define XSCUGIC_SPI_CPU2_MASK 0x00000004U /**< CPU 2 Mask*/
-#define XSCUGIC_SPI_CPU1_MASK 0x00000002U /**< CPU 1 Mask*/
-#define XSCUGIC_SPI_CPU0_MASK 0x00000001U /**< CPU 0 Mask*/
-/* @} */
-
-/** @name Interrupt Configuration Register 0xC00-0xCFC
- * The interrupt configuration registers program an SFI to be active HIGH level
- * sensitive or rising edge sensitive.
- * Each bit pair describes the configuration for an INT_ID.
- * SFI Read Only b10 always
- * PPI Read Only depending on how the PPIs are configured.
- * b01 Active HIGH level sensitive
- * b11 Rising edge sensitive
- * SPI LSB is read only.
- * b01 Active HIGH level sensitive
- * b11 Rising edge sensitive/
- * There are registers for each of the CPU interfaces at offset 0xC00 through
- * 0xC04. With up to 8 registers aliased to each address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 255 of these registers staring at location 0xC08.
- * @{
- */
-#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */
-/* @} */
-
-/** @name PPI Status Register
- * Enables an external AMBA master to access the status of the PPI inputs.
- * A CPU can only read the status of its local PPI signals and cannot read the
- * status for other CPUs.
- * This register is aliased for each CPU interface.
- * @{
- */
-#define XSCUGIC_PPI_C15_MASK 0x00008000U /**< PPI Status */
-#define XSCUGIC_PPI_C14_MASK 0x00004000U /**< PPI Status */
-#define XSCUGIC_PPI_C13_MASK 0x00002000U /**< PPI Status */
-#define XSCUGIC_PPI_C12_MASK 0x00001000U /**< PPI Status */
-#define XSCUGIC_PPI_C11_MASK 0x00000800U /**< PPI Status */
-#define XSCUGIC_PPI_C10_MASK 0x00000400U /**< PPI Status */
-#define XSCUGIC_PPI_C09_MASK 0x00000200U /**< PPI Status */
-#define XSCUGIC_PPI_C08_MASK 0x00000100U /**< PPI Status */
-#define XSCUGIC_PPI_C07_MASK 0x00000080U /**< PPI Status */
-#define XSCUGIC_PPI_C06_MASK 0x00000040U /**< PPI Status */
-#define XSCUGIC_PPI_C05_MASK 0x00000020U /**< PPI Status */
-#define XSCUGIC_PPI_C04_MASK 0x00000010U /**< PPI Status */
-#define XSCUGIC_PPI_C03_MASK 0x00000008U /**< PPI Status */
-#define XSCUGIC_PPI_C02_MASK 0x00000004U /**< PPI Status */
-#define XSCUGIC_PPI_C01_MASK 0x00000002U /**< PPI Status */
-#define XSCUGIC_PPI_C00_MASK 0x00000001U /**< PPI Status */
-/* @} */
-
-/** @name SPI Status Register 0xd04-0xd7C
- * Enables an external AMBA master to access the status of the SPI inputs.
- * There are up to 63 registers if the maximum number of SPI inputs are
- * configured.
- * @{
- */
-#define XSCUGIC_SPI_N_MASK 0x00000001U /**< Each bit corresponds to an SPI
- input */
-/* @} */
-
-/** @name AHB Configuration Register
- * Provides the status of the CFGBIGEND input signal and allows the endianness
- * of the GIC to be set.
- * @{
- */
-#define XSCUGIC_AHB_END_MASK 0x00000004U /**< 0-GIC uses little Endian,
- 1-GIC uses Big Endian */
-#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002U /**< 0-Uses CFGBIGEND control,
- 1-use the AHB_END bit */
-#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U /**< State of CFGBIGEND */
-
-/* @} */
-
-/** @name Software Triggered Interrupt Register
- * Controls issuing of software interrupts.
- * @{
- */
-#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000U
-#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U /**< Target List filter
- b00-Use the target List
- b01-All CPUs except requester
- b10-To Requester
- b11-reserved */
-#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U /**< CPU Target list */
-#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U /**< 0= Use a secure interrupt */
-#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU /**< Set to the INTID
- signaled to the CPU*/
-/* @} */
-
-/** @name CPU Interface Register Map
- *
- * Define the offsets from the base address for all CPU registers of the
- * interrupt controller, some registers may be reserved in the hardware device.
- * @{
- */
-#define XSCUGIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control
- Register */
-#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */
-#define XSCUGIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */
-#define XSCUGIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */
-#define XSCUGIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */
-#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */
-#define XSCUGIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt
- Register */
-#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure
- Binary Point Register */
-
-/**< 0x00000020 to 0x00000FBC are reserved and should not be read or written
- * to. */
-/* @} */
-
-
-/** @name Control Register
- * CPU Interface Control register definitions
- * All bits are defined here although some are not available in the non-secure
- * mode.
- * @{
- */
-#define XSCUGIC_CNTR_SBPR_MASK 0x00000010U /**< Secure Binary Pointer,
- 0=separate registers,
- 1=both use bin_pt_s */
-#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008U /**< Use nFIQ_C for secure
- interrupts,
- 0= use IRQ for both,
- 1=Use FIQ for secure, IRQ for non*/
-#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U /**< Ack control for secure or non secure */
-#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002U /**< Non Secure enable */
-#define XSCUGIC_CNTR_EN_S_MASK 0x00000001U /**< Secure enable, 0=Disabled, 1=Enabled */
-/* @} */
-
-
-/** @name Binary Point Register
- * Binary Point register definitions
- * @{
- */
-
-#define XSCUGIC_BIN_PT_MASK 0x00000007U /**< Binary point mask value
- Value Secure Non-secure
- b000 0xFE 0xFF
- b001 0xFC 0xFE
- b010 0xF8 0xFC
- b011 0xF0 0xF8
- b100 0xE0 0xF0
- b101 0xC0 0xE0
- b110 0x80 0xC0
- b111 0x00 0x80
- */
-/*@}*/
-
-/** @name Interrupt Acknowledge Register
- * Interrupt Acknowledge register definitions
- * Identifies the current Pending interrupt, and the CPU ID for software
- * interrupts.
- */
-#define XSCUGIC_ACK_INTID_MASK 0x000003FFU /**< Interrupt ID */
-#define XSCUGIC_CPUID_MASK 0x00000C00U /**< CPU ID */
-/* @} */
-
-/** @name End of Interrupt Register
- * End of Interrupt register definitions
- * Allows the CPU to signal the GIC when it completes an interrupt service
- * routine.
- */
-#define XSCUGIC_EOI_INTID_MASK 0x000003FFU /**< Interrupt ID */
-
-/* @} */
-
-/** @name Running Priority Register
- * Running Priority register definitions
- * Identifies the interrupt priority level of the highest priority active
- * interrupt.
- */
-#define XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU /**< Interrupt Priority */
-/* @} */
-
-#if defined (GICv3)
-#define XSCUGIC_IROUTER_BASE_OFFSET 0x6000U
-#endif
-/*
- * Highest Pending Interrupt register definitions
- * Identifies the interrupt priority of the highest priority pending interrupt
- */
-#define XSCUGIC_PEND_INTID_MASK 0x000003FFU /**< Pending Interrupt ID */
-/* @} */
-#if defined (GICv3)
-/** @name ReDistributor Interface Register Map
- *
- * @{
- */
-#define XSCUGIC_RDIST_OFFSET 0x80000U
-#define XSCUGIC_RDIST_BASE_ADDRESS (XPAR_SCUGIC_0_DIST_BASEADDR + XSCUGIC_RDIST_OFFSET)
-#define XSCUGIC_RDIST_SGI_PPI_OFFSET 0x90000U
-#define XSCUGIC_RDIST_SGI_PPI_BASE_ADDRESS (XPAR_SCUGIC_0_DIST_BASEADDR + XSCUGIC_RDIST_SGI_PPI_OFFSET)
-#define XSCUGIC_RDIST_ISENABLE_OFFSET 0x100U
-#define XSCUGIC_RDIST_IPRIORITYR_OFFSET 0x400U
-#define XSCUGIC_RDIST_IGROUPR_OFFSET 0x80U
-#define XSCUGIC_RDIST_GRPMODR_OFFSET 0xD00U
-#define XSCUGIC_RDIST_INT_CONFIG_OFFSET 0xC00U
-#define XSCUGIC_RDIST_WAKER_OFFSET 0x14U
-#define XSCUGIC_SGIR_EL1_INITID_SHIFT 24U
-
-/*
- * GICR_IGROUPR register definitions
- */
-#if EL3
-#define XSCUGIC_DEFAULT_SECURITY 0x0U
-#else
-#define XSCUGIC_DEFAULT_SECURITY 0xFFFFFFFFU
-#endif
-/*
- * GICR_WAKER register definitions
- */
-#define XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK 0x7
-#endif
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Configuration Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Priority Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Routing Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_IROUTER_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_IROUTER_BASE_OFFSET + (InterruptID * 8))
-
-/****************************************************************************/
-/**
-*
-* Read the SPI Target Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
-/****************************************************************************/
-/**
-*
-* Read the SPI Target Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_SECURITY_TARGET_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_SECURITY_OFFSET + (((InterruptID)/32U)*4U))
-
-/****************************************************************************/
-/**
-*
-* Read the Re-distributor Interrupt configuration register offset
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_RDIST_INT_CONFIG_OFFSET + ((InterruptID /16)*4))
-
-/****************************************************************************/
-/**
-*
-* Read the Re-distributor Interrupt Priority register offset
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_RDIST_IPRIORITYR_OFFSET + (InterruptID * 4))
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Clear-Enable Register offset for an interrupt ID
-*
-* @param Register is the register offset for the clear/enable bank.
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
- ((Register) + (((InterruptID)/32U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the given Intc register.
-*
-* @param BaseAddress is the base address of the device.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_ReadReg(BaseAddress, RegOffset) \
- (Xil_In32((BaseAddress) + (RegOffset)))
-
-
-/****************************************************************************/
-/**
-*
-* Write the given Intc register.
-*
-* @param BaseAddress is the base address of the device.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
- (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
-
-
-/************************** Function Prototypes ******************************/
-
-void XScuGic_DeviceInterruptHandler(void *DeviceId);
-s32 XScuGic_DeviceInitialize(u32 DeviceId);
-void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
- Xil_InterruptHandler IntrHandler, void *CallBackRef);
-void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
- u8 Priority, u8 Trigger);
-void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
- u8 *Priority, u8 *Trigger);
-void XScuGic_InterruptMapFromCpuByDistAddr(u32 DistBaseAddress,
- u8 Cpu_Id, u32 Int_Id);
-void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
- u8 Cpu_Id, u32 Int_Id);
-void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
- u8 Cpu_Id);
-void XScuGic_EnableIntr (u32 DistBaseAddress, u32 Int_Id);
-void XScuGic_DisableIntr (u32 DistBaseAddress, u32 Int_Id);
-/************************** Variable Definitions *****************************/
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/66/301098525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/66/301098525243001d18b399c1eb9b3628
deleted file mode 100644
index 179c840..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/66/301098525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,329 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xdmaps.h
-* @addtogroup dmaps_v2_8
-* @{
-* @details
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00 hbm 08/19/10 First Release
-* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
-* the maximum number of channels.
-* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
-* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
-* Added the tcl file to automatically generate the
-* xparameters.h
-* 1.02a sg 05/16/12 Made changes for doxygen and moved some function
-* header from the xdmaps.h file to xdmaps.c file
-* Other cleanup for coding guidelines and CR 657109
-* and CR 657898
-* The xdmaps_example_no_intr.c example is removed
-* as it is using interrupts and is similar to
-* the interrupt example - CR 652477
-* 1.03a sg 07/16/2012 changed inline to __inline for CR665681
-* 1.04a nm 10/22/2012 Fixed CR# 681671.
-* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled
-* with -Wall and -Wextra option in bsp.
-* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
-* function description.
-* Fixed CR# 704396. Removed unused variables
-* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
-* function.
-* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc.
-* Removed the PDBG prints. By default they were always
-* defined out and never used. The PDBG is non-standard for
-* Xilinx drivers and no other driver does something similar.
-* Since there is no easy way to fix compilation issues with
-* the IARCC compiler around PDBG, it is better to remove it.
-* Users can always use xil_printfs if they want to debug.
-* 2.0 adk 10/12/13 Updated as per the New Tcl API's
-* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
-* 2.2 mus 08/12/16 Declared all inline functions in xdmaps.c as extern, to avoid
-* linker error for IAR compiler
-* 2.3 ms 01/23/17 Modified xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 2.4 adk 13/08/18 Fixed armcc compiler warnings in the driver CR-1008310.
-* 2.8 sk 05/18/21 Modify all inline functions declarations from extern inline
-* to static inline to avoid the linkage conflict for IAR compiler.
-*
-*
-*****************************************************************************/
-
-#ifndef XDMAPS_H /* prevent circular inclusions */
-#define XDMAPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xparameters.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-
-#include "xdmaps_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of device (IPIF) */
-} XDmaPs_Config;
-
-
-/** DMA channle control structure. It's for AXI bus transaction.
- * This struct will be translated into a 32-bit channel control register value.
- */
-typedef struct {
- unsigned int EndianSwapSize; /**< Endian swap size. */
- unsigned int DstCacheCtrl; /**< Destination cache control */
- unsigned int DstProtCtrl; /**< Destination protection control */
- unsigned int DstBurstLen; /**< Destination burst length */
- unsigned int DstBurstSize; /**< Destination burst size */
- unsigned int DstInc; /**< Destination incrementing or fixed
- * address */
- unsigned int SrcCacheCtrl; /**< Source cache control */
- unsigned int SrcProtCtrl; /**< Source protection control */
- unsigned int SrcBurstLen; /**< Source burst length */
- unsigned int SrcBurstSize; /**< Source burst size */
- unsigned int SrcInc; /**< Source incrementing or fixed
- * address */
-} XDmaPs_ChanCtrl;
-
-/** DMA block descriptor stucture.
- */
-typedef struct {
- u32 SrcAddr; /**< Source starting address */
- u32 DstAddr; /**< Destination starting address */
- unsigned int Length; /**< Number of bytes for the block */
-} XDmaPs_BD;
-
-/**
- * A DMA command consisits of a channel control struct, a block descriptor,
- * a user defined program, a pointer pointing to generated DMA program, and
- * execution result.
- *
- */
-typedef struct {
- XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */
- XDmaPs_BD BD; /**< Together with SgLength field,
- * it's a scatter-gather list.
- */
- void *UserDmaProg; /**< If user wants the driver to
- * execute their own DMA program,
- * this field points to the DMA
- * program.
- */
- int UserDmaProgLength; /**< The length of user defined
- * DMA program.
- */
-
- void *GeneratedDmaProg; /**< The DMA program genreated
- * by the driver. This field will be
- * set if a user invokes the DMA
- * program generation function. Or
- * the DMA command is finished and
- * a user informs the driver not to
- * release the program buffer.
- * This field has two purposes, one
- * is to ask the driver to generate
- * a DMA program while the DMAC is
- * performaning DMA transactions. The
- * other purpose is to debug the
- * driver.
- */
- int GeneratedDmaProgLength; /**< The length of the DMA program
- * generated by the driver
- */
- int DmaStatus; /**< 0 on success, otherwise error code
- */
- u32 ChanFaultType; /**< Channel fault type in case of fault
- */
- u32 ChanFaultPCAddr; /**< Channel fault PC address
- */
-} XDmaPs_Cmd;
-
-/**
- * It's the done handler a user can set for a channel
- */
-typedef void (*XDmaPsDoneHandler) (unsigned int Channel,
- XDmaPs_Cmd *DmaCmd,
- void *CallbackRef);
-
-/**
- * It's the fault handler a user can set for a channel
- */
-typedef void (*XDmaPsFaultHandler) (unsigned int Channel,
- XDmaPs_Cmd *DmaCmd,
- void *CallbackRef);
-
-#define XDMAPS_MAX_CHAN_BUFS 2
-#define XDMAPS_CHAN_BUF_LEN 128
-
-/**
- * The XDmaPs_ProgBuf is the struct for a DMA program buffer.
- */
-typedef struct {
- char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the
- * content */
- unsigned Len; /**< The actual length of the DMA
- * program in bytes. */
- int Allocated; /**< A tag indicating whether the
- * buffer is allocated or not */
-} XDmaPs_ProgBuf;
-
-/**
- * The XDmaPs_ChannelData is a struct to book keep individual channel of
- * the DMAC.
- */
-typedef struct {
- unsigned DevId; /**< Device id indicating which DMAC */
- unsigned ChanId; /**< Channel number of the DMAC */
- XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of
- program buffers*/
- XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */
- void *DoneRef; /**< Done interrupt callback data */
- XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */
- XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished.
- * This field is for debugging purpose
- */
- int HoldDmaProg; /**< A tag indicating whether to hold the
- * DMA program after the DMA is done.
- */
-
-} XDmaPs_ChannelData;
-
-/**
- * The XDmaPs driver instance data structure. A pointer to an instance data
- * structure is passed around by functions to refer to a specific driver
- * instance.
- */
-typedef struct {
- XDmaPs_Config Config; /**< Configuration data structure */
- int IsReady; /**< Device is Ready */
- int CacheLength; /**< icache length */
- XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */
- void *FaultRef; /**< fault call back data */
- XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV];
- /**<
- * channel data
- */
-} XDmaPs;
-
-/*
- * Functions implemented in xdmaps.c
- */
-int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
- XDmaPs_Config *Config,
- u32 EffectiveAddr);
-
-int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
- XDmaPs_Cmd *Cmd,
- int HoldDmaProg);
-
-int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel);
-int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel,
- XDmaPs_Cmd *Cmd);
-int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel,
- XDmaPs_Cmd *Cmd);
-void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
-
-
-int XDmaPs_ResetManager(XDmaPs *InstPtr);
-int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel);
-
-
-int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
- unsigned Channel,
- XDmaPsDoneHandler DoneHandler,
- void *CallbackRef);
-
-int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
- XDmaPsFaultHandler FaultHandler,
- void *CallbackRef);
-
-void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
-int XDmaPs_Instr_DMARMB(char *DmaProg);
-int XDmaPs_Instr_DMAWMB(char *DmaProg);
-
-/**
- * To avoid linkage error,modify all inline functions from extern
- * inline to static inline for IAR compiler
- */
-#ifdef __ICCARM__
-static INLINE int XDmaPs_Instr_DMAEND(char *DmaProg);
-static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src);
-static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
- u32 Imm, unsigned int Ns);
-static INLINE int XDmaPs_Instr_DMALD(char *DmaProg);
-static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
- unsigned LoopIterations);
-static INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc);
-static INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm);
-static INLINE int XDmaPs_Instr_DMANOP(char *DmaProg);
-static INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber);
-static INLINE int XDmaPs_Instr_DMAST(char *DmaProg);
-static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize);
-static INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize);
-#endif
-
-/**
- * Driver done interrupt service routines for the channels.
- * We need this done ISR mainly because the driver needs to release the
- * DMA program buffer. This is the one that connects the GIC
- */
-void XDmaPs_DoneISR_0(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_1(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_2(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_3(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_4(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_5(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_6(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_7(XDmaPs *InstPtr);
-
-/**
- * Driver fault interrupt service routine
- */
-void XDmaPs_FaultISR(XDmaPs *InstPtr);
-
-
-/*
- * Static loopup function implemented in xdmaps_sinit.c
- */
-XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId);
-
-
-/*
- * self-test functions in xdmaps_selftest.c
- */
-int XDmaPs_SelfTest(XDmaPs *InstPtr);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/66/91ff82595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/66/91ff82595243001d18b399c1eb9b3628
deleted file mode 100644
index da7e768..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/66/91ff82595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,36 +0,0 @@
-/* print.c -- print a string on the output device.
- *
- * Copyright (c) 1995 Cygnus Support
- *
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- *
- */
-
-/*
- * print -- do a raw print of a string
- */
-#include "xil_printf.h"
-
-void print(const char8 *ptr)
-{
-#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
- XPVXenConsole_Write(ptr);
-#else
-#ifdef STDOUT_BASEADDRESS
- while (*ptr != (char8)0) {
- outbyte (*ptr);
- ptr++;
- }
-#else
-(void)ptr;
-#endif
-#endif
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/66/a04a95555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/66/a04a95555243001d18b399c1eb9b3628
deleted file mode 100644
index 53eac10..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/66/a04a95555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,25 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/* The errno variable is stored in the reentrancy structure. This
- function returns its address for use by the macro errno defined in
- errno.h. */
-
-#include
-#include
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) sint32 * __errno (void);
-}
-#endif
-
-__attribute__((weak)) sint32 *
-__errno (void)
-{
- return &_REENT->_errno;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/67/502c23595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/67/502c23595243001d18b399c1eb9b3628
deleted file mode 100644
index 46b7045..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/67/502c23595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,60 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm.h
-*
-* @addtogroup r5_specific Cortex R5 Processor Specific Include Files
-*
-* The xpseudo_asm.h includes xreg_cortexr5.h and xpseudo_asm_gcc.h.
-*
-* The xreg_cortexr5.h file contains definitions for inline assembler code.
-* It provides inline definitions for Cortex R5 GPRs, SPRs,co-processor
-* registers and Debug register
-*
-* The xpseudo_asm_gcc.h contains the definitions for the most often used
-* inline assembler instructions, available as macros. These can be very
-* useful for tasks such as setting or getting special purpose registers,
-* synchronization,or cache manipulation. These inline assembler instructions
-* can be used from drivers and user applications written in C.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.00 pkp 02/10/14 Initial version
-* 6.2 mus 01/27/17 Updated to support IAR compiler
-* 7.3 dp 06/25/20 Initial version for armclang
-*
-*
-******************************************************************************/
-#ifndef XPSEUDO_ASM_H /* prevent circular inclusions */
-#define XPSEUDO_ASM_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xreg_cortexr5.h"
-#if defined (__clang__)
-#include "xpseudo_asm_armclang.h"
-#elif defined (__GNUC__)
-#include "xpseudo_asm_gcc.h"
-#elif defined (__ICCARM__)
-#include "xpseudo_asm_iccarm.h"
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XPSEUDO_ASM_H */
-/**
-* @} End of "addtogroup r5_specific".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/67/61f7de585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/67/61f7de585243001d18b399c1eb9b3628
deleted file mode 100644
index d90ef88..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/67/61f7de585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,83 +0,0 @@
-###############################################################################
-# Copyright (c) 2011 - 2020 Xilinx, Inc. All rights reserved.
-# SPDX-License-Identifier: MIT
-###############################################################################
-DRIVER_LIB_VERSION = v1.0
-
-include config.make
-
-CC=$(COMPILER)
-AR=$(ARCHIVER)
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS))
-ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS))
-
-ifeq (($(notdir $(CC))) , arm-xilinx-eabi-gcc)
-ECC_FLAGS += -nostartfiles\
- -march=armv7-a \
- -mfloat-abi=soft \
- -mfpu=neon
-endif
-
-ifeq (($(notdir $(CC))) , arm-none-eabi-gcc)
-ECC_FLAGS += -nostartfiles
-endif
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-SRCFILES:=$(wildcard *.c)
-
-ASSEMBLY_SRCFILES:=$(wildcard *.S)
-
-OBJECTS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(wildcard *.c))))
-
-ASSEMBLY_OBJECTS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(wildcard *.S))))
-
-INCLUDEFILES=*.h
-
-libs: $(LIBS)
-
-standalone_libs: $(OBJECTS) $(ASSEMBLY_OBJECTS)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-ASSEMBLY_DEPFILES := $(ASSEMBLY_SRCFILES:%.S=$(RELEASEDIR)%.d)
-
-include $(wildcard $(ASSEMBLY_DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.S
- $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $<
-
-$(RELEASEDIR)%.o: %.c
- $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $<
-
-profile_libs:
- $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" libs
-
-.PHONY: include
-include: standalone_includes profile_includes
-
-standalone_includes: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-profile_includes:
- $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" include
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf ${ASSEMBLY_OBJECTS}
- rm -rf $(DEPFILES)
- rm -rf $(ASSEMBLY_DEPFILES)
- $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" clean
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/67/80f1e6595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/67/80f1e6595243001d18b399c1eb9b3628
deleted file mode 100644
index 6675e7e..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/67/80f1e6595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,6580 +0,0 @@
-/*----------------------------------------------------------------------------/
-/ FatFs - Generic FAT Filesystem Module R0.13b /
-/-----------------------------------------------------------------------------/
-/
-/ Copyright (C) 2018, ChaN, all right reserved.
-/
-/ FatFs module is an open source software. Redistribution and use of FatFs in
-/ source and binary forms, with or without modification, are permitted provided
-/ that the following condition is met:
-/
-/ 1. Redistributions of source code must retain the above copyright notice,
-/ this condition and the following disclaimer.
-/
-/ This software is provided by the copyright holder and contributors "AS IS"
-/ and any warranties related to this software are DISCLAIMED.
-/ The copyright owner or contributors be NOT LIABLE for any damages caused
-/ by use of this software.
-/
-/----------------------------------------------------------------------------*/
-
-/**
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 3.9 mn 04/18/18 Resolve build warnings for xilffs library
-* 4.2 aru 07/10/19 Fix Coverity warnings
-* mn 08/16/19 Initialize Status variables with failure values
-* 4.3 mn 02/05/20 Add support for Multi Partitions
-* mn 04/23/20 Add partition 0 for supporting default partition
-******************************************************************************/
-#include "xparameters.h"
-#if (defined FILE_SYSTEM_INTERFACE_SD) || (defined FILE_SYSTEM_INTERFACE_RAM)
-#include "ff.h" /* Declarations of FatFs API */
-#include "diskio.h" /* Declarations of device I/O functions */
-#include "xil_printf.h"
-
-
-/*--------------------------------------------------------------------------
-
- Module Private Definitions
-
----------------------------------------------------------------------------*/
-
-#if FF_DEFINED != 63463 /* Revision ID */
-#error Wrong include file (ff.h).
-#endif
-
-
-/* Character code support macros */
-#define IsUpper(c) ((c) >= 'A' && (c) <= 'Z')
-#define IsLower(c) ((c) >= 'a' && (c) <= 'z')
-#define IsDigit(c) ((c) >= '0' && (c) <= '9')
-#define IsSurrogate(c) ((c) >= 0xD800 && (c) <= 0xDFFF)
-#define IsSurrogateH(c) ((c) >= 0xD800 && (c) <= 0xDBFF)
-#define IsSurrogateL(c) ((c) >= 0xDC00 && (c) <= 0xDFFF)
-
-
-/* Additional file attribute bits for internal use */
-#define AM_VOL 0x08 /* Volume label */
-#define AM_LFN 0x0F /* LFN entry */
-#define AM_MASK 0x3F /* Mask of defined bits */
-
-
-/* Additional file access control and file status flags for internal use */
-#define FA_SEEKEND 0x20 /* Seek to end of the file on file open */
-#define FA_MODIFIED 0x40 /* File has been modified */
-#define FA_DIRTY 0x80 /* FIL.buf[] needs to be written-back */
-
-
-/* Name status flags in fn[11] */
-#define NSFLAG 11 /* Index of the name status byte */
-#define NS_LOSS 0x01 /* Out of 8.3 format */
-#define NS_LFN 0x02 /* Force to create LFN entry */
-#define NS_LAST 0x04 /* Last segment */
-#define NS_BODY 0x08 /* Lower case flag (body) */
-#define NS_EXT 0x10 /* Lower case flag (ext) */
-#define NS_DOT 0x20 /* Dot entry */
-#define NS_NOLFN 0x40 /* Do not find LFN */
-#define NS_NONAME 0x80 /* Not followed */
-
-
-/* Limits and boundaries */
-#define MAX_DIR 0x200000 /* Max size of FAT directory */
-#define MAX_DIR_EX 0x10000000 /* Max size of exFAT directory */
-#define MAX_FAT12 0xFF5 /* Max FAT12 clusters (differs from specs, but right for real DOS/Windows behavior) */
-#define MAX_FAT16 0xFFF5 /* Max FAT16 clusters (differs from specs, but right for real DOS/Windows behavior) */
-#define MAX_FAT32 0x0FFFFFF5 /* Max FAT32 clusters (not specified, practical limit) */
-#define MAX_EXFAT 0x7FFFFFFD /* Max exFAT clusters (differs from specs, implementation limit) */
-
-
-/* FatFs refers the FAT structure as simple byte array instead of structure member
-/ because the C structure is not binary compatible between different platforms */
-
-#define BS_JmpBoot 0 /* x86 jump instruction (3-byte) */
-#define BS_OEMName 3 /* OEM name (8-byte) */
-#define BPB_BytsPerSec 11 /* Sector size [byte] (WORD) */
-#define BPB_SecPerClus 13 /* Cluster size [sector] (BYTE) */
-#define BPB_RsvdSecCnt 14 /* Size of reserved area [sector] (WORD) */
-#define BPB_NumFATs 16 /* Number of FATs (BYTE) */
-#define BPB_RootEntCnt 17 /* Size of root directory area for FAT [entry] (WORD) */
-#define BPB_TotSec16 19 /* Volume size (16-bit) [sector] (WORD) */
-#define BPB_Media 21 /* Media descriptor byte (BYTE) */
-#define BPB_FATSz16 22 /* FAT size (16-bit) [sector] (WORD) */
-#define BPB_SecPerTrk 24 /* Number of sectors per track for int13h [sector] (WORD) */
-#define BPB_NumHeads 26 /* Number of heads for int13h (WORD) */
-#define BPB_HiddSec 28 /* Volume offset from top of the drive (DWORD) */
-#define BPB_TotSec32 32 /* Volume size (32-bit) [sector] (DWORD) */
-#define BS_DrvNum 36 /* Physical drive number for int13h (BYTE) */
-#define BS_NTres 37 /* WindowsNT error flag (BYTE) */
-#define BS_BootSig 38 /* Extended boot signature (BYTE) */
-#define BS_VolID 39 /* Volume serial number (DWORD) */
-#define BS_VolLab 43 /* Volume label string (8-byte) */
-#define BS_FilSysType 54 /* Filesystem type string (8-byte) */
-#define BS_BootCode 62 /* Boot code (448-byte) */
-#define BS_55AA 510 /* Signature word (WORD) */
-
-#define BPB_FATSz32 36 /* FAT32: FAT size [sector] (DWORD) */
-#define BPB_ExtFlags32 40 /* FAT32: Extended flags (WORD) */
-#define BPB_FSVer32 42 /* FAT32: Filesystem version (WORD) */
-#define BPB_RootClus32 44 /* FAT32: Root directory cluster (DWORD) */
-#define BPB_FSInfo32 48 /* FAT32: Offset of FSINFO sector (WORD) */
-#define BPB_BkBootSec32 50 /* FAT32: Offset of backup boot sector (WORD) */
-#define BS_DrvNum32 64 /* FAT32: Physical drive number for int13h (BYTE) */
-#define BS_NTres32 65 /* FAT32: Error flag (BYTE) */
-#define BS_BootSig32 66 /* FAT32: Extended boot signature (BYTE) */
-#define BS_VolID32 67 /* FAT32: Volume serial number (DWORD) */
-#define BS_VolLab32 71 /* FAT32: Volume label string (8-byte) */
-#define BS_FilSysType32 82 /* FAT32: Filesystem type string (8-byte) */
-#define BS_BootCode32 90 /* FAT32: Boot code (420-byte) */
-
-#define BPB_ZeroedEx 11 /* exFAT: MBZ field (53-byte) */
-#define BPB_VolOfsEx 64 /* exFAT: Volume offset from top of the drive [sector] (QWORD) */
-#define BPB_TotSecEx 72 /* exFAT: Volume size [sector] (QWORD) */
-#define BPB_FatOfsEx 80 /* exFAT: FAT offset from top of the volume [sector] (DWORD) */
-#define BPB_FatSzEx 84 /* exFAT: FAT size [sector] (DWORD) */
-#define BPB_DataOfsEx 88 /* exFAT: Data offset from top of the volume [sector] (DWORD) */
-#define BPB_NumClusEx 92 /* exFAT: Number of clusters (DWORD) */
-#define BPB_RootClusEx 96 /* exFAT: Root directory start cluster (DWORD) */
-#define BPB_VolIDEx 100 /* exFAT: Volume serial number (DWORD) */
-#define BPB_FSVerEx 104 /* exFAT: Filesystem version (WORD) */
-#define BPB_VolFlagEx 106 /* exFAT: Volume flags (WORD) */
-#define BPB_BytsPerSecEx 108 /* exFAT: Log2 of sector size in unit of byte (BYTE) */
-#define BPB_SecPerClusEx 109 /* exFAT: Log2 of cluster size in unit of sector (BYTE) */
-#define BPB_NumFATsEx 110 /* exFAT: Number of FATs (BYTE) */
-#define BPB_DrvNumEx 111 /* exFAT: Physical drive number for int13h (BYTE) */
-#define BPB_PercInUseEx 112 /* exFAT: Percent in use (BYTE) */
-#define BPB_RsvdEx 113 /* exFAT: Reserved (7-byte) */
-#define BS_BootCodeEx 120 /* exFAT: Boot code (390-byte) */
-
-#define DIR_Name 0 /* Short file name (11-byte) */
-#define DIR_Attr 11 /* Attribute (BYTE) */
-#define DIR_NTres 12 /* Lower case flag (BYTE) */
-#define DIR_CrtTime10 13 /* Created time sub-second (BYTE) */
-#define DIR_CrtTime 14 /* Created time (DWORD) */
-#define DIR_LstAccDate 18 /* Last accessed date (WORD) */
-#define DIR_FstClusHI 20 /* Higher 16-bit of first cluster (WORD) */
-#define DIR_ModTime 22 /* Modified time (DWORD) */
-#define DIR_FstClusLO 26 /* Lower 16-bit of first cluster (WORD) */
-#define DIR_FileSize 28 /* File size (DWORD) */
-#define LDIR_Ord 0 /* LFN: LFN order and LLE flag (BYTE) */
-#define LDIR_Attr 11 /* LFN: LFN attribute (BYTE) */
-#define LDIR_Type 12 /* LFN: Entry type (BYTE) */
-#define LDIR_Chksum 13 /* LFN: Checksum of the SFN (BYTE) */
-#define LDIR_FstClusLO 26 /* LFN: MBZ field (WORD) */
-#define XDIR_Type 0 /* exFAT: Type of exFAT directory entry (BYTE) */
-#define XDIR_NumLabel 1 /* exFAT: Number of volume label characters (BYTE) */
-#define XDIR_Label 2 /* exFAT: Volume label (11-WORD) */
-#define XDIR_CaseSum 4 /* exFAT: Sum of case conversion table (DWORD) */
-#define XDIR_NumSec 1 /* exFAT: Number of secondary entries (BYTE) */
-#define XDIR_SetSum 2 /* exFAT: Sum of the set of directory entries (WORD) */
-#define XDIR_Attr 4 /* exFAT: File attribute (WORD) */
-#define XDIR_CrtTime 8 /* exFAT: Created time (DWORD) */
-#define XDIR_ModTime 12 /* exFAT: Modified time (DWORD) */
-#define XDIR_AccTime 16 /* exFAT: Last accessed time (DWORD) */
-#define XDIR_CrtTime10 20 /* exFAT: Created time subsecond (BYTE) */
-#define XDIR_ModTime10 21 /* exFAT: Modified time subsecond (BYTE) */
-#define XDIR_CrtTZ 22 /* exFAT: Created timezone (BYTE) */
-#define XDIR_ModTZ 23 /* exFAT: Modified timezone (BYTE) */
-#define XDIR_AccTZ 24 /* exFAT: Last accessed timezone (BYTE) */
-#define XDIR_GenFlags 33 /* exFAT: General secondary flags (BYTE) */
-#define XDIR_NumName 35 /* exFAT: Number of file name characters (BYTE) */
-#define XDIR_NameHash 36 /* exFAT: Hash of file name (WORD) */
-#define XDIR_ValidFileSize 40 /* exFAT: Valid file size (QWORD) */
-#define XDIR_FstClus 52 /* exFAT: First cluster of the file data (DWORD) */
-#define XDIR_FileSize 56 /* exFAT: File/Directory size (QWORD) */
-
-#define SZDIRE 32 /* Size of a directory entry */
-#define DDEM 0xE5 /* Deleted directory entry mark set to DIR_Name[0] */
-#define RDDEM 0x05 /* Replacement of the character collides with DDEM */
-#define LLEF 0x40 /* Last long entry flag in LDIR_Ord */
-
-#define FSI_LeadSig 0 /* FAT32 FSI: Leading signature (DWORD) */
-#define FSI_StrucSig 484 /* FAT32 FSI: Structure signature (DWORD) */
-#define FSI_Free_Count 488 /* FAT32 FSI: Number of free clusters (DWORD) */
-#define FSI_Nxt_Free 492 /* FAT32 FSI: Last allocated cluster (DWORD) */
-
-#define MBR_Table 446 /* MBR: Offset of partition table in the MBR */
-#define SZ_PTE 16 /* MBR: Size of a partition table entry */
-#define PTE_Boot 0 /* MBR PTE: Boot indicator */
-#define PTE_StHead 1 /* MBR PTE: Start head */
-#define PTE_StSec 2 /* MBR PTE: Start sector */
-#define PTE_StCyl 3 /* MBR PTE: Start cylinder */
-#define PTE_System 4 /* MBR PTE: System ID */
-#define PTE_EdHead 5 /* MBR PTE: End head */
-#define PTE_EdSec 6 /* MBR PTE: End sector */
-#define PTE_EdCyl 7 /* MBR PTE: End cylinder */
-#define PTE_StLba 8 /* MBR PTE: Start in LBA */
-#define PTE_SizLba 12 /* MBR PTE: Size in LBA */
-
-
-/* Post process on fatal error in the file operations */
-#define ABORT(fs, res) { fp->err = (BYTE)(res); LEAVE_FF(fs, res); }
-
-
-/* Re-entrancy related */
-#if FF_FS_REENTRANT
-#if FF_USE_LFN == 1
-#error Static LFN work area cannot be used at thread-safe configuration
-#endif
-#define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; }
-#else
-#define LEAVE_FF(fs, res) return res
-#endif
-
-
-/* Definitions of volume - physical location conversion */
-#if FF_MULTI_PARTITION
-#define LD2PD(vol) VolToPart[vol].pd /* Get physical drive number */
-#define LD2PT(vol) VolToPart[vol].pt /* Get partition index */
-#else
-#define LD2PD(vol) (BYTE)(vol) /* Each logical drive is bound to the same physical drive number */
-#define LD2PT(vol) 0 /* Find first valid partition or in SFD */
-#endif
-
-
-/* Definitions of sector size */
-#if (FF_MAX_SS < FF_MIN_SS) || (FF_MAX_SS != 512 && FF_MAX_SS != 1024 && FF_MAX_SS != 2048 && FF_MAX_SS != 4096) || (FF_MIN_SS != 512 && FF_MIN_SS != 1024 && FF_MIN_SS != 2048 && FF_MIN_SS != 4096)
-#error Wrong sector size configuration
-#endif
-#if FF_MAX_SS == FF_MIN_SS
-#define SS(fs) ((UINT)FF_MAX_SS) /* Fixed sector size */
-#else
-#define SS(fs) ((fs)->ssize) /* Variable sector size */
-#endif
-
-
-/* Timestamp */
-#if FF_FS_NORTC == 1
-#if FF_NORTC_YEAR < 1980 || FF_NORTC_YEAR > 2107 || FF_NORTC_MON < 1 || FF_NORTC_MON > 12 || FF_NORTC_MDAY < 1 || FF_NORTC_MDAY > 31
-#error Invalid FF_FS_NORTC settings
-#endif
-#define GET_FATTIME() ((DWORD)(FF_NORTC_YEAR - 1980) << 25 | (DWORD)FF_NORTC_MON << 21 | (DWORD)FF_NORTC_MDAY << 16)
-#else
-#define GET_FATTIME() get_fattime()
-#endif
-
-
-/* File lock controls */
-#if FF_FS_LOCK != 0
-#if FF_FS_READONLY
-#error FF_FS_LOCK must be 0 at read-only configuration
-#endif
-typedef struct {
- FATFS *fs; /* Object ID 1, volume (NULL:blank entry) */
- DWORD clu; /* Object ID 2, containing directory (0:root) */
- DWORD ofs; /* Object ID 3, offset in the directory */
- WORD ctr; /* Object open counter, 0:none, 0x01..0xFF:read mode open count, 0x100:write mode */
-} FILESEM;
-#endif
-
-
-/* SBCS up-case tables (\x80-\xFF) */
-#define TBL_CT437 {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
- 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
- 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
- 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
- 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-#define TBL_CT720 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
- 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
- 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
- 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
- 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-#define TBL_CT737 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
- 0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
- 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96, \
- 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
- 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xEF,0xF5,0xF0,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
- 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-#define TBL_CT771 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
- 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
- 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
- 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDC,0xDE,0xDE, \
- 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFE,0xFF}
-#define TBL_CT775 {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F, \
- 0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
- 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
- 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
- 0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF, \
- 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-#define TBL_CT850 {0x43,0x55,0x45,0x41,0x41,0x41,0x41,0x43,0x45,0x45,0x45,0x49,0x49,0x49,0x41,0x41, \
- 0x45,0x92,0x92,0x4F,0x4F,0x4F,0x55,0x55,0x59,0x4F,0x55,0x4F,0x9C,0x4F,0x9E,0x9F, \
- 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
- 0xB0,0xB1,0xB2,0xB3,0xB4,0x41,0x41,0x41,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0x41,0x41,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
- 0xD1,0xD1,0x45,0x45,0x45,0x49,0x49,0x49,0x49,0xD9,0xDA,0xDB,0xDC,0xDD,0x49,0xDF, \
- 0x4F,0xE1,0x4F,0x4F,0x4F,0x4F,0xE6,0xE8,0xE8,0x55,0x55,0x55,0x59,0x59,0xEE,0xEF, \
- 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-#define TBL_CT852 {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F, \
- 0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0xAC, \
- 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF, \
- 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
- 0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF, \
- 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
-#define TBL_CT855 {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F, \
- 0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
- 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF, \
- 0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
- 0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
- 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF, \
- 0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
-#define TBL_CT857 {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x49,0x8E,0x8F, \
- 0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
- 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
- 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
- 0xD0,0xD1,0xD2,0xD3,0xD4,0x49,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0xED,0xEE,0xEF, \
- 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-#define TBL_CT860 {0x80,0x9A,0x90,0x8F,0x8E,0x91,0x86,0x80,0x89,0x89,0x92,0x8B,0x8C,0x98,0x8E,0x8F, \
- 0x90,0x91,0x92,0x8C,0x99,0xA9,0x96,0x9D,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0x86,0x8B,0x9F,0x96,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
- 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
- 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
- 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-#define TBL_CT861 {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x8B,0x8B,0x8D,0x8E,0x8F, \
- 0x90,0x92,0x92,0x4F,0x99,0x8D,0x55,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
- 0xA4,0xA5,0xA6,0xA7,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
- 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
- 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
- 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-#define TBL_CT862 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
- 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
- 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
- 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
- 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-#define TBL_CT863 {0x43,0x55,0x45,0x41,0x41,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x41,0x8F, \
- 0x45,0x45,0x45,0x4F,0x45,0x49,0x55,0x55,0x98,0x4F,0x55,0x9B,0x9C,0x55,0x55,0x9F, \
- 0xA0,0xA1,0x4F,0x55,0xA4,0xA5,0xA6,0xA7,0x49,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
- 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
- 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
- 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-#define TBL_CT864 {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
- 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
- 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
- 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
- 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-#define TBL_CT865 {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
- 0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
- 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
- 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
- 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-#define TBL_CT866 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
- 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
- 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
- 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
- 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
- 0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-#define TBL_CT869 {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
- 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x86,0x9C,0x8D,0x8F,0x90, \
- 0x91,0x90,0x92,0x95,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
- 0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
- 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
- 0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xA4,0xA5,0xA6,0xD9,0xDA,0xDB,0xDC,0xA7,0xA8,0xDF, \
- 0xA9,0xAA,0xAC,0xAD,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xCF,0xCF,0xD0,0xEF, \
- 0xF0,0xF1,0xD1,0xD2,0xD3,0xF5,0xD4,0xF7,0xF8,0xF9,0xD5,0x96,0x95,0x98,0xFE,0xFF}
-
-
-/* DBCS code range |----- 1st byte -----| |----------- 2nd byte -----------| */
-#define TBL_DC932 {0x81, 0x9F, 0xE0, 0xFC, 0x40, 0x7E, 0x80, 0xFC, 0x00, 0x00}
-#define TBL_DC936 {0x81, 0xFE, 0x00, 0x00, 0x40, 0x7E, 0x80, 0xFE, 0x00, 0x00}
-#define TBL_DC949 {0x81, 0xFE, 0x00, 0x00, 0x41, 0x5A, 0x61, 0x7A, 0x81, 0xFE}
-#define TBL_DC950 {0x81, 0xFE, 0x00, 0x00, 0x40, 0x7E, 0xA1, 0xFE, 0x00, 0x00}
-
-
-/* Macros for table definitions */
-#define MERGE_2STR(a, b) a ## b
-#define MKCVTBL(hd, cp) MERGE_2STR(hd, cp)
-
-
-
-
-/*--------------------------------------------------------------------------
-
- Module Private Work Area
-
----------------------------------------------------------------------------*/
-/* Remark: Variables defined here without initial value shall be guaranteed
-/ zero/null at start-up. If not, the linker option or start-up routine is
-/ not compliance with C standard. */
-
-/*--------------------------------*/
-/* File/Volume controls */
-/*--------------------------------*/
-
-#if FF_VOLUMES < 1 || FF_VOLUMES > 10
-#error Wrong FF_VOLUMES setting
-#endif
-static FATFS* FatFs[FF_VOLUMES]; /* Pointer to the filesystem objects (logical drives) */
-static WORD Fsid; /* Filesystem mount ID */
-
-#if FF_FS_RPATH != 0
-static BYTE CurrVol; /* Current drive */
-#endif
-
-#if FF_FS_LOCK != 0
-static FILESEM Files[FF_FS_LOCK]; /* Open object lock semaphores */
-#endif
-
-#if FF_STR_VOLUME_ID
-#ifdef FF_VOLUME_STRS
-static const char* const VolumeStr[FF_VOLUMES] = {FF_VOLUME_STRS}; /* Pre-defined volume ID */
-#endif
-#endif
-
-
-/*--------------------------------*/
-/* LFN/Directory working buffer */
-/*--------------------------------*/
-
-#if FF_USE_LFN == 0 /* Non-LFN configuration */
-#if FF_FS_EXFAT
-#error LFN must be enabled when enable exFAT
-#endif
-#define DEF_NAMBUF
-#define INIT_NAMBUF(fs)
-#define FREE_NAMBUF()
-#define LEAVE_MKFS(res) return res
-
-#else /* LFN configurations */
-#if FF_MAX_LFN < 12 || FF_MAX_LFN > 255
-#error Wrong setting of FF_MAX_LFN
-#endif
-#if FF_LFN_BUF < FF_SFN_BUF || FF_SFN_BUF < 12
-#error Wrong setting of FF_LFN_BUF or FF_SFN_BUF
-#endif
-#if FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3
-#error Wrong setting of FF_LFN_UNICODE
-#endif
-static const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* FAT: Offset of LFN characters in the directory entry */
-#define MAXDIRB(nc) ((nc + 44U) / 15 * SZDIRE) /* exFAT: Size of directory entry block scratchpad buffer needed for the name length */
-
-#if FF_USE_LFN == 1 /* LFN enabled with static working buffer */
-#if FF_FS_EXFAT
-static BYTE DirBuf[MAXDIRB(FF_MAX_LFN)]; /* Directory entry block scratchpad buffer */
-#endif
-static WCHAR LfnBuf[FF_MAX_LFN + 1]; /* LFN working buffer */
-#define DEF_NAMBUF
-#define INIT_NAMBUF(fs)
-#define FREE_NAMBUF()
-#define LEAVE_MKFS(res) return res
-
-#elif FF_USE_LFN == 2 /* LFN enabled with dynamic working buffer on the stack */
-#if FF_FS_EXFAT
-#define DEF_NAMBUF WCHAR lbuf[FF_MAX_LFN+1]; BYTE dbuf[MAXDIRB(FF_MAX_LFN)]; /* LFN working buffer and directory entry block scratchpad buffer */
-#define INIT_NAMBUF(fs) { (fs)->lfnbuf = lbuf; (fs)->dirbuf = dbuf; }
-#define FREE_NAMBUF()
-#else
-#define DEF_NAMBUF WCHAR lbuf[FF_MAX_LFN+1]; /* LFN working buffer */
-#define INIT_NAMBUF(fs) { (fs)->lfnbuf = lbuf; }
-#define FREE_NAMBUF()
-#endif
-#define LEAVE_MKFS(res) return res
-
-#elif FF_USE_LFN == 3 /* LFN enabled with dynamic working buffer on the heap */
-#if FF_FS_EXFAT
-#define DEF_NAMBUF WCHAR *lfn; /* Pointer to LFN working buffer and directory entry block scratchpad buffer */
-#define INIT_NAMBUF(fs) { lfn = ff_memalloc((FF_MAX_LFN+1)*2 + MAXDIRB(FF_MAX_LFN)); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; (fs)->dirbuf = (BYTE*)(lfn+FF_MAX_LFN+1); }
-#define FREE_NAMBUF() ff_memfree(lfn)
-#else
-#define DEF_NAMBUF WCHAR *lfn; /* Pointer to LFN working buffer */
-#define INIT_NAMBUF(fs) { lfn = ff_memalloc((FF_MAX_LFN+1)*2); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; }
-#define FREE_NAMBUF() ff_memfree(lfn)
-#endif
-#define LEAVE_MKFS(res) { if (!work) ff_memfree(buf); return res; }
-#define MAX_MALLOC 0x8000 /* Must be >=FF_MAX_SS */
-
-#else
-#error Wrong setting of FF_USE_LFN
-
-#endif /* FF_USE_LFN == 1 */
-#endif /* FF_USE_LFN == 0 */
-
-
-
-/*--------------------------------*/
-/* Code conversion tables */
-/*--------------------------------*/
-
-#if FF_CODE_PAGE == 0 /* Run-time code page configuration */
-#define CODEPAGE CodePage
-static WORD CodePage; /* Current code page */
-static const BYTE *ExCvt, *DbcTbl; /* Pointer to current SBCS up-case table and DBCS code range table below */
-static const BYTE Ct437[] = TBL_CT437;
-static const BYTE Ct720[] = TBL_CT720;
-static const BYTE Ct737[] = TBL_CT737;
-static const BYTE Ct771[] = TBL_CT771;
-static const BYTE Ct775[] = TBL_CT775;
-static const BYTE Ct850[] = TBL_CT850;
-static const BYTE Ct852[] = TBL_CT852;
-static const BYTE Ct855[] = TBL_CT855;
-static const BYTE Ct857[] = TBL_CT857;
-static const BYTE Ct860[] = TBL_CT860;
-static const BYTE Ct861[] = TBL_CT861;
-static const BYTE Ct862[] = TBL_CT862;
-static const BYTE Ct863[] = TBL_CT863;
-static const BYTE Ct864[] = TBL_CT864;
-static const BYTE Ct865[] = TBL_CT865;
-static const BYTE Ct866[] = TBL_CT866;
-static const BYTE Ct869[] = TBL_CT869;
-static const BYTE Dc932[] = TBL_DC932;
-static const BYTE Dc936[] = TBL_DC936;
-static const BYTE Dc949[] = TBL_DC949;
-static const BYTE Dc950[] = TBL_DC950;
-
-#elif FF_CODE_PAGE < 900 /* Static code page configuration (SBCS) */
-#define CODEPAGE FF_CODE_PAGE
-static const BYTE ExCvt[] = MKCVTBL(TBL_CT, FF_CODE_PAGE);
-
-#else /* Static code page configuration (DBCS) */
-#define CODEPAGE FF_CODE_PAGE
-static const BYTE DbcTbl[] = MKCVTBL(TBL_DC, FF_CODE_PAGE);
-
-#endif
-
-#if FF_MULTI_PARTITION
-PARTITION VolToPart[] = {
- {0, 0}, /* Logical drive 0 ==> Physical drive 0, 0th partition */
- {0, 1}, /* Logical drive 1 ==> Physical drive 0, 1st partition */
- {0, 2}, /* Logical drive 2 ==> Physical drive 0, 2nd partition */
- {0, 3}, /* Logical drive 3 ==> Physical drive 0, 3rd partition */
- {0, 4}, /* Logical drive 4 ==> Physical drive 0, 4th partition */
- {1, 0}, /* Logical drive 5 ==> Physical drive 1, 0th partition */
- {1, 1}, /* Logical drive 6 ==> Physical drive 1, 1st partition */
- {1, 2}, /* Logical drive 7 ==> Physical drive 1, 2nd partition */
- {1, 3}, /* Logical drive 8 ==> Physical drive 1, 3rd partition */
- {1, 4} /* Logical drive 9 ==> Physical drive 1, 4th partition */
-};
-#endif
-
-
-
-/*--------------------------------------------------------------------------
-
- Module Private Functions
-
----------------------------------------------------------------------------*/
-
-
-/*-----------------------------------------------------------------------*/
-/* Load/Store multi-byte word in the FAT structure */
-/*-----------------------------------------------------------------------*/
-
-static WORD ld_word (const BYTE* ptr) /* Load a 2-byte little-endian word */
-{
- WORD rv;
-
- rv = ptr[1];
- rv = rv << 8 | ptr[0];
- return rv;
-}
-
-static DWORD ld_dword (const BYTE* ptr) /* Load a 4-byte little-endian word */
-{
- DWORD rv;
-
- rv = ptr[3];
- rv = rv << 8 | ptr[2];
- rv = rv << 8 | ptr[1];
- rv = rv << 8 | ptr[0];
- return rv;
-}
-
-#if FF_FS_EXFAT
-static QWORD ld_qword (const BYTE* ptr) /* Load an 8-byte little-endian word */
-{
- QWORD rv;
-
- rv = ptr[7];
- rv = rv << 8 | ptr[6];
- rv = rv << 8 | ptr[5];
- rv = rv << 8 | ptr[4];
- rv = rv << 8 | ptr[3];
- rv = rv << 8 | ptr[2];
- rv = rv << 8 | ptr[1];
- rv = rv << 8 | ptr[0];
- return rv;
-}
-#endif
-
-#if !FF_FS_READONLY
-static void st_word (BYTE* ptr, WORD val) /* Store a 2-byte word in little-endian */
-{
- *ptr++ = (BYTE)val; val >>= 8;
- *ptr++ = (BYTE)val;
-}
-
-static void st_dword (BYTE* ptr, DWORD val) /* Store a 4-byte word in little-endian */
-{
- *ptr++ = (BYTE)val; val >>= 8;
- *ptr++ = (BYTE)val; val >>= 8;
- *ptr++ = (BYTE)val; val >>= 8;
- *ptr++ = (BYTE)val;
-}
-
-#if FF_FS_EXFAT
-static void st_qword (BYTE* ptr, QWORD val) /* Store an 8-byte word in little-endian */
-{
- *ptr++ = (BYTE)val; val >>= 8;
- *ptr++ = (BYTE)val; val >>= 8;
- *ptr++ = (BYTE)val; val >>= 8;
- *ptr++ = (BYTE)val; val >>= 8;
- *ptr++ = (BYTE)val; val >>= 8;
- *ptr++ = (BYTE)val; val >>= 8;
- *ptr++ = (BYTE)val; val >>= 8;
- *ptr++ = (BYTE)val;
-}
-#endif
-#endif /* !FF_FS_READONLY */
-
-
-
-/*-----------------------------------------------------------------------*/
-/* String functions */
-/*-----------------------------------------------------------------------*/
-
-/* Copy memory to memory */
-static void mem_cpy (void* dst, const void* src, UINT cnt)
-{
- BYTE *d = (BYTE*)dst;
- const BYTE *s = (const BYTE*)src;
-
-#if FF_WORD_ACCESS == 1
- while (cnt >= sizeof (int)) {
- *(int*)d = *(int*)s;
- d += sizeof (int); s += sizeof (int);
- cnt -= sizeof (int);
- }
-#endif
- if (cnt != 0) {
- do {
- *d++ = *s++;
- } while (--cnt);
- }
-}
-
-
-/* Fill memory block */
-static void mem_set (void* dst, int val, UINT cnt)
-{
- BYTE *d = (BYTE*)dst;
-
- do {
- *d++ = (BYTE)val;
- } while (--cnt);
-}
-
-
-/* Compare memory block */
-static int mem_cmp (const void* dst, const void* src, UINT cnt) /* ZR:same, NZ:different */
-{
- const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src;
- int r = 0;
-
- do {
- r = *d++ - *s++;
- } while (--cnt && r == 0);
-
- return r;
-}
-
-
-/* Check if chr is contained in the string */
-static int chk_chr (const char* str, int chr) /* NZ:contained, ZR:not contained */
-{
- while (*str && *str != chr) str++;
- return *str;
-}
-
-
-/* Test if the character is DBC 1st byte */
-static int dbc_1st (BYTE c)
-{
-#if FF_CODE_PAGE == 0 /* Variable code page */
- if (DbcTbl && c >= DbcTbl[0]) {
- if (c <= DbcTbl[1]) return 1; /* 1st byte range 1 */
- if (c >= DbcTbl[2] && c <= DbcTbl[3]) return 1; /* 1st byte range 2 */
- }
-#elif FF_CODE_PAGE >= 900 /* DBCS fixed code page */
- if (c >= DbcTbl[0]) {
- if (c <= DbcTbl[1]) return 1;
- if (c >= DbcTbl[2] && c <= DbcTbl[3]) return 1;
- }
-#else /* SBCS fixed code page */
- if (c != 0) return 0; /* Always false */
-#endif
- return 0;
-}
-
-
-/* Test if the character is DBC 2nd byte */
-static int dbc_2nd (BYTE c)
-{
-#if FF_CODE_PAGE == 0 /* Variable code page */
- if (DbcTbl && c >= DbcTbl[4]) {
- if (c <= DbcTbl[5]) return 1; /* 2nd byte range 1 */
- if (c >= DbcTbl[6] && c <= DbcTbl[7]) return 1; /* 2nd byte range 2 */
- if (c >= DbcTbl[8] && c <= DbcTbl[9]) return 1; /* 2nd byte range 3 */
- }
-#elif FF_CODE_PAGE >= 900 /* DBCS fixed code page */
- if (c >= DbcTbl[4]) {
- if (c <= DbcTbl[5]) return 1;
- if (c >= DbcTbl[6] && c <= DbcTbl[7]) return 1;
- if (c >= DbcTbl[8] && c <= DbcTbl[9]) return 1;
- }
-#else /* SBCS fixed code page */
- if (c != 0) return 0; /* Always false */
-#endif
- return 0;
-}
-
-
-#if FF_USE_LFN
-
-/* Get a character from TCHAR string in defined API encodeing */
-static DWORD tchar2uni ( /* Returns character in UTF-16 encoding (>=0x10000 on double encoding unit, 0xFFFFFFFF on decode error) */
- const TCHAR** str /* Pointer to pointer to TCHAR string in configured encoding */
-)
-{
- DWORD uc;
- const TCHAR *p = *str;
-
-#if FF_LFN_UNICODE == 1 /* UTF-16 input */
- WCHAR wc;
-
- uc = *p++; /* Get a unit */
- if (IsSurrogate(uc)) { /* Surrogate? */
- wc = *p++; /* Get low surrogate */
- if (!IsSurrogateH(uc) || !IsSurrogateL(wc)) return 0xFFFFFFFF; /* Wrong surrogate? */
- uc = uc << 16 | wc;
- }
-
-#elif FF_LFN_UNICODE == 2 /* UTF-8 input */
- BYTE b;
- int nf;
-
- uc = (BYTE)*p++; /* Get a unit */
- if (uc & 0x80) { /* Multiple byte code? */
- if ((uc & 0xE0) == 0xC0) { /* 2-byte sequence? */
- uc &= 0x1F; nf = 1;
- } else {
- if ((uc & 0xF0) == 0xE0) { /* 3-byte sequence? */
- uc &= 0x0F; nf = 2;
- } else {
- if ((uc & 0xF8) == 0xF0) { /* 4-byte sequence? */
- uc &= 0x07; nf = 3;
- } else { /* Wrong sequence */
- return 0xFFFFFFFF;
- }
- }
- }
- do { /* Get trailing bytes */
- b = (BYTE)*p++;
- if ((b & 0xC0) != 0x80) return 0xFFFFFFFF; /* Wrong sequence? */
- uc = uc << 6 | (b & 0x3F);
- } while (--nf != 0);
- if (uc < 0x80 || IsSurrogate(uc) || uc >= 0x110000) return 0xFFFFFFFF; /* Wrong code? */
- if (uc >= 0x010000) uc = 0xD800DC00 | ((uc - 0x10000) << 6 & 0x3FF0000) | (uc & 0x3FF); /* Make a surrogate pair if needed */
- }
-
-#elif FF_LFN_UNICODE == 3 /* UTF-32 input */
- uc = (TCHAR)*p++; /* Get a unit */
- if (uc >= 0x110000) return 0xFFFFFFFF; /* Wrong code? */
- if (uc >= 0x010000) uc = 0xD800DC00 | ((uc - 0x10000) << 6 & 0x3FF0000) | (uc & 0x3FF); /* Make a surrogate pair if needed */
-
-#else /* ANSI/OEM input */
- BYTE b;
- WCHAR wc;
-
- wc = (BYTE)*p++; /* Get a byte */
- if (dbc_1st((BYTE)wc)) { /* Is it a DBC 1st byte? */
- b = (BYTE)*p++; /* Get 2nd byte */
- if (!dbc_2nd(b)) return 0xFFFFFFFF; /* Invalid code? */
- wc = (wc << 8) + b; /* Make a DBC */
- }
- if (wc != 0) {
- wc = ff_oem2uni(wc, CODEPAGE); /* ANSI/OEM ==> Unicode */
- if (wc == 0) return 0xFFFFFFFF; /* Invalid code? */
- }
- uc = wc;
-
-#endif
- *str = p; /* Next read pointer */
- return uc;
-}
-
-
-/* Output a TCHAR string in defined API encoding */
-static BYTE put_utf ( /* Returns number of encoding units written (0:buffer overflow or wrong encoding) */
- DWORD chr, /* UTF-16 encoded character (Double encoding unit char if >=0x10000) */
- TCHAR* buf, /* Output buffer */
- UINT szb /* Size of the buffer */
-)
-{
-#if FF_LFN_UNICODE == 1 /* UTF-16 output */
- WCHAR hs, wc;
-
- hs = (WCHAR)(chr >> 16);
- wc = (WCHAR)chr;
- if (hs == 0) { /* Single encoding unit? */
- if (szb < 1 || IsSurrogate(wc)) return 0; /* Buffer overflow or wrong code? */
- *buf = wc;
- return 1;
- }
- if (szb < 2 || !IsSurrogateH(hs) || !IsSurrogateL(wc)) return 0; /* Buffer overflow or wrong surrogate? */
- *buf++ = hs;
- *buf++ = wc;
- return 2;
-
-#elif FF_LFN_UNICODE == 2 /* UTF-8 output */
- DWORD hc;
-
- if (chr < 0x80) { /* Single byte code? */
- if (szb < 1) return 0; /* Buffer overflow? */
- *buf = (TCHAR)chr;
- return 1;
- }
- if (chr < 0x800) { /* 2-byte sequence? */
- if (szb < 2) return 0; /* Buffer overflow? */
- *buf++ = (TCHAR)(0xC0 | (chr >> 6 & 0x1F));
- *buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F));
- return 2;
- }
- if (chr < 0x10000) { /* 3-byte sequence? */
- if (szb < 3 || IsSurrogate(chr)) return 0; /* Buffer overflow or wrong code? */
- *buf++ = (TCHAR)(0xE0 | (chr >> 12 & 0x0F));
- *buf++ = (TCHAR)(0x80 | (chr >> 6 & 0x3F));
- *buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F));
- return 3;
- }
- /* 4-byte sequence */
- if (szb < 4) return 0; /* Buffer overflow? */
- hc = ((chr & 0xFFFF0000) - 0xD8000000) >> 6; /* Get high 10 bits */
- chr = (chr & 0xFFFF) - 0xDC00; /* Get low 10 bits */
- if (hc >= 0x100000 || chr >= 0x400) return 0; /* Wrong surrogate? */
- chr = (hc | chr) + 0x10000;
- *buf++ = (TCHAR)(0xF0 | (chr >> 18 & 0x07));
- *buf++ = (TCHAR)(0x80 | (chr >> 12 & 0x3F));
- *buf++ = (TCHAR)(0x80 | (chr >> 6 & 0x3F));
- *buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F));
- return 4;
-
-#elif FF_LFN_UNICODE == 3 /* UTF-32 output */
- DWORD hc;
-
- if (szb < 1) return 0; /* Buffer overflow? */
- if (chr >= 0x10000) { /* Out of BMP? */
- hc = ((chr & 0xFFFF0000) - 0xD8000000) >> 6; /* Get high 10 bits */
- chr = (chr & 0xFFFF) - 0xDC00; /* Get low 10 bits */
- if (hc >= 0x100000 || chr >= 0x400) return 0; /* Wrong surrogate? */
- chr = (hc | chr) + 0x10000;
- }
- *buf++ = (TCHAR)chr;
- return 1;
-
-#else /* ANSI/OEM output */
- WCHAR wc;
-
- wc = ff_uni2oem(chr, CODEPAGE);
- if (wc >= 0x100) { /* Is this a DBC? */
- if (szb < 2) return 0;
- *buf++ = (char)(wc >> 8); /* Store DBC 1st byte */
- *buf++ = (TCHAR)wc; /* Store DBC 2nd byte */
- return 2;
- }
- if (wc == 0 || szb < 1) return 0; /* Invalid char or buffer overflow? */
- *buf++ = (TCHAR)wc; /* Store the character */
- return 1;
-#endif
-}
-#endif /* FF_USE_LFN */
-
-
-#if FF_FS_REENTRANT
-/*-----------------------------------------------------------------------*/
-/* Request/Release grant to access the volume */
-/*-----------------------------------------------------------------------*/
-static int lock_fs ( /* 1:Ok, 0:timeout */
- FATFS* fs /* Filesystem object */
-)
-{
- return ff_req_grant(fs->sobj);
-}
-
-
-static void unlock_fs (
- FATFS* fs, /* Filesystem object */
- FRESULT res /* Result code to be returned */
-)
-{
- if (fs && res != FR_NOT_ENABLED && res != FR_INVALID_DRIVE && res != FR_TIMEOUT) {
- ff_rel_grant(fs->sobj);
- }
-}
-
-#endif
-
-
-
-#if FF_FS_LOCK != 0
-/*-----------------------------------------------------------------------*/
-/* File lock control functions */
-/*-----------------------------------------------------------------------*/
-
-static FRESULT chk_lock ( /* Check if the file can be accessed */
- DIR* dp, /* Directory object pointing the file to be checked */
- int acc /* Desired access type (0:Read mode open, 1:Write mode open, 2:Delete or rename) */
-)
-{
- UINT i, be;
-
- /* Search open object table for the object */
- be = 0;
- for (i = 0; i < FF_FS_LOCK; i++) {
- if (Files[i].fs) { /* Existing entry */
- if (Files[i].fs == dp->obj.fs && /* Check if the object matches with an open object */
- Files[i].clu == dp->obj.sclust &&
- Files[i].ofs == dp->dptr) break;
- } else { /* Blank entry */
- be = 1;
- }
- }
- if (i == FF_FS_LOCK) { /* The object has not been opened */
- return (!be && acc != 2) ? FR_TOO_MANY_OPEN_FILES : FR_OK; /* Is there a blank entry for new object? */
- }
-
- /* The object was opened. Reject any open against writing file and all write mode open */
- return (acc != 0 || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK;
-}
-
-
-static int enq_lock (void) /* Check if an entry is available for a new object */
-{
- UINT i;
-
- for (i = 0; i < FF_FS_LOCK && Files[i].fs; i++) ;
- return (i == FF_FS_LOCK) ? 0 : 1;
-}
-
-
-static UINT inc_lock ( /* Increment object open counter and returns its index (0:Internal error) */
- DIR* dp, /* Directory object pointing the file to register or increment */
- int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */
-)
-{
- UINT i;
-
-
- for (i = 0; i < FF_FS_LOCK; i++) { /* Find the object */
- if (Files[i].fs == dp->obj.fs &&
- Files[i].clu == dp->obj.sclust &&
- Files[i].ofs == dp->dptr) break;
- }
-
- if (i == FF_FS_LOCK) { /* Not opened. Register it as new. */
- for (i = 0; i < FF_FS_LOCK && Files[i].fs; i++) ;
- if (i == FF_FS_LOCK) return 0; /* No free entry to register (int err) */
- Files[i].fs = dp->obj.fs;
- Files[i].clu = dp->obj.sclust;
- Files[i].ofs = dp->dptr;
- Files[i].ctr = 0;
- }
-
- if (acc >= 1 && Files[i].ctr) return 0; /* Access violation (int err) */
-
- Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1; /* Set semaphore value */
-
- return i + 1; /* Index number origin from 1 */
-}
-
-
-static FRESULT dec_lock ( /* Decrement object open counter */
- UINT i /* Semaphore index (1..) */
-)
-{
- WORD n;
- FRESULT res = FR_DISK_ERR;
-
-
- if (--i < FF_FS_LOCK) { /* Index number origin from 0 */
- n = Files[i].ctr;
- if (n == 0x100) n = 0; /* If write mode open, delete the entry */
- if (n > 0) n--; /* Decrement read mode open count */
- Files[i].ctr = n;
- if (n == 0) Files[i].fs = 0; /* Delete the entry if open count gets zero */
- res = FR_OK;
- } else {
- res = FR_INT_ERR; /* Invalid index number */
- }
- return res;
-}
-
-
-static void clear_lock ( /* Clear lock entries of the volume */
- FATFS *fs
-)
-{
- UINT i;
-
- for (i = 0; i < FF_FS_LOCK; i++) {
- if (Files[i].fs == fs) Files[i].fs = 0;
- }
-}
-
-#endif /* FF_FS_LOCK != 0 */
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Move/Flush disk access window in the filesystem object */
-/*-----------------------------------------------------------------------*/
-#if !FF_FS_READONLY
-static FRESULT sync_window ( /* Returns FR_OK or FR_DISK_ERR */
- FATFS* fs /* Filesystem object */
-)
-{
- FRESULT res = FR_DISK_ERR;
-
- if (fs->wflag) { /* Is the disk access window dirty */
- if (disk_write(fs->pdrv, fs->win, fs->winsect, 1) == RES_OK) { /* Write back the window */
- fs->wflag = 0; /* Clear window dirty flag */
- if (fs->winsect - fs->fatbase < fs->fsize) { /* Is it in the 1st FAT? */
- if (fs->n_fats == 2) disk_write(fs->pdrv, fs->win, fs->winsect + fs->fsize, 1); /* Reflect it to 2nd FAT if needed */
- }
- res = FR_OK;
- }
- } else {
- res = FR_OK;
- }
-
- return res;
-}
-#endif
-
-
-static FRESULT move_window ( /* Returns FR_OK or FR_DISK_ERR */
- FATFS* fs, /* Filesystem object */
- DWORD sector /* Sector number to make appearance in the fs->win[] */
-)
-{
- FRESULT res = FR_DISK_ERR;
-
- if (sector != fs->winsect) { /* Window offset changed? */
-#if !FF_FS_READONLY
- res = sync_window(fs); /* Write-back changes */
- if (res == FR_OK) { /* Fill sector window with new data */
-#endif
- if (disk_read(fs->pdrv, fs->win, sector, 1) != RES_OK) {
- sector = 0xFFFFFFFF; /* Invalidate window if read data is not valid */
- res = FR_DISK_ERR;
- } else {
- res = FR_OK;
- }
- fs->winsect = sector;
-#if !FF_FS_READONLY
- }
-#endif
- } else {
- res = FR_OK;
- }
- return res;
-}
-
-
-
-
-#if !FF_FS_READONLY
-/*-----------------------------------------------------------------------*/
-/* Synchronize filesystem and data on the storage */
-/*-----------------------------------------------------------------------*/
-
-static FRESULT sync_fs ( /* Returns FR_OK or FR_DISK_ERR */
- FATFS* fs /* Filesystem object */
-)
-{
- FRESULT res = FR_DISK_ERR;
-
-
- res = sync_window(fs);
- if (res == FR_OK) {
- if (fs->fs_type == FS_FAT32 && fs->fsi_flag == 1) { /* FAT32: Update FSInfo sector if needed */
- /* Create FSInfo structure */
- mem_set(fs->win, 0, SS(fs));
- st_word(fs->win + BS_55AA, 0xAA55);
- st_dword(fs->win + FSI_LeadSig, 0x41615252);
- st_dword(fs->win + FSI_StrucSig, 0x61417272);
- st_dword(fs->win + FSI_Free_Count, fs->free_clst);
- st_dword(fs->win + FSI_Nxt_Free, fs->last_clst);
- /* Write it into the FSInfo sector */
- fs->winsect = fs->volbase + 1;
- disk_write(fs->pdrv, fs->win, fs->winsect, 1);
- fs->fsi_flag = 0;
- }
- /* Make sure that no pending write process in the lower layer */
- if (disk_ioctl(fs->pdrv, CTRL_SYNC, 0) != RES_OK) res = FR_DISK_ERR;
- }
-
- return res;
-}
-
-#endif
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Get physical sector number from cluster number */
-/*-----------------------------------------------------------------------*/
-
-static DWORD clst2sect ( /* !=0:Sector number, 0:Failed (invalid cluster#) */
- FATFS* fs, /* Filesystem object */
- DWORD clst /* Cluster# to be converted */
-)
-{
- clst -= 2; /* Cluster number is origin from 2 */
- if (clst >= fs->n_fatent - 2) return 0; /* Is it invalid cluster number? */
- return fs->database + fs->csize * clst; /* Start sector number of the cluster */
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* FAT access - Read value of a FAT entry */
-/*-----------------------------------------------------------------------*/
-
-static DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, 2..0x7FFFFFFF:Cluster status */
- FFOBJID* obj, /* Corresponding object */
- DWORD clst /* Cluster number to get the value */
-)
-{
- UINT wc, bc;
- DWORD val;
- FATFS *fs = obj->fs;
-
-
- if (clst < 2 || clst >= fs->n_fatent) { /* Check if in valid range */
- val = 1; /* Internal error */
-
- } else {
- val = 0xFFFFFFFF; /* Default value falls on disk error */
-
- switch (fs->fs_type) {
- case FS_FAT12 :
- bc = (UINT)clst; bc += bc / 2;
- if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
- wc = fs->win[bc++ % SS(fs)]; /* Get 1st byte of the entry */
- if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
- wc |= fs->win[bc % SS(fs)] << 8; /* Merge 2nd byte of the entry */
- val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF); /* Adjust bit position */
- break;
-
- case FS_FAT16 :
- if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))) != FR_OK) break;
- val = ld_word(fs->win + clst * 2 % SS(fs)); /* Simple WORD array */
- break;
-
- case FS_FAT32 :
- if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break;
- val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF; /* Simple DWORD array but mask out upper 4 bits */
- break;
-#if FF_FS_EXFAT
- case FS_EXFAT :
- if ((obj->objsize != 0 && obj->sclust != 0) || obj->stat == 0) { /* Object except root dir must have valid data length */
- DWORD cofs = clst - obj->sclust; /* Offset from start cluster */
- DWORD clen = (DWORD)((obj->objsize - 1) / SS(fs)) / fs->csize; /* Number of clusters - 1 */
-
- if (obj->stat == 2 && cofs <= clen) { /* Is it a contiguous chain? */
- val = (cofs == clen) ? 0x7FFFFFFF : clst + 1; /* No data on the FAT, generate the value */
- break;
- }
- if (obj->stat == 3 && cofs < obj->n_cont) { /* Is it in the 1st fragment? */
- val = clst + 1; /* Generate the value */
- break;
- }
- if (obj->stat != 2) { /* Get value from FAT if FAT chain is valid */
- if (obj->n_frag != 0) { /* Is it on the growing edge? */
- val = 0x7FFFFFFF; /* Generate EOC */
- } else {
- if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break;
- val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x7FFFFFFF;
- }
- break;
- }
- }
- val = 1; /* Internal error */
- break;
-#endif
- default:
- val = 1; /* Internal error */
- }
- }
-
- return val;
-}
-
-
-
-
-#if !FF_FS_READONLY
-/*-----------------------------------------------------------------------*/
-/* FAT access - Change value of a FAT entry */
-/*-----------------------------------------------------------------------*/
-
-static FRESULT put_fat ( /* FR_OK(0):succeeded, !=0:error */
- FATFS* fs, /* Corresponding filesystem object */
- DWORD clst, /* FAT index number (cluster number) to be changed */
- DWORD val /* New value to be set to the entry */
-)
-{
- UINT bc;
- BYTE *p;
- FRESULT res = FR_INT_ERR;
-
-
- if (clst >= 2 && clst < fs->n_fatent) { /* Check if in valid range */
- switch (fs->fs_type) {
- case FS_FAT12 :
- bc = (UINT)clst; bc += bc / 2; /* bc: byte offset of the entry */
- res = move_window(fs, fs->fatbase + (bc / SS(fs)));
- if (res != FR_OK) break;
- p = fs->win + bc++ % SS(fs);
- *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; /* Put 1st byte */
- fs->wflag = 1;
- res = move_window(fs, fs->fatbase + (bc / SS(fs)));
- if (res != FR_OK) break;
- p = fs->win + bc % SS(fs);
- *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); /* Put 2nd byte */
- fs->wflag = 1;
- break;
-
- case FS_FAT16 :
- res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)));
- if (res != FR_OK) break;
- st_word(fs->win + clst * 2 % SS(fs), (WORD)val); /* Simple WORD array */
- fs->wflag = 1;
- break;
-
- case FS_FAT32 :
-#if FF_FS_EXFAT
- case FS_EXFAT :
-#endif
- res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)));
- if (res != FR_OK) break;
- if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) {
- val = (val & 0x0FFFFFFF) | (ld_dword(fs->win + clst * 4 % SS(fs)) & 0xF0000000);
- }
- st_dword(fs->win + clst * 4 % SS(fs), val);
- fs->wflag = 1;
- break;
- }
- }
- return res;
-}
-
-#endif /* !FF_FS_READONLY */
-
-
-
-
-#if FF_FS_EXFAT && !FF_FS_READONLY
-/*-----------------------------------------------------------------------*/
-/* exFAT: Accessing FAT and Allocation Bitmap */
-/*-----------------------------------------------------------------------*/
-
-/*--------------------------------------*/
-/* Find a contiguous free cluster block */
-/*--------------------------------------*/
-
-static DWORD find_bitmap ( /* 0:Not found, 2..:Cluster block found, 0xFFFFFFFF:Disk error */
- FATFS* fs, /* Filesystem object */
- DWORD clst, /* Cluster number to scan from */
- DWORD ncl /* Number of contiguous clusters to find (1..) */
-)
-{
- BYTE bm, bv;
- UINT i;
- DWORD val, scl, ctr;
-
-
- clst -= 2; /* The first bit in the bitmap corresponds to cluster #2 */
- if (clst >= fs->n_fatent - 2) clst = 0;
- scl = val = clst; ctr = 0;
- for (;;) {
- if (move_window(fs, fs->database + val / 8 / SS(fs)) != FR_OK) return 0xFFFFFFFF; /* (assuming bitmap is located top of the cluster heap) */
- i = val / 8 % SS(fs); bm = 1 << (val % 8);
- do {
- do {
- bv = fs->win[i] & bm; bm <<= 1; /* Get bit value */
- if (++val >= fs->n_fatent - 2) { /* Next cluster (with wrap-around) */
- val = 0; bm = 0; i = SS(fs);
- }
- if (bv == 0) { /* Is it a free cluster? */
- if (++ctr == ncl) return scl + 2; /* Check if run length is sufficient for required */
- } else {
- scl = val; ctr = 0; /* Encountered a cluster in-use, restart to scan */
- }
- if (val == clst) return 0; /* All cluster scanned? */
- } while (bm != 0);
- bm = 1;
- } while (++i < SS(fs));
- }
-}
-
-
-/*----------------------------------------*/
-/* Set/Clear a block of allocation bitmap */
-/*----------------------------------------*/
-
-static FRESULT change_bitmap (
- FATFS* fs, /* Filesystem object */
- DWORD clst, /* Cluster number to change from */
- DWORD ncl, /* Number of clusters to be changed */
- int bv /* bit value to be set (0 or 1) */
-)
-{
- BYTE bm;
- UINT i;
- DWORD sect;
-
-
- clst -= 2; /* The first bit corresponds to cluster #2 */
- sect = fs->database + clst / 8 / SS(fs); /* Sector address (assuming bitmap is located top of the cluster heap) */
- i = clst / 8 % SS(fs); /* Byte offset in the sector */
- bm = 1 << (clst % 8); /* Bit mask in the byte */
- for (;;) {
- if (move_window(fs, sect++) != FR_OK) return FR_DISK_ERR;
- do {
- do {
- if (bv == (int)((fs->win[i] & bm) != 0)) return FR_INT_ERR; /* Is the bit expected value? */
- fs->win[i] ^= bm; /* Flip the bit */
- fs->wflag = 1;
- if (--ncl == 0) return FR_OK; /* All bits processed? */
- } while (bm <<= 1); /* Next bit */
- bm = 1;
- } while (++i < SS(fs)); /* Next byte */
- i = 0;
- }
-}
-
-
-/*---------------------------------------------*/
-/* Fill the first fragment of the FAT chain */
-/*---------------------------------------------*/
-
-static FRESULT fill_first_frag (
- FFOBJID* obj /* Pointer to the corresponding object */
-)
-{
- FRESULT res = FR_DISK_ERR;
- DWORD cl, n;
-
-
- if (obj->stat == 3) { /* Has the object been changed 'fragmented' in this session? */
- for (cl = obj->sclust, n = obj->n_cont; n; cl++, n--) { /* Create cluster chain on the FAT */
- res = put_fat(obj->fs, cl, cl + 1);
- if (res != FR_OK) return res;
- }
- obj->stat = 0; /* Change status 'FAT chain is valid' */
- }
- return FR_OK;
-}
-
-
-/*---------------------------------------------*/
-/* Fill the last fragment of the FAT chain */
-/*---------------------------------------------*/
-
-static FRESULT fill_last_frag (
- FFOBJID* obj, /* Pointer to the corresponding object */
- DWORD lcl, /* Last cluster of the fragment */
- DWORD term /* Value to set the last FAT entry */
-)
-{
- FRESULT res = FR_DISK_ERR;
-
-
- while (obj->n_frag > 0) { /* Create the chain of last fragment */
- res = put_fat(obj->fs, lcl - obj->n_frag + 1, (obj->n_frag > 1) ? lcl - obj->n_frag + 2 : term);
- if (res != FR_OK) return res;
- obj->n_frag--;
- }
- return FR_OK;
-}
-
-#endif /* FF_FS_EXFAT && !FF_FS_READONLY */
-
-
-
-#if !FF_FS_READONLY
-/*-----------------------------------------------------------------------*/
-/* FAT handling - Remove a cluster chain */
-/*-----------------------------------------------------------------------*/
-
-static FRESULT remove_chain ( /* FR_OK(0):succeeded, !=0:error */
- FFOBJID* obj, /* Corresponding object */
- DWORD clst, /* Cluster to remove a chain from */
- DWORD pclst /* Previous cluster of clst (0:entire chain) */
-)
-{
- FRESULT res = FR_DISK_ERR;
- DWORD nxt;
- FATFS *fs = obj->fs;
-#if FF_FS_EXFAT || FF_USE_TRIM
- DWORD scl = clst, ecl = clst;
-#endif
-#if FF_USE_TRIM
- DWORD rt[2];
-#endif
-
- if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Check if in valid range */
-
- /* Mark the previous cluster 'EOC' on the FAT if it exists */
- if (pclst != 0 && (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT || obj->stat != 2)) {
- res = put_fat(fs, pclst, 0xFFFFFFFF);
- if (res != FR_OK) return res;
- }
-
- /* Remove the chain */
- do {
- nxt = get_fat(obj, clst); /* Get cluster status */
- if (nxt == 0) break; /* Empty cluster? */
- if (nxt == 1) return FR_INT_ERR; /* Internal error? */
- if (nxt == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error? */
- if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) {
- res = put_fat(fs, clst, 0); /* Mark the cluster 'free' on the FAT */
- if (res != FR_OK) return res;
- }
- if (fs->free_clst < fs->n_fatent - 2) { /* Update FSINFO */
- fs->free_clst++;
- fs->fsi_flag |= 1;
- }
-#if FF_FS_EXFAT || FF_USE_TRIM
- if (ecl + 1 == nxt) { /* Is next cluster contiguous? */
- ecl = nxt;
- } else { /* End of contiguous cluster block */
-#if FF_FS_EXFAT
- if (fs->fs_type == FS_EXFAT) {
- res = change_bitmap(fs, scl, ecl - scl + 1, 0); /* Mark the cluster block 'free' on the bitmap */
- if (res != FR_OK) return res;
- }
-#endif
-#if FF_USE_TRIM
- rt[0] = clst2sect(fs, scl); /* Start of data area freed */
- rt[1] = clst2sect(fs, ecl) + fs->csize - 1; /* End of data area freed */
- disk_ioctl(fs->pdrv, CTRL_TRIM, rt); /* Inform device the data in the block is no longer needed */
-#endif
- scl = ecl = nxt;
- }
-#endif
- clst = nxt; /* Next cluster */
- } while (clst < fs->n_fatent); /* Repeat while not the last link */
-
-#if FF_FS_EXFAT
- /* Some post processes for chain status */
- if (fs->fs_type == FS_EXFAT) {
- if (pclst == 0) { /* Has the entire chain been removed? */
- obj->stat = 0; /* Change the chain status 'initial' */
- } else {
- if (obj->stat == 0) { /* Is it a fragmented chain from the beginning of this session? */
- clst = obj->sclust; /* Follow the chain to check if it gets contiguous */
- while (clst != pclst) {
- nxt = get_fat(obj, clst);
- if (nxt < 2) return FR_INT_ERR;
- if (nxt == 0xFFFFFFFF) return FR_DISK_ERR;
- if (nxt != clst + 1) break; /* Not contiguous? */
- clst++;
- }
- if (clst == pclst) { /* Has the chain got contiguous again? */
- obj->stat = 2; /* Change the chain status 'contiguous' */
- }
- } else {
- if (obj->stat == 3 && pclst >= obj->sclust && pclst <= obj->sclust + obj->n_cont) { /* Was the chain fragmented in this session and got contiguous again? */
- obj->stat = 2; /* Change the chain status 'contiguous' */
- }
- }
- }
- }
-#endif
- return FR_OK;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* FAT handling - Stretch a chain or Create a new chain */
-/*-----------------------------------------------------------------------*/
-
-static DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */
- FFOBJID* obj, /* Corresponding object */
- DWORD clst /* Cluster# to stretch, 0:Create a new chain */
-)
-{
- DWORD cs, ncl, scl;
- FRESULT res = FR_DISK_ERR;
- FATFS *fs = obj->fs;
-
-
- if (clst == 0) { /* Create a new chain */
- scl = fs->last_clst; /* Suggested cluster to start to find */
- if (scl == 0 || scl >= fs->n_fatent) scl = 1;
- }
- else { /* Stretch a chain */
- cs = get_fat(obj, clst); /* Check the cluster status */
- if (cs < 2) return 1; /* Test for insanity */
- if (cs == 0xFFFFFFFF) return cs; /* Test for disk error */
- if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */
- scl = clst; /* Cluster to start to find */
- }
- if (fs->free_clst == 0) return 0; /* No free cluster */
-
-#if FF_FS_EXFAT
- if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */
- ncl = find_bitmap(fs, scl, 1); /* Find a free cluster */
- if (ncl == 0 || ncl == 0xFFFFFFFF) return ncl; /* No free cluster or hard error? */
- res = change_bitmap(fs, ncl, 1, 1); /* Mark the cluster 'in use' */
- if (res == FR_INT_ERR) return 1;
- if (res == FR_DISK_ERR) return 0xFFFFFFFF;
- if (clst == 0) { /* Is it a new chain? */
- obj->stat = 2; /* Set status 'contiguous' */
- } else { /* It is a stretched chain */
- if (obj->stat == 2 && ncl != scl + 1) { /* Is the chain got fragmented? */
- obj->n_cont = scl - obj->sclust; /* Set size of the contiguous part */
- obj->stat = 3; /* Change status 'just fragmented' */
- }
- }
- if (obj->stat != 2) { /* Is the file non-contiguous? */
- if (ncl == clst + 1) { /* Is the cluster next to previous one? */
- obj->n_frag = obj->n_frag ? obj->n_frag + 1 : 2; /* Increment size of last framgent */
- } else { /* New fragment */
- if (obj->n_frag == 0) obj->n_frag = 1;
- res = fill_last_frag(obj, clst, ncl); /* Fill last fragment on the FAT and link it to new one */
- if (res == FR_OK) obj->n_frag = 1;
- }
- }
- } else
-#endif
- { /* On the FAT/FAT32 volume */
- ncl = 0;
- if (scl == clst) { /* Stretching an existing chain? */
- ncl = scl + 1; /* Test if next cluster is free */
- if (ncl >= fs->n_fatent) ncl = 2;
- cs = get_fat(obj, ncl); /* Get next cluster status */
- if (cs == 1 || cs == 0xFFFFFFFF) return cs; /* Test for error */
- if (cs != 0) { /* Not free? */
- cs = fs->last_clst; /* Start at suggested cluster if it is valid */
- if (cs >= 2 && cs < fs->n_fatent) scl = cs;
- ncl = 0;
- }
- }
- if (ncl == 0) { /* The new cluster cannot be contiguous and find another fragment */
- ncl = scl; /* Start cluster */
- for (;;) {
- ncl++; /* Next cluster */
- if (ncl >= fs->n_fatent) { /* Check wrap-around */
- ncl = 2;
- if (ncl > scl) return 0; /* No free cluster found? */
- }
- cs = get_fat(obj, ncl); /* Get the cluster status */
- if (cs == 0) break; /* Found a free cluster? */
- if (cs == 1 || cs == 0xFFFFFFFF) return cs; /* Test for error */
- if (ncl == scl) return 0; /* No free cluster found? */
- }
- }
- res = put_fat(fs, ncl, 0xFFFFFFFF); /* Mark the new cluster 'EOC' */
- if (res == FR_OK && clst != 0) {
- res = put_fat(fs, clst, ncl); /* Link it from the previous one if needed */
- }
- }
-
- if (res == FR_OK) { /* Update FSINFO if function succeeded. */
- fs->last_clst = ncl;
- if (fs->free_clst <= fs->n_fatent - 2) fs->free_clst--;
- fs->fsi_flag |= 1;
- } else {
- ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1; /* Failed. Generate error status */
- }
-
- return ncl; /* Return new cluster number or error status */
-}
-
-#endif /* !FF_FS_READONLY */
-
-
-
-
-#if FF_USE_FASTSEEK
-/*-----------------------------------------------------------------------*/
-/* FAT handling - Convert offset into cluster with link map table */
-/*-----------------------------------------------------------------------*/
-
-static DWORD clmt_clust ( /* <2:Error, >=2:Cluster number */
- FIL* fp, /* Pointer to the file object */
- FSIZE_t ofs /* File offset to be converted to cluster# */
-)
-{
- DWORD cl, ncl, *tbl;
- FATFS *fs = fp->obj.fs;
-
-
- tbl = fp->cltbl + 1; /* Top of CLMT */
- cl = (DWORD)(ofs / SS(fs) / fs->csize); /* Cluster order from top of the file */
- for (;;) {
- ncl = *tbl++; /* Number of cluters in the fragment */
- if (ncl == 0) return 0; /* End of table? (error) */
- if (cl < ncl) break; /* In this fragment? */
- cl -= ncl; tbl++; /* Next fragment */
- }
- return cl + *tbl; /* Return the cluster number */
-}
-
-#endif /* FF_USE_FASTSEEK */
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Directory handling - Fill a cluster with zeros */
-/*-----------------------------------------------------------------------*/
-
-#if !FF_FS_READONLY
-static FRESULT dir_clear ( /* Returns FR_OK or FR_DISK_ERR */
- FATFS *fs, /* Filesystem object */
- DWORD clst /* Directory table to clear */
-)
-{
- DWORD sect;
- UINT n, szb;
- BYTE *ibuf;
-
-
- if (sync_window(fs) != FR_OK) return FR_DISK_ERR; /* Flush disk access window */
- sect = clst2sect(fs, clst); /* Top of the cluster */
- fs->winsect = sect; /* Set window to top of the cluster */
- mem_set(fs->win, 0, SS(fs)); /* Clear window buffer */
-#if FF_USE_LFN == 3 /* Quick table clear by using multi-secter write */
- /* Allocate a temporary buffer */
- for (szb = ((DWORD)fs->csize * SS(fs) >= MAX_MALLOC) ? MAX_MALLOC : fs->csize * SS(fs), ibuf = 0; szb > SS(fs) && (ibuf = ff_memalloc(szb)) == 0; szb /= 2) ;
- if (szb > SS(fs)) { /* Buffer allocated? */
- mem_set(ibuf, 0, szb);
- szb /= SS(fs); /* Bytes -> Sectors */
- for (n = 0; n < fs->csize && disk_write(fs->pdrv, ibuf, sect + n, szb) == RES_OK; n += szb) ; /* Fill the cluster with 0 */
- ff_memfree(ibuf);
- } else
-#endif
- {
- ibuf = fs->win; szb = 1; /* Use window buffer (many single-sector writes may take a time) */
- for (n = 0; n < fs->csize && disk_write(fs->pdrv, ibuf, sect + n, szb) == RES_OK; n += szb) ; /* Fill the cluster with 0 */
- }
- return (n == fs->csize) ? FR_OK : FR_DISK_ERR;
-}
-#endif /* !FF_FS_READONLY */
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Directory handling - Set directory index */
-/*-----------------------------------------------------------------------*/
-
-static FRESULT dir_sdi ( /* FR_OK(0):succeeded, !=0:error */
- DIR* dp, /* Pointer to directory object */
- DWORD ofs /* Offset of directory table */
-)
-{
- DWORD csz, clst;
- FATFS *fs = dp->obj.fs;
-
-
- if (ofs >= (DWORD)((FF_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR) || ofs % SZDIRE) { /* Check range of offset and alignment */
- return FR_INT_ERR;
- }
- dp->dptr = ofs; /* Set current offset */
- clst = dp->obj.sclust; /* Table start cluster (0:root) */
- if (clst == 0 && fs->fs_type >= FS_FAT32) { /* Replace cluster# 0 with root cluster# */
- clst = fs->dirbase;
- if (FF_FS_EXFAT) dp->obj.stat = 0; /* exFAT: Root dir has an FAT chain */
- }
-
- if (clst == 0) { /* Static table (root-directory on the FAT volume) */
- if (ofs / SZDIRE >= fs->n_rootdir) return FR_INT_ERR; /* Is index out of range? */
- dp->sect = fs->dirbase;
-
- } else { /* Dynamic table (sub-directory or root-directory on the FAT32/exFAT volume) */
- csz = (DWORD)fs->csize * SS(fs); /* Bytes per cluster */
- while (ofs >= csz) { /* Follow cluster chain */
- clst = get_fat(&dp->obj, clst); /* Get next cluster */
- if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */
- if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Reached to end of table or internal error */
- ofs -= csz;
- }
- dp->sect = clst2sect(fs, clst);
- }
- dp->clust = clst; /* Current cluster# */
- if (dp->sect == 0) return FR_INT_ERR;
- dp->sect += ofs / SS(fs); /* Sector# of the directory entry */
- dp->dir = fs->win + (ofs % SS(fs)); /* Pointer to the entry in the win[] */
-
- return FR_OK;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Directory handling - Move directory table index next */
-/*-----------------------------------------------------------------------*/
-
-static FRESULT dir_next ( /* FR_OK(0):succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */
- DIR* dp, /* Pointer to the directory object */
- int stretch /* 0: Do not stretch table, 1: Stretch table if needed */
-)
-{
- DWORD ofs, clst;
- FATFS *fs = dp->obj.fs;
-
-
- ofs = dp->dptr + SZDIRE; /* Next entry */
- if (ofs >= (DWORD)((FF_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR)) dp->sect = 0; /* Disable it if the offset reached the max value */
- if (dp->sect == 0) return FR_NO_FILE; /* Report EOT if it has been disabled */
-
- if (ofs % SS(fs) == 0) { /* Sector changed? */
- dp->sect++; /* Next sector */
-
- if (dp->clust == 0) { /* Static table */
- if (ofs / SZDIRE >= fs->n_rootdir) { /* Report EOT if it reached end of static table */
- dp->sect = 0; return FR_NO_FILE;
- }
- }
- else { /* Dynamic table */
- if ((ofs / SS(fs) & (fs->csize - 1)) == 0) { /* Cluster changed? */
- clst = get_fat(&dp->obj, dp->clust); /* Get next cluster */
- if (clst <= 1) return FR_INT_ERR; /* Internal error */
- if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */
- if (clst >= fs->n_fatent) { /* It reached end of dynamic table */
-#if !FF_FS_READONLY
- if (!stretch) { /* If no stretch, report EOT */
- dp->sect = 0; return FR_NO_FILE;
- }
- clst = create_chain(&dp->obj, dp->clust); /* Allocate a cluster */
- if (clst == 0) return FR_DENIED; /* No free cluster */
- if (clst == 1) return FR_INT_ERR; /* Internal error */
- if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */
- if (dir_clear(fs, clst) != FR_OK) return FR_DISK_ERR; /* Clean up the stretched table */
- if (FF_FS_EXFAT) dp->obj.stat |= 4; /* exFAT: The directory has been stretched */
-#else
- if (!stretch) dp->sect = 0; /* (this line is to suppress compiler warning) */
- dp->sect = 0; return FR_NO_FILE; /* Report EOT */
-#endif
- }
- dp->clust = clst; /* Initialize data for new cluster */
- dp->sect = clst2sect(fs, clst);
- }
- }
- }
- dp->dptr = ofs; /* Current entry */
- dp->dir = fs->win + ofs % SS(fs); /* Pointer to the entry in the win[] */
-
- return FR_OK;
-}
-
-
-
-
-#if !FF_FS_READONLY
-/*-----------------------------------------------------------------------*/
-/* Directory handling - Reserve a block of directory entries */
-/*-----------------------------------------------------------------------*/
-
-static FRESULT dir_alloc ( /* FR_OK(0):succeeded, !=0:error */
- DIR* dp, /* Pointer to the directory object */
- UINT nent /* Number of contiguous entries to allocate */
-)
-{
- FRESULT res = FR_DISK_ERR;
- UINT n;
- FATFS *fs = dp->obj.fs;
-
-
- res = dir_sdi(dp, 0);
- if (res == FR_OK) {
- n = 0;
- do {
- res = move_window(fs, dp->sect);
- if (res != FR_OK) break;
-#if FF_FS_EXFAT
- if ((fs->fs_type == FS_EXFAT) ? (int)((dp->dir[XDIR_Type] & 0x80) == 0) : (int)(dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0)) {
-#else
- if (dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0) {
-#endif
- if (++n == nent) break; /* A block of contiguous free entries is found */
- } else {
- n = 0; /* Not a blank entry. Restart to search */
- }
- res = dir_next(dp, 1);
- } while (res == FR_OK); /* Next entry with table stretch enabled */
- }
-
- if (res == FR_NO_FILE) res = FR_DENIED; /* No directory entry to allocate */
- return res;
-}
-
-#endif /* !FF_FS_READONLY */
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* FAT: Directory handling - Load/Store start cluster number */
-/*-----------------------------------------------------------------------*/
-
-static DWORD ld_clust ( /* Returns the top cluster value of the SFN entry */
- FATFS* fs, /* Pointer to the fs object */
- const BYTE* dir /* Pointer to the key entry */
-)
-{
- DWORD cl;
-
- cl = ld_word(dir + DIR_FstClusLO);
- if (fs->fs_type == FS_FAT32) {
- cl |= (DWORD)ld_word(dir + DIR_FstClusHI) << 16;
- }
-
- return cl;
-}
-
-
-#if !FF_FS_READONLY
-static void st_clust (
- FATFS* fs, /* Pointer to the fs object */
- BYTE* dir, /* Pointer to the key entry */
- DWORD cl /* Value to be set */
-)
-{
- st_word(dir + DIR_FstClusLO, (WORD)cl);
- if (fs->fs_type == FS_FAT32) {
- st_word(dir + DIR_FstClusHI, (WORD)(cl >> 16));
- }
-}
-#endif
-
-
-
-#if FF_USE_LFN
-/*--------------------------------------------------------*/
-/* FAT-LFN: Compare a part of file name with an LFN entry */
-/*--------------------------------------------------------*/
-
-static int cmp_lfn ( /* 1:matched, 0:not matched */
- const WCHAR* lfnbuf, /* Pointer to the LFN working buffer to be compared */
- BYTE* dir /* Pointer to the directory entry containing the part of LFN */
-)
-{
- UINT i, s;
- WCHAR wc, uc;
-
-
- if (ld_word(dir + LDIR_FstClusLO) != 0) return 0; /* Check LDIR_FstClusLO */
-
- i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */
-
- for (wc = 1, s = 0; s < 13; s++) { /* Process all characters in the entry */
- uc = ld_word(dir + LfnOfs[s]); /* Pick an LFN character */
- if (wc != 0) {
- if (i >= FF_MAX_LFN || ff_wtoupper(uc) != ff_wtoupper(lfnbuf[i++])) { /* Compare it */
- return 0; /* Not matched */
- }
- wc = uc;
- } else {
- if (uc != 0xFFFF) return 0; /* Check filler */
- }
- }
-
- if ((dir[LDIR_Ord] & LLEF) && wc && lfnbuf[i]) return 0; /* Last segment matched but different length */
-
- return 1; /* The part of LFN matched */
-}
-
-
-#if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 || FF_USE_LABEL || FF_FS_EXFAT
-/*-----------------------------------------------------*/
-/* FAT-LFN: Pick a part of file name from an LFN entry */
-/*-----------------------------------------------------*/
-
-static int pick_lfn ( /* 1:succeeded, 0:buffer overflow or invalid LFN entry */
- WCHAR* lfnbuf, /* Pointer to the LFN working buffer */
- BYTE* dir /* Pointer to the LFN entry */
-)
-{
- UINT i, s;
- WCHAR wc, uc;
-
-
- if (ld_word(dir + LDIR_FstClusLO) != 0) return 0; /* Check LDIR_FstClusLO is 0 */
-
- i = ((dir[LDIR_Ord] & ~LLEF) - 1) * 13; /* Offset in the LFN buffer */
-
- for (wc = 1, s = 0; s < 13; s++) { /* Process all characters in the entry */
- uc = ld_word(dir + LfnOfs[s]); /* Pick an LFN character */
- if (wc != 0) {
- if (i >= FF_MAX_LFN) return 0; /* Buffer overflow? */
- lfnbuf[i++] = wc = uc; /* Store it */
- } else {
- if (uc != 0xFFFF) return 0; /* Check filler */
- }
- }
-
- if (dir[LDIR_Ord] & LLEF) { /* Put terminator if it is the last LFN part */
- if (i >= FF_MAX_LFN) return 0; /* Buffer overflow? */
- lfnbuf[i] = 0;
- }
-
- return 1; /* The part of LFN is valid */
-}
-#endif
-
-
-#if !FF_FS_READONLY
-/*-----------------------------------------*/
-/* FAT-LFN: Create an entry of LFN entries */
-/*-----------------------------------------*/
-
-static void put_lfn (
- const WCHAR* lfn, /* Pointer to the LFN */
- BYTE* dir, /* Pointer to the LFN entry to be created */
- BYTE ord, /* LFN order (1-20) */
- BYTE sum /* Checksum of the corresponding SFN */
-)
-{
- UINT i, s;
- WCHAR wc;
-
-
- dir[LDIR_Chksum] = sum; /* Set checksum */
- dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */
- dir[LDIR_Type] = 0;
- st_word(dir + LDIR_FstClusLO, 0);
-
- i = (ord - 1) * 13; /* Get offset in the LFN working buffer */
- s = wc = 0;
- do {
- if (wc != 0xFFFF) wc = lfn[i++]; /* Get an effective character */
- st_word(dir + LfnOfs[s], wc); /* Put it */
- if (wc == 0) wc = 0xFFFF; /* Padding characters for left locations */
- } while (++s < 13);
- if (wc == 0xFFFF || !lfn[i]) ord |= LLEF; /* Last LFN part is the start of LFN sequence */
- dir[LDIR_Ord] = ord; /* Set the LFN order */
-}
-
-#endif /* !FF_FS_READONLY */
-#endif /* FF_USE_LFN */
-
-
-
-#if FF_USE_LFN && !FF_FS_READONLY
-/*-----------------------------------------------------------------------*/
-/* FAT-LFN: Create a Numbered SFN */
-/*-----------------------------------------------------------------------*/
-
-static void gen_numname (
- BYTE* dst, /* Pointer to the buffer to store numbered SFN */
- const BYTE* src, /* Pointer to SFN */
- const WCHAR* lfn, /* Pointer to LFN */
- UINT seq /* Sequence number */
-)
-{
- BYTE ns[8], c;
- UINT i, j;
- WCHAR wc;
- DWORD sr;
-
-
- mem_cpy(dst, src, 11);
-
- if (seq > 5) { /* In case of many collisions, generate a hash number instead of sequential number */
- sr = seq;
- while (*lfn) { /* Create a CRC as hash value */
- wc = *lfn++;
- for (i = 0; i < 16; i++) {
- sr = (sr << 1) + (wc & 1);
- wc >>= 1;
- if (sr & 0x10000) sr ^= 0x11021;
- }
- }
- seq = (UINT)sr;
- }
-
- /* itoa (hexdecimal) */
- i = 7;
- do {
- c = (BYTE)((seq % 16) + '0');
- if (c > '9') c += 7;
- ns[i--] = c;
- seq /= 16;
- } while (seq);
- ns[i] = '~';
-
- /* Append the number to the SFN body */
- for (j = 0; j < i && dst[j] != ' '; j++) {
- if (dbc_1st(dst[j])) {
- if (j == i - 1) break;
- j++;
- }
- }
- do {
- dst[j++] = (i < 8) ? ns[i++] : ' ';
- } while (j < 8);
-}
-#endif /* FF_USE_LFN && !FF_FS_READONLY */
-
-
-
-#if FF_USE_LFN
-/*-----------------------------------------------------------------------*/
-/* FAT-LFN: Calculate checksum of an SFN entry */
-/*-----------------------------------------------------------------------*/
-
-static BYTE sum_sfn (
- const BYTE* dir /* Pointer to the SFN entry */
-)
-{
- BYTE sum = 0;
- UINT n = 11;
-
- do {
- sum = (sum >> 1) + (sum << 7) + *dir++;
- } while (--n);
- return sum;
-}
-
-#endif /* FF_USE_LFN */
-
-
-
-#if FF_FS_EXFAT
-/*-----------------------------------------------------------------------*/
-/* exFAT: Checksum */
-/*-----------------------------------------------------------------------*/
-
-static WORD xdir_sum ( /* Get checksum of the directoly entry block */
- const BYTE* dir /* Directory entry block to be calculated */
-)
-{
- UINT i, szblk;
- WORD sum;
-
-
- szblk = (dir[XDIR_NumSec] + 1) * SZDIRE; /* Number of bytes of the entry block */
- for (i = sum = 0; i < szblk; i++) {
- if (i == XDIR_SetSum) { /* Skip 2-byte sum field */
- i++;
- } else {
- sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + dir[i];
- }
- }
- return sum;
-}
-
-
-
-static WORD xname_sum ( /* Get check sum (to be used as hash) of the file name */
- const WCHAR* name /* File name to be calculated */
-)
-{
- WCHAR chr;
- WORD sum = 0;
-
-
- while ((chr = *name++) != 0) {
- chr = (WCHAR)ff_wtoupper(chr); /* File name needs to be up-case converted */
- sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr & 0xFF);
- sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr >> 8);
- }
- return sum;
-}
-
-
-#if !FF_FS_READONLY && FF_USE_MKFS
-static DWORD xsum32 ( /* Returns 32-bit checksum */
- BYTE dat, /* Byte to be calculated (byte-by-byte processing) */
- DWORD sum /* Previous sum value */
-)
-{
- sum = ((sum & 1) ? 0x80000000 : 0) + (sum >> 1) + dat;
- return sum;
-}
-#endif
-
-
-#if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2
-/*------------------------------------------------------*/
-/* exFAT: Get object information from a directory block */
-/*------------------------------------------------------*/
-
-static void get_xfileinfo (
- BYTE* dirb, /* Pointer to the directory entry block 85+C0+C1s */
- FILINFO* fno /* Buffer to store the extracted file information */
-)
-{
- WCHAR wc, hs;
- UINT di, si, nc;
-
- /* Get file name from the entry block */
- si = SZDIRE * 2; /* 1st C1 entry */
- nc = 0; hs = 0; di = 0;
- while (nc < dirb[XDIR_NumName]) {
- if (si >= MAXDIRB(FF_MAX_LFN)) { di = 0; break; } /* Truncated directory block? */
- if ((si % SZDIRE) == 0) si += 2; /* Skip entry type field */
- wc = ld_word(dirb + si); si += 2; nc++; /* Get a character */
- if (hs == 0 && IsSurrogate(wc)) { /* Is it a surrogate? */
- hs = wc; continue; /* Get low surrogate */
- }
- wc = put_utf((DWORD)hs << 16 | wc, &fno->fname[di], FF_LFN_BUF - di); /* Store it in API encoding */
- if (wc == 0) { di = 0; break; } /* Buffer overflow or wrong encoding? */
- di += wc;
- hs = 0;
- }
- if (hs != 0) di = 0; /* Broken surrogate pair? */
- if (di == 0) fno->fname[di++] = '?'; /* Inaccessible object name? */
- fno->fname[di] = 0; /* Terminate the name */
- fno->altname[0] = 0; /* exFAT does not support SFN */
-
- fno->fattrib = dirb[XDIR_Attr]; /* Attribute */
- fno->fsize = (fno->fattrib & AM_DIR) ? 0 : ld_qword(dirb + XDIR_FileSize); /* Size */
- fno->ftime = ld_word(dirb + XDIR_ModTime + 0); /* Time */
- fno->fdate = ld_word(dirb + XDIR_ModTime + 2); /* Date */
-}
-
-#endif /* FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 */
-
-
-/*-----------------------------------*/
-/* exFAT: Get a directory entry block */
-/*-----------------------------------*/
-
-static FRESULT load_xdir ( /* FR_INT_ERR: invalid entry block */
- DIR* dp /* Reading directory object pointing top of the entry block to load */
-)
-{
- FRESULT res = FR_DISK_ERR;
- UINT i, sz_ent;
- BYTE* dirb = dp->obj.fs->dirbuf; /* Pointer to the on-memory directory entry block 85+C0+C1s */
-
-
- /* Load 85 entry */
- res = move_window(dp->obj.fs, dp->sect);
- if (res != FR_OK) return res;
- if (dp->dir[XDIR_Type] != 0x85) return FR_INT_ERR; /* Invalid order */
- mem_cpy(dirb + 0 * SZDIRE, dp->dir, SZDIRE);
- sz_ent = (dirb[XDIR_NumSec] + 1) * SZDIRE;
- if (sz_ent < 3 * SZDIRE || sz_ent > 19 * SZDIRE) return FR_INT_ERR;
-
- /* Load C0 entry */
- res = dir_next(dp, 0);
- if (res == FR_NO_FILE) res = FR_INT_ERR; /* It cannot be */
- if (res != FR_OK) return res;
- res = move_window(dp->obj.fs, dp->sect);
- if (res != FR_OK) return res;
- if (dp->dir[XDIR_Type] != 0xC0) return FR_INT_ERR; /* Invalid order */
- mem_cpy(dirb + 1 * SZDIRE, dp->dir, SZDIRE);
- if (MAXDIRB(dirb[XDIR_NumName]) > sz_ent) return FR_INT_ERR;
-
- /* Load C1 entries */
- i = 2 * SZDIRE; /* C1 offset to load */
- do {
- res = dir_next(dp, 0);
- if (res == FR_NO_FILE) res = FR_INT_ERR; /* It cannot be */
- if (res != FR_OK) return res;
- res = move_window(dp->obj.fs, dp->sect);
- if (res != FR_OK) return res;
- if (dp->dir[XDIR_Type] != 0xC1) return FR_INT_ERR; /* Invalid order */
- if (i < MAXDIRB(FF_MAX_LFN)) mem_cpy(dirb + i, dp->dir, SZDIRE);
- } while ((i += SZDIRE) < sz_ent);
-
- /* Sanity check (do it for only accessible object) */
- if (i <= MAXDIRB(FF_MAX_LFN)) {
- if (xdir_sum(dirb) != ld_word(dirb + XDIR_SetSum)) return FR_INT_ERR;
- }
- return FR_OK;
-}
-
-
-/*------------------------------------------------------------------*/
-/* exFAT: Initialize object allocation info with loaded entry block */
-/*------------------------------------------------------------------*/
-
-static void init_alloc_info (
- FATFS* fs, /* Filesystem object */
- FFOBJID* obj /* Object allocation information to be initialized */
-)
-{
- obj->sclust = ld_dword(fs->dirbuf + XDIR_FstClus); /* Start cluster */
- obj->objsize = ld_qword(fs->dirbuf + XDIR_FileSize); /* Size */
- obj->stat = fs->dirbuf[XDIR_GenFlags] & 2; /* Allocation status */
- obj->n_frag = 0; /* No last fragment info */
-}
-
-
-
-#if !FF_FS_READONLY || FF_FS_RPATH != 0
-/*------------------------------------------------*/
-/* exFAT: Load the object's directory entry block */
-/*------------------------------------------------*/
-
-static FRESULT load_obj_xdir (
- DIR* dp, /* Blank directory object to be used to access containing directory */
- const FFOBJID* obj /* Object with its containing directory information */
-)
-{
- FRESULT res = FR_DISK_ERR;
-
- /* Open object containing directory */
- dp->obj.fs = obj->fs;
- dp->obj.sclust = obj->c_scl;
- dp->obj.stat = (BYTE)obj->c_size;
- dp->obj.objsize = obj->c_size & 0xFFFFFF00;
- dp->obj.n_frag = 0;
- dp->blk_ofs = obj->c_ofs;
-
- res = dir_sdi(dp, dp->blk_ofs); /* Goto object's entry block */
- if (res == FR_OK) {
- res = load_xdir(dp); /* Load the object's entry block */
- }
- return res;
-}
-#endif
-
-
-#if !FF_FS_READONLY
-/*----------------------------------------*/
-/* exFAT: Store the directory entry block */
-/*----------------------------------------*/
-
-static FRESULT store_xdir (
- DIR* dp /* Pointer to the directory object */
-)
-{
- FRESULT res = FR_DISK_ERR;
- UINT nent;
- BYTE* dirb = dp->obj.fs->dirbuf; /* Pointer to the directory entry block 85+C0+C1s */
-
- /* Create set sum */
- st_word(dirb + XDIR_SetSum, xdir_sum(dirb));
- nent = dirb[XDIR_NumSec] + 1;
-
- /* Store the directory entry block to the directory */
- res = dir_sdi(dp, dp->blk_ofs);
- while (res == FR_OK) {
- res = move_window(dp->obj.fs, dp->sect);
- if (res != FR_OK) break;
- mem_cpy(dp->dir, dirb, SZDIRE);
- dp->obj.fs->wflag = 1;
- if (--nent == 0) break;
- dirb += SZDIRE;
- res = dir_next(dp, 0);
- }
- return (res == FR_OK || res == FR_DISK_ERR) ? res : FR_INT_ERR;
-}
-
-
-
-/*-------------------------------------------*/
-/* exFAT: Create a new directory entry block */
-/*-------------------------------------------*/
-
-static void create_xdir (
- BYTE* dirb, /* Pointer to the directory entry block buffer */
- const WCHAR* lfn /* Pointer to the object name */
-)
-{
- UINT i;
- BYTE nc1, nlen;
- WCHAR wc;
-
-
- /* Create 85,C0 entry */
- mem_set(dirb, 0, 2 * SZDIRE);
- dirb[0 * SZDIRE + XDIR_Type] = 0x85; /* 85 entry */
- dirb[1 * SZDIRE + XDIR_Type] = 0xC0; /* C0 entry */
-
- /* Create C1 entries */
- i = SZDIRE * 2; /* Top of C1 entries */
- nlen = nc1 = 0; wc = 1;
- do {
- dirb[i++] = 0xC1; dirb[i++] = 0; /* Entry type C1 */
- do { /* Fill name field */
- if (wc != 0 && (wc = lfn[nlen]) != 0) nlen++; /* Get a character if exist */
- st_word(dirb + i, wc); /* Store it */
- i += 2;
- } while (i % SZDIRE != 0);
- nc1++;
- } while (lfn[nlen]); /* Fill next entry if any char follows */
-
- dirb[XDIR_NumName] = nlen; /* Set name length */
- dirb[XDIR_NumSec] = 1 + nc1; /* Set secondary count (C0 + C1s) */
- st_word(dirb + XDIR_NameHash, xname_sum(lfn)); /* Set name hash */
-}
-
-#endif /* !FF_FS_READONLY */
-#endif /* FF_FS_EXFAT */
-
-
-
-#if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 || FF_USE_LABEL || FF_FS_EXFAT
-/*-----------------------------------------------------------------------*/
-/* Read an object from the directory */
-/*-----------------------------------------------------------------------*/
-
-#define dir_read_file(dp) dir_read(dp, 0)
-#define dir_read_label(dp) dir_read(dp, 1)
-
-static FRESULT dir_read (
- DIR* dp, /* Pointer to the directory object */
- int vol /* Filtered by 0:file/directory or 1:volume label */
-)
-{
- FRESULT res = FR_NO_FILE;
- FATFS *fs = dp->obj.fs;
- BYTE a, c;
-#if FF_USE_LFN
- BYTE ord = 0xFF, sum = 0xFF;
-#endif
-
- while (dp->sect) {
- res = move_window(fs, dp->sect);
- if (res != FR_OK) break;
- c = dp->dir[DIR_Name]; /* Test for the entry type */
- if (c == 0) {
- res = FR_NO_FILE; break; /* Reached to end of the directory */
- }
-#if FF_FS_EXFAT
- if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */
- if (FF_USE_LABEL && vol) {
- if (c == 0x83) break; /* Volume label entry? */
- } else {
- if (c == 0x85) { /* Start of the file entry block? */
- dp->blk_ofs = dp->dptr; /* Get location of the block */
- res = load_xdir(dp); /* Load the entry block */
- if (res == FR_OK) {
- dp->obj.attr = fs->dirbuf[XDIR_Attr] & AM_MASK; /* Get attribute */
- }
- break;
- }
- }
- } else
-#endif
- { /* On the FAT/FAT32 volume */
- dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK; /* Get attribute */
-#if FF_USE_LFN /* LFN configuration */
- if (c == DDEM || c == '.' || (int)((a & ~AM_ARC) == AM_VOL) != vol) { /* An entry without valid data */
- ord = 0xFF;
- } else {
- if (a == AM_LFN) { /* An LFN entry is found */
- if (c & LLEF) { /* Is it start of an LFN sequence? */
- sum = dp->dir[LDIR_Chksum];
- c &= (BYTE)~LLEF; ord = c;
- dp->blk_ofs = dp->dptr;
- }
- /* Check LFN validity and capture it */
- ord = (c == ord && sum == dp->dir[LDIR_Chksum] && pick_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF;
- } else { /* An SFN entry is found */
- if (ord != 0 || sum != sum_sfn(dp->dir)) { /* Is there a valid LFN? */
- dp->blk_ofs = 0xFFFFFFFF; /* It has no LFN. */
- }
- break;
- }
- }
-#else /* Non LFN configuration */
- if (c != DDEM && c != '.' && a != AM_LFN && (int)((a & ~AM_ARC) == AM_VOL) == vol) { /* Is it a valid entry? */
- break;
- }
-#endif
- }
- res = dir_next(dp, 0); /* Next entry */
- if (res != FR_OK) break;
- }
-
- if (res != FR_OK) dp->sect = 0; /* Terminate the read operation on error or EOT */
- return res;
-}
-
-#endif /* FF_FS_MINIMIZE <= 1 || FF_USE_LABEL || FF_FS_RPATH >= 2 */
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Directory handling - Find an object in the directory */
-/*-----------------------------------------------------------------------*/
-
-static FRESULT dir_find ( /* FR_OK(0):succeeded, !=0:error */
- DIR* dp /* Pointer to the directory object with the file name */
-)
-{
- FRESULT res = FR_DISK_ERR;
- FATFS *fs = dp->obj.fs;
- BYTE c;
-#if FF_USE_LFN
- BYTE a, ord, sum;
-#endif
-
- res = dir_sdi(dp, 0); /* Rewind directory object */
- if (res != FR_OK) return res;
-#if FF_FS_EXFAT
- if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */
- BYTE nc;
- UINT di, ni;
- WORD hash = xname_sum(fs->lfnbuf); /* Hash value of the name to find */
-
- while ((res = dir_read_file(dp)) == FR_OK) { /* Read an item */
-#if FF_MAX_LFN < 255
- if (fs->dirbuf[XDIR_NumName] > FF_MAX_LFN) continue; /* Skip comparison if inaccessible object name */
-#endif
- if (ld_word(fs->dirbuf + XDIR_NameHash) != hash) continue; /* Skip comparison if hash mismatched */
- for (nc = fs->dirbuf[XDIR_NumName], di = SZDIRE * 2, ni = 0; nc; nc--, di += 2, ni++) { /* Compare the name */
- if ((di % SZDIRE) == 0) di += 2;
- if (ff_wtoupper(ld_word(fs->dirbuf + di)) != ff_wtoupper(fs->lfnbuf[ni])) break;
- }
- if (nc == 0 && !fs->lfnbuf[ni]) break; /* Name matched? */
- }
- return res;
- }
-#endif
- /* On the FAT/FAT32 volume */
-#if FF_USE_LFN
- ord = sum = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */
-#endif
- do {
- res = move_window(fs, dp->sect);
- if (res != FR_OK) break;
- c = dp->dir[DIR_Name];
- if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */
-#if FF_USE_LFN /* LFN configuration */
- dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK;
- if (c == DDEM || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */
- ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */
- } else {
- if (a == AM_LFN) { /* An LFN entry is found */
- if (!(dp->fn[NSFLAG] & NS_NOLFN)) {
- if (c & LLEF) { /* Is it start of LFN sequence? */
- sum = dp->dir[LDIR_Chksum];
- c &= (BYTE)~LLEF; ord = c; /* LFN start order */
- dp->blk_ofs = dp->dptr; /* Start offset of LFN */
- }
- /* Check validity of the LFN entry and compare it with given name */
- ord = (c == ord && sum == dp->dir[LDIR_Chksum] && cmp_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF;
- }
- } else { /* An SFN entry is found */
- if (ord == 0 && sum == sum_sfn(dp->dir)) break; /* LFN matched? */
- if (!(dp->fn[NSFLAG] & NS_LOSS) && !mem_cmp(dp->dir, dp->fn, 11)) break; /* SFN matched? */
- ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */
- }
- }
-#else /* Non LFN configuration */
- dp->obj.attr = dp->dir[DIR_Attr] & AM_MASK;
- if (!(dp->dir[DIR_Attr] & AM_VOL) && !mem_cmp(dp->dir, dp->fn, 11)) break; /* Is it a valid entry? */
-#endif
- res = dir_next(dp, 0); /* Next entry */
- } while (res == FR_OK);
-
- return res;
-}
-
-
-
-
-#if !FF_FS_READONLY
-/*-----------------------------------------------------------------------*/
-/* Register an object to the directory */
-/*-----------------------------------------------------------------------*/
-
-static FRESULT dir_register ( /* FR_OK:succeeded, FR_DENIED:no free entry or too many SFN collision, FR_DISK_ERR:disk error */
- DIR* dp /* Target directory with object name to be created */
-)
-{
- FRESULT res = FR_DISK_ERR;
- FATFS *fs = dp->obj.fs;
-#if FF_USE_LFN /* LFN configuration */
- UINT n, nlen, nent;
- BYTE sn[12], sum;
-
-
- if (dp->fn[NSFLAG] & (NS_DOT | NS_NONAME)) return FR_INVALID_NAME; /* Check name validity */
- for (nlen = 0; fs->lfnbuf[nlen]; nlen++) ; /* Get lfn length */
-
-#if FF_FS_EXFAT
- if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */
- nent = (nlen + 14) / 15 + 2; /* Number of entries to allocate (85+C0+C1s) */
- res = dir_alloc(dp, nent); /* Allocate entries */
- if (res != FR_OK) return res;
- dp->blk_ofs = dp->dptr - SZDIRE * (nent - 1); /* Set the allocated entry block offset */
-
- if (dp->obj.stat & 4) { /* Has the directory been stretched? */
- dp->obj.stat &= ~4;
- res = fill_first_frag(&dp->obj); /* Fill the first fragment on the FAT if needed */
- if (res != FR_OK) return res;
- res = fill_last_frag(&dp->obj, dp->clust, 0xFFFFFFFF); /* Fill the last fragment on the FAT if needed */
- if (res != FR_OK) return res;
- if (dp->obj.sclust != 0) { /* Is it a sub directory? */
- DIR dj;
-
- res = load_obj_xdir(&dj, &dp->obj); /* Load the object status */
- if (res != FR_OK) return res;
- dp->obj.objsize += (DWORD)fs->csize * SS(fs); /* Increase the directory size by cluster size */
- st_qword(fs->dirbuf + XDIR_FileSize, dp->obj.objsize); /* Update the allocation status */
- st_qword(fs->dirbuf + XDIR_ValidFileSize, dp->obj.objsize);
- fs->dirbuf[XDIR_GenFlags] = dp->obj.stat | 1;
- res = store_xdir(&dj); /* Store the object status */
- if (res != FR_OK) return res;
- }
- }
-
- create_xdir(fs->dirbuf, fs->lfnbuf); /* Create on-memory directory block to be written later */
- return FR_OK;
- }
-#endif
- /* On the FAT/FAT32 volume */
- mem_cpy(sn, dp->fn, 12);
- if (sn[NSFLAG] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */
- dp->fn[NSFLAG] = NS_NOLFN; /* Find only SFN */
- for (n = 1; n < 100; n++) {
- gen_numname(dp->fn, sn, fs->lfnbuf, n); /* Generate a numbered name */
- res = dir_find(dp); /* Check if the name collides with existing SFN */
- if (res != FR_OK) break;
- }
- if (n == 100) return FR_DENIED; /* Abort if too many collisions */
- if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */
- dp->fn[NSFLAG] = sn[NSFLAG];
- }
-
- /* Create an SFN with/without LFNs. */
- nent = (sn[NSFLAG] & NS_LFN) ? (nlen + 12) / 13 + 1 : 1; /* Number of entries to allocate */
- res = dir_alloc(dp, nent); /* Allocate entries */
- if (res == FR_OK && --nent) { /* Set LFN entry if needed */
- res = dir_sdi(dp, dp->dptr - nent * SZDIRE);
- if (res == FR_OK) {
- sum = sum_sfn(dp->fn); /* Checksum value of the SFN tied to the LFN */
- do { /* Store LFN entries in bottom first */
- res = move_window(fs, dp->sect);
- if (res != FR_OK) break;
- put_lfn(fs->lfnbuf, dp->dir, (BYTE)nent, sum);
- fs->wflag = 1;
- res = dir_next(dp, 0); /* Next entry */
- } while (res == FR_OK && --nent);
- }
- }
-
-#else /* Non LFN configuration */
- res = dir_alloc(dp, 1); /* Allocate an entry for SFN */
-
-#endif
-
- /* Set SFN entry */
- if (res == FR_OK) {
- res = move_window(fs, dp->sect);
- if (res == FR_OK) {
- mem_set(dp->dir, 0, SZDIRE); /* Clean the entry */
- mem_cpy(dp->dir + DIR_Name, dp->fn, 11); /* Put SFN */
-#if FF_USE_LFN
- dp->dir[DIR_NTres] = dp->fn[NSFLAG] & (NS_BODY | NS_EXT); /* Put NT flag */
-#endif
- fs->wflag = 1;
- }
- }
-
- return res;
-}
-
-#endif /* !FF_FS_READONLY */
-
-
-
-#if !FF_FS_READONLY && FF_FS_MINIMIZE == 0
-/*-----------------------------------------------------------------------*/
-/* Remove an object from the directory */
-/*-----------------------------------------------------------------------*/
-
-static FRESULT dir_remove ( /* FR_OK:Succeeded, FR_DISK_ERR:A disk error */
- DIR* dp /* Directory object pointing the entry to be removed */
-)
-{
- FRESULT res = FR_DISK_ERR;
- FATFS *fs = dp->obj.fs;
-#if FF_USE_LFN /* LFN configuration */
- DWORD last = dp->dptr;
-
- res = (dp->blk_ofs == 0xFFFFFFFF) ? FR_OK : dir_sdi(dp, dp->blk_ofs); /* Goto top of the entry block if LFN is exist */
- if (res == FR_OK) {
- do {
- res = move_window(fs, dp->sect);
- if (res != FR_OK) break;
- if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) { /* On the exFAT volume */
- dp->dir[XDIR_Type] &= 0x7F; /* Clear the entry InUse flag. */
- } else { /* On the FAT/FAT32 volume */
- dp->dir[DIR_Name] = DDEM; /* Mark the entry 'deleted'. */
- }
- fs->wflag = 1;
- if (dp->dptr >= last) break; /* If reached last entry then all entries of the object has been deleted. */
- res = dir_next(dp, 0); /* Next entry */
- } while (res == FR_OK);
- if (res == FR_NO_FILE) res = FR_INT_ERR;
- }
-#else /* Non LFN configuration */
-
- res = move_window(fs, dp->sect);
- if (res == FR_OK) {
- dp->dir[DIR_Name] = DDEM; /* Mark the entry 'deleted'.*/
- fs->wflag = 1;
- }
-#endif
-
- return res;
-}
-
-#endif /* !FF_FS_READONLY && FF_FS_MINIMIZE == 0 */
-
-
-
-#if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2
-/*-----------------------------------------------------------------------*/
-/* Get file information from directory entry */
-/*-----------------------------------------------------------------------*/
-
-static void get_fileinfo (
- DIR* dp, /* Pointer to the directory object */
- FILINFO* fno /* Pointer to the file information to be filled */
-)
-{
- UINT si, di;
-#if FF_USE_LFN
- WCHAR wc, hs;
- FATFS *fs = dp->obj.fs;
-#else
- TCHAR c;
-#endif
-
-
- fno->fname[0] = 0; /* Invaidate file info */
- if (dp->sect == 0) return; /* Exit if read pointer has reached end of directory */
-
-#if FF_USE_LFN /* LFN configuration */
-#if FF_FS_EXFAT
- if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */
- get_xfileinfo(fs->dirbuf, fno);
- return;
- } else
-#endif
- { /* On the FAT/FAT32 volume */
- if (dp->blk_ofs != 0xFFFFFFFF) { /* Get LFN if available */
- si = di = hs = 0;
- while (fs->lfnbuf[si] != 0) {
- wc = fs->lfnbuf[si++]; /* Get an LFN character (UTF-16) */
- if (hs == 0 && IsSurrogate(wc)) { /* Is it a surrogate? */
- hs = wc; continue; /* Get low surrogate */
- }
- wc = put_utf((DWORD)hs << 16 | wc, &fno->fname[di], FF_LFN_BUF - di); /* Store it in UTF-16 or UTF-8 encoding */
- if (wc == 0) { di = 0; break; } /* Invalid char or buffer overflow? */
- di += wc;
- hs = 0;
- }
- if (hs != 0) di = 0; /* Broken surrogate pair? */
- fno->fname[di] = 0; /* Terminate the LFN (null string means LFN is invalid) */
- }
- }
-
- si = di = 0;
- while (si < 11) { /* Get SFN from SFN entry */
- wc = dp->dir[si++]; /* Get a char */
- if (wc == ' ') continue; /* Skip padding spaces */
- if (wc == RDDEM) wc = DDEM; /* Restore replaced DDEM character */
- if (si == 9 && di < FF_SFN_BUF) fno->altname[di++] = '.'; /* Insert a . if extension is exist */
-#if FF_LFN_UNICODE >= 1 /* Unicode output */
- if (dbc_1st((BYTE)wc) && si != 8 && si != 11 && dbc_2nd(dp->dir[si])) { /* Make a DBC if needed */
- wc = wc << 8 | dp->dir[si++];
- }
- wc = ff_oem2uni(wc, CODEPAGE); /* ANSI/OEM -> Unicode */
- if (wc == 0) { di = 0; break; } /* Wrong char in the current code page? */
- wc = put_utf(wc, &fno->altname[di], FF_SFN_BUF - di); /* Store it in Unicode */
- if (wc == 0) { di = 0; break; } /* Buffer overflow? */
- di += wc;
-#else /* ANSI/OEM output */
- fno->altname[di++] = (TCHAR)wc; /* Store it without any conversion */
-#endif
- }
- fno->altname[di] = 0; /* Terminate the SFN (null string means SFN is invalid) */
-
- if (fno->fname[0] == 0) { /* If LFN is invalid, altname[] needs to be copied to fname[] */
- if (di == 0) { /* If LFN and SFN both are invalid, this object is inaccessible */
- fno->fname[di++] = '?';
- } else {
- for (si = di = 0; fno->altname[si]; si++, di++) { /* Copy altname[] to fname[] with case information */
- wc = (WCHAR)fno->altname[si];
- if (IsUpper(wc) && (dp->dir[DIR_NTres] & ((si >= 9) ? NS_EXT : NS_BODY))) wc += 0x20;
- fno->fname[di] = (TCHAR)wc;
- }
- }
- fno->fname[di] = 0; /* Terminate the LFN */
- if (!dp->dir[DIR_NTres]) fno->altname[0] = 0; /* Altname is not needed if neither LFN nor case info is exist. */
- }
-
-#else /* Non-LFN configuration */
- si = di = 0;
- while (si < 11) { /* Copy name body and extension */
- c = (TCHAR)dp->dir[si++];
- if (c == ' ') continue; /* Skip padding spaces */
- if (c == RDDEM) c = DDEM; /* Restore replaced DDEM character */
- if (si == 9) fno->fname[di++] = '.';/* Insert a . if extension is exist */
- fno->fname[di++] = c;
- }
- fno->fname[di] = 0;
-#endif
-
- fno->fattrib = dp->dir[DIR_Attr]; /* Attribute */
- fno->fsize = ld_dword(dp->dir + DIR_FileSize); /* Size */
- fno->ftime = ld_word(dp->dir + DIR_ModTime + 0); /* Time */
- fno->fdate = ld_word(dp->dir + DIR_ModTime + 2); /* Date */
-}
-
-#endif /* FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 */
-
-
-
-#if FF_USE_FIND && FF_FS_MINIMIZE <= 1
-/*-----------------------------------------------------------------------*/
-/* Pattern matching */
-/*-----------------------------------------------------------------------*/
-
-static DWORD get_achar ( /* Get a character and advances ptr */
- const TCHAR** ptr /* Pointer to pointer to the ANSI/OEM or Unicode string */
-)
-{
- DWORD chr;
-
-
-#if FF_USE_LFN && FF_LFN_UNICODE >= 1 /* Unicode input */
- chr = tchar2uni(ptr);
- if (chr == 0xFFFFFFFF) chr = 0; /* Wrong UTF encoding is recognized as end of the string */
- chr = ff_wtoupper(chr);
-
-#else /* ANSI/OEM input */
- chr = (BYTE)*(*ptr)++; /* Get a byte */
- if (IsLower(chr)) chr -= 0x20; /* To upper ASCII char */
-#if FF_CODE_PAGE == 0
- if (ExCvt && chr >= 0x80) chr = ExCvt[chr - 0x80]; /* To upper SBCS extended char */
-#elif FF_CODE_PAGE < 900
- if (chr >= 0x80) chr = ExCvt[chr - 0x80]; /* To upper SBCS extended char */
-#endif
-#if FF_CODE_PAGE == 0 || FF_CODE_PAGE >= 900
- if (dbc_1st((BYTE)chr)) { /* Get DBC 2nd byte if needed */
- chr = dbc_2nd((BYTE)**ptr) ? chr << 8 | (BYTE)*(*ptr)++ : 0;
- }
-#endif
-
-#endif
- return chr;
-}
-
-
-static int pattern_matching ( /* 0:not matched, 1:matched */
- const TCHAR* pat, /* Matching pattern */
- const TCHAR* nam, /* String to be tested */
- int skip, /* Number of pre-skip chars (number of ?s) */
- int inf /* Infinite search (* specified) */
-)
-{
- const TCHAR *pp, *np;
- DWORD pc, nc;
- int nm, nx;
-
-
- while (skip--) { /* Pre-skip name chars */
- if (!get_achar(&nam)) return 0; /* Branch mismatched if less name chars */
- }
- if (*pat == 0 && inf) return 1; /* (short circuit) */
-
- do {
- pp = pat; np = nam; /* Top of pattern and name to match */
- for (;;) {
- if (*pp == '?' || *pp == '*') { /* Wildcard? */
- nm = nx = 0;
- do { /* Analyze the wildcard block */
- if (*pp++ == '?') nm++; else nx = 1;
- } while (*pp == '?' || *pp == '*');
- if (pattern_matching(pp, np, nm, nx)) return 1; /* Test new branch (recurs up to number of wildcard blocks in the pattern) */
- nc = *np; break; /* Branch mismatched */
- }
- pc = get_achar(&pp); /* Get a pattern char */
- nc = get_achar(&np); /* Get a name char */
- if (pc != nc) break; /* Branch mismatched? */
- if (pc == 0) return 1; /* Branch matched? (matched at end of both strings) */
- }
- get_achar(&nam); /* nam++ */
- } while (inf && nc); /* Retry until end of name if infinite search is specified */
-
- return 0;
-}
-
-#endif /* FF_USE_FIND && FF_FS_MINIMIZE <= 1 */
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Pick a top segment and create the object name in directory form */
-/*-----------------------------------------------------------------------*/
-
-static FRESULT create_name ( /* FR_OK: successful, FR_INVALID_NAME: could not create */
- DIR* dp, /* Pointer to the directory object */
- const TCHAR** path /* Pointer to pointer to the segment in the path string */
-)
-{
-#if FF_USE_LFN /* LFN configuration */
- BYTE b, cf;
- WCHAR wc, *lfn;
- DWORD uc;
- UINT i, ni, si, di;
- const TCHAR *p;
-
-
- /* Create LFN into LFN working buffer */
- p = *path; lfn = dp->obj.fs->lfnbuf; di = 0;
- for (;;) {
- uc = tchar2uni(&p); /* Get a character */
- if (uc == 0xFFFFFFFF) return FR_INVALID_NAME; /* Invalid code or UTF decode error */
- if (uc >= 0x10000) lfn[di++] = (WCHAR)(uc >> 16); /* Store high surrogate if needed */
- wc = (WCHAR)uc;
- if (wc < ' ' || wc == '/' || wc == '\\') break; /* Break if end of the path or a separator is found */
- if (wc < 0x80 && chk_chr("\"*:<>\?|\x7F", wc)) return FR_INVALID_NAME; /* Reject illegal characters for LFN */
- if (di >= FF_MAX_LFN) return FR_INVALID_NAME; /* Reject too long name */
- lfn[di++] = wc; /* Store the Unicode character */
- }
- while (*p == '/' || *p == '\\') p++; /* Skip duplicated separators if exist */
- *path = p; /* Return pointer to the next segment */
- cf = (wc < ' ') ? NS_LAST : 0; /* Set last segment flag if end of the path */
-
-#if FF_FS_RPATH != 0
- if ((di == 1 && lfn[di - 1] == '.') ||
- (di == 2 && lfn[di - 1] == '.' && lfn[di - 2] == '.')) { /* Is this segment a dot name? */
- lfn[di] = 0;
- for (i = 0; i < 11; i++) { /* Create dot name for SFN entry */
- dp->fn[i] = (i < di) ? '.' : ' ';
- }
- dp->fn[i] = cf | NS_DOT; /* This is a dot entry */
- return FR_OK;
- }
-#endif
- while (di) { /* Snip off trailing spaces and dots if exist */
- wc = lfn[di - 1];
- if (wc != ' ' && wc != '.') break;
- di--;
- }
- lfn[di] = 0; /* LFN is created into the working buffer */
- if (di == 0) return FR_INVALID_NAME; /* Reject null name */
-
- /* Create SFN in directory form */
- for (si = 0; lfn[si] == ' '; si++) ; /* Remove leading spaces */
- if (si > 0 || lfn[si] == '.') cf |= NS_LOSS | NS_LFN; /* Is there any leading space or dot? */
- while (di > 0 && lfn[di - 1] != '.') di--; /* Find last dot (di<=si: no extension) */
-
- mem_set(dp->fn, ' ', 11);
- i = b = 0; ni = 8;
- for (;;) {
- wc = lfn[si++]; /* Get an LFN character */
- if (wc == 0) break; /* Break on end of the LFN */
- if (wc == ' ' || (wc == '.' && si != di)) { /* Remove embedded spaces and dots */
- cf |= NS_LOSS | NS_LFN;
- continue;
- }
-
- if (i >= ni || si == di) { /* End of field? */
- if (ni == 11) { /* Name extension overflow? */
- cf |= NS_LOSS | NS_LFN;
- break;
- }
- if (si != di) cf |= NS_LOSS | NS_LFN; /* Name body overflow? */
- if (si > di) break; /* No name extension? */
- si = di; i = 8; ni = 11; b <<= 2; /* Enter name extension */
- continue;
- }
-
- if (wc >= 0x80) { /* Is this a non-ASCII character? */
- cf |= NS_LFN; /* LFN entry needs to be created */
-#if FF_CODE_PAGE == 0
- if (ExCvt) { /* At SBCS */
- wc = ff_uni2oem(wc, CODEPAGE); /* Unicode ==> ANSI/OEM code */
- if (wc & 0x80) wc = ExCvt[wc & 0x7F]; /* Convert extended character to upper (SBCS) */
- } else { /* At DBCS */
- wc = ff_uni2oem(ff_wtoupper(wc), CODEPAGE); /* Unicode ==> Upper convert ==> ANSI/OEM code */
- }
-#elif FF_CODE_PAGE < 900 /* SBCS cfg */
- wc = ff_uni2oem(wc, CODEPAGE); /* Unicode ==> ANSI/OEM code */
- if (wc & 0x80) wc = ExCvt[wc & 0x7F]; /* Convert extended character to upper (SBCS) */
-#else /* DBCS cfg */
- wc = ff_uni2oem(ff_wtoupper(wc), CODEPAGE); /* Unicode ==> Upper convert ==> ANSI/OEM code */
-#endif
- }
-
- if (wc >= 0x100) { /* Is this a DBC? */
- if (i >= ni - 1) { /* Field overflow? */
- cf |= NS_LOSS | NS_LFN;
- i = ni; continue; /* Next field */
- }
- dp->fn[i++] = (BYTE)(wc >> 8); /* Put 1st byte */
- } else { /* SBC */
- if (wc == 0 || chk_chr("+,;=[]", wc)) { /* Replace illegal characters for SFN if needed */
- wc = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */
- } else {
- if (IsUpper(wc)) { /* ASCII upper case? */
- b |= 2;
- }
- if (IsLower(wc)) { /* ASCII lower case? */
- b |= 1; wc -= 0x20;
- }
- }
- }
- dp->fn[i++] = (BYTE)wc;
- }
-
- if (dp->fn[0] == DDEM) dp->fn[0] = RDDEM; /* If the first character collides with DDEM, replace it with RDDEM */
-
- if (ni == 8) b <<= 2; /* Shift capital flags if no extension */
- if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) cf |= NS_LFN; /* LFN entry needs to be created if composite capitals */
- if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended character, NT flags are created */
- if (b & 0x01) cf |= NS_EXT; /* NT flag (Extension has small capital letters only) */
- if (b & 0x04) cf |= NS_BODY; /* NT flag (Body has small capital letters only) */
- }
-
- dp->fn[NSFLAG] = cf; /* SFN is created into dp->fn[] */
-
- return FR_OK;
-
-
-#else /* FF_USE_LFN : Non-LFN configuration */
- BYTE c, d, *sfn;
- UINT ni, si, i;
- const char *p;
-
- /* Create file name in directory form */
- p = *path; sfn = dp->fn;
- mem_set(sfn, ' ', 11);
- si = i = 0; ni = 8;
-#if FF_FS_RPATH != 0
- if (p[si] == '.') { /* Is this a dot entry? */
- for (;;) {
- c = (BYTE)p[si++];
- if (c != '.' || si >= 3) break;
- sfn[i++] = c;
- }
- if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME;
- *path = p + si; /* Return pointer to the next segment */
- sfn[NSFLAG] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of the path */
- return FR_OK;
- }
-#endif
- for (;;) {
- c = (BYTE)p[si++]; /* Get a byte */
- if (c <= ' ') break; /* Break if end of the path name */
- if (c == '/' || c == '\\') { /* Break if a separator is found */
- while (p[si] == '/' || p[si] == '\\') si++; /* Skip duplicated separator if exist */
- break;
- }
- if (c == '.' || i >= ni) { /* End of body or field overflow? */
- if (ni == 11 || c != '.') return FR_INVALID_NAME; /* Field overflow or invalid dot? */
- i = 8; ni = 11; /* Enter file extension field */
- continue;
- }
-#if FF_CODE_PAGE == 0
- if (ExCvt && c >= 0x80) { /* Is SBC extended character? */
- c = ExCvt[c & 0x7F]; /* To upper SBC extended character */
- }
-#elif FF_CODE_PAGE < 900
- if (c >= 0x80) { /* Is SBC extended character? */
- c = ExCvt[c & 0x7F]; /* To upper SBC extended character */
- }
-#endif
- if (dbc_1st(c)) { /* Check if it is a DBC 1st byte */
- d = (BYTE)p[si++]; /* Get 2nd byte */
- if (!dbc_2nd(d) || i >= ni - 1) return FR_INVALID_NAME; /* Reject invalid DBC */
- sfn[i++] = c;
- sfn[i++] = d;
- } else { /* SBC */
- if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) return FR_INVALID_NAME; /* Reject illegal chrs for SFN */
- if (IsLower(c)) c -= 0x20; /* To upper */
- sfn[i++] = c;
- }
- }
- *path = p + si; /* Return pointer to the next segment */
- if (i == 0) return FR_INVALID_NAME; /* Reject nul string */
-
- if (sfn[0] == DDEM) sfn[0] = RDDEM; /* If the first character collides with DDEM, replace it with RDDEM */
- sfn[NSFLAG] = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of the path */
-
- return FR_OK;
-#endif /* FF_USE_LFN */
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Follow a file path */
-/*-----------------------------------------------------------------------*/
-
-static FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */
- DIR* dp, /* Directory object to return last directory and found object */
- const TCHAR* path /* Full-path string to find a file or directory */
-)
-{
- FRESULT res = FR_DISK_ERR;
- BYTE ns;
- FATFS *fs = dp->obj.fs;
-
-
-#if FF_FS_RPATH != 0
- if (*path != '/' && *path != '\\') { /* Without heading separator */
- dp->obj.sclust = fs->cdir; /* Start from current directory */
- } else
-#endif
- { /* With heading separator */
- while (*path == '/' || *path == '\\') path++; /* Strip heading separator */
- dp->obj.sclust = 0; /* Start from root directory */
- }
-#if FF_FS_EXFAT
- dp->obj.n_frag = 0; /* Invalidate last fragment counter of the object */
-#if FF_FS_RPATH != 0
- if (fs->fs_type == FS_EXFAT && dp->obj.sclust) { /* exFAT: Retrieve the sub-directory's status */
- DIR dj;
-
- dp->obj.c_scl = fs->cdc_scl;
- dp->obj.c_size = fs->cdc_size;
- dp->obj.c_ofs = fs->cdc_ofs;
- res = load_obj_xdir(&dj, &dp->obj);
- if (res != FR_OK) return res;
- dp->obj.objsize = ld_dword(fs->dirbuf + XDIR_FileSize);
- dp->obj.stat = fs->dirbuf[XDIR_GenFlags] & 2;
- }
-#endif
-#endif
-
- if ((UINT)*path < ' ') { /* Null path name is the origin directory itself */
- dp->fn[NSFLAG] = NS_NONAME;
- res = dir_sdi(dp, 0);
-
- } else { /* Follow path */
- for (;;) {
- res = create_name(dp, &path); /* Get a segment name of the path */
- if (res != FR_OK) break;
- res = dir_find(dp); /* Find an object with the segment name */
- ns = dp->fn[NSFLAG];
- if (res != FR_OK) { /* Failed to find the object */
- if (res == FR_NO_FILE) { /* Object is not found */
- if (FF_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exist, stay there */
- if (!(ns & NS_LAST)) continue; /* Continue to follow if not last segment */
- dp->fn[NSFLAG] = NS_NONAME;
- res = FR_OK;
- } else { /* Could not find the object */
- if (!(ns & NS_LAST)) res = FR_NO_PATH; /* Adjust error code if not last segment */
- }
- }
- break;
- }
- if (ns & NS_LAST) break; /* Last segment matched. Function completed. */
- /* Get into the sub-directory */
- if (!(dp->obj.attr & AM_DIR)) { /* It is not a sub-directory and cannot follow */
- res = FR_NO_PATH; break;
- }
-#if FF_FS_EXFAT
- if (fs->fs_type == FS_EXFAT) { /* Save containing directory information for next dir */
- dp->obj.c_scl = dp->obj.sclust;
- dp->obj.c_size = ((DWORD)dp->obj.objsize & 0xFFFFFF00) | dp->obj.stat;
- dp->obj.c_ofs = dp->blk_ofs;
- init_alloc_info(fs, &dp->obj); /* Open next directory */
- } else
-#endif
- {
- dp->obj.sclust = ld_clust(fs, fs->win + dp->dptr % SS(fs)); /* Open next directory */
- }
- }
- }
-
- return res;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Get logical drive number from path name */
-/*-----------------------------------------------------------------------*/
-
-static int get_ldnumber ( /* Returns logical drive number (-1:invalid drive number or null pointer) */
- const TCHAR** path /* Pointer to pointer to the path name */
-)
-{
- const TCHAR *tp, *tt;
- TCHAR tc;
- int i, vol = -1;
-#if FF_STR_VOLUME_ID /* Find string volume ID */
- const char *sp;
- char c;
-#endif
-
- tt = tp = *path;
- if (!tp) return vol; /* Invalid path name? */
- do tc = *tt++; while ((UINT)tc >= (FF_USE_LFN ? ' ' : '!') && tc != ':'); /* Find a colon in the path */
-
- if (tc == ':') { /* DOS/Windows style volume ID? */
- i = FF_VOLUMES;
- if (IsDigit(*tp) && tp + 2 == tt) { /* Is there a numeric volume ID + colon? */
- i = (int)*tp - '0'; /* Get the LD number */
- }
-#if FF_STR_VOLUME_ID == 1 /* Arbitrary string is enabled */
- else {
- i = 0;
- do {
- sp = VolumeStr[i]; tp = *path; /* This string volume ID and path name */
- do { /* Compare the volume ID with path name */
- c = *sp++; tc = *tp++;
- if (IsLower(c)) c -= 0x20;
- if (IsLower(tc)) tc -= 0x20;
- } while (c && (TCHAR)c == tc);
- } while ((c || tp != tt) && ++i < FF_VOLUMES); /* Repeat for each id until pattern match */
- }
-#endif
- if ((UINT)i < FF_VOLUMES) { /* If a volume ID is found, get the drive number and strip it */
- vol = i; /* Drive number */
- *path = tt; /* Snip the drive prefix off */
- }
- return vol;
- }
-#if FF_STR_VOLUME_ID == 2 /* Unix style volume ID is enabled */
- if (*tp == '/') {
- i = 0;
- do {
- sp = VolumeStr[i]; tp = *path; /* This string volume ID and path name */
- do { /* Compare the volume ID with path name */
- c = *sp++; tc = *(++tp);
- if (IsLower(c)) c -= 0x20;
- if (IsLower(tc)) tc -= 0x20;
- } while (c && (TCHAR)c == tc);
- } while ((c || (tc != '/' && (UINT)tc >= (FF_USE_LFN ? ' ' : '!'))) && ++i < FF_VOLUMES); /* Repeat for each ID until pattern match */
- if (i < FF_VOLUMES) { /* If a volume ID is found, get the drive number and strip it */
- vol = i; /* Drive number */
- *path = tp; /* Snip the drive prefix off */
- return vol;
- }
- }
-#endif
- /* No drive prefix is found */
-#if FF_FS_RPATH != 0
- vol = CurrVol; /* Default drive is current drive */
-#else
- vol = 0; /* Default drive is 0 */
-#endif
- return vol; /* Return the default drive */
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Load a sector and check if it is an FAT VBR */
-/*-----------------------------------------------------------------------*/
-
-static BYTE check_fs ( /* 0:FAT, 1:exFAT, 2:Valid BS but not FAT, 3:Not a BS, 4:Disk error */
- FATFS* fs, /* Filesystem object */
- DWORD sect /* Sector# (lba) to load and check if it is an FAT-VBR or not */
-)
-{
- fs->wflag = 0; fs->winsect = 0xFFFFFFFF; /* Invaidate window */
- if (move_window(fs, sect) != FR_OK) return 4; /* Load boot record */
-
- if (ld_word(fs->win + BS_55AA) != 0xAA55) return 3; /* Check boot record signature (always here regardless of the sector size) */
-
-#if FF_FS_EXFAT
- if (!mem_cmp(fs->win + BS_JmpBoot, "\xEB\x76\x90" "EXFAT ", 11)) return 1; /* Check if exFAT VBR */
-#endif
- if (fs->win[BS_JmpBoot] == 0xE9 || fs->win[BS_JmpBoot] == 0xEB || fs->win[BS_JmpBoot] == 0xE8) { /* Valid JumpBoot code? */
- if (!mem_cmp(fs->win + BS_FilSysType, "FAT", 3)) return 0; /* Is it an FAT VBR? */
- if (!mem_cmp(fs->win + BS_FilSysType32, "FAT32", 5)) return 0; /* Is it an FAT32 VBR? */
- }
- return 2; /* Valid BS but not FAT */
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Determine logical drive number and mount the volume if needed */
-/*-----------------------------------------------------------------------*/
-
-static FRESULT find_volume ( /* FR_OK(0): successful, !=0: an error occurred */
- const TCHAR** path, /* Pointer to pointer to the path name (drive number) */
- FATFS** rfs, /* Pointer to pointer to the found filesystem object */
- BYTE mode /* !=0: Check write protection for write access */
-)
-{
- BYTE fmt, *pt;
- int vol;
- DSTATUS stat;
- DWORD bsect, fasize, tsect, sysect, nclst, szbfat, br[4];
- WORD nrsv;
- FATFS *fs;
- UINT i;
-
-
- /* Get logical drive number */
- *rfs = 0;
- vol = get_ldnumber(path);
- if (vol < 0) return FR_INVALID_DRIVE;
-
- /* Check if the filesystem object is valid or not */
- fs = FatFs[vol]; /* Get pointer to the filesystem object */
- if (!fs) return FR_NOT_ENABLED; /* Is the filesystem object available? */
-#if FF_FS_REENTRANT
- if (!lock_fs(fs)) return FR_TIMEOUT; /* Lock the volume */
-#endif
- *rfs = fs; /* Return pointer to the filesystem object */
-
- mode &= (BYTE)~FA_READ; /* Desired access mode, write access or not */
- if (fs->fs_type != 0) { /* If the volume has been mounted */
- stat = disk_status(fs->pdrv);
- if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized */
- if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check write protection if needed */
- return FR_WRITE_PROTECTED;
- }
- return FR_OK; /* The filesystem object is valid */
- }
- }
-
- /* The filesystem object is not valid. */
- /* Following code attempts to mount the volume. (analyze BPB and initialize the filesystem object) */
-
- fs->fs_type = 0; /* Clear the filesystem object */
- fs->pdrv = LD2PD(vol); /* Bind the logical drive and a physical drive */
- stat = disk_initialize(fs->pdrv); /* Initialize the physical drive */
- if (stat & STA_NOINIT) { /* Check if the initialization succeeded */
- return FR_NOT_READY; /* Failed to initialize due to no medium or hard error */
- }
- if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check disk write protection if needed */
- return FR_WRITE_PROTECTED;
- }
-#if FF_MAX_SS != FF_MIN_SS /* Get sector size (multiple sector size cfg only) */
- if (disk_ioctl(fs->pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK) return FR_DISK_ERR;
- if (SS(fs) > FF_MAX_SS || SS(fs) < FF_MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR;
-#endif
-
- /* Find an FAT partition on the drive. Supports only generic partitioning rules, FDISK and SFD. */
- bsect = 0;
- fmt = check_fs(fs, bsect); /* Load sector 0 and check if it is an FAT-VBR as SFD */
- if (fmt == 2 || (fmt < 2 && LD2PT(vol) != 0)) { /* Not an FAT-VBR or forced partition number */
- for (i = 0; i < 4; i++) { /* Get partition offset */
- pt = fs->win + (MBR_Table + i * SZ_PTE);
- br[i] = pt[PTE_System] ? ld_dword(pt + PTE_StLba) : 0;
- }
- i = LD2PT(vol); /* Partition number: 0:auto, 1-4:forced */
- if (i != 0) i--;
- do { /* Find an FAT volume */
- bsect = br[i];
- fmt = bsect ? check_fs(fs, bsect) : 3; /* Check the partition */
- } while (LD2PT(vol) == 0 && fmt >= 2 && ++i < 4);
- }
- if (fmt == 4) return FR_DISK_ERR; /* An error occurred in the disk I/O layer */
- if (fmt >= 2) return FR_NO_FILESYSTEM; /* No FAT volume is found */
-
- /* An FAT volume is found (bsect). Following code initializes the filesystem object */
-
-#if FF_FS_EXFAT
- if (fmt == 1) {
- QWORD maxlba;
-
- for (i = BPB_ZeroedEx; i < BPB_ZeroedEx + 53 && fs->win[i] == 0; i++) ; /* Check zero filler */
- if (i < BPB_ZeroedEx + 53) return FR_NO_FILESYSTEM;
-
- if (ld_word(fs->win + BPB_FSVerEx) != 0x100) return FR_NO_FILESYSTEM; /* Check exFAT version (must be version 1.0) */
-
- if (1 << fs->win[BPB_BytsPerSecEx] != SS(fs)) { /* (BPB_BytsPerSecEx must be equal to the physical sector size) */
- return FR_NO_FILESYSTEM;
- }
-
- maxlba = ld_qword(fs->win + BPB_TotSecEx) + bsect; /* Last LBA + 1 of the volume */
- if (maxlba >= 0x100000000) return FR_NO_FILESYSTEM; /* (It cannot be handled in 32-bit LBA) */
-
- fs->fsize = ld_dword(fs->win + BPB_FatSzEx); /* Number of sectors per FAT */
-
- fs->n_fats = fs->win[BPB_NumFATsEx]; /* Number of FATs */
- if (fs->n_fats != 1) return FR_NO_FILESYSTEM; /* (Supports only 1 FAT) */
-
- fs->csize = 1 << fs->win[BPB_SecPerClusEx]; /* Cluster size */
- if (fs->csize == 0) return FR_NO_FILESYSTEM; /* (Must be 1..32768) */
-
- nclst = ld_dword(fs->win + BPB_NumClusEx); /* Number of clusters */
- if (nclst > MAX_EXFAT) return FR_NO_FILESYSTEM; /* (Too many clusters) */
- fs->n_fatent = nclst + 2;
-
- /* Boundaries and Limits */
- fs->volbase = bsect;
- fs->database = bsect + ld_dword(fs->win + BPB_DataOfsEx);
- fs->fatbase = bsect + ld_dword(fs->win + BPB_FatOfsEx);
- if (maxlba < (QWORD)fs->database + nclst * fs->csize) return FR_NO_FILESYSTEM; /* (Volume size must not be smaller than the size required) */
- fs->dirbase = ld_dword(fs->win + BPB_RootClusEx);
-
- /* Check if bitmap location is in assumption (at the first cluster) */
- if (move_window(fs, clst2sect(fs, fs->dirbase)) != FR_OK) return FR_DISK_ERR;
- for (i = 0; i < SS(fs); i += SZDIRE) {
- if (fs->win[i] == 0x81 && ld_dword(fs->win + i + 20) == 2) break; /* 81 entry with cluster #2? */
- }
- if (i == SS(fs)) return FR_NO_FILESYSTEM;
-#if !FF_FS_READONLY
- fs->last_clst = fs->free_clst = 0xFFFFFFFF; /* Initialize cluster allocation information */
-#endif
- fmt = FS_EXFAT; /* FAT sub-type */
- } else
-#endif /* FF_FS_EXFAT */
- {
- if (ld_word(fs->win + BPB_BytsPerSec) != SS(fs)) return FR_NO_FILESYSTEM; /* (BPB_BytsPerSec must be equal to the physical sector size) */
-
- fasize = ld_word(fs->win + BPB_FATSz16); /* Number of sectors per FAT */
- if (fasize == 0) fasize = ld_dword(fs->win + BPB_FATSz32);
- fs->fsize = fasize;
-
- fs->n_fats = fs->win[BPB_NumFATs]; /* Number of FATs */
- if (fs->n_fats != 1 && fs->n_fats != 2) return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */
- fasize *= fs->n_fats; /* Number of sectors for FAT area */
-
- fs->csize = fs->win[BPB_SecPerClus]; /* Cluster size */
- if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) return FR_NO_FILESYSTEM; /* (Must be power of 2) */
-
- fs->n_rootdir = ld_word(fs->win + BPB_RootEntCnt); /* Number of root directory entries */
- if (fs->n_rootdir % (SS(fs) / SZDIRE)) return FR_NO_FILESYSTEM; /* (Must be sector aligned) */
-
- tsect = ld_word(fs->win + BPB_TotSec16); /* Number of sectors on the volume */
- if (tsect == 0) tsect = ld_dword(fs->win + BPB_TotSec32);
-
- nrsv = ld_word(fs->win + BPB_RsvdSecCnt); /* Number of reserved sectors */
- if (nrsv == 0) return FR_NO_FILESYSTEM; /* (Must not be 0) */
-
- /* Determine the FAT sub type */
- sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZDIRE); /* RSV + FAT + DIR */
- if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */
- nclst = (tsect - sysect) / fs->csize; /* Number of clusters */
- if (nclst == 0) return FR_NO_FILESYSTEM; /* (Invalid volume size) */
- fmt = 0;
- if (nclst <= MAX_FAT32) fmt = FS_FAT32;
- if (nclst <= MAX_FAT16) fmt = FS_FAT16;
- if (nclst <= MAX_FAT12) fmt = FS_FAT12;
- if (fmt == 0) return FR_NO_FILESYSTEM;
-
- /* Boundaries and Limits */
- fs->n_fatent = nclst + 2; /* Number of FAT entries */
- fs->volbase = bsect; /* Volume start sector */
- fs->fatbase = bsect + nrsv; /* FAT start sector */
- fs->database = bsect + sysect; /* Data start sector */
- if (fmt == FS_FAT32) {
- if (ld_word(fs->win + BPB_FSVer32) != 0) return FR_NO_FILESYSTEM; /* (Must be FAT32 revision 0.0) */
- if (fs->n_rootdir != 0) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */
- fs->dirbase = ld_dword(fs->win + BPB_RootClus32); /* Root directory start cluster */
- szbfat = fs->n_fatent * 4; /* (Needed FAT size) */
- } else {
- if (fs->n_rootdir == 0) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must not be 0) */
- fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */
- szbfat = (fmt == FS_FAT16) ? /* (Needed FAT size) */
- fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1);
- }
- if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) return FR_NO_FILESYSTEM; /* (BPB_FATSz must not be less than the size needed) */
-
-#if !FF_FS_READONLY
- /* Get FSInfo if available */
- fs->last_clst = fs->free_clst = 0xFFFFFFFF; /* Initialize cluster allocation information */
- fs->fsi_flag = 0x80;
-#if (FF_FS_NOFSINFO & 3) != 3
- if (fmt == FS_FAT32 /* Allow to update FSInfo only if BPB_FSInfo32 == 1 */
- && ld_word(fs->win + BPB_FSInfo32) == 1
- && move_window(fs, bsect + 1) == FR_OK)
- {
- fs->fsi_flag = 0;
- if (ld_word(fs->win + BS_55AA) == 0xAA55 /* Load FSInfo data if available */
- && ld_dword(fs->win + FSI_LeadSig) == 0x41615252
- && ld_dword(fs->win + FSI_StrucSig) == 0x61417272)
- {
-#if (FF_FS_NOFSINFO & 1) == 0
- fs->free_clst = ld_dword(fs->win + FSI_Free_Count);
-#endif
-#if (FF_FS_NOFSINFO & 2) == 0
- fs->last_clst = ld_dword(fs->win + FSI_Nxt_Free);
-#endif
- }
- }
-#endif /* (FF_FS_NOFSINFO & 3) != 3 */
-#endif /* !FF_FS_READONLY */
- }
-
- fs->fs_type = fmt; /* FAT sub-type */
- fs->id = ++Fsid; /* Volume mount ID */
-#if FF_USE_LFN == 1
- fs->lfnbuf = LfnBuf; /* Static LFN working buffer */
-#if FF_FS_EXFAT
- fs->dirbuf = DirBuf; /* Static directory block scratchpad buuffer */
-#endif
-#endif
-#if FF_FS_RPATH != 0
- fs->cdir = 0; /* Initialize current directory */
-#endif
-#if FF_FS_LOCK != 0 /* Clear file lock semaphores */
- clear_lock(fs);
-#endif
- return FR_OK;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Check if the file/directory object is valid or not */
-/*-----------------------------------------------------------------------*/
-
-static FRESULT validate ( /* Returns FR_OK or FR_INVALID_OBJECT */
- FFOBJID* obj, /* Pointer to the FFOBJID, the 1st member in the FIL/DIR object, to check validity */
- FATFS** rfs /* Pointer to pointer to the owner filesystem object to return */
-)
-{
- FRESULT res = FR_INVALID_OBJECT;
-
-
- if (obj && obj->fs && obj->fs->fs_type && obj->id == obj->fs->id) { /* Test if the object is valid */
-#if FF_FS_REENTRANT
- if (lock_fs(obj->fs)) { /* Obtain the filesystem object */
- if (!(disk_status(obj->fs->pdrv) & STA_NOINIT)) { /* Test if the phsical drive is kept initialized */
- res = FR_OK;
- } else {
- unlock_fs(obj->fs, FR_OK);
- }
- } else {
- res = FR_TIMEOUT;
- }
-#else
- if (!(disk_status(obj->fs->pdrv) & STA_NOINIT)) { /* Test if the phsical drive is kept initialized */
- res = FR_OK;
- }
-#endif
- }
- *rfs = (res == FR_OK) ? obj->fs : 0; /* Corresponding filesystem object */
- return res;
-}
-
-
-
-
-/*---------------------------------------------------------------------------
-
- Public Functions (FatFs API)
-
-----------------------------------------------------------------------------*/
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Mount/Unmount a Logical Drive */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_mount (
- FATFS* fs, /* Pointer to the filesystem object (NULL:unmount)*/
- const TCHAR* path, /* Logical drive number to be mounted/unmounted */
- BYTE opt /* Mode option 0:Do not mount (delayed mount), 1:Mount immediately */
-)
-{
- FATFS *cfs;
- int vol;
- FRESULT res = FR_DISK_ERR;
- const TCHAR *rp = path;
-
-
- /* Get logical drive number */
- vol = get_ldnumber(&rp);
- if (vol < 0) return FR_INVALID_DRIVE;
- cfs = FatFs[vol]; /* Pointer to fs object */
-
- if (cfs) {
-#if FF_FS_LOCK != 0
- clear_lock(cfs);
-#endif
-#if FF_FS_REENTRANT /* Discard sync object of the current volume */
- if (!ff_del_syncobj(cfs->sobj)) return FR_INT_ERR;
-#endif
- cfs->fs_type = 0; /* Clear old fs object */
- }
-
- if (fs) {
- fs->fs_type = 0; /* Clear new fs object */
-#if FF_FS_REENTRANT /* Create sync object for the new volume */
- if (!ff_cre_syncobj((BYTE)vol, &fs->sobj)) return FR_INT_ERR;
-#endif
- }
- FatFs[vol] = fs; /* Register new fs object */
-
- if (opt == 0) return FR_OK; /* Do not mount now, it will be mounted later */
-
- res = find_volume(&path, &fs, 0); /* Force mounted the volume */
- LEAVE_FF(fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Open or Create a File */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_open (
- FIL* fp, /* Pointer to the blank file object */
- const TCHAR* path, /* Pointer to the file name */
- BYTE mode /* Access mode and file open mode flags */
-)
-{
- FRESULT res = FR_DISK_ERR;
- DIR dj = {0};
- FATFS *fs;
-#if !FF_FS_READONLY
- DWORD dw, cl, bcs, clst, sc;
- FSIZE_t ofs;
-#endif
- DEF_NAMBUF
-
-
- if (!fp) return FR_INVALID_OBJECT;
-
- /* Get logical drive number */
- mode &= FF_FS_READONLY ? FA_READ : FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_CREATE_NEW | FA_OPEN_ALWAYS | FA_OPEN_APPEND;
- res = find_volume(&path, &fs, mode);
- if (res == FR_OK) {
- dj.obj.fs = fs;
- INIT_NAMBUF(fs);
- res = follow_path(&dj, path); /* Follow the file path */
-#if !FF_FS_READONLY /* Read/Write configuration */
- if (res == FR_OK) {
- if (dj.fn[NSFLAG] & NS_NONAME) { /* Origin directory itself? */
- res = FR_INVALID_NAME;
- }
-#if FF_FS_LOCK != 0
- else {
- res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0); /* Check if the file can be used */
- }
-#endif
- }
- /* Create or Open a file */
- if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) {
- if (res != FR_OK) { /* No file, create new */
- if (res == FR_NO_FILE) { /* There is no file to open, create a new entry */
-#if FF_FS_LOCK != 0
- res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES;
-#else
- res = dir_register(&dj);
-#endif
- }
- mode |= FA_CREATE_ALWAYS; /* File is created */
- }
- else { /* Any object with the same name is already existing */
- if (dj.obj.attr & (AM_RDO | AM_DIR)) { /* Cannot overwrite it (R/O or DIR) */
- res = FR_DENIED;
- } else {
- if (mode & FA_CREATE_NEW) res = FR_EXIST; /* Cannot create as new file */
- }
- }
- if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate the file if overwrite mode */
-#if FF_FS_EXFAT
- if (fs->fs_type == FS_EXFAT) {
- /* Get current allocation info */
- fp->obj.fs = fs;
- init_alloc_info(fs, &fp->obj);
- /* Set directory entry block initial state */
- mem_set(fs->dirbuf + 2, 0, 30); /* Clear 85 entry except for NumSec */
- mem_set(fs->dirbuf + 38, 0, 26); /* Clear C0 entry except for NumName and NameHash */
- fs->dirbuf[XDIR_Attr] = AM_ARC;
- st_dword(fs->dirbuf + XDIR_CrtTime, GET_FATTIME());
- fs->dirbuf[XDIR_GenFlags] = 1;
- res = store_xdir(&dj);
- if (res == FR_OK && fp->obj.sclust != 0) { /* Remove the cluster chain if exist */
- res = remove_chain(&fp->obj, fp->obj.sclust, 0);
- fs->last_clst = fp->obj.sclust - 1; /* Reuse the cluster hole */
- }
- } else
-#endif
- {
- /* Set directory entry initial state */
- cl = ld_clust(fs, dj.dir); /* Get current cluster chain */
- st_dword(dj.dir + DIR_CrtTime, GET_FATTIME()); /* Set created time */
- dj.dir[DIR_Attr] = AM_ARC; /* Reset attribute */
- st_clust(fs, dj.dir, 0); /* Reset file allocation info */
- st_dword(dj.dir + DIR_FileSize, 0);
- fs->wflag = 1;
- if (cl != 0) { /* Remove the cluster chain if exist */
- dw = fs->winsect;
- res = remove_chain(&dj.obj, cl, 0);
- if (res == FR_OK) {
- res = move_window(fs, dw);
- fs->last_clst = cl - 1; /* Reuse the cluster hole */
- }
- }
- }
- }
- }
- else { /* Open an existing file */
- if (res == FR_OK) { /* Is the object existing? */
- if (dj.obj.attr & AM_DIR) { /* File open against a directory */
- res = FR_NO_FILE;
- } else {
- if ((mode & FA_WRITE) && (dj.obj.attr & AM_RDO)) { /* Write mode open against R/O file */
- res = FR_DENIED;
- }
- }
- }
- }
- if (res == FR_OK) {
- if (mode & FA_CREATE_ALWAYS) mode |= FA_MODIFIED; /* Set file change flag if created or overwritten */
- fp->dir_sect = fs->winsect; /* Pointer to the directory entry */
- fp->dir_ptr = dj.dir;
-#if FF_FS_LOCK != 0
- fp->obj.lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0); /* Lock the file for this session */
- if (fp->obj.lockid == 0) res = FR_INT_ERR;
-#endif
- }
-#else /* R/O configuration */
- if (res == FR_OK) {
- if (dj.fn[NSFLAG] & NS_NONAME) { /* Is it origin directory itself? */
- res = FR_INVALID_NAME;
- } else {
- if (dj.obj.attr & AM_DIR) { /* Is it a directory? */
- res = FR_NO_FILE;
- }
- }
- }
-#endif
-
- if (res == FR_OK) {
-#if FF_FS_EXFAT
- if (fs->fs_type == FS_EXFAT) {
- fp->obj.c_scl = dj.obj.sclust; /* Get containing directory info */
- fp->obj.c_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat;
- fp->obj.c_ofs = dj.blk_ofs;
- init_alloc_info(fs, &fp->obj);
- } else
-#endif
- {
- fp->obj.sclust = ld_clust(fs, dj.dir); /* Get object allocation info */
- fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize);
- }
-#if FF_USE_FASTSEEK
- fp->cltbl = 0; /* Disable fast seek mode */
-#endif
- fp->obj.fs = fs; /* Validate the file object */
- fp->obj.id = fs->id;
- fp->flag = mode; /* Set file access mode */
- fp->err = 0; /* Clear error flag */
- fp->sect = 0; /* Invalidate current data sector */
- fp->fptr = 0; /* Set file pointer top of the file */
-#if !FF_FS_READONLY
-#if !FF_FS_TINY
- mem_set(fp->buf, 0, FF_MAX_SS); /* Clear sector buffer */
-#endif
- if ((mode & FA_SEEKEND) && fp->obj.objsize > 0) { /* Seek to end of file if FA_OPEN_APPEND is specified */
- fp->fptr = fp->obj.objsize; /* Offset to seek */
- bcs = (DWORD)fs->csize * SS(fs); /* Cluster size in byte */
- clst = fp->obj.sclust; /* Follow the cluster chain */
- for (ofs = fp->obj.objsize; res == FR_OK && ofs > bcs; ofs -= bcs) {
- clst = get_fat(&fp->obj, clst);
- if (clst <= 1) res = FR_INT_ERR;
- if (clst == 0xFFFFFFFF) res = FR_DISK_ERR;
- }
- fp->clust = clst;
- if (res == FR_OK && ofs % SS(fs)) { /* Fill sector buffer if not on the sector boundary */
- if ((sc = clst2sect(fs, clst)) == 0) {
- res = FR_INT_ERR;
- } else {
- fp->sect = sc + (DWORD)(ofs / SS(fs));
-#if !FF_FS_TINY
- if (disk_read(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) res = FR_DISK_ERR;
-#endif
- }
- }
- }
-#endif
- }
-
- FREE_NAMBUF();
- }
-
- if (res != FR_OK) fp->obj.fs = 0; /* Invalidate file object on error */
-
- LEAVE_FF(fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Read File */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_read (
- FIL* fp, /* Pointer to the file object */
- void* buff, /* Pointer to data buffer */
- UINT btr, /* Number of bytes to read */
- UINT* br /* Pointer to number of bytes read */
-)
-{
- FRESULT res = FR_DISK_ERR;
- FATFS *fs;
- DWORD clst, sect;
- FSIZE_t remain;
- UINT rcnt, cc, csect;
- BYTE *rbuff = (BYTE*)buff;
-
-
- *br = 0; /* Clear read byte counter */
- res = validate(&fp->obj, &fs); /* Check validity of the file object */
- if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */
- if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */
- remain = fp->obj.objsize - fp->fptr;
- if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */
-
- for ( ; btr; /* Repeat until btr bytes read */
- btr -= rcnt, *br += rcnt, rbuff += rcnt, fp->fptr += rcnt) {
- if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */
- csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1)); /* Sector offset in the cluster */
- if (csect == 0) { /* On the cluster boundary? */
- if (fp->fptr == 0) { /* On the top of the file? */
- clst = fp->obj.sclust; /* Follow cluster chain from the origin */
- } else { /* Middle or end of the file */
-#if FF_USE_FASTSEEK
- if (fp->cltbl) {
- clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */
- } else
-#endif
- {
- clst = get_fat(&fp->obj, fp->clust); /* Follow cluster chain on the FAT */
- }
- }
- if (clst < 2) ABORT(fs, FR_INT_ERR);
- if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
- fp->clust = clst; /* Update current cluster */
- }
- sect = clst2sect(fs, fp->clust); /* Get current sector */
- if (sect == 0) ABORT(fs, FR_INT_ERR);
- sect += csect;
- cc = btr / SS(fs); /* When remaining bytes >= sector size, */
- if (cc > 0) { /* Read maximum contiguous sectors directly */
- if (csect + cc > fs->csize) { /* Clip at cluster boundary */
- cc = fs->csize - csect;
- }
- if (disk_read(fs->pdrv, rbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR);
-#if !FF_FS_READONLY && FF_FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it contains a dirty sector */
-#if FF_FS_TINY
- if (fs->wflag && fs->winsect - sect < cc) {
- mem_cpy(rbuff + ((fs->winsect - sect) * SS(fs)), fs->win, SS(fs));
- }
-#else
- if ((fp->flag & FA_DIRTY) && fp->sect - sect < cc) {
- mem_cpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs));
- }
-#endif
-#endif
- rcnt = SS(fs) * cc; /* Number of bytes transferred */
- continue;
- }
-#if !FF_FS_TINY
- if (fp->sect != sect) { /* Load data sector if not in cache */
-#if !FF_FS_READONLY
- if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */
- if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
- fp->flag &= (BYTE)~FA_DIRTY;
- }
-#endif
- if (disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Fill sector cache */
- }
-#endif
- fp->sect = sect;
- }
- rcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes left in the sector */
- if (rcnt > btr) rcnt = btr; /* Clip it by btr if needed */
-#if FF_FS_TINY
- if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window */
- mem_cpy(rbuff, fs->win + fp->fptr % SS(fs), rcnt); /* Extract partial sector */
-#else
- mem_cpy(rbuff, fp->buf + fp->fptr % SS(fs), rcnt); /* Extract partial sector */
-#endif
- }
-
- LEAVE_FF(fs, FR_OK);
-}
-
-
-
-
-#if !FF_FS_READONLY
-/*-----------------------------------------------------------------------*/
-/* Write File */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_write (
- FIL* fp, /* Pointer to the file object */
- const void* buff, /* Pointer to the data to be written */
- UINT btw, /* Number of bytes to write */
- UINT* bw /* Pointer to number of bytes written */
-)
-{
- FRESULT res = FR_DISK_ERR;
- FATFS *fs;
- DWORD clst, sect;
- UINT wcnt, cc, csect;
- const BYTE *wbuff = (const BYTE*)buff;
-
-
- *bw = 0; /* Clear write byte counter */
- res = validate(&fp->obj, &fs); /* Check validity of the file object */
- if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */
- if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */
-
- /* Check fptr wrap-around (file size cannot reach 4 GiB at FAT volume) */
- if ((!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) && (DWORD)(fp->fptr + btw) < (DWORD)fp->fptr) {
- btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr);
- }
-
- for ( ; btw; /* Repeat until all data written */
- btw -= wcnt, *bw += wcnt, wbuff += wcnt, fp->fptr += wcnt, fp->obj.objsize = (fp->fptr > fp->obj.objsize) ? fp->fptr : fp->obj.objsize) {
- if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */
- csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1); /* Sector offset in the cluster */
- if (csect == 0) { /* On the cluster boundary? */
- if (fp->fptr == 0) { /* On the top of the file? */
- clst = fp->obj.sclust; /* Follow from the origin */
- if (clst == 0) { /* If no cluster is allocated, */
- clst = create_chain(&fp->obj, 0); /* create a new cluster chain */
- }
- } else { /* On the middle or end of the file */
-#if FF_USE_FASTSEEK
- if (fp->cltbl) {
- clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */
- } else
-#endif
- {
- clst = create_chain(&fp->obj, fp->clust); /* Follow or stretch cluster chain on the FAT */
- }
- }
- if (clst == 0) break; /* Could not allocate a new cluster (disk full) */
- if (clst == 1) ABORT(fs, FR_INT_ERR);
- if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
- fp->clust = clst; /* Update current cluster */
- if (fp->obj.sclust == 0) fp->obj.sclust = clst; /* Set start cluster if the first write */
- }
-#if FF_FS_TINY
- if (fs->winsect == fp->sect && sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Write-back sector cache */
-#else
- if (fp->flag & FA_DIRTY) { /* Write-back sector cache */
- if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
- fp->flag &= (BYTE)~FA_DIRTY;
- }
-#endif
- sect = clst2sect(fs, fp->clust); /* Get current sector */
- if (sect == 0) ABORT(fs, FR_INT_ERR);
- sect += csect;
- cc = btw / SS(fs); /* When remaining bytes >= sector size, */
- if (cc > 0) { /* Write maximum contiguous sectors directly */
- if (csect + cc > fs->csize) { /* Clip at cluster boundary */
- cc = fs->csize - csect;
- }
- if (disk_write(fs->pdrv, wbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR);
-#if FF_FS_MINIMIZE <= 2
-#if FF_FS_TINY
- if (fs->winsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */
- mem_cpy(fs->win, wbuff + ((fs->winsect - sect) * SS(fs)), SS(fs));
- fs->wflag = 0;
- }
-#else
- if (fp->sect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */
- mem_cpy(fp->buf, wbuff + ((fp->sect - sect) * SS(fs)), SS(fs));
- fp->flag &= (BYTE)~FA_DIRTY;
- }
-#endif
-#endif
- wcnt = SS(fs) * cc; /* Number of bytes transferred */
- continue;
- }
-#if FF_FS_TINY
- if (fp->fptr >= fp->obj.objsize) { /* Avoid silly cache filling on the growing edge */
- if (sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR);
- fs->winsect = sect;
- }
-#else
- if (fp->sect != sect && /* Fill sector cache with file data */
- fp->fptr < fp->obj.objsize &&
- disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) {
- ABORT(fs, FR_DISK_ERR);
- }
-#endif
- fp->sect = sect;
- }
- wcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes left in the sector */
- if (wcnt > btw) wcnt = btw; /* Clip it by btw if needed */
-#if FF_FS_TINY
- if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window */
- mem_cpy(fs->win + fp->fptr % SS(fs), wbuff, wcnt); /* Fit data to the sector */
- fs->wflag = 1;
-#else
- mem_cpy(fp->buf + fp->fptr % SS(fs), wbuff, wcnt); /* Fit data to the sector */
- fp->flag |= FA_DIRTY;
-#endif
- }
-
- fp->flag |= FA_MODIFIED; /* Set file change flag */
-
- LEAVE_FF(fs, FR_OK);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Synchronize the File */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_sync (
- FIL* fp /* Pointer to the file object */
-)
-{
- FRESULT res = FR_DISK_ERR;
- FATFS *fs;
- DWORD tm;
- BYTE *dir;
-
-
- res = validate(&fp->obj, &fs); /* Check validity of the file object */
- if (res == FR_OK) {
- if (fp->flag & FA_MODIFIED) { /* Is there any change to the file? */
-#if !FF_FS_TINY
- if (fp->flag & FA_DIRTY) { /* Write-back cached data if needed */
- if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) LEAVE_FF(fs, FR_DISK_ERR);
- fp->flag &= (BYTE)~FA_DIRTY;
- }
-#endif
- /* Update the directory entry */
- tm = GET_FATTIME(); /* Modified time */
-#if FF_FS_EXFAT
- if (fs->fs_type == FS_EXFAT) {
- res = fill_first_frag(&fp->obj); /* Fill first fragment on the FAT if needed */
- if (res == FR_OK) {
- res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF); /* Fill last fragment on the FAT if needed */
- }
- if (res == FR_OK) {
- DIR dj;
- DEF_NAMBUF
-
- INIT_NAMBUF(fs);
- res = load_obj_xdir(&dj, &fp->obj); /* Load directory entry block */
- if (res == FR_OK) {
- fs->dirbuf[XDIR_Attr] |= AM_ARC; /* Set archive attribute to indicate that the file has been changed */
- fs->dirbuf[XDIR_GenFlags] = fp->obj.stat | 1; /* Update file allocation information */
- st_dword(fs->dirbuf + XDIR_FstClus, fp->obj.sclust);
- st_qword(fs->dirbuf + XDIR_FileSize, fp->obj.objsize);
- st_qword(fs->dirbuf + XDIR_ValidFileSize, fp->obj.objsize);
- st_dword(fs->dirbuf + XDIR_ModTime, tm); /* Update modified time */
- fs->dirbuf[XDIR_ModTime10] = 0;
- st_dword(fs->dirbuf + XDIR_AccTime, 0);
- res = store_xdir(&dj); /* Restore it to the directory */
- if (res == FR_OK) {
- res = sync_fs(fs);
- fp->flag &= (BYTE)~FA_MODIFIED;
- }
- }
- FREE_NAMBUF();
- }
- } else
-#endif
- {
- res = move_window(fs, fp->dir_sect);
- if (res == FR_OK) {
- dir = fp->dir_ptr;
- dir[DIR_Attr] |= AM_ARC; /* Set archive attribute to indicate that the file has been changed */
- st_clust(fp->obj.fs, dir, fp->obj.sclust); /* Update file allocation information */
- st_dword(dir + DIR_FileSize, (DWORD)fp->obj.objsize); /* Update file size */
- st_dword(dir + DIR_ModTime, tm); /* Update modified time */
- st_word(dir + DIR_LstAccDate, 0);
- fs->wflag = 1;
- res = sync_fs(fs); /* Restore it to the directory */
- fp->flag &= (BYTE)~FA_MODIFIED;
- }
- }
- }
- }
-
- LEAVE_FF(fs, res);
-}
-
-#endif /* !FF_FS_READONLY */
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Close File */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_close (
- FIL* fp /* Pointer to the file object to be closed */
-)
-{
- FRESULT res = FR_DISK_ERR;
- FATFS *fs;
-
-#if !FF_FS_READONLY
- res = f_sync(fp); /* Flush cached data */
- if (res == FR_OK)
-#endif
- {
- res = validate(&fp->obj, &fs); /* Lock volume */
- if (res == FR_OK) {
-#if FF_FS_LOCK != 0
- res = dec_lock(fp->obj.lockid); /* Decrement file open counter */
- if (res == FR_OK) fp->obj.fs = 0; /* Invalidate file object */
-#else
- fp->obj.fs = 0; /* Invalidate file object */
-#endif
-#if FF_FS_REENTRANT
- unlock_fs(fs, FR_OK); /* Unlock volume */
-#endif
- }
- }
- return res;
-}
-
-
-
-
-#if FF_FS_RPATH >= 1
-/*-----------------------------------------------------------------------*/
-/* Change Current Directory or Current Drive, Get Current Directory */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_chdrive (
- const TCHAR* path /* Drive number to set */
-)
-{
- int vol;
-
-
- /* Get logical drive number */
- vol = get_ldnumber(&path);
- if (vol < 0) return FR_INVALID_DRIVE;
- CurrVol = (BYTE)vol; /* Set it as current volume */
-
- return FR_OK;
-}
-
-
-
-FRESULT f_chdir (
- const TCHAR* path /* Pointer to the directory path */
-)
-{
-#if FF_STR_VOLUME_ID == 2
- UINT i;
-#endif
- FRESULT res = FR_DISK_ERR;
- DIR dj;
- FATFS *fs;
- DEF_NAMBUF
-
-
- /* Get logical drive */
- res = find_volume(&path, &fs, 0);
- if (res == FR_OK) {
- dj.obj.fs = fs;
- INIT_NAMBUF(fs);
- res = follow_path(&dj, path); /* Follow the path */
- if (res == FR_OK) { /* Follow completed */
- if (dj.fn[NSFLAG] & NS_NONAME) { /* Is it the start directory itself? */
- fs->cdir = dj.obj.sclust;
-#if FF_FS_EXFAT
- if (fs->fs_type == FS_EXFAT) {
- fs->cdc_scl = dj.obj.c_scl;
- fs->cdc_size = dj.obj.c_size;
- fs->cdc_ofs = dj.obj.c_ofs;
- }
-#endif
- } else {
- if (dj.obj.attr & AM_DIR) { /* It is a sub-directory */
-#if FF_FS_EXFAT
- if (fs->fs_type == FS_EXFAT) {
- fs->cdir = ld_dword(fs->dirbuf + XDIR_FstClus); /* Sub-directory cluster */
- fs->cdc_scl = dj.obj.sclust; /* Save containing directory information */
- fs->cdc_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat;
- fs->cdc_ofs = dj.blk_ofs;
- } else
-#endif
- {
- fs->cdir = ld_clust(fs, dj.dir); /* Sub-directory cluster */
- }
- } else {
- res = FR_NO_PATH; /* Reached but a file */
- }
- }
- }
- FREE_NAMBUF();
- if (res == FR_NO_FILE) res = FR_NO_PATH;
-#if FF_STR_VOLUME_ID == 2 /* Also current drive is changed at Unix style volume ID */
- if (res == FR_OK) {
- for (i = FF_VOLUMES - 1; i && fs != FatFs[i]; i--) ; /* Set current drive */
- CurrVol = (BYTE)i;
- }
-#endif
- }
-
- LEAVE_FF(fs, res);
-}
-
-
-#if FF_FS_RPATH >= 2
-FRESULT f_getcwd (
- TCHAR* buff, /* Pointer to the directory path */
- UINT len /* Size of buff in unit of TCHAR */
-)
-{
- FRESULT res = FR_DISK_ERR;
- DIR dj;
- FATFS *fs;
- UINT i, n;
- DWORD ccl;
- TCHAR *tp = buff;
-#if FF_VOLUMES >= 2
- UINT vl;
-#endif
-#if FF_STR_VOLUME_ID
- const char *vp;
-#endif
- FILINFO fno;
- DEF_NAMBUF
-
-
- /* Get logical drive */
- buff[0] = 0; /* Set null string to get current volume */
- res = find_volume((const TCHAR**)&buff, &fs, 0); /* Get current volume */
- if (res == FR_OK) {
- dj.obj.fs = fs;
- INIT_NAMBUF(fs);
-
- /* Follow parent directories and create the path */
- i = len; /* Bottom of buffer (directory stack base) */
- if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) { /* (Cannot do getcwd on exFAT and returns root path) */
- dj.obj.sclust = fs->cdir; /* Start to follow upper directory from current directory */
- while ((ccl = dj.obj.sclust) != 0) { /* Repeat while current directory is a sub-directory */
- res = dir_sdi(&dj, 1 * SZDIRE); /* Get parent directory */
- if (res != FR_OK) break;
- res = move_window(fs, dj.sect);
- if (res != FR_OK) break;
- dj.obj.sclust = ld_clust(fs, dj.dir); /* Goto parent directory */
- res = dir_sdi(&dj, 0);
- if (res != FR_OK) break;
- do { /* Find the entry links to the child directory */
- res = dir_read_file(&dj);
- if (res != FR_OK) break;
- if (ccl == ld_clust(fs, dj.dir)) break; /* Found the entry */
- res = dir_next(&dj, 0);
- } while (res == FR_OK);
- if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */
- if (res != FR_OK) break;
- get_fileinfo(&dj, &fno); /* Get the directory name and push it to the buffer */
- for (n = 0; fno.fname[n]; n++) ; /* Name length */
- if (i < n + 1) { /* Insufficient space to store the path name? */
- res = FR_NOT_ENOUGH_CORE; break;
- }
- while (n) buff[--i] = fno.fname[--n]; /* Stack the name */
- buff[--i] = '/';
- }
- }
- if (res == FR_OK) {
- if (i == len) buff[--i] = '/'; /* Is it the root-directory? */
-#if FF_VOLUMES >= 2 /* Put drive prefix */
- vl = 0;
-#if FF_STR_VOLUME_ID >= 1 /* String volume ID */
- for (n = 0, vp = (const char*)VolumeStr[CurrVol]; vp[n]; n++) ;
- if (i >= n + 2) {
- if (FF_STR_VOLUME_ID == 2) *tp++ = (TCHAR)'/';
- for (vl = 0; vl < n; *tp++ = (TCHAR)vp[vl], vl++) ;
- if (FF_STR_VOLUME_ID == 1) *tp++ = (TCHAR)':';
- vl++;
- }
-#else /* Numeric volume ID */
- if (i >= 3) {
- *tp++ = (TCHAR)'0' + CurrVol;
- *tp++ = (TCHAR)':';
- vl = 2;
- }
-#endif
- if (vl == 0) res = FR_NOT_ENOUGH_CORE;
-#endif
- /* Add current directory path */
- if (res == FR_OK) {
- do *tp++ = buff[i++]; while (i < len); /* Copy stacked path string */
- }
- }
- FREE_NAMBUF();
- }
-
- *tp = 0;
- LEAVE_FF(fs, res);
-}
-
-#endif /* FF_FS_RPATH >= 2 */
-#endif /* FF_FS_RPATH >= 1 */
-
-
-
-#if FF_FS_MINIMIZE <= 2
-/*-----------------------------------------------------------------------*/
-/* Seek File Read/Write Pointer */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_lseek (
- FIL* fp, /* Pointer to the file object */
- FSIZE_t ofs /* File pointer from top of file */
-)
-{
- FRESULT res = FR_DISK_ERR;
- FATFS *fs;
- DWORD clst, bcs, nsect;
- FSIZE_t ifptr;
-#if FF_USE_FASTSEEK
- DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl;
-#endif
-
- res = validate(&fp->obj, &fs); /* Check validity of the file object */
- if (res == FR_OK) res = (FRESULT)fp->err;
-#if FF_FS_EXFAT && !FF_FS_READONLY
- if (res == FR_OK && fs->fs_type == FS_EXFAT) {
- res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF); /* Fill last fragment on the FAT if needed */
- }
-#endif
- if (res != FR_OK) LEAVE_FF(fs, res);
-
-#if FF_USE_FASTSEEK
- if (fp->cltbl) { /* Fast seek */
- if (ofs == CREATE_LINKMAP) { /* Create CLMT */
- tbl = fp->cltbl;
- tlen = *tbl++; ulen = 2; /* Given table size and required table size */
- cl = fp->obj.sclust; /* Origin of the chain */
- if (cl != 0) {
- do {
- /* Get a fragment */
- tcl = cl; ncl = 0; ulen += 2; /* Top, length and used items */
- do {
- pcl = cl; ncl++;
- cl = get_fat(&fp->obj, cl);
- if (cl <= 1) ABORT(fs, FR_INT_ERR);
- if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
- } while (cl == pcl + 1);
- if (ulen <= tlen) { /* Store the length and top of the fragment */
- *tbl++ = ncl; *tbl++ = tcl;
- }
- } while (cl < fs->n_fatent); /* Repeat until end of chain */
- }
- *fp->cltbl = ulen; /* Number of items used */
- if (ulen <= tlen) {
- *tbl = 0; /* Terminate table */
- } else {
- res = FR_NOT_ENOUGH_CORE; /* Given table size is smaller than required */
- }
- } else { /* Fast seek */
- if (ofs > fp->obj.objsize) ofs = fp->obj.objsize; /* Clip offset at the file size */
- fp->fptr = ofs; /* Set file pointer */
- if (ofs > 0) {
- fp->clust = clmt_clust(fp, ofs - 1);
- dsc = clst2sect(fs, fp->clust);
- if (dsc == 0) ABORT(fs, FR_INT_ERR);
- dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1);
- if (fp->fptr % SS(fs) && dsc != fp->sect) { /* Refill sector cache if needed */
-#if !FF_FS_TINY
-#if !FF_FS_READONLY
- if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */
- if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
- fp->flag &= (BYTE)~FA_DIRTY;
- }
-#endif
- if (disk_read(fs->pdrv, fp->buf, dsc, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Load current sector */
-#endif
- fp->sect = dsc;
- }
- }
- }
- } else
-#endif
-
- /* Normal Seek */
- {
-#if FF_FS_EXFAT
- if (fs->fs_type != FS_EXFAT && ofs >= 0x100000000) ofs = 0xFFFFFFFF; /* Clip at 4 GiB - 1 if at FATxx */
-#endif
- if (ofs > fp->obj.objsize && (FF_FS_READONLY || !(fp->flag & FA_WRITE))) { /* In read-only mode, clip offset with the file size */
- ofs = fp->obj.objsize;
- }
- ifptr = fp->fptr;
- fp->fptr = nsect = 0;
- if (ofs > 0) {
- bcs = (DWORD)fs->csize * SS(fs); /* Cluster size (byte) */
- if (ifptr > 0 &&
- (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */
- fp->fptr = (ifptr - 1) & ~(FSIZE_t)(bcs - 1); /* start from the current cluster */
- ofs -= fp->fptr;
- clst = fp->clust;
- } else { /* When seek to back cluster, */
- clst = fp->obj.sclust; /* start from the first cluster */
-#if !FF_FS_READONLY
- if (clst == 0) { /* If no cluster chain, create a new chain */
- clst = create_chain(&fp->obj, 0);
- if (clst == 1) ABORT(fs, FR_INT_ERR);
- if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
- fp->obj.sclust = clst;
- }
-#endif
- fp->clust = clst;
- }
- if (clst != 0) {
- while (ofs > bcs) { /* Cluster following loop */
- ofs -= bcs; fp->fptr += bcs;
-#if !FF_FS_READONLY
- if (fp->flag & FA_WRITE) { /* Check if in write mode or not */
- if (FF_FS_EXFAT && fp->fptr > fp->obj.objsize) { /* No FAT chain object needs correct objsize to generate FAT value */
- fp->obj.objsize = fp->fptr;
- fp->flag |= FA_MODIFIED;
- }
- clst = create_chain(&fp->obj, clst); /* Follow chain with forceed stretch */
- if (clst == 0) { /* Clip file size in case of disk full */
- ofs = 0; break;
- }
- } else
-#endif
- {
- clst = get_fat(&fp->obj, clst); /* Follow cluster chain if not in write mode */
- }
- if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
- if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR);
- fp->clust = clst;
- }
- fp->fptr += ofs;
- if (ofs % SS(fs)) {
- nsect = clst2sect(fs, clst); /* Current sector */
- if (nsect == 0) ABORT(fs, FR_INT_ERR);
- nsect += (DWORD)(ofs / SS(fs));
- }
- }
- }
- if (!FF_FS_READONLY && fp->fptr > fp->obj.objsize) { /* Set file change flag if the file size is extended */
- fp->obj.objsize = fp->fptr;
- fp->flag |= FA_MODIFIED;
- }
- if (fp->fptr % SS(fs) && nsect != fp->sect) { /* Fill sector cache if needed */
-#if !FF_FS_TINY
-#if !FF_FS_READONLY
- if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */
- if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
- fp->flag &= (BYTE)~FA_DIRTY;
- }
-#endif
- if (disk_read(fs->pdrv, fp->buf, nsect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR); /* Fill sector cache */
-#endif
- fp->sect = nsect;
- }
- }
-
- LEAVE_FF(fs, res);
-}
-
-
-
-#if FF_FS_MINIMIZE <= 1
-/*-----------------------------------------------------------------------*/
-/* Create a Directory Object */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_opendir (
- DIR* dp, /* Pointer to directory object to create */
- const TCHAR* path /* Pointer to the directory path */
-)
-{
- FRESULT res = FR_DISK_ERR;
- FATFS *fs;
- DEF_NAMBUF
-
-
- if (!dp) return FR_INVALID_OBJECT;
-
- /* Get logical drive */
- res = find_volume(&path, &fs, 0);
- if (res == FR_OK) {
- dp->obj.fs = fs;
- INIT_NAMBUF(fs);
- res = follow_path(dp, path); /* Follow the path to the directory */
- if (res == FR_OK) { /* Follow completed */
- if (!(dp->fn[NSFLAG] & NS_NONAME)) { /* It is not the origin directory itself */
- if (dp->obj.attr & AM_DIR) { /* This object is a sub-directory */
-#if FF_FS_EXFAT
- if (fs->fs_type == FS_EXFAT) {
- dp->obj.c_scl = dp->obj.sclust; /* Get containing directory inforamation */
- dp->obj.c_size = ((DWORD)dp->obj.objsize & 0xFFFFFF00) | dp->obj.stat;
- dp->obj.c_ofs = dp->blk_ofs;
- init_alloc_info(fs, &dp->obj); /* Get object allocation info */
- } else
-#endif
- {
- dp->obj.sclust = ld_clust(fs, dp->dir); /* Get object allocation info */
- }
- } else { /* This object is a file */
- res = FR_NO_PATH;
- }
- }
- if (res == FR_OK) {
- dp->obj.id = fs->id;
- res = dir_sdi(dp, 0); /* Rewind directory */
-#if FF_FS_LOCK != 0
- if (res == FR_OK) {
- if (dp->obj.sclust != 0) {
- dp->obj.lockid = inc_lock(dp, 0); /* Lock the sub directory */
- if (!dp->obj.lockid) res = FR_TOO_MANY_OPEN_FILES;
- } else {
- dp->obj.lockid = 0; /* Root directory need not to be locked */
- }
- }
-#endif
- }
- }
- FREE_NAMBUF();
- if (res == FR_NO_FILE) res = FR_NO_PATH;
- }
- if (res != FR_OK) dp->obj.fs = 0; /* Invalidate the directory object if function failed */
-
- LEAVE_FF(fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Close Directory */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_closedir (
- DIR *dp /* Pointer to the directory object to be closed */
-)
-{
- FRESULT res = FR_DISK_ERR;
- FATFS *fs;
-
-
- res = validate(&dp->obj, &fs); /* Check validity of the file object */
- if (res == FR_OK) {
-#if FF_FS_LOCK != 0
- if (dp->obj.lockid) res = dec_lock(dp->obj.lockid); /* Decrement sub-directory open counter */
- if (res == FR_OK) dp->obj.fs = 0; /* Invalidate directory object */
-#else
- dp->obj.fs = 0; /* Invalidate directory object */
-#endif
-#if FF_FS_REENTRANT
- unlock_fs(fs, FR_OK); /* Unlock volume */
-#endif
- }
- return res;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Read Directory Entries in Sequence */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_readdir (
- DIR* dp, /* Pointer to the open directory object */
- FILINFO* fno /* Pointer to file information to return */
-)
-{
- FRESULT res = FR_DISK_ERR;
- FATFS *fs;
- DEF_NAMBUF
-
-
- res = validate(&dp->obj, &fs); /* Check validity of the directory object */
- if (res == FR_OK) {
- if (!fno) {
- res = dir_sdi(dp, 0); /* Rewind the directory object */
- } else {
- INIT_NAMBUF(fs);
- res = dir_read_file(dp); /* Read an item */
- if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory */
- if (res == FR_OK) { /* A valid entry is found */
- get_fileinfo(dp, fno); /* Get the object information */
- res = dir_next(dp, 0); /* Increment index for next */
- if (res == FR_NO_FILE) res = FR_OK; /* Ignore end of directory now */
- }
- FREE_NAMBUF();
- }
- }
- LEAVE_FF(fs, res);
-}
-
-
-
-#if FF_USE_FIND
-/*-----------------------------------------------------------------------*/
-/* Find Next File */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_findnext (
- DIR* dp, /* Pointer to the open directory object */
- FILINFO* fno /* Pointer to the file information structure */
-)
-{
- FRESULT res = FR_DISK_ERR;
-
-
- for (;;) {
- res = f_readdir(dp, fno); /* Get a directory item */
- if (res != FR_OK || !fno || !fno->fname[0]) break; /* Terminate if any error or end of directory */
- if (pattern_matching(dp->pat, fno->fname, 0, 0)) break; /* Test for the file name */
-#if FF_USE_LFN && FF_USE_FIND == 2
- if (pattern_matching(dp->pat, fno->altname, 0, 0)) break; /* Test for alternative name if exist */
-#endif
- }
- return res;
-}
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Find First File */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_findfirst (
- DIR* dp, /* Pointer to the blank directory object */
- FILINFO* fno, /* Pointer to the file information structure */
- const TCHAR* path, /* Pointer to the directory to open */
- const TCHAR* pattern /* Pointer to the matching pattern */
-)
-{
- FRESULT res = FR_DISK_ERR;
-
-
- dp->pat = pattern; /* Save pointer to pattern string */
- res = f_opendir(dp, path); /* Open the target directory */
- if (res == FR_OK) {
- res = f_findnext(dp, fno); /* Find the first item */
- }
- return res;
-}
-
-#endif /* FF_USE_FIND */
-
-
-
-#if FF_FS_MINIMIZE == 0
-/*-----------------------------------------------------------------------*/
-/* Get File Status */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_stat (
- const TCHAR* path, /* Pointer to the file path */
- FILINFO* fno /* Pointer to file information to return */
-)
-{
- FRESULT res = FR_DISK_ERR;
- DIR dj = {0};
- DEF_NAMBUF
-
-
- /* Get logical drive */
- res = find_volume(&path, &dj.obj.fs, 0);
- if (res == FR_OK) {
- INIT_NAMBUF(dj.obj.fs);
- res = follow_path(&dj, path); /* Follow the file path */
- if (res == FR_OK) { /* Follow completed */
- if (dj.fn[NSFLAG] & NS_NONAME) { /* It is origin directory */
- res = FR_INVALID_NAME;
- } else { /* Found an object */
- if (fno) get_fileinfo(&dj, fno);
- }
- }
- FREE_NAMBUF();
- }
-
- LEAVE_FF(dj.obj.fs, res);
-}
-
-
-
-#if !FF_FS_READONLY
-/*-----------------------------------------------------------------------*/
-/* Get Number of Free Clusters */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_getfree (
- const TCHAR* path, /* Logical drive number */
- DWORD* nclst, /* Pointer to a variable to return number of free clusters */
- FATFS** fatfs /* Pointer to return pointer to corresponding filesystem object */
-)
-{
- FRESULT res = FR_DISK_ERR;
- FATFS *fs;
- DWORD nfree, clst, sect, stat;
- UINT i;
- FFOBJID obj;
-
-
- /* Get logical drive */
- res = find_volume(&path, &fs, 0);
- if (res == FR_OK) {
- *fatfs = fs; /* Return ptr to the fs object */
- /* If free_clst is valid, return it without full FAT scan */
- if (fs->free_clst <= fs->n_fatent - 2) {
- *nclst = fs->free_clst;
- } else {
- /* Scan FAT to obtain number of free clusters */
- nfree = 0;
- if (fs->fs_type == FS_FAT12) { /* FAT12: Scan bit field FAT entries */
- clst = 2; obj.fs = fs;
- do {
- stat = get_fat(&obj, clst);
- if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }
- if (stat == 1) { res = FR_INT_ERR; break; }
- if (stat == 0) nfree++;
- } while (++clst < fs->n_fatent);
- } else {
-#if FF_FS_EXFAT
- if (fs->fs_type == FS_EXFAT) { /* exFAT: Scan allocation bitmap */
- BYTE bm;
- UINT b;
-
- clst = fs->n_fatent - 2; /* Number of clusters */
- sect = fs->database; /* Assuming bitmap starts at cluster 2 */
- i = 0; /* Offset in the sector */
- do { /* Counts numbuer of bits with zero in the bitmap */
- if (i == 0) {
- res = move_window(fs, sect++);
- if (res != FR_OK) break;
- }
- for (b = 8, bm = fs->win[i]; b && clst; b--, clst--) {
- if (!(bm & 1)) nfree++;
- bm >>= 1;
- }
- i = (i + 1) % SS(fs);
- } while (clst);
- } else
-#endif
- { /* FAT16/32: Scan WORD/DWORD FAT entries */
- clst = fs->n_fatent; /* Number of entries */
- sect = fs->fatbase; /* Top of the FAT */
- i = 0; /* Offset in the sector */
- do { /* Counts numbuer of entries with zero in the FAT */
- if (i == 0) {
- res = move_window(fs, sect++);
- if (res != FR_OK) break;
- }
- if (fs->fs_type == FS_FAT16) {
- if (ld_word(fs->win + i) == 0) nfree++;
- i += 2;
- } else {
- if ((ld_dword(fs->win + i) & 0x0FFFFFFF) == 0) nfree++;
- i += 4;
- }
- i %= SS(fs);
- } while (--clst);
- }
- }
- *nclst = nfree; /* Return the free clusters */
- fs->free_clst = nfree; /* Now free_clst is valid */
- fs->fsi_flag |= 1; /* FAT32: FSInfo is to be updated */
- }
- }
-
- LEAVE_FF(fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Truncate File */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_truncate (
- FIL* fp /* Pointer to the file object */
-)
-{
- FRESULT res = FR_DISK_ERR;
- FATFS *fs;
- DWORD ncl;
-
-
- res = validate(&fp->obj, &fs); /* Check validity of the file object */
- if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
- if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */
-
- if (fp->fptr < fp->obj.objsize) { /* Process when fptr is not on the eof */
- if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */
- res = remove_chain(&fp->obj, fp->obj.sclust, 0);
- fp->obj.sclust = 0;
- } else { /* When truncate a part of the file, remove remaining clusters */
- ncl = get_fat(&fp->obj, fp->clust);
- res = FR_OK;
- if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR;
- if (ncl == 1) res = FR_INT_ERR;
- if (res == FR_OK && ncl < fs->n_fatent) {
- res = remove_chain(&fp->obj, ncl, fp->clust);
- }
- }
- fp->obj.objsize = fp->fptr; /* Set file size to current read/write point */
- fp->flag |= FA_MODIFIED;
-#if !FF_FS_TINY
- if (res == FR_OK && (fp->flag & FA_DIRTY)) {
- if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) {
- res = FR_DISK_ERR;
- } else {
- fp->flag &= (BYTE)~FA_DIRTY;
- }
- }
-#endif
- if (res != FR_OK) ABORT(fs, res);
- }
-
- LEAVE_FF(fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Delete a File/Directory */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_unlink (
- const TCHAR* path /* Pointer to the file or directory path */
-)
-{
- FRESULT res = FR_DISK_ERR;
- DIR dj, sdj;
- DWORD dclst = 0;
- FATFS *fs;
-#if FF_FS_EXFAT
- FFOBJID obj;
-#endif
- DEF_NAMBUF
-
-
- /* Get logical drive */
- res = find_volume(&path, &fs, FA_WRITE);
- if (res == FR_OK) {
- dj.obj.fs = fs;
- INIT_NAMBUF(fs);
- res = follow_path(&dj, path); /* Follow the file path */
- if (FF_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT)) {
- res = FR_INVALID_NAME; /* Cannot remove dot entry */
- }
-#if FF_FS_LOCK != 0
- if (res == FR_OK) res = chk_lock(&dj, 2); /* Check if it is an open object */
-#endif
- if (res == FR_OK) { /* The object is accessible */
- if (dj.fn[NSFLAG] & NS_NONAME) {
- res = FR_INVALID_NAME; /* Cannot remove the origin directory */
- } else {
- if (dj.obj.attr & AM_RDO) {
- res = FR_DENIED; /* Cannot remove R/O object */
- }
- }
- if (res == FR_OK) {
-#if FF_FS_EXFAT
- obj.fs = fs;
- if (fs->fs_type == FS_EXFAT) {
- init_alloc_info(fs, &obj);
- dclst = obj.sclust;
- } else
-#endif
- {
- dclst = ld_clust(fs, dj.dir);
- }
- if (dj.obj.attr & AM_DIR) { /* Is it a sub-directory? */
-#if FF_FS_RPATH != 0
- if (dclst == fs->cdir) { /* Is it the current directory? */
- res = FR_DENIED;
- } else
-#endif
- {
- sdj.obj.fs = fs; /* Open the sub-directory */
- sdj.obj.sclust = dclst;
-#if FF_FS_EXFAT
- if (fs->fs_type == FS_EXFAT) {
- sdj.obj.objsize = obj.objsize;
- sdj.obj.stat = obj.stat;
- }
-#endif
- res = dir_sdi(&sdj, 0);
- if (res == FR_OK) {
- res = dir_read_file(&sdj); /* Test if the directory is empty */
- if (res == FR_OK) res = FR_DENIED; /* Not empty? */
- if (res == FR_NO_FILE) res = FR_OK; /* Empty? */
- }
- }
- }
- }
- if (res == FR_OK) {
- res = dir_remove(&dj); /* Remove the directory entry */
- if (res == FR_OK && dclst != 0) { /* Remove the cluster chain if exist */
-#if FF_FS_EXFAT
- res = remove_chain(&obj, dclst, 0);
-#else
- res = remove_chain(&dj.obj, dclst, 0);
-#endif
- }
- if (res == FR_OK) res = sync_fs(fs);
- }
- }
- FREE_NAMBUF();
- }
-
- LEAVE_FF(fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Create a Directory */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_mkdir (
- const TCHAR* path /* Pointer to the directory path */
-)
-{
- FRESULT res = FR_DISK_ERR;
- DIR dj;
- FFOBJID sobj;
- FATFS *fs;
- BYTE *dir;
- DWORD dcl, pcl, tm;
- DEF_NAMBUF
-
-
- /* Get logical drive */
- res = find_volume(&path, &fs, FA_WRITE);
- if (res == FR_OK) {
- dj.obj.fs = fs;
- INIT_NAMBUF(fs);
- res = follow_path(&dj, path); /* Follow the file path */
- if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */
- if (FF_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT)) {
- res = FR_INVALID_NAME;
- }
- if (res == FR_NO_FILE) { /* Can create a new directory */
- sobj.fs = fs; /* New object id to create a new chain */
- dcl = create_chain(&sobj, 0); /* Allocate a cluster for the new directory */
- res = FR_OK;
- if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster */
- if (dcl == 1) res = FR_INT_ERR;
- if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR;
- tm = GET_FATTIME();
- if (res == FR_OK) { /* Initialize the new directory table */
- res = dir_clear(fs, dcl); /* Clean up the new table */
- if (res == FR_OK && (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT)) { /* Create dot entries (FAT only) */
- dir = fs->win;
- mem_set(dir + DIR_Name, ' ', 11); /* Create "." entry */
- dir[DIR_Name] = '.';
- dir[DIR_Attr] = AM_DIR;
- st_dword(dir + DIR_ModTime, tm);
- st_clust(fs, dir, dcl);
- mem_cpy(dir + SZDIRE, dir, SZDIRE); /* Create ".." entry */
- dir[SZDIRE + 1] = '.'; pcl = dj.obj.sclust;
- st_clust(fs, dir + SZDIRE, pcl);
- fs->wflag = 1;
- }
- }
- if (res == FR_OK) {
- res = dir_register(&dj); /* Register the object to the directory */
- }
- if (res == FR_OK) {
-#if FF_FS_EXFAT
- if (fs->fs_type == FS_EXFAT) { /* Initialize directory entry block */
- st_dword(fs->dirbuf + XDIR_ModTime, tm); /* Created time */
- st_dword(fs->dirbuf + XDIR_FstClus, dcl); /* Table start cluster */
- st_dword(fs->dirbuf + XDIR_FileSize, (DWORD)fs->csize * SS(fs)); /* File size needs to be valid */
- st_dword(fs->dirbuf + XDIR_ValidFileSize, (DWORD)fs->csize * SS(fs));
- fs->dirbuf[XDIR_GenFlags] = 3; /* Initialize the object flag */
- fs->dirbuf[XDIR_Attr] = AM_DIR; /* Attribute */
- res = store_xdir(&dj);
- } else
-#endif
- {
- dir = dj.dir;
- st_dword(dir + DIR_ModTime, tm); /* Created time */
- st_clust(fs, dir, dcl); /* Table start cluster */
- dir[DIR_Attr] = AM_DIR; /* Attribute */
- fs->wflag = 1;
- }
- if (res == FR_OK) {
- res = sync_fs(fs);
- }
- } else {
- (void)remove_chain(&dj.obj, dcl, 0); /* Could not register, remove cluster chain */
- }
- }
- FREE_NAMBUF();
- }
-
- LEAVE_FF(fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Rename a File/Directory */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_rename (
- const TCHAR* path_old, /* Pointer to the object name to be renamed */
- const TCHAR* path_new /* Pointer to the new name */
-)
-{
- FRESULT res = FR_DISK_ERR;
- DIR djo, djn;
- FATFS *fs;
- BYTE buf[FF_FS_EXFAT ? SZDIRE * 2 : SZDIRE], *dir;
- DWORD dw;
- DEF_NAMBUF
-
-
- get_ldnumber(&path_new); /* Snip the drive number of new name off */
- res = find_volume(&path_old, &fs, FA_WRITE); /* Get logical drive of the old object */
- if (res == FR_OK) {
- djo.obj.fs = fs;
- INIT_NAMBUF(fs);
- res = follow_path(&djo, path_old); /* Check old object */
- if (res == FR_OK && (djo.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check validity of name */
-#if FF_FS_LOCK != 0
- if (res == FR_OK) {
- res = chk_lock(&djo, 2);
- }
-#endif
- if (res == FR_OK) { /* Object to be renamed is found */
-#if FF_FS_EXFAT
- if (fs->fs_type == FS_EXFAT) { /* At exFAT volume */
- BYTE nf, nn;
- WORD nh;
-
- mem_cpy(buf, fs->dirbuf, SZDIRE * 2); /* Save 85+C0 entry of old object */
- mem_cpy(&djn, &djo, sizeof djo);
- res = follow_path(&djn, path_new); /* Make sure if new object name is not in use */
- if (res == FR_OK) { /* Is new name already in use by any other object? */
- res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST;
- }
- if (res == FR_NO_FILE) { /* It is a valid path and no name collision */
- res = dir_register(&djn); /* Register the new entry */
- if (res == FR_OK) {
- nf = fs->dirbuf[XDIR_NumSec]; nn = fs->dirbuf[XDIR_NumName];
- nh = ld_word(fs->dirbuf + XDIR_NameHash);
- mem_cpy(fs->dirbuf, buf, SZDIRE * 2); /* Restore 85+C0 entry */
- fs->dirbuf[XDIR_NumSec] = nf; fs->dirbuf[XDIR_NumName] = nn;
- st_word(fs->dirbuf + XDIR_NameHash, nh);
- if (!(fs->dirbuf[XDIR_Attr] & AM_DIR)) fs->dirbuf[XDIR_Attr] |= AM_ARC; /* Set archive attribute if it is a file */
-/* Start of critical section where an interruption can cause a cross-link */
- res = store_xdir(&djn);
- }
- }
- } else
-#endif
- { /* At FAT/FAT32 volume */
- mem_cpy(buf, djo.dir, SZDIRE); /* Save directory entry of the object */
- mem_cpy(&djn, &djo, sizeof (DIR)); /* Duplicate the directory object */
- res = follow_path(&djn, path_new); /* Make sure if new object name is not in use */
- if (res == FR_OK) { /* Is new name already in use by any other object? */
- res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST;
- }
- if (res == FR_NO_FILE) { /* It is a valid path and no name collision */
- res = dir_register(&djn); /* Register the new entry */
- if (res == FR_OK) {
- dir = djn.dir; /* Copy directory entry of the object except name */
- mem_cpy(dir + 13, buf + 13, SZDIRE - 13);
- dir[DIR_Attr] = buf[DIR_Attr];
- if (!(dir[DIR_Attr] & AM_DIR)) dir[DIR_Attr] |= AM_ARC; /* Set archive attribute if it is a file */
- fs->wflag = 1;
- if ((dir[DIR_Attr] & AM_DIR) && djo.obj.sclust != djn.obj.sclust) { /* Update .. entry in the sub-directory if needed */
- dw = clst2sect(fs, ld_clust(fs, dir));
- if (dw == 0) {
- res = FR_INT_ERR;
- } else {
-/* Start of critical section where an interruption can cause a cross-link */
- res = move_window(fs, dw);
- dir = fs->win + SZDIRE * 1; /* Ptr to .. entry */
- if (res == FR_OK && dir[1] == '.') {
- st_clust(fs, dir, djn.obj.sclust);
- fs->wflag = 1;
- }
- }
- }
- }
- }
- }
- if (res == FR_OK) {
- res = dir_remove(&djo); /* Remove old entry */
- if (res == FR_OK) {
- res = sync_fs(fs);
- }
- }
-/* End of the critical section */
- }
- FREE_NAMBUF();
- }
-
- LEAVE_FF(fs, res);
-}
-
-#endif /* !FF_FS_READONLY */
-#endif /* FF_FS_MINIMIZE == 0 */
-#endif /* FF_FS_MINIMIZE <= 1 */
-#endif /* FF_FS_MINIMIZE <= 2 */
-
-
-
-#if FF_USE_CHMOD && !FF_FS_READONLY
-/*-----------------------------------------------------------------------*/
-/* Change Attribute */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_chmod (
- const TCHAR* path, /* Pointer to the file path */
- BYTE attr, /* Attribute bits */
- BYTE mask /* Attribute mask to change */
-)
-{
- FRESULT res = FR_DISK_ERR;
- DIR dj;
- FATFS *fs;
- DEF_NAMBUF
-
-
- res = find_volume(&path, &fs, FA_WRITE); /* Get logical drive */
- if (res == FR_OK) {
- dj.obj.fs = fs;
- INIT_NAMBUF(fs);
- res = follow_path(&dj, path); /* Follow the file path */
- if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check object validity */
- if (res == FR_OK) {
- mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */
-#if FF_FS_EXFAT
- if (fs->fs_type == FS_EXFAT) {
- fs->dirbuf[XDIR_Attr] = (attr & mask) | (fs->dirbuf[XDIR_Attr] & (BYTE)~mask); /* Apply attribute change */
- res = store_xdir(&dj);
- } else
-#endif
- {
- dj.dir[DIR_Attr] = (attr & mask) | (dj.dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */
- fs->wflag = 1;
- }
- if (res == FR_OK) {
- res = sync_fs(fs);
- }
- }
- FREE_NAMBUF();
- }
-
- LEAVE_FF(fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Change Timestamp */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_utime (
- const TCHAR* path, /* Pointer to the file/directory name */
- const FILINFO* fno /* Pointer to the timestamp to be set */
-)
-{
- FRESULT res = FR_DISK_ERR;
- DIR dj;
- FATFS *fs;
- DEF_NAMBUF
-
-
- res = find_volume(&path, &fs, FA_WRITE); /* Get logical drive */
- if (res == FR_OK) {
- dj.obj.fs = fs;
- INIT_NAMBUF(fs);
- res = follow_path(&dj, path); /* Follow the file path */
- if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME; /* Check object validity */
- if (res == FR_OK) {
-#if FF_FS_EXFAT
- if (fs->fs_type == FS_EXFAT) {
- st_dword(fs->dirbuf + XDIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime);
- res = store_xdir(&dj);
- } else
-#endif
- {
- st_dword(dj.dir + DIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime);
- fs->wflag = 1;
- }
- if (res == FR_OK) {
- res = sync_fs(fs);
- }
- }
- FREE_NAMBUF();
- }
-
- LEAVE_FF(fs, res);
-}
-
-#endif /* FF_USE_CHMOD && !FF_FS_READONLY */
-
-
-
-#if FF_USE_LABEL
-/*-----------------------------------------------------------------------*/
-/* Get Volume Label */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_getlabel (
- const TCHAR* path, /* Logical drive number */
- TCHAR* label, /* Buffer to store the volume label */
- DWORD* vsn /* Variable to store the volume serial number */
-)
-{
- FRESULT res = FR_DISK_ERR;
- DIR dj;
- FATFS *fs;
- UINT si, di;
- WCHAR wc;
-
- /* Get logical drive */
- res = find_volume(&path, &fs, 0);
-
- /* Get volume label */
- if (res == FR_OK && label) {
- dj.obj.fs = fs; dj.obj.sclust = 0; /* Open root directory */
- res = dir_sdi(&dj, 0);
- if (res == FR_OK) {
- res = dir_read_label(&dj); /* Find a volume label entry */
- if (res == FR_OK) {
-#if FF_FS_EXFAT
- if (fs->fs_type == FS_EXFAT) {
- WCHAR hs;
-
- for (si = di = hs = 0; si < dj.dir[XDIR_NumLabel]; si++) { /* Extract volume label from 83 entry */
- wc = ld_word(dj.dir + XDIR_Label + si * 2);
- if (hs == 0 && IsSurrogate(wc)) { /* Is the code a surrogate? */
- hs = wc; continue;
- }
- wc = put_utf((DWORD)hs << 16 | wc, &label[di], 4);
- if (wc == 0) { di = 0; break; }
- di += wc;
- hs = 0;
- }
- if (hs != 0) di = 0; /* Broken surrogate pair? */
- label[di] = 0;
- } else
-#endif
- {
- si = di = 0; /* Extract volume label from AM_VOL entry */
- while (si < 11) {
- wc = dj.dir[si++];
-#if FF_USE_LFN && FF_LFN_UNICODE >= 1 /* Unicode output */
- if (dbc_1st((BYTE)wc) && si < 11) wc = wc << 8 | dj.dir[si++]; /* Is it a DBC? */
- wc = ff_oem2uni(wc, CODEPAGE); /* Convert it into Unicode */
- if (wc != 0) wc = put_utf(wc, &label[di], 4); /* Put it in Unicode */
- if (wc == 0) { di = 0; break; }
- di += wc;
-#else /* ANSI/OEM output */
- label[di++] = (TCHAR)wc;
-#endif
- }
- do { /* Truncate trailing spaces */
- label[di] = 0;
- if (di == 0) break;
- } while (label[--di] == ' ');
- }
- }
- }
- if (res == FR_NO_FILE) { /* No label entry and return nul string */
- label[0] = 0;
- res = FR_OK;
- }
- }
-
- /* Get volume serial number */
- if (res == FR_OK && vsn) {
- res = move_window(fs, fs->volbase);
- if (res == FR_OK) {
- switch (fs->fs_type) {
- case FS_EXFAT:
- di = BPB_VolIDEx; break;
-
- case FS_FAT32:
- di = BS_VolID32; break;
-
- default:
- di = BS_VolID;
- }
- *vsn = ld_dword(fs->win + di);
- }
- }
-
- LEAVE_FF(fs, res);
-}
-
-
-
-#if !FF_FS_READONLY
-/*-----------------------------------------------------------------------*/
-/* Set Volume Label */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_setlabel (
- const TCHAR* label /* Volume label to set with heading logical drive number */
-)
-{
- FRESULT res = FR_DISK_ERR;
- DIR dj;
- FATFS *fs;
- BYTE dirvn[22];
- UINT di;
- WCHAR wc;
- static const char badchr[] = "+.,;=[]/\\\"*:<>\?|\x7F"; /* [0..] for FAT, [7..] for exFAT */
-#if FF_USE_LFN
- DWORD dc;
-#endif
-
- /* Get logical drive */
- res = find_volume(&label, &fs, FA_WRITE);
- if (res != FR_OK) LEAVE_FF(fs, res);
-
-#if FF_FS_EXFAT
- if (fs->fs_type == FS_EXFAT) { /* On the exFAT volume */
- mem_set(dirvn, 0, 22);
- di = 0;
- while ((UINT)*label >= ' ') { /* Create volume label */
- dc = tchar2uni(&label); /* Get a Unicode character */
- if (dc >= 0x10000) {
- if (dc == 0xFFFFFFFF || di >= 10) { /* Wrong surrogate or buffer overflow */
- dc = 0;
- } else {
- st_word(dirvn + di * 2, (WCHAR)(dc >> 16)); di++;
- }
- }
- if (dc == 0 || chk_chr(badchr + 7, (int)dc) || di >= 11) { /* Check validity of the volume label */
- LEAVE_FF(fs, FR_INVALID_NAME);
- }
- st_word(dirvn + di * 2, (WCHAR)dc); di++;
- }
- } else
-#endif
- { /* On the FAT/FAT32 volume */
- mem_set(dirvn, ' ', 11);
- di = 0;
- while ((UINT)*label >= ' ') { /* Create volume label */
-#if FF_USE_LFN
- dc = tchar2uni(&label);
- wc = (dc < 0x10000) ? ff_uni2oem(ff_wtoupper(dc), CODEPAGE) : 0;
-#else /* ANSI/OEM input */
- wc = (BYTE)*label++;
- if (dbc_1st((BYTE)wc)) wc = dbc_2nd((BYTE)*label) ? wc << 8 | (BYTE)*label++ : 0;
- if (IsLower(wc)) wc -= 0x20; /* To upper ASCII characters */
-#if FF_CODE_PAGE == 0
- if (ExCvt && wc >= 0x80) wc = ExCvt[wc - 0x80]; /* To upper extended characters (SBCS cfg) */
-#elif FF_CODE_PAGE < 900
- if (wc >= 0x80) wc = ExCvt[wc - 0x80]; /* To upper extended characters (SBCS cfg) */
-#endif
-#endif
- if (wc == 0 || chk_chr(badchr + 0, (int)wc) || di >= (UINT)((wc >= 0x100) ? 10 : 11)) { /* Reject invalid characters for volume label */
- LEAVE_FF(fs, FR_INVALID_NAME);
- }
- if (wc >= 0x100) dirvn[di++] = (BYTE)(wc >> 8);
- dirvn[di++] = (BYTE)wc;
- }
- if (dirvn[0] == DDEM) LEAVE_FF(fs, FR_INVALID_NAME); /* Reject illegal name (heading DDEM) */
- while (di && dirvn[di - 1] == ' ') di--; /* Snip trailing spaces */
- }
-
- /* Set volume label */
- dj.obj.fs = fs; dj.obj.sclust = 0; /* Open root directory */
- res = dir_sdi(&dj, 0);
- if (res == FR_OK) {
- res = dir_read_label(&dj); /* Get volume label entry */
- if (res == FR_OK) {
- if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) {
- dj.dir[XDIR_NumLabel] = (BYTE)di; /* Change the volume label */
- mem_cpy(dj.dir + XDIR_Label, dirvn, 22);
- } else {
- if (di != 0) {
- mem_cpy(dj.dir, dirvn, 11); /* Change the volume label */
- } else {
- dj.dir[DIR_Name] = DDEM; /* Remove the volume label */
- }
- }
- fs->wflag = 1;
- res = sync_fs(fs);
- } else { /* No volume label entry or an error */
- if (res == FR_NO_FILE) {
- res = FR_OK;
- if (di != 0) { /* Create a volume label entry */
- res = dir_alloc(&dj, 1); /* Allocate an entry */
- if (res == FR_OK) {
- mem_set(dj.dir, 0, SZDIRE); /* Clean the entry */
- if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) {
- dj.dir[XDIR_Type] = 0x83; /* Create 83 entry */
- dj.dir[XDIR_NumLabel] = (BYTE)di;
- mem_cpy(dj.dir + XDIR_Label, dirvn, 22);
- } else {
- dj.dir[DIR_Attr] = AM_VOL; /* Create volume label entry */
- mem_cpy(dj.dir, dirvn, 11);
- }
- fs->wflag = 1;
- res = sync_fs(fs);
- }
- }
- }
- }
- }
-
- LEAVE_FF(fs, res);
-}
-
-#endif /* !FF_FS_READONLY */
-#endif /* FF_USE_LABEL */
-
-
-
-#if FF_USE_EXPAND && !FF_FS_READONLY
-/*-----------------------------------------------------------------------*/
-/* Allocate a Contiguous Blocks to the File */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_expand (
- FIL* fp, /* Pointer to the file object */
- FSIZE_t fsz, /* File size to be expanded to */
- BYTE opt /* Operation mode 0:Find and prepare or 1:Find and allocate */
-)
-{
- FRESULT res = FR_DISK_ERR;
- FATFS *fs;
- DWORD n, clst, stcl, scl, ncl, tcl, lclst;
-
-
- res = validate(&fp->obj, &fs); /* Check validity of the file object */
- if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
- if (fsz == 0 || fp->obj.objsize != 0 || !(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);
-#if FF_FS_EXFAT
- if (fs->fs_type != FS_EXFAT && fsz >= 0x100000000) LEAVE_FF(fs, FR_DENIED); /* Check if in size limit */
-#endif
- n = (DWORD)fs->csize * SS(fs); /* Cluster size */
- tcl = (DWORD)(fsz / n) + ((fsz & (n - 1)) ? 1 : 0); /* Number of clusters required */
- stcl = fs->last_clst; lclst = 0;
- if (stcl < 2 || stcl >= fs->n_fatent) stcl = 2;
-
-#if FF_FS_EXFAT
- if (fs->fs_type == FS_EXFAT) {
- scl = find_bitmap(fs, stcl, tcl); /* Find a contiguous cluster block */
- if (scl == 0) res = FR_DENIED; /* No contiguous cluster block was found */
- if (scl == 0xFFFFFFFF) res = FR_DISK_ERR;
- if (res == FR_OK) { /* A contiguous free area is found */
- if (opt) { /* Allocate it now */
- res = change_bitmap(fs, scl, tcl, 1); /* Mark the cluster block 'in use' */
- lclst = scl + tcl - 1;
- } else { /* Set it as suggested point for next allocation */
- lclst = scl - 1;
- }
- }
- } else
-#endif
- {
- scl = clst = stcl; ncl = 0;
- for (;;) { /* Find a contiguous cluster block */
- n = get_fat(&fp->obj, clst);
- if (++clst >= fs->n_fatent) clst = 2;
- if (n == 1) { res = FR_INT_ERR; break; }
- if (n == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }
- if (n == 0) { /* Is it a free cluster? */
- if (++ncl == tcl) break; /* Break if a contiguous cluster block is found */
- } else {
- scl = clst; ncl = 0; /* Not a free cluster */
- }
- if (clst == stcl) { res = FR_DENIED; break; } /* No contiguous cluster? */
- }
- if (res == FR_OK) { /* A contiguous free area is found */
- if (opt) { /* Allocate it now */
- for (clst = scl, n = tcl; n; clst++, n--) { /* Create a cluster chain on the FAT */
- res = put_fat(fs, clst, (n == 1) ? 0xFFFFFFFF : clst + 1);
- if (res != FR_OK) break;
- lclst = clst;
- }
- } else { /* Set it as suggested point for next allocation */
- lclst = scl - 1;
- }
- }
- }
-
- if (res == FR_OK) {
- fs->last_clst = lclst; /* Set suggested start cluster to start next */
- if (opt) { /* Is it allocated now? */
- fp->obj.sclust = scl; /* Update object allocation information */
- fp->obj.objsize = fsz;
- if (FF_FS_EXFAT) fp->obj.stat = 2; /* Set status 'contiguous chain' */
- fp->flag |= FA_MODIFIED;
- if (fs->free_clst <= fs->n_fatent - 2) { /* Update FSINFO */
- fs->free_clst -= tcl;
- fs->fsi_flag |= 1;
- }
- }
- }
-
- LEAVE_FF(fs, res);
-}
-
-#endif /* FF_USE_EXPAND && !FF_FS_READONLY */
-
-
-
-#if FF_USE_FORWARD
-/*-----------------------------------------------------------------------*/
-/* Forward Data to the Stream Directly */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_forward (
- FIL* fp, /* Pointer to the file object */
- UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */
- UINT btf, /* Number of bytes to forward */
- UINT* bf /* Pointer to number of bytes forwarded */
-)
-{
- FRESULT res = FR_DISK_ERR;
- FATFS *fs;
- DWORD clst, sect;
- FSIZE_t remain;
- UINT rcnt, csect;
- BYTE *dbuf;
-
-
- *bf = 0; /* Clear transfer byte counter */
- res = validate(&fp->obj, &fs); /* Check validity of the file object */
- if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
- if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */
-
- remain = fp->obj.objsize - fp->fptr;
- if (btf > remain) btf = (UINT)remain; /* Truncate btf by remaining bytes */
-
- for ( ; btf && (*func)(0, 0); /* Repeat until all data transferred or stream goes busy */
- fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) {
- csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1)); /* Sector offset in the cluster */
- if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */
- if (csect == 0) { /* On the cluster boundary? */
- clst = (fp->fptr == 0) ? /* On the top of the file? */
- fp->obj.sclust : get_fat(&fp->obj, fp->clust);
- if (clst <= 1) ABORT(fs, FR_INT_ERR);
- if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
- fp->clust = clst; /* Update current cluster */
- }
- }
- sect = clst2sect(fs, fp->clust); /* Get current data sector */
- if (sect == 0) ABORT(fs, FR_INT_ERR);
- sect += csect;
-#if FF_FS_TINY
- if (move_window(fs, sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window to the file data */
- dbuf = fs->win;
-#else
- if (fp->sect != sect) { /* Fill sector cache with file data */
-#if !FF_FS_READONLY
- if (fp->flag & FA_DIRTY) { /* Write-back dirty sector cache */
- if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
- fp->flag &= (BYTE)~FA_DIRTY;
- }
-#endif
- if (disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
- }
- dbuf = fp->buf;
-#endif
- fp->sect = sect;
- rcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes left in the sector */
- if (rcnt > btf) rcnt = btf; /* Clip it by btr if needed */
- rcnt = (*func)(dbuf + ((UINT)fp->fptr % SS(fs)), rcnt); /* Forward the file data */
- if (rcnt == 0) ABORT(fs, FR_INT_ERR);
- }
-
- LEAVE_FF(fs, FR_OK);
-}
-#endif /* FF_USE_FORWARD */
-
-
-
-#if FF_USE_MKFS && !FF_FS_READONLY
-/*-----------------------------------------------------------------------*/
-/* Create an FAT/exFAT volume */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_mkfs (
- const TCHAR* path, /* Logical drive number */
- BYTE opt, /* Format option */
- DWORD au, /* Size of allocation unit (cluster) [byte] */
- void* work, /* Pointer to working buffer (null: use heap memory) */
- UINT len /* Size of working buffer [byte] */
-)
-{
- const UINT n_fats = 1; /* Number of FATs for FAT/FAT32 volume (1 or 2) */
- const UINT n_rootdir = 512; /* Number of root directory entries for FAT volume */
- static const WORD cst[] = {1, 4, 16, 64, 256, 512, 0}; /* Cluster size boundary for FAT volume (4Ks unit) */
- static const WORD cst32[] = {1, 2, 4, 8, 16, 32, 0}; /* Cluster size boundary for FAT32 volume (128Ks unit) */
- BYTE fmt, sys, *buf, *pte, pdrv, part;
- WORD ss; /* Sector size */
- DWORD szb_buf, sz_buf, sz_blk, n_clst, pau, sect, nsect, n;
- DWORD b_vol, b_fat, b_data; /* Base LBA for volume, fat, data */
- DWORD sz_vol, sz_rsv, sz_fat, sz_dir; /* Size for volume, fat, dir, data */
- UINT i;
- int vol;
- DSTATUS stat;
-#if FF_USE_TRIM || FF_FS_EXFAT
- DWORD tbl[3];
-#endif
-
-
- /* Check mounted drive and clear work area */
- vol = get_ldnumber(&path); /* Get target logical drive */
- if (vol < 0) return FR_INVALID_DRIVE;
- if (FatFs[vol]) FatFs[vol]->fs_type = 0; /* Clear the volume if mounted */
- pdrv = LD2PD(vol); /* Physical drive */
- part = LD2PT(vol); /* Partition (0:create as new, 1-4:get from partition table) */
-
- /* Check physical drive status */
- stat = disk_initialize(pdrv);
- if (stat & STA_NOINIT) return FR_NOT_READY;
- if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
- if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk) != RES_OK || !sz_blk || sz_blk > 32768 || (sz_blk & (sz_blk - 1))) sz_blk = 1; /* Erase block to align data area */
-#if FF_MAX_SS != FF_MIN_SS /* Get sector size of the medium if variable sector size cfg. */
- if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &ss) != RES_OK) return FR_DISK_ERR;
- if (ss > FF_MAX_SS || ss < FF_MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR;
-#else
- ss = FF_MAX_SS;
-#endif
- if ((au != 0 && au < ss) || au > 0x1000000 || (au & (au - 1))) return FR_INVALID_PARAMETER; /* Check if au is valid */
- au /= ss; /* Cluster size in unit of sector */
-
- /* Get working buffer */
-#if FF_USE_LFN == 3
- if (!work) { /* Use heap memory for working buffer */
- for (szb_buf = MAX_MALLOC, buf = 0; szb_buf >= ss && (buf = ff_memalloc(szb_buf)) == 0; szb_buf /= 2) ;
- sz_buf = szb_buf / ss; /* Size of working buffer (sector) */
- } else
-#endif
- {
- buf = (BYTE*)work; /* Working buffer */
- sz_buf = len / ss; /* Size of working buffer (sector) */
- szb_buf = sz_buf * ss; /* Size of working buffer (byte) */
- }
- if (!buf || sz_buf == 0) return FR_NOT_ENOUGH_CORE;
-
- /* Determine where the volume to be located (b_vol, sz_vol) */
- if (FF_MULTI_PARTITION && part != 0) {
- /* Get partition information from partition table in the MBR */
- if (disk_read(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Load MBR */
- if (ld_word(buf + BS_55AA) != 0xAA55) LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if MBR is valid */
- pte = buf + (MBR_Table + (part - 1) * SZ_PTE);
- if (pte[PTE_System] == 0) LEAVE_MKFS(FR_MKFS_ABORTED); /* No partition? */
- b_vol = ld_dword(pte + PTE_StLba); /* Get volume start sector */
- sz_vol = ld_dword(pte + PTE_SizLba); /* Get volume size */
- } else {
- /* Create a single-partition in this function */
- if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_vol) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
- b_vol = (opt & FM_SFD) ? 0 : 63; /* Volume start sector */
- if (sz_vol < b_vol) LEAVE_MKFS(FR_MKFS_ABORTED);
- sz_vol -= b_vol; /* Volume size */
- }
- if (sz_vol < 128) LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if volume size is >=128s */
-
- /* Pre-determine the FAT type */
- do {
- if (FF_FS_EXFAT && (opt & FM_EXFAT)) { /* exFAT possible? */
- if ((opt & FM_ANY) == FM_EXFAT || sz_vol >= 0x4000000 || au > 128) { /* exFAT only, vol >= 64Ms or au > 128s ? */
- fmt = FS_EXFAT; break;
- }
- }
- if (au > 128) LEAVE_MKFS(FR_INVALID_PARAMETER); /* Too large au for FAT/FAT32 */
- if (opt & FM_FAT32) { /* FAT32 possible? */
- if ((opt & FM_ANY) == FM_FAT32 || !(opt & FM_FAT)) { /* FAT32 only or no-FAT? */
- fmt = FS_FAT32; break;
- }
- }
- if (!(opt & FM_FAT)) LEAVE_MKFS(FR_INVALID_PARAMETER); /* no-FAT? */
- fmt = FS_FAT16;
- } while (0);
-
-#if FF_FS_EXFAT
- if (fmt == FS_EXFAT) { /* Create an exFAT volume */
- DWORD szb_bit, szb_case, sum, nb, cl;
- WCHAR ch, si;
- UINT j, st;
- BYTE b;
-
- if (sz_vol < 0x1000) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume? */
-#if FF_USE_TRIM
- tbl[0] = b_vol; tbl[1] = b_vol + sz_vol - 1; /* Inform the device the volume area may be erased */
- disk_ioctl(pdrv, CTRL_TRIM, tbl);
-#endif
- /* Determine FAT location, data location and number of clusters */
- if (au == 0) { /* au auto-selection */
- au = 8;
- if (sz_vol >= 0x80000) au = 64; /* >= 512Ks */
- if (sz_vol >= 0x4000000) au = 256; /* >= 64Ms */
- }
- b_fat = b_vol + 32; /* FAT start at offset 32 */
- sz_fat = ((sz_vol / au + 2) * 4 + ss - 1) / ss; /* Number of FAT sectors */
- b_data = (b_fat + sz_fat + sz_blk - 1) & ~(sz_blk - 1); /* Align data area to the erase block boundary */
- if (b_data >= sz_vol / 2) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume? */
- n_clst = (sz_vol - (b_data - b_vol)) / au; /* Number of clusters */
- if (n_clst <16) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too few clusters? */
- if (n_clst > MAX_EXFAT) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too many clusters? */
-
- szb_bit = (n_clst + 7) / 8; /* Size of allocation bitmap */
- tbl[0] = (szb_bit + au * ss - 1) / (au * ss); /* Number of allocation bitmap clusters */
-
- /* Create a compressed up-case table */
- sect = b_data + au * tbl[0]; /* Table start sector */
- sum = 0; /* Table checksum to be stored in the 82 entry */
- st = 0; si = 0; i = 0; j = 0; szb_case = 0;
- do {
- switch (st) {
- case 0:
- ch = (WCHAR)ff_wtoupper(si); /* Get an up-case char */
- if (ch != si) {
- si++; break; /* Store the up-case char if exist */
- }
- for (j = 1; (WCHAR)(si + j) && (WCHAR)(si + j) == ff_wtoupper((WCHAR)(si + j)); j++) ; /* Get run length of no-case block */
- if (j >= 128) {
- ch = 0xFFFF; st = 2; break; /* Compress the no-case block if run is >= 128 */
- }
- st = 1; /* Do not compress short run */
- ch = si++; /* Fill the short run */
- if (--j == 0) st = 0;
- break;
- case 1:
- ch = si++; /* Fill the short run */
- if (--j == 0) st = 0;
- break;
-
- default:
- ch = (WCHAR)j; si += (WCHAR)j; /* Number of chars to skip */
- st = 0;
- }
- sum = xsum32(buf[i + 0] = (BYTE)ch, sum); /* Put it into the write buffer */
- sum = xsum32(buf[i + 1] = (BYTE)(ch >> 8), sum);
- i += 2; szb_case += 2;
- if (si == 0 || i == szb_buf) { /* Write buffered data when buffer full or end of process */
- n = (i + ss - 1) / ss;
- if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
- sect += n; i = 0;
- }
- } while (si);
- tbl[1] = (szb_case + au * ss - 1) / (au * ss); /* Number of up-case table clusters */
- tbl[2] = 1; /* Number of root dir clusters */
-
- /* Initialize the allocation bitmap */
- sect = b_data; nsect = (szb_bit + ss - 1) / ss; /* Start of bitmap and number of sectors */
- nb = tbl[0] + tbl[1] + tbl[2]; /* Number of clusters in-use by system */
- do {
- mem_set(buf, 0, szb_buf);
- for (i = 0; nb >= 8 && i < szb_buf; buf[i++] = 0xFF, nb -= 8) ;
- for (b = 1; nb != 0 && i < szb_buf; buf[i] |= b, b <<= 1, nb--) ;
- n = (nsect > sz_buf) ? sz_buf : nsect; /* Write the buffered data */
- if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
- sect += n; nsect -= n;
- } while (nsect);
-
- /* Initialize the FAT */
- sect = b_fat; nsect = sz_fat; /* Start of FAT and number of FAT sectors */
- j = nb = cl = 0;
- do {
- mem_set(buf, 0, szb_buf); i = 0; /* Clear work area and reset write index */
- if (cl == 0) { /* Set entry 0 and 1 */
- st_dword(buf + i, 0xFFFFFFF8); i += 4; cl++;
- st_dword(buf + i, 0xFFFFFFFF); i += 4; cl++;
- }
- do { /* Create chains of bitmap, up-case and root dir */
- while (nb != 0 && i < szb_buf) { /* Create a chain */
- st_dword(buf + i, (nb > 1) ? cl + 1 : 0xFFFFFFFF);
- i += 4; cl++; nb--;
- }
- if (nb == 0 && j < 3) nb = tbl[j++]; /* Next chain */
- } while (nb != 0 && i < szb_buf);
- n = (nsect > sz_buf) ? sz_buf : nsect; /* Write the buffered data */
- if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
- sect += n; nsect -= n;
- } while (nsect);
-
- /* Initialize the root directory */
- mem_set(buf, 0, szb_buf);
- buf[SZDIRE * 0 + 0] = 0x83; /* 83 entry (volume label) */
- buf[SZDIRE * 1 + 0] = 0x81; /* 81 entry (allocation bitmap) */
- st_dword(buf + SZDIRE * 1 + 20, 2); /* cluster */
- st_dword(buf + SZDIRE * 1 + 24, szb_bit); /* size */
- buf[SZDIRE * 2 + 0] = 0x82; /* 82 entry (up-case table) */
- st_dword(buf + SZDIRE * 2 + 4, sum); /* sum */
- st_dword(buf + SZDIRE * 2 + 20, 2 + tbl[0]); /* cluster */
- st_dword(buf + SZDIRE * 2 + 24, szb_case); /* size */
- sect = b_data + au * (tbl[0] + tbl[1]); nsect = au; /* Start of the root directory and number of sectors */
- do { /* Fill root directory sectors */
- n = (nsect > sz_buf) ? sz_buf : nsect;
- if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
- mem_set(buf, 0, ss);
- sect += n; nsect -= n;
- } while (nsect);
-
- /* Create two set of the exFAT VBR blocks */
- sect = b_vol;
- for (n = 0; n < 2; n++) {
- /* Main record (+0) */
- mem_set(buf, 0, ss);
- mem_cpy(buf + BS_JmpBoot, "\xEB\x76\x90" "EXFAT ", 11); /* Boot jump code (x86), OEM name */
- st_dword(buf + BPB_VolOfsEx, b_vol); /* Volume offset in the physical drive [sector] */
- st_dword(buf + BPB_TotSecEx, sz_vol); /* Volume size [sector] */
- st_dword(buf + BPB_FatOfsEx, b_fat - b_vol); /* FAT offset [sector] */
- st_dword(buf + BPB_FatSzEx, sz_fat); /* FAT size [sector] */
- st_dword(buf + BPB_DataOfsEx, b_data - b_vol); /* Data offset [sector] */
- st_dword(buf + BPB_NumClusEx, n_clst); /* Number of clusters */
- st_dword(buf + BPB_RootClusEx, 2 + tbl[0] + tbl[1]); /* Root dir cluster # */
- st_dword(buf + BPB_VolIDEx, GET_FATTIME()); /* VSN */
- st_word(buf + BPB_FSVerEx, 0x100); /* Filesystem version (1.00) */
- for (buf[BPB_BytsPerSecEx] = 0, i = ss; i >>= 1; buf[BPB_BytsPerSecEx]++) ; /* Log2 of sector size [byte] */
- for (buf[BPB_SecPerClusEx] = 0, i = au; i >>= 1; buf[BPB_SecPerClusEx]++) ; /* Log2 of cluster size [sector] */
- buf[BPB_NumFATsEx] = 1; /* Number of FATs */
- buf[BPB_DrvNumEx] = 0x80; /* Drive number (for int13) */
- st_word(buf + BS_BootCodeEx, 0xFEEB); /* Boot code (x86) */
- st_word(buf + BS_55AA, 0xAA55); /* Signature (placed here regardless of sector size) */
- for (i = sum = 0; i < ss; i++) { /* VBR checksum */
- if (i != BPB_VolFlagEx && i != BPB_VolFlagEx + 1 && i != BPB_PercInUseEx) sum = xsum32(buf[i], sum);
- }
- if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
- /* Extended bootstrap record (+1..+8) */
- mem_set(buf, 0, ss);
- st_word(buf + ss - 2, 0xAA55); /* Signature (placed at end of sector) */
- for (j = 1; j < 9; j++) {
- for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ; /* VBR checksum */
- if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
- }
- /* OEM/Reserved record (+9..+10) */
- mem_set(buf, 0, ss);
- for ( ; j < 11; j++) {
- for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ; /* VBR checksum */
- if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
- }
- /* Sum record (+11) */
- for (i = 0; i < ss; i += 4) st_dword(buf + i, sum); /* Fill with checksum value */
- if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
- }
-
- } else
-#endif /* FF_FS_EXFAT */
- { /* Create an FAT/FAT32 volume */
- do {
- pau = au;
- /* Pre-determine number of clusters and FAT sub-type */
- if (fmt == FS_FAT32) { /* FAT32 volume */
- if (pau == 0) { /* au auto-selection */
- n = sz_vol / 0x20000; /* Volume size in unit of 128KS */
- for (i = 0, pau = 1; cst32[i] && cst32[i] <= n; i++, pau <<= 1) ; /* Get from table */
- }
- n_clst = sz_vol / pau; /* Number of clusters */
- sz_fat = (n_clst * 4 + 8 + ss - 1) / ss; /* FAT size [sector] */
- sz_rsv = 32; /* Number of reserved sectors */
- sz_dir = 0; /* No static directory */
- if (n_clst <= MAX_FAT16 || n_clst > MAX_FAT32) LEAVE_MKFS(FR_MKFS_ABORTED);
- } else { /* FAT volume */
- if (pau == 0) { /* au auto-selection */
- n = sz_vol / 0x1000; /* Volume size in unit of 4KS */
- for (i = 0, pau = 1; cst[i] && cst[i] <= n; i++, pau <<= 1) ; /* Get from table */
- }
- n_clst = sz_vol / pau;
- if (n_clst > MAX_FAT12) {
- n = n_clst * 2 + 4; /* FAT size [byte] */
- } else {
- fmt = FS_FAT12;
- n = (n_clst * 3 + 1) / 2 + 3; /* FAT size [byte] */
- }
- sz_fat = (n + ss - 1) / ss; /* FAT size [sector] */
- sz_rsv = 1; /* Number of reserved sectors */
- sz_dir = (DWORD)n_rootdir * SZDIRE / ss; /* Rootdir size [sector] */
- }
- b_fat = b_vol + sz_rsv; /* FAT base */
- b_data = b_fat + sz_fat * n_fats + sz_dir; /* Data base */
-
- /* Align data base to erase block boundary (for flash memory media) */
- n = ((b_data + sz_blk - 1) & ~(sz_blk - 1)) - b_data; /* Next nearest erase block from current data base */
- if (fmt == FS_FAT32) { /* FAT32: Move FAT base */
- sz_rsv += n; b_fat += n;
- } else { /* FAT: Expand FAT size */
- sz_fat += n / n_fats;
- }
-
- /* Determine number of clusters and final check of validity of the FAT sub-type */
- if (sz_vol < b_data + pau * 16 - b_vol) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too small volume */
- n_clst = (sz_vol - sz_rsv - sz_fat * n_fats - sz_dir) / pau;
- if (fmt == FS_FAT32) {
- if (n_clst <= MAX_FAT16) { /* Too few clusters for FAT32 */
- if (au == 0 && (au = pau / 2) != 0) continue; /* Adjust cluster size and retry */
- LEAVE_MKFS(FR_MKFS_ABORTED);
- }
- }
- if (fmt == FS_FAT16) {
- if (n_clst > MAX_FAT16) { /* Too many clusters for FAT16 */
- if (au == 0 && (pau * 2) <= 64) {
- au = pau * 2; continue; /* Adjust cluster size and retry */
- }
- if ((opt & FM_FAT32)) {
- fmt = FS_FAT32; continue; /* Switch type to FAT32 and retry */
- }
- if (au == 0 && (au = pau * 2) <= 128) continue; /* Adjust cluster size and retry */
- LEAVE_MKFS(FR_MKFS_ABORTED);
- }
- if (n_clst <= MAX_FAT12) { /* Too few clusters for FAT16 */
- if (au == 0 && (au = pau * 2) <= 128) continue; /* Adjust cluster size and retry */
- LEAVE_MKFS(FR_MKFS_ABORTED);
- }
- }
- if (fmt == FS_FAT12 && n_clst > MAX_FAT12) LEAVE_MKFS(FR_MKFS_ABORTED); /* Too many clusters for FAT12 */
-
- /* Ok, it is the valid cluster configuration */
- break;
- } while (1);
-
-#if FF_USE_TRIM
- tbl[0] = b_vol; tbl[1] = b_vol + sz_vol - 1; /* Inform the device the volume area can be erased */
- disk_ioctl(pdrv, CTRL_TRIM, tbl);
-#endif
- /* Create FAT VBR */
- mem_set(buf, 0, ss);
- mem_cpy(buf + BS_JmpBoot, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code (x86), OEM name */
- st_word(buf + BPB_BytsPerSec, ss); /* Sector size [byte] */
- buf[BPB_SecPerClus] = (BYTE)pau; /* Cluster size [sector] */
- st_word(buf + BPB_RsvdSecCnt, (WORD)sz_rsv); /* Size of reserved area */
- buf[BPB_NumFATs] = (BYTE)n_fats; /* Number of FATs */
- st_word(buf + BPB_RootEntCnt, (WORD)((fmt == FS_FAT32) ? 0 : n_rootdir)); /* Number of root directory entries */
- if (sz_vol < 0x10000) {
- st_word(buf + BPB_TotSec16, (WORD)sz_vol); /* Volume size in 16-bit LBA */
- } else {
- st_dword(buf + BPB_TotSec32, sz_vol); /* Volume size in 32-bit LBA */
- }
- buf[BPB_Media] = 0xF8; /* Media descriptor byte */
- st_word(buf + BPB_SecPerTrk, 63); /* Number of sectors per track (for int13) */
- st_word(buf + BPB_NumHeads, 255); /* Number of heads (for int13) */
- st_dword(buf + BPB_HiddSec, b_vol); /* Volume offset in the physical drive [sector] */
- if (fmt == FS_FAT32) {
- st_dword(buf + BS_VolID32, GET_FATTIME()); /* VSN */
- st_dword(buf + BPB_FATSz32, sz_fat); /* FAT size [sector] */
- st_dword(buf + BPB_RootClus32, 2); /* Root directory cluster # (2) */
- st_word(buf + BPB_FSInfo32, 1); /* Offset of FSINFO sector (VBR + 1) */
- st_word(buf + BPB_BkBootSec32, 6); /* Offset of backup VBR (VBR + 6) */
- buf[BS_DrvNum32] = 0x80; /* Drive number (for int13) */
- buf[BS_BootSig32] = 0x29; /* Extended boot signature */
- mem_cpy(buf + BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */
- } else {
- st_dword(buf + BS_VolID, GET_FATTIME()); /* VSN */
- st_word(buf + BPB_FATSz16, (WORD)sz_fat); /* FAT size [sector] */
- buf[BS_DrvNum] = 0x80; /* Drive number (for int13) */
- buf[BS_BootSig] = 0x29; /* Extended boot signature */
- mem_cpy(buf + BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */
- }
- st_word(buf + BS_55AA, 0xAA55); /* Signature (offset is fixed here regardless of sector size) */
- if (disk_write(pdrv, buf, b_vol, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Write it to the VBR sector */
-
- /* Create FSINFO record if needed */
- if (fmt == FS_FAT32) {
- (void)disk_write(pdrv, buf, b_vol + 6, 1); /* Write backup VBR (VBR + 6) */
- mem_set(buf, 0, ss);
- st_dword(buf + FSI_LeadSig, 0x41615252);
- st_dword(buf + FSI_StrucSig, 0x61417272);
- st_dword(buf + FSI_Free_Count, n_clst - 1); /* Number of free clusters */
- st_dword(buf + FSI_Nxt_Free, 2); /* Last allocated cluster# */
- st_word(buf + BS_55AA, 0xAA55);
- (void)disk_write(pdrv, buf, b_vol + 7, 1); /* Write backup FSINFO (VBR + 7) */
- (void)disk_write(pdrv, buf, b_vol + 1, 1); /* Write original FSINFO (VBR + 1) */
- }
-
- /* Initialize FAT area */
- mem_set(buf, 0, (UINT)szb_buf);
- sect = b_fat; /* FAT start sector */
- for (i = 0; i < n_fats; i++) { /* Initialize FATs each */
- if (fmt == FS_FAT32) {
- st_dword(buf + 0, 0xFFFFFFF8); /* Entry 0 */
- st_dword(buf + 4, 0xFFFFFFFF); /* Entry 1 */
- st_dword(buf + 8, 0x0FFFFFFF); /* Entry 2 (root directory) */
- } else {
- st_dword(buf + 0, (fmt == FS_FAT12) ? 0xFFFFF8 : 0xFFFFFFF8); /* Entry 0 and 1 */
- }
- nsect = sz_fat; /* Number of FAT sectors */
- do { /* Fill FAT sectors */
- n = (nsect > sz_buf) ? sz_buf : nsect;
- if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
- mem_set(buf, 0, ss);
- sect += n; nsect -= n;
- } while (nsect);
- }
-
- /* Initialize root directory (fill with zero) */
- nsect = (fmt == FS_FAT32) ? pau : sz_dir; /* Number of root directory sectors */
- do {
- n = (nsect > sz_buf) ? sz_buf : nsect;
- if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
- sect += n; nsect -= n;
- } while (nsect);
- }
-
- /* Determine system ID in the partition table */
- if (FF_FS_EXFAT && fmt == FS_EXFAT) {
- sys = 0x07; /* HPFS/NTFS/exFAT */
- } else {
- if (fmt == FS_FAT32) {
- sys = 0x0C; /* FAT32X */
- } else {
- if (sz_vol >= 0x10000) {
- sys = 0x06; /* FAT12/16 (large) */
- } else {
- sys = (fmt == FS_FAT16) ? 0x04 : 0x01; /* FAT16 : FAT12 */
- }
- }
- }
-
- /* Update partition information */
- if (FF_MULTI_PARTITION && part != 0) { /* Created in the existing partition */
- /* Update system ID in the partition table */
- if (disk_read(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Read the MBR */
- buf[MBR_Table + (part - 1) * SZ_PTE + PTE_System] = sys; /* Set system ID */
- if (disk_write(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Write it back to the MBR */
- } else { /* Created as a new single partition */
- if (!(opt & FM_SFD)) { /* Create partition table if in FDISK format */
- mem_set(buf, 0, ss);
- st_word(buf + BS_55AA, 0xAA55); /* MBR signature */
- pte = buf + MBR_Table; /* Create partition table for single partition in the drive */
- pte[PTE_Boot] = 0; /* Boot indicator */
- pte[PTE_StHead] = 1; /* Start head */
- pte[PTE_StSec] = 1; /* Start sector */
- pte[PTE_StCyl] = 0; /* Start cylinder */
- pte[PTE_System] = sys; /* System type */
- n = (b_vol + sz_vol) / (63 * 255); /* (End CHS may be invalid) */
- pte[PTE_EdHead] = 254; /* End head */
- pte[PTE_EdSec] = (BYTE)(((n >> 2) & 0xC0) | 63); /* End sector */
- pte[PTE_EdCyl] = (BYTE)n; /* End cylinder */
- st_dword(pte + PTE_StLba, b_vol); /* Start offset in LBA */
- st_dword(pte + PTE_SizLba, sz_vol); /* Size in sectors */
- if (disk_write(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); /* Write it to the MBR */
- }
- }
-
- if (disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
-
- LEAVE_MKFS(FR_OK);
-}
-
-
-
-#if FF_MULTI_PARTITION
-/*-----------------------------------------------------------------------*/
-/* Create Partition Table on the Physical Drive */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_fdisk (
- BYTE pdrv, /* Physical drive number */
- const DWORD* szt, /* Pointer to the size table for each partitions */
- void* work /* Pointer to the working buffer (null: use heap memory) */
-)
-{
- UINT i, n, sz_cyl, tot_cyl, b_cyl, e_cyl, p_cyl;
- BYTE s_hd, e_hd, *p, *buf = (BYTE*)work;
- DSTATUS stat;
- DWORD sz_disk, sz_part, s_part;
- FRESULT res = FR_DISK_ERR;
-
-
- stat = disk_initialize(pdrv);
- if (stat & STA_NOINIT) return FR_NOT_READY;
- if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
- if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_disk)) return FR_DISK_ERR;
-
- buf = (BYTE*)work;
-#if FF_USE_LFN == 3
- if (!buf) buf = ff_memalloc(FF_MAX_SS); /* Use heap memory for working buffer */
-#endif
- if (!buf) return FR_NOT_ENOUGH_CORE;
-
- /* Determine the CHS without any consideration of the drive geometry */
- for (n = 16; n < 256 && sz_disk / n / 63 > 1024; n *= 2) ;
- if (n == 256) n--;
- e_hd = (BYTE)(n - 1);
- sz_cyl = 63 * n;
- tot_cyl = sz_disk / sz_cyl;
-
- /* Create partition table */
- mem_set(buf, 0, FF_MAX_SS);
- p = buf + MBR_Table; b_cyl = 0;
- for (i = 0; i < 4; i++, p += SZ_PTE) {
- p_cyl = (szt[i] <= 100U) ? (DWORD)tot_cyl * szt[i] / 100 : szt[i] / sz_cyl; /* Number of cylinders */
- if (p_cyl == 0) continue;
- s_part = (DWORD)sz_cyl * b_cyl;
- sz_part = (DWORD)sz_cyl * p_cyl;
- if (i == 0) { /* Exclude first track of cylinder 0 */
- s_hd = 1;
- s_part += 63; sz_part -= 63;
- } else {
- s_hd = 0;
- }
- e_cyl = b_cyl + p_cyl - 1; /* End cylinder */
- if (e_cyl >= tot_cyl) LEAVE_MKFS(FR_INVALID_PARAMETER);
-
- /* Set partition table */
- p[1] = s_hd; /* Start head */
- p[2] = (BYTE)(((b_cyl >> 2) & 0xC0) | 1); /* Start sector */
- p[3] = (BYTE)b_cyl; /* Start cylinder */
- p[4] = 0x07; /* System type (temporary setting) */
- p[5] = e_hd; /* End head */
- p[6] = (BYTE)(((e_cyl >> 2) & 0xC0) | 63); /* End sector */
- p[7] = (BYTE)e_cyl; /* End cylinder */
- st_dword(p + 8, s_part); /* Start sector in LBA */
- st_dword(p + 12, sz_part); /* Number of sectors */
-
- /* Next partition */
- b_cyl += p_cyl;
- }
- st_word(p, 0xAA55); /* MBR signature (always at offset 510) */
-
- /* Write it to the MBR */
- res = (disk_write(pdrv, buf, 0, 1) == RES_OK && disk_ioctl(pdrv, CTRL_SYNC, 0) == RES_OK) ? FR_OK : FR_DISK_ERR;
- LEAVE_MKFS(res);
-}
-
-#endif /* FF_MULTI_PARTITION */
-#endif /* FF_USE_MKFS && !FF_FS_READONLY */
-
-
-
-
-#if FF_USE_STRFUNC
-#if FF_USE_LFN && FF_LFN_UNICODE && (FF_STRF_ENCODE < 0 || FF_STRF_ENCODE > 3)
-#error Wrong FF_STRF_ENCODE setting
-#endif
-/*-----------------------------------------------------------------------*/
-/* Get a String from the File */
-/*-----------------------------------------------------------------------*/
-
-TCHAR* f_gets (
- TCHAR* buff, /* Pointer to the string buffer to read */
- int len, /* Size of string buffer (items) */
- FIL* fp /* Pointer to the file object */
-)
-{
- int nc = 0;
- TCHAR *p = buff;
- BYTE s[4];
- UINT rc;
- DWORD dc;
-#if FF_USE_LFN && FF_LFN_UNICODE && FF_STRF_ENCODE <= 2
- WCHAR wc;
-#endif
-#if FF_USE_LFN && FF_LFN_UNICODE && FF_STRF_ENCODE == 3
- UINT ct;
-#endif
-
-#if FF_USE_LFN && FF_LFN_UNICODE /* With code conversion (Unicode API) */
- /* Make a room for the character and terminator */
- if (FF_LFN_UNICODE == 1) len -= (FF_STRF_ENCODE == 0) ? 1 : 2;
- if (FF_LFN_UNICODE == 2) len -= (FF_STRF_ENCODE == 0) ? 3 : 4;
- if (FF_LFN_UNICODE == 3) len -= 1;
- while (nc < len) {
-#if FF_STRF_ENCODE == 0 /* Read a character in ANSI/OEM */
- f_read(fp, s, 1, &rc);
- if (rc != 1) break;
- wc = s[0];
- if (dbc_1st((BYTE)wc)) {
- f_read(fp, s, 1, &rc);
- if (rc != 1 || !dbc_2nd(s[0])) continue;
- wc = wc << 8 | s[0];
- }
- dc = ff_oem2uni(wc, CODEPAGE);
- if (dc == 0) continue;
-#elif FF_STRF_ENCODE == 1 || FF_STRF_ENCODE == 2 /* Read a character in UTF-16LE/BE */
- f_read(fp, s, 2, &rc);
- if (rc != 2) break;
- dc = (FF_STRF_ENCODE == 1) ? ld_word(s) : s[0] << 8 | s[1];
- if (IsSurrogateL(dc)) continue;
- if (IsSurrogateH(dc)) {
- f_read(fp, s, 2, &rc);
- if (rc != 2) break;
- wc = (FF_STRF_ENCODE == 1) ? ld_word(s) : s[0] << 8 | s[1];
- if (!IsSurrogateL(wc)) continue;
- dc = ((dc & 0x3FF) + 0x40) << 10 | (wc & 0x3FF);
- }
-#else /* Read a character in UTF-8 */
- f_read(fp, s, 1, &rc);
- if (rc != 1) break;
- dc = s[0];
- if (dc >= 0x80) { /* Multi-byte character? */
- ct = 0;
- if ((dc & 0xE0) == 0xC0) { dc &= 0x1F; ct = 1; } /* 2-byte? */
- if ((dc & 0xF0) == 0xE0) { dc &= 0x0F; ct = 2; } /* 3-byte? */
- if ((dc & 0xF8) == 0xF0) { dc &= 0x07; ct = 3; } /* 4-byte? */
- if (ct == 0) continue;
- f_read(fp, s, ct, &rc); /* Get trailing bytes */
- if (rc != ct) break;
- rc = 0;
- do { /* Merge trailing bytes */
- if ((s[rc] & 0xC0) != 0x80) break;
- dc = dc << 6 | (s[rc] & 0x3F);
- } while (++rc < ct);
- if (rc != ct || dc < 0x80 || IsSurrogate(dc) || dc >= 0x110000) continue; /* Wrong encoding? */
- }
-#endif
- if (FF_USE_STRFUNC == 2 && dc == '\r') continue; /* Strip \r off if needed */
-#if FF_LFN_UNICODE == 1 || FF_LFN_UNICODE == 3 /* Output it in UTF-16/32 encoding */
- if (FF_LFN_UNICODE == 1 && dc >= 0x10000) { /* Out of BMP at UTF-16? */
- *p++ = (TCHAR)(0xD800 | ((dc >> 10) - 0x40)); nc++; /* Make and output high surrogate */
- dc = 0xDC00 | (dc & 0x3FF); /* Make low surrogate */
- }
- *p++ = (TCHAR)dc; nc++;
- if (dc == '\n') break; /* End of line? */
-#elif FF_LFN_UNICODE == 2 /* Output it in UTF-8 encoding */
- if (dc < 0x80) { /* 1-byte */
- *p++ = (TCHAR)dc;
- nc++;
- if (dc == '\n') break; /* End of line? */
- } else {
- if (dc < 0x800) { /* 2-byte */
- *p++ = (TCHAR)(0xC0 | (dc >> 6 & 0x1F));
- *p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F));
- nc += 2;
- } else {
- if (dc < 0x10000) { /* 3-byte */
- *p++ = (TCHAR)(0xE0 | (dc >> 12 & 0x0F));
- *p++ = (TCHAR)(0x80 | (dc >> 6 & 0x3F));
- *p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F));
- nc += 3;
- } else { /* 4-byte */
- *p++ = (TCHAR)(0xF0 | (dc >> 18 & 0x07));
- *p++ = (TCHAR)(0x80 | (dc >> 12 & 0x3F));
- *p++ = (TCHAR)(0x80 | (dc >> 6 & 0x3F));
- *p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F));
- nc += 4;
- }
- }
- }
-#endif
- }
-
-#else /* Byte-by-byte without any conversion (ANSI/OEM API) */
- len -= 1; /* Make a room for the terminator */
- while (nc < len) {
- f_read(fp, s, 1, &rc);
- if (rc != 1) break;
- dc = s[0];
- if (FF_USE_STRFUNC == 2 && dc == '\r') continue;
- *p++ = (TCHAR)dc; nc++;
- if (dc == '\n') break;
- }
-#endif
-
- *p = 0; /* Terminate the string */
- return nc ? buff : 0; /* When no data read due to EOF or error, return with error. */
-}
-
-
-
-
-#if !FF_FS_READONLY
-#include
-/*-----------------------------------------------------------------------*/
-/* Put a Character to the File */
-/*-----------------------------------------------------------------------*/
-
-typedef struct { /* Putchar output buffer and work area */
- FIL *fp; /* Ptr to the writing file */
- int idx, nchr; /* Write index of buf[] (-1:error), number of encoding units written */
-#if FF_USE_LFN && FF_LFN_UNICODE == 1
- WCHAR hs;
-#elif FF_USE_LFN && FF_LFN_UNICODE == 2
- BYTE bs[4];
- UINT wi, ct;
-#endif
- BYTE buf[64]; /* Write buffer */
-} putbuff;
-
-
-static
-void putc_bfd ( /* Buffered write with code conversion */
- putbuff* pb,
- TCHAR c
-)
-{
- UINT n;
- int i, nc;
-#if FF_USE_LFN && FF_LFN_UNICODE
- WCHAR hs, wc;
-#if FF_LFN_UNICODE == 2
- DWORD dc;
- TCHAR *tp;
-#endif
-#endif
-
- if (FF_USE_STRFUNC == 2 && c == '\n') { /* LF -> CRLF conversion */
- putc_bfd(pb, '\r');
- }
-
- i = pb->idx; /* Write index of pb->buf[] */
- if (i < 0) return;
- nc = pb->nchr; /* Write unit counter */
-
-#if FF_USE_LFN && FF_LFN_UNICODE
-#if FF_LFN_UNICODE == 1 /* UTF-16 input */
- if (IsSurrogateH(c)) {
- pb->hs = c; return;
- }
- hs = pb->hs; pb->hs = 0;
- if (hs != 0) {
- if (!IsSurrogateL(c)) hs = 0;
- } else {
- if (IsSurrogateL(c)) return;
- }
- wc = c;
-#elif FF_LFN_UNICODE == 2 /* UTF-8 input */
- for (;;) {
- if (pb->ct == 0) { /* Out of multi-byte sequence? */
- pb->bs[pb->wi = 0] = (BYTE)c; /* Save 1st byte */
- if ((BYTE)c < 0x80) break; /* 1-byte? */
- if (((BYTE)c & 0xE0) == 0xC0) pb->ct = 1; /* 2-byte? */
- if (((BYTE)c & 0xF0) == 0xE0) pb->ct = 2; /* 3-byte? */
- if (((BYTE)c & 0xF1) == 0xF0) pb->ct = 3; /* 4-byte? */
- return;
- } else { /* In the multi-byte sequence */
- if (((BYTE)c & 0xC0) != 0x80) { /* Broken sequence? */
- pb->ct = 0; continue;
- }
- pb->bs[++pb->wi] = (BYTE)c; /* Save the trailing byte */
- if (--pb->ct == 0) break; /* End of multi-byte sequence? */
- return;
- }
- }
- tp = (TCHAR*)pb->bs;
- dc = tchar2uni(&tp); /* UTF-8 ==> UTF-16 */
- if (dc == 0xFFFFFFFF) return;
- wc = (WCHAR)dc;
- hs = (WCHAR)(dc >> 16);
-#elif FF_LFN_UNICODE == 3 /* UTF-32 input */
- if (IsSurrogate(c) || c >= 0x110000) return;
- if (c >= 0x10000) {
- hs = (WCHAR)(0xD800 | ((c >> 10) - 0x40)); /* Make high surrogate */
- wc = 0xDC00 | (c & 0x3FF); /* Make low surrogate */
- } else {
- hs = 0;
- wc = (WCHAR)c;
- }
-#endif
-
-#if FF_STRF_ENCODE == 1 /* Write a character in UTF-16LE */
- if (hs != 0) {
- st_word(&pb->buf[i], hs);
- i += 2;
- nc++;
- }
- st_word(&pb->buf[i], wc);
- i += 2;
-#elif FF_STRF_ENCODE == 2 /* Write a character in UTF-16BE */
- if (hs != 0) {
- pb->buf[i++] = (BYTE)(hs >> 8);
- pb->buf[i++] = (BYTE)hs;
- nc++;
- }
- pb->buf[i++] = (BYTE)(wc >> 8);
- pb->buf[i++] = (BYTE)wc;
-#elif FF_STRF_ENCODE == 3 /* Write it in UTF-8 */
- if (hs != 0) { /* 4-byte */
- nc += 3;
- hs = (hs & 0x3FF) + 0x40;
- pb->buf[i++] = (BYTE)(0xF0 | hs >> 8);
- pb->buf[i++] = (BYTE)(0x80 | (hs >> 2 & 0x3F));
- pb->buf[i++] = (BYTE)(0x80 | (hs & 3) << 4 | (wc >> 6 & 0x0F));
- pb->buf[i++] = (BYTE)(0x80 | (wc & 0x3F));
- } else {
- if (wc < 0x80) { /* 1-byte */
- pb->buf[i++] = (BYTE)wc;
- } else {
- if (wc < 0x800) { /* 2-byte */
- nc += 1;
- pb->buf[i++] = (BYTE)(0xC0 | wc >> 6);
- } else { /* 3-byte */
- nc += 2;
- pb->buf[i++] = (BYTE)(0xE0 | wc >> 12);
- pb->buf[i++] = (BYTE)(0x80 | (wc >> 6 & 0x3F));
- }
- pb->buf[i++] = (BYTE)(0x80 | (wc & 0x3F));
- }
- }
-#else /* Write it in ANSI/OEM */
- if (hs != 0) return;
- wc = ff_uni2oem(wc, CODEPAGE); /* UTF-16 ==> ANSI/OEM */
- if (wc == 0) return;;
- if (wc >= 0x100) {
- pb->buf[i++] = (BYTE)(wc >> 8); nc++;
- }
- pb->buf[i++] = (BYTE)wc;
-#endif
-
-#else /* ANSI/OEM input (without re-encode) */
- pb->buf[i++] = (BYTE)c;
-#endif
-
- if (i >= (int)(sizeof pb->buf) - 4) { /* Write buffered characters to the file */
- f_write(pb->fp, pb->buf, (UINT)i, &n);
- i = (n == (UINT)i) ? 0 : -1;
- }
- pb->idx = i;
- pb->nchr = nc + 1;
-}
-
-
-static
-int putc_flush ( /* Flush left characters in the buffer */
- putbuff* pb
-)
-{
- UINT nw;
-
- if ( pb->idx >= 0 /* Flush buffered characters to the file */
- && f_write(pb->fp, pb->buf, (UINT)pb->idx, &nw) == FR_OK
- && (UINT)pb->idx == nw) return pb->nchr;
- return EOF;
-}
-
-
-static
-void putc_init ( /* Initialize write buffer */
- putbuff* pb,
- FIL* fp
-)
-{
- mem_set(pb, 0, sizeof (putbuff));
- pb->fp = fp;
-}
-
-
-
-int f_putc (
- TCHAR c, /* A character to be output */
- FIL* fp /* Pointer to the file object */
-)
-{
- putbuff pb;
-
-
- putc_init(&pb, fp);
- putc_bfd(&pb, c); /* Put the character */
- return putc_flush(&pb);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Put a String to the File */
-/*-----------------------------------------------------------------------*/
-
-int f_puts (
- const TCHAR* str, /* Pointer to the string to be output */
- FIL* fp /* Pointer to the file object */
-)
-{
- putbuff pb;
-
-
- putc_init(&pb, fp);
- while (*str) putc_bfd(&pb, *str++); /* Put the string */
- return putc_flush(&pb);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Put a Formatted String to the File */
-/*-----------------------------------------------------------------------*/
-
-int f_printf (
- FIL* fp, /* Pointer to the file object */
- const TCHAR* fmt, /* Pointer to the format string */
- ... /* Optional arguments... */
-)
-{
- va_list arp;
- putbuff pb;
- BYTE f, r;
- UINT i, j, w;
- DWORD v;
- TCHAR c, d, str[32], *p;
-
-
- putc_init(&pb, fp);
-
- va_start(arp, fmt);
-
- for (;;) {
- c = *fmt++;
- if (c == 0) break; /* End of string */
- if (c != '%') { /* Non escape character */
- putc_bfd(&pb, c);
- continue;
- }
- w = f = 0;
- c = *fmt++;
- if (c == '0') { /* Flag: '0' padding */
- f = 1; c = *fmt++;
- } else {
- if (c == '-') { /* Flag: left justified */
- f = 2; c = *fmt++;
- }
- }
- if (c == '*') { /* Minimum width by argument */
- w = va_arg(arp, int);
- c = *fmt++;
- } else {
- while (IsDigit(c)) { /* Minimum width */
- w = w * 10 + c - '0';
- c = *fmt++;
- }
- }
- if (c == 'l' || c == 'L') { /* Type prefix: Size is long int */
- f |= 4; c = *fmt++;
- }
- if (c == 0) break;
- d = c;
- if (IsLower(d)) d -= 0x20;
- switch (d) { /* Atgument type is... */
- case 'S' : /* String */
- p = va_arg(arp, TCHAR*);
- for (j = 0; p[j]; j++) ;
- if (!(f & 2)) { /* Right padded */
- while (j++ < w) putc_bfd(&pb, ' ') ;
- }
- while (*p) putc_bfd(&pb, *p++) ; /* String body */
- while (j++ < w) putc_bfd(&pb, ' ') ; /* Left padded */
- continue;
-
- case 'C' : /* Character */
- putc_bfd(&pb, (TCHAR)va_arg(arp, int)); continue;
-
- case 'B' : /* Unsigned binary */
- r = 2; break;
-
- case 'O' : /* Unsigned octal */
- r = 8; break;
-
- case 'D' : /* Signed decimal */
- case 'U' : /* Unsigned decimal */
- r = 10; break;
-
- case 'X' : /* Unsigned hexdecimal */
- r = 16; break;
-
- default: /* Unknown type (pass-through) */
- putc_bfd(&pb, c); continue;
- }
-
- /* Get an argument and put it in numeral */
- v = (f & 4) ? (DWORD)va_arg(arp, long) : ((d == 'D') ? (DWORD)(long)va_arg(arp, int) : (DWORD)va_arg(arp, unsigned int));
- if (d == 'D' && (v & 0x80000000)) {
- v = 0 - v;
- f |= 8;
- }
- i = 0;
- do {
- d = (TCHAR)(v % r); v /= r;
- if (d > 9) d += (c == 'x') ? 0x27 : 0x07;
- str[i++] = d + '0';
- } while (v && i < sizeof str / sizeof *str);
- if (f & 8) str[i++] = '-';
- j = i; d = (f & 1) ? '0' : ' ';
- if (!(f & 2)) {
- while (j++ < w) putc_bfd(&pb, d); /* Right pad */
- }
- do {
- putc_bfd(&pb, str[--i]); /* Number body */
- } while (i);
- while (j++ < w) putc_bfd(&pb, d); /* Left pad */
- }
-
- va_end(arp);
-
- return putc_flush(&pb);
-}
-
-#endif /* !FF_FS_READONLY */
-#endif /* FF_USE_STRFUNC */
-
-
-
-#if FF_CODE_PAGE == 0
-/*-----------------------------------------------------------------------*/
-/* Set Active Codepage for the Path Name */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_setcp (
- WORD cp /* Value to be set as active code page */
-)
-{
- static const WORD validcp[] = { 437, 720, 737, 771, 775, 850, 852, 857, 860, 861, 862, 863, 864, 865, 866, 869, 932, 936, 949, 950, 0};
- static const BYTE* const tables[] = {Ct437, Ct720, Ct737, Ct771, Ct775, Ct850, Ct852, Ct857, Ct860, Ct861, Ct862, Ct863, Ct864, Ct865, Ct866, Ct869, Dc932, Dc936, Dc949, Dc950, 0};
- UINT i;
-
-
- for (i = 0; validcp[i] != 0 && validcp[i] != cp; i++) ; /* Find the code page */
- if (validcp[i] != cp) return FR_INVALID_PARAMETER; /* Not found? */
-
- CodePage = cp;
- if (cp >= 900) { /* DBCS */
- ExCvt = 0;
- DbcTbl = tables[i];
- } else { /* SBCS */
- ExCvt = tables[i];
- DbcTbl = 0;
- }
- return FR_OK;
-}
-#endif /* FF_CODE_PAGE == 0 */
-
-#endif /* (defined FILE_SYSTEM_INTERFACE_SD) || (defined FILE_SYSTEM_INTERFACE_RAM) */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/67/a026a1545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/67/a026a1545243001d18b399c1eb9b3628
deleted file mode 100644
index b733141..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/67/a026a1545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,215 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xemacps_bdring.h
-* @addtogroup emacps_v3_15
-* @{
-*
-* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
-* DMA functionalities.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 First release
-* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
-* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
-* changed to volatile.
-*
-*
-*
-******************************************************************************/
-
-#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */
-#define XEMACPS_BDRING_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/**************************** Type Definitions *******************************/
-
-/** This is an internal structure used to maintain the DMA list */
-typedef struct {
- UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
- UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */
- UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */
- u32 Length; /**< Total size of ring in bytes */
- u32 RunState; /**< Flag to indicate DMA is started */
- u32 Separation; /**< Number of bytes between the starting address
- of adjacent BDs */
- XEmacPs_Bd *FreeHead;
- /**< First BD in the free group */
- XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
- XEmacPs_Bd *HwHead; /**< First BD in the work group */
- XEmacPs_Bd *HwTail; /**< Last BD in the work group */
- XEmacPs_Bd *PostHead;
- /**< First BD in the post-work group */
- XEmacPs_Bd *BdaRestart;
- /**< BDA to load when channel is started */
-
- volatile u32 HwCnt; /**< Number of BDs in work group */
- u32 PreCnt; /**< Number of BDs in pre-work group */
- u32 FreeCnt; /**< Number of allocatable BDs in the free group */
- u32 PostCnt; /**< Number of BDs in post-work group */
- u32 AllCnt; /**< Total Number of BDs for channel */
-} XEmacPs_BdRing;
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
-* Use this macro at initialization time to determine how many BDs will fit
-* in a BD list within the given memory constraints.
-*
-* The results of this macro can be provided to XEmacPs_BdRingCreate().
-*
-* @param Alignment specifies what byte alignment the BDs must fall on and
-* must be a power of 2 to get an accurate calculation (32, 64, 128,...)
-* @param Bytes is the number of bytes to be used to store BDs.
-*
-* @return Number of BDs that can fit in the given memory area
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
-*
-******************************************************************************/
-#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \
- (u32)((Bytes) / (sizeof(XEmacPs_Bd)))
-
-/*****************************************************************************/
-/**
-* Use this macro at initialization time to determine how many bytes of memory
-* is required to contain a given number of BDs at a given alignment.
-*
-* @param Alignment specifies what byte alignment the BDs must fall on. This
-* parameter must be a power of 2 to get an accurate calculation (32, 64,
-* 128,...)
-* @param NumBd is the number of BDs to calculate memory size requirements for
-*
-* @return The number of bytes of memory required to create a BD list with the
-* given memory constraints.
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
-*
-******************************************************************************/
-#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \
- (u32)(sizeof(XEmacPs_Bd) * (NumBd))
-
-/****************************************************************************/
-/**
-* Return the total number of BDs allocated by this channel with
-* XEmacPs_BdRingCreate().
-*
-* @param RingPtr is the DMA channel to operate on.
-*
-* @return The total number of BDs allocated for this channel.
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
-
-/****************************************************************************/
-/**
-* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
-* processing.
-*
-* @param RingPtr is the DMA channel to operate on.
-*
-* @return The number of BDs currently allocatable.
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt)
-
-/****************************************************************************/
-/**
-* Return the next BD from BdPtr in a list.
-*
-* @param RingPtr is the DMA channel to operate on.
-* @param BdPtr is the BD to operate on.
-*
-* @return The next BD in the list relative to the BdPtr parameter.
-*
-* @note
-* C-style signature:
-* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
-* XEmacPs_Bd *BdPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingNext(RingPtr, BdPtr) \
- (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ? \
- (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) : \
- (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
-
-/****************************************************************************/
-/**
-* Return the previous BD from BdPtr in the list.
-*
-* @param RingPtr is the DMA channel to operate on.
-* @param BdPtr is the BD to operate on
-*
-* @return The previous BD in the list relative to the BdPtr parameter.
-*
-* @note
-* C-style signature:
-* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
-* XEmacPs_Bd *BdPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \
- (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \
- (XEmacPs_Bd*)(RingPtr)->HighBdAddr : \
- (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Scatter gather DMA related functions in xemacps_bdring.c
- */
-LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
- UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
-LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
- u8 Direction);
-LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd ** BdSetPtr);
-LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr);
-LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr);
-LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr);
-u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
- XEmacPs_Bd ** BdSetPtr);
-u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
- XEmacPs_Bd ** BdSetPtr);
-LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
-
-void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* end of protection macros */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/67/a04bf7565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/67/a04bf7565243001d18b399c1eb9b3628
deleted file mode 100644
index 1befce1..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/67/a04bf7565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,255 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpm_counter.c
-*
-* This file contains APIs for configuring and controlling the Cortex-A9
-* Performance Monitor Events. For more information about the event counters,
-* see xpm_counter.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 4.2 pkp 07/21/14 Corrected reset value of event counter in function
-* Xpm_ResetEventCounters to fix CR#796275
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xpm_counter.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-typedef const u32 PmcrEventCfg32[XPM_CTRCOUNT];
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void Xpm_DisableEventCounters(void);
-void Xpm_EnableEventCounters (void);
-void Xpm_ResetEventCounters (void);
-
-/******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @brief This function disables the Cortex A9 event counters.
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_DisableEventCounters(void)
-{
- /* Disable the event counters */
- mtcp(XREG_CP15_COUNT_ENABLE_CLR, 0x3f);
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function enables the Cortex A9 event counters.
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_EnableEventCounters(void)
-{
- /* Enable the event counters */
- mtcp(XREG_CP15_COUNT_ENABLE_SET, 0x3f);
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function resets the Cortex A9 event counters.
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_ResetEventCounters(void)
-{
- u32 Reg;
-#ifdef __GNUC__
- Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
-#else
- { register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL);
- Reg = C15Reg; }
-#endif
- Reg |= (1U << 1U); /* reset event counters */
- mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
-
-}
-
-/****************************************************************************/
-/**
-* @brief This function configures the Cortex A9 event counters controller,
-* with the event codes, in a configuration selected by the user and
-* enables the counters.
-*
-* @param PmcrCfg: Configuration value based on which the event counters
-* are configured. XPM_CNTRCFG* values defined in xpm_counter.h can
-* be utilized for setting configuration.
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_SetEvents(s32 PmcrCfg)
-{
- u32 Counter;
- static PmcrEventCfg32 PmcrEvents[] = {
- {
- XPM_EVENT_SOFTINCR,
- XPM_EVENT_INSRFETCH_CACHEREFILL,
- XPM_EVENT_INSTRFECT_TLBREFILL,
- XPM_EVENT_DATA_CACHEREFILL,
- XPM_EVENT_DATA_CACHEACCESS,
- XPM_EVENT_DATA_TLBREFILL
- },
- {
- XPM_EVENT_DATA_READS,
- XPM_EVENT_DATA_WRITE,
- XPM_EVENT_EXCEPTION,
- XPM_EVENT_EXCEPRETURN,
- XPM_EVENT_CHANGECONTEXT,
- XPM_EVENT_SW_CHANGEPC
- },
- {
- XPM_EVENT_IMMEDBRANCH,
- XPM_EVENT_UNALIGNEDACCESS,
- XPM_EVENT_BRANCHMISS,
- XPM_EVENT_CLOCKCYCLES,
- XPM_EVENT_BRANCHPREDICT,
- XPM_EVENT_JAVABYTECODE
- },
- {
- XPM_EVENT_SWJAVABYTECODE,
- XPM_EVENT_JAVABACKBRANCH,
- XPM_EVENT_COHERLINEMISS,
- XPM_EVENT_COHERLINEHIT,
- XPM_EVENT_INSTRSTALL,
- XPM_EVENT_DATASTALL
- },
- {
- XPM_EVENT_MAINTLBSTALL,
- XPM_EVENT_STREXPASS,
- XPM_EVENT_STREXFAIL,
- XPM_EVENT_DATAEVICT,
- XPM_EVENT_NODISPATCH,
- XPM_EVENT_ISSUEEMPTY
- },
- {
- XPM_EVENT_INSTRRENAME,
- XPM_EVENT_PREDICTFUNCRET,
- XPM_EVENT_MAINEXEC,
- XPM_EVENT_SECEXEC,
- XPM_EVENT_LDRSTR,
- XPM_EVENT_FLOATRENAME
- },
- {
- XPM_EVENT_NEONRENAME,
- XPM_EVENT_PLDSTALL,
- XPM_EVENT_WRITESTALL,
- XPM_EVENT_INSTRTLBSTALL,
- XPM_EVENT_DATATLBSTALL,
- XPM_EVENT_INSTR_uTLBSTALL
- },
- {
- XPM_EVENT_DATA_uTLBSTALL,
- XPM_EVENT_DMB_STALL,
- XPM_EVENT_INT_CLKEN,
- XPM_EVENT_DE_CLKEN,
- XPM_EVENT_INSTRISB,
- XPM_EVENT_INSTRDSB
- },
- {
- XPM_EVENT_INSTRDMB,
- XPM_EVENT_EXTINT,
- XPM_EVENT_PLE_LRC,
- XPM_EVENT_PLE_LRS,
- XPM_EVENT_PLE_FLUSH,
- XPM_EVENT_PLE_CMPL
- },
- {
- XPM_EVENT_PLE_OVFL,
- XPM_EVENT_PLE_PROG,
- XPM_EVENT_PLE_LRC,
- XPM_EVENT_PLE_LRS,
- XPM_EVENT_PLE_FLUSH,
- XPM_EVENT_PLE_CMPL
- },
- {
- XPM_EVENT_DATASTALL,
- XPM_EVENT_INSRFETCH_CACHEREFILL,
- XPM_EVENT_INSTRFECT_TLBREFILL,
- XPM_EVENT_DATA_CACHEREFILL,
- XPM_EVENT_DATA_CACHEACCESS,
- XPM_EVENT_DATA_TLBREFILL
- },
- };
- const u32 *ptr = PmcrEvents[PmcrCfg];
-
- Xpm_DisableEventCounters();
-
- for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
-
- /* Selecet event counter */
- mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
-
- /* Set the event */
- mtcp(XREG_CP15_EVENT_TYPE_SEL, ptr[Counter]);
- }
-
- Xpm_ResetEventCounters();
- Xpm_EnableEventCounters();
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function disables the event counters and returns the counter
-* values.
-*
-* @param PmCtrValue: Pointer to an array of type u32 PmCtrValue[6].
-* It is an output parameter which is used to return the PM
-* counter values.
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_GetEventCounters(u32 *PmCtrValue)
-{
- u32 Counter;
-
- Xpm_DisableEventCounters();
-
- for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
-
- mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
-#ifdef __GNUC__
- PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_PERF_MONITOR_COUNT, PmCtrValue[Counter]);
-#else
- { register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT);
- PmCtrValue[Counter] = Cp15Reg; }
-#endif
- }
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/67/a09714575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/67/a09714575243001d18b399c1eb9b3628
deleted file mode 100644
index c3dabfc..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/67/a09714575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,351 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/******************************************************************************/
-/**
- * @file xusbps.c
-* @addtogroup usbps_v2_7
-* @{
- *
- * The XUsbPs driver. Functions in this file are the minimum required
- * functions for this driver. See xusbps.h for a detailed description of the
- * driver.
- *
- * @note None.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- --------------------------------------------------------
- * 1.00a jz 10/10/10 First release
- * 2.1 kpc 04/28/14 Removed unused functions
- * 2.5 pm 02/20/20 Added usb state interface.
- *
- ******************************************************************************/
-
-/***************************** Include Files **********************************/
-#include
-#include "xusbps.h"
-
-/************************** Constant Definitions ******************************/
-
-/**************************** Type Definitions ********************************/
-
-/***************** Macros (Inline Functions) Definitions **********************/
-
-/************************** Variable Definitions ******************************/
-
-/************************** Function Prototypes *******************************/
-
-/*****************************************************************************/
-/**
-*
-* This function initializes a XUsbPs instance/driver.
-*
-* The initialization entails:
-* - Initialize all members of the XUsbPs structure.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param ConfigPtr is a pointer to a XUsbPs_Config configuration
-* structure. This structure will contain the requested
-* configuration for the device. Typically, this is a local
-* structure and the content of which will be copied into the
-* configuration structure within XUsbPs.
-* @param VirtBaseAddress is the base address of the device. For systems
-* with virtual memory, this address must be the virtual address
-* of the device.
-* For systems that do not support virtual memory this address
-* should be the physical address of the device. For backwards
-* compatibility NULL may be passed in systems that do not support
-* virtual memory (deprecated).
-*
-* @return
-* - XST_SUCCESS no errors occurred.
-* - XST_FAILURE an error occurred during initialization.
-*
-* @note
-* After calling XUsbPs_CfgInitialize() the controller
-* IS NOT READY for use. Before the controller can be used its
-* DEVICE parameters must be configured. See xusbps.h
-* for details.
-*
-******************************************************************************/
-int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
- const XUsbPs_Config *ConfigPtr, u32 VirtBaseAddress)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
-
- /* Copy the config structure. */
- InstancePtr->Config = *ConfigPtr;
-
- /* Check if the user provided a non-NULL base address. If so, we have
- * to overwrite the base address in the configuration structure.
- */
- if (0 != VirtBaseAddress) {
- InstancePtr->Config.BaseAddress = VirtBaseAddress;
- }
-
- /* Initialize the XUsbPs structure to default values. */
- InstancePtr->CurrentAltSetting = XUSBPS_DEFAULT_ALT_SETTING;
-
- InstancePtr->HandlerFunc = NULL;
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function performs device reset, device is stopped at the end.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XUsbPs_DeviceReset(XUsbPs *InstancePtr)
-{
- int Timeout;
-
- /* Clear all setup token semaphores by reading the
- * XUSBPS_EPSTAT_OFFSET register and writing its value back to
- * itself.
- */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPSTAT_OFFSET,
- XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPSTAT_OFFSET));
-
- /* Clear all the endpoint complete status bits by reading the
- * XUSBPS_EPCOMPL_OFFSET register and writings its value back
- * to itself.
- */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPCOMPL_OFFSET,
- XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPCOMPL_OFFSET));
-
- /* Cancel all endpoint prime status by waiting until all bits
- * in XUSBPS_EPPRIME_OFFSET are 0 and then writing 0xFFFFFFFF
- * to XUSBPS_EPFLUSH_OFFSET.
- *
- * Avoid hanging here by using a Timeout counter...
- */
- Timeout = XUSBPS_TIMEOUT_COUNTER;
- while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPPRIME_OFFSET) &
- XUSBPS_EP_ALL_MASK) && --Timeout) {
- /* NOP */
- }
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF);
-
- XUsbPs_Stop(InstancePtr);
-
- /* Write to CR register for controller reset */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
- XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_CMD_OFFSET) | XUSBPS_CMD_RST_MASK);
-
- /* Wait for reset to finish, hardware clears the reset bit once done */
- Timeout = 1000000;
- while((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_CMD_OFFSET) &
- XUSBPS_CMD_RST_MASK) && --Timeout) {
- /* NOP */
- }
-}
-/*****************************************************************************/
-/**
-*
-* This function resets the USB device. All the configuration registers are
-* reset to their default values. The function waits until the reset operation
-* is complete or for a certain duration within which the reset operation is
-* expected to be completed.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @return
-* - XST_SUCCESS Reset operation completed successfully.
-* - XST_FAILURE Reset operation timed out.
-*
-* @note None.
-*
-******************************************************************************/
-int XUsbPs_Reset(XUsbPs *InstancePtr)
-{
- int Timeout;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /* Write a 1 to the RESET bit. The RESET bit is cleared by HW once the
- * RESET is complete.
- *
- * We are going to wait for the RESET bit to clear before we return
- * from this function. Unfortunately we do not have timers available at
- * this point to determine when we should report a Timeout.
- *
- * However, by using a large number for the poll loop we can assume
- * that the polling operation will take longer than the expected time
- * the HW needs to RESET. If the poll loop expires we can assume a
- * Timeout. The drawback is that on a slow system (and even on a fast
- * system) this can lead to _very_ long Timeout periods.
- */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_CMD_OFFSET, XUSBPS_CMD_RST_MASK);
-
-
- /* Wait for the RESET bit to be cleared by HW. */
- Timeout = XUSBPS_TIMEOUT_COUNTER;
- while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_CMD_OFFSET) &
- XUSBPS_CMD_RST_MASK) && --Timeout) {
- /* NOP */
- }
-
- if (0 == Timeout) {
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
- * USB Suspend
- *
- * In order to conserve power, USB devices automatically enter the suspended
- * state when the device has observed no bus traffic for a specified period.
- * When suspended, the USB device maintains any internal status, including its
- * address and configuration. Attached devices must be prepared to suspend at
- * any time they are powered, regardless of if they have been assigned a
- * non-default address, are configured, or neither. Bus activity may cease due
- * to the host entering a suspend mode of its own. In addition, a USB device
- * shall also enter the suspended state when the hub port it is attached to is
- * disabled.
- *
- * A USB device exits suspend mode when there is bus activity. A USB device may
- * also request the host to exit suspend mode or selective suspend by using
- * electrical signaling to indicate remote wakeup. The ability of a device to
- * signal remote wakeup is optional. If the USB device is capable of remote
- * wakeup signaling, the device must support the ability of the host to enable
- * and disable this capability. When the device is reset, remote wakeup
- * signaling must be disabled.
- *
- * @param InstancePtr is a pointer to XUsbPs instance of the controller.
- *
- * @return
- * - XST_SUCCESS if the USB device has entered Suspend mode
- * successfully
- * - XST_FAILURE on any error
- *
- * @note None.
- *
- ******************************************************************************/
-int XUsbPs_Suspend(const XUsbPs *InstancePtr)
-{
- (void) InstancePtr;
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-* USB Resume
-*
- If the USB controller is suspended, its operation is resumed when any
-* non-idle signaling is received on its upstream facing port.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @return
-* - XST_SUCCESS if the USB device has Resumed successfully
-* - XST_FAILURE on any error
-*
-* @note None.
-*
-******************************************************************************/
-int XUsbPs_Resume(const XUsbPs *InstancePtr)
-{
- (void) InstancePtr;
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-* USB Assert Resume
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @return
-* - XST_SUCCESS if the USB device has Resumed successfully
-* - XST_FAILURE on any error
-*
-* @note None.
-*
-******************************************************************************/
-
-int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr)
-{
- (void) InstancePtr;
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-* This functions sets the controller's DEVICE address. It also sets the
-* advance bit so the controller will wait for the next IN-ACK before the new
-* address takes effect.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param Address is the Address of the device.
-*
-* @return
-* - XST_SUCCESS: Address set successfully.
-* - XST_FAILURE: An error occurred.
-* - XST_INVALID_PARAM: Invalid parameter passed, e.g. address
-* value too big.
-*
-* @note None.
-*
-*****************************************************************************/
-int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- if ((InstancePtr->AppData != NULL) &&
- (InstancePtr->AppData->State ==
- XUSBPS_STATE_CONFIGURED)) {
- return XST_FAILURE;
- }
-
- /* Check address range validity. */
- if (Address > XUSBPS_DEVICEADDR_MAX) {
- return XST_INVALID_PARAM;
- }
-
- /* Set the address register with the Address value provided. Also set
- * the Address Advance Bit. This will cause the address to be set only
- * after an IN occurred and has been ACKed on the endpoint.
- */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_DEVICEADDR_OFFSET,
- (Address << XUSBPS_DEVICEADDR_ADDR_SHIFT) |
- XUSBPS_DEVICEADDR_DEVICEAADV_MASK);
-
- if (InstancePtr->AppData != NULL) {
- if (Address)
- InstancePtr->AppData->State = XUSBPS_STATE_ADDRESS;
- else
- InstancePtr->AppData->State = XUSBPS_STATE_DEFAULT;
- }
- return XST_SUCCESS;
-}
-
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/68/809edf595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/68/809edf595243001d18b399c1eb9b3628
deleted file mode 100644
index 0c9f9bb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/68/809edf595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,31 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 2021.2
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2022 Xilinx, Inc. All Rights Reserved.
-* SPDX-License-Identifier: MIT
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xadcps.h"
-
-/*
-* The configuration table for devices
-*/
-
-XAdcPs_Config XAdcPs_ConfigTable[XPAR_XADCPS_NUM_INSTANCES] =
-{
- {
- XPAR_PS7_XADC_0_DEVICE_ID,
- XPAR_PS7_XADC_0_BASEADDR
- }
-};
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/68/c10cdc545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/68/c10cdc545243001d18b399c1eb9b3628
deleted file mode 100644
index de98c61..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/68/c10cdc545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,345 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xscutimer.h
-* @addtogroup scutimer_v2_3
-* @{
-* @details
-*
-* The timer driver supports the Cortex A9 private timer.
-*
-* The timer driver supports the following features:
-* - Normal mode and Auto reload mode
-* - Interrupts (Interrupt handler is not provided in this driver. Application
-* has to register it's own handler)
-*
-* Initialization and Configuration
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate with the Timer.
-*
-* XScuTimer_CfgInitialize() API is used to initialize the Timer. The
-* user needs to first call the XScuTimer_LookupConfig() API which returns
-* the Configuration structure pointer which is passed as a parameter to
-* the XScuTimer_CfgInitialize() API.
-*
-* Interrupts
-*
-* The Timer hardware supports interrupts.
-*
-* This driver does not provide a Interrupt Service Routine (ISR) for the device.
-* It is the responsibility of the application to provide one if needed. Refer to
-* the interrupt example provided with this driver for details on using the
-* Timer in interrupt mode.
-*
-* Virtual Memory
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-* Threads
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* Asserts
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* Building the driver
-*
-* The XScuTimer driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-*
-*
-* NOTE:
-* The timer is not a part of the snoop control unit as indicated by the
-* prefix "scu" in the name of the driver.
-* It is an independent module in APU.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm 03/10/10 First release
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 2.3 mus 08/31/20 Updated makefile to support parallel make and
-* incremental builds, it would help to reduce compilation
-* time.
-*
-*
-******************************************************************************/
-#ifndef XSCUTIMER_H /* prevent circular inclusions */
-#define XSCUTIMER_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xscutimer_hw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddr; /**< Base address of the device */
-} XScuTimer_Config;
-
-/**
- * The XScuTimer driver instance data. The user is required to allocate a
- * variable of this type for every timer device in the system.
- * A pointer to a variable of this type is then passed to the driver API
- * functions.
- */
-typedef struct {
- XScuTimer_Config Config; /**< Hardware Configuration */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStarted; /**< Device timer is running */
-} XScuTimer;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Check if the timer has expired.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return
-* - TRUE if the timer has expired.
-* - FALSE if the timer has not expired.
-*
-* @note C-style signature:
-* int XScuTimer_IsExpired(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_IsExpired(InstancePtr) \
- ((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_ISR_OFFSET) & \
- XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
- XSCUTIMER_ISR_EVENT_FLAG_MASK)
-
-/****************************************************************************/
-/**
-*
-* Re-start the timer. This macro will read the timer load register
-* and writes the same value to load register to update the counter register.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_RestartTimer(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_RestartTimer(InstancePtr) \
- XScuTimer_LoadTimer((InstancePtr), \
- XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_LOAD_OFFSET))
-
-/****************************************************************************/
-/**
-*
-* Write to the timer load register. This will also update the
-* timer counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-* @param Value is the count to be loaded in to the load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_LoadTimer(InstancePtr, Value) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_LOAD_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer counter register value. It can be called at any
-* time.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return Contents of the timer counter register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_GetCounterValue(InstancePtr) \
- XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_COUNTER_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Enable auto-reload mode.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_EnableAutoReload(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) | \
- XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
-
-/****************************************************************************/
-/**
-*
-* Disable auto-reload mode.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_DisableAutoReload(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) & \
- ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Enable the Timer interrupt.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_EnableInterrupt(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) | \
- XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
-
-/****************************************************************************/
-/**
-*
-* Disable the Timer interrupt.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_DisableInterrupt(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) & \
- ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
-
-/*****************************************************************************/
-/**
-*
-* This function reads the interrupt status.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_GetInterruptStatus(InstancePtr) \
- XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_ISR_OFFSET)
-
-/*****************************************************************************/
-/**
-*
-* This function clears the interrupt status.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_ClearInterruptStatus(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Lookup configuration in xscutimer_sinit.c
- */
-XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId);
-
-/*
- * Selftest function in xscutimer_selftest.c
- */
-s32 XScuTimer_SelfTest(XScuTimer *InstancePtr);
-
-/*
- * Interface functions in xscutimer.c
- */
-s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
- XScuTimer_Config *ConfigPtr, u32 EffectiveAddress);
-void XScuTimer_Start(XScuTimer *InstancePtr);
-void XScuTimer_Stop(XScuTimer *InstancePtr);
-void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue);
-u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/68/d115c3595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/68/d115c3595243001d18b399c1eb9b3628
deleted file mode 100644
index 9d17f5c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/68/d115c3595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,86 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xtime_l.h
-* @addtogroup a9_time_apis Cortex A9 Time Functions
-*
-* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This
-* counter increases by one at every two processor cycles. These functions can
-* be used to get/set time in the global timer.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 1.00a rp/sdm 11/03/09 Initial release.
-* 3.06a sgd 05/15/12 Updated get/set time functions to make use Global Timer
-* 3.06a asa 06/17/12 Reverted back the changes to make use Global Timer.
-* 3.07a sgd 07/05/12 Updated get/set time functions to make use Global Timer
-* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep
-* implementation
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
-* displaying same warnings multiple times. It fixes CR#1090562.
-*
-*
-******************************************************************************/
-
-/**
-*@cond nocomments
-*/
-
-#ifndef XTIME_H /* prevent circular inclusions */
-#define XTIME_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xparameters.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-typedef u64 XTime;
-
-/************************** Constant Definitions *****************************/
-#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR
-#define GTIMER_COUNTER_LOWER_OFFSET 0x00U
-#define GTIMER_COUNTER_UPPER_OFFSET 0x04U
-#define GTIMER_CONTROL_OFFSET 0x08U
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY)
-#else
-/* Global Timer is always clocked at half of the CPU frequency */
-#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
-#endif
-/************************** Variable Definitions *****************************/
-
-/**
-*@endcond
-*/
-
-/************************** Function Prototypes ******************************/
-
-void XTime_SetTime(XTime Xtime_Global);
-void XTime_GetTime(XTime *Xtime_Global);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XTIME_H */
-/**
-* @} End of "addtogroup a9_time_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/68/e007b7595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/68/e007b7595243001d18b399c1eb9b3628
deleted file mode 100644
index 7e29233..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/68/e007b7595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,165 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_testmem.h
-* @addtogroup common_test_utils Test Utilities for Memory and Caches
-*
-* - Cache test: xil_testcache.h contains utility functions to test cache.
-*
-* - I/O test: The Xil_testio.h file contains endian related memory IO functions. A
-* subset of the memory tests can be selected or all of the tests can be run in order.
-* If there is an error detected by a subtest, the test stops and the failure code is
-* returned. Further tests are not run even if all of the tests are selected.
-*
-* - Memory test: The xil_testmem.h file contains utility functions to test memory.
-* A subset of the memory tests can be selected or all of the tests can be run
-* in order. If there is an error detected by a subtest, the test stops and the
-* failure code is returned. Further tests are not run even if all of the tests are selected.
-*
-*
-* Following list describes the supported memory tests:
-*
-* - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
-*
-* - XIL_TESTMEM_INCREMENT: This test
-* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
-* test value for memory.
-*
-* - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
-* uses a walking '1' as the test value for memory.
-* @code
-* location 1 = 0x00000001
-* location 2 = 0x00000002
-* ...
-* @endcode
-*
-* - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
-* This test uses the inverse value of the walking ones test
-* as the test value for memory.
-* @code
-* location 1 = 0xFFFFFFFE
-* location 2 = 0xFFFFFFFD
-* ...
-*@endcode
-*
-* - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
-* This test uses the inverse of the address of the location under test
-* as the test value for memory.
-*
-* - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
-* This test uses the provided patters as the test value for memory.
-* If zero is provided as the pattern the test uses '0xDEADBEEF".
-*
-* @warning
-* The tests are DESTRUCTIVE. Run before any initialized memory spaces
-* have been set up.
-* The address provided to the memory tests is not checked for
-* validity except for the NULL case. It is possible to provide a code-space
-* pointer for this test to start with and ultimately destroy executable code
-* causing random failures.
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 08/25/09 First release
-* 7.5 mus 03/10/21 Added new set of Xil_TestMem32, Xil_TestMem16 and
-* Xil_TestMem8 APIs to support memory test for memory
-* regions mapped at extended addresses
-* (addresses > 4 GB). These new set of APIs would be
-* compiled only for 32 bit Microblaze processor, if
-* XPAR_MICROBLAZE_ADDR_SIZE is greater than 32.
-* It fixes CR#1089129.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 5.00 pkp 05/29/14 First release
-* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep
-* implementation
-* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
-* displaying same warnings multiple times. It fixes CR#1090562.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00 pkp 02/20/14 First release
-* 5.04 pkp 12/18/15 Updated MPU initialization as per the proper address map
-* 6.00 pkp 06/27/16 moving the Init_MPU code to .boot section since it is a
-* part of processor boot process
-* 6.2 mus 01/27/17 Updated to support IAR compiler
-* 7.1 mus 09/11/19 Added warning message if DDR size is not in power of 2.
-* Fix for CR#1038577.
-* 7.2 asa 04/08/20 Fix warning in the function Init_MPU.
-* 7.5 mus 01/13/21 Removed redundant declaration for Mpu_Config,
-* declaration is present in xil_mpu.h.
-* 7.5 asa 03/07/21 Ensure that Update_MpuConfig_Array stays in .boot section
-* as it is used only during bootup.
-* Add function header to Init_MPU function.
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_printf.h"
-#include "xreg_cortexr5.h"
-#include "xil_mpu.h"
-#include "xpseudo_asm.h"
-#include "xparameters.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-static const struct {
- u64 size;
- unsigned int encoding;
-}region_size[] = {
- { 0x20, REGION_32B },
- { 0x40, REGION_64B },
- { 0x80, REGION_128B },
- { 0x100, REGION_256B },
- { 0x200, REGION_512B },
- { 0x400, REGION_1K },
- { 0x800, REGION_2K },
- { 0x1000, REGION_4K },
- { 0x2000, REGION_8K },
- { 0x4000, REGION_16K },
- { 0x8000, REGION_32K },
- { 0x10000, REGION_64K },
- { 0x20000, REGION_128K },
- { 0x40000, REGION_256K },
- { 0x80000, REGION_512K },
- { 0x100000, REGION_1M },
- { 0x200000, REGION_2M },
- { 0x400000, REGION_4M },
- { 0x800000, REGION_8M },
- { 0x1000000, REGION_16M },
- { 0x2000000, REGION_32M },
- { 0x4000000, REGION_64M },
- { 0x8000000, REGION_128M },
- { 0x10000000, REGION_256M },
- { 0x20000000, REGION_512M },
- { 0x40000000, REGION_1G },
- { 0x80000000, REGION_2G },
- { 0x100000000, REGION_4G },
-};
-
-/************************** Function Prototypes ******************************/
-#if defined (__GNUC__)
-void Init_MPU(void) __attribute__((__section__(".boot")));
-static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib) __attribute__((__section__(".boot")));
-static void Xil_DisableMPURegions(void) __attribute__((__section__(".boot")));
-static inline void Update_MpuConfig_Array(u32 Addr,u32 RegSize,u32 RegNum, u32 Attrib) __attribute__((__section__(".boot")));
-#elif defined (__ICCARM__)
-#pragma default_function_attributes = @ ".boot"
-void Init_MPU(void);
-static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib);
-static void Xil_DisableMPURegions(void);
-#endif
-/*****************************************************************************
-*
-* Initialize MPU for a given address map and Enabled the background Region in
-* MPU with default memory attributes for rest of address range for Cortex R5
-* processor.
-*
-* @param None.
-*
-* @return None.
-*
-*
-******************************************************************************/
-static inline void Update_MpuConfig_Array(u32 Addr,u32 RegSize,u32 RegNum,
- u32 Attrib)
-{
- Mpu_Config[RegNum].RegionStatus = MPU_REG_ENABLED;
- Mpu_Config[RegNum].BaseAddress = Addr;
- Mpu_Config[RegNum].Size = RegSize;
- Mpu_Config[RegNum].Attribute = Attrib;
-}
-
-/*****************************************************************************
-*
-* Initialize MPU for during bootup with predefined region attributes.
-*
-* @param None.
-*
-* @return None.
-*
-*
-******************************************************************************/
-void Init_MPU(void)
-{
- u32 Addr;
- u32 RegSize = 0U;
- u32 Attrib;
- u32 RegNum = 0, i, Offset = 0;
- u64 size;
-
- Xil_DisableMPURegions();
-
- Addr = 0x00000000U;
-#ifdef XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR
- /* If the DDR is present, configure region as per DDR size */
- size = (XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR - XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR) + 1;
- if (size < 0x80000000) {
- /* Lookup the size. */
- for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) {
- if (size <= region_size[i].size) {
- RegSize = region_size[i].encoding;
-
- /* Check if DDR size is in power of 2*/
- if ( XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR == 0x100000)
- Offset = XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR;
- if (region_size[i].size > (size + Offset + 1)) {
- xil_printf ("WARNING: DDR size mapped to Cortexr5 processor is not \
- in power of 2. As processor allocates MPU regions size \
- in power of 2, address range %llx to %x has been \
- incorrectly mapped as normal memory \n", \
- region_size[i].size - 1, ((u32)XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR + 1));
- }
- break;
- }
- }
- } else {
- /* if the DDR size is > 2GB, truncate it to 2GB */
- RegSize = REGION_2G;
- }
-#else
- /* For DDRless system, configure region for TCM */
- RegSize = REGION_256K;
-#endif
- Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /*
- * 1G of strongly ordered memory from 0x80000000 to 0xBFFFFFFF for PL.
- * 512 MB - LPD-PL interface
- * 256 MB - FPD-PL (HPM0) interface
- * 256 MB - FPD-PL (HPM1) interface
- */
- Addr = 0x80000000;
- RegSize = REGION_1G;
- Attrib = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 512M of device memory from 0xC0000000 to 0xDFFFFFFF for QSPI */
- Addr = 0xC0000000U;
- RegSize = REGION_512M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 256M of device memory from 0xE0000000 to 0xEFFFFFFF for PCIe Low */
- Addr = 0xE0000000U;
- RegSize = REGION_256M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 16M of device memory from 0xF8000000 to 0xF8FFFFFF for STM_CORESIGHT */
- Addr = 0xF8000000U;
- RegSize = REGION_16M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 1M of device memory from 0xF9000000 to 0xF90FFFFF for RPU_A53_GIC */
- Addr = 0xF9000000U;
- RegSize = REGION_1M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 16M of device memory from 0xFD000000 to 0xFDFFFFFF for FPS slaves */
- Addr = 0xFD000000U;
- RegSize = REGION_16M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 16M of device memory from 0xFE000000 to 0xFEFFFFFF for Upper LPS slaves */
- Addr = 0xFE000000U;
- RegSize = REGION_16M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /*
- * 16M of device memory from 0xFF000000 to 0xFFFFFFFF for Lower LPS slaves,
- * CSU, PMU, TCM, OCM
- */
- Addr = 0xFF000000U;
- RegSize = REGION_16M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 256K of OCM RAM from 0xFFFC0000 to 0xFFFFFFFF marked as normal memory */
- Addr = 0xFFFC0000U;
- RegSize = REGION_256K;
- Attrib = NORM_NSHARED_WB_WA| PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
-
- /* A total of 10 MPU regions are allocated with another 6 being free for users */
-
-}
-
-/*****************************************************************************
-*
-* Set the memory attributes for a section of memory with starting address addr
-* of the region size defined by reg_size having attributes attrib of region number
-* reg_num
-*
-* @param addr is the address for which attributes are to be set.
-* @param attrib specifies the attributes for that memory region.
-* @param reg_size specifies the size for that memory region.
-* @param reg_num specifies the number for that memory region.
-* @return None.
-*
-*
-******************************************************************************/
-static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib)
-{
- u32 Local_reg_size = reg_size;
-
- Local_reg_size = Local_reg_size<<1U;
- Local_reg_size |= REGION_EN;
- dsb();
- mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num);
- isb();
- mtcp(XREG_CP15_MPU_REG_BASEADDR,addr); /* Set base address of a region */
- mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL,attrib); /* Set the control attribute */
- mtcp(XREG_CP15_MPU_REG_SIZE_EN,Local_reg_size); /* set the region size and enable it*/
- dsb();
- isb(); /* synchronize context on this processor */
-}
-
-
-/*****************************************************************************
-*
-* Disable all the MPU regions if any of them is enabled
-*
-* @param None.
-*
-* @return None.
-*
-*
-******************************************************************************/
-static void Xil_DisableMPURegions(void)
-{
- u32 Temp = 0U;
- u32 Index = 0U;
- for (Index = 0; Index <= 15; Index++) {
- mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index);
-#if defined (__GNUC__)
- Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
-#endif
- Temp &= (~REGION_EN);
- dsb();
- mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
- dsb();
- isb();
- }
-
-}
-
-#if defined (__ICCARM__)
-#pragma default_function_attributes =
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6a/e13151545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6a/e13151545243001d18b399c1eb9b3628
deleted file mode 100644
index edf6684..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6a/e13151545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,558 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpm_counter.h
-*
-* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions
-*
-* Cortex A9 event counter functions can be utilized to configure and control
-* the Cortex-A9 performance monitor events.
-*
-* Cortex-A9 performance monitor has six event counters which can be used to
-* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines
-* configurations XPM_CNTRCFGx which can be used to program the event counters
-* to count a set of events.
-*
-* @note
-* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
-* being used for time keeping.
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-*
-******************************************************************************/
-
-/**
-*@cond nocomments
-*/
-
-#ifndef XPMCOUNTER_H /* prevent circular inclusions */
-#define XPMCOUNTER_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/************************** Constant Definitions ****************************/
-
-/* Number of performance counters */
-#define XPM_CTRCOUNT 6U
-
-/* The following constants define the Cortex-A9 Performance Monitor Events */
-
-/*
- * Software increment. The register is incremented only on writes to the
- * Software Increment Register
- */
-#define XPM_EVENT_SOFTINCR 0x00U
-
-/*
- * Instruction fetch that causes a refill at (at least) the lowest level(s) of
- * instruction or unified cache. Includes the speculative linefills in the
- * count
- */
-#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
-
-/*
- * Instruction fetch that causes a TLB refill at (at least) the lowest level of
- * TLB. Includes the speculative requests in the count
- */
-#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
-
-/*
- * Data read or write operation that causes a refill at (at least) the lowest
- * level(s)of data or unified cache. Counts the number of allocations performed
- * in the Data Cache due to a read or a write
- */
-#define XPM_EVENT_DATA_CACHEREFILL 0x03U
-
-/*
- * Data read or write operation that causes a cache access at (at least) the
- * lowest level(s) of data or unified cache. This includes speculative reads
- */
-#define XPM_EVENT_DATA_CACHEACCESS 0x04U
-
-/*
- * Data read or write operation that causes a TLB refill at (at least) the
- * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
- * CP15 Cache operation by MVA and CP15 VA to PA operations
- */
-#define XPM_EVENT_DATA_TLBREFILL 0x05U
-
-/*
- * Data read architecturally executed. Counts the number of data read
- * instructions accepted by the Load Store Unit. This includes counting the
- * speculative and aborted LDR/LDM, as well as the reads due to the SWP
- * instructions
- */
-#define XPM_EVENT_DATA_READS 0x06U
-
-/*
- * Data write architecturally executed. Counts the number of data write
- * instructions accepted by the Load Store Unit. This includes counting the
- * speculative and aborted STR/STM, as well as the writes due to the SWP
- * instructions
- */
-#define XPM_EVENT_DATA_WRITE 0x07U
-
-/* Exception taken. Counts the number of exceptions architecturally taken.*/
-#define XPM_EVENT_EXCEPTION 0x09U
-
-/* Exception return architecturally executed.*/
-#define XPM_EVENT_EXCEPRETURN 0x0AU
-
-/*
- * Change to ContextID retired. Counts the number of instructions
- * architecturally executed writing into the ContextID Register
- */
-#define XPM_EVENT_CHANGECONTEXT 0x0BU
-
-/*
- * Software change of PC, except by an exception, architecturally executed.
- * Count the number of PC changes architecturally executed, excluding the PC
- * changes due to taken exceptions
- */
-#define XPM_EVENT_SW_CHANGEPC 0x0CU
-
-/*
- * Immediate branch architecturally executed (taken or not taken). This includes
- * the branches which are flushed due to a previous load/store which aborts
- * late
- */
-#define XPM_EVENT_IMMEDBRANCH 0x0DU
-
-/*
- * Unaligned access architecturally executed. Counts the number of aborted
- * unaligned accessed architecturally executed, and the number of not-aborted
- * unaligned accesses, including the speculative ones
- */
-#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
-
-/*
- * Branch mispredicted/not predicted. Counts the number of mispredicted or
- * not-predicted branches executed. This includes the branches which are flushed
- * due to a previous load/store which aborts late
- */
-#define XPM_EVENT_BRANCHMISS 0x10U
-
-/*
- * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
- * event is not exported on the PMUEVENT bus
- */
-#define XPM_EVENT_CLOCKCYCLES 0x11U
-
-/*
- * Branches or other change in program flow that could have been predicted by
- * the branch prediction resources of the processor. This includes the branches
- * which are flushed due to a previous load/store which aborts late
- */
-#define XPM_EVENT_BRANCHPREDICT 0x12U
-
-/*
- * Java bytecode execute. Counts the number of Java bytecodes being decoded,
- * including speculative ones
- */
-#define XPM_EVENT_JAVABYTECODE 0x40U
-
-/*
- * Software Java bytecode executed. Counts the number of software java bytecodes
- * being decoded, including speculative ones
- */
-#define XPM_EVENT_SWJAVABYTECODE 0x41U
-
-/*
- * Jazelle backward branches executed. Counts the number of Jazelle taken
- * branches being executed. This includes the branches which are flushed due
- * to a previous load/store which aborts late
- */
-#define XPM_EVENT_JAVABACKBRANCH 0x42U
-
-/*
- * Coherent linefill miss Counts the number of coherent linefill requests
- * performed by the Cortex-A9 processor which also miss in all the other
- * Cortex-A9 processors, meaning that the request is sent to the external
- * memory
- */
-#define XPM_EVENT_COHERLINEMISS 0x50U
-
-/*
- * Coherent linefill hit. Counts the number of coherent linefill requests
- * performed by the Cortex-A9 processor which hit in another Cortex-A9
- * processor, meaning that the linefill data is fetched directly from the
- * relevant Cortex-A9 cache
- */
-#define XPM_EVENT_COHERLINEHIT 0x51U
-
-/*
- * Instruction cache dependent stall cycles. Counts the number of cycles where
- * the processor is ready to accept new instructions, but does not receive any
- * due to the instruction side not being able to provide any and the
- * instruction cache is currently performing at least one linefill
- */
-#define XPM_EVENT_INSTRSTALL 0x60U
-
-/*
- * Data cache dependent stall cycles. Counts the number of cycles where the core
- * has some instructions that it cannot issue to any pipeline, and the Load
- * Store unit has at least one pending linefill request, and no pending
- */
-#define XPM_EVENT_DATASTALL 0x61U
-
-/*
- * Main TLB miss stall cycles. Counts the number of cycles where the processor
- * is stalled waiting for the completion of translation table walks from the
- * main TLB. The processor stalls can be due to the instruction side not being
- * able to provide the instructions, or to the data side not being able to
- * provide the necessary data, due to them waiting for the main TLB translation
- * table walk to complete
- */
-#define XPM_EVENT_MAINTLBSTALL 0x62U
-
-/*
- * Counts the number of STREX instructions architecturally executed and
- * passed
- */
-#define XPM_EVENT_STREXPASS 0x63U
-
-/*
- * Counts the number of STREX instructions architecturally executed and
- * failed
- */
-#define XPM_EVENT_STREXFAIL 0x64U
-
-/*
- * Data eviction. Counts the number of eviction requests due to a linefill in
- * the data cache
- */
-#define XPM_EVENT_DATAEVICT 0x65U
-
-/*
- * Counts the number of cycles where the issue stage does not dispatch any
- * instruction because it is empty or cannot dispatch any instructions
- */
-#define XPM_EVENT_NODISPATCH 0x66U
-
-/*
- * Counts the number of cycles where the issue stage is empty
- */
-#define XPM_EVENT_ISSUEEMPTY 0x67U
-
-/*
- * Counts the number of instructions going through the Register Renaming stage.
- * This number is an approximate number of the total number of instructions
- * speculatively executed, and even more approximate of the total number of
- * instructions architecturally executed. The approximation depends mainly on
- * the branch misprediction rate.
- * The renaming stage can handle two instructions in the same cycle so the event
- * is two bits long:
- * - b00 no instructions renamed
- * - b01 one instruction renamed
- * - b10 two instructions renamed
- */
-#define XPM_EVENT_INSTRRENAME 0x68U
-
-/*
- * Counts the number of procedure returns whose condition codes do not fail,
- * excluding all returns from exception. This count includes procedure returns
- * which are flushed due to a previous load/store which aborts late.
- * Only the following instructions are reported:
- * - BX R14
- * - MOV PC LR
- * - POP {..,pc}
- * - LDR pc,[sp],#offset
- * The following instructions are not reported:
- * - LDMIA R9!,{..,PC} (ThumbEE state only)
- * - LDR PC,[R9],#offset (ThumbEE state only)
- * - BX R0 (Rm != R14)
- * - MOV PC,R0 (Rm != R14)
- * - LDM SP,{...,PC} (writeback not specified)
- * - LDR PC,[SP,#offset] (wrong addressing mode)
- */
-#define XPM_EVENT_PREDICTFUNCRET 0x6EU
-
-/*
- * Counts the number of instructions being executed in the main execution
- * pipeline of the processor, the multiply pipeline and arithmetic logic unit
- * pipeline. The counted instructions are still speculative
- */
-#define XPM_EVENT_MAINEXEC 0x70U
-
-/*
- * Counts the number of instructions being executed in the processor second
- * execution pipeline (ALU). The counted instructions are still speculative
- */
-#define XPM_EVENT_SECEXEC 0x71U
-
-/*
- * Counts the number of instructions being executed in the Load/Store unit. The
- * counted instructions are still speculative
- */
-#define XPM_EVENT_LDRSTR 0x72U
-
-/*
- * Counts the number of Floating-point instructions going through the Register
- * Rename stage. Instructions are still speculative in this stage.
- *Two floating-point instructions can be renamed in the same cycle so the event
- * is two bitslong:
- *0b00 no floating-point instruction renamed
- *0b01 one floating-point instruction renamed
- *0b10 two floating-point instructions renamed
- */
-#define XPM_EVENT_FLOATRENAME 0x73U
-
-/*
- * Counts the number of Neon instructions going through the Register Rename
- * stage.Instructions are still speculative in this stage.
- * Two NEON instructions can be renamed in the same cycle so the event is two
- * bits long:
- *0b00 no NEON instruction renamed
- *0b01 one NEON instruction renamed
- *0b10 two NEON instructions renamed
- */
-#define XPM_EVENT_NEONRENAME 0x74U
-
-/*
- * Counts the number of cycles where the processor is stalled because PLD slots
- * are all full
- */
-#define XPM_EVENT_PLDSTALL 0x80U
-
-/*
- * Counts the number of cycles when the processor is stalled and the data side
- * is stalled too because it is full and executing writes to the external
- * memory
- */
-#define XPM_EVENT_WRITESTALL 0x81U
-
-/*
- * Counts the number of stall cycles due to main TLB misses on requests issued
- * by the instruction side
- */
-#define XPM_EVENT_INSTRTLBSTALL 0x82U
-
-/*
- * Counts the number of stall cycles due to main TLB misses on requests issued
- * by the data side
- */
-#define XPM_EVENT_DATATLBSTALL 0x83U
-
-/*
- * Counts the number of stall cycles due to micro TLB misses on the instruction
- * side. This event does not include main TLB miss stall cycles that are already
- * counted in the corresponding main TLB event
- */
-#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
-
-/*
- * Counts the number of stall cycles due to micro TLB misses on the data side.
- * This event does not include main TLB miss stall cycles that are already
- * counted in the corresponding main TLB event
- */
-#define XPM_EVENT_DATA_uTLBSTALL 0x85U
-
-/*
- * Counts the number of stall cycles because of the execution of a DMB memory
- * barrier. This includes all DMB instructions being executed, even
- * speculatively
- */
-#define XPM_EVENT_DMB_STALL 0x86U
-
-/*
- * Counts the number of cycles during which the integer core clock is enabled
- */
-#define XPM_EVENT_INT_CLKEN 0x8AU
-
-/*
- * Counts the number of cycles during which the Data Engine clock is enabled
- */
-#define XPM_EVENT_DE_CLKEN 0x8BU
-
-/*
- * Counts the number of ISB instructions architecturally executed
- */
-#define XPM_EVENT_INSTRISB 0x90U
-
-/*
- * Counts the number of DSB instructions architecturally executed
- */
-#define XPM_EVENT_INSTRDSB 0x91U
-
-/*
- * Counts the number of DMB instructions speculatively executed
- */
-#define XPM_EVENT_INSTRDMB 0x92U
-
-/*
- * Counts the number of external interrupts executed by the processor
- */
-#define XPM_EVENT_EXTINT 0x93U
-
-/*
- * PLE cache line request completed
- */
-#define XPM_EVENT_PLE_LRC 0xA0U
-
-/*
- * PLE cache line request skipped
- */
-#define XPM_EVENT_PLE_LRS 0xA1U
-
-/*
- * PLE FIFO flush
- */
-#define XPM_EVENT_PLE_FLUSH 0xA2U
-
-/*
- * PLE request complete
- */
-#define XPM_EVENT_PLE_CMPL 0xA3U
-
-/*
- * PLE FIFO overflow
- */
-#define XPM_EVENT_PLE_OVFL 0xA4U
-
-/*
- * PLE request programmed
- */
-#define XPM_EVENT_PLE_PROG 0xA5U
-
-/*
- * The following constants define the configurations for Cortex-A9 Performance
- * Monitor Events. Each configuration configures the event counters for a set
- * of events.
- * -----------------------------------------------
- * Config PmCtr0... PmCtr5
- * -----------------------------------------------
- * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR,
- * XPM_EVENT_INSRFETCH_CACHEREFILL,
- * XPM_EVENT_INSTRFECT_TLBREFILL,
- * XPM_EVENT_DATA_CACHEREFILL,
- * XPM_EVENT_DATA_CACHEACCESS,
- * XPM_EVENT_DATA_TLBREFILL }
- *
- * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS,
- * XPM_EVENT_DATA_WRITE,
- * XPM_EVENT_EXCEPTION,
- * XPM_EVENT_EXCEPRETURN,
- * XPM_EVENT_CHANGECONTEXT,
- * XPM_EVENT_SW_CHANGEPC }
- *
- * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH,
- * XPM_EVENT_UNALIGNEDACCESS,
- * XPM_EVENT_BRANCHMISS,
- * XPM_EVENT_CLOCKCYCLES,
- * XPM_EVENT_BRANCHPREDICT,
- * XPM_EVENT_JAVABYTECODE }
- *
- * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE,
- * XPM_EVENT_JAVABACKBRANCH,
- * XPM_EVENT_COHERLINEMISS,
- * XPM_EVENT_COHERLINEHIT,
- * XPM_EVENT_INSTRSTALL,
- * XPM_EVENT_DATASTALL }
- *
- * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL,
- * XPM_EVENT_STREXPASS,
- * XPM_EVENT_STREXFAIL,
- * XPM_EVENT_DATAEVICT,
- * XPM_EVENT_NODISPATCH,
- * XPM_EVENT_ISSUEEMPTY }
- *
- * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME,
- * XPM_EVENT_PREDICTFUNCRET,
- * XPM_EVENT_MAINEXEC,
- * XPM_EVENT_SECEXEC,
- * XPM_EVENT_LDRSTR,
- * XPM_EVENT_FLOATRENAME }
- *
- * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME,
- * XPM_EVENT_PLDSTALL,
- * XPM_EVENT_WRITESTALL,
- * XPM_EVENT_INSTRTLBSTALL,
- * XPM_EVENT_DATATLBSTALL,
- * XPM_EVENT_INSTR_uTLBSTALL }
- *
- * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL,
- * XPM_EVENT_DMB_STALL,
- * XPM_EVENT_INT_CLKEN,
- * XPM_EVENT_DE_CLKEN,
- * XPM_EVENT_INSTRISB,
- * XPM_EVENT_INSTRDSB }
- *
- * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB,
- * XPM_EVENT_EXTINT,
- * XPM_EVENT_PLE_LRC,
- * XPM_EVENT_PLE_LRS,
- * XPM_EVENT_PLE_FLUSH,
- * XPM_EVENT_PLE_CMPL }
- *
- * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL,
- * XPM_EVENT_PLE_PROG,
- * XPM_EVENT_PLE_LRC,
- * XPM_EVENT_PLE_LRS,
- * XPM_EVENT_PLE_FLUSH,
- * XPM_EVENT_PLE_CMPL }
- *
- * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL,
- * XPM_EVENT_INSRFETCH_CACHEREFILL,
- * XPM_EVENT_INSTRFECT_TLBREFILL,
- * XPM_EVENT_DATA_CACHEREFILL,
- * XPM_EVENT_DATA_CACHEACCESS,
- * XPM_EVENT_DATA_TLBREFILL }
- */
-#define XPM_CNTRCFG1 0
-#define XPM_CNTRCFG2 1
-#define XPM_CNTRCFG3 2
-#define XPM_CNTRCFG4 3
-#define XPM_CNTRCFG5 4
-#define XPM_CNTRCFG6 5
-#define XPM_CNTRCFG7 6
-#define XPM_CNTRCFG8 7
-#define XPM_CNTRCFG9 8
-#define XPM_CNTRCFG10 9
-#define XPM_CNTRCFG11 10
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/**
-*@endcond
-*/
-
-/************************** Function Prototypes *****************************/
-
-/* Interface functions to access performance counters from abstraction layer */
-void Xpm_SetEvents(s32 PmcrCfg);
-void Xpm_GetEventCounters(u32 *PmCtrValue);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-* @} End of "addtogroup a9_event_counter_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6a/e223ee565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6a/e223ee565243001d18b399c1eb9b3628
deleted file mode 100644
index 1d18bfb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6a/e223ee565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,203 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_types.h
-*
-* @addtogroup common_types Basic Data types for Xilinx® Software IP
-*
-* The xil_types.h file contains basic types for Xilinx software IP. These data types
-* are applicable for all processors supported by Xilinx.
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 First release
-* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
-* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
-* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
-* Define LONG and ULONG datatypes and mask values
-* 7.00 mus 01/07/19 Add cpp extern macro
-* 7.1 aru 08/19/19 Shift the value in UPPER_32_BITS only if it
-* is 64-bit processor
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-#ifndef XIL_TYPES_H /* prevent circular inclusions */
-#define XIL_TYPES_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include
-#include
-
-/************************** Constant Definitions *****************************/
-
-#ifndef TRUE
-# define TRUE 1U
-#endif
-
-#ifndef FALSE
-# define FALSE 0U
-#endif
-
-#ifndef NULL
-#define NULL 0U
-#endif
-
-#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be
- assigend to "IsReady" member of driver
- instance to indicate that driver
- instance is initialized and ready to use. */
-#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to
- "IsStarted" member of driver instance
- to indicate that driver instance is
- started and it can be enabled. */
-
-/* @name New types
- * New simple types.
- * @{
- */
-#ifndef __KERNEL__
-#ifndef XBASIC_TYPES_H
-/*
- * guarded against xbasic_types.h.
- */
-typedef uint8_t u8;
-typedef uint16_t u16;
-typedef uint32_t u32;
-/** @}*/
-#define __XUINT64__
-typedef struct
-{
- u32 Upper;
- u32 Lower;
-} Xuint64;
-
-
-/*****************************************************************************/
-/**
-* @brief Return the most significant half of the 64 bit data type.
-*
-* @param x is the 64 bit word.
-*
-* @return The upper 32 bits of the 64 bit word.
-*
-******************************************************************************/
-#define XUINT64_MSW(x) ((x).Upper)
-
-/*****************************************************************************/
-/**
-* @brief Return the least significant half of the 64 bit data type.
-*
-* @param x is the 64 bit word.
-*
-* @return The lower 32 bits of the 64 bit word.
-*
-******************************************************************************/
-#define XUINT64_LSW(x) ((x).Lower)
-
-#endif /* XBASIC_TYPES_H */
-
-/*
- * xbasic_types.h does not typedef s* or u64
- */
-/** @{ */
-typedef char char8;
-typedef int8_t s8;
-typedef int16_t s16;
-typedef int32_t s32;
-typedef int64_t s64;
-typedef uint64_t u64;
-typedef int sint32;
-
-typedef intptr_t INTPTR;
-typedef uintptr_t UINTPTR;
-typedef ptrdiff_t PTRDIFF;
-/** @}*/
-#if !defined(LONG) || !defined(ULONG)
-typedef long LONG;
-typedef unsigned long ULONG;
-#endif
-
-#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
-#define ULONG64_LO_MASK ~ULONG64_HI_MASK
-
-#else
-#include
-#endif
-
-/** @{ */
-/**
- * This data type defines an interrupt handler for a device.
- * The argument points to the instance of the component
- */
-typedef void (*XInterruptHandler) (void *InstancePtr);
-
-/**
- * This data type defines an exception handler for a processor.
- * The argument points to the instance of the component
- */
-typedef void (*XExceptionHandler) (void *InstancePtr);
-
-/**
- * @brief Returns 32-63 bits of a number.
- * @param n : Number being accessed.
- * @return Bits 32-63 of number.
- *
- * @note A basic shift-right of a 64- or 32-bit quantity.
- * Use this to suppress the "right shift count >= width of type"
- * warning when that quantity is 32-bits.
- */
-#if defined (__aarch64__) || defined (__arch64__)
-#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
-#else
-#define UPPER_32_BITS(n) 0U
-#endif
-/**
- * @brief Returns 0-31 bits of a number
- * @param n : Number being accessed.
- * @return Bits 0-31 of number
- */
-#define LOWER_32_BITS(n) ((u32)(n))
-
-
-
-
-/************************** Constant Definitions *****************************/
-
-#ifndef TRUE
-#define TRUE 1U
-#endif
-
-#ifndef FALSE
-#define FALSE 0U
-#endif
-
-#ifndef NULL
-#define NULL 0U
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
- *@endcond
- */
-/**
-* @} End of "addtogroup common_types".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6b/718724555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6b/718724555243001d18b399c1eb9b3628
deleted file mode 100644
index 150a298..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6b/718724555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,408 +0,0 @@
-;/******************************************************************************
-;* Copyright (c) 2019 - 2021 Xilinx, Inc. All rights reserved.
-;* SPDX-License-Identifier: MIT
-;******************************************************************************/
-;/*****************************************************************************/
-;/**
-;* @file boot.S
-;*
-;* @addtogroup a53_64_boot_code Cortex A53 64bit Processor Boot Code
-;* @{
-;*
boot.S
-;*
-;* The boot code performs minimum configuration which is required for an
-;* application. Cortex-A53 starts by checking current exception level. If the
-;* current exception level is EL3 and BSP is built for EL3, it will do
-;* initialization required for application execution at EL3. Below is a
-;* sequence illustrating what all configuration is performed before control
-;* reaches to main function for EL3 execution.
-;*
-;* 1. Program vector table base for exception handling
-;* 2. Set reset vector table base address
-;* 3. Program stack pointer for EL3
-;* 4. Routing of interrupts to EL3
-;* 5. Enable ECC protection
-;* 6. Program generic counter frequency
-;* 7. Invalidate instruction cache, data cache and TLBs
-;* 8. Configure MMU registers and program base address of translation table
-;* 9. Transfer control to _start which clears BSS sections and runs global
-;* constructor before jumping to main application
-;*
-;* If current exception level is EL1 and BSP is also built for EL1_NONSECURE
-;* it will perform initialization required for application execution at EL1
-;* non-secure. For all other combination, the execution will go into infinite
-;* loop. Below is a sequence illustrating what all configuration is performed
-;* before control reaches to main function for EL1 execution.
-;*
-;* 1. Program vector table base for exception handling
-;* 2. Program stack pointer for EL1
-;* 3. Invalidate instruction cache, data cache and TLBs
-;* 4. Configure MMU registers and program base address of translation table
-;* 5. Transfer control to _start which clears BSS sections and runs global
-;* constructor before jumping to main application
-;*
-;*
-;* MODIFICATION HISTORY:
-;*
-;* Ver Who Date Changes
-;* ----- ------- -------- ---------------------------------------------------
-;* 7.0 mus 02/26/19 First release
-;* 7.2 mus 01/08/19 Added support for versal
-;* sd 02/23/20 Clock Init is called
-;* sd 03/21/20 Added XCLOCKING flag
-;*
-;******************************************************************************/
-
-#include "xparameters.h"
-#include "bspconfig.h"
-#include "xil_errata.h"
-
- EXPORT _prestart
- EXPORT _boot
-
- IMPORT MMUTableL0
- IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base|
- IMPORT _vector_table
- IMPORT __main
-#ifdef XCLOCKING
- IMPORT Xil_ClockInit
-#endif
-
-#ifndef FREERTOS_BSP
- IMPORT FPUStatus
-#endif
-
-rvbar_base EQU 0xFD5C0040
-MODE_EL1 EQU 0x5
-DAIF_BIT EQU 0x1C0
-TT_S1_FAULT EQU 0x0
-TT_S1_TABLE EQU 0x3
-
- AREA |.boot|, CODE
-
-; This initializes the various processor modes
-
-_prestart
-_boot
- mov x0, #0
- mov x1, #0
- mov x2, #0
- mov x3, #0
- mov x4, #0
- mov x5, #0
- mov x6, #0
- mov x7, #0
- mov x8, #0
- mov x9, #0
- mov x10, #0
- mov x11, #0
- mov x12, #0
- mov x13, #0
- mov x14, #0
- mov x15, #0
- mov x16, #0
- mov x17, #0
- mov x18, #0
- mov x19, #0
- mov x20, #0
- mov x21, #0
- mov x22, #0
- mov x23, #0
- mov x24, #0
- mov x25, #0
- mov x26, #0
- mov x27, #0
- mov x28, #0
- mov x29, #0
- mov x30, #0
-
-OKToRun
- mrs x0, currentEL
- cmp x0, #0xC
- beq InitEL3
- cmp x0, #0x4
- beq InitEL1
- b error ; Go to error if current exception level is neither EL3 nor EL1
-
-
-InitEL3
-#if (EL3 == 1)
- ldr x1, =_vector_table ; Set vector table base address
- msr VBAR_EL3, x1
- mrs x0, MPIDR_EL1 ; Get the CPU ID
- and x0, x0, #0xFF
- mov w0, w0
- ldr w2, =rvbar_base ; Calculate the rvbar base address for particular CPU core
- mov w3, #0x8
- mul w0, w0, w3
- add w2, w2, w0
- str x1, [x2] ; Store vector base address to rvbar
- ldr x2, =|Image$$ARM_LIB_STACK$$ZI$$Base| ; Define stack pointer for current exception level
- mov sp, x2
-
- mov x0, #0 ; Enable Trapping of SIMD/FPU register for standalone BSP
-#ifndef FREERTOS_BSP
- orr x0, x0, #(0x1 << 10)
-#endif
- msr CPTR_EL3, x0
- isb
-
-;
-; Clear FPUStatus variable to make sure that it contains current
-; status of FPU i.e. disabled. In case of a warm restart execution
-; when bss sections are not cleared, it may contain previously updated
-; value which does not hold true now
-;
-#ifndef FREERTOS_BSP
- ldr x0, =FPUStatus
- str xzr, [x0]
-#endif
-
-; Configure SCR_EL3
- mov w1, #0 ; Initial value of register is unknown
- orr w1, w1, #(1 << 11) ; Set ST bit (Secure EL1 can access CNTPS_TVAL_EL1, CNTPS_CTL_EL1 & CNTPS_CVAL_EL1)
- orr w1, w1, #(1 << 10) ; Set RW bit (EL1 is AArch64, as this is the Secure world)
- orr w1, w1, #(1 << 3) ; Set EA bit (SError routed to EL3)
- orr w1, w1, #(1 << 2) ; Set FIQ bit (FIQs routed to EL3)
- orr w1, w1, #(1 << 1) ; Set IRQ bit (IRQs routed to EL3)
- msr SCR_EL3, x1
-
-; Configure cpu auxiliary control register EL1
- ldr x0, =0x80CA000 ; L1 Data prefetch control - 5, Enable device split throttle, 2 independent data prefetch streams
-#if (CONFIG_ARM_ERRATA_855873)
-;
-; Set ENDCCASCI bit in CPUACTLR_EL1 register, to execute data
-; cache clean operations as data cache clean and invalidate
-;
- orr x0, x0, #(1 << 44) ; Set ENDCCASCI bit
-#endif
- msr S3_1_C15_C2_0, x0 ; CPUACTLR_EL1
-
-; Program the counter frequency
-#if defined (versal)
- ldr x0, =XPAR_CPU_CORTEXA72_0_TIMESTAMP_CLK_FREQ
-#else
- ldr x0, =XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ
- msr CNTFRQ_EL0, x0
-#endif
-
-; Enable hardware coherency between cores
- mrs x0, S3_1_c15_c2_1 ; Read EL1 CPU Extended Control Register
- orr x0, x0, #(1 << 6) ; Set the SMPEN bit
- msr S3_1_c15_c2_1, x0 ; Write EL1 CPU Extended Control Register
- isb
-
- tlbi ALLE3
- ic IALLU ; Invalidate I cache to PoU
- bl invalidate_dcaches
- dsb sy
- isb
-
- ldr x1, =MMUTableL0 ; Get address of level 0 for TTBR0_EL3
- msr TTBR0_EL3, x1 ; Set TTBR0_EL3
-
-;
-; Set up memory attributes
-; This equates to:
-; 0 = b01000100 = Normal, Inner/Outer Non-Cacheable
-; 1 = b11111111 = Normal, Inner/Outer WB/WA/RA
-; 2 = b00000000 = Device-nGnRnE
-; 3 = b00000100 = Device-nGnRE
-; 4 = b10111011 = Normal, Inner/Outer WT/WA/RA
-;
- ldr x1, =0x000000BB0400FF44
- msr MAIR_EL3, x1
-#if defined (versal)
-; Set up TCR_EL3
-; Physical Address Size PS = 100 -> 44bits 16 TB
-; Granual Size TG0 = 00 -> 4KB
-; size offset of the memory region T0SZ = 20 -> (region size 2^(64-20) = 2^44)
- ldr x1,=0x80843514
-#else
-;
-; Set up TCR_EL3
-; Physical Address Size PS = 010 -> 40bits 1TB
-; Granule Size TG0 = 00 -> 4KB
-; Size offset of the memory region T0SZ = 24 -> (region size 2^(64-24) = 2^40)
-;
- ldr x1, =0x80823518
-#endif
- msr TCR_EL3, x1
- isb
-
-
-; Enable SError Exception for asynchronous abort
- mrs x1, DAIF
- mov x2, #(0x1<<8)
- bic x1, x1, x2
- msr DAIF, x1
-
-
-; Configure SCTLR_EL3
- mov x1, #0 ; Most of the SCTLR_EL3 bits are unknown at reset
- orr x1, x1, #(1 << 12) ; Enable I cache
- orr x1, x1, #(1 << 3) ; Enable SP alignment check
- orr x1, x1, #(1 << 2) ; Enable caches
- orr x1, x1, #(1 << 0) ; Enable MMU
- msr SCTLR_EL3, x1
- dsb sy
- isb
-
-#ifdef XCLOCKING
- b Xil_Clockinit
-#endif
- b __main ; Jump to start
-
-#else
- b error ; Present exception level and selected exception level mismatch
-
-#endif
-
-InitEL1
-#if (EL1_NONSECURE == 1)
- ldr x1, =_vector_table ; Set vector table base address
-
- msr VBAR_EL1, x1
- mrs x0, CPACR_EL1
- mov x2, #(0x3 << 0x20)
- bic x0, x0, x2
- msr CPACR_EL1, x0
- isb
-
-;
-; Clear FPUStatus variable to make sure that it contains current
-; status of FPU i.e. disabled. In case of a warm restart execution
-; when bss sections are not cleared, it may contain previously updated
-; value which does not hold true now
-;
-#ifndef FREERTOS_BSP
- ldr x0, =FPUStatus
- str xzr, [x0]
-#endif
- ldr x2, =|Image$$ARM_LIB_STACK$$ZI$$Base| ; Define stack pointer for current exception level
- mov sp, x2
-
-; Disable MMU
- mov x1, #0x0
- msr SCTLR_EL1, x1
- isb
-
- TLBI VMALLE1
- ic IALLU ; Invalidate I cache to PoU
- bl invalidate_dcaches
- dsb sy
- isb
-
- ldr x1, =MMUTableL0 ; Get address of level 0 for TTBR0_EL1
- msr TTBR0_EL1, x1 ; Set TTBR0_EL1
-
-;
-; Set up memory attributes
-; This equates to:
-; 0 = b01000100 = Normal, Inner/Outer Non-Cacheable
-; 1 = b11111111 = Normal, Inner/Outer WB/WA/RA
-; 2 = b00000000 = Device-nGnRnE
-; 3 = b00000100 = Device-nGnRE
-; 4 = b10111011 = Normal, Inner/Outer WT/WA/RA
-;
- ldr x1, =0x000000BB0400FF44
- msr MAIR_EL1, x1
-
-#if defined (versal)
-;
-; Set up TCR_EL1
-; Physical Address Size PS = 100 -> 44bits 16TB
-; Granual Size TG0 = 00 -> 4KB
-; size offset of the memory region T0SZ = 20 -> (region size 2^(64-20) = 2^44)
-;
- ldr x1,=0x485800514
-#else
-;
-; Set up TCR_EL1
-; Physical Address Size PS = 010 -> 40bits 1TB
-; Granule Size TG0 = 00 -> 4KB
-; Size offset of the memory region T0SZ = 24 -> (region size 2^(64-24) = 2^40)
-;
- ldr x1, =0x285800518
-#endif
- msr TCR_EL1, x1
- isb
-
-
-; Enable SError Exception for asynchronous abort
- mrs x1,DAIF
- mov x2, #(0x1<<8)
- bic x1,x1,x2
- msr DAIF,x1
-
-
-; Enable MMU
- mov x1,#0x0
- orr x1, x1, #(1 << 18) ; Set WFE non trapping
- orr x1, x1, #(1 << 17) ; Set WFI non trapping
- orr x1, x1, #(1 << 5) ; Set CP15 barrier enabled
- orr x1, x1, #(1 << 12) ; Set I bit
- orr x1, x1, #(1 << 2) ; Set C bit
- orr x1, x1, #(1 << 0) ; Set M bit
- msr SCTLR_EL1, x1
- isb
-
- bl __main ; Jump to start
-#else
- b error ; present exception level and selected exception level mismatch
-#endif
-
-error
- b error
-
-invalidate_dcaches
- dmb ISH
- mrs x0, CLIDR_EL1 ; x0 = CLIDR
- ubfx w2, w0, #24, #3 ; w2 = CLIDR>Loc
- cmp w2, #0 ; LoC is 0?
- b.eq invalidateCaches_end ; No cleaning required and enable MMU
- mov w1, #0 ; w1 = level iterator
-
-invalidateCaches_flush_level
- add w3, w1, w1, lsl #1 ; w3 = w1 * 3 (right-shift for cache type)
- lsr w3, w0, w3 ; w3 = w0 >> w3
- ubfx w3, w3, #0, #3 ; w3 = cache type of this level
- cmp w3, #2 ; No cache at this level?
- b.lt invalidateCaches_next_level
- lsl w4, w1, #1
- msr CSSELR_EL1, x4 ; Select current cache level in CSSELR
- isb ; ISB required to reflect new CSIDR
- mrs x4, CCSIDR_EL1 ; w4 = CSIDR
- ubfx w3, w4, #0, #3
- add w3, w3, #2 ; w3 = log2(line size)
- ubfx w5, w4, #13, #15
- ubfx w4, w4, #3, #10 ; w4 = Way number
- clz w6, w4 ; w6 = 32 - log2(number of ways)
-
-invalidateCaches_flush_set
- mov w8, w4 ; w8 = Way number
-
-invalidateCaches_flush_way
- lsl w7, w1, #1 ; Fill level field
- lsl w9, w5, w3
- orr w7, w7, w9 ; Fill index field
- lsl w9, w8, w6
- orr w7, w7, w9 ; Fill way field
- dc CISW, x7 ; Invalidate by set/way to point of coherency
- subs w8, w8, #1 ; Decrement way
- b.ge invalidateCaches_flush_way
- subs w5, w5, #1 ; Decrement set
- b.ge invalidateCaches_flush_set
-
-invalidateCaches_next_level
- add w1, w1, #1 ; Next level
- cmp w2, w1
- b.gt invalidateCaches_flush_level
-
-invalidateCaches_end
- ret
-
- END
-;
-; @} End of "addtogroup a53_64_boot_code"
-;
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6b/f0ca26585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6b/f0ca26585243001d18b399c1eb9b3628
deleted file mode 100644
index 7834953..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6b/f0ca26585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,31 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 2021.2
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2022 Xilinx, Inc. All Rights Reserved.
-* SPDX-License-Identifier: MIT
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xscuwdt.h"
-
-/*
-* The configuration table for devices
-*/
-
-XScuWdt_Config XScuWdt_ConfigTable[XPAR_XSCUWDT_NUM_INSTANCES] =
-{
- {
- XPAR_PS7_SCUWDT_0_DEVICE_ID,
- XPAR_PS7_SCUWDT_0_BASEADDR
- }
-};
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6c/01cd41585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6c/01cd41585243001d18b399c1eb9b3628
deleted file mode 100644
index 3438d96..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6c/01cd41585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1 +0,0 @@
-collect (PROJECT_LIB_HEADERS xparameters_ps.h)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6c/318dfd565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6c/318dfd565243001d18b399c1eb9b3628
deleted file mode 100644
index a2443fe..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6c/318dfd565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,100 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xtime_l.c
-*
-* This file contains low level functions to get/set time from the Global Timer
-* register in the ARM Cortex A9 MP core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 1.00a rp/sdm 11/03/09 Initial release.
-* 3.07a sgd 07/05/12 Updated get/set time functions to make use Global Timer
-* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
-* displaying same warnings multiple times. It fixes CR#1090562.
-*
-*
-* @note None.
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "xtime_l.h"
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER)
-#pragma message ("For the sleep routines, Global timer is being used")
-#endif
-/****************************************************************************/
-/**
-* @brief Set the time in the Global Timer Counter Register.
-*
-* @param Xtime_Global: 64-bit Value to be written to the Global Timer
-* Counter Register.
-*
-* @return None.
-*
-* @note When this function is called by any one processor in a multi-
-* processor environment, reference time will reset/lost for all
-* processors.
-*
-****************************************************************************/
-void XTime_SetTime(XTime Xtime_Global)
-{
- /* Disable Global Timer */
- Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x0);
-
- /* Updating Global Timer Counter Register */
- Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_LOWER_OFFSET, (u32)Xtime_Global);
- Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_UPPER_OFFSET,
- (u32)((u32)(Xtime_Global>>32U)));
-
- /* Enable Global Timer */
- Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x1);
-}
-
-/****************************************************************************/
-/**
-* @brief Get the time from the Global Timer Counter Register.
-*
-* @param Xtime_Global: Pointer to the 64-bit location which will be
-* updated with the current timer value.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XTime_GetTime(XTime *Xtime_Global)
-{
- u32 low;
- u32 high;
-
- /* Reading Global Timer Counter Register */
- do
- {
- high = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET);
- low = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_LOWER_OFFSET);
- } while(Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET) != high);
-
- *Xtime_Global = (((XTime) high) << 32U) | (XTime) low;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6c/4186db565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6c/4186db565243001d18b399c1eb9b3628
deleted file mode 100644
index 4b289a7..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6c/4186db565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,43 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_hal.h
-*
-* Contains all the HAL header files.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/28/09 Initial release
-*
-*
-* The xil_testcache.h file contains utility functions to test cache.
-*
-* @{
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 07/29/09 First release
-*
-*
-******************************************************************************/
-
-/**
-*@cond nocomments
-*/
-
-#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */
-#define XIL_TESTCACHE_H /* by using protection macros */
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern s32 Xil_TestDCacheRange(void);
-extern s32 Xil_TestDCacheAll(void);
-extern s32 Xil_TestICacheRange(void);
-extern s32 Xil_TestICacheAll(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
-
-/**
-* @} End of "addtogroup common_test_utils".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6d/32a934545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6d/32a934545243001d18b399c1eb9b3628
deleted file mode 100644
index 21c8ced..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6d/32a934545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,75 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache_l.h
-*
-* Contains L1 and L2 specific functions for the ARM cache functionality
-* used by xcache.c. This functionality is being made available here for
-* more sophisticated users.
-*
-* @addtogroup a9_cache_apis
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 01/24/10 First release
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-*
-******************************************************************************/
-#ifndef XIL_CACHE_MACH_H
-#define XIL_CACHE_MACH_H
-
-#include "xil_types.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Function Prototypes ******************************/
-
-void Xil_DCacheInvalidateLine(u32 adr);
-void Xil_DCacheFlushLine(u32 adr);
-void Xil_DCacheStoreLine(u32 adr);
-void Xil_ICacheInvalidateLine(u32 adr);
-
-void Xil_L1DCacheEnable(void);
-void Xil_L1DCacheDisable(void);
-void Xil_L1DCacheInvalidate(void);
-void Xil_L1DCacheInvalidateLine(u32 adr);
-void Xil_L1DCacheInvalidateRange(u32 adr, u32 len);
-void Xil_L1DCacheFlush(void);
-void Xil_L1DCacheFlushLine(u32 adr);
-void Xil_L1DCacheFlushRange(u32 adr, u32 len);
-void Xil_L1DCacheStoreLine(u32 adr);
-
-void Xil_L1ICacheEnable(void);
-void Xil_L1ICacheDisable(void);
-void Xil_L1ICacheInvalidate(void);
-void Xil_L1ICacheInvalidateLine(u32 adr);
-void Xil_L1ICacheInvalidateRange(u32 adr, u32 len);
-
-void Xil_L2CacheEnable(void);
-void Xil_L2CacheDisable(void);
-void Xil_L2CacheInvalidate(void);
-void Xil_L2CacheInvalidateLine(u32 adr);
-void Xil_L2CacheInvalidateRange(u32 adr, u32 len);
-void Xil_L2CacheFlush(void);
-void Xil_L2CacheFlushLine(u32 adr);
-void Xil_L2CacheFlushRange(u32 adr, u32 len);
-void Xil_L2CacheStoreLine(u32 adr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-* @} End of "addtogroup a9_cache_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6d/5002a7595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6d/5002a7595243001d18b399c1eb9b3628
deleted file mode 100644
index 10366fb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6d/5002a7595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,436 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_misc_psreset_api.c
-*
-* This file contains the implementation of the reset sequence for various
-* zynq ps devices like DDR,OCM,Slcr,Ethernet,Usb.. controllers. The reset
-* sequence provided to the interfaces is based on the provision in
-* slcr reset functional block.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00b kpc 03/07/13 First release
-* 5.4 pkp 09/11/15 Change the description for XOcm_Remap function
-*
-*
-******************************************************************************/
-
-
-/***************************** Include Files *********************************/
-#include "xil_misc_psreset_api.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for ddr reset.
-*
-*
-* @return N/A.
-*
-******************************************************************************/
-void XDdr_ResetHw(void)
-{
- u32 RegVal;
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert and deassert the ddr softreset bit */
- RegVal = Xil_In32(XDDRC_CTRL_BASEADDR);
- RegVal &= (u32)(~XDDRPS_CTRL_RESET_MASK);
- Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
- RegVal |= ((u32)XDDRPS_CTRL_RESET_MASK);
- Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
-
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for remapping the ocm memory region
-* to postbootrom state.
-*
-* @return N/A.
-*
-******************************************************************************/
-void XOcm_Remap(void)
-{
- u32 RegVal;
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Map the ocm region to postbootrom state */
- RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR);
- RegVal = (RegVal & (u32)(~XSLCR_OCM_CFG_HIADDR_MASK)) | (u32)XSLCR_OCM_CFG_RESETVAL;
- Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for SMC reset sequence
-*
-* @param BaseAddress of the interface
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSmc_ResetHw(u32 BaseAddress)
-{
- u32 RegVal;
-
- /* Clear the interuupts */
- RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET);
- RegVal = RegVal | (u32)XSMC_MEMC_CLR_CONFIG_MASK;
- Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal);
- /* Clear the idle counter registers */
- Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0U);
- Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0U);
- /* Update the ecc registers with reset values */
- Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET,
- XSMC_ECC_MEMCFG1_RESET_VAL);
- Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD1_OFFSET,
- XSMC_ECC_MEMCMD1_RESET_VAL);
- Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD2_OFFSET,
- XSMC_ECC_MEMCMD2_RESET_VAL);
-
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for updating the slcr mio registers
-* with reset values
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_MioWriteResetValues(void)
-{
- u32 i;
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Update all the MIO registers with reset values */
- for (i=0U; i<=1U;i++)
- {
- Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
- XSLCR_MIO_PIN_00_RESET_VAL);
- }
- for (; i<=8U;i++)
- {
- Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
- XSLCR_MIO_PIN_02_RESET_VAL);
- }
- for (; i<=53U ;i++)
- {
- Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
- XSLCR_MIO_PIN_00_RESET_VAL);
- }
-
-
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for updating the slcr pll registers
-* with reset values
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_PllWriteResetValues(void)
-{
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
-
- /* update the pll control registers with reset values */
- Xil_Out32(XSLCR_IO_PLL_CTRL_ADDR, XSLCR_IO_PLL_CTRL_RESET_VAL);
- Xil_Out32(XSLCR_ARM_PLL_CTRL_ADDR, XSLCR_ARM_PLL_CTRL_RESET_VAL);
- Xil_Out32(XSLCR_DDR_PLL_CTRL_ADDR, XSLCR_DDR_PLL_CTRL_RESET_VAL);
- /* update the pll config registers with reset values */
- Xil_Out32(XSLCR_IO_PLL_CFG_ADDR, XSLCR_IO_PLL_CFG_RESET_VAL);
- Xil_Out32(XSLCR_ARM_PLL_CFG_ADDR, XSLCR_ARM_PLL_CFG_RESET_VAL);
- Xil_Out32(XSLCR_DDR_PLL_CFG_ADDR, XSLCR_DDR_PLL_CFG_RESET_VAL);
- /* update the clock control registers with reset values */
- Xil_Out32(XSLCR_ARM_CLK_CTRL_ADDR, XSLCR_ARM_CLK_CTRL_RESET_VAL);
- Xil_Out32(XSLCR_DDR_CLK_CTRL_ADDR, XSLCR_DDR_CLK_CTRL_RESET_VAL);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for disabling the level shifters
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_DisableLevelShifters(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Disable the level shifters */
- RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_LVL_SHFTR_EN_MASK);
- Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal);
-
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for OCM software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_OcmReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_OCM_RST_CTRL_VAL);
- Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_OCM_RST_CTRL_VAL);
- Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for Ethernet software reset from
-* the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_EmacPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_GEM_RST_CTRL_VAL);
- Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_GEM_RST_CTRL_VAL);
- Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for USB software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_UsbPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_USB_RST_CTRL_VAL);
- Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_USB_RST_CTRL_VAL);
- Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for QSPI software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_QspiPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_QSPI_RST_CTRL_VAL);
- Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_QSPI_RST_CTRL_VAL);
- Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for SPI software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_SpiPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_SPI_RST_CTRL_VAL);
- Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_SPI_RST_CTRL_VAL);
- Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for i2c software reset from the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_I2cPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_I2C_RST_CTRL_VAL);
- Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_I2C_RST_CTRL_VAL);
- Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for UART software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_UartPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_UART_RST_CTRL_VAL);
- Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_UART_RST_CTRL_VAL);
- Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for CAN software reset from slcr
-* registers
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_CanPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_CAN_RST_CTRL_VAL);
- Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_CAN_RST_CTRL_VAL);
- Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for SMC software reset from the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_SmcPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_SMC_RST_CTRL_VAL);
- Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_SMC_RST_CTRL_VAL);
- Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for DMA controller software reset
-* from the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_DmaPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_DMAC_RST_CTRL_VAL);
- Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_DMAC_RST_CTRL_VAL);
- Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for Gpio AMBA software reset from
-* the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_GpioPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_GPIO_RST_CTRL_VAL);
- Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_GPIO_RST_CTRL_VAL);
- Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6d/51c38a555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6d/51c38a555243001d18b399c1eb9b3628
deleted file mode 100644
index 78df271..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6d/51c38a555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,14 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: MIT
-*
-******************************************************************************/
-#include "xil_types.h"
-
-/* Stub for istty sys-call */
-__attribute__((weak)) s32 _sys_istty(__attribute__((unused)) u32* f)
-{
- /* cannot read/write files */
- return 1;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6d/d13098555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6d/d13098555243001d18b399c1eb9b3628
deleted file mode 100644
index f0c63a3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6d/d13098555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,30 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#include
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) sint32 _isatty(sint32 fd);
-}
-#endif
-
-/*
- * isatty -- returns 1 if connected to a terminal device,
- * returns 0 if not. Since we're hooked up to a
- * serial port, we'll say yes _AND return a 1.
- */
-__attribute__((weak)) sint32 isatty(sint32 fd)
-{
- (void)fd;
- return (1);
-}
-
-__attribute__((weak)) sint32 _isatty(sint32 fd)
-{
- (void)fd;
- return (1);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6d/e243ad595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6d/e243ad595243001d18b399c1eb9b3628
deleted file mode 100644
index ba7531d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6d/e243ad595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,143 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2017 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/*****************************************************************************/
-/**
-*
-* @file xil_sleeptimer.c
-*
-* This file provides the common helper routines for the sleep API's
-*
-*
-* MODIFICATION HISTORY :
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 6.6 srm 10/18/17 First Release.
-* 6.6 srm 04/20/18 Fixed compilation warning in Xil_SleepTTCCommon API
-* 7.0 mus 03/27/19 Updated XTime_StartTTCTimer to skip IOU slcr address
-* space access, if processor is nonsecure and IOU slcr
-* address space is secure. CR#1015725.
-*
-*
-*****************************************************************************/
-
-/**************************** Include Files ********************************/
-
-#include "xil_io.h"
-#include "xil_sleeptimer.h"
-#include "xtime_l.h"
-
-/**************************** Constant Definitions *************************/
-
-
-/* Function definitions are applicable only when TTC3 is present*/
-#if defined (SLEEP_TIMER_BASEADDR)
-/****************************************************************************/
-/**
-*
-* This is a helper function used by sleep/usleep APIs to
-* have delay in sec/usec
-*
-* @param delay - delay time in seconds/micro seconds
-*
-* @param frequency - Number of counts per second/micro second
-*
-* @return none
-*
-* @note none
-*
-*****************************************************************************/
-void Xil_SleepTTCCommon(u32 delay, u64 frequency)
-{
- u64 tEnd = 0U;
- u64 tCur = 0U;
- XCntrVal TimeHighVal = 0U;
- XCntrVal TimeLowVal1 = 0U;
- XCntrVal TimeLowVal2 = 0U;
-
- TimeLowVal1 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET);
- tEnd = (u64)TimeLowVal1 + ((u64)(delay) * frequency);
- do
- {
- TimeLowVal2 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET);
- if (TimeLowVal2 < TimeLowVal1) {
- TimeHighVal++;
- }
- TimeLowVal1 = TimeLowVal2;
- tCur = (((u64) TimeHighVal) << XSLEEP_TIMER_REG_SHIFT) |
- (u64)TimeLowVal2;
- }while (tCur < tEnd);
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This API starts the Triple Timer Counter
-*
-* @param none
-*
-* @return none
-*
-* @note none
-*
-*****************************************************************************/
-void XTime_StartTTCTimer()
-{
- u32 TimerPrescalar;
- u32 TimerCntrl;
-
-#if (defined (__aarch64__) && EL3==1) || (defined (ARMR5) && (PROCESSOR_ACCESS_VALUE & IOU_SLCR_TZ_MASK)) || defined (ARMA53_32)
- u32 LpdRst;
-
-#if defined (versal)
- u32 RstAddr = CRL_TTC_RST;
- u32 RstMask = CRL_TTC_BASE_RST_MASK << XSLEEP_TTC_INSTANCE;
-#else
- u32 RstAddr = RST_LPD_IOU2;
- u32 RstMask = RST_LPD_IOU2_TTC_BASE_RESET_MASK << XSLEEP_TTC_INSTANCE;
-#endif
- /* check if the timer is reset */
- LpdRst = XSleep_ReadCounterVal(RstAddr);
- if ((LpdRst & RstMask) != 0 ) {
- LpdRst = LpdRst & (~RstMask);
- Xil_Out32(RstAddr, LpdRst);
- } else {
-#endif
- TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET);
- /* check if Timer is disabled */
- if ((TimerCntrl & XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK) == 0) {
- TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET);
- /* check if Timer is configured with proper functionalty for sleep */
- if ((TimerPrescalar & XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK) == 0)
- return;
- }
-#if (defined (__aarch64__) && EL3==1) || (defined (ARMR5) && (PROCESSOR_ACCESS_VALUE & IOU_SLCR_TZ_MASK)) || defined (ARMA53_32)
- }
-#endif
- /* Disable the timer to configure */
- TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET);
- TimerCntrl = TimerCntrl | XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK;
- Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET,
- TimerCntrl);
- /* Disable the prescalar */
- TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET);
- TimerPrescalar = TimerPrescalar & (~XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK);
- Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET,
- TimerPrescalar);
- /* Enable the Timer */
- TimerCntrl = TimerCntrl & (~XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK);
- Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET,
- TimerCntrl);
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6e/0011a2545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6e/0011a2545243001d18b399c1eb9b3628
deleted file mode 100644
index 6627f04..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6e/0011a2545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,38 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 2021.2
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2022 Xilinx, Inc. All Rights Reserved.
-* SPDX-License-Identifier: MIT
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xemacps.h"
-
-/*
-* The configuration table for devices
-*/
-
-XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] =
-{
- {
- XPAR_PS7_ETHERNET_0_DEVICE_ID,
- XPAR_PS7_ETHERNET_0_BASEADDR,
- XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT,
- XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0,
- XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1,
- XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0,
- XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1,
- XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0,
- XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1
- }
-};
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6e/102b30565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6e/102b30565243001d18b399c1eb9b3628
deleted file mode 100644
index 06fa5cc..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6e/102b30565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,115 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_mmu.h
-*
-* @addtogroup r5_mpu_apis Cortex R5 Processor MPU specific APIs
-*
-* MPU functions provides access to MPU operations such as enable MPU, disable
-* MPU and set attribute for section of memory.
-* Boot code invokes Init_MPU function to configure the MPU. A total of 10 MPU
-* regions are allocated with another 6 being free for users. Overview of the
-* memory attributes for different MPU regions is as given below,
-*
-*| | Memory Range | Attributes of MPURegion |
-*|-----------------------|-------------------------|-----------------------------|
-*| DDR | 0x00000000 - 0x7FFFFFFF | Normal write-back Cacheable |
-*| PL | 0x80000000 - 0xBFFFFFFF | Strongly Ordered |
-*| QSPI | 0xC0000000 - 0xDFFFFFFF | Device Memory |
-*| PCIe | 0xE0000000 - 0xEFFFFFFF | Device Memory |
-*| STM_CORESIGHT | 0xF8000000 - 0xF8FFFFFF | Device Memory |
-*| RPU_R5_GIC | 0xF9000000 - 0xF90FFFFF | Device memory |
-*| FPS | 0xFD000000 - 0xFDFFFFFF | Device Memory |
-*| LPS | 0xFE000000 - 0xFFFFFFFF | Device Memory |
-*| OCM | 0xFFFC0000 - 0xFFFFFFFF | Normal write-back Cacheable |
-*
-*
-* @note
-* For a system where DDR is less than 2GB, region after DDR and before PL is
-* marked as undefined in translation table. Memory range 0xFE000000-0xFEFFFFFF is
-* allocated for upper LPS slaves, where as memory region 0xFF000000-0xFFFFFFFF is
-* allocated for lower LPS slaves.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00 pkp 02/10/14 Initial version
-* 6.4 asa 08/16/17 Added many APIs for MPU access to make MPU usage
-* user-friendly. The APIs added are: Xil_UpdateMPUConfig,
-* Xil_GetMPUConfig, Xil_GetNumOfFreeRegions,
-* Xil_GetNextMPURegion, Xil_DisableMPURegionByRegNum,
-* Xil_GetMPUFreeRegMask, Xil_SetMPURegionByRegNum, and
-* Xil_InitializeExistingMPURegConfig.
-* Added a new array of structure of type XMpuConfig to
-* represent the MPU configuration table.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.1 nsk 11/07/16 First release.
-*
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-
-/***************** Inline Functions Definitions ********************/
-/*****************************************************************************/
-/**
-* @brief This function copies memory from once location to other.
-*
-* @param dst: pointer pointing to destination memory
-*
-* @param src: pointer pointing to source memory
-*
-* @param cnt: 32 bit length of bytes to be copied
-*
-*****************************************************************************/
-void Xil_MemCpy(void* dst, const void* src, u32 cnt)
-{
- char *d = (char*)(void *)dst;
- const char *s = src;
-
- while (cnt >= sizeof (int)) {
- *(int*)d = *(int*)s;
- d += sizeof (int);
- s += sizeof (int);
- cnt -= sizeof (int);
- }
- while (cnt >= sizeof (u16)) {
- *(u16*)d = *(u16*)s;
- d += sizeof (u16);
- s += sizeof (u16);
- cnt -= sizeof (u16);
- }
- while ((cnt) > 0U){
- *d = *s;
- d += 1U;
- s += 1U;
- cnt -= 1U;
- }
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6e/81b670565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6e/81b670565243001d18b399c1eb9b3628
deleted file mode 100644
index b00e96a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6e/81b670565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,27 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#ifndef UNDEFINE_FILE_OPS
-#include
-#include "xil_types.h"
-#include
-struct tms* tms;
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) clock_t _times(struct tms* tms);
-}
-#endif
-
-__attribute__((weak)) clock_t _times(struct tms* tms)
-{
- (void)tms;
-
- errno = EIO;
- return (-1);
-}
-
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6e/d04212565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6e/d04212565243001d18b399c1eb9b3628
deleted file mode 100644
index 49a15f7..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6e/d04212565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,59 +0,0 @@
-;/******************************************************************************
-;* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-;* SPDX-License-Identifier: MIT
-;******************************************************************************/
-;/*****************************************************************************/
-;/**
-;* @file xil-crt0.S
-;*
-;*
-;* MODIFICATION HISTORY:
-;*
-;* Ver Who Date Changes
-;* ----- ---- -------- ---------------------------------------------------
-;* 7.3 dp 06/25/20 Initial version for armclang
-;*
-;*
-;* @note
-;*
-;* None.
-;*
-;******************************************************************************/
-#include "xparameters.h"
-#include "bspconfig.h"
-
- IMPORT |Image$$BSS_SECTION$$Base|
- IMPORT Xil_InitializeExistingMPURegConfig
- EXPORT _startup
- IMPORT __cpu_init
- IMPORT __main
-#ifdef SLEEP_TIMER_BASEADDR
- IMPORT XTime_StartTTCTimer
-#endif
- AREA |.text|, CODE
- REQUIRE8 {TRUE}
- PRESERVE8 {TRUE}
- ENTRY
-
-_startup
- bl __cpu_init ;Initialize the CPU first (BSP provides this)
- ;configure the timer if TTC is present
-#ifdef SLEEP_TIMER_BASEADDR
- bl XTime_StartTTCTimer
-#endif
- bl Xil_InitializeExistingMPURegConfig ;/* Initialize MPU config */
- ;make sure argc and argv are valid
- mov r0, #0
- mov r1, #0
-
-#ifdef XCLOCKING
- bl Xil_ClockInit
-#endif
- bl __main ;Jump to main C code
-
- bl exit
-
-exit ;should never get here
- b exit
-
- END
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6e/e0bb46525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6e/e0bb46525243001d18b399c1eb9b3628
deleted file mode 100644
index c283696..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6e/e0bb46525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,3 +0,0 @@
-/export/
-*.o
-*.d
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6f/103038585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6f/103038585243001d18b399c1eb9b3628
deleted file mode 100644
index d880230..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6f/103038585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,78 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xsdps_sinit.c
-* @addtogroup sdps_v3_13
-* @{
-*
-* The implementation of the XSdPs component's static initialization
-* functionality.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a hk/sg 10/17/13 Initial release
-* kvn 07/15/15 Modified the code according to MISRAC-2012.
-* 3.7 aru 03/12/19 Modified the code according to MISRAC-2012.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xstatus.h"
-#include "xsdps.h"
-#include "xparameters.h"
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-/**
- * XSdPs Configuration Table
- */
-extern XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES];
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* Looks up the device configuration based on the unique device ID. A table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId contains the ID of the device to look up the
-* configuration for.
-*
-* @return
-*
-* A pointer to the configuration found or NULL if the specified device ID was
-* not found. See xsdps.h for the definition of XSdPs_Config.
-*
-* @note None.
-*
-******************************************************************************/
-XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId)
-{
- XSdPs_Config *CfgPtr = NULL;
- u32 Index;
-
- for (Index = 0U; Index < (u32)XPAR_XSDPS_NUM_INSTANCES; Index++) {
- if (XSdPs_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XSdPs_ConfigTable[Index];
- break;
- }
- }
- return (XSdPs_Config *)CfgPtr;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6f/206075585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6f/206075585243001d18b399c1eb9b3628
deleted file mode 100644
index 8abb888..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6f/206075585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,116 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xtime_l.c
-*
-* This file contains low level functions to get/set time from the Global Timer
-* register in the ARM Cortex A53 MP core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 5.00 pkp 05/29/14 First release
-* 5.05 pkp 04/13/16 Added XTime_StartTimer API to start the global timer
-* counter if it is disabled. Also XTime_GetTime calls
-* this API to ensure the global timer counter is enabled
-* 6.02 pkp 01/22/17 Added support for EL1 non-secure
-* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
-* displaying same warnings multiple times. It fixes CR#1090562.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sv 01/18/10 First Release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
-* in safety mode and modified the code such as
-* Use of mixed mode arithmetic,Declared the pointer param
-* as Pointer to const,Casting operation to a pointer,
-* Literal value requires a U suffix.
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xstatus.h"
-#include "xgpiops.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-/*****************************************************************************/
-/**
-*
-* This function runs a self-test on the GPIO driver/device. This function
-* does a register read/write test on some of the Interrupt Registers.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-*
-* @return
-* - XST_SUCCESS if the self-test passed.
-* - XST_FAILURE otherwise.
-*
-*
-******************************************************************************/
-s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr)
-{
- s32 Status = (s32)0;
- u32 IntrEnabled;
- u32 CurrentIntrType = 0U;
- u32 CurrentIntrPolarity = 0U;
- u32 CurrentIntrOnAny = 0U;
- u32 IntrType = 0U;
- u32 IntrPolarity = 0U;
- u32 IntrOnAny = 0U;
- u32 IntrTestValue = 0x22U;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Disable the Interrupts for Bank 0 . */
- IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr, XGPIOPS_BANK0);
- XGpioPs_IntrDisable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
-
- /*
- * Get the Current Interrupt properties for Bank 0.
- * Set them to a known value, read it back and compare.
- */
- XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &CurrentIntrType,
- &CurrentIntrPolarity, &CurrentIntrOnAny);
-
- XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, IntrTestValue,
- IntrTestValue, IntrTestValue);
-
- XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &IntrType,
- &IntrPolarity, &IntrOnAny);
-
- if ((IntrType != IntrTestValue) && (IntrPolarity != IntrTestValue) &&
- (IntrOnAny != IntrTestValue)) {
-
- Status = (s32)XST_FAILURE;
- }
-
- /*
- * Restore the contents of all the interrupt registers modified in this
- * test.
- */
- XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, CurrentIntrType,
- CurrentIntrPolarity, CurrentIntrOnAny);
-
- XGpioPs_IntrEnable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
-
- return Status;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6f/a08de6575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6f/a08de6575243001d18b399c1eb9b3628
deleted file mode 100644
index 5feeb49..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/6f/a08de6575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,39 +0,0 @@
-DRIVER_LIB_VERSION = 1.0
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I$(INCLUDEDIR)
-
-SRCFILES:=$(wildcard *.c)
-
-OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
-
-libs: $(OBJECTS)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf $(DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/013252565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/013252565243001d18b399c1eb9b3628
deleted file mode 100644
index d8aef59..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/013252565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,169 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xenv.h
-*
-* Defines common services that are typically found in a host operating.
-* environment. This include file simply includes an OS specific file based
-* on the compile-time constant BUILD_ENV_*, where * is the name of the target
-* environment.
-*
-* All services are defined as macros.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b ch 10/24/02 Added XENV_LINUX
-* 1.00a rmm 04/17/02 First release
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XENV_H /* prevent circular inclusions */
-#define XENV_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * Select which target environment we are operating under
- */
-
-/* VxWorks target environment */
-#if defined XENV_VXWORKS
-#include "xenv_vxworks.h"
-
-/* Linux target environment */
-#elif defined XENV_LINUX
-#include "xenv_linux.h"
-
-/* Unit test environment */
-#elif defined XENV_UNITTEST
-#include "ut_xenv.h"
-
-/* Integration test environment */
-#elif defined XENV_INTTEST
-#include "int_xenv.h"
-
-/* Standalone environment selected */
-#else
-#include "xenv_standalone.h"
-#endif
-
-
-/*
- * The following comments specify the types and macro wrappers that are
- * expected to be defined by the target specific header files
- */
-
-/**************************** Type Definitions *******************************/
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP
- *
- * A structure that contains a time stamp used by other time stamp macros
- * defined below. This structure is processor dependent.
- */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- *
- * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
- *
- * Copies a non-overlapping block of memory.
- *
- * @param DestPtr is the destination address to copy data to.
- * @param SrcPtr is the source address to copy data from.
- * @param Bytes is the number of bytes to copy.
- *
- * @return None
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
- *
- * Fills an area of memory with constant data.
- *
- * @param DestPtr is the destination address to set.
- * @param Data contains the value to set.
- * @param Bytes is the number of bytes to set.
- *
- * @return None
- */
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
- *
- * Samples the processor's or external timer's time base counter.
- *
- * @param StampPtr is the storage for the retrieved time stamp.
- *
- * @return None
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
- *
- * Computes the delta between the two time stamps.
- *
- * @param Stamp1Ptr - First sampled time stamp.
- * @param Stamp1Ptr - Sedond sampled time stamp.
- *
- * @return An unsigned int value with units of microseconds.
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
- *
- * Computes the delta between the two time stamps.
- *
- * @param Stamp1Ptr - First sampled time stamp.
- * @param Stamp1Ptr - Sedond sampled time stamp.
- *
- * @return An unsigned int value with units of milliseconds.
- */
-
-/*****************************************************************************//**
- *
- * XENV_USLEEP(unsigned delay)
- *
- * Delay the specified number of microseconds.
- *
- * @param delay is the number of microseconds to delay.
- *
- * @return None
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/103daa565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/103daa565243001d18b399c1eb9b3628
deleted file mode 100644
index de30ce1..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/103daa565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,130 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file microblaze_sleep.h
-*
-* @addtogroup microblaze_sleep_routines Sleep Routines for Microblaze
-*
-* The microblaze_sleep.h file contains microblaze sleep APIs. These APIs
-* provides delay for requested duration.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 4.1 asa 04/18/14 Add sleep function - first release.
-* 6.6 srm 10/18/17 Added the Register offset definitions and Control/Status
-* Register bit masks of the Axi timer.
-* 7.5 mus 04/21/21 Microblaze frequency can be changed run time. Sleep routines
-* needs to use updated frequency for delay calculation, else
-* sleep calls would result into incorrect behavior. Added
-* Xil_SetMBFrequency API to write updated frequency value to
-* MBFreq variable, and updated ITERS_PER_SEC macro to read
-* frequency value from MBFreq variable, instead of using XPARS.
-* Xil_SetMBFrequency must be called immediately after change
-* in Microblaze frequency run time, it would keep sleep
-* routines in sync with Microblaze frequency.
-* Added Xil_GetMBFrequency to read current Microbalze frequency.
-* It fixes CR#1094568.
-* 7.6 mus 08/23/21 Updated prototypes for functions which are not taking any
-* arguments with void keyword. This has been done to fix
-* compilation warnings with "-Wstrict-prototypes" flag.
-* It fixes CR#1108601.
-*
-*
-*
-* @note
-* The microblaze_sleep.h file may contain architecture-dependent items.
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-#ifndef MICROBLAZE_SLEEP_H /* prevent circular inclusions */
-#define MICROBLAZE_SLEEP_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "mb_interface.h"
-#include "xparameters.h"
-#include "sleep.h"
-
-/************************** Constant Definitions *****************************/
-
-#if defined (XSLEEP_TIMER_IS_AXI_TIMER)
-
-/** @name Register Offset Definitions
- * Register offsets within the Axi timer counter, there are multiple
- * timer counters within a single device
- * @{
- */
-#define XSLEEP_TIMER_AXITIMER_TCSR0_OFFSET 0U /**< Control/Status register */
-#define XSLEEP_TIMER_AXITIMER_TLR_OFFSET 4U /**< Load register */
-#define XSLEEP_TIMER_AXITIMER_TCR_OFFSET 8U /**< Timer counter register */
-/* @} */
-
-/** @name Control Status Register Bit Definitions
- * Control Status Register bit masks
- * Used to configure the Axi timer counter device.
- * @{
- */
-#define XSLEEP_TIMER_AXITIMER_CSR_ENABLE_TMR_MASK 0x00000080U
- /**< Enables only the specific timer */
-#define XSLEEP_TIMER_AXITIMER_CSR_AUTO_RELOAD_MASK 0x00000010U
- /**< In compare mode, configures the timer
- * counter to reload from the Load Register.
- * The default mode causes the timer counter
- * to hold when the compare value is hit. In
- * capture mode, configures the timer counter
- * to not hold the previous capture value if
- * a new event occurs. The default mode cause
- * the timer counter to hold the capture value
- * until recognized.*/
-#define XSLEEP_TIMER_AXITIMER_CSR_LOAD_MASK 0x00000020U
- /**< Loads the timer using the load value
- * provided earlier in the Load Register,
- * XSLEEP_TIMER_AXITIMER_TLR_OFFSET. */
-#define XSLEEP_TIMER_AXITIMER_CSR_INT_OCCURED_MASK 0x00000100U
- /**< If bit is set, an interrupt has occurred.
- * If set and '1' is written to this bit
- * position, bit is cleared.*/
-#define XSLEEP_TIMER_AXITIMER_CSR_ENABLE_TMR_MASK 0x00000080U
- /**< Enables only the specific timer */
-/* @} */
-
-/**************************** Type Definitions *******************************/
-/************************** Function Prototypes ******************************/
-
-static void Xil_SleepAxiTimer(u32 delay, u64 frequency);
-static void XTime_StartAxiTimer(void);
-#else
-u32 Xil_SetMBFrequency(u32 Val);
-u32 Xil_GetMBFrequency(void);
-#endif
-/**
- *@endcond
- */
-void MB_Sleep(u32 MilliSeconds) __attribute__((__deprecated__));
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup microblaze_sleep_routines".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/1066a6595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/1066a6595243001d18b399c1eb9b3628
deleted file mode 100644
index d6bc637..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/1066a6595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,47 +0,0 @@
-/******************************************************************************/
-/**
-* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-* @file xil_mem.h
-*
-* @addtogroup common_mem_operation_api Customized APIs for Memory Operations
-*
-* The xil_mem.h file contains prototype for functions related
-* to memory operations. These APIs are applicable for all processors supported
-* by Xilinx.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.1 nsk 11/07/16 First release.
-* 7.0 mus 01/07/19 Add cpp extern macro
-*
-*
-*
-*****************************************************************************/
-#ifndef XIL_MEM_H /* prevent circular inclusions */
-#define XIL_MEM_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Function Prototypes *****************************/
-
-void Xil_MemCpy(void* dst, const void* src, u32 cnt);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_MEM_H */
-/**
-* @} End of "addtogroup common_mem_operation_api".
-*/
\ No newline at end of file
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/11bf35585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/11bf35585243001d18b399c1eb9b3628
deleted file mode 100644
index 8c81985..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/11bf35585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,848 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xsdps_options.c
-* @addtogroup sdps_v3_13
-* @{
-*
-* Contains API's for changing the various options in host and card.
-* See xsdps.h for a detailed description of the device and driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a hk/sg 10/17/13 Initial release
-* 2.1 hk 04/18/14 Increase sleep for eMMC switch command.
-* Add sleep for microblaze designs. CR# 781117.
-* 2.3 sk 09/23/14 Use XSdPs_Change_ClkFreq API whenever changing
-* clock.CR# 816586.
-* 2.5 sg 07/09/15 Added SD 3.0 features
-* kvn 07/15/15 Modified the code according to MISRAC-2012.
-* 2.7 sk 01/08/16 Added workaround for issue in auto tuning mode
-* of SDR50, SDR104 and HS200.
-* sk 02/16/16 Corrected the Tuning logic.
-* sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
-* 2.8 sk 04/20/16 Added new workaround for auto tuning.
-* 3.0 sk 07/07/16 Used usleep API for both arm and microblaze.
-* sk 07/16/16 Added support for UHS modes.
-* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
-* operating modes.
-* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
-* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
-* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value.
-* 3.2 sk 02/01/17 Added HSD and DDR mode support for eMMC.
-* sk 02/01/17 Consider bus width parameter from design for switching
-* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
-* vns 03/13/17 Fixed MISRAC mandatory violation
-* sk 03/20/17 Add support for EL1 non-secure mode.
-* 3.3 mn 07/25/17 Removed SD0_OTAPDLYENA and SD1_OTAPDLYENA bits
-* mn 08/07/17 Properly set OTAPDLY value by clearing previous bit
-* settings
-* mn 08/17/17 Added CCI support for A53 and disabled data cache
-* operations when it is enabled.
-* mn 08/22/17 Updated for Word Access System support
-* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
-* 3.6 mn 07/06/18 Fix Cppcheck warnings for sdps driver
-* 3.7 aru 03/12/19 Modified the code according to MISRAC-2012.
-* mn 03/27/19 Disable calls to dll_reset API for versal SPP Platforms
-* 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
-* mn 05/21/19 Set correct tap delays for Versal
-* mn 05/21/19 Disable DLL Reset code for Versal
-* mn 08/29/19 Add call to Cache Invalidation API in XSdPs_Get_BusWidth
-* 3.9 mn 03/03/20 Restructured the code for more readability and modularity
-* mn 03/16/20 Move XSdPs_Select_Card API to User APIs
-* 3.10 mn 06/05/20 Modified code for SD Non-Blocking Read support
-* 3.12 sk 01/28/21 Added support for non-blocking write.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xsdps_core.h"
-/************************** Constant Definitions *****************************/
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to change clock freq to given value.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param SelFreq - Clock frequency in Hz.
-*
-* @return None
-*
-* @note This API will change clock frequency to the value less than
-* or equal to the given value using the permissible dividors.
-*
-******************************************************************************/
-s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
- /* Program the Tap delays */
- XSdPs_SetTapDelay(InstancePtr);
- }
-
- Status = XSdPs_SetClock(InstancePtr, SelFreq);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* Update Block size for read/write operations.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param BlkSize - Block size passed by the user.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- Status = XSdPs_CheckBusIdle(InstancePtr, (XSDPS_PSR_INHIBIT_CMD_MASK
- | XSDPS_PSR_INHIBIT_DAT_MASK
- | XSDPS_PSR_WR_ACTIVE_MASK
- | XSDPS_PSR_RD_ACTIVE_MASK));
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- /* Send block write command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD16, BlkSize, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Set block size to the value passed */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
- BlkSize & XSDPS_BLK_SIZE_MASK);
-
- InstancePtr->BlkSize = BlkSize;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to get bus width support by card.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param ReadBuff - buffer to store SCR register returned by card.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *ReadBuff)
-{
- s32 Status;
- u16 BlkCnt;
- u16 BlkSize;
- s32 LoopCnt;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- for (LoopCnt = 0; LoopCnt < 8; LoopCnt++) {
- ReadBuff[LoopCnt] = 0U;
- }
-
- /* Send block write command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
- InstancePtr->RelCardAddr, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- BlkCnt = XSDPS_SCR_BLKCNT;
- BlkSize = XSDPS_SCR_BLKSIZE;
-
- XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, ReadBuff);
-
- Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0U, BlkCnt);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Check for transfer done */
- Status = XSdps_CheckTransferDone(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- if (InstancePtr->Config.IsCacheCoherent == 0U) {
- Xil_DCacheInvalidateRange((INTPTR)ReadBuff,
- (INTPTR)BlkCnt * BlkSize);
- }
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to set bus width to 4-bit in card and host
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr)
-{
- s32 Status;
- u32 StatusReg;
- u32 Arg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * check for bus width for 3.0 controller and return if
- * bus width is <4
- */
- if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
- (InstancePtr->Config.BusWidth < XSDPS_WIDTH_4)) {
- Status = XST_SUCCESS;
- goto RETURN_PATH;
- }
-
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr,
- 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, (u32)InstancePtr->BusWidth, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } else {
- if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
- if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
- Arg = XSDPS_MMC_DDR_8_BIT_BUS_ARG;
- } else {
- Arg = XSDPS_MMC_8_BIT_BUS_ARG;
- }
- } else {
- if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
- Arg = XSDPS_MMC_DDR_4_BIT_BUS_ARG;
- } else {
- Arg = XSDPS_MMC_4_BIT_BUS_ARG;
- }
- }
-
- Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, Arg);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
-
- StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL1_OFFSET);
-
- /* Width setting in controller */
- if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
- StatusReg |= XSDPS_HC_EXT_BUS_WIDTH;
- } else {
- StatusReg |= XSDPS_HC_WIDTH_MASK;
- }
-
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL1_OFFSET,
- (u8)StatusReg);
-
- if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
- StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET);
- StatusReg &= (u32)(~XSDPS_HC2_UHS_MODE_MASK);
- StatusReg |= InstancePtr->Mode;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET, (u16)StatusReg);
- }
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to get bus speed supported by card.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param ReadBuff - buffer to store function group support data
-* returned by card.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff)
-{
- s32 Status;
- u32 Arg;
- u16 BlkCnt;
- u16 BlkSize;
- s32 LoopCnt;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- for (LoopCnt = 0; LoopCnt < 64; LoopCnt++) {
- ReadBuff[LoopCnt] = 0U;
- }
-
- BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
- BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
-
- XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, ReadBuff);
-
- Arg = XSDPS_SWITCH_CMD_HS_GET;
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Check for transfer done */
- Status = XSdps_CheckTransferDone(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- if (InstancePtr->Config.IsCacheCoherent == 0U) {
- Xil_DCacheInvalidateRange((INTPTR)ReadBuff,
- (INTPTR)BlkCnt * BlkSize);
- }
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to get SD card status information.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param SdStatReg - buffer to store status data returned by card.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Get_Status(XSdPs *InstancePtr, u8 *SdStatReg)
-{
- s32 Status;
- u16 BlkCnt;
- u16 BlkSize;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Send block write command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
- InstancePtr->RelCardAddr, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- BlkCnt = XSDPS_SD_STATUS_BLKCNT;
- BlkSize = XSDPS_SD_STATUS_BLKSIZE;
-
- XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, SdStatReg);
-
- Status = XSdPs_CmdTransfer(InstancePtr, ACMD13, 0U, BlkCnt);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Check for transfer done */
- Status = XSdps_CheckTransferDone(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- if (InstancePtr->Config.IsCacheCoherent == 0U) {
- Xil_DCacheInvalidateRange((INTPTR)SdStatReg,
- (INTPTR)BlkCnt * BlkSize);
- }
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to set high speed in card and host. Changes clock in host accordingly.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
-{
- s32 Status;
- u32 StatusReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
- Status = XSdPs_Change_SdBusSpeed(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } else {
- Status = XSdPs_Change_MmcBusSpeed(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if ((InstancePtr->Mode == XSDPS_HS200_MODE) ||
- (InstancePtr->Mode == XSDPS_UHS_SPEED_MODE_SDR104) ||
- (InstancePtr->Mode == XSDPS_UHS_SPEED_MODE_SDR50)) {
- Status = XSdPs_Execute_Tuning(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
-
- StatusReg = (u32)XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL1_OFFSET);
- StatusReg |= XSDPS_HC_SPEED_MASK;
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg);
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to get EXT_CSD register of eMMC.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param ReadBuff - buffer to store EXT_CSD
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
-{
- s32 Status;
- u32 Arg = 0U;
- u16 BlkCnt;
- u16 BlkSize;
- s32 LoopCnt;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- for (LoopCnt = 0; LoopCnt < 512; LoopCnt++) {
- ReadBuff[LoopCnt] = 0U;
- }
-
- BlkCnt = XSDPS_EXT_CSD_CMD_BLKCNT;
- BlkSize = XSDPS_EXT_CSD_CMD_BLKSIZE;
-
- XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, ReadBuff);
-
- /* Send SEND_EXT_CSD command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Check for transfer done */
- Status = XSdps_CheckTransferDone(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- if (InstancePtr->Config.IsCacheCoherent == 0U) {
- Xil_DCacheInvalidateRange((INTPTR)ReadBuff,
- (INTPTR)BlkCnt * BlkSize);
- }
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to write EXT_CSD register of eMMC.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param Arg is the argument to be sent along with the command
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Check for transfer done */
- Status = XSdps_CheckTransferDone(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to send pullup command to card before using DAT line 3(using 4-bit bus)
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Pullup(XSdPs *InstancePtr)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
- InstancePtr->RelCardAddr, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XSdPs_CmdTransfer(InstancePtr, ACMD42, 0U, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* Selects card and sets default block size
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-* - XSDPS_CT_ERROR if Command Transfer fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Select_Card (XSdPs *InstancePtr)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Send CMD7 - Select card */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD7,
- InstancePtr->RelCardAddr, 0U);
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function performs SD read in polled mode.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Arg is the address passed by the user that is to be sent as
-* argument along with the command.
-* @param BlkCnt - Block count passed by the user.
-* @param Buff - Pointer to the data buffer for a DMA transfer.
-*
-* @return
-* - XST_SUCCESS if Transfer initialization was successful
-* - XST_FAILURE if failure - could be because another transfer
-* is in progress or command or data inhibit is set
-*
-******************************************************************************/
-s32 XSdPs_StartReadTransfer(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- if (InstancePtr->IsBusy == TRUE) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Setup the Read Transfer */
- Status = XSdPs_SetupTransfer(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Read from the card */
- Status = XSdPs_Read(InstancePtr, Arg, BlkCnt, Buff);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- InstancePtr->IsBusy = TRUE;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function start SD write transfer.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Arg is the address passed by the user that is to be sent as
-* argument along with the command.
-* @param BlkCnt - Block count passed by the user.
-* @param Buff - Pointer to the data buffer for a DMA transfer.
-*
-* @return
-* - XST_SUCCESS if Transfer initialization was successful
-* - XST_FAILURE if failure - could be because another transfer
-* is in progress or command or data inhibit is set
-*
-******************************************************************************/
-s32 XSdPs_StartWriteTransfer(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- if (InstancePtr->IsBusy == TRUE) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Setup the Write Transfer */
- Status = XSdPs_SetupTransfer(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* write to the card */
- Status = XSdPs_Write(InstancePtr, Arg, BlkCnt, Buff);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- InstancePtr->IsBusy = TRUE;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to check if the transfer is completed successfully.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if transfer was successful
-* - XST_FAILURE if failure
-* - XST_DEVICE_BUSY - if the transfer is still in progress
-*
-******************************************************************************/
-s32 XSdPs_CheckReadTransfer(XSdPs *InstancePtr)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- Status = XSdPs_CheckTransferComplete(InstancePtr);
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to check for the write transfer completed.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if transfer was successful
-* - XST_FAILURE if failure
-* - XST_DEVICE_BUSY - if the transfer is still in progress
-*
-******************************************************************************/
-s32 XSdPs_CheckWriteTransfer(XSdPs *InstancePtr)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- Status = XSdPs_CheckTransferComplete(InstancePtr);
-
- return Status;
-}
-
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/507c04555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/507c04555243001d18b399c1eb9b3628
deleted file mode 100644
index 4c9faef..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/507c04555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,16 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include
-
-/*
- * abort -- go out via exit...
- */
-__attribute__((weak)) void abort(void)
-{
- _exit(1);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/6039ce595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/6039ce595243001d18b399c1eb9b3628
deleted file mode 100644
index fd8da2c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/6039ce595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,741 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xuartps_options.c
-* @addtogroup uartps_v3_11
-* @{
-*
-* The implementation of the options functions for the XUartPs driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00 drg/jz 01/13/10 First Release
-* 1.00 sdm 09/27/11 Fixed a bug in XUartPs_SetFlowDelay where the input
-* value was not being written to the register.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.2 rk 07/20/16 Modified the logic for transmission break bit set
-*
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xuartps.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-/*
- * The following data type is a map from an option to the offset in the
- * register to which it belongs as well as its bit mask in that register.
- */
-typedef struct {
- u16 Option;
- u16 RegisterOffset;
- u32 Mask;
-} Mapping;
-
-/*
- * Create the table which contains options which are to be processed to get/set
- * the options. These options are table driven to allow easy maintenance and
- * expansion of the options.
- */
-
-static Mapping OptionsTable[] = {
- {XUARTPS_OPTION_SET_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STARTBRK},
- {XUARTPS_OPTION_STOP_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STOPBRK},
- {XUARTPS_OPTION_RESET_TMOUT, XUARTPS_CR_OFFSET, XUARTPS_CR_TORST},
- {XUARTPS_OPTION_RESET_TX, XUARTPS_CR_OFFSET, XUARTPS_CR_TXRST},
- {XUARTPS_OPTION_RESET_RX, XUARTPS_CR_OFFSET, XUARTPS_CR_RXRST},
- {XUARTPS_OPTION_ASSERT_RTS, XUARTPS_MODEMCR_OFFSET,
- XUARTPS_MODEMCR_RTS},
- {XUARTPS_OPTION_ASSERT_DTR, XUARTPS_MODEMCR_OFFSET,
- XUARTPS_MODEMCR_DTR},
- {XUARTPS_OPTION_SET_FCM, XUARTPS_MODEMCR_OFFSET, XUARTPS_MODEMCR_FCM}
-};
-
-/* Create a constant for the number of entries in the table */
-
-#define XUARTPS_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(Mapping))
-
-/************************** Function Prototypes *****************************/
-
-/****************************************************************************/
-/**
-*
-* Gets the options for the specified driver instance. The options are
-* implemented as bit masks such that multiple options may be enabled or
-* disabled simultaneously.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-*
-* The current options for the UART. The options are bit masks that are
-* contained in the file xuartps.h and named XUARTPS_OPTION_*.
-*
-* @note None.
-*
-*****************************************************************************/
-u16 XUartPs_GetOptions(XUartPs *InstancePtr)
-{
- u16 Options = 0U;
- u32 Register;
- u32 Index;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Loop through the options table to map the physical options in the
- * registers of the UART to the logical options to be returned
- */
- for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
- Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- OptionsTable[Index].
- RegisterOffset);
-
- /*
- * If the bit in the register which correlates to the option
- * is set, then set the corresponding bit in the options,
- * ignoring any bits which are zero since the options variable
- * is initialized to zero
- */
- if ((Register & OptionsTable[Index].Mask) != (u32)0) {
- Options |= OptionsTable[Index].Option;
- }
- }
-
- return Options;
-}
-
-/****************************************************************************/
-/**
-*
-* Sets the options for the specified driver instance. The options are
-* implemented as bit masks such that multiple options may be enabled or
-* disabled simultaneously.
-*
-* The GetOptions function may be called to retrieve the currently enabled
-* options. The result is ORed in the desired new settings to be enabled and
-* ANDed with the inverse to clear the settings to be disabled. The resulting
-* value is then used as the options for the SetOption function call.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param Options contains the options to be set which are bit masks
-* contained in the file xuartps.h and named XUARTPS_OPTION_*.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options)
-{
- u32 Index;
- u32 Register;
-
- /* Assert validates the input arguments */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Loop through the options table to map the logical options to the
- * physical options in the registers of the UART.
- */
- for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
-
- /*
- * Read the register which contains option so that the register
- * can be changed without destoying any other bits of the
- * register.
- */
- Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- OptionsTable[Index].
- RegisterOffset);
-
- /*
- * If the option is set in the input, then set the corresponding
- * bit in the specified register, otherwise clear the bit in
- * the register.
- */
- if ((Options & OptionsTable[Index].Option) != (u16)0) {
- if(OptionsTable[Index].Option == XUARTPS_OPTION_SET_BREAK)
- Register &= ~XUARTPS_CR_STOPBRK;
- Register |= OptionsTable[Index].Mask;
- }
- else {
- Register &= ~OptionsTable[Index].Mask;
- }
-
- /* Write the new value to the register to set the option */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- OptionsTable[Index].RegisterOffset,
- Register);
- }
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the receive FIFO trigger level. The receive trigger
-* level indicates the number of bytes in the receive FIFO that cause a receive
-* data event (interrupt) to be generated.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return The current receive FIFO trigger level. This is a value
-* from 0-31.
-*
-* @note None.
-*
-*****************************************************************************/
-u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr)
-{
- u8 RtrigRegister;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the value of the FIFO control register so that the threshold
- * can be retrieved, this read takes special register processing
- */
- RtrigRegister = (u8) XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_RXWM_OFFSET);
-
- /* Return only the trigger level from the register value */
-
- RtrigRegister &= (u8)XUARTPS_RXWM_MASK;
- return RtrigRegister;
-}
-
-/****************************************************************************/
-/**
-*
-* This functions sets the receive FIFO trigger level. The receive trigger
-* level specifies the number of bytes in the receive FIFO that cause a receive
-* data event (interrupt) to be generated.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param TriggerLevel contains the trigger level to set.
-*
-* @return None
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel)
-{
- u32 RtrigRegister;
-
- /* Assert validates the input arguments */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(TriggerLevel <= (u8)XUARTPS_RXWM_MASK);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- RtrigRegister = ((u32)TriggerLevel) & (u32)XUARTPS_RXWM_MASK;
-
- /*
- * Write the new value for the FIFO control register to it such that the
- * threshold is changed
- */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_RXWM_OFFSET, RtrigRegister);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the modem status from the specified UART. The modem
-* status indicates any changes of the modem signals. This function allows
-* the modem status to be read in a polled mode. The modem status is updated
-* whenever it is read such that reading it twice may not yield the same
-* results.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-*
-* The modem status which are bit masks that are contained in the file
-* xuartps.h and named XUARTPS_MODEM_*.
-*
-* @note
-*
-* The bit masks used for the modem status are the exact bits of the modem
-* status register with no abstraction.
-*
-*****************************************************************************/
-u16 XUartPs_GetModemStatus(XUartPs *InstancePtr)
-{
- u32 ModemStatusRegister;
- u16 TmpRegister;
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Read the modem status register to return
- */
- ModemStatusRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_MODEMSR_OFFSET);
- TmpRegister = (u16)ModemStatusRegister;
- return TmpRegister;
-}
-
-/****************************************************************************/
-/**
-*
-* This function determines if the specified UART is sending data.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-* - TRUE if the UART is sending data
-* - FALSE if UART is not sending data
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XUartPs_IsSending(XUartPs *InstancePtr)
-{
- u32 ChanStatRegister;
- u32 ChanTmpSRegister;
- u32 ActiveResult;
- u32 EmptyResult;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the channel status register to determine if the transmitter is
- * active
- */
- ChanStatRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_SR_OFFSET);
-
- /*
- * If the transmitter is active, or the TX FIFO is not empty, then indicate
- * that the UART is still sending some data
- */
- ActiveResult = ChanStatRegister & ((u32)XUARTPS_SR_TACTIVE);
- EmptyResult = ChanStatRegister & ((u32)XUARTPS_SR_TXEMPTY);
- ChanTmpSRegister = (((u32)XUARTPS_SR_TACTIVE) == ActiveResult) ||
- (((u32)XUARTPS_SR_TXEMPTY) != EmptyResult);
-#if defined (XCLOCKING)
- if (!ChanTmpSRegister)
- Xil_ClockDisable(InstancePtr->Config.RefClk);
-#endif
- return ChanTmpSRegister;
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the operational mode of the UART. The UART can operate
-* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
-* echo.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-*
-* The operational mode is specified by constants defined in xuartps.h. The
-* constants are named XUARTPS_OPER_MODE_*
-*
-* @note None.
-*
-*****************************************************************************/
-u8 XUartPs_GetOperMode(XUartPs *InstancePtr)
-{
- u32 ModeRegister;
- u8 OperMode;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Read the Mode register. */
- ModeRegister =
- XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_MR_OFFSET);
-
- ModeRegister &= (u32)XUARTPS_MR_CHMODE_MASK;
- /* Return the constant */
- switch (ModeRegister) {
- case XUARTPS_MR_CHMODE_NORM:
- OperMode = XUARTPS_OPER_MODE_NORMAL;
- break;
- case XUARTPS_MR_CHMODE_ECHO:
- OperMode = XUARTPS_OPER_MODE_AUTO_ECHO;
- break;
- case XUARTPS_MR_CHMODE_L_LOOP:
- OperMode = XUARTPS_OPER_MODE_LOCAL_LOOP;
- break;
- case XUARTPS_MR_CHMODE_R_LOOP:
- OperMode = XUARTPS_OPER_MODE_REMOTE_LOOP;
- break;
- default:
- OperMode = (u8) ((ModeRegister & (u32)XUARTPS_MR_CHMODE_MASK) >>
- XUARTPS_MR_CHMODE_SHIFT);
- break;
- }
-
- return OperMode;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the operational mode of the UART. The UART can operate
-* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
-* echo.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param OperationMode is the mode of the UART.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode)
-{
- u32 ModeRegister;
-
- /* Assert validates the input arguments. */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(OperationMode <= XUARTPS_OPER_MODE_REMOTE_LOOP);
-
- /* Read the Mode register. */
- ModeRegister =
- XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_MR_OFFSET);
-
- /* Set the correct value by masking the bits, then ORing the const. */
- ModeRegister &= (u32)(~XUARTPS_MR_CHMODE_MASK);
-
- switch (OperationMode) {
- case XUARTPS_OPER_MODE_NORMAL:
- ModeRegister |= (u32)XUARTPS_MR_CHMODE_NORM;
- break;
- case XUARTPS_OPER_MODE_AUTO_ECHO:
- ModeRegister |= (u32)XUARTPS_MR_CHMODE_ECHO;
- break;
- case XUARTPS_OPER_MODE_LOCAL_LOOP:
- ModeRegister |= (u32)XUARTPS_MR_CHMODE_L_LOOP;
- break;
- case XUARTPS_OPER_MODE_REMOTE_LOOP:
- ModeRegister |= (u32)XUARTPS_MR_CHMODE_R_LOOP;
- break;
- default:
- /* Default case made for MISRA-C Compliance. */
- break;
- }
-
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
- ModeRegister);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the Flow Delay.
-* 0 - 3: Flow delay inactive
-* 4 - 32: If Flow Control mode is enabled, UART_rtsN is deactivated when the
-* receive FIFO fills to this level.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-*
-* The Flow Delay is specified by constants defined in xuartps_hw.h. The
-* constants are named XUARTPS_FLOWDEL*
-*
-* @note None.
-*
-*****************************************************************************/
-u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr)
-{
- u32 FdelTmpRegister;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Read the Mode register. */
- FdelTmpRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_FLOWDEL_OFFSET);
-
- /* Return the contents of the flow delay register */
- FdelTmpRegister = (u8)(FdelTmpRegister & (u32)XUARTPS_FLOWDEL_MASK);
- return FdelTmpRegister;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the Flow Delay.
-* 0 - 3: Flow delay inactive
-* 4 - 63: If Flow Control mode is enabled, UART_rtsN is deactivated when the
-* receive FIFO fills to this level.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param FlowDelayValue is the Setting for the flow delay.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue)
-{
- u32 FdelRegister;
-
- /* Assert validates the input arguments */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(FlowDelayValue > (u8)XUARTPS_FLOWDEL_MASK);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Set the correct value by shifting the input constant, then masking
- * the bits
- */
- FdelRegister = ((u32)FlowDelayValue) & (u32)XUARTPS_FLOWDEL_MASK;
-
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_FLOWDEL_OFFSET, FdelRegister);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the Receive Timeout of the UART.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return The current setting for receive time out.
-*
-* @note None.
-*
-*****************************************************************************/
-u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr)
-{
- u32 RtoRegister;
- u8 RtoRTmpRegister;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Read the Receive Timeout register. */
- RtoRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_RXTOUT_OFFSET);
-
- /* Return the contents of the mode register shifted appropriately */
- RtoRTmpRegister = (u8)(RtoRegister & (u32)XUARTPS_RXTOUT_MASK);
- return RtoRTmpRegister;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the Receive Timeout of the UART.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param RecvTimeout setting allows the UART to detect an idle connection
-* on the receiver data line.
-* Timeout duration = RecvTimeout x 4 x Bit Period. 0 disables the
-* timeout function.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout)
-{
- u32 RtoRegister;
-
- /* Assert validates the input arguments */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Set the correct value by masking the bits */
- RtoRegister = ((u32)RecvTimeout & (u32)XUARTPS_RXTOUT_MASK);
-
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_RXTOUT_OFFSET, RtoRegister);
-
- /* Configure CR to restart the receiver timeout counter */
- RtoRegister =
- XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_CR_OFFSET);
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
- (RtoRegister | XUARTPS_CR_TORST));
-
-}
-/****************************************************************************/
-/**
-*
-* Sets the data format for the device. The data format includes the
-* baud rate, number of data bits, number of stop bits, and parity. It is the
-* caller's responsibility to ensure that the UART is not sending or receiving
-* data when this function is called.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param FormatPtr is a pointer to a format structure containing the data
-* format to be set.
-*
-* @return
-* - XST_SUCCESS if the data format was successfully set.
-* - XST_UART_BAUD_ERROR indicates the baud rate could not be
-* set because of the amount of error with the baud rate and
-* the input clock frequency.
-* - XST_INVALID_PARAM if one of the parameters was not valid.
-*
-* @note
-*
-* The data types in the format type, data bits and parity, are 32 bit fields
-* to prevent a compiler warning.
-* The asserts in this function will cause a warning if these fields are
-* bytes.
-*
-*
-*****************************************************************************/
-s32 XUartPs_SetDataFormat(XUartPs *InstancePtr,
- XUartPsFormat * FormatPtr)
-{
- s32 Status;
- u32 ModeRegister;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(FormatPtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Verify the inputs specified are valid */
- if ((FormatPtr->DataBits > ((u32)XUARTPS_FORMAT_6_BITS)) ||
- (FormatPtr->StopBits > ((u8)XUARTPS_FORMAT_2_STOP_BIT)) ||
- (FormatPtr->Parity > ((u32)XUARTPS_FORMAT_NO_PARITY))) {
- Status = XST_INVALID_PARAM;
- } else {
-
- /*
- * Try to set the baud rate and if it's not successful then don't
- * continue altering the data format, this is done first to avoid the
- * format from being altered when an error occurs
- */
- Status = XUartPs_SetBaudRate(InstancePtr, FormatPtr->BaudRate);
- if (Status != (s32)XST_SUCCESS) {
- ;
- } else {
-
- ModeRegister =
- XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_MR_OFFSET);
-
- /*
- * Set the length of data (8,7,6) by first clearing out the bits
- * that control it in the register, then set the length in the register
- */
- ModeRegister &= (u32)(~XUARTPS_MR_CHARLEN_MASK);
- ModeRegister |= (FormatPtr->DataBits << XUARTPS_MR_CHARLEN_SHIFT);
-
- /*
- * Set the number of stop bits in the mode register by first clearing
- * out the bits that control it in the register, then set the number
- * of stop bits in the register.
- */
- ModeRegister &= (u32)(~XUARTPS_MR_STOPMODE_MASK);
- ModeRegister |= (((u32)FormatPtr->StopBits) << XUARTPS_MR_STOPMODE_SHIFT);
-
- /*
- * Set the parity by first clearing out the bits that control it in the
- * register, then set the bits in the register, the default is no parity
- * after clearing the register bits
- */
- ModeRegister &= (u32)(~XUARTPS_MR_PARITY_MASK);
- ModeRegister |= (FormatPtr->Parity << XUARTPS_MR_PARITY_SHIFT);
-
- /* Update the mode register */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
- ModeRegister);
-
- Status = XST_SUCCESS;
- }
- }
- return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* Gets the data format for the specified UART. The data format includes the
-* baud rate, number of data bits, number of stop bits, and parity.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param FormatPtr is a pointer to a format structure that will contain
-* the data format after this call completes.
-*
-* @return None.
-*
-* @note None.
-*
-*
-*****************************************************************************/
-void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr)
-{
- u32 ModeRegister;
-
-
- /* Assert validates the input arguments */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(FormatPtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Get the baud rate from the instance, this is not retrieved from the
- * hardware because it is only kept as a divisor such that it is more
- * difficult to get back to the baud rate
- */
- FormatPtr->BaudRate = InstancePtr->BaudRate;
-
- ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_MR_OFFSET);
-
- /* Get the length of data (8,7,6,5) */
- FormatPtr->DataBits =
- ((ModeRegister & (u32)XUARTPS_MR_CHARLEN_MASK) >>
- XUARTPS_MR_CHARLEN_SHIFT);
-
- /* Get the number of stop bits */
- FormatPtr->StopBits =
- (u8)((ModeRegister & (u32)XUARTPS_MR_STOPMODE_MASK) >>
- XUARTPS_MR_STOPMODE_SHIFT);
-
- /* Determine what parity is */
- FormatPtr->Parity =
- (u32)((ModeRegister & (u32)XUARTPS_MR_PARITY_MASK) >>
- XUARTPS_MR_PARITY_SHIFT);
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/608cd5595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/608cd5595243001d18b399c1eb9b3628
deleted file mode 100644
index b924726..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/608cd5595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,507 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
- *
- * @file xusbps_endpoint.h
-* @addtogroup usbps_v2_7
-* @{
- *
- * This is an internal file containung the definitions for endpoints. It is
- * included by the xusbps_endpoint.c which is implementing the endpoint
- * functions and by xusbps_intr.c.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- --------------------------------------------------------
- * 1.00a wgr 10/10/10 First release
- * 2.5 pm 02/20/20 Added multiplier bit for ISO frame handling.
- *
- *
- ******************************************************************************/
-#ifndef XUSBPS_ENDPOINT_H
-#define XUSBPS_ENDPOINT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xusbps.h"
-#include "xil_types.h"
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-
-/**
- * Endpoint Device Transfer Descriptor
- *
- * The dTD describes to the device controller the location and quantity of data
- * to be sent/received for given transfer. The driver does not attempt to
- * modify any field in an active dTD except the Next Link Pointer.
- */
-#define XUSBPS_dTDNLP 0x00 /**< Pointer to the next descriptor */
-#define XUSBPS_dTDTOKEN 0x04 /**< Descriptor Token */
-#define XUSBPS_dTDBPTR0 0x08 /**< Buffer Pointer 0 */
-#define XUSBPS_dTDBPTR1 0x0C /**< Buffer Pointer 1 */
-#define XUSBPS_dTDBPTR2 0x10 /**< Buffer Pointer 2 */
-#define XUSBPS_dTDBPTR3 0x14 /**< Buffer Pointer 3 */
-#define XUSBPS_dTDBPTR4 0x18 /**< Buffer Pointer 4 */
-#define XUSBPS_dTDBPTR(n) (XUSBPS_dTDBPTR0 + (n) * 0x04)
-#define XUSBPS_dTDRSRVD 0x1C /**< Reserved field */
-
-/* We use the reserved field in the dTD to store user data. */
-#define XUSBPS_dTDUSERDATA XUSBPS_dTDRSRVD /**< Reserved field */
-
-
-/** @name dTD Next Link Pointer (dTDNLP) bit positions.
- * @{
- */
-#define XUSBPS_dTDNLP_T_MASK 0x00000001
- /**< USB dTD Next Link Pointer Terminate Bit */
-#define XUSBPS_dTDNLP_ADDR_MASK 0xFFFFFFE0
- /**< USB dTD Next Link Pointer Address [31:5] */
-/* @} */
-
-
-/** @name dTD Token (dTDTOKEN) bit positions.
- * @{
- */
-#define XUSBPS_dTDTOKEN_XERR_MASK 0x00000008 /**< dTD Transaction Error */
-#define XUSBPS_dTDTOKEN_BUFERR_MASK 0x00000020 /**< dTD Data Buffer Error */
-#define XUSBPS_dTDTOKEN_HALT_MASK 0x00000040 /**< dTD Halted Flag */
-#define XUSBPS_dTDTOKEN_ACTIVE_MASK 0x00000080 /**< dTD Active Bit */
-#define XUSBPS_dTDTOKEN_MULTO_MASK 0x00000C00 /**< Multiplier Override Field [1:0] */
-#define XUSBPS_dTDTOKEN_IOC_MASK 0x00008000 /**< Interrupt on Complete Bit */
-#define XUSBPS_dTDTOKEN_LEN_MASK 0x7FFF0000 /**< Transfer Length Field */
-/* @} */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- *
- * IMPORTANT NOTE:
- * ===============
- *
- * Many of the following macros modify Device Queue Head (dQH) data structures
- * and Device Transfer Descriptor (dTD) data structures. Those structures can
- * potentially reside in CACHED memory. Therefore, it's the callers
- * responsibility to ensure cache coherency by using provided
- *
- * XUsbPs_dQHInvalidateCache()
- * XUsbPs_dQHFlushCache()
- * XUsbPs_dTDInvalidateCache()
- * XUsbPs_dTDFlushCache()
- *
- * function calls.
- *
- ******************************************************************************/
-#define XUsbPs_dTDInvalidateCache(dTDPtr) \
- Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
-
-#define XUsbPs_dTDFlushCache(dTDPtr) \
- Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
-
-#define XUsbPs_dQHInvalidateCache(dQHPtr) \
- Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
-
-#define XUsbPs_dQHFlushCache(dQHPtr) \
- Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Transfer Length for the given Transfer Descriptor.
- *
- * @param dTDPtr is pointer to the dTD element.
- * @param Len is the length to be set. Range: 0..16384
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetTransferLen(dTDPtr, Len) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
- ~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16))
-
-
-/*****************************************************************************/
-/**
- *
- * This macro gets the Next Link pointer of the given Transfer Descriptor.
- *
- * @param dTDPtr is pointer to the dTD element.
- *
- * @return TransferLength field of the descriptor.
- *
- * @note C-style signature:
- * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDGetNLP(dTDPtr) \
- (XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\
- & XUSBPS_dTDNLP_ADDR_MASK))
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Next Link pointer of the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- * @param NLP is the Next Link Pointer
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetNLP(dTDPtr, NLP) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
- (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
- ~XUSBPS_dTDNLP_ADDR_MASK) | \
- ((NLP) & XUSBPS_dTDNLP_ADDR_MASK))
-
-
-/*****************************************************************************/
-/**
- *
- * This macro gets the Transfer Length for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @return TransferLength field of the descriptor.
- *
- * @note C-style signature:
- * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDGetTransferLen(dTDPtr) \
- (u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) \
- & XUSBPS_dTDTOKEN_LEN_MASK) >> 16)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Interrupt On Complete (IOC) bit for the given Transfer
- * Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetIOC(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetIOC(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
- XUSBPS_dTDTOKEN_IOC_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Terminate bit for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetTerminate(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetTerminate(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) | \
- XUSBPS_dTDNLP_T_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro clears the Terminate bit for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDClrTerminate(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDClrTerminate(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
- ~XUSBPS_dTDNLP_T_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro checks if the given descriptor is active.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @return
- * - TRUE: The buffer is active.
- * - FALSE: The buffer is not active.
- *
- * @note C-style signature:
- * int XUsbPs_dTDIsActive(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDIsActive(dTDPtr) \
- ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
- XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Active bit for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetActive(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetActive(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
- XUSBPS_dTDTOKEN_ACTIVE_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the multiplier bit for the Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- * @param val is the multiplier value.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetMultO(u32 dTDPtr, u32 val)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetMultO(dTDPtr, val) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
- (~XUSBPS_dTDTOKEN_MULTO_MASK)) | val)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro reads the content of a field in a Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- * @param Id is the field ID inside the dTD element to read.
- *
- * @note C-style signature:
- * u32 XUsbPs_ReaddTD(u32 dTDPtr, u32 Id)
- *
- ******************************************************************************/
-#define XUsbPs_ReaddTD(dTDPtr, Id) (*(u32 *)((u32)(dTDPtr) + (u32)(Id)))
-
-/*****************************************************************************/
-/**
- *
- * This macro writes a value to a field in a Transfer Descriptor.
- *
- * @param dTDPtr is pointer to the dTD element.
- * @param Id is the field ID inside the dTD element to read.
- * @param Val is the value to write to the field.
- *
- * @note C-style signature:
- * u32 XUsbPs_WritedTD(u32 dTDPtr, u32 Id, u32 Val)
- *
- ******************************************************************************/
-#define XUsbPs_WritedTD(dTDPtr, Id, Val) \
- (*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val))
-
-
-/******************************************************************************/
-/**
- * Endpoint Device Queue Head
- *
- * Device queue heads are arranged in an array in a continuous area of memory
- * pointed to by the ENDPOINTLISTADDR pointer. The device controller will index
- * into this array based upon the endpoint number received from the USB bus.
- * All information necessary to respond to transactions for all primed
- * transfers is contained in this list so the Device Controller can readily
- * respond to incoming requests without having to traverse a linked list.
- *
- * The device Endpoint Queue Head (dQH) is where all transfers are managed. The
- * dQH is a 48-byte data structure, but must be aligned on a 64-byte boundary.
- * During priming of an endpoint, the dTD (device transfer descriptor) is
- * copied into the overlay area of the dQH, which starts at the nextTD pointer
- * DWord and continues through the end of the buffer pointers DWords. After a
- * transfer is complete, the dTD status DWord is updated in the dTD pointed to
- * by the currentTD pointer. While a packet is in progress, the overlay area of
- * the dQH is used as a staging area for the dTD so that the Device Controller
- * can access needed information with little minimal latency.
- *
- * @note
- * Software must ensure that no interface data structure reachable by the
- * Device Controller spans a 4K-page boundary. The first element of the
- * Endpoint Queue Head List must be aligned on a 4K boundary.
- */
-#define XUSBPS_dQHCFG 0x00 /**< dQH Configuration */
-#define XUSBPS_dQHCPTR 0x04 /**< dQH Current dTD Pointer */
-#define XUSBPS_dQHdTDNLP 0x08 /**< dTD Next Link Ptr in dQH
- overlay */
-#define XUSBPS_dQHdTDTOKEN 0x0C /**< dTD Token in dQH overlay */
-#define XUSBPS_dQHSUB0 0x28 /**< USB dQH Setup Buffer 0 */
-#define XUSBPS_dQHSUB1 0x2C /**< USB dQH Setup Buffer 1 */
-
-
-/** @name dQH Configuration (dQHCFG) bit positions.
- * @{
- */
-#define XUSBPS_dQHCFG_IOS_MASK 0x00008000
- /**< USB dQH Interrupt on Setup Bit */
-#define XUSBPS_dQHCFG_MPL_MASK 0x07FF0000
- /**< USB dQH Maximum Packet Length
- * Field [10:0] */
-#define XUSBPS_dQHCFG_MPL_SHIFT 16
-#define XUSBPS_dQHCFG_ZLT_MASK 0x20000000
- /**< USB dQH Zero Length Termination
- * Select Bit */
-#define XUSBPS_dQHCFG_MULT_MASK 0xC0000000
- /* USB dQH Number of Transactions Field
- * [1:0] */
-#define XUSBPS_dQHCFG_MULT_SHIFT 30
-/* @} */
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Maximum Packet Length field of the give Queue Head.
- *
- * @param dQHPtr is a pointer to the dQH element.
- * @param Len is the length to be set.
- *
- * @note C-style signature:
- * void XUsbPs_dQHSetMaxPacketLen(u32 dQHPtr, u32 Len)
- *
- ******************************************************************************/
-#define XUsbPs_dQHSetMaxPacketLen(dQHPtr, Len) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
- ~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16))
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Interrupt On Setup (IOS) bit for an endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHSetIOS(u32 dQHPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dQHSetIOS(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
- XUSBPS_dQHCFG_IOS_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro clears the Interrupt On Setup (IOS) bit for an endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHClrIOS(u32 dQHPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dQHClrIOS(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
- ~XUSBPS_dQHCFG_IOS_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro enables Zero Length Termination for the endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHEnableZLT(u32 dQHPtr)
- *
- *
- ******************************************************************************/
-#define XUsbPs_dQHEnableZLT(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
- ~XUSBPS_dQHCFG_ZLT_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro disables Zero Length Termination for the endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHDisableZLT(u32 dQHPtr)
- *
- *
- ******************************************************************************/
-#define XUsbPs_dQHDisableZLT(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
- XUSBPS_dQHCFG_ZLT_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro reads the content of a field in a Queue Head.
- *
- * @param dQHPtr is a pointer to the dQH element.
- * @param Id is the Field ID inside the dQH element to read.
- *
- * @note C-style signature:
- * u32 XUsbPs_ReaddQH(u32 dQHPtr, u32 Id)
- *
- ******************************************************************************/
-#define XUsbPs_ReaddQH(dQHPtr, Id) (*(u32 *)((u32)(dQHPtr) + (u32) (Id)))
-
-/*****************************************************************************/
-/**
- *
- * This macro writes a value to a field in a Queue Head.
- *
- * @param dQHPtr is a pointer to the dQH element.
- * @param Id is the Field ID inside the dQH element to read.
- * @param Val is the Value to write to the field.
- *
- * @note C-style signature:
- * u32 XUsbPs_WritedQH(u32 dQHPtr, u32 Id, u32 Val)
- *
- ******************************************************************************/
-#define XUsbPs_WritedQH(dQHPtr, Id, Val) \
- (*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val))
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XUSBPS_ENDPOINT_H */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/70ed78595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/70ed78595243001d18b399c1eb9b3628
deleted file mode 100644
index f6678a8..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/70ed78595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,62 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.c
-*
-* @addtogroup microblaze_cache_apis Microblaze Cache APIs
-* @{
-*
-* This contains implementation of cache related driver functions.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00 hbm 07/28/09 Initial release
-* 3.10 asa 05/04/13 This version of MicroBlaze BSP adds support for system
-* cache/L2 cache. Existing APIs in this file are modified
-* to add support for L2 cache.
-* These changes are done for implementing PR #697214.
-*
-*
-*
-******************************************************************************/
-
-#include "xil_cache.h"
-
-
-/****************************************************************************/
-/**
-*
-* @brief Disable the data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheDisable(void)
-{
- Xil_DCacheFlush();
- Xil_DCacheInvalidate();
- Xil_L1DCacheDisable();
-}
-
-/****************************************************************************/
-/**
-*
-* @brief Disable the instruction cache.
-*
-* @return None.
-*
-*
-****************************************************************************/
-void Xil_ICacheDisable(void)
-{
- Xil_ICacheInvalidate();
- Xil_L1ICacheDisable();
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/726492555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/726492555243001d18b399c1eb9b3628
deleted file mode 100644
index 811d2b0..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/726492555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,23 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#ifndef UNDEFINE_FILE_OPS
-#include "xil_types.h"
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) s32 _close(s32 fd);
-}
-#endif
-
-/*
- * close -- We don't need to do anything, but pretend we did.
- */
-
-__attribute__((weak)) s32 _close(s32 fd)
-{
- (void)fd;
- return (0);
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/917ee8565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/917ee8565243001d18b399c1eb9b3628
deleted file mode 100644
index e40988e..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/917ee8565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,366 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_spinlock.c
-*
-* Implements a spinlocking mechanism using ARM load-exclusive and
-* store-exclusive instructions.
-*
-* spinlocks in baremetal world are useful mainly for AMP kind of use cases
-* where different applications run in different CPUs in a CPU cluster and
-* they have a common resource to work with.
-* A simple yet common example is:
-* R5-0 and R5-1 have separate applications and at runtime they try to access a
-* shared register space (GIC) or shared memory space. Mutual exclusion is
-* really needed for such use cases.
-* Similar use case applies for Zynq CortexA9-0 and CortesA9-1.
-*
-* The spinlock mechanism provided with this file is very simple to cater to
-* baremetal world requirements.
-*
-* A) Unlike OS type of use cases, at any point of time, only a single lock
-* can be used. There is no way in BM world we can support multiple locks
-* at the same time.
-* B) The spinlocking is available for ARM v7 (Cortex-R5 and Cortex-A9).
-* C) Users need to provide a lock (essentially a shared address), and a flag
-* (also a shared address) for spinlocking to work. These shared addresses
-* must be agreed upon by apps running on both CPUs. Needless to say,
-* the linker scripts must change accordingly so that apps running on both
-* CPUs can have a shared DDR region from which address can be used for
-* spinlocking.
-* D) The address that is used for spinlocking and the address that is used
-* as flag address must be in a memory region that is strongly-ordered
-* or device memory.
-* E) Like any similar standard use cases, one application running in any
-* of the CPUs must create the spinlock address. It is advisable that the
-* the same application must destroy or release the spinlock address,
-* though nothing stops the other CPU in destroying and releasing the
-* spinlock addresses. There has to be understanding between applications
-* running on both the CPUs to ensure that correct ordering is followed.
-* Once a spinlock is released, it spinlock APIs cannot be used anymore.
-* F) Once a spinlock address is created it can be used any number of times
-* to protect critical sections as long as a certain set of rules are
-* followed and a certain set of sequences are followed. More about the
-* sequences later in this description.
-* G) To re-iterate, the spinlocking mechanism provided through this file is
-* pretty rudimentary. Users can always improvise. The use case that
-* the whole mechanism is trying to solve is: common register space
-* being accesses in an AMP scenario by independent applications running
-* at multiple CPUs.
-*
-* The usage of APIs provided in this file are summarized below.
-* A) Applications running at both the CPUs ensure that they allocate shared
-* memory space to be used for locking and flag maintenance.
-* B) The memory allocated as shared should be of minimum size 1 MB. This
-* limitation is because the way translation tables/memory map is setup
-* for R5 or A9. In future, this limitation can be brought down 4 KB.
-* C) The spinlock and the flag address must be uncached. Users need to c
-* all Xilinx provided API Xil_SetTlbAttributes to mark the shared
-* 1 MB memory space as strongly ordered or device memory.
-* D) Both the applications must call the API Xil_InitializeSpinLock with
-* the spinlock address, flag address and flag value to be used. Currently
-* only one flag value is supported (i.e. XIL_SPINLOCK_ENABLE with
-* a value of 1).
-* Only if the Xil_InitializeSpinLock returns success, should they
-* proceed to use Xil_SpinLock and Xil_SpinUnlock.
-* F) Afterwards applications can start using the APIs Xil_SpinLock() and
-* Xil_SpinUnlock() to protect the critical sections.
-* G) It is highly suggested to use Xil_IsSpinLockEnabled() as a check
-* before using Xil_SpinLock() or Xil_SpinUnlock(). Refer to the code
-* snippet below.
-* H) If spinlock is no more needed by an application, they can use the API
-* Xil_ReleaseSpinLock().
-* I) Once a spinlock is created it can be used as many numbers of time as
-* needed.
-*
-* A typical code snippet with R5 as an example and lock address falling
-* in the 1 MB memory region (0x300000 to 0x400000) is given below.
-*
-* Code snippet for R5-0 (that runs first):
-* int main()
-* {
-* u32 *sharedlockaddr = (int *)0x300008;
-* u32 *sharedlockflagaddr = int *)0x30000C;
-* Xil_SetTlbAttributes(0x300000,STRONG_ORDERD_SHARED | PRIV_RW_USER_RW);
-* Xil_InitializeSpinLock((UINTPTR)sharedlockaddr,(UINTPTR)sharedlockflagaddr,
-* XIL_SPINLOCK_ENABLE);
-* ....
-* ....
-* if (Xil_IsSpinLockEnabled())
-* Xil_SpinLock();
-* // Critical Section
-* ....
-* ....
-* if (Xil_IsSpinLockEnabled())
-* Xil_SpinUnlock();
-* .....
-* .....
-* Xil_ReleaseSpinLock();
-* } // End of main
-*
-* * Code snippet for R5-1 (that runs second):
-* int main()
-* {
-* u32 *sharedlockaddr = (int *)0x300008;
-* u32 *sharedlockflagaddr = int *)0x30000C;
-* Xil_SetTlbAttributes(0x300000,STRONG_ORDERD_SHARED | PRIV_RW_USER_RW);
-* Xil_InitializeSpinLock((UINTPTR)sharedlockaddr,(UINTPTR)sharedlockflagaddr,
-* XIL_SPINLOCK_ENABLE);
-* ....
-* if (Xil_IsSpinLockEnabled())
-* Xil_SpinLock();
-* // Critical Section
-* ....
-* ....
-* if (Xil_IsSpinLockEnabled())
-* Xil_SpinUnlock();
-* .....
-* .....
-* Xil_ReleaseSpinLock();
-* } // End of main
-*
-* Xil_SpinLock() and Xil_SpinLock() return XST_FAILURE if the spinlock
-* is initialized. Instead of calling Xil_IsSpinLockEnabled before using
-* Xil_SpinLock() or Xil_SpinLock(), users can also check the return
-* value of Xil_SpinLock and Xil_SpinLock. If a lock is not initialized,
-* Xil_SpinLock will just return failure and not perform load-exclusive
-* operations.
-*
-* Guidelines on when to use the spinlocking mechanism in Xilinx baremetal
-* environment:
-* A) Spinlocking mechanism can only be used for Cortex-R5s (split mode)
-* and Cortex-A9s (Zynq).
-* B) In Cortex-R5 split mode or Cortex-A9 cluster, applications running on
-* both the CPUs, by design should never be sharing the same peripheral.
-* It is impossible to support such use cases reliably.
-* Hence none of the peripheral drivers (except GIC driver) have
-* spinlocking support added into their APIs.
-* C) GIC register space is shared by both the CPUs (R5 split mode, A9s).
-* The GIC driver APIs have spinlocking mechanism added to the relevant
-* APIs. Users need to follow the guidelines stated earlier to enable
-* the spinlocks and use them.
-* It is really advisable to use spinlock mechanism for use cases where
-* applications running on multiple CPUs can simultaneously access
-* GIC register space through driver APIs.
-* D) The spinlock mechanism can be used to protect any critical region
-* implemented through shared memory space.
-*
-* IMPORTANT NOTE: Circular spinlocks are not allowed (as expected).
-* Use case where an application calls Xil_SpinLock back to back without
-* calling Xil_SpinUnlock in between will/may result in a deadlock
-* condition.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 7.5 asa 02/23/21 First release
-* 7.5 asa 04/28/21 Fixed bug Xil_IsSpinLockEnabled to avoid
-* dereferencing to address zero.
-*
-*
-******************************************************************************/
-
-
-/***************************** Include Files ********************************/
-#if !defined (__aarch64__) && defined(__GNUC__) && !defined(__clang__)
-#include "xil_spinlock.h"
-
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-
-/************************** Variable Definitions ****************************/
-static UINTPTR Xil_Spinlock_Addr = 0x0;
-static UINTPTR Xil_Spinlock_Flag_Addr = 0x0;
-
-/************************** Function Prototypes *****************************/
-
-/****************************************************************************/
-/**
-*
-* @brief Used at the beginning of a critical section. This API takes the
-* lock using load-exclusive and store-exclusive operations. In
-* case the lock is not available (being held by an application
-* running at the other CPU and doing operations inside the
-* critical section, the control will never go out from the API
-* till the other CPU releases the lock.
-*
-* @param None.
-*
-* @return XST_FAILURE: If spinlock is not properly initialized.
-* XST_SUCCESS: If the lock was successfully obtained.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 Xil_SpinLock(void)
-{
- UINTPTR lockaddr = Xil_Spinlock_Addr;
- u32 LockTempVar;
-
- if (Xil_Spinlock_Addr == 0) {
- return XST_FAILURE;
- }
-
- __asm__ __volatile__(
- "1: ldrex %0, [%1] \n"
- " teq %0, %3 \n"
- " strexeq %0, %2, [%1] \n"
- " teqeq %0, #0 \n"
- " bne 1b \n"
- " dmb \n"
- : "=&r" (LockTempVar)
- : "r" (lockaddr), "r"(XIL_SPINLOCK_LOCKVAL), "r"(XIL_SPINLOCK_RESETVAL)
- : "cc");
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* @brief Used to release a lock previously held by calling Xil_SpinLock.
-*
-* @param None.
-*
-* @return XST_FAILURE: If spinlock is not properly initialized.
-* XST_SUCCESS: If the lock was successfully obtained.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 Xil_SpinUnlock(void)
-{
- UINTPTR lockaddr = Xil_Spinlock_Addr;
-
- if (Xil_Spinlock_Addr == 0) {
- return XST_FAILURE;
- }
- __asm__ __volatile__(
- "dmb \n"
- "str %1, [%0] \n"
- :
- : "r" (lockaddr), "r" (XIL_SPINLOCK_RESETVAL)
- : "cc");
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-* @brief Used to initialize a spinlock.
-*
-* @param lockaddr: Address of the lock variable. The address must be in
-* a shared memory region.
-* lockflagaddr: Address of the flag variable. The address must be
-* in a shared memory region.
-* lockflag: The value of the flag. Currently only one value
-* is supported, which is XIL_SPINLOCK_ENABLE.
-*
-* @return XST_SUCCESS, if the initialization succeeded.
-* XST_FAILURE, if the initialization failed
-*
-* @note None.
-*
-*****************************************************************************/
-u32 Xil_InitializeSpinLock(UINTPTR lockaddr, UINTPTR lockflagaddr,
- u32 lockflag)
-{
- if (Xil_Spinlock_Flag_Addr == 0) {
- Xil_Spinlock_Flag_Addr = lockflagaddr;
- if (*(u32 *)Xil_Spinlock_Flag_Addr == XIL_SPINLOCK_ENABLED) {
- /*
- * spinlock is already initialized by one of the CPUs, just update
- * the local variable Xil_Spinlock_Addr with the passed address
- * and dont write to the lock value as it might be currently
- * getting used.
- */
- /*
- * Ensure to update the global variable Xil_Spinlock_Addr only
- * if it is zero. A non-zero value may mean that there is something
- * wrong.
- */
- if (Xil_Spinlock_Addr == 0) {
- Xil_Spinlock_Addr = lockaddr;
- } else {
- /*
- * May be spinlock is already initialized and the user has not
- * called Xil_ReleaseSpinLock before calling Xil_InitializeSpinLock.
- */
- return XST_FAILURE;
- }
- } else {
- /* All good, do the necessary initializations */
- Xil_Spinlock_Addr = lockaddr;
- *(u32 *)(Xil_Spinlock_Addr) = XIL_SPINLOCK_RESETVAL;
- *(u32 *)(Xil_Spinlock_Flag_Addr) = lockflag;
- }
- return XST_SUCCESS;
- } else {
- /*
- * Most probably spinlock is already initialized and the user has not
- * called Xil_ReleaseSpinLock before calling Xil_InitializeSpinLock.
- */
- return XST_FAILURE;
- }
-}
-
-
-/****************************************************************************/
-/**
-* @brief Used to release the spinlock. Typically called by the application
-* once spinlock feature is no more required.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void Xil_ReleaseSpinLock(void)
-{
- Xil_Spinlock_Addr = 0;
- Xil_Spinlock_Flag_Addr = 0;
-}
-
-/****************************************************************************/
-/**
-* @brief Used to know if the spinlock feature has been enabled. To ensure
-* that spinlock feature does not break use cases where lock is
-* not initialized, the application must call this API first to know
-* if it can use spinlock. If this API returns non-zero value, an
-* application should then use Xil_SpinLock or Xil_SpinUnlock.
-*
-* @param None
-*
-* @return Non-zero, if spinlock is already initialized and can be used.
-* Zero, if spinlock is not initialized.
-*
-* @note
-*
-*****************************************************************************/
-u32 Xil_IsSpinLockEnabled(void)
-{
- u32 retVal = FALSE;
-
- if (Xil_Spinlock_Flag_Addr != 0) {
- if (*(u32 *)(Xil_Spinlock_Flag_Addr) == XIL_SPINLOCK_ENABLED) {
- retVal = TRUE;
- }
- }
- return retVal;
-}
-#endif /* !(__aarch64__) && (__GNUC__) && !(__clang__)*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/a0cff3535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/a0cff3535243001d18b399c1eb9b3628
deleted file mode 100644
index 4f985dc..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/a0cff3535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,505 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
- *
- * @file xusbps_hw.h
-* @addtogroup usbps_v2_7
-* @{
- *
- * This header file contains identifiers and low-level driver functions (or
- * macros) that can be used to access the device. High-level driver functions
- * are defined in xusbps.h.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.00a wgr 10/10/10 First release
- * 1.04a nm 10/23/12 Fixed CR# 679106.
- * 1.05a kpc 07/03/13 Added XUsbPs_ResetHw function prototype
- * 2.00a kpc 04/03/14 Fixed CR#777764. Corrected max endpoint vale and masks
- * 2.5 pm 02/20/20 Added Endpoint Control Register bit positions for Rx & Tx
- *
- *
- ******************************************************************************/
-#ifndef XUSBPS_HW_H
-#define XUSBPS_HW_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-
-#define XUSBPS_REG_SPACING 4
-
-/** @name Timer 0 Register offsets
- *
- * @{
- */
-#define XUSBPS_TIMER0_LD_OFFSET 0x00000080
-#define XUSBPS_TIMER0_CTL_OFFSET 0x00000084
-/* @} */
-
-/** @name Timer Control Register bit mask
- *
- * @{
- */
-#define XUSBPS_TIMER_RUN_MASK 0x80000000
-#define XUSBPS_TIMER_STOP_MASK 0x80000000
-#define XUSBPS_TIMER_RESET_MASK 0x40000000
-#define XUSBPS_TIMER_REPEAT_MASK 0x01000000
-/* @} */
-
-/** @name Timer Control Register bit mask
- *
- * @{
- */
-#define XUSBPS_TIMER_COUNTER_MASK 0x00FFFFFF
-/* @} */
-
-/** @name Device Hardware Parameters
- *
- * @{
- */
-#define XUSBPS_HWDEVICE_OFFSET 0x0000000C
-
-#define XUSBPS_EP_NUM_MASK 0x3E
-#define XUSBPS_EP_NUM_SHIFT 1
-/* @} */
-
-/** @name Capability Register offsets
- */
-#define XUSBPS_HCSPARAMS_OFFSET 0x00000104
-
-/** @name Operational Register offsets.
- * Register comments are tagged with "H:" and "D:" for Host and Device modes,
- * respectively.
- * Tags are only present for registers that have a different meaning DEVICE and
- * HOST modes. Most registers are only valid for either DEVICE or HOST mode.
- * Those registers don't have tags.
- * @{
- */
-#define XUSBPS_CMD_OFFSET 0x00000140 /**< Configuration */
-#define XUSBPS_ISR_OFFSET 0x00000144 /**< Interrupt Status */
-#define XUSBPS_IER_OFFSET 0x00000148 /**< Interrupt Enable */
-#define XUSBPS_FRAME_OFFSET 0x0000014C /**< USB Frame Index */
-#define XUSBPS_LISTBASE_OFFSET 0x00000154 /**< H: Periodic List Base Address */
-#define XUSBPS_DEVICEADDR_OFFSET 0x00000154 /**< D: Device Address */
-#define XUSBPS_ASYNCLISTADDR_OFFSET 0x00000158 /**< H: Async List Address */
-#define XUSBPS_EPLISTADDR_OFFSET 0x00000158 /**< D: Endpoint List Addr */
-#define XUSBPS_TTCTRL_OFFSET 0x0000015C /**< TT Control */
-#define XUSBPS_BURSTSIZE_OFFSET 0x00000160 /**< Burst Size */
-#define XUSBPS_TXFILL_OFFSET 0x00000164 /**< Tx Fill Tuning */
-#define XUSBPS_ULPIVIEW_OFFSET 0x00000170 /**< ULPI Viewport */
-#define XUSBPS_EPNAKISR_OFFSET 0x00000178 /**< Endpoint NAK IRQ Status */
-#define XUSBPS_EPNAKIER_OFFSET 0x0000017C /**< Endpoint NAK IRQ Enable */
-#define XUSBPS_PORTSCR1_OFFSET 0x00000184 /**< Port Control/Status 1 */
-
-/* NOTE: The Port Control / Status Register index is 1-based. */
-#define XUSBPS_PORTSCRn_OFFSET(n) \
- (XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING))
-
-
-#define XUSBPS_OTGCSR_OFFSET 0x000001A4 /**< OTG Status and Control */
-#define XUSBPS_MODE_OFFSET 0x000001A8 /**< USB Mode */
-#define XUSBPS_EPSTAT_OFFSET 0x000001AC /**< Endpoint Setup Status */
-#define XUSBPS_EPPRIME_OFFSET 0x000001B0 /**< Endpoint Prime */
-#define XUSBPS_EPFLUSH_OFFSET 0x000001B4 /**< Endpoint Flush */
-#define XUSBPS_EPRDY_OFFSET 0x000001B8 /**< Endpoint Ready */
-#define XUSBPS_EPCOMPL_OFFSET 0x000001BC /**< Endpoint Complete */
-#define XUSBPS_EPCR0_OFFSET 0x000001C0 /**< Endpoint Control 0 */
-#define XUSBPS_EPCR1_OFFSET 0x000001C4 /**< Endpoint Control 1 */
-#define XUSBPS_EPCR2_OFFSET 0x000001C8 /**< Endpoint Control 2 */
-#define XUSBPS_EPCR3_OFFSET 0x000001CC /**< Endpoint Control 3 */
-#define XUSBPS_EPCR4_OFFSET 0x000001D0 /**< Endpoint Control 4 */
-
-#define XUSBPS_MAX_ENDPOINTS 12 /**< Number of supported Endpoints in
- * this core. */
-#define XUSBPS_EP_OUT_MASK 0x00000FFF /**< OUR (RX) endpoint mask */
-#define XUSBPS_EP_IN_MASK 0x0FFF0000 /**< IN (TX) endpoint mask */
-#define XUSBPS_EP_ALL_MASK 0x0FFF0FFF /**< Mask used for endpoint control
- * registers */
-#define XUSBPS_EPCRn_OFFSET(n) \
- (XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING))
-
-#define XUSBPS_EPFLUSH_RX_SHIFT 0
-#define XUSBPS_EPFLUSH_TX_SHIFT 16
-
-/* @} */
-
-
-
-/** @name Endpoint Control Register (EPCR) bit positions.
- * @{
- */
-
-/* Definitions for TX Endpoint bits */
-#define XUSBPS_EPCR_TXT_TYPE_SHIFT 18 /* < Endpoint Type - TX bit shift*/
-#define XUSBPS_EPCR_TXT_TYPE_MASK 0x000C0000 /* < Endpoint Type - TX read only*/
-#define XUSBPS_EPCR_TXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - TX */
-#define XUSBPS_EPCR_TXT_ISO_MASK 0x00040000 /**< Isochronous. Endpoint */
-#define XUSBPS_EPCR_TXT_BULK_MASK 0x00080000 /**< Bulk Endpoint - TX */
-#define XUSBPS_EPCR_TXT_INTR_MASK 0x000C0000 /**< Interrupt Endpoint */
-#define XUSBPS_EPCR_TXS_MASK 0x00010000 /**< Stall TX endpoint */
-#define XUSBPS_EPCR_TXE_MASK 0x00800000 /**< Transmit enable - TX */
-#define XUSBPS_EPCR_TXR_MASK 0x00400000 /**< Data Toggle Reset Bit */
-
-
-/* Definitions for RX Endpoint bits */
-#define XUSBPS_EPCR_RXT_TYPE_SHIFT 2 /* < Endpoint Type - RX bit shift*/
-#define XUSBPS_EPCR_RXT_TYPE_MASK 0x0000000C /**< Endpoint Type - RX read only*/
-#define XUSBPS_EPCR_RXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - RX */
-#define XUSBPS_EPCR_RXT_ISO_MASK 0x00000004 /**< Isochronous Endpoint */
-#define XUSBPS_EPCR_RXT_BULK_MASK 0x00000008 /**< Bulk Endpoint - RX */
-#define XUSBPS_EPCR_RXT_INTR_MASK 0x0000000C /**< Interrupt Endpoint */
-#define XUSBPS_EPCR_RXS_MASK 0x00000001 /**< Stall RX endpoint. */
-#define XUSBPS_EPCR_RXE_MASK 0x00000080 /**< Transmit enable. - RX */
-#define XUSBPS_EPCR_RXR_MASK 0x00000040 /**< Data Toggle Reset Bit */
-/* @} */
-
-
-/** @name USB Command Register (CR) bit positions.
- * @{
- */
-#define XUSBPS_CMD_RS_MASK 0x00000001 /**< Run/Stop */
-#define XUSBPS_CMD_RST_MASK 0x00000002 /**< Controller RESET */
-#define XUSBPS_CMD_FS01_MASK 0x0000000C /**< Frame List Size bit 0,1 */
-#define XUSBPS_CMD_PSE_MASK 0x00000010 /**< Periodic Sched Enable */
-#define XUSBPS_CMD_ASE_MASK 0x00000020 /**< Async Sched Enable */
-#define XUSBPS_CMD_IAA_MASK 0x00000040 /**< IRQ Async Advance Doorbell */
-#define XUSBPS_CMD_ASP_MASK 0x00000300 /**< Async Sched Park Mode Cnt */
-#define XUSBPS_CMD_ASPE_MASK 0x00000800 /**< Async Sched Park Mode Enbl */
-#define XUSBPS_CMD_SUTW_MASK 0x00002000 /**< Setup TripWire */
-#define XUSBPS_CMD_ATDTW_MASK 0x00004000 /**< Add dTD TripWire */
-#define XUSBPS_CMD_FS2_MASK 0x00008000 /**< Frame List Size bit 2 */
-#define XUSBPS_CMD_ITC_MASK 0x00FF0000 /**< IRQ Threshold Control */
-/* @} */
-
-
-/**
- * @name Interrupt Threshold
- * These definitions are used by software to set the maximum rate at which the
- * USB controller will generate interrupt requests. The interrupt interval is
- * given in number of micro-frames.
- *
- * USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF)
- * packet each and every 1ms. USB also defines a high-speed micro-frame with a
- * 125us frame time. For each micro-frame a SOF (Start Of Frame) packet is
- * generated. Data is sent in between the SOF packets. The interrupt threshold
- * defines how many micro-frames the controller waits before issuing an
- * interrupt after data has been received.
- *
- * For a threshold of 0 the controller will issue an interrupt immediately
- * after the last byte of the data has been received. For a threshold n>0 the
- * controller will wait for n micro-frames before issuing an interrupt.
- *
- * Therefore, a setting of 8 micro-frames (default) means that the controller
- * will issue at most 1 interrupt per millisecond.
- *
- * @{
- */
-#define XUSBPS_CMD_ITHRESHOLD_0 0x00 /**< Immediate interrupt. */
-#define XUSBPS_CMD_ITHRESHOLD_1 0x01 /**< 1 micro-frame */
-#define XUSBPS_CMD_ITHRESHOLD_2 0x02 /**< 2 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_4 0x04 /**< 4 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_8 0x08 /**< 8 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_16 0x10 /**< 16 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_32 0x20 /**< 32 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_64 0x40 /**< 64 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_MAX XUSBPS_CMD_ITHRESHOLD_64
-#define XUSBPS_CMD_ITHRESHOLD_DEFAULT XUSBPS_CMD_ITHRESHOLD_8
-/* @} */
-
-
-
-/** @name USB Interrupt Status Register (ISR) / Interrupt Enable Register (IER)
- * bit positions.
- * @{
- */
-#define XUSBPS_IXR_UI_MASK 0x00000001 /**< USB Transaction Complete */
-#define XUSBPS_IXR_UE_MASK 0x00000002 /**< Transaction Error */
-#define XUSBPS_IXR_PC_MASK 0x00000004 /**< Port Change Detect */
-#define XUSBPS_IXR_FRE_MASK 0x00000008 /**< Frame List Rollover */
-#define XUSBPS_IXR_AA_MASK 0x00000020 /**< Async Advance */
-#define XUSBPS_IXR_UR_MASK 0x00000040 /**< RESET Received */
-#define XUSBPS_IXR_SR_MASK 0x00000080 /**< Start of Frame */
-#define XUSBPS_IXR_SLE_MASK 0x00000100 /**< Device Controller Suspend */
-#define XUSBPS_IXR_ULPI_MASK 0x00000400 /**< ULPI IRQ */
-#define XUSBPS_IXR_HCH_MASK 0x00001000 /**< Host Controller Halted
- * Read Only */
-#define XUSBPS_IXR_RCL_MASK 0x00002000 /**< USB Reclamation Read Only */
-#define XUSBPS_IXR_PS_MASK 0x00004000 /**< Periodic Sched Status
- * Read Only */
-#define XUSBPS_IXR_AS_MASK 0x00008000 /**< Async Sched Status Read only */
-#define XUSBPS_IXR_NAK_MASK 0x00010000 /**< NAK IRQ */
-#define XUSBPS_IXR_UA_MASK 0x00040000 /**< USB Host Async IRQ */
-#define XUSBPS_IXR_UP_MASK 0x00080000 /**< USB Host Periodic IRQ */
-#define XUSBPS_IXR_TI0_MASK 0x01000000 /**< Timer 0 Interrupt */
-#define XUSBPS_IXR_TI1_MASK 0x02000000 /**< Timer 1 Interrupt */
-
-#define XUSBPS_IXR_ALL (XUSBPS_IXR_UI_MASK | \
- XUSBPS_IXR_UE_MASK | \
- XUSBPS_IXR_PC_MASK | \
- XUSBPS_IXR_FRE_MASK | \
- XUSBPS_IXR_AA_MASK | \
- XUSBPS_IXR_UR_MASK | \
- XUSBPS_IXR_SR_MASK | \
- XUSBPS_IXR_SLE_MASK | \
- XUSBPS_IXR_ULPI_MASK | \
- XUSBPS_IXR_HCH_MASK | \
- XUSBPS_IXR_RCL_MASK | \
- XUSBPS_IXR_PS_MASK | \
- XUSBPS_IXR_AS_MASK | \
- XUSBPS_IXR_NAK_MASK | \
- XUSBPS_IXR_UA_MASK | \
- XUSBPS_IXR_UP_MASK | \
- XUSBPS_IXR_TI0_MASK | \
- XUSBPS_IXR_TI1_MASK)
- /**< Mask for ALL IRQ types */
-/* @} */
-
-
-/** @name USB Mode Register (MODE) bit positions.
- * @{
- */
-#define XUSBPS_MODE_CM_MASK 0x00000003 /**< Controller Mode Select */
-#define XUSBPS_MODE_CM_IDLE_MASK 0x00000000
-#define XUSBPS_MODE_CM_DEVICE_MASK 0x00000002
-#define XUSBPS_MODE_CM_HOST_MASK 0x00000003
-#define XUSBPS_MODE_ES_MASK 0x00000004 /**< USB Endian Select */
-#define XUSBPS_MODE_SLOM_MASK 0x00000008 /**< USB Setup Lockout Mode Disable */
-#define XUSBPS_MODE_SDIS_MASK 0x00000010
-#define XUSBPS_MODE_VALID_MASK 0x0000001F
-
-/* @} */
-
-
-/** @name USB Device Address Register (DEVICEADDR) bit positions.
- * @{
- */
-#define XUSBPS_DEVICEADDR_DEVICEAADV_MASK 0x01000000
- /**< Device Addr Auto Advance */
-#define XUSBPS_DEVICEADDR_ADDR_MASK 0xFE000000
- /**< Device Address */
-#define XUSBPS_DEVICEADDR_ADDR_SHIFT 25
- /**< Address shift */
-#define XUSBPS_DEVICEADDR_MAX 127
- /**< Biggest allowed address */
-/* @} */
-
-/** @name USB TT Control Register (TTCTRL) bit positions.
- * @{
- */
-#define XUSBPS_TTCTRL_HUBADDR_MASK 0x7F000000 /**< TT Hub Address */
-/* @} */
-
-
-/** @name USB Burst Size Register (BURSTSIZE) bit posisions.
- * @{
- */
-#define XUSBPS_BURSTSIZE_RX_MASK 0x000000FF /**< RX Burst Length */
-#define XUSBPS_BURSTSIZE_TX_MASK 0x0000FF00 /**< TX Burst Length */
-/* @} */
-
-
-/** @name USB Tx Fill Tuning Register (TXFILL) bit positions.
- * @{
- */
-#define XUSBPS_TXFILL_OVERHEAD_MASK 0x000000FF
- /**< Scheduler Overhead */
-#define XUSBPS_TXFILL_HEALTH_MASK 0x00001F00
- /**< Scheduler Health Cntr */
-#define XUSBPS_TXFILL_BURST_MASK 0x003F0000
- /**< FIFO Burst Threshold */
-/* @} */
-
-
-/** @name USB ULPI Viewport Register (ULPIVIEW) bit positions.
- * @{
- */
-#define XUSBPS_ULPIVIEW_DATWR_MASK 0x000000FF /**< ULPI Data Write */
-#define XUSBPS_ULPIVIEW_DATRD_MASK 0x0000FF00 /**< ULPI Data Read */
-#define XUSBPS_ULPIVIEW_ADDR_MASK 0x00FF0000 /**< ULPI Data Address */
-#define XUSBPS_ULPIVIEW_PORT_MASK 0x07000000 /**< ULPI Port Number */
-#define XUSBPS_ULPIVIEW_SS_MASK 0x08000000 /**< ULPI Synchronous State */
-#define XUSBPS_ULPIVIEW_RW_MASK 0x20000000 /**< ULPI Read/Write Control */
-#define XUSBPS_ULPIVIEW_RUN_MASK 0x40000000 /**< ULPI Run */
-#define XUSBPS_ULPIVIEW_WU_MASK 0x80000000 /**< ULPI Wakeup */
-/* @} */
-
-
-/** @name Port Status Control Register bit positions.
- * @{
- */
-#define XUSBPS_PORTSCR_CCS_MASK 0x00000001 /**< Current Connect Status */
-#define XUSBPS_PORTSCR_CSC_MASK 0x00000002 /**< Connect Status Change */
-#define XUSBPS_PORTSCR_PE_MASK 0x00000004 /**< Port Enable/Disable */
-#define XUSBPS_PORTSCR_PEC_MASK 0x00000008 /**< Port Enable/Disable Change */
-#define XUSBPS_PORTSCR_OCA_MASK 0x00000010 /**< Over-current Active */
-#define XUSBPS_PORTSCR_OCC_MASK 0x00000020 /**< Over-current Change */
-#define XUSBPS_PORTSCR_FPR_MASK 0x00000040 /**< Force Port Resume */
-#define XUSBPS_PORTSCR_SUSP_MASK 0x00000080 /**< Suspend */
-#define XUSBPS_PORTSCR_PR_MASK 0x00000100 /**< Port Reset */
-#define XUSBPS_PORTSCR_HSP_MASK 0x00000200 /**< High Speed Port */
-#define XUSBPS_PORTSCR_LS_MASK 0x00000C00 /**< Line Status */
-#define XUSBPS_PORTSCR_PP_MASK 0x00001000 /**< Port Power */
-#define XUSBPS_PORTSCR_PO_MASK 0x00002000 /**< Port Owner */
-#define XUSBPS_PORTSCR_PIC_MASK 0x0000C000 /**< Port Indicator Control */
-#define XUSBPS_PORTSCR_PTC_MASK 0x000F0000 /**< Port Test Control */
-#define XUSBPS_PORTSCR_WKCN_MASK 0x00100000 /**< Wake on Connect Enable */
-#define XUSBPS_PORTSCR_WKDS_MASK 0x00200000 /**< Wake on Disconnect Enable */
-#define XUSBPS_PORTSCR_WKOC_MASK 0x00400000 /**< Wake on Over-current Enable */
-#define XUSBPS_PORTSCR_PHCD_MASK 0x00800000 /**< PHY Low Power Suspend -
- * Clock Disable */
-#define XUSBPS_PORTSCR_PFSC_MASK 0x01000000 /**< Port Force Full Speed
- * Connect */
-#define XUSBPS_PORTSCR_PSPD_MASK 0x0C000000 /**< Port Speed */
-/* @} */
-
-
-/** @name On-The-Go Status Control Register (OTGCSR) bit positions.
- * @{
- */
-#define XUSBPS_OTGSC_VD_MASK 0x00000001 /**< VBus Discharge Bit */
-#define XUSBPS_OTGSC_VC_MASK 0x00000002 /**< VBus Charge Bit */
-#define XUSBPS_OTGSC_HAAR_MASK 0x00000004 /**< HW Assist Auto Reset
- * Enable Bit */
-#define XUSBPS_OTGSC_OT_MASK 0x00000008 /**< OTG Termination Bit */
-#define XUSBPS_OTGSC_DP_MASK 0x00000010 /**< Data Pulsing Pull-up
- * Enable Bit */
-#define XUSBPS_OTGSC_IDPU_MASK 0x00000020 /**< ID Pull-up Enable Bit */
-#define XUSBPS_OTGSC_HADP_MASK 0x00000040 /**< HW Assist Data Pulse
- * Enable Bit */
-#define XUSBPS_OTGSC_HABA_MASK 0x00000080 /**< USB Hardware Assist
- * B Disconnect to A
- * Connect Enable Bit */
-#define XUSBPS_OTGSC_ID_MASK 0x00000100 /**< ID Status Flag */
-#define XUSBPS_OTGSC_AVV_MASK 0x00000200 /**< USB A VBus Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_ASV_MASK 0x00000400 /**< USB A Session Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_BSV_MASK 0x00000800 /**< USB B Session Valid Status Flag */
-#define XUSBPS_OTGSC_BSE_MASK 0x00001000 /**< USB B Session End Status Flag */
-#define XUSBPS_OTGSC_1MST_MASK 0x00002000 /**< USB 1 Millisecond Timer Status Flag */
-#define XUSBPS_OTGSC_DPS_MASK 0x00004000 /**< Data Pulse Status Flag */
-#define XUSBPS_OTGSC_IDIS_MASK 0x00010000 /**< USB ID Interrupt Status Flag */
-#define XUSBPS_OTGSC_AVVIS_MASK 0x00020000 /**< USB A VBus Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_ASVIS_MASK 0x00040000 /**< USB A Session Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_BSVIS_MASK 0x00080000 /**< USB B Session Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_BSEIS_MASK 0x00100000 /**< USB B Session End Interrupt Status Flag */
-#define XUSBPS_OTGSC_1MSS_MASK 0x00200000 /**< 1 Millisecond Timer Interrupt Status Flag */
-#define XUSBPS_OTGSC_DPIS_MASK 0x00400000 /**< Data Pulse Interrupt Status Flag */
-#define XUSBPS_OTGSC_IDIE_MASK 0x01000000 /**< ID Interrupt Enable Bit */
-#define XUSBPS_OTGSC_AVVIE_MASK 0x02000000 /**< USB A VBus Valid Interrupt Enable Bit */
-#define XUSBPS_OTGSC_ASVIE_MASK 0x04000000 /**< USB A Session Valid Interrupt Enable Bit */
-#define XUSBPS_OTGSC_BSVIE_MASK 0x08000000 /**< USB B Session Valid Interrupt Enable Bit */
-#define XUSBPS_OTGSC_BSEE_MASK 0x10000000 /**< USB B Session End Interrupt Enable Bit */
-#define XUSBPS_OTGSC_1MSE_MASK 0x20000000 /**< 1 Millisecond Timer
- * Interrupt Enable Bit */
-#define XUSBPS_OTGSC_DPIE_MASK 0x40000000 /**< Data Pulse Interrupt
- * Enable Bit */
-
-#define XUSBPS_OTG_ISB_ALL (XUSBPS_OTGSC_IDIS_MASK |\
- XUSBPS_OTGSC_AVVIS_MASK | \
- XUSBPS_OTGSC_ASVIS_MASK | \
- XUSBPS_OTGSC_BSVIS_MASK | \
- XUSBPS_OTGSC_BSEIS_MASK | \
- XUSBPS_OTGSC_1MSS_MASK | \
- XUSBPS_OTGSC_DPIS_MASK)
- /** Mask for All IRQ status masks */
-
-#define XUSBPS_OTG_IEB_ALL (XUSBPS_OTGSC_IDIE_MASK |\
- XUSBPS_OTGSC_AVVIE_MASK | \
- XUSBPS_OTGSC_ASVIE_MASK | \
- XUSBPS_OTGSC_BSVIE_MASK | \
- XUSBPS_OTGSC_BSEE_IEB_MASK | \
- XUSBPS_OTGSC_1MSE_MASK | \
- XUSBPS_OTGSC_DPIE_MASK)
- /** Mask for All IRQ Enable masks */
-/* @} */
-
-
-/**< Alignment of the Device Queue Head List BASE. */
-#define XUSBPS_dQH_BASE_ALIGN 2048
-
-/**< Alignment of a Device Queue Head structure. */
-#define XUSBPS_dQH_ALIGN 64
-
-/**< Alignment of a Device Transfer Descriptor structure. */
-#define XUSBPS_dTD_ALIGN 32
-
-/**< Size of one RX buffer for a OUT Transfer Descriptor. */
-#define XUSBPS_dTD_BUF_SIZE 4096
-
-/**< Maximum size of one RX/TX buffer. */
-#define XUSBPS_dTD_BUF_MAX_SIZE 16*1024
-
-/**< Alignment requirement for Transfer Descriptor buffers. */
-#define XUSBPS_dTD_BUF_ALIGN 4096
-
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* This macro reads the given register.
-*
-* @param BaseAddress is the base address for the USB registers.
-* @param RegOffset is the register offset to be read.
-*
-* @return The 32-bit value of the register.
-*
-* @note C-style signature:
-* u32 XUsbPs_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XUsbPs_ReadReg(BaseAddress, RegOffset) \
- Xil_In32(BaseAddress + (RegOffset))
-
-
-/****************************************************************************/
-/**
-*
-* This macro writes the given register.
-*
-* @param BaseAddress is the the base address for the USB registers.
-* @param RegOffset is the register offset to be written.
-* @param Data is the the 32-bit value to write to the register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XUsbPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
- *****************************************************************************/
-#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data) \
- Xil_Out32(BaseAddress + (RegOffset), (Data))
-
-
-/************************** Function Prototypes ******************************/
-/*
- * Perform reset operation to the USB PS interface
- */
-void XUsbPs_ResetHw(u32 BaseAddress);
-/************************** Variable Definitions ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XUSBPS_L_H */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/f0c8d3575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/f0c8d3575243001d18b399c1eb9b3628
deleted file mode 100644
index df92a53..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/f0c8d3575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,487 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xemacps.c
-* @addtogroup emacps_v3_15
-* @{
-*
-* The XEmacPs driver. Functions in this file are the minimum required functions
-* for this driver. See xemacps.h for a detailed description of the driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 First release
-* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and
-* 64-bit changes.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.0 hk 02/20/15 Added support for jumbo frames. Increase AHB burst.
-* Disable extended mode. Perform all 64 bit changes under
-* check for arch64.
-* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr registers
-* 3.5 hk 08/14/17 Update cache coherency information of the interface in
-* its config structure.
-* 3.8 hk 09/17/18 Cleanup stale comments.
-* 3.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
-* 3.10 hk 05/16/19 Clear status registers properly in reset
-* 3.11 sd 02/14/20 Add clock support
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xemacps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-void XEmacPs_StubHandler(void); /* Default handler routine */
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-* Initialize a specific XEmacPs instance/driver. The initialization entails:
-* - Initialize fields of the XEmacPs instance structure
-* - Reset hardware and apply default options
-* - Configure the DMA channels
-*
-* The PHY is setup independently from the device. Use the MII or whatever other
-* interface may be present for setup.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param CfgPtr is the device configuration structure containing required
-* hardware build data.
-* @param EffectiveAddress is the base address of the device. If address
-* translation is not utilized, this parameter can be passed in using
-* CfgPtr->Config.BaseAddress to specify the physical base address.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-*
-******************************************************************************/
-LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
- UINTPTR EffectiveAddress)
-{
- /* Verify arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(CfgPtr != NULL);
-
- /* Set device base address and ID */
- InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
- InstancePtr->Config.BaseAddress = EffectiveAddress;
- InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent;
-#if defined (XCLOCKING)
- InstancePtr->Config.RefClk = CfgPtr->RefClk;
-#endif
-
- InstancePtr->Config.S1GDiv0 = CfgPtr->S1GDiv0;
- InstancePtr->Config.S1GDiv1 = CfgPtr->S1GDiv1;
- InstancePtr->Config.S100MDiv0 = CfgPtr->S100MDiv0;
- InstancePtr->Config.S100MDiv1 = CfgPtr->S100MDiv1;
- InstancePtr->Config.S10MDiv0 = CfgPtr->S10MDiv0;
- InstancePtr->Config.S10MDiv1 = CfgPtr->S10MDiv1;
-
- /* Set callbacks to an initial stub routine */
- InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler));
- InstancePtr->RecvHandler = ((XEmacPs_Handler)(void*)XEmacPs_StubHandler);
- InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void*)XEmacPs_StubHandler);
-
- /* Reset the hardware and set default options */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
- XEmacPs_Reset(InstancePtr);
-
- return (LONG)(XST_SUCCESS);
-}
-
-
-/*****************************************************************************/
-/**
-* Start the Ethernet controller as follows:
-* - Enable transmitter if XTE_TRANSMIT_ENABLE_OPTION is set
-* - Enable receiver if XTE_RECEIVER_ENABLE_OPTION is set
-* - Start the SG DMA send and receive channels and enable the device
-* interrupt
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return N/A
-*
-* @note
-* Hardware is configured with scatter-gather DMA, the driver expects to start
-* the scatter-gather channels and expects that the user has previously set up
-* the buffer descriptor lists.
-*
-* This function makes use of internal resources that are shared between the
-* Start, Stop, and Set/ClearOptions functions. So if one task might be setting
-* device options while another is trying to start the device, the user is
-* required to provide protection of this shared data (typically using a
-* semaphore).
-*
-* This function must not be preempted by an interrupt that may service the
-* device.
-*
-******************************************************************************/
-void XEmacPs_Start(XEmacPs *InstancePtr)
-{
- u32 Reg;
-
- /* Assert bad arguments and conditions */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
-#if defined (XCLOCKING)
- if (InstancePtr->IsStarted != (u32)XIL_COMPONENT_IS_STARTED) {
- Xil_ClockEnable(InstancePtr->Config.RefClk);
- }
-#endif
-
- /* Start DMA */
- /* When starting the DMA channels, both transmit and receive sides
- * need an initialized BD list.
- */
- if (InstancePtr->Version == 2) {
- Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0);
- Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_RXQBASE_OFFSET,
- InstancePtr->RxBdRing.BaseBdAddr);
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_TXQBASE_OFFSET,
- InstancePtr->TxBdRing.BaseBdAddr);
- }
-
- /* clear any existed int status */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
- XEMACPS_IXR_ALL_MASK);
-
- /* Enable transmitter if not already enabled */
- if ((InstancePtr->Options & (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION)!=0x00000000U) {
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET);
- if ((!(Reg & XEMACPS_NWCTRL_TXEN_MASK))==TRUE) {
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET,
- Reg | (u32)XEMACPS_NWCTRL_TXEN_MASK);
- }
- }
-
- /* Enable receiver if not already enabled */
- if ((InstancePtr->Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET);
- if ((!(Reg & XEMACPS_NWCTRL_RXEN_MASK))==TRUE) {
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET,
- Reg | (u32)XEMACPS_NWCTRL_RXEN_MASK);
- }
- }
-
- /* Enable TX and RX interrupts */
- XEmacPs_IntEnable(InstancePtr, (XEMACPS_IXR_TX_ERR_MASK |
- XEMACPS_IXR_RX_ERR_MASK | (u32)XEMACPS_IXR_FRAMERX_MASK |
- (u32)XEMACPS_IXR_TXCOMPL_MASK));
-
- /* Enable TX Q1 Interrupts */
- if (InstancePtr->Version > 2)
- XEmacPs_IntQ1Enable(InstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK);
-
- /* Mark as started */
- InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
-
- return;
-}
-
-
-/*****************************************************************************/
-/**
-* Gracefully stop the Ethernet MAC as follows:
-* - Disable all interrupts from this device
-* - Stop DMA channels
-* - Disable the tansmitter and receiver
-*
-* Device options currently in effect are not changed.
-*
-* This function will disable all interrupts. Default interrupts settings that
-* had been enabled will be restored when XEmacPs_Start() is called.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @note
-* This function makes use of internal resources that are shared between the
-* Start, Stop, SetOptions, and ClearOptions functions. So if one task might be
-* setting device options while another is trying to start the device, the user
-* is required to provide protection of this shared data (typically using a
-* semaphore).
-*
-* Stopping the DMA channels causes this function to block until the DMA
-* operation is complete.
-*
-******************************************************************************/
-void XEmacPs_Stop(XEmacPs *InstancePtr)
-{
- u32 Reg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- /* Disable all interrupts */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
- XEMACPS_IXR_ALL_MASK);
-
- /* Disable the receiver & transmitter */
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET);
- Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
- Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET, Reg);
-
- /* Mark as stopped */
- InstancePtr->IsStarted = 0U;
-#if defined (XCLOCKING)
- Xil_ClockDisable(InstancePtr->Config.RefClk);
-#endif
-}
-
-
-/*****************************************************************************/
-/**
-* Perform a graceful reset of the Ethernet MAC. Resets the DMA channels, the
-* transmitter, and the receiver.
-*
-* Steps to reset
-* - Stops transmit and receive channels
-* - Stops DMA
-* - Configure transmit and receive buffer size to default
-* - Clear transmit and receive status register and counters
-* - Clear all interrupt sources
-* - Clear phy (if there is any previously detected) address
-* - Clear MAC addresses (1-4) as well as Type IDs and hash value
-*
-* All options are placed in their default state. Any frames in the
-* descriptor lists will remain in the lists. The side effect of doing
-* this is that after a reset and following a restart of the device, frames
-* were in the list before the reset may be transmitted or received.
-*
-* The upper layer software is responsible for re-configuring (if necessary)
-* and restarting the MAC after the reset. Note also that driver statistics
-* are not cleared on reset. It is up to the upper layer software to clear the
-* statistics if needed.
-*
-* When a reset is required, the driver notifies the upper layer software of
-* this need through the ErrorHandler callback and specific status codes.
-* The upper layer software is responsible for calling this Reset function
-* and then re-configuring the device.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-******************************************************************************/
-void XEmacPs_Reset(XEmacPs *InstancePtr)
-{
- u32 Reg;
- u8 i;
- s8 EmacPs_zero_MAC[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- /* Stop the device and reset hardware */
- XEmacPs_Stop(InstancePtr);
- InstancePtr->Options = XEMACPS_DEFAULT_OPTIONS;
-
- InstancePtr->Version = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, 0xFC);
-
- InstancePtr->Version = (InstancePtr->Version >> 16) & 0xFFF;
-
- InstancePtr->MaxMtuSize = XEMACPS_MTU;
- InstancePtr->MaxFrameSize = XEMACPS_MTU + XEMACPS_HDR_SIZE +
- XEMACPS_TRL_SIZE;
- InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
- XEMACPS_HDR_VLAN_SIZE;
- InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
-
- /* Setup hardware with default values */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET,
- (XEMACPS_NWCTRL_STATCLR_MASK |
- XEMACPS_NWCTRL_MDEN_MASK) &
- (u32)(~XEMACPS_NWCTRL_LOOPEN_MASK));
-
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCFG_OFFSET);
- Reg &= XEMACPS_NWCFG_MDCCLKDIV_MASK;
-
- Reg = Reg | (u32)XEMACPS_NWCFG_100_MASK |
- (u32)XEMACPS_NWCFG_FDEN_MASK |
- (u32)XEMACPS_NWCFG_UCASTHASHEN_MASK;
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCFG_OFFSET, Reg);
- if (InstancePtr->Version > 2) {
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET,
- (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET) |
- XEMACPS_NWCFG_DWIDTH_64_MASK));
- }
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_DMACR_OFFSET,
- (((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
- (((((u32)XEMACPS_RX_BUF_SIZE %
- (u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
- (u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
- (u32)(XEMACPS_DMACR_RXBUF_MASK)) |
- (u32)XEMACPS_DMACR_RXSIZE_MASK |
- (u32)XEMACPS_DMACR_TXSIZE_MASK);
-
-
- if (InstancePtr->Version > 2) {
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
- (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) |
-#if defined(__aarch64__) || defined(__arch64__)
- (u32)XEMACPS_DMACR_ADDR_WIDTH_64 |
-#endif
- (u32)XEMACPS_DMACR_INCR16_AHB_BURST));
- }
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_TXSR_OFFSET, XEMACPS_SR_ALL_MASK);
-
- XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_SEND);
- if (InstancePtr->Version > 2)
- XEmacPs_SetQueuePtr(InstancePtr, 0, 0x01U, (u16)XEMACPS_SEND);
- XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_RECV);
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_RXSR_OFFSET, XEMACPS_SR_ALL_MASK);
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET,
- XEMACPS_IXR_ALL_MASK);
-
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_ISR_OFFSET);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
- Reg);
-
- XEmacPs_ClearHash(InstancePtr);
-
- for (i = 1U; i < 5U; i++) {
- (void)XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i);
- (void)XEmacPs_SetTypeIdCheck(InstancePtr, 0x00000000U, i);
- }
-
- /* clear all counters */
- for (i = 0U; i < (u8)((XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4U);
- i++) {
- (void)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_OCTTXL_OFFSET + (u32)(((u32)i) * ((u32)4)));
- }
-
- /* Disable the receiver */
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET);
- Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET, Reg);
-
- /* Sync default options with hardware but leave receiver and
- * transmitter disabled. They get enabled with XEmacPs_Start() if
- * XEMACPS_TRANSMITTER_ENABLE_OPTION and
- * XEMACPS_RECEIVER_ENABLE_OPTION are set.
- */
- (void)XEmacPs_SetOptions(InstancePtr, InstancePtr->Options &
- ~((u32)XEMACPS_TRANSMITTER_ENABLE_OPTION |
- (u32)XEMACPS_RECEIVER_ENABLE_OPTION));
-
- (void)XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options);
-}
-
-
-/******************************************************************************/
-/**
- * This is a stub for the asynchronous callbacks. The stub is here in case the
- * upper layer forgot to set the handler(s). On initialization, all handlers are
- * set to this callback. It is considered an error for this handler to be
- * invoked.
- *
- ******************************************************************************/
-void XEmacPs_StubHandler(void)
-{
- Xil_AssertVoidAlways();
-}
-
-/*****************************************************************************/
-/**
-* This function sets the start address of the transmit/receive buffer queue.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param QPtr is the address of the Queue to be written
-* @param QueueNum is the Buffer Queue Index
-* @param Direction indicates Transmit/Receive
-*
-* @note
-* The buffer queue addresses has to be set before starting the transfer, so
-* this function has to be called in prior to XEmacPs_Start()
-*
-******************************************************************************/
-void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
- u16 Direction)
-{
- /* Assert bad arguments and conditions */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- /* If already started, then there is nothing to do */
- if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
- return;
- }
-
- if (QueueNum == 0x00U) {
- if (Direction == XEMACPS_SEND) {
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_TXQBASE_OFFSET,
- (QPtr & ULONG64_LO_MASK));
- } else {
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_RXQBASE_OFFSET,
- (QPtr & ULONG64_LO_MASK));
- }
- }
- else {
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_TXQ1BASE_OFFSET,
- (QPtr & ULONG64_LO_MASK));
- }
-#ifdef __aarch64__
- if (Direction == XEMACPS_SEND) {
- /* Set the MSB of TX Queue start address */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_MSBBUF_TXQBASE_OFFSET,
- (u32)((QPtr & ULONG64_HI_MASK) >> 32U));
- } else {
- /* Set the MSB of RX Queue start address */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_MSBBUF_RXQBASE_OFFSET,
- (u32)((QPtr & ULONG64_HI_MASK) >> 32U));
- }
-#endif
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/f0d798565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/f0d798565243001d18b399c1eb9b3628
deleted file mode 100644
index 2495824..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7/f0d798565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,60 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2006 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-*
-* microblaze_init_icache_range (unsigned int cache_start, unsigned int cache_len)
-*
-* Invalidate icache on the microblaze
-*
-* Parameters:
-* 'cache_start' - address in the Icache where invalidation begins
-* 'cache_len' - length (in bytes) worth of Icache to be invalidated
-*
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-
-#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020
-#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
-
-#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
-#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
-#endif
-
- .text
- .globl microblaze_init_icache_range
- .ent microblaze_init_icache_range
- .align 2
-
-microblaze_init_icache_range:
-#if (XPAR_MICROBLAZE_USE_ICACHE==1) && (XPAR_MICROBLAZE_ALLOW_ICACHE_WR==1)
- mfs r9, rmsr /* Disable Icache and interrupts before invalidating */
- andi r10, r9, (~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE))
- mts rmsr, r10
-
- andi r5, r5, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align to cache line */
-
- add r6, r5, r6 /* Compute end */
- andi r6, r6, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align to cache line */
-
-L_start:
- wic r5, r0 /* Invalidate the Cache (delay slot) */
-
- cmpu r18, r5, r6 /* Are we at the end ? */
- blei r18, L_done
-
- brid L_start /* Branch to the beginning of the loop */
- addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the address by 4 (delay slot) */
-
-L_done:
- rtsd r15, 8 /* Return */
- mts rmsr, r9
-#else
- rtsd r15, 8 /* Return */
- nop
-#endif
- .end microblaze_init_icache_range
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/70/300308595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/70/300308595243001d18b399c1eb9b3628
deleted file mode 100644
index 9425ff3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/70/300308595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,48 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file cpu_init.S
-*
-* This file contains CPU specific initialization. Invoked from main CRT
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 5.00 pkp 02/10/14 Initial version
-*
-*
-*
-******************************************************************************/
-
- .text
- .global __cpu_init
- .align 2
-__cpu_init:
-
-/* Clear cp15 regs with unknown reset values */
- mov r0, #0x0
- mcr p15, 0, r0, c5, c0, 0 /* DFSR */
- mcr p15, 0, r0, c5, c0, 1 /* IFSR */
- mcr p15, 0, r0, c6, c0, 0 /* DFAR */
- mcr p15, 0, r0, c6, c0, 2 /* IFAR */
- mcr p15, 0, r0, c9, c13, 2 /* PMXEVCNTR */
- mcr p15, 0, r0, c13, c0, 2 /* TPIDRURW */
- mcr p15, 0, r0, c13, c0, 3 /* TPIDRURO */
-
-
-/* Reset and start Cycle Counter */
- mov r2, #0x80000000 /* clear overflow */
- mcr p15, 0, r2, c9, c12, 3
- mov r2, #0xd /* D, C, E */
- mcr p15, 0, r2, c9, c12, 0
- mov r2, #0x80000000 /* enable cycle counter */
- mcr p15, 0, r2, c9, c12, 1
-
- bx lr
-
-.end
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/70/321764575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/70/321764575243001d18b399c1eb9b3628
deleted file mode 100644
index 51cc7c5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/70/321764575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,477 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xadcps_hw.h
-* @addtogroup xadcps_v2_6
-* @{
-*
-* This header file contains identifiers and basic driver functions (or
-* macros) that can be used to access the XADC device through the Device
-* Config Interface of the Zynq.
-*
-*
-* Refer to the device specification for more information about this driver.
-*
-* @note None.
-*
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a bss 12/22/11 First release based on the XPS/AXI xadc driver
-* 1.03a bss 11/01/13 Modified macros to use correct Register offsets
-* CR#749687
-* 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors.
-*
-*
-*
-*****************************************************************************/
-#ifndef XADCPS_HW_H /* Prevent circular inclusions */
-#define XADCPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**@name Register offsets of XADC in the Device Config
- *
- * The following constants provide access to each of the registers of the
- * XADC device.
- * @{
- */
-
-#define XADCPS_CFG_OFFSET 0x00U /**< Configuration Register */
-#define XADCPS_INT_STS_OFFSET 0x04U /**< Interrupt Status Register */
-#define XADCPS_INT_MASK_OFFSET 0x08U /**< Interrupt Mask Register */
-#define XADCPS_MSTS_OFFSET 0x0CU /**< Misc status register */
-#define XADCPS_CMDFIFO_OFFSET 0x10U /**< Command FIFO Register */
-#define XADCPS_RDFIFO_OFFSET 0x14U /**< Read FIFO Register */
-#define XADCPS_MCTL_OFFSET 0x18U /**< Misc control register */
-
-/* @} */
-
-
-
-
-
-/** @name XADC Config Register Bit definitions
- * @{
- */
-#define XADCPS_CFG_ENABLE_MASK 0x80000000U /**< Enable access from PS mask */
-#define XADCPS_CFG_CFIFOTH_MASK 0x00F00000U /**< Command FIFO Threshold mask */
-#define XADCPS_CFG_DFIFOTH_MASK 0x000F0000U /**< Data FIFO Threshold mask */
-#define XADCPS_CFG_WEDGE_MASK 0x00002000U /**< Write Edge Mask */
-#define XADCPS_CFG_REDGE_MASK 0x00001000U /**< Read Edge Mask */
-#define XADCPS_CFG_TCKRATE_MASK 0x00000300U /**< Clock freq control */
-#define XADCPS_CFG_IGAP_MASK 0x0000001FU /**< Idle Gap between
- * successive commands */
-/* @} */
-
-
-/** @name XADC Interrupt Status/Mask Register Bit definitions
- *
- * The definitions are same for the Interrupt Status Register and
- * Interrupt Mask Register. They are defined only once.
- * @{
- */
-#define XADCPS_INTX_ALL_MASK 0x000003FFU /**< Alarm Signals Mask */
-#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200U /**< CMD FIFO less than threshold */
-#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100U /**< Data FIFO greater than threshold */
-#define XADCPS_INTX_OT_MASK 0x00000080U /**< Over temperature Alarm Status */
-#define XADCPS_INTX_ALM_ALL_MASK 0x0000007FU /**< Alarm Signals Mask */
-#define XADCPS_INTX_ALM6_MASK 0x00000040U /**< Alarm 6 Mask */
-#define XADCPS_INTX_ALM5_MASK 0x00000020U /**< Alarm 5 Mask */
-#define XADCPS_INTX_ALM4_MASK 0x00000010U /**< Alarm 4 Mask */
-#define XADCPS_INTX_ALM3_MASK 0x00000008U /**< Alarm 3 Mask */
-#define XADCPS_INTX_ALM2_MASK 0x00000004U /**< Alarm 2 Mask */
-#define XADCPS_INTX_ALM1_MASK 0x00000002U /**< Alarm 1 Mask */
-#define XADCPS_INTX_ALM0_MASK 0x00000001U /**< Alarm 0 Mask */
-
-/* @} */
-
-
-/** @name XADC Miscellaneous Register Bit definitions
- * @{
- */
-#define XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000U /**< Command FIFO Level mask */
-#define XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000U /**< Data FIFO Level Mask */
-#define XADCPS_MSTS_CFIFOF_MASK 0x00000800U /**< Command FIFO Full Mask */
-#define XADCPS_MSTS_CFIFOE_MASK 0x00000400U /**< Command FIFO Empty Mask */
-#define XADCPS_MSTS_DFIFOF_MASK 0x00000200U /**< Data FIFO Full Mask */
-#define XADCPS_MSTS_DFIFOE_MASK 0x00000100U /**< Data FIFO Empty Mask */
-#define XADCPS_MSTS_OT_MASK 0x00000080U /**< Over Temperature Mask */
-#define XADCPS_MSTS_ALM_MASK 0x0000007FU /**< Alarms Mask */
-/* @} */
-
-
-/** @name XADC Miscellaneous Control Register Bit definitions
- * @{
- */
-#define XADCPS_MCTL_RESET_MASK 0x00000010U /**< Reset XADC */
-#define XADCPS_MCTL_FLUSH_MASK 0x00000001U /**< Flush the FIFOs */
-/* @} */
-
-
-/**@name Internal Register offsets of the XADC
- *
- * The following constants provide access to each of the internal registers of
- * the XADC device.
- * @{
- */
-
-/*
- * XADC Internal Channel Registers
- */
-#define XADCPS_TEMP_OFFSET 0x00U /**< On-chip Temperature Reg */
-#define XADCPS_VCCINT_OFFSET 0x01U /**< On-chip VCCINT Data Reg */
-#define XADCPS_VCCAUX_OFFSET 0x02U /**< On-chip VCCAUX Data Reg */
-#define XADCPS_VPVN_OFFSET 0x03U /**< ADC out of VP/VN */
-#define XADCPS_VREFP_OFFSET 0x04U /**< On-chip VREFP Data Reg */
-#define XADCPS_VREFN_OFFSET 0x05U /**< On-chip VREFN Data Reg */
-#define XADCPS_VBRAM_OFFSET 0x06U /**< On-chip VBRAM , 7 Series */
-#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08U /**< ADC A Supply Offset Reg */
-#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09U /**< ADC A Offset Data Reg */
-#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0AU /**< ADC A Gain Error Reg */
-#define XADCPS_VCCPINT_OFFSET 0x0DU /**< On-chip VCCPINT Reg, Zynq */
-#define XADCPS_VCCPAUX_OFFSET 0x0EU /**< On-chip VCCPAUX Reg, Zynq */
-#define XADCPS_VCCPDRO_OFFSET 0x0FU /**< On-chip VCCPDRO Reg, Zynq */
-
-/*
- * XADC External Channel Registers
- */
-#define XADCPS_AUX00_OFFSET 0x10U /**< ADC out of VAUXP0/VAUXN0 */
-#define XADCPS_AUX01_OFFSET 0x11U /**< ADC out of VAUXP1/VAUXN1 */
-#define XADCPS_AUX02_OFFSET 0x12U /**< ADC out of VAUXP2/VAUXN2 */
-#define XADCPS_AUX03_OFFSET 0x13U /**< ADC out of VAUXP3/VAUXN3 */
-#define XADCPS_AUX04_OFFSET 0x14U /**< ADC out of VAUXP4/VAUXN4 */
-#define XADCPS_AUX05_OFFSET 0x15U /**< ADC out of VAUXP5/VAUXN5 */
-#define XADCPS_AUX06_OFFSET 0x16U /**< ADC out of VAUXP6/VAUXN6 */
-#define XADCPS_AUX07_OFFSET 0x17U /**< ADC out of VAUXP7/VAUXN7 */
-#define XADCPS_AUX08_OFFSET 0x18U /**< ADC out of VAUXP8/VAUXN8 */
-#define XADCPS_AUX09_OFFSET 0x19U /**< ADC out of VAUXP9/VAUXN9 */
-#define XADCPS_AUX10_OFFSET 0x1AU /**< ADC out of VAUXP10/VAUXN10 */
-#define XADCPS_AUX11_OFFSET 0x1BU /**< ADC out of VAUXP11/VAUXN11 */
-#define XADCPS_AUX12_OFFSET 0x1CU /**< ADC out of VAUXP12/VAUXN12 */
-#define XADCPS_AUX13_OFFSET 0x1DU /**< ADC out of VAUXP13/VAUXN13 */
-#define XADCPS_AUX14_OFFSET 0x1EU /**< ADC out of VAUXP14/VAUXN14 */
-#define XADCPS_AUX15_OFFSET 0x1FU /**< ADC out of VAUXP15/VAUXN15 */
-
-/*
- * XADC Registers for Maximum/Minimum data captured for the
- * on chip Temperature/VCCINT/VCCAUX data.
- */
-#define XADCPS_MAX_TEMP_OFFSET 0x20U /**< Max Temperature Reg */
-#define XADCPS_MAX_VCCINT_OFFSET 0x21U /**< Max VCCINT Register */
-#define XADCPS_MAX_VCCAUX_OFFSET 0x22U /**< Max VCCAUX Register */
-#define XADCPS_MAX_VCCBRAM_OFFSET 0x23U /**< Max BRAM Register, 7 series */
-#define XADCPS_MIN_TEMP_OFFSET 0x24U /**< Min Temperature Reg */
-#define XADCPS_MIN_VCCINT_OFFSET 0x25U /**< Min VCCINT Register */
-#define XADCPS_MIN_VCCAUX_OFFSET 0x26U /**< Min VCCAUX Register */
-#define XADCPS_MIN_VCCBRAM_OFFSET 0x27U /**< Min BRAM Register, 7 series */
-#define XADCPS_MAX_VCCPINT_OFFSET 0x28U /**< Max VCCPINT Register, Zynq */
-#define XADCPS_MAX_VCCPAUX_OFFSET 0x29U /**< Max VCCPAUX Register, Zynq */
-#define XADCPS_MAX_VCCPDRO_OFFSET 0x2AU /**< Max VCCPDRO Register, Zynq */
-#define XADCPS_MIN_VCCPINT_OFFSET 0x2CU /**< Min VCCPINT Register, Zynq */
-#define XADCPS_MIN_VCCPAUX_OFFSET 0x2DU /**< Min VCCPAUX Register, Zynq */
-#define XADCPS_MIN_VCCPDRO_OFFSET 0x2EU /**< Min VCCPDRO Register,Zynq */
- /* Undefined 0x2F to 0x3E */
-#define XADCPS_FLAG_OFFSET 0x3FU /**< Flag Register */
-
-/*
- * XADC Configuration Registers
- */
-#define XADCPS_CFR0_OFFSET 0x40U /**< Configuration Register 0 */
-#define XADCPS_CFR1_OFFSET 0x41U /**< Configuration Register 1 */
-#define XADCPS_CFR2_OFFSET 0x42U /**< Configuration Register 2 */
-
-/* Test Registers 0x43 to 0x47 */
-
-/*
- * XADC Sequence Registers
- */
-#define XADCPS_SEQ00_OFFSET 0x48U /**< Seq Reg 00 Adc Channel Selection */
-#define XADCPS_SEQ01_OFFSET 0x49U /**< Seq Reg 01 Adc Channel Selection */
-#define XADCPS_SEQ02_OFFSET 0x4AU /**< Seq Reg 02 Adc Average Enable */
-#define XADCPS_SEQ03_OFFSET 0x4BU /**< Seq Reg 03 Adc Average Enable */
-#define XADCPS_SEQ04_OFFSET 0x4CU /**< Seq Reg 04 Adc Input Mode Select */
-#define XADCPS_SEQ05_OFFSET 0x4DU /**< Seq Reg 05 Adc Input Mode Select */
-#define XADCPS_SEQ06_OFFSET 0x4EU /**< Seq Reg 06 Adc Acquisition Select */
-#define XADCPS_SEQ07_OFFSET 0x4FU /**< Seq Reg 07 Adc Acquisition Select */
-
-/*
- * XADC Alarm Threshold/Limit Registers (ATR)
- */
-#define XADCPS_ATR_TEMP_UPPER_OFFSET 0x50U /**< Temp Upper Alarm Register */
-#define XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51U /**< VCCINT Upper Alarm Reg */
-#define XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52U /**< VCCAUX Upper Alarm Reg */
-#define XADCPS_ATR_OT_UPPER_OFFSET 0x53U /**< Over Temp Upper Alarm Reg */
-#define XADCPS_ATR_TEMP_LOWER_OFFSET 0x54U /**< Temp Lower Alarm Register */
-#define XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55U /**< VCCINT Lower Alarm Reg */
-#define XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56U /**< VCCAUX Lower Alarm Reg */
-#define XADCPS_ATR_OT_LOWER_OFFSET 0x57U /**< Over Temp Lower Alarm Reg */
-#define XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58U /**< VBRAM Upper Alarm, 7 series */
-#define XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59U /**< VCCPINT Upper Alarm, Zynq */
-#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5AU /**< VCCPAUX Upper Alarm, Zynq */
-#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5BU /**< VCCPDRO Upper Alarm, Zynq */
-#define XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5CU /**< VRBAM Lower Alarm, 7 Series */
-#define XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5DU /**< VCCPINT Lower Alarm, Zynq */
-#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5EU /**< VCCPAUX Lower Alarm, Zynq */
-#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5FU /**< VCCPDRO Lower Alarm, Zynq */
-
-/* Undefined 0x60 to 0x7F */
-
-/*@}*/
-
-
-
-/**
- * @name Configuration Register 0 (CFR0) mask(s)
- * @{
- */
-#define XADCPS_CFR0_CAL_AVG_MASK 0x00008000U /**< Averaging enable Mask */
-#define XADCPS_CFR0_AVG_VALID_MASK 0x00003000U /**< Averaging bit Mask */
-#define XADCPS_CFR0_AVG1_MASK 0x00000000U /**< No Averaging */
-#define XADCPS_CFR0_AVG16_MASK 0x00001000U /**< Average 16 samples */
-#define XADCPS_CFR0_AVG64_MASK 0x00002000U /**< Average 64 samples */
-#define XADCPS_CFR0_AVG256_MASK 0x00003000U /**< Average 256 samples */
-#define XADCPS_CFR0_AVG_SHIFT 12U /**< Averaging bits shift */
-#define XADCPS_CFR0_MUX_MASK 0x00000800U /**< External Mask Enable */
-#define XADCPS_CFR0_DU_MASK 0x00000400U /**< Bipolar/Unipolar mode */
-#define XADCPS_CFR0_EC_MASK 0x00000200U /**< Event driven/
- * Continuous mode selection
- */
-#define XADCPS_CFR0_ACQ_MASK 0x00000100U /**< Add acquisition by 6 ADCCLK */
-#define XADCPS_CFR0_CHANNEL_MASK 0x0000001FU /**< Channel number bit Mask */
-
-/*@}*/
-
-/**
- * @name Configuration Register 1 (CFR1) mask(s)
- * @{
- */
-#define XADCPS_CFR1_SEQ_VALID_MASK 0x0000F000U /**< Sequence bit Mask */
-#define XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x00000000U /**< Default Safe Mode */
-#define XADCPS_CFR1_SEQ_ONEPASS_MASK 0x00001000U /**< Onepass through Seq */
-#define XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x00002000U /**< Continuous Cycling Seq */
-#define XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x00003000U /**< Single channel - No Seq */
-#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x00004000U /**< Simulataneous Sampling Mask */
-#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x00008000U /**< Independent Mode */
-#define XADCPS_CFR1_SEQ_SHIFT 12U /**< Sequence bit shift */
-#define XADCPS_CFR1_ALM_VCCPDRO_MASK 0x00000800U /**< Alm 6 - VCCPDRO, Zynq */
-#define XADCPS_CFR1_ALM_VCCPAUX_MASK 0x00000400U /**< Alm 5 - VCCPAUX, Zynq */
-#define XADCPS_CFR1_ALM_VCCPINT_MASK 0x00000200U /**< Alm 4 - VCCPINT, Zynq */
-#define XADCPS_CFR1_ALM_VBRAM_MASK 0x00000100U /**< Alm 3 - VBRAM, 7 series */
-#define XADCPS_CFR1_CAL_VALID_MASK 0x000000F0U /**< Valid Calibration Mask */
-#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x00000080U /**< Calibration 3 -Power
- Supply Gain/Offset
- Enable */
-#define XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x00000040U /**< Calibration 2 -Power
- Supply Offset Enable */
-#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x00000020U /**< Calibration 1 -ADC Gain
- Offset Enable */
-#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x00000010U /**< Calibration 0 -ADC Offset
- Enable */
-#define XADCPS_CFR1_CAL_DISABLE_MASK 0x00000000U /**< No Calibration */
-#define XADCPS_CFR1_ALM_ALL_MASK 0x00000F0FU /**< Mask for all alarms */
-#define XADCPS_CFR1_ALM_VCCAUX_MASK 0x00000008U /**< Alarm 2 - VCCAUX Enable */
-#define XADCPS_CFR1_ALM_VCCINT_MASK 0x00000004U /**< Alarm 1 - VCCINT Enable */
-#define XADCPS_CFR1_ALM_TEMP_MASK 0x00000002U /**< Alarm 0 - Temperature */
-#define XADCPS_CFR1_OT_MASK 0x00000001U /**< Over Temperature Enable */
-
-/*@}*/
-
-/**
- * @name Configuration Register 2 (CFR2) mask(s)
- * @{
- */
-#define XADCPS_CFR2_CD_VALID_MASK 0xFF00U /**
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 7.2 sd 02/06/20 First release of clocking
-* 7.2 sd 03/20/20 Added checking for isolation case
-*
-*
-******************************************************************************/
-
-#include "xil_clocking.h"
-/************************** Variable Definitions *****************************/
-
-#if defined (XPAR_XCRPSU_0_DEVICE_ID) && defined (XCLOCKING)
-
-XClock ClockInstance; /* Instance of clock Controller */
-XClockPs_Config *ConfigPtr;
-
-
-XStatus Xil_ClockInit(void)
-{
- XStatus Status = XST_FAILURE;
-
- /* Lookup clock configurations */
- ConfigPtr = XClock_LookupConfig(XPAR_XCLOCKPS_DEVICE_ID);
-
- /* Initialize the Clock controller driver */
- Status = XClock_CfgInitialize(&ClockInstance, ConfigPtr);
- return Status;
-}
-
-XStatus Xil_ClockEnable(XClock_OutputClks ClockId)
-{
-
- XStatus Status = XST_FAILURE;
-
- Status = XClock_EnableClock(ClockId);
- return Status;
-}
-
-XStatus Xil_ClockDisable(XClock_OutputClks ClockId)
-{
- XStatus Status = XST_FAILURE;
-
- Status = XClock_DisableClock(ClockId);
- return Status;
-}
-
-XStatus Xil_ClockGetRate(XClock_OutputClks ClockId, XClockRate *Rate)
-{
- XStatus Status = XST_FAILURE;
-
- Xil_AssertNonvoid(Rate != NULL);
-
- Status = XClock_GetRate(ClockId, Rate);
- if (XST_SUCCESS == Status) {
- xdbg_printf(XDBG_DEBUG_GENERAL, "Operating rate = %lx\n",*Rate);
- } else {
- xdbg_printf(XDBG_DEBUG_ERROR, "Failed: Fetching rate\r\n");
- }
- return Status;
-}
-
-XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate,
- XClockRate *SetRate)
-{
- XStatus Status = XST_FAILURE;
-
- Xil_AssertNonvoid(SetRate != NULL);
-
- if (Rate == 0) {
- return XST_FAILURE;
- }
- Status = XClock_SetRate(ClockId, Rate, SetRate);
- if (XST_SUCCESS != Status) {
- xdbg_printf(XDBG_DEBUG_ERROR, "Failed Setting rate\n");
- }
- return Status;
-}
-
-#else
-XStatus Xil_ClockGetRate(XClock_OutputClks ClockId, XClockRate *Rate)
-{
- (void) ClockId;
- (void) Rate;
- return XST_FAILURE;
-}
-
-XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate,
- XClockRate *SetRate) {
- (void) ClockId;
- (void) Rate;
- (void) SetRate;
- return XST_FAILURE;
-}
-
-XStatus Xil_ClockInit(void)
-{
- return XST_SUCCESS;
-}
-
-XStatus Xil_ClockEnable(XClock_OutputClks ClockId)
-{
- (void) ClockId;
- return XST_SUCCESS;
-}
-
-XStatus Xil_ClockDisable(XClock_OutputClks ClockId)
-{
- (void) ClockId;
- return XST_SUCCESS;
-}
-
-#endif /* XCLOCKING */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/70/e0e3c2585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/70/e0e3c2585243001d18b399c1eb9b3628
deleted file mode 100644
index fffd926..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/70/e0e3c2585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,159 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm_iccarm.h
-*
-* This header file contains macros for using inline assembler code. It is
-* written specifically for the IAR C/C++ compiler.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm 10/28/09 First release
-* 3.12a asa 11/02/13 Removed the macro mfcpsr to make it a function.
-* 5.3 pkp 10/09/15 Modified dsb, dmb and isb definitions
-* 5.4 pkp 03/02/16 Included header file intrinsic.h for assembly
-* instructions definitions
-* 6.2 kvn 03/03/17 Added support thumb mode
-* 7.2 asa 04/03/20 Renamed the str macro to strw.
-*
-* The boot code performs minimum configuration which is required for an
-* application to run starting from processor reset state of the processor. Below is a
-* sequence illustrating what all configuration is performed before control
-* reaches to main function.
-*
-* 1. Program vector table base for exception handling
-* 2. Invalidate instruction cache, data cache and TLBs
-* 3. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine,
-* abort, system)
-* 4. Configure MMU with short descriptor translation table format and program
-* base address of translation table
-* 5. Enable data cache, instruction cache and MMU
-* 6. Enable Floating point unit
-* 7. Transfer control to _start which clears BSS sections, initializes
-* global timer and runs global constructor before jumping to main
-* application
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 1.00a ecm/sdm 10/20/09 Initial version
-* 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
-* register settings.
-* 3.06a asa 06/17/12 Modified the TTBR settings and L2 Cache auxiliary
-* register settings.
-* 3.07a asa 07/16/12 Modified the L2 Cache controller settings to improve
-* performance. Changed the property of the ".boot"
-* section.
-* 3.07a sgd 08/21/12 Modified the L2 Cache controller and cp15 Aux Control
-* Register settings
-* 3.09a sgd 02/06/13 Updated SLCR l2c Ram Control register to a
-* value of 0x00020202. Fix for CR 697094 (SI#687034).
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-* 4.2 pkp 06/19/14 Enabled asynchronous abort exception
-* 5.0 pkp 16/15/14 Modified initialization code to enable scu after
-* MMU is enabled
-* 5.1 pkp 05/13/15 Changed the initialization order so to first invalidate
-* caches and TLB, enable MMU and caches, then enable SMP
-* bit in ACTLR. L2Cache invalidation and enabling of L2Cache
-* is done later.
-* 5.4 asa 12/6/15 Added code to initialize SPSR for all relevant modes.
-* 6.0 mus 08/04/16 Added code to detect zynq-7000 base silicon configuration and
-* attempt to enable dual core behavior on single cpu zynq-7000s
-* devices is prevented from corrupting system behavior.
-* 6.0 mus 08/24/16 Check CPU core before putting cpu1 to reset for single core
-* zynq-7000s devices
-* 7.6 mus 09/02/21 SCU invalidation should be done only from primary CPU, so
-* skipping it when USE_AMP is set to 1. It fixes CR#1109723
-*
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#include "xparameters.h"
-#include "xil_errata.h"
-
-.globl MMUTable
-.global _prestart
-.global _boot
-.global __stack
-.global __irq_stack
-.global __supervisor_stack
-.global __abort_stack
-.global __fiq_stack
-.global __undef_stack
-.global _vector_table
-
-.set PSS_L2CC_BASE_ADDR, 0xF8F02000
-.set PSS_SLCR_BASE_ADDR, 0xF8000000
-
-.set RESERVED, 0x0fffff00
-.set TblBase , MMUTable
-.set LRemap, 0xFE00000F /* set the base address of the peripheral block as not shared */
-.set L2CCWay, (PSS_L2CC_BASE_ADDR + 0x077C) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)*/
-.set L2CCSync, (PSS_L2CC_BASE_ADDR + 0x0730) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)*/
-.set L2CCCrtl, (PSS_L2CC_BASE_ADDR + 0x0100) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)*/
-.set L2CCAuxCrtl, (PSS_L2CC_BASE_ADDR + 0x0104) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)*/
-.set L2CCTAGLatReg, (PSS_L2CC_BASE_ADDR + 0x0108) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)*/
-.set L2CCDataLatReg, (PSS_L2CC_BASE_ADDR + 0x010C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)*/
-.set L2CCIntClear, (PSS_L2CC_BASE_ADDR + 0x0220) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)*/
-.set L2CCIntRaw, (PSS_L2CC_BASE_ADDR + 0x021C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)*/
-
-.set SLCRlockReg, (PSS_SLCR_BASE_ADDR + 0x04) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/
-.set SLCRUnlockReg, (PSS_SLCR_BASE_ADDR + 0x08) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/
-.set SLCRL2cRamReg, (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/
-.set SLCRCPURSTReg, (0xF8000000 + 0x244) /*(XPS_SYS_CTRL_BASEADDR + A9_CPU_RST_CTRL_OFFSET)*/
-.set EFUSEStaus, (0xF800D000 + 0x10) /*(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)*/
-
-/* workaround for simulation not working when L1 D and I caches,MMU and L2 cache enabled - DT568997 */
-.if SIM_MODE == 1
-.set CRValMmuCac, 0b00000000000000 /* Disable IDC, and MMU */
-.else
-.set CRValMmuCac, 0b01000000000101 /* Enable IDC, and MMU */
-.endif
-
-.set CRValHiVectorAddr, 0b10000000000000 /* Set the Vector address to high, 0xFFFF0000 */
-
-.set L2CCAuxControl, 0x72360000 /* Enable all prefetching, Cache replacement policy, Parity enable,
- Event monitor bus enable and Way Size (64 KB) */
-.set L2CCControl, 0x01 /* Enable L2CC */
-.set L2CCTAGLatency, 0x0111 /* latency for TAG RAM */
-.set L2CCDataLatency, 0x0121 /* latency for DATA RAM */
-
-.set SLCRlockKey, 0x767B /* SLCR lock key */
-.set SLCRUnlockKey, 0xDF0D /* SLCR unlock key */
-.set SLCRL2cRamConfig, 0x00020202 /* SLCR L2C ram configuration */
-
-/* Stack Pointer locations for boot code */
-.set Undef_stack, __undef_stack
-.set FIQ_stack, __fiq_stack
-.set Abort_stack, __abort_stack
-.set SPV_stack, __supervisor_stack
-.set IRQ_stack, __irq_stack
-.set SYS_stack, __stack
-
-.set vector_base, _vector_table
-
-.set FPEXC_EN, 0x40000000 /* FPU enable bit, (1 << 30) */
-
-.section .boot,"ax"
-
-
-/* this initializes the various processor modes */
-
-_prestart:
-_boot:
-
-#if XPAR_CPU_ID==0
- /* only allow cpu0 through */
- mrc p15,0,r1,c0,c0,5
- and r1, r1, #0xf
- cmp r1, #0
- beq CheckEFUSE
- EndlessLoop0:
- wfe
- b EndlessLoop0
-
-CheckEFUSE:
- ldr r0,=EFUSEStaus
- ldr r1,[r0] /* Read eFuse setting */
- ands r1,r1,#0x80 /* Check whether device is having single core */
- beq OKToRun
-
- /* single core device, reset cpu1 */
- ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
- ldr r1,=SLCRUnlockKey /* set unlock key */
- str r1, [r0] /* Unlock SLCR */
-
- ldr r0,=SLCRCPURSTReg
- ldr r1,[r0] /* Read CPU Software Reset Control register */
- orr r1,r1,#0x22
- str r1,[r0] /* Reset CPU1 */
-
- ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
- ldr r1,=SLCRlockKey /* set lock key */
- str r1, [r0] /* lock SLCR */
-
-#elif XPAR_CPU_ID==1
- /* only allow cpu1 through */
- mrc p15,0,r1,c0,c0,5
- and r1, r1, #0xf
- cmp r1, #1
- beq CheckEFUSE1
- b EndlessLoop1
-
-CheckEFUSE1:
- ldr r0,=EFUSEStaus
- ldr r1,[r0] /* Read eFuse setting */
- ands r1,r1,#0x80 /* Check whether device is having single core */
- beq OKToRun
- EndlessLoop1:
- wfe
- b EndlessLoop1
-#endif
-
-OKToRun:
- mrc p15, 0, r0, c0, c0, 0 /* Get the revision */
- and r5, r0, #0x00f00000
- and r6, r0, #0x0000000f
- orr r6, r6, r5, lsr #20-4
-
-#ifdef CONFIG_ARM_ERRATA_742230
- cmp r6, #0x22 /* only present up to r2p2 */
- mrcle p15, 0, r10, c15, c0, 1 /* read diagnostic register */
- orrle r10, r10, #1 << 4 /* set bit #4 */
- mcrle p15, 0, r10, c15, c0, 1 /* write diagnostic register */
-#endif
-
-#ifdef CONFIG_ARM_ERRATA_743622
- teq r5, #0x00200000 /* only present in r2p* */
- mrceq p15, 0, r10, c15, c0, 1 /* read diagnostic register */
- orreq r10, r10, #1 << 6 /* set bit #6 */
- mcreq p15, 0, r10, c15, c0, 1 /* write diagnostic register */
-#endif
-
- /* set VBAR to the _vector_table address in linker script */
- ldr r0, =vector_base
- mcr p15, 0, r0, c12, c0, 0
-
- /*invalidate scu*/
-#if USE_AMP!=1
- ldr r7, =0xf8f0000c
- ldr r6, =0xffff
- str r6, [r7]
-#endif
-
- /* Invalidate caches and TLBs */
- mov r0,#0 /* r0 = 0 */
- mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
- mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
- mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */
- bl invalidate_dcache /* invalidate dcache */
-
- /* Disable MMU, if enabled */
- mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */
- bic r0, r0, #0x1 /* clear bit 0 */
- mcr p15, 0, r0, c1, c0, 0 /* write value back */
-
-#ifdef SHAREABLE_DDR
- /* Mark the entire DDR memory as shareable */
- ldr r3, =0x3ff /* 1024 entries to cover 1G DDR */
- ldr r0, =TblBase /* MMU Table address in memory */
- ldr r2, =0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
-shareable_loop:
- str r2, [r0] /* write the entry to MMU table */
- add r0, r0, #0x4 /* next entry in the table */
- add r2, r2, #0x100000 /* next section */
- subs r3, r3, #1
- bge shareable_loop /* loop till 1G is covered */
-#endif
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the irq stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x12 /* IRQ mode */
- msr cpsr, r2
- ldr r13,=IRQ_stack /* IRQ stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the supervisor stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x13 /* supervisor mode */
- msr cpsr, r2
- ldr r13,=SPV_stack /* Supervisor stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the Abort stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x17 /* Abort mode */
- msr cpsr, r2
- ldr r13,=Abort_stack /* Abort stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the FIQ stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x11 /* FIQ mode */
- msr cpsr, r2
- ldr r13,=FIQ_stack /* FIQ stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the Undefine stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x1b /* Undefine mode */
- msr cpsr, r2
- ldr r13,=Undef_stack /* Undefine stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the system stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x1F /* SYS mode */
- msr cpsr, r2
- ldr r13,=SYS_stack /* SYS stack pointer */
-
- /*set scu enable bit in scu*/
- ldr r7, =0xf8f00000
- ldr r0, [r7]
- orr r0, r0, #0x1
- str r0, [r7]
-
- /* enable MMU and cache */
-
- ldr r0,=TblBase /* Load MMU translation table base */
- orr r0, r0, #0x5B /* Outer-cacheable, WB */
- mcr 15, 0, r0, c2, c0, 0 /* TTB0 */
-
- mvn r0,#0 /* Load MMU domains -- all ones=manager */
- mcr p15,0,r0,c3,c0,0
-
- /* Enable mmu, icahce and dcache */
- ldr r0,=CRValMmuCac
- mcr p15,0,r0,c1,c0,0 /* Enable cache and MMU */
- dsb /* dsb allow the MMU to start up */
- isb /* isb flush prefetch buffer */
-
- /* Write to ACTLR */
- mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/
- orr r0, r0, #(0x01 << 6) /* set SMP bit */
- orr r0, r0, #(0x01 ) /* Cache/TLB maintenance broadcast */
- mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/
-
-/* Invalidate L2 Cache and enable L2 Cache*/
-/* For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) */
-#if USE_AMP!=1
- ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */
- mov r1, #0 /* force the disable bit */
- str r1, [r0] /* disable the L2 Caches */
-
- ldr r0,=L2CCAuxCrtl /* Load L2CC base address base + Aux control register */
- ldr r1,[r0] /* read the register */
- ldr r2,=L2CCAuxControl /* set the default bits */
- orr r1,r1,r2
- str r1, [r0] /* store the Aux Control Register */
-
- ldr r0,=L2CCTAGLatReg /* Load L2CC base address base + TAG Latency address */
- ldr r1,=L2CCTAGLatency /* set the latencies for the TAG*/
- str r1, [r0] /* store the TAG Latency register Register */
-
- ldr r0,=L2CCDataLatReg /* Load L2CC base address base + Data Latency address */
- ldr r1,=L2CCDataLatency /* set the latencies for the Data*/
- str r1, [r0] /* store the Data Latency register Register */
-
- ldr r0,=L2CCWay /* Load L2CC base address base + way register*/
- ldr r2, =0xFFFF
- str r2, [r0] /* force invalidate */
-
- ldr r0,=L2CCSync /* need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET */
- /* Load L2CC base address base + sync register*/
- /* poll for completion */
-Sync: ldr r1, [r0]
- cmp r1, #0
- bne Sync
-
- ldr r0,=L2CCIntRaw /* clear pending interrupts */
- ldr r1,[r0]
- ldr r0,=L2CCIntClear
- str r1,[r0]
-
- ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
- ldr r1,=SLCRUnlockKey /* set unlock key */
- str r1, [r0] /* Unlock SLCR */
-
- ldr r0,=SLCRL2cRamReg /* Load SLCR base address base + l2c Ram Control register */
- ldr r1,=SLCRL2cRamConfig /* set the configuration value */
- str r1, [r0] /* store the L2c Ram Control Register */
-
- ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
- ldr r1,=SLCRlockKey /* set lock key */
- str r1, [r0] /* lock SLCR */
-
- ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */
- ldr r1,[r0] /* read the register */
- mov r2, #L2CCControl /* set the enable bit */
- orr r1,r1,r2
- str r1, [r0] /* enable the L2 Caches */
-#endif
-
- mov r0, r0
- mrc p15, 0, r1, c1, c0, 2 /* read cp access control register (CACR) into r1 */
- orr r1, r1, #(0xf << 20) /* enable full access for p10 & p11 */
- mcr p15, 0, r1, c1, c0, 2 /* write back into CACR */
-
- /* enable vfp */
- fmrx r1, FPEXC /* read the exception register */
- orr r1,r1, #FPEXC_EN /* set VFP enable bit, leave the others in orig state */
- fmxr FPEXC, r1 /* write back the exception register */
-
- mrc p15,0,r0,c1,c0,0 /* flow prediction enable */
- orr r0, r0, #(0x01 << 11) /* #0x8000 */
- mcr p15,0,r0,c1,c0,0
-
- mrc p15,0,r0,c1,c0,1 /* read Auxiliary Control Register */
- orr r0, r0, #(0x1 << 2) /* enable Dside prefetch */
- orr r0, r0, #(0x1 << 1) /* enable L2 Prefetch hint */
- mcr p15,0,r0,c1,c0,1 /* write Auxiliary Control Register */
-
- mrs r0, cpsr /* get the current PSR */
- bic r0, r0, #0x100 /* enable asynchronous abort exception */
- msr cpsr_xsf, r0
-
-
- b _start /* jump to C startup code */
- and r0, r0, r0 /* no op */
-
-.Ldone: b .Ldone /* Paranoia: we should never get here */
-
-
-/*
- *************************************************************************
- *
- * invalidate_dcache - invalidate the entire d-cache by set/way
- *
- * Note: for Cortex-A9, there is no cp instruction for invalidating
- * the whole D-cache. Need to invalidate each line.
- *
- *************************************************************************
- */
-invalidate_dcache:
- mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */
- ands r3, r0, #0x7000000
- mov r3, r3, lsr #23 /* cache level value (naturally aligned) */
- beq finished
- mov r10, #0 /* start with level 0 */
-loop1:
- add r2, r10, r10, lsr #1 /* work out 3xcachelevel */
- mov r1, r0, lsr r2 /* bottom 3 bits are the Cache type for this level */
- and r1, r1, #7 /* get those 3 bits alone */
- cmp r1, #2
- blt skip /* no cache or only instruction cache at this level */
- mcr p15, 2, r10, c0, c0, 0 /* write the Cache Size selection register */
- isb /* isb to sync the change to the CacheSizeID reg */
- mrc p15, 1, r1, c0, c0, 0 /* reads current Cache Size ID register */
- and r2, r1, #7 /* extract the line length field */
- add r2, r2, #4 /* add 4 for the line length offset (log2 16 bytes) */
- ldr r4, =0x3ff
- ands r4, r4, r1, lsr #3 /* r4 is the max number on the way size (right aligned) */
- clz r5, r4 /* r5 is the bit position of the way size increment */
- ldr r7, =0x7fff
- ands r7, r7, r1, lsr #13 /* r7 is the max number of the index size (right aligned) */
-loop2:
- mov r9, r4 /* r9 working copy of the max way size (right aligned) */
-loop3:
- orr r11, r10, r9, lsl r5 /* factor in the way number and cache number into r11 */
- orr r11, r11, r7, lsl r2 /* factor in the index number */
- mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */
- subs r9, r9, #1 /* decrement the way number */
- bge loop3
- subs r7, r7, #1 /* decrement the index */
- bge loop2
-skip:
- add r10, r10, #2 /* increment the cache number */
- cmp r3, r10
- bgt loop1
-
-finished:
- mov r10, #0 /* switch back to cache level 0 */
- mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
- dsb
- isb
-
- bx lr
-
-.end
-/**
-* @} End of "addtogroup a9_boot_code".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/71/5096e8515243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/71/5096e8515243001d18b399c1eb9b3628
deleted file mode 100644
index ac01e66..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/71/5096e8515243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,2 +0,0 @@
-/Debug/
-/Release/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/71/7224d8595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/71/7224d8595243001d18b399c1eb9b3628
deleted file mode 100644
index 4f985dc..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/71/7224d8595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,505 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
- *
- * @file xusbps_hw.h
-* @addtogroup usbps_v2_7
-* @{
- *
- * This header file contains identifiers and low-level driver functions (or
- * macros) that can be used to access the device. High-level driver functions
- * are defined in xusbps.h.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.00a wgr 10/10/10 First release
- * 1.04a nm 10/23/12 Fixed CR# 679106.
- * 1.05a kpc 07/03/13 Added XUsbPs_ResetHw function prototype
- * 2.00a kpc 04/03/14 Fixed CR#777764. Corrected max endpoint vale and masks
- * 2.5 pm 02/20/20 Added Endpoint Control Register bit positions for Rx & Tx
- *
- *
- ******************************************************************************/
-#ifndef XUSBPS_HW_H
-#define XUSBPS_HW_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-
-#define XUSBPS_REG_SPACING 4
-
-/** @name Timer 0 Register offsets
- *
- * @{
- */
-#define XUSBPS_TIMER0_LD_OFFSET 0x00000080
-#define XUSBPS_TIMER0_CTL_OFFSET 0x00000084
-/* @} */
-
-/** @name Timer Control Register bit mask
- *
- * @{
- */
-#define XUSBPS_TIMER_RUN_MASK 0x80000000
-#define XUSBPS_TIMER_STOP_MASK 0x80000000
-#define XUSBPS_TIMER_RESET_MASK 0x40000000
-#define XUSBPS_TIMER_REPEAT_MASK 0x01000000
-/* @} */
-
-/** @name Timer Control Register bit mask
- *
- * @{
- */
-#define XUSBPS_TIMER_COUNTER_MASK 0x00FFFFFF
-/* @} */
-
-/** @name Device Hardware Parameters
- *
- * @{
- */
-#define XUSBPS_HWDEVICE_OFFSET 0x0000000C
-
-#define XUSBPS_EP_NUM_MASK 0x3E
-#define XUSBPS_EP_NUM_SHIFT 1
-/* @} */
-
-/** @name Capability Register offsets
- */
-#define XUSBPS_HCSPARAMS_OFFSET 0x00000104
-
-/** @name Operational Register offsets.
- * Register comments are tagged with "H:" and "D:" for Host and Device modes,
- * respectively.
- * Tags are only present for registers that have a different meaning DEVICE and
- * HOST modes. Most registers are only valid for either DEVICE or HOST mode.
- * Those registers don't have tags.
- * @{
- */
-#define XUSBPS_CMD_OFFSET 0x00000140 /**< Configuration */
-#define XUSBPS_ISR_OFFSET 0x00000144 /**< Interrupt Status */
-#define XUSBPS_IER_OFFSET 0x00000148 /**< Interrupt Enable */
-#define XUSBPS_FRAME_OFFSET 0x0000014C /**< USB Frame Index */
-#define XUSBPS_LISTBASE_OFFSET 0x00000154 /**< H: Periodic List Base Address */
-#define XUSBPS_DEVICEADDR_OFFSET 0x00000154 /**< D: Device Address */
-#define XUSBPS_ASYNCLISTADDR_OFFSET 0x00000158 /**< H: Async List Address */
-#define XUSBPS_EPLISTADDR_OFFSET 0x00000158 /**< D: Endpoint List Addr */
-#define XUSBPS_TTCTRL_OFFSET 0x0000015C /**< TT Control */
-#define XUSBPS_BURSTSIZE_OFFSET 0x00000160 /**< Burst Size */
-#define XUSBPS_TXFILL_OFFSET 0x00000164 /**< Tx Fill Tuning */
-#define XUSBPS_ULPIVIEW_OFFSET 0x00000170 /**< ULPI Viewport */
-#define XUSBPS_EPNAKISR_OFFSET 0x00000178 /**< Endpoint NAK IRQ Status */
-#define XUSBPS_EPNAKIER_OFFSET 0x0000017C /**< Endpoint NAK IRQ Enable */
-#define XUSBPS_PORTSCR1_OFFSET 0x00000184 /**< Port Control/Status 1 */
-
-/* NOTE: The Port Control / Status Register index is 1-based. */
-#define XUSBPS_PORTSCRn_OFFSET(n) \
- (XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING))
-
-
-#define XUSBPS_OTGCSR_OFFSET 0x000001A4 /**< OTG Status and Control */
-#define XUSBPS_MODE_OFFSET 0x000001A8 /**< USB Mode */
-#define XUSBPS_EPSTAT_OFFSET 0x000001AC /**< Endpoint Setup Status */
-#define XUSBPS_EPPRIME_OFFSET 0x000001B0 /**< Endpoint Prime */
-#define XUSBPS_EPFLUSH_OFFSET 0x000001B4 /**< Endpoint Flush */
-#define XUSBPS_EPRDY_OFFSET 0x000001B8 /**< Endpoint Ready */
-#define XUSBPS_EPCOMPL_OFFSET 0x000001BC /**< Endpoint Complete */
-#define XUSBPS_EPCR0_OFFSET 0x000001C0 /**< Endpoint Control 0 */
-#define XUSBPS_EPCR1_OFFSET 0x000001C4 /**< Endpoint Control 1 */
-#define XUSBPS_EPCR2_OFFSET 0x000001C8 /**< Endpoint Control 2 */
-#define XUSBPS_EPCR3_OFFSET 0x000001CC /**< Endpoint Control 3 */
-#define XUSBPS_EPCR4_OFFSET 0x000001D0 /**< Endpoint Control 4 */
-
-#define XUSBPS_MAX_ENDPOINTS 12 /**< Number of supported Endpoints in
- * this core. */
-#define XUSBPS_EP_OUT_MASK 0x00000FFF /**< OUR (RX) endpoint mask */
-#define XUSBPS_EP_IN_MASK 0x0FFF0000 /**< IN (TX) endpoint mask */
-#define XUSBPS_EP_ALL_MASK 0x0FFF0FFF /**< Mask used for endpoint control
- * registers */
-#define XUSBPS_EPCRn_OFFSET(n) \
- (XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING))
-
-#define XUSBPS_EPFLUSH_RX_SHIFT 0
-#define XUSBPS_EPFLUSH_TX_SHIFT 16
-
-/* @} */
-
-
-
-/** @name Endpoint Control Register (EPCR) bit positions.
- * @{
- */
-
-/* Definitions for TX Endpoint bits */
-#define XUSBPS_EPCR_TXT_TYPE_SHIFT 18 /* < Endpoint Type - TX bit shift*/
-#define XUSBPS_EPCR_TXT_TYPE_MASK 0x000C0000 /* < Endpoint Type - TX read only*/
-#define XUSBPS_EPCR_TXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - TX */
-#define XUSBPS_EPCR_TXT_ISO_MASK 0x00040000 /**< Isochronous. Endpoint */
-#define XUSBPS_EPCR_TXT_BULK_MASK 0x00080000 /**< Bulk Endpoint - TX */
-#define XUSBPS_EPCR_TXT_INTR_MASK 0x000C0000 /**< Interrupt Endpoint */
-#define XUSBPS_EPCR_TXS_MASK 0x00010000 /**< Stall TX endpoint */
-#define XUSBPS_EPCR_TXE_MASK 0x00800000 /**< Transmit enable - TX */
-#define XUSBPS_EPCR_TXR_MASK 0x00400000 /**< Data Toggle Reset Bit */
-
-
-/* Definitions for RX Endpoint bits */
-#define XUSBPS_EPCR_RXT_TYPE_SHIFT 2 /* < Endpoint Type - RX bit shift*/
-#define XUSBPS_EPCR_RXT_TYPE_MASK 0x0000000C /**< Endpoint Type - RX read only*/
-#define XUSBPS_EPCR_RXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - RX */
-#define XUSBPS_EPCR_RXT_ISO_MASK 0x00000004 /**< Isochronous Endpoint */
-#define XUSBPS_EPCR_RXT_BULK_MASK 0x00000008 /**< Bulk Endpoint - RX */
-#define XUSBPS_EPCR_RXT_INTR_MASK 0x0000000C /**< Interrupt Endpoint */
-#define XUSBPS_EPCR_RXS_MASK 0x00000001 /**< Stall RX endpoint. */
-#define XUSBPS_EPCR_RXE_MASK 0x00000080 /**< Transmit enable. - RX */
-#define XUSBPS_EPCR_RXR_MASK 0x00000040 /**< Data Toggle Reset Bit */
-/* @} */
-
-
-/** @name USB Command Register (CR) bit positions.
- * @{
- */
-#define XUSBPS_CMD_RS_MASK 0x00000001 /**< Run/Stop */
-#define XUSBPS_CMD_RST_MASK 0x00000002 /**< Controller RESET */
-#define XUSBPS_CMD_FS01_MASK 0x0000000C /**< Frame List Size bit 0,1 */
-#define XUSBPS_CMD_PSE_MASK 0x00000010 /**< Periodic Sched Enable */
-#define XUSBPS_CMD_ASE_MASK 0x00000020 /**< Async Sched Enable */
-#define XUSBPS_CMD_IAA_MASK 0x00000040 /**< IRQ Async Advance Doorbell */
-#define XUSBPS_CMD_ASP_MASK 0x00000300 /**< Async Sched Park Mode Cnt */
-#define XUSBPS_CMD_ASPE_MASK 0x00000800 /**< Async Sched Park Mode Enbl */
-#define XUSBPS_CMD_SUTW_MASK 0x00002000 /**< Setup TripWire */
-#define XUSBPS_CMD_ATDTW_MASK 0x00004000 /**< Add dTD TripWire */
-#define XUSBPS_CMD_FS2_MASK 0x00008000 /**< Frame List Size bit 2 */
-#define XUSBPS_CMD_ITC_MASK 0x00FF0000 /**< IRQ Threshold Control */
-/* @} */
-
-
-/**
- * @name Interrupt Threshold
- * These definitions are used by software to set the maximum rate at which the
- * USB controller will generate interrupt requests. The interrupt interval is
- * given in number of micro-frames.
- *
- * USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF)
- * packet each and every 1ms. USB also defines a high-speed micro-frame with a
- * 125us frame time. For each micro-frame a SOF (Start Of Frame) packet is
- * generated. Data is sent in between the SOF packets. The interrupt threshold
- * defines how many micro-frames the controller waits before issuing an
- * interrupt after data has been received.
- *
- * For a threshold of 0 the controller will issue an interrupt immediately
- * after the last byte of the data has been received. For a threshold n>0 the
- * controller will wait for n micro-frames before issuing an interrupt.
- *
- * Therefore, a setting of 8 micro-frames (default) means that the controller
- * will issue at most 1 interrupt per millisecond.
- *
- * @{
- */
-#define XUSBPS_CMD_ITHRESHOLD_0 0x00 /**< Immediate interrupt. */
-#define XUSBPS_CMD_ITHRESHOLD_1 0x01 /**< 1 micro-frame */
-#define XUSBPS_CMD_ITHRESHOLD_2 0x02 /**< 2 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_4 0x04 /**< 4 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_8 0x08 /**< 8 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_16 0x10 /**< 16 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_32 0x20 /**< 32 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_64 0x40 /**< 64 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_MAX XUSBPS_CMD_ITHRESHOLD_64
-#define XUSBPS_CMD_ITHRESHOLD_DEFAULT XUSBPS_CMD_ITHRESHOLD_8
-/* @} */
-
-
-
-/** @name USB Interrupt Status Register (ISR) / Interrupt Enable Register (IER)
- * bit positions.
- * @{
- */
-#define XUSBPS_IXR_UI_MASK 0x00000001 /**< USB Transaction Complete */
-#define XUSBPS_IXR_UE_MASK 0x00000002 /**< Transaction Error */
-#define XUSBPS_IXR_PC_MASK 0x00000004 /**< Port Change Detect */
-#define XUSBPS_IXR_FRE_MASK 0x00000008 /**< Frame List Rollover */
-#define XUSBPS_IXR_AA_MASK 0x00000020 /**< Async Advance */
-#define XUSBPS_IXR_UR_MASK 0x00000040 /**< RESET Received */
-#define XUSBPS_IXR_SR_MASK 0x00000080 /**< Start of Frame */
-#define XUSBPS_IXR_SLE_MASK 0x00000100 /**< Device Controller Suspend */
-#define XUSBPS_IXR_ULPI_MASK 0x00000400 /**< ULPI IRQ */
-#define XUSBPS_IXR_HCH_MASK 0x00001000 /**< Host Controller Halted
- * Read Only */
-#define XUSBPS_IXR_RCL_MASK 0x00002000 /**< USB Reclamation Read Only */
-#define XUSBPS_IXR_PS_MASK 0x00004000 /**< Periodic Sched Status
- * Read Only */
-#define XUSBPS_IXR_AS_MASK 0x00008000 /**< Async Sched Status Read only */
-#define XUSBPS_IXR_NAK_MASK 0x00010000 /**< NAK IRQ */
-#define XUSBPS_IXR_UA_MASK 0x00040000 /**< USB Host Async IRQ */
-#define XUSBPS_IXR_UP_MASK 0x00080000 /**< USB Host Periodic IRQ */
-#define XUSBPS_IXR_TI0_MASK 0x01000000 /**< Timer 0 Interrupt */
-#define XUSBPS_IXR_TI1_MASK 0x02000000 /**< Timer 1 Interrupt */
-
-#define XUSBPS_IXR_ALL (XUSBPS_IXR_UI_MASK | \
- XUSBPS_IXR_UE_MASK | \
- XUSBPS_IXR_PC_MASK | \
- XUSBPS_IXR_FRE_MASK | \
- XUSBPS_IXR_AA_MASK | \
- XUSBPS_IXR_UR_MASK | \
- XUSBPS_IXR_SR_MASK | \
- XUSBPS_IXR_SLE_MASK | \
- XUSBPS_IXR_ULPI_MASK | \
- XUSBPS_IXR_HCH_MASK | \
- XUSBPS_IXR_RCL_MASK | \
- XUSBPS_IXR_PS_MASK | \
- XUSBPS_IXR_AS_MASK | \
- XUSBPS_IXR_NAK_MASK | \
- XUSBPS_IXR_UA_MASK | \
- XUSBPS_IXR_UP_MASK | \
- XUSBPS_IXR_TI0_MASK | \
- XUSBPS_IXR_TI1_MASK)
- /**< Mask for ALL IRQ types */
-/* @} */
-
-
-/** @name USB Mode Register (MODE) bit positions.
- * @{
- */
-#define XUSBPS_MODE_CM_MASK 0x00000003 /**< Controller Mode Select */
-#define XUSBPS_MODE_CM_IDLE_MASK 0x00000000
-#define XUSBPS_MODE_CM_DEVICE_MASK 0x00000002
-#define XUSBPS_MODE_CM_HOST_MASK 0x00000003
-#define XUSBPS_MODE_ES_MASK 0x00000004 /**< USB Endian Select */
-#define XUSBPS_MODE_SLOM_MASK 0x00000008 /**< USB Setup Lockout Mode Disable */
-#define XUSBPS_MODE_SDIS_MASK 0x00000010
-#define XUSBPS_MODE_VALID_MASK 0x0000001F
-
-/* @} */
-
-
-/** @name USB Device Address Register (DEVICEADDR) bit positions.
- * @{
- */
-#define XUSBPS_DEVICEADDR_DEVICEAADV_MASK 0x01000000
- /**< Device Addr Auto Advance */
-#define XUSBPS_DEVICEADDR_ADDR_MASK 0xFE000000
- /**< Device Address */
-#define XUSBPS_DEVICEADDR_ADDR_SHIFT 25
- /**< Address shift */
-#define XUSBPS_DEVICEADDR_MAX 127
- /**< Biggest allowed address */
-/* @} */
-
-/** @name USB TT Control Register (TTCTRL) bit positions.
- * @{
- */
-#define XUSBPS_TTCTRL_HUBADDR_MASK 0x7F000000 /**< TT Hub Address */
-/* @} */
-
-
-/** @name USB Burst Size Register (BURSTSIZE) bit posisions.
- * @{
- */
-#define XUSBPS_BURSTSIZE_RX_MASK 0x000000FF /**< RX Burst Length */
-#define XUSBPS_BURSTSIZE_TX_MASK 0x0000FF00 /**< TX Burst Length */
-/* @} */
-
-
-/** @name USB Tx Fill Tuning Register (TXFILL) bit positions.
- * @{
- */
-#define XUSBPS_TXFILL_OVERHEAD_MASK 0x000000FF
- /**< Scheduler Overhead */
-#define XUSBPS_TXFILL_HEALTH_MASK 0x00001F00
- /**< Scheduler Health Cntr */
-#define XUSBPS_TXFILL_BURST_MASK 0x003F0000
- /**< FIFO Burst Threshold */
-/* @} */
-
-
-/** @name USB ULPI Viewport Register (ULPIVIEW) bit positions.
- * @{
- */
-#define XUSBPS_ULPIVIEW_DATWR_MASK 0x000000FF /**< ULPI Data Write */
-#define XUSBPS_ULPIVIEW_DATRD_MASK 0x0000FF00 /**< ULPI Data Read */
-#define XUSBPS_ULPIVIEW_ADDR_MASK 0x00FF0000 /**< ULPI Data Address */
-#define XUSBPS_ULPIVIEW_PORT_MASK 0x07000000 /**< ULPI Port Number */
-#define XUSBPS_ULPIVIEW_SS_MASK 0x08000000 /**< ULPI Synchronous State */
-#define XUSBPS_ULPIVIEW_RW_MASK 0x20000000 /**< ULPI Read/Write Control */
-#define XUSBPS_ULPIVIEW_RUN_MASK 0x40000000 /**< ULPI Run */
-#define XUSBPS_ULPIVIEW_WU_MASK 0x80000000 /**< ULPI Wakeup */
-/* @} */
-
-
-/** @name Port Status Control Register bit positions.
- * @{
- */
-#define XUSBPS_PORTSCR_CCS_MASK 0x00000001 /**< Current Connect Status */
-#define XUSBPS_PORTSCR_CSC_MASK 0x00000002 /**< Connect Status Change */
-#define XUSBPS_PORTSCR_PE_MASK 0x00000004 /**< Port Enable/Disable */
-#define XUSBPS_PORTSCR_PEC_MASK 0x00000008 /**< Port Enable/Disable Change */
-#define XUSBPS_PORTSCR_OCA_MASK 0x00000010 /**< Over-current Active */
-#define XUSBPS_PORTSCR_OCC_MASK 0x00000020 /**< Over-current Change */
-#define XUSBPS_PORTSCR_FPR_MASK 0x00000040 /**< Force Port Resume */
-#define XUSBPS_PORTSCR_SUSP_MASK 0x00000080 /**< Suspend */
-#define XUSBPS_PORTSCR_PR_MASK 0x00000100 /**< Port Reset */
-#define XUSBPS_PORTSCR_HSP_MASK 0x00000200 /**< High Speed Port */
-#define XUSBPS_PORTSCR_LS_MASK 0x00000C00 /**< Line Status */
-#define XUSBPS_PORTSCR_PP_MASK 0x00001000 /**< Port Power */
-#define XUSBPS_PORTSCR_PO_MASK 0x00002000 /**< Port Owner */
-#define XUSBPS_PORTSCR_PIC_MASK 0x0000C000 /**< Port Indicator Control */
-#define XUSBPS_PORTSCR_PTC_MASK 0x000F0000 /**< Port Test Control */
-#define XUSBPS_PORTSCR_WKCN_MASK 0x00100000 /**< Wake on Connect Enable */
-#define XUSBPS_PORTSCR_WKDS_MASK 0x00200000 /**< Wake on Disconnect Enable */
-#define XUSBPS_PORTSCR_WKOC_MASK 0x00400000 /**< Wake on Over-current Enable */
-#define XUSBPS_PORTSCR_PHCD_MASK 0x00800000 /**< PHY Low Power Suspend -
- * Clock Disable */
-#define XUSBPS_PORTSCR_PFSC_MASK 0x01000000 /**< Port Force Full Speed
- * Connect */
-#define XUSBPS_PORTSCR_PSPD_MASK 0x0C000000 /**< Port Speed */
-/* @} */
-
-
-/** @name On-The-Go Status Control Register (OTGCSR) bit positions.
- * @{
- */
-#define XUSBPS_OTGSC_VD_MASK 0x00000001 /**< VBus Discharge Bit */
-#define XUSBPS_OTGSC_VC_MASK 0x00000002 /**< VBus Charge Bit */
-#define XUSBPS_OTGSC_HAAR_MASK 0x00000004 /**< HW Assist Auto Reset
- * Enable Bit */
-#define XUSBPS_OTGSC_OT_MASK 0x00000008 /**< OTG Termination Bit */
-#define XUSBPS_OTGSC_DP_MASK 0x00000010 /**< Data Pulsing Pull-up
- * Enable Bit */
-#define XUSBPS_OTGSC_IDPU_MASK 0x00000020 /**< ID Pull-up Enable Bit */
-#define XUSBPS_OTGSC_HADP_MASK 0x00000040 /**< HW Assist Data Pulse
- * Enable Bit */
-#define XUSBPS_OTGSC_HABA_MASK 0x00000080 /**< USB Hardware Assist
- * B Disconnect to A
- * Connect Enable Bit */
-#define XUSBPS_OTGSC_ID_MASK 0x00000100 /**< ID Status Flag */
-#define XUSBPS_OTGSC_AVV_MASK 0x00000200 /**< USB A VBus Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_ASV_MASK 0x00000400 /**< USB A Session Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_BSV_MASK 0x00000800 /**< USB B Session Valid Status Flag */
-#define XUSBPS_OTGSC_BSE_MASK 0x00001000 /**< USB B Session End Status Flag */
-#define XUSBPS_OTGSC_1MST_MASK 0x00002000 /**< USB 1 Millisecond Timer Status Flag */
-#define XUSBPS_OTGSC_DPS_MASK 0x00004000 /**< Data Pulse Status Flag */
-#define XUSBPS_OTGSC_IDIS_MASK 0x00010000 /**< USB ID Interrupt Status Flag */
-#define XUSBPS_OTGSC_AVVIS_MASK 0x00020000 /**< USB A VBus Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_ASVIS_MASK 0x00040000 /**< USB A Session Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_BSVIS_MASK 0x00080000 /**< USB B Session Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_BSEIS_MASK 0x00100000 /**< USB B Session End Interrupt Status Flag */
-#define XUSBPS_OTGSC_1MSS_MASK 0x00200000 /**< 1 Millisecond Timer Interrupt Status Flag */
-#define XUSBPS_OTGSC_DPIS_MASK 0x00400000 /**< Data Pulse Interrupt Status Flag */
-#define XUSBPS_OTGSC_IDIE_MASK 0x01000000 /**< ID Interrupt Enable Bit */
-#define XUSBPS_OTGSC_AVVIE_MASK 0x02000000 /**< USB A VBus Valid Interrupt Enable Bit */
-#define XUSBPS_OTGSC_ASVIE_MASK 0x04000000 /**< USB A Session Valid Interrupt Enable Bit */
-#define XUSBPS_OTGSC_BSVIE_MASK 0x08000000 /**< USB B Session Valid Interrupt Enable Bit */
-#define XUSBPS_OTGSC_BSEE_MASK 0x10000000 /**< USB B Session End Interrupt Enable Bit */
-#define XUSBPS_OTGSC_1MSE_MASK 0x20000000 /**< 1 Millisecond Timer
- * Interrupt Enable Bit */
-#define XUSBPS_OTGSC_DPIE_MASK 0x40000000 /**< Data Pulse Interrupt
- * Enable Bit */
-
-#define XUSBPS_OTG_ISB_ALL (XUSBPS_OTGSC_IDIS_MASK |\
- XUSBPS_OTGSC_AVVIS_MASK | \
- XUSBPS_OTGSC_ASVIS_MASK | \
- XUSBPS_OTGSC_BSVIS_MASK | \
- XUSBPS_OTGSC_BSEIS_MASK | \
- XUSBPS_OTGSC_1MSS_MASK | \
- XUSBPS_OTGSC_DPIS_MASK)
- /** Mask for All IRQ status masks */
-
-#define XUSBPS_OTG_IEB_ALL (XUSBPS_OTGSC_IDIE_MASK |\
- XUSBPS_OTGSC_AVVIE_MASK | \
- XUSBPS_OTGSC_ASVIE_MASK | \
- XUSBPS_OTGSC_BSVIE_MASK | \
- XUSBPS_OTGSC_BSEE_IEB_MASK | \
- XUSBPS_OTGSC_1MSE_MASK | \
- XUSBPS_OTGSC_DPIE_MASK)
- /** Mask for All IRQ Enable masks */
-/* @} */
-
-
-/**< Alignment of the Device Queue Head List BASE. */
-#define XUSBPS_dQH_BASE_ALIGN 2048
-
-/**< Alignment of a Device Queue Head structure. */
-#define XUSBPS_dQH_ALIGN 64
-
-/**< Alignment of a Device Transfer Descriptor structure. */
-#define XUSBPS_dTD_ALIGN 32
-
-/**< Size of one RX buffer for a OUT Transfer Descriptor. */
-#define XUSBPS_dTD_BUF_SIZE 4096
-
-/**< Maximum size of one RX/TX buffer. */
-#define XUSBPS_dTD_BUF_MAX_SIZE 16*1024
-
-/**< Alignment requirement for Transfer Descriptor buffers. */
-#define XUSBPS_dTD_BUF_ALIGN 4096
-
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* This macro reads the given register.
-*
-* @param BaseAddress is the base address for the USB registers.
-* @param RegOffset is the register offset to be read.
-*
-* @return The 32-bit value of the register.
-*
-* @note C-style signature:
-* u32 XUsbPs_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XUsbPs_ReadReg(BaseAddress, RegOffset) \
- Xil_In32(BaseAddress + (RegOffset))
-
-
-/****************************************************************************/
-/**
-*
-* This macro writes the given register.
-*
-* @param BaseAddress is the the base address for the USB registers.
-* @param RegOffset is the register offset to be written.
-* @param Data is the the 32-bit value to write to the register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XUsbPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
- *****************************************************************************/
-#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data) \
- Xil_Out32(BaseAddress + (RegOffset), (Data))
-
-
-/************************** Function Prototypes ******************************/
-/*
- * Perform reset operation to the USB PS interface
- */
-void XUsbPs_ResetHw(u32 BaseAddress);
-/************************** Variable Definitions ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XUSBPS_L_H */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/71/81456e565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/71/81456e565243001d18b399c1eb9b3628
deleted file mode 100644
index 1e9e6fb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/71/81456e565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,522 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xstatus.h
-*
-* @addtogroup common_status_codes Xilinx software status codes
-*
-* The xstatus.h file contains the Xilinx software status codes.These codes are
-* used throughout the Xilinx device drivers.
-*
-* @{
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XSTATUS_H /* prevent circular inclusions */
-#define XSTATUS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/*********************** Common statuses 0 - 500 *****************************/
-/**
-@name Common Status Codes for All Device Drivers
-@{
-*/
-#define XST_SUCCESS 0L
-#define XST_FAILURE 1L
-#define XST_DEVICE_NOT_FOUND 2L
-#define XST_DEVICE_BLOCK_NOT_FOUND 3L
-#define XST_INVALID_VERSION 4L
-#define XST_DEVICE_IS_STARTED 5L
-#define XST_DEVICE_IS_STOPPED 6L
-#define XST_FIFO_ERROR 7L /*!< An error occurred during an
- operation with a FIFO such as
- an underrun or overrun, this
- error requires the device to
- be reset */
-#define XST_RESET_ERROR 8L /*!< An error occurred which requires
- the device to be reset */
-#define XST_DMA_ERROR 9L /*!< A DMA error occurred, this error
- typically requires the device
- using the DMA to be reset */
-#define XST_NOT_POLLED 10L /*!< The device is not configured for
- polled mode operation */
-#define XST_FIFO_NO_ROOM 11L /*!< A FIFO did not have room to put
- the specified data into */
-#define XST_BUFFER_TOO_SMALL 12L /*!< The buffer is not large enough
- to hold the expected data */
-#define XST_NO_DATA 13L /*!< There was no data available */
-#define XST_REGISTER_ERROR 14L /*!< A register did not contain the
- expected value */
-#define XST_INVALID_PARAM 15L /*!< An invalid parameter was passed
- into the function */
-#define XST_NOT_SGDMA 16L /*!< The device is not configured for
- scatter-gather DMA operation */
-#define XST_LOOPBACK_ERROR 17L /*!< A loopback test failed */
-#define XST_NO_CALLBACK 18L /*!< A callback has not yet been
- registered */
-#define XST_NO_FEATURE 19L /*!< Device is not configured with
- the requested feature */
-#define XST_NOT_INTERRUPT 20L /*!< Device is not configured for
- interrupt mode operation */
-#define XST_DEVICE_BUSY 21L /*!< Device is busy */
-#define XST_ERROR_COUNT_MAX 22L /*!< The error counters of a device
- have maxed out */
-#define XST_IS_STARTED 23L /*!< Used when part of device is
- already started i.e.
- sub channel */
-#define XST_IS_STOPPED 24L /*!< Used when part of device is
- already stopped i.e.
- sub channel */
-#define XST_DATA_LOST 26L /*!< Driver defined error */
-#define XST_RECV_ERROR 27L /*!< Generic receive error */
-#define XST_SEND_ERROR 28L /*!< Generic transmit error */
-#define XST_NOT_ENABLED 29L /*!< A requested service is not
- available because it has not
- been enabled */
-#define XST_NO_ACCESS 30L /* Generic access error */
-#define XST_TIMEOUT 31L /*!< Event timeout occurred */
-
-/** @} */
-/***************** Utility Component statuses 401 - 500 *********************/
-/**
-@name Utility Component Status Codes 401 - 500
-@{
-*/
-#define XST_MEMTEST_FAILED 401L /*!< Memory test failed */
-
-/** @} */
-/***************** Common Components statuses 501 - 1000 *********************/
-/**
-@name Packet Fifo Status Codes 501 - 510
-@{
-*/
-/********************* Packet Fifo statuses 501 - 510 ************************/
-
-#define XST_PFIFO_LACK_OF_DATA 501L /*!< Not enough data in FIFO */
-#define XST_PFIFO_NO_ROOM 502L /*!< Not enough room in FIFO */
-#define XST_PFIFO_BAD_REG_VALUE 503L /*!< Self test, a register value
- was invalid after reset */
-#define XST_PFIFO_ERROR 504L /*!< Generic packet FIFO error */
-#define XST_PFIFO_DEADLOCK 505L /*!< Packet FIFO is reporting
- * empty and full simultaneously
- */
-/** @} */
-/**
-@name DMA Status Codes 511 - 530
-@{
-*/
-/************************** DMA statuses 511 - 530 ***************************/
-
-#define XST_DMA_TRANSFER_ERROR 511L /*!< Self test, DMA transfer
- failed */
-#define XST_DMA_RESET_REGISTER_ERROR 512L /*!< Self test, a register value
- was invalid after reset */
-#define XST_DMA_SG_LIST_EMPTY 513L /*!< Scatter gather list contains
- no buffer descriptors ready
- to be processed */
-#define XST_DMA_SG_IS_STARTED 514L /*!< Scatter gather not stopped */
-#define XST_DMA_SG_IS_STOPPED 515L /*!< Scatter gather not running */
-#define XST_DMA_SG_LIST_FULL 517L /*!< All the buffer descriptors of
- the scatter gather list are
- being used */
-#define XST_DMA_SG_BD_LOCKED 518L /*!< The scatter gather buffer
- descriptor which is to be
- copied over in the scatter
- list is locked */
-#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /*!< No buffer descriptors have been
- put into the scatter gather
- list to be committed */
-#define XST_DMA_SG_COUNT_EXCEEDED 521L /*!< The packet count threshold
- specified was larger than the
- total # of buffer descriptors
- in the scatter gather list */
-#define XST_DMA_SG_LIST_EXISTS 522L /*!< The scatter gather list has
- already been created */
-#define XST_DMA_SG_NO_LIST 523L /*!< No scatter gather list has
- been created */
-#define XST_DMA_SG_BD_NOT_COMMITTED 524L /*!< The buffer descriptor which was
- being started was not committed
- to the list */
-#define XST_DMA_SG_NO_DATA 525L /*!< The buffer descriptor to start
- has already been used by the
- hardware so it can't be reused
- */
-#define XST_DMA_SG_LIST_ERROR 526L /*!< General purpose list access
- error */
-#define XST_DMA_BD_ERROR 527L /*!< General buffer descriptor
- error */
-/** @} */
-/**
-@name IPIF Status Codes Codes 531 - 550
-@{
-*/
-/************************** IPIF statuses 531 - 550 ***************************/
-
-#define XST_IPIF_REG_WIDTH_ERROR 531L /*!< An invalid register width
- was passed into the function */
-#define XST_IPIF_RESET_REGISTER_ERROR 532L /*!< The value of a register at
- reset was not valid */
-#define XST_IPIF_DEVICE_STATUS_ERROR 533L /*!< A write to the device interrupt
- status register did not read
- back correctly */
-#define XST_IPIF_DEVICE_ACK_ERROR 534L /*!< The device interrupt status
- register did not reset when
- acked */
-#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /*!< The device interrupt enable
- register was not updated when
- other registers changed */
-#define XST_IPIF_IP_STATUS_ERROR 536L /*!< A write to the IP interrupt
- status register did not read
- back correctly */
-#define XST_IPIF_IP_ACK_ERROR 537L /*!< The IP interrupt status register
- did not reset when acked */
-#define XST_IPIF_IP_ENABLE_ERROR 538L /*!< IP interrupt enable register was
- not updated correctly when other
- registers changed */
-#define XST_IPIF_DEVICE_PENDING_ERROR 539L /*!< The device interrupt pending
- register did not indicate the
- expected value */
-#define XST_IPIF_DEVICE_ID_ERROR 540L /*!< The device interrupt ID register
- did not indicate the expected
- value */
-#define XST_IPIF_ERROR 541L /*!< Generic ipif error */
-/** @} */
-
-/****************** Device specific statuses 1001 - 4095 *********************/
-/**
-@name Ethernet Status Codes 1001 - 1050
-@{
-*/
-/********************* Ethernet statuses 1001 - 1050 *************************/
-
-#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /*!< Memory space is not big enough
- * to hold the minimum number of
- * buffers or descriptors */
-#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /*!< Memory allocation failed */
-#define XST_EMAC_MII_READ_ERROR 1003L /*!< MII read error */
-#define XST_EMAC_MII_BUSY 1004L /*!< An MII operation is in progress */
-#define XST_EMAC_OUT_OF_BUFFERS 1005L /*!< Driver is out of buffers */
-#define XST_EMAC_PARSE_ERROR 1006L /*!< Invalid driver init string */
-#define XST_EMAC_COLLISION_ERROR 1007L /*!< Excess deferral or late
- * collision on polled send */
-/** @} */
-/**
-@name UART Status Codes 1051 - 1075
-@{
-*/
-/*********************** UART statuses 1051 - 1075 ***************************/
-#define XST_UART
-
-#define XST_UART_INIT_ERROR 1051L
-#define XST_UART_START_ERROR 1052L
-#define XST_UART_CONFIG_ERROR 1053L
-#define XST_UART_TEST_FAIL 1054L
-#define XST_UART_BAUD_ERROR 1055L
-#define XST_UART_BAUD_RANGE 1056L
-
-/** @} */
-/**
-@name IIC Status Codes 1076 - 1100
-@{
-*/
-/************************ IIC statuses 1076 - 1100 ***************************/
-
-#define XST_IIC_SELFTEST_FAILED 1076 /*!< self test failed */
-#define XST_IIC_BUS_BUSY 1077 /*!< bus found busy */
-#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /*!< mastersend attempted with */
- /* general call address */
-#define XST_IIC_STAND_REG_RESET_ERROR 1079 /*!< A non parameterizable reg */
- /* value after reset not valid */
-#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /*!< Tx fifo included in design */
- /* value after reset not valid */
-#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /*!< Rx fifo included in design */
- /* value after reset not valid */
-#define XST_IIC_TBA_REG_RESET_ERROR 1082 /*!< 10 bit addr incl in design */
- /* value after reset not valid */
-#define XST_IIC_CR_READBACK_ERROR 1083 /*!< Read of the control register */
- /* didn't return value written */
-#define XST_IIC_DTR_READBACK_ERROR 1084 /*!< Read of the data Tx reg */
- /* didn't return value written */
-#define XST_IIC_DRR_READBACK_ERROR 1085 /*!< Read of the data Receive reg */
- /* didn't return value written */
-#define XST_IIC_ADR_READBACK_ERROR 1086 /*!< Read of the data Tx reg */
- /* didn't return value written */
-#define XST_IIC_TBA_READBACK_ERROR 1087 /*!< Read of the 10 bit addr reg */
- /* didn't return written value */
-#define XST_IIC_NOT_SLAVE 1088 /*!< The device isn't a slave */
-#define XST_IIC_ARB_LOST 1089 /*!< Arbitration lost for master */
-/** @} */
-/**
-@name ATMC Status Codes 1101 - 1125
-@{
-*/
-/*********************** ATMC statuses 1101 - 1125 ***************************/
-
-#define XST_ATMC_ERROR_COUNT_MAX 1101L /*!< the error counters in the ATM
- controller hit the max value
- which requires the statistics
- to be cleared */
-/** @} */
-/**
-@name Flash Status Codes 1126 - 1150
-@{
-*/
-/*********************** Flash statuses 1126 - 1150 **************************/
-
-#define XST_FLASH_BUSY 1126L /*!< Flash is erasing or programming
- */
-#define XST_FLASH_READY 1127L /*!< Flash is ready for commands */
-#define XST_FLASH_ERROR 1128L /*!< Flash had detected an internal
- error. Use XFlash_DeviceControl
- to retrieve device specific codes
- */
-#define XST_FLASH_ERASE_SUSPENDED 1129L /*!< Flash is in suspended erase state
- */
-#define XST_FLASH_WRITE_SUSPENDED 1130L /*!< Flash is in suspended write state
- */
-#define XST_FLASH_PART_NOT_SUPPORTED 1131L /*!< Flash type not supported by
- driver */
-#define XST_FLASH_NOT_SUPPORTED 1132L /*!< Operation not supported */
-#define XST_FLASH_TOO_MANY_REGIONS 1133L /*!< Too many erase regions */
-#define XST_FLASH_TIMEOUT_ERROR 1134L /*!< Programming or erase operation
- aborted due to a timeout */
-#define XST_FLASH_ADDRESS_ERROR 1135L /*!< Accessed flash outside its
- addressible range */
-#define XST_FLASH_ALIGNMENT_ERROR 1136L /*!< Write alignment error */
-#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /*!< Couldn't return immediately from
- write/erase function with
- XFL_NON_BLOCKING_WRITE/ERASE
- option cleared */
-#define XST_FLASH_CFI_QUERY_ERROR 1138L /*!< Failed to query the device */
-/** @} */
-/**
-@name SPI Status Codes 1151 - 1175
-@{
-*/
-/*********************** SPI statuses 1151 - 1175 ****************************/
-
-#define XST_SPI_MODE_FAULT 1151 /*!< master was selected as slave */
-#define XST_SPI_TRANSFER_DONE 1152 /*!< data transfer is complete */
-#define XST_SPI_TRANSMIT_UNDERRUN 1153 /*!< slave underruns transmit register */
-#define XST_SPI_RECEIVE_OVERRUN 1154 /*!< device overruns receive register */
-#define XST_SPI_NO_SLAVE 1155 /*!< no slave has been selected yet */
-#define XST_SPI_TOO_MANY_SLAVES 1156 /*!< more than one slave is being
- * selected */
-#define XST_SPI_NOT_MASTER 1157 /*!< operation is valid only as master */
-#define XST_SPI_SLAVE_ONLY 1158 /*!< device is configured as slave-only
- */
-#define XST_SPI_SLAVE_MODE_FAULT 1159 /*!< slave was selected while disabled */
-#define XST_SPI_SLAVE_MODE 1160 /*!< device has been addressed as slave */
-#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /*!< device received data in slave mode */
-
-#define XST_SPI_COMMAND_ERROR 1162 /*!< unrecognised command - qspi only */
-#define XST_SPI_POLL_DONE 1163 /*!< controller completed polling the
- device for status */
-/** @} */
-/**
-@name OPB Arbiter Status Codes 1176 - 1200
-@{
-*/
-/********************** OPB Arbiter statuses 1176 - 1200 *********************/
-
-#define XST_OPBARB_INVALID_PRIORITY 1176 /*!< the priority registers have either
- * one master assigned to two or more
- * priorities, or one master not
- * assigned to any priority
- */
-#define XST_OPBARB_NOT_SUSPENDED 1177 /*!< an attempt was made to modify the
- * priority levels without first
- * suspending the use of priority
- * levels
- */
-#define XST_OPBARB_PARK_NOT_ENABLED 1178 /*!< bus parking by id was enabled but
- * bus parking was not enabled
- */
-#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /*!< the arbiter must be in fixed
- * priority mode to allow the
- * priorities to be changed
- */
-/** @} */
-/**
-@name INTC Status Codes 1201 - 1225
-@{
-*/
-/************************ Intc statuses 1201 - 1225 **************************/
-
-#define XST_INTC_FAIL_SELFTEST 1201 /*!< self test failed */
-#define XST_INTC_CONNECT_ERROR 1202 /*!< interrupt already in use */
-/** @} */
-/**
-@name TmrCtr Status Codes 1226 - 1250
-@{
-*/
-/********************** TmrCtr statuses 1226 - 1250 **************************/
-
-#define XST_TMRCTR_TIMER_FAILED 1226 /*!< self test failed */
-/** @} */
-/**
-@name WdtTb Status Codes 1251 - 1275
-@{
-*/
-/********************** WdtTb statuses 1251 - 1275 ***************************/
-
-#define XST_WDTTB_TIMER_FAILED 1251L
-/** @} */
-/**
-@name PlbArb status Codes 1276 - 1300
-@{
-*/
-/********************** PlbArb statuses 1276 - 1300 **************************/
-
-#define XST_PLBARB_FAIL_SELFTEST 1276L
-/** @} */
-/**
-@name Plb2Opb Status Codes 1301 - 1325
-@{
-*/
-/********************** Plb2Opb statuses 1301 - 1325 *************************/
-
-#define XST_PLB2OPB_FAIL_SELFTEST 1301L
-/** @} */
-/**
-@name Opb2Plb Status 1326 - 1350
-@{
-*/
-/********************** Opb2Plb statuses 1326 - 1350 *************************/
-
-#define XST_OPB2PLB_FAIL_SELFTEST 1326L
-/** @} */
-/**
-@name SysAce Status Codes 1351 - 1360
-@{
-*/
-/********************** SysAce statuses 1351 - 1360 **************************/
-
-#define XST_SYSACE_NO_LOCK 1351L /*!< No MPU lock has been granted */
-/** @} */
-/**
-@name PCI Bridge Status Codes 1361 - 1375
-@{
-*/
-/********************** PCI Bridge statuses 1361 - 1375 **********************/
-
-#define XST_PCI_INVALID_ADDRESS 1361L
-/** @} */
-/**
-@name FlexRay Constants 1400 - 1409
-@{
-*/
-/********************** FlexRay constants 1400 - 1409 *************************/
-
-#define XST_FR_TX_ERROR 1400
-#define XST_FR_TX_BUSY 1401
-#define XST_FR_BUF_LOCKED 1402
-#define XST_FR_NO_BUF 1403
-/** @} */
-/**
-@name USB constants 1410 - 1420
-@{
-*/
-/****************** USB constants 1410 - 1420 *******************************/
-
-#define XST_USB_ALREADY_CONFIGURED 1410
-#define XST_USB_BUF_ALIGN_ERROR 1411
-#define XST_USB_NO_DESC_AVAILABLE 1412
-#define XST_USB_BUF_TOO_BIG 1413
-#define XST_USB_NO_BUF 1414
-/** @} */
-/**
-@name HWICAP constants 1421 - 1429
-@{
-*/
-/****************** HWICAP constants 1421 - 1429 *****************************/
-
-#define XST_HWICAP_WRITE_DONE 1421
-
-/** @} */
-/**
-@name AXI VDMA constants 1430 - 1440
-@{
-*/
-/****************** AXI VDMA constants 1430 - 1440 *****************************/
-
-#define XST_VDMA_MISMATCH_ERROR 1430
-/** @} */
-/**
-@name NAND Flash Status Codes 1441 - 1459
-@{
-*/
-/*********************** NAND Flash statuses 1441 - 1459 *********************/
-
-#define XST_NAND_BUSY 1441L /*!< Flash is erasing or
- * programming
- */
-#define XST_NAND_READY 1442L /*!< Flash is ready for commands
- */
-#define XST_NAND_ERROR 1443L /*!< Flash had detected an
- * internal error.
- */
-#define XST_NAND_PART_NOT_SUPPORTED 1444L /*!< Flash type not supported by
- * driver
- */
-#define XST_NAND_OPT_NOT_SUPPORTED 1445L /*!< Operation not supported
- */
-#define XST_NAND_TIMEOUT_ERROR 1446L /*!< Programming or erase
- * operation aborted due to a
- * timeout
- */
-#define XST_NAND_ADDRESS_ERROR 1447L /*!< Accessed flash outside its
- * addressible range
- */
-#define XST_NAND_ALIGNMENT_ERROR 1448L /*!< Write alignment error
- */
-#define XST_NAND_PARAM_PAGE_ERROR 1449L /*!< Failed to read parameter
- * page of the device
- */
-#define XST_NAND_CACHE_ERROR 1450L /*!< Flash page buffer error
- */
-
-#define XST_NAND_WRITE_PROTECTED 1451L /*!< Flash is write protected
- */
-/** @} */
-
-/**************************** Type Definitions *******************************/
-
-typedef s32 XStatus;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
-
-/**
-* @} End of "addtogroup common_status_codes".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/71/f138e5585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/71/f138e5585243001d18b399c1eb9b3628
deleted file mode 100644
index 25fc262..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/71/f138e5585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,132 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xil-crt0.S
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 10/20/09 Initial version
-* 3.05a sdm 02/02/12 Added code for profiling
-* 3.06a sgd 05/16/12 Added global constructors and cleanup code
-* Uart initialization based on compiler flag
-* 3.07a sgd 07/05/12 Updated with reset and start Global Timer
-* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
-* 4.2 pkp 08/04/14 Removed PEEP board related code which contained
-* initialization of uart smc nor and sram
-* 5.3 pkp 10/07/15 Added support for OpenAMP by not initializing global
-* timer when USE_AMP flag is defined
-* 6.6 srm 10/18/17 Added timer configuration using XTime_StartTTCTimer API.
-* Now the TTC instance as specified by the user will be
-* started.
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#include "bspconfig.h"
-
- .file "xil-crt0.S"
- .section ".got2","aw"
- .align 2
-
- .text
-.Lsbss_start:
- .long __sbss_start
-
-.Lsbss_end:
- .long __sbss_end
-
-.Lbss_start:
- .long __bss_start
-
-.Lbss_end:
- .long __bss_end
-
-.Lstack:
- .long __stack
-
-
- .globl _start
-_start:
- bl __cpu_init /* Initialize the CPU first (BSP provides this) */
-
- mov r0, #0
-
- /* clear sbss */
- ldr r1,.Lsbss_start /* calculate beginning of the SBSS */
- ldr r2,.Lsbss_end /* calculate end of the SBSS */
-
-.Lloop_sbss:
- cmp r1,r2
- bge .Lenclsbss /* If no SBSS, no clearing required */
- str r0, [r1], #4
- b .Lloop_sbss
-
-.Lenclsbss:
- /* clear bss */
- ldr r1,.Lbss_start /* calculate beginning of the BSS */
- ldr r2,.Lbss_end /* calculate end of the BSS */
-
-.Lloop_bss:
- cmp r1,r2
- bge .Lenclbss /* If no BSS, no clearing required */
- str r0, [r1], #4
- b .Lloop_bss
-
-.Lenclbss:
-
- /* set stack pointer */
- ldr r13,.Lstack /* stack address */
-
- /* Reset and start Global Timer */
- mov r0, #0x0
- mov r1, #0x0
-
- /* Reset and start Triple Timer Counter */
- #if defined SLEEP_TIMER_BASEADDR
- bl XTime_StartTTCTimer
- #endif
-
-#if USE_AMP != 1
- bl XTime_SetTime
-#endif
-
-#ifdef PROFILING /* defined in Makefile */
- /* Setup profiling stuff */
- bl _profile_init
-#endif /* PROFILING */
-
- /* run global constructors */
- bl __libc_init_array
-
- /* make sure argc and argv are valid */
- mov r0, #0
- mov r1, #0
-
- /* Let her rip */
- bl main
-
- /* Cleanup global constructors */
- bl __libc_fini_array
-
-#ifdef PROFILING
- /* Cleanup profiling stuff */
- bl _profile_clean
-#endif /* PROFILING */
-
- /* All done */
- bl exit
-
-.Lexit: /* should never get here */
- b .Lexit
-
-.Lstart:
- .size _start,.Lstart-_start
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/72/207695595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/72/207695595243001d18b399c1eb9b3628
deleted file mode 100644
index 6719ab0..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/72/207695595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,62 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file vectors.h
-*
-* This file contains the C level vector prototypes for the ARM Cortex A9 core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 10/20/10 Initial version, moved over from bsp area
-* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#ifndef _VECTORS_H_
-#define _VECTORS_H_
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void FIQInterrupt(void);
-void IRQInterrupt(void);
-#if !defined (__aarch64__)
-void SWInterrupt(void);
-void DataAbortInterrupt(void);
-void PrefetchAbortInterrupt(void);
-void UndefinedException(void);
-#else
-void SynchronousInterrupt(void);
-void SErrorInterrupt(void);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* protection macro */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/72/510cd5585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/72/510cd5585243001d18b399c1eb9b3628
deleted file mode 100644
index 243c109..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/72/510cd5585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,12 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#include "xil_types.h"
-/* Stub for read() sys-call */
-__weak s32 _sys_read(u32 fh, u8 *buf, u32 len, s32 mode)
-{
- /* Return the number of character NOT read */
- return len;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/73/113038585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/73/113038585243001d18b399c1eb9b3628
deleted file mode 100644
index d90ef88..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/73/113038585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,83 +0,0 @@
-###############################################################################
-# Copyright (c) 2011 - 2020 Xilinx, Inc. All rights reserved.
-# SPDX-License-Identifier: MIT
-###############################################################################
-DRIVER_LIB_VERSION = v1.0
-
-include config.make
-
-CC=$(COMPILER)
-AR=$(ARCHIVER)
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS))
-ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS))
-
-ifeq (($(notdir $(CC))) , arm-xilinx-eabi-gcc)
-ECC_FLAGS += -nostartfiles\
- -march=armv7-a \
- -mfloat-abi=soft \
- -mfpu=neon
-endif
-
-ifeq (($(notdir $(CC))) , arm-none-eabi-gcc)
-ECC_FLAGS += -nostartfiles
-endif
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-SRCFILES:=$(wildcard *.c)
-
-ASSEMBLY_SRCFILES:=$(wildcard *.S)
-
-OBJECTS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(wildcard *.c))))
-
-ASSEMBLY_OBJECTS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(wildcard *.S))))
-
-INCLUDEFILES=*.h
-
-libs: $(LIBS)
-
-standalone_libs: $(OBJECTS) $(ASSEMBLY_OBJECTS)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-ASSEMBLY_DEPFILES := $(ASSEMBLY_SRCFILES:%.S=$(RELEASEDIR)%.d)
-
-include $(wildcard $(ASSEMBLY_DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.S
- $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $<
-
-$(RELEASEDIR)%.o: %.c
- $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $<
-
-profile_libs:
- $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" libs
-
-.PHONY: include
-include: standalone_includes profile_includes
-
-standalone_includes: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-profile_includes:
- $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" include
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf ${ASSEMBLY_OBJECTS}
- rm -rf $(DEPFILES)
- rm -rf $(ASSEMBLY_DEPFILES)
- $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" clean
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/73/300579545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/73/300579545243001d18b399c1eb9b3628
deleted file mode 100644
index 6f40407..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/73/300579545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,52 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xcoresightpsdcc.h
-* @addtogroup coresightps_dcc_v1_8
-* @{
-* @details
-*
-* CoreSight driver component.
-*
-* The coresight is a part of debug communication channel (DCC) group. Jtag UART
-* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
-* ARM target in XSDB console before running the jtag terminal command. Using the
-* coresight driver component, the output stream can be directed to a log file.
-*
-* @note None.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------
-* 1.00 kvn 02/14/15 First release
-* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
-* kvn 08/18/15 Modified Makefile according to compiler changes.
-* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
-* for MB BSPs. Instead it throws up a warning. This
-* fixes the CR#953056.
-* 1.5 sne 01/19/19 Fixed MISRA-C Violations CR#1025101.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#ifndef XCORESIGHTPSDCC_H /* prevent circular inclusions */
-#define XCORESIGHTPSDCC_H /* by using protection macros */
-#ifndef __MICROBLAZE__
-#include
-
-void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
-
-u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
-#endif
-#endif
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/73/30569e565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/73/30569e565243001d18b399c1eb9b3628
deleted file mode 100644
index 6a5b232..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/73/30569e565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,46 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2008 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-* microblaze_invalidate_cache_ext()
-*
-*Invalidate the entire L2 Cache
-*
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-#include "microblaze_instructions.h"
-
-#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
-#define CACHEABLE_REGION_SIZE (XPAR_MICROBLAZE_DCACHE_HIGHADDR - XPAR_MICROBLAZE_DCACHE_BASEADDR)
-
- .text
- .globl microblaze_invalidate_cache_ext
- .ent microblaze_invalidate_cache_ext
- .align 2
-
-microblaze_invalidate_cache_ext:
-
-#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
- ADDIK r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN))
-
- ADDIK r6, r0, CACHEABLE_REGION_SIZE-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
- ANDI r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
-
-Loop_start:
- wdc.ext.clear r5, r6
-#if defined (__arch64__ )
- addlik r6, r6,-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
- beagei r6, Loop_start
-#else
- bgtid r6,Loop_start
- addik r6, r6,-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
-#endif
-#endif
- rtsd r15, 8
- nop
-
- .end microblaze_invalidate_cache_ext
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/73/4047bf525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/73/4047bf525243001d18b399c1eb9b3628
deleted file mode 100644
index 60f4ba3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/73/4047bf525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,53 +0,0 @@
-/******************************************************************************
-* Copyright (c) 1995 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-*******************************************************************************/
- #ifndef XIL_PRINTF_H
- #define XIL_PRINTF_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include
-#include
-#include
-#include "xil_types.h"
-#include "xparameters.h"
-#include "bspconfig.h"
-#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
-#include "xen_console.h"
-#endif
-
-/*----------------------------------------------------*/
-/* Use the following parameter passing structure to */
-/* make xil_printf re-entrant. */
-/*----------------------------------------------------*/
-
-struct params_s;
-
-
-/*---------------------------------------------------*/
-/* The purpose of this routine is to output data the */
-/* same as the standard printf function without the */
-/* overhead most run-time libraries involve. Usually */
-/* the printf brings in many kilobytes of code and */
-/* that is unacceptable in most embedded systems. */
-/*---------------------------------------------------*/
-
-typedef char8* charptr;
-typedef s32 (*func_ptr)(int c);
-
-/* */
-
-void xil_printf( const char8 *ctrl1, ...);
-void xil_vprintf(const char8 *ctrl1, va_list argp);
-void print( const char8 *ptr);
-extern void outbyte (char8 c);
-extern char8 inbyte(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/73/816f5b585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/73/816f5b585243001d18b399c1eb9b3628
deleted file mode 100644
index dd7972e..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/73/816f5b585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,26 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file initialise_monitor_handles.c
-*
-* Contains blank function to avoid compilation error
-*
-* @note
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/29/14 First release
-*
-******************************************************************************/
-__attribute__((weak)) void initialise_monitor_handles(){
-
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/74/20d268575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/74/20d268575243001d18b399c1eb9b3628
deleted file mode 100644
index a8544b3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/74/20d268575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,40 +0,0 @@
-/*******************************************************************************
-* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-*******************************************************************************/
-
-/******************************************************************************/
-/**
- *
- * @file xddrps.h
- * @addtogroup ddrps_v1_2
- * @{
- * @details
- *
- * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps
- * IP core.
- *
- * @note None.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.0 nsk 08/06/15 First Release
- * 1.0 nsk 08/20/15 Updated define_addr_params in ddrps.tcl
- * to support PBD Designs (CR #876857)
- *
- *
- *
-*******************************************************************************/
-
-#ifndef XDDRPS_H_
-/* Prevent circular inclusions by using protection macros. */
-#define XDDRPS_H_
-
-/******************************* Include Files ********************************/
-
-
-#endif /* XDDRPS_H_ */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/74/712aef555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/74/712aef555243001d18b399c1eb9b3628
deleted file mode 100644
index 0f7eb74..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/74/712aef555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,174 +0,0 @@
-;******************************************************************************
-; Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-; SPDX-License-Identifier: MIT
-;*****************************************************************************
-;****************************************************************************
-;**
-; @file translation_table.s
-;
-; This file contains the initialization for the MMU table in RAM
-; needed by the Cortex A9 processor
-;
-;
-; MODIFICATION HISTORY:
-;
-; Ver Who Date Changes
-; ----- ---- -------- ---------------------------------------------------
-; 1.00a ecm 10/20/09 Initial version
-; 3.07a sgd 07/05/12 Configuring device address spaces as shareable device
-; instead of strongly-ordered.
-; 4.2 pkp 09/02/14 modified translation table entries according to address map
-; 4.2 pkp 09/11/14 modified translation table entries to resolve compilation
-; error for solving CR#822897
-; 6.1 pkp 07/11/16 Corrected comments for memory attributes
-; 6.8 mus 07/12/2018 Mark DDR memory as inner cacheable, if BSP is built
-; with the USE_AMP flag.
-;
-;
-; @note
-;
-; None.
-;
-;****************************************************************************
- EXPORT MMUTable
-
-;ARMCC AREA |.mmu_tbl|,CODE,ALIGN=14
-; RSEG mmu_tbl:CODE:ROOT (14)
- SECTION .mmu_tbl:CODE:ROOT(14)
-
-MMUTable
- ; Each table entry occupies one 32-bit word and there are
- ; 4096 entries, so the entire table takes up 16KB.
- ; Each entry covers a 1MB section.
-
-
-; 0x00000000 - 0x3ffffff (DDR Cacheable)
-count SETA 0
-sect SETA 0
- REPT 0x400
- #ifndef USE_AMP
- DCD sect + 0x15de6 ; S=1, TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1
- #else
- DCD sect + 0x14de6 ; S=1, TEX=b100 AP=b11, Domain=b1111, C=b0, B=b1
- #endif
-sect SETA sect+0x100000
-count SETA count+1
- ENDR
-
-; 0x40000000 - 0x7fffffff (GpAxi0)
-count SETA 0
- REPT 0x400
- DCD sect + 0xc02 ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0
-sect SETA sect+0x100000
-count SETA count+1
- ENDR
-
-; 0x80000000 - 0xbfffffff (GpAxi1)
-count SETA 0
- REPT 0x400
- DCD sect + 0xc02 ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0
-sect SETA sect+0x100000
-count SETA count+1
- ENDR
-
-; 0xc0000000 - 0xdfffffff (undef)
-count SETA 0
- REPT 0x200
- DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0
-sect SETA sect+0x100000
-count SETA count+1
- ENDR
-
-; 0xe0000000 - 0xe02fffff (IOP dev)
-count SETA 0
- REPT 0x3
- DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0
-sect SETA sect+0x100000
-count SETA count+1
- ENDR
-
- ; 0xe0300000 - 0xe0ffffff (undef/reserved)
-count SETA 0
- REPT 0xD
- DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0
-sect SETA sect+0x100000
-count SETA count+1
- ENDR
-
-; 0xe1000000 - 0xe1ffffff (NAND)
-count SETA 0
- REPT 0x10
- DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0
-sect SETA sect+0x100000
-count SETA count+1
- ENDR
-
-; 0xe2000000 - 0xe3ffffff (NOR)
-count SETA 0
- REPT 0x20
- DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0
-sect SETA sect+0x100000
-count SETA count+1
- ENDR
-
-; 0xe4000000 - 0xe5ffffff (SRAM)
-count SETA 0
- REPT 0x20
- DCD sect + 0xc0e ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1
-sect SETA sect+0x100000
-count SETA count+1
- ENDR
-
-; 0xe6000000 - 0xf7ffffff (reserved)
-count SETA 0
- REPT 0x0120
- DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0
-sect SETA sect+0x100000
-count SETA count+1
- ENDR
-
-; 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and
-; 0xf8f03000 to 0xf8ffffff are reserved but due to granual size of
-; 1MB, it is not possible to define separate regions for them
-
-; 0xf8000000 - 0xf8ffffff (APB device regs)
-count SETA 0
- REPT 0x10
- DCD sect + 0xc06 ; S=0, TEX=b010 AP=b11, Domain=b0, C=b0, B=b0
-sect SETA sect+0x100000
-count SETA count+1
- ENDR
-
-; 0xf9000000 - 0xfbffffff (reserved)
-count SETA 0
- REPT 0x30
- DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0
-sect SETA sect+0x100000
-count SETA count+1
- ENDR
-
-; 0xfc000000 - 0xfdffffff (QSPI)
-count SETA 0
- REPT 0x20
- DCD sect + 0xc0a ; S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b0
-sect SETA sect+0x100000
-count SETA count+1
- ENDR
-
-; 0xfe000000 - 0xffefffff (reserved)
-count SETA 0
- REPT 0x1F
- DCD sect ; S=0, TEX=b000 AP=b00, Domain=b0, C=b0, B=b0
-sect SETA sect+0x100000
-count SETA count+1
- ENDR
-
-; 0xfff00000 to 0xfffb0000 is reserved but due to granual size of
-; 1MB, it is not possible to define separate region for it
-
-; 0xfff00000 to 0xfffb0000 (OCM)
-count SETA 0
- DCD sect + 0x4c0e ; S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1
-sect SETA sect+0x100000
-
- END
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/74/900003565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/74/900003565243001d18b399c1eb9b3628
deleted file mode 100644
index 31156ee..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/74/900003565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,96 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xl2cc_counter.h
-*
-* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions
-*
-* xl2cc_counter.h contains APIs for configuring and controlling the event
-* counters in PL310 L2 cache controller.
-* PL310 has two event counters which can be used to count variety of events
-* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions
-* for different configurations which can be used for the event counters to
-* count a set of events.
-*
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
-* inside the APIs
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-*
-******************************************************************************/
-
-/**
-*@cond nocomments
-*/
-
-#ifndef L2CCCOUNTER_H /* prevent circular inclusions */
-#define L2CCCOUNTER_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/************************** Constant Definitions ****************************/
-
-/*
- * The following constants define the event codes for the event counters.
- */
-#define XL2CC_CO 0x1
-#define XL2CC_DRHIT 0x2
-#define XL2CC_DRREQ 0x3
-#define XL2CC_DWHIT 0x4
-#define XL2CC_DWREQ 0x5
-#define XL2CC_DWTREQ 0x6
-#define XL2CC_IRHIT 0x7
-#define XL2CC_IRREQ 0x8
-#define XL2CC_WA 0x9
-#define XL2CC_IPFALLOC 0xa
-#define XL2CC_EPFHIT 0xb
-#define XL2CC_EPFALLOC 0xc
-#define XL2CC_SRRCVD 0xd
-#define XL2CC_SRCONF 0xe
-#define XL2CC_EPFRCVD 0xf
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/**
-*@endcond
-*/
-
-/************************** Function Prototypes *****************************/
-
-void XL2cc_EventCtrInit(s32 Event0, s32 Event1);
-void XL2cc_EventCtrStart(void);
-void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* L2CCCOUNTER_H */
-/**
-* @} End of "addtogroup l2_event_counter_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/74/b09518545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/74/b09518545243001d18b399c1eb9b3628
deleted file mode 100644
index 6b51ea9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/74/b09518545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,28 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-
-#ifndef _MBLAZE_NT_TYPES_H
-#define _MBLAZE_NT_TYPES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef char byte;
-typedef short half;
-typedef int word;
-typedef unsigned char ubyte;
-typedef unsigned short uhalf;
-typedef unsigned int uword;
-typedef ubyte boolean;
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/74/f0ddaf525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/74/f0ddaf525243001d18b399c1eb9b3628
deleted file mode 100644
index 21c8ced..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/74/f0ddaf525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,75 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache_l.h
-*
-* Contains L1 and L2 specific functions for the ARM cache functionality
-* used by xcache.c. This functionality is being made available here for
-* more sophisticated users.
-*
-* @addtogroup a9_cache_apis
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 01/24/10 First release
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 5.00a sgd 05/17/13 Initial release
-*
-*
-*
-* @note
-*
-******************************************************************************/
-#ifndef ___MD5_H___
-#define ___MD5_H___
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-#define MD5_SIGNATURE_BYTE_SIZE 64
-
-/**************************** Type Definitions *******************************/
-
-typedef u8 boolean;
-typedef u8 signature[ MD5_SIGNATURE_BYTE_SIZE ];
-
-struct MD5Context
- {
- u32 buffer[ 4 ];
- u32 bits[ 2 ];
- signature intermediate;
- };
-typedef struct MD5Context MD5Context;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*
- * The four core functions - F1 is optimized somewhat
- */
-#define F1( x, y, z ) ( z ^ ( x & ( y ^ z ) ) )
-#define F2( x, y, z ) F1( z, x, y )
-#define F3( x, y, z ) ( x ^ y ^ z )
-#define F4( x, y, z ) ( y ^ ( x | ~z ) )
-
-
-/*
- * This is the central step in the MD5 algorithm
- */
-#define MD5_STEP( f, w, x, y, z, data, s ) \
- ( w += f( x, y, z ) + data, w = w << s | w >> ( 32 - s ), w += x )
-
-
-/************************** Function Prototypes ******************************/
-
-void * MD5Memset( void *dest, int ch, u32 count );
-
-void * MD5Memcpy( void *dest, const void *src, u32 count, boolean doByteSwap );
-
-void MD5Transform( u32 *buffer, u32 *intermediate );
-
-void MD5Init( MD5Context *context );
-
-void MD5Update( MD5Context *context, u8 *buffer, u32 len, boolean doByteSwap );
-
-void MD5Final( MD5Context *context, u8 *digest, boolean doByteSwap );
-
-void md5( u8 *input, u32 len, u8 *digest, boolean doByteSwap );
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* ___MD5_H___ */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/75/80efb1545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/75/80efb1545243001d18b399c1eb9b3628
deleted file mode 100644
index 33b33eb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/75/80efb1545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,167 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xgpio_l.h
-* @addtogroup gpio_v4_8
-* @{
-*
-* This header file contains identifiers and driver functions (or
-* macros) that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-*
-* The macros that are available in this file use a multiply to calculate the
-* addresses of registers. The user can control whether that multiply is done
-* at run time or at compile time. A constant passed as the channel parameter
-* will cause the multiply to be done at compile time. A variable passed as the
-* channel parameter will cause it to occur at run time.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a jhl 04/24/02 First release of low level driver
-* 2.00a jhl 11/26/03 Added support for dual channels and interrupts. This
-* change required the functions to be changed such that
-* the interface is not compatible with previous versions.
-* See the examples in the example directory for macros
-* to help compile an application that was designed for
-* previous versions of the driver. The interrupt registers
-* are accessible using the ReadReg and WriteReg macros and
-* a channel parameter was added to the other macros.
-* 2.11a mta 03/21/07 Updated to new coding style
-* 2.12a sv 11/21/07 Updated driver to support access through DCR bus.
-* 3.00a sv 11/21/09 Renamed the macros XGpio_mWriteReg to XGpio_WriteReg
-* XGpio_mReadReg to XGpio_ReadReg.
-* Removed the macros XGpio_mSetDataDirection,
-* XGpio_mGetDataReg and XGpio_mSetDataReg. Users
-* should use XGpio_WriteReg/XGpio_ReadReg to achieve the
-* same functionality.
-* 4.1 lks 11/18/15 Removed support for DCR bridge
-*
-*
-******************************************************************************/
-
-#ifndef XGPIO_L_H /* prevent circular inclusions */
-#define XGPIO_L_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-
-/************************** Constant Definitions *****************************/
-
-/** @name Registers
- *
- * Register offsets for this device.
- * @{
- */
-#define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */
-#define XGPIO_TRI_OFFSET 0x4 /**< I/O direction reg for 1st channel */
-#define XGPIO_DATA2_OFFSET 0x8 /**< Data register for 2nd channel */
-#define XGPIO_TRI2_OFFSET 0xC /**< I/O direction reg for 2nd channel */
-
-#define XGPIO_GIE_OFFSET 0x11C /**< Glogal interrupt enable register */
-#define XGPIO_ISR_OFFSET 0x120 /**< Interrupt status register */
-#define XGPIO_IER_OFFSET 0x128 /**< Interrupt enable register */
-
-/** @} */
-
-/* The following constant describes the offset of each channels data and
- * tristate register from the base address.
- */
-#define XGPIO_CHAN_OFFSET 8 /**< Channel offeset */
-
-/** @name Interrupt Status and Enable Register bitmaps and masks
- *
- * Bit definitions for the interrupt status register and interrupt enable
- * registers.
- * @{
- */
-#define XGPIO_IR_MASK 0x3 /**< Mask of all bits */
-#define XGPIO_IR_CH1_MASK 0x1 /**< Mask for the 1st channel */
-#define XGPIO_IR_CH2_MASK 0x2 /**< Mask for the 2nd channel */
-/** @}*/
-
-
-/** @name Global Interrupt Enable Register bitmaps and masks
- *
- * Bit definitions for the Global Interrupt Enable register
- * @{
- */
-#define XGPIO_GIE_GINTR_ENABLE_MASK 0x80000000 /**< Mask for Global Interrupt */
-/** @}*/
-
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XGpio_In32 Xil_In32 /**< Input Operations */
-#define XGpio_Out32 Xil_Out32 /**< Output Operations */
-
-
-/****************************************************************************/
-/**
-*
-* Write a value to a GPIO register. A 32 bit write is performed. If the
-* GPIO core is implemented in a smaller width, only the least significant data
-* is written.
-*
-* @param BaseAddress is the base address of the GPIO device.
-* @param RegOffset is the register offset from the base to write to.
-* @param Data is the data written to the register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XGpio_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
-****************************************************************************/
-#define XGpio_WriteReg(BaseAddress, RegOffset, Data) \
- XGpio_Out32((BaseAddress) + (RegOffset), (u32)(Data))
-
-/****************************************************************************/
-/**
-*
-* Read a value from a GPIO register. A 32 bit read is performed. If the
-* GPIO core is implemented in a smaller width, only the least
-* significant data is read from the register. The most significant data
-* will be read as 0.
-*
-* @param BaseAddress is the base address of the GPIO device.
-* @param RegOffset is the register offset from the base to read from.
-*
-* @return Data read from the register.
-*
-* @note C-style signature:
-* u32 XGpio_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-****************************************************************************/
-#define XGpio_ReadReg(BaseAddress, RegOffset) \
- XGpio_In32((BaseAddress) + (RegOffset))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/75/a25252595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/75/a25252595243001d18b399c1eb9b3628
deleted file mode 100644
index 5f39620..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/75/a25252595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,20 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#include
-#include "xil_types.h"
-sint32 fcntl (sint32 fd, sint32 cmd, sint32 arg);
-
-/*
- * fcntl -- Manipulate a file descriptor.
- * We don't have a filesystem, so we do nothing.
- */
-sint32 fcntl (sint32 fd, sint32 cmd, sint32 arg)
-{
- (void) fd;
- (void) cmd;
- (void) arg;
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/75/b0ee89575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/75/b0ee89575243001d18b399c1eb9b3628
deleted file mode 100644
index 7e29233..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/75/b0ee89575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,165 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_testmem.h
-* @addtogroup common_test_utils Test Utilities for Memory and Caches
-*
-* - Cache test: xil_testcache.h contains utility functions to test cache.
-*
-* - I/O test: The Xil_testio.h file contains endian related memory IO functions. A
-* subset of the memory tests can be selected or all of the tests can be run in order.
-* If there is an error detected by a subtest, the test stops and the failure code is
-* returned. Further tests are not run even if all of the tests are selected.
-*
-* - Memory test: The xil_testmem.h file contains utility functions to test memory.
-* A subset of the memory tests can be selected or all of the tests can be run
-* in order. If there is an error detected by a subtest, the test stops and the
-* failure code is returned. Further tests are not run even if all of the tests are selected.
-*
-*
-* Following list describes the supported memory tests:
-*
-* - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
-*
-* - XIL_TESTMEM_INCREMENT: This test
-* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
-* test value for memory.
-*
-* - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
-* uses a walking '1' as the test value for memory.
-* @code
-* location 1 = 0x00000001
-* location 2 = 0x00000002
-* ...
-* @endcode
-*
-* - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
-* This test uses the inverse value of the walking ones test
-* as the test value for memory.
-* @code
-* location 1 = 0xFFFFFFFE
-* location 2 = 0xFFFFFFFD
-* ...
-*@endcode
-*
-* - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
-* This test uses the inverse of the address of the location under test
-* as the test value for memory.
-*
-* - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
-* This test uses the provided patters as the test value for memory.
-* If zero is provided as the pattern the test uses '0xDEADBEEF".
-*
-* @warning
-* The tests are DESTRUCTIVE. Run before any initialized memory spaces
-* have been set up.
-* The address provided to the memory tests is not checked for
-* validity except for the NULL case. It is possible to provide a code-space
-* pointer for this test to start with and ultimately destroy executable code
-* causing random failures.
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 08/25/09 First release
-* 7.5 mus 03/10/21 Added new set of Xil_TestMem32, Xil_TestMem16 and
-* Xil_TestMem8 APIs to support memory test for memory
-* regions mapped at extended addresses
-* (addresses > 4 GB). These new set of APIs would be
-* compiled only for 32 bit Microblaze processor, if
-* XPAR_MICROBLAZE_ADDR_SIZE is greater than 32.
-* It fixes CR#1089129.
-*
-;* MODIFICATION HISTORY:
-;*
-;* Ver Who Date Changes
-;* ----- ------- -------- ---------------------------------------------------
-;* 7.3 dp 06/25/20 Initial version for armclang
-;*
-;*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xscuwdt.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/****************************************************************************/
-/**
-*
-* Initialize a specific watchdog timer instance/driver. This function
-* must be called before other functions of the driver are called.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-* @param ConfigPtr is the config structure.
-* @param EffectiveAddress is the base address for the device. It could be
-* a virtual address if address translation is supported in the
-* system, otherwise it is the physical address.
-*
-* @return
-* - XST_SUCCESS if initialization was successful.
-* - XST_DEVICE_IS_STARTED if the device has already been started.
-*
-* @note This function enables the watchdog mode.
-*
-******************************************************************************/
-s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
- XScuWdt_Config *ConfigPtr, u32 EffectiveAddress)
-{
- s32 CfgStatus;
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
- Xil_AssertNonvoid(EffectiveAddress != 0x00U);
-
- /*
- * If the device is started, disallow the initialize and return a
- * status indicating it is started. This allows the user to stop the
- * device and reinitialize, but prevents a user from inadvertently
- * initializing.
- */
- if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
- CfgStatus = (s32)XST_DEVICE_IS_STARTED;
- }
- else {
- /*
- * Copy configuration into instance.
- */
- InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
-
- /*
- * Save the base address pointer such that the registers of the block
- * can be accessed and indicate it has not been started yet.
- */
- InstancePtr->Config.BaseAddr = EffectiveAddress;
- InstancePtr->IsStarted = 0U;
-
- /*
- * Put the watchdog timer in Watchdog mode.
- */
- XScuWdt_SetWdMode(InstancePtr);
-
- /*
- * Indicate the instance is ready to use, successfully initialized.
- */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- CfgStatus =(s32)XST_SUCCESS;
- }
- return CfgStatus;
-}
-
-/****************************************************************************/
-/**
-*
-* Start the watchdog counter of the device.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note User needs to select the appropriate mode (watchdog/timer)
-* before using this API.
-* See XScuWdt_SetWdMode/XScuWdt_SetTimerMode macros in
-* xscuwdt.h.
-*
-******************************************************************************/
-void XScuWdt_Start(XScuWdt *InstancePtr)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the contents of the Control register.
- */
- Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr,
- XSCUWDT_CONTROL_OFFSET);
-
- /*
- * Set the 'watchdog enable' bit in the register.
- */
- Register |= XSCUWDT_CONTROL_WD_ENABLE_MASK;
-
- /*
- * Update the Control register with the new value.
- */
- XScuWdt_WriteReg(InstancePtr->Config.BaseAddr,
- XSCUWDT_CONTROL_OFFSET, Register);
-
- /*
- * Indicate that the device is started.
- */
- InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
-}
-
-/****************************************************************************/
-/**
-*
-* Stop the watchdog timer.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XScuWdt_Stop(XScuWdt *InstancePtr)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the contents of the Control register.
- */
- Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr,
- XSCUWDT_CONTROL_OFFSET);
-
- /*
- * Clear the 'watchdog enable' bit in the register.
- */
- Register &= (~(u32)XSCUWDT_CONTROL_WD_ENABLE_MASK);
-
- /*
- * Update the Control register with the new value.
- */
- XScuWdt_WriteReg(InstancePtr->Config.BaseAddr,
- XSCUWDT_CONTROL_OFFSET, Register);
-
- /*
- * Indicate that the device is stopped.
- */
- InstancePtr->IsStarted = 0U;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/76/608fa8565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/76/608fa8565243001d18b399c1eb9b3628
deleted file mode 100644
index 25f08a2..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/76/608fa8565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,278 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file microblaze_sleep.c
-*
-* Contains implementation of microblaze sleep function.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 4.1 hk 04/18/14 Add sleep function.
-* 6.0 asa 08/15/16 Updated the sleep/usleep signature. Fix for CR#956899.
-* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
-* implementation. Now sleep routines will use Axi Timer
-* or machine cycles as specified by the user.
-* 6.8 mus 10/04/18 FreeRTOS BSP always use default method for sleep
-* implementation, It does not have user configurable sleep
-* implementation support, that is why FreeRTOS tcl does not
-* export XSLEEP_TIMER_IS_DEFAULT_TIMER macro to
-* xparameters.h. Modified code to always use default timer
-* path for FreeRTOS BSP, based on the "FREERTOS_BSP" macro.
-* It fixes CR#1012363.
-* 7.5 dp 01/05/21 Updated COUNTS_PER_U/MSECOND, ITERS_PER_M/USEC macros to
-* round it off to nearest possible value so that delta error
-* in time calculations can be minimized.
-* 7.5 mus 04/21/21 Microblaze frequency can be changed run time. Sleep routines
-* needs to use updated frequency for delay calculation, else
-* sleep calls would result into incorrect behavior. Added
-* Xil_SetMBFrequency API to write updated frequency value to
-* MBFreq variable, and updated ITERS_PER_SEC macro to read
-* frequency value from MBFreq variable, instead of using XPARS.
-* Xil_SetMBFrequency must be called immediately after change
-* in Microblaze frequency run time, it would keep sleep
-* routines in sync with Microblaze frequency.
-* Added Xil_GetMBFrequency to read current Microbalze frequency.
-* It fixes CR#1094568.
-* 7.6 mus 08/23/21 Updated prototypes for functions which are not taking any
-* arguments with void keyword. This has been done to fix
-* compilation warnings with "-Wstrict-prototypes" flag.
-* It fixes CR#1108601
-*
-*
-*
-* @note
-*
-* This file may contain architecture-dependent code.
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "microblaze_sleep.h"
-#include "bspconfig.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#if defined (XSLEEP_TIMER_IS_AXI_TIMER)
-#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY)
-#define COUNTS_PER_MSECOND ((COUNTS_PER_SECOND + 500) / 1000)
-#define COUNTS_PER_USECOND ((COUNTS_PER_SECOND + 500000)/ 1000000)
-#warning "May wait for more than the specified delay"
-#elif defined (XSLEEP_TIMER_IS_DEFAULT_TIMER) || defined (FREERTOS_BSP)
-#define ITERS_PER_SEC (Xil_GetMBFrequency() / 4)
-#define ITERS_PER_MSEC ((ITERS_PER_SEC + 500) / 1000)
-#define ITERS_PER_USEC ((ITERS_PER_MSEC + 500) / 1000)
-#pragma message ("For the sleep routines, assembly instructions are used")
-#endif
-/***************** Variable Definitions *********************/
-#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER) || defined (FREERTOS_BSP)
-/**
- * This variable stores current value of Microblaze frequency.
- * It would be used by sleep routines to generate delay.
- */
-static u32 MBFreq = XPAR_CPU_CORE_CLOCK_FREQ_HZ;
-#endif
-
-/*****************************************************************************/
-
-#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER) || defined (FREERTOS_BSP)
-/*****************************************************************************/
-/**
-* @brief Sets variable which stores Microblaze frequency value
-* @param Val - Frequency value to be set
-* @return XST_SUCCESS - If frequency updated successfully
-* XST_INVALID_PARAM - If specified frequency value is not valid
-*
-* @note It must be called after runtime change in Microblaze frequency,
-* failing to do so would result in to incorrect behavior of sleep
-* routines
-*
-******************************************************************************/
-u32 Xil_SetMBFrequency(u32 Val)
-{
- if ( Val != 0) {
- MBFreq = Val;
- return XST_SUCCESS;
- }
- return XST_INVALID_PARAM;
-}
-
-/*****************************************************************************/
-/**
-* @brief Returns current Microblaze frequency value
-* @return MBFreq - Current Microblaze frequency value
-*
-******************************************************************************/
-u32 Xil_GetMBFrequency(void)
-{
- return MBFreq;
-}
-
-static void sleep_common(u32 n, u32 iters)
-{
- asm volatile (
- "1: \n\t"
- "addik %1, %1, -1 \n\t"
- "add r7, r0, %0 \n\t"
- "2: \n\t"
- "addik r7, r7, -1 \n\t"
- "bneid r7, 2b \n\t"
- "or r0, r0, r0 \n\t"
- "bneid %1, 1b \n\t"
- "or r0, r0, r0 \n\t"
- :
- : "r"(iters), "r"(n)
- );
-}
-#endif
-
-/*****************************************************************************/
-/**
-* @brief Provides delay for requested duration.
-* @param useconds- time in useconds.
-* @return 0
-*
-* @note Instruction cache should be enabled for this to work.
-*
-******************************************************************************/
-int usleep_MB(unsigned long useconds)
-{
-#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER) || defined (FREERTOS_BSP)
- sleep_common((u32)useconds, ITERS_PER_USEC);
-#elif defined (XSLEEP_TIMER_IS_AXI_TIMER)
- /* Start Axi timer */
- XTime_StartAxiTimer();
- Xil_SleepAxiTimer(useconds, COUNTS_PER_USECOND);
-#endif
-
- return 0;
-}
-
-/*****************************************************************************/
-/**
-* @brief Provides delay for requested duration.
-* @param seconds- time in useconds.
-* @return 0
-*
-* @note Instruction cache should be enabled for this to work.
-*
-******************************************************************************/
-unsigned sleep_MB(unsigned int seconds)
-{
-#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER) || defined (FREERTOS_BSP)
- sleep_common(seconds, ITERS_PER_SEC);
-#elif defined (XSLEEP_TIMER_IS_AXI_TIMER)
- /* Start Axi timer */
- XTime_StartAxiTimer();
- Xil_SleepAxiTimer(seconds, COUNTS_PER_SECOND);
-#endif
-
- return 0;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Provides delay for requested duration..
-*
-* @param MilliSeconds- Delay time in milliseconds.
-*
-* @return None.
-*
-* @note Instruction cache should be enabled for this to work.
-*
-******************************************************************************/
-void MB_Sleep(u32 MilliSeconds)
-{
-#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER) || defined (FREERTOS_BSP)
- sleep_common(MilliSeconds, ITERS_PER_MSEC);
-
-#elif defined (XSLEEP_TIMER_IS_AXI_TIMER)
- /* Start Axi timer */
- XTime_StartAxiTimer();
- Xil_SleepAxiTimer(MilliSeconds, COUNTS_PER_MSECOND);
-#endif
-}
-
-/*****************************************************************************/
-/**
- *
- * @brief Provides delay for requested duration by using Axi Timer.
- *
- * @param delay - delay time in seconds/milli seconds/micro seconds.
- * frequency - Number of counts per
- * second/milli second/micro second.
- *
- * @return None.
- *
- *
- ******************************************************************************/
-#if defined (XSLEEP_TIMER_IS_AXI_TIMER)
-static void Xil_SleepAxiTimer(u32 delay, u64 frequency)
-{
- u64 tEnd = 0U;
- u64 tCur = 0U;
- u32 TimeHighVal = 0U;
- u32 TimeLowVal1 = 0U;
- u32 TimeLowVal2 = 0U;
-
- TimeLowVal1 = Xil_In32((SLEEP_TIMER_BASEADDR) +
- (XSLEEP_TIMER_AXITIMER_TCR_OFFSET));
- tEnd = (u64)TimeLowVal1 + ((u64)(delay) * frequency);
- do
- {
- TimeLowVal2 = Xil_In32((SLEEP_TIMER_BASEADDR) +
- (XSLEEP_TIMER_AXITIMER_TCR_OFFSET));
- if (TimeLowVal2 < TimeLowVal1) {
- TimeHighVal++;
- }
- TimeLowVal1 = TimeLowVal2;
- tCur = (((u64) TimeHighVal) << 32U) | (u64)TimeLowVal2;
- }while (tCur < tEnd);
-}
-
-/*****************************************************************************/
-/**
- *
- * @brief This API starts the Axi Timer only when the timer is not enabled.
- *
- * @param None.
- *
- * @return None.
- *
- * @note Instruction cache should be enabled for this to work.
- *
- ******************************************************************************/
- static void XTime_StartAxiTimer(void)
- {
- u32 ControlStatusReg;
-
- /* Checking if the timer is enabled */
- if(Xil_In32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_AXITIMER_TCSR0_OFFSET) &&
- XSLEEP_TIMER_AXITIMER_CSR_ENABLE_TMR_MASK)
- {
- return;
- }
- /*
- * Read the current register contents such that only the necessary bits
- * of the register are modified in the following operations
- */
- ControlStatusReg = Xil_In32(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_AXITIMER_TCSR0_OFFSET);
- /*
- * Remove the reset condition such that the timer counter starts running
- * with the value loaded from the compare register
- */
- Xil_Out32((SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_AXITIMER_TCSR0_OFFSET),
- (ControlStatusReg | XSLEEP_TIMER_AXITIMER_CSR_ENABLE_TMR_MASK |
- XSLEEP_TIMER_AXITIMER_CSR_AUTO_RELOAD_MASK));
- }
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/76/b02396575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/76/b02396575243001d18b399c1eb9b3628
deleted file mode 100644
index a3d5ae4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/76/b02396575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,399 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xqspips_hw.h
-* @addtogroup qspips_v3_9
-* @{
-*
-* This header file contains the identifiers and basic HW access driver
-* functions (or macros) that can be used to access the device. Other driver
-* functions are defined in xqspips.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00 sdm 11/25/10 First release
-* 2.00a ka 07/25/12 Added a few register defines for CR 670297
-* and removed some defines of reserved fields for
-* CR 671468
-* Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
-* bit in Configuration register.
-* 2.01a sg 02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
-* which need write to clear. Removed Read zeros mask from
-* LQSPI Config register.
-* 2.03a hk 08/22/13 Added prototypes of API's for QSPI reset and
-* linear mode initialization for boot. Added related
-* constant definitions.
-* 3.1 hk 08/13/14 Changed definition of CR reset value masks to set/reset
-* required bits leaving reserved bits untouched. CR# 796813.
-* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
-* controller does not update FIFO status flags as expected
-* when thresholds are used.
-* 3.6 akm 03/28/19 Fixed memory leak issue while reading from qspi.(CR#1016357)
-*
-*
-*
-******************************************************************************/
-#ifndef XQSPIPS_HW_H /* prevent circular inclusions */
-#define XQSPIPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets from the base address of an QSPI device.
- * @{
- */
-#define XQSPIPS_CR_OFFSET 0x00 /**< Configuration Register */
-#define XQSPIPS_SR_OFFSET 0x04 /**< Interrupt Status */
-#define XQSPIPS_IER_OFFSET 0x08 /**< Interrupt Enable */
-#define XQSPIPS_IDR_OFFSET 0x0c /**< Interrupt Disable */
-#define XQSPIPS_IMR_OFFSET 0x10 /**< Interrupt Enabled Mask */
-#define XQSPIPS_ER_OFFSET 0x14 /**< Enable/Disable Register */
-#define XQSPIPS_DR_OFFSET 0x18 /**< Delay Register */
-#define XQSPIPS_TXD_00_OFFSET 0x1C /**< Transmit 4-byte inst/data */
-#define XQSPIPS_RXD_OFFSET 0x20 /**< Data Receive Register */
-#define XQSPIPS_SICR_OFFSET 0x24 /**< Slave Idle Count */
-#define XQSPIPS_TXWR_OFFSET 0x28 /**< Transmit FIFO Watermark */
-#define XQSPIPS_RXWR_OFFSET 0x2C /**< Receive FIFO Watermark */
-#define XQSPIPS_GPIO_OFFSET 0x30 /**< GPIO Register */
-#define XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38 /**< Loopback Delay Adjust Reg */
-#define XQSPIPS_TXD_01_OFFSET 0x80 /**< Transmit 1-byte inst */
-#define XQSPIPS_TXD_10_OFFSET 0x84 /**< Transmit 2-byte inst */
-#define XQSPIPS_TXD_11_OFFSET 0x88 /**< Transmit 3-byte inst */
-#define XQSPIPS_LQSPI_CR_OFFSET 0xA0 /**< Linear QSPI config register */
-#define XQSPIPS_LQSPI_SR_OFFSET 0xA4 /**< Linear QSPI status register */
-#define XQSPIPS_MOD_ID_OFFSET 0xFC /**< Module ID register */
-
-/* @} */
-
-/** @name Configuration Register
- *
- * This register contains various control bits that
- * affect the operation of the QSPI device. Read/Write.
- * @{
- */
-
-#define XQSPIPS_CR_IFMODE_MASK 0x80000000 /**< Flash mem interface mode */
-#define XQSPIPS_CR_ENDIAN_MASK 0x04000000 /**< Tx/Rx FIFO endianness */
-#define XQSPIPS_CR_MANSTRT_MASK 0x00010000 /**< Manual Transmission Start */
-#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start
- Enable */
-#define XQSPIPS_CR_SSFORCE_MASK 0x00004000 /**< Force Slave Select */
-#define XQSPIPS_CR_SSCTRL_MASK 0x00000400 /**< Slave Select Decode */
-#define XQSPIPS_CR_SSCTRL_SHIFT 10 /**< Slave Select Decode shift */
-#define XQSPIPS_CR_DATA_SZ_MASK 0x000000C0 /**< Size of word to be
- transferred */
-#define XQSPIPS_CR_PRESC_MASK 0x00000038 /**< Prescaler Setting */
-#define XQSPIPS_CR_PRESC_SHIFT 3 /**< Prescaler shift */
-#define XQSPIPS_CR_PRESC_MAXIMUM 0x07 /**< Prescaler maximum value */
-
-#define XQSPIPS_CR_CPHA_MASK 0x00000004 /**< Phase Configuration */
-#define XQSPIPS_CR_CPOL_MASK 0x00000002 /**< Polarity Configuration */
-
-#define XQSPIPS_CR_MSTREN_MASK 0x00000001 /**< Master Mode Enable */
-
-#define XQSPIPS_CR_HOLD_B_MASK 0x00080000 /**< HOLD_B Pin Drive Enable */
-
-#define XQSPIPS_CR_REF_CLK_MASK 0x00000100 /**< Ref clk bit - should be 0 */
-
-/* Deselect the Slave select line and set the transfer size to 32 at reset */
-#define XQSPIPS_CR_RESET_MASK_SET XQSPIPS_CR_IFMODE_MASK | \
- XQSPIPS_CR_SSCTRL_MASK | \
- XQSPIPS_CR_DATA_SZ_MASK | \
- XQSPIPS_CR_MSTREN_MASK | \
- XQSPIPS_CR_SSFORCE_MASK | \
- XQSPIPS_CR_HOLD_B_MASK
-#define XQSPIPS_CR_RESET_MASK_CLR XQSPIPS_CR_CPOL_MASK | \
- XQSPIPS_CR_CPHA_MASK | \
- XQSPIPS_CR_PRESC_MASK | \
- XQSPIPS_CR_MANSTRTEN_MASK | \
- XQSPIPS_CR_MANSTRT_MASK | \
- XQSPIPS_CR_ENDIAN_MASK | \
- XQSPIPS_CR_REF_CLK_MASK
-/* @} */
-
-
-/** @name QSPI Interrupt Registers
- *
- * QSPI Status Register
- *
- * This register holds the interrupt status flags for an QSPI device. Some
- * of the flags are level triggered, which means that they are set as long
- * as the interrupt condition exists. Other flags are edge triggered,
- * which means they are set once the interrupt condition occurs and remain
- * set until they are cleared by software. The interrupts are cleared by
- * writing a '1' to the interrupt bit position in the Status Register.
- * Read/Write.
- *
- * QSPI Interrupt Enable Register
- *
- * This register is used to enable chosen interrupts for an QSPI device.
- * Writing a '1' to a bit in this register sets the corresponding bit in the
- * QSPI Interrupt Mask register. Write only.
- *
- * QSPI Interrupt Disable Register
- *
- * This register is used to disable chosen interrupts for an QSPI device.
- * Writing a '1' to a bit in this register clears the corresponding bit in the
- * QSPI Interrupt Mask register. Write only.
- *
- * QSPI Interrupt Mask Register
- *
- * This register shows the enabled/disabled interrupts of an QSPI device.
- * Read only.
- *
- * All four registers have the same bit definitions. They are only defined once
- * for each of the Interrupt Enable Register, Interrupt Disable Register,
- * Interrupt Mask Register, and Channel Interrupt Status Register
- * @{
- */
-
-#define XQSPIPS_IXR_TXUF_MASK 0x00000040 /**< QSPI Tx FIFO Underflow */
-#define XQSPIPS_IXR_RXFULL_MASK 0x00000020 /**< QSPI Rx FIFO Full */
-#define XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010 /**< QSPI Rx FIFO Not Empty */
-#define XQSPIPS_IXR_TXFULL_MASK 0x00000008 /**< QSPI Tx FIFO Full */
-#define XQSPIPS_IXR_TXOW_MASK 0x00000004 /**< QSPI Tx FIFO Overwater */
-#define XQSPIPS_IXR_RXOVR_MASK 0x00000001 /**< QSPI Rx FIFO Overrun */
-#define XQSPIPS_IXR_DFLT_MASK 0x00000025 /**< QSPI default interrupts
- mask */
-#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041 /**< Interrupts which
- need write to clear */
-#define XQSPIPS_ISR_RESET_STATE 0x00000004 /**< Default to tx/rx empty */
-#define XQSPIPS_IXR_DISABLE_ALL 0x0000007D /**< Disable all interrupts */
-/* @} */
-
-
-/** @name Enable Register
- *
- * This register is used to enable or disable an QSPI device.
- * Read/Write
- * @{
- */
-#define XQSPIPS_ER_ENABLE_MASK 0x00000001 /**< QSPI Enable Bit Mask */
-/* @} */
-
-
-/** @name Delay Register
- *
- * This register is used to program timing delays in
- * slave mode. Read/Write
- * @{
- */
-#define XQSPIPS_DR_NSS_MASK 0xFF000000 /**< Delay to de-assert slave select
- between two words mask */
-#define XQSPIPS_DR_NSS_SHIFT 24 /**< Delay to de-assert slave select
- between two words shift */
-#define XQSPIPS_DR_BTWN_MASK 0x00FF0000 /**< Delay Between Transfers
- mask */
-#define XQSPIPS_DR_BTWN_SHIFT 16 /**< Delay Between Transfers shift */
-#define XQSPIPS_DR_AFTER_MASK 0x0000FF00 /**< Delay After Transfers mask */
-#define XQSPIPS_DR_AFTER_SHIFT 8 /**< Delay After Transfers shift */
-#define XQSPIPS_DR_INIT_MASK 0x000000FF /**< Delay Initially mask */
-/* @} */
-
-/** @name Slave Idle Count Registers
- *
- * This register defines the number of pclk cycles the slave waits for a the
- * QSPI clock to become stable in quiescent state before it can detect the start
- * of the next transfer in CPHA = 1 mode.
- * Read/Write
- *
- * @{
- */
-#define XQSPIPS_SICR_MASK 0x000000FF /**< Slave Idle Count Mask */
-/* @} */
-
-
-/** @name Transmit FIFO Watermark Register
- *
- * This register defines the watermark setting for the Transmit FIFO.
- *
- * @{
- */
-#define XQSPIPS_TXWR_MASK 0x0000003F /**< Transmit Watermark Mask */
-#define XQSPIPS_TXWR_RESET_VALUE 0x00000001 /**< Transmit Watermark
- * register reset value */
-
-/* @} */
-
-/** @name Receive FIFO Watermark Register
- *
- * This register defines the watermark setting for the Receive FIFO.
- *
- * @{
- */
-#define XQSPIPS_RXWR_MASK 0x0000003F /**< Receive Watermark Mask */
-#define XQSPIPS_RXWR_RESET_VALUE 0x00000001 /**< Receive Watermark
- * register reset value */
-
-/* @} */
-
-/** @name FIFO Depth
- *
- * This macro provides the depth of transmit FIFO and receive FIFO.
- *
- * @{
- */
-#define XQSPIPS_FIFO_DEPTH 63 /**< FIFO depth (words) */
-/* @} */
-
-
-/** @name Linear QSPI Configuration Register
- *
- * This register contains various control bits that
- * affect the operation of the Linear QSPI controller. Read/Write.
- *
- * @{
- */
-#define XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */
-#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */
-#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Separate memory bus */
-#define XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */
-#define XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */
-#define XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */
-#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O
- or quad I/O */
-#define XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700 /**< Number of dummy bytes
- between addr and return
- read data */
-#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */
-#define XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B /**< Default CR value */
-/* @} */
-
-/** @name Linear QSPI Status Register
- *
- * This register contains various status bits of the Linear QSPI controller.
- * Read/Write.
- *
- * @{
- */
-#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004 /**< AXI Data FSM Error
- received */
-#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002 /**< AXI write command
- received */
-/* @} */
-
-
-/** @name Loopback Delay Adjust Register
- *
- * This register contains various bit masks of Loopback Delay Adjust Register.
- *
- * @{
- */
-
-#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */
-
-/* @} */
-
-
-/** @name SLCR Register
- *
- * Register offsets from SLCR base address.
- *
- * @{
- */
-
-#define SLCR_LOCK 0x00000004 /**< SLCR Write Protection Lock */
-#define SLCR_UNLOCK 0x00000008 /**< SLCR Write Protection Unlock */
-#define LQSPI_RST_CTRL 0x00000230 /**< Quad SPI Software Reset Control */
-#define SLCR_LOCKSTA 0x0000000C /**< SLCR Write Protection status */
-
-/* @} */
-
-
-/** @name SLCR Register
- *
- * Bit Masks of above SLCR Registers .
- *
- * @{
- */
-
-#ifndef XPAR_XSLCR_0_BASEADDR
-#define XPAR_XSLCR_0_BASEADDR 0xF8000000
-#endif
-#define SLCR_LOCK_MASK 0x767B /**< Write Protection Lock mask*/
-#define SLCR_UNLOCK_MASK 0xDF0D /**< SLCR Write Protection Unlock */
-#define LQSPI_RST_CTRL_MASK 0x3 /**< Quad SPI Software Reset Control */
-
-/* @} */
-
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XQspiPs_In32 Xil_In32
-#define XQspiPs_Out32 Xil_Out32
-#define XQSPIPS_DUMMY_TX_DATA 0xFFFFFFFF
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-#define XQspiPs_ReadReg(BaseAddress, RegOffset) \
- XQspiPs_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u32 RegisterValue)
-*
-******************************************************************************/
-#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Functions implemented in xqspips_hw.c
- */
-void XQspiPs_ResetHw(u32 BaseAddress);
-void XQspiPs_LinearInit(u32 BaseAddress);
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/76/b09589565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/76/b09589565243001d18b399c1eb9b3628
deleted file mode 100644
index 0da9fd9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/76/b09589565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,40 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-* File : microblaze_enable_dcache.s
-* Date : 2002, March 20.
-* Company: Xilinx
-* Group : Emerging Software Technologies
-*
-* Summary:
-* Enable L1 dcache on the microblaze.
-*
-*
-******************************************************************************/
-
-#include "xparameters.h"
-
- .text
- .globl microblaze_enable_dcache
- .ent microblaze_enable_dcache
- .align 2
-microblaze_enable_dcache:
-
-#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
- rtsd r15, 8
- msrset r0, 0x80
-#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- #Read the MSR register
- mfs r8, rmsr
- #Set the interrupt enable bit
- ori r8, r8, 0x80
- #Save the MSR register
- mts rmsr, r8
- #Return
- rtsd r15, 8
- nop
-#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- .end microblaze_enable_dcache
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/77/217695595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/77/217695595243001d18b399c1eb9b3628
deleted file mode 100644
index e3e7962..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/77/217695595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,95 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/* write.c -- write bytes to an output device.
- */
-#ifndef UNDEFINE_FILE_OPS
-#include "xil_printf.h"
-#include "xparameters.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) sint32 _write (sint32 fd, char8* buf, sint32 nbytes);
-}
-#endif
-
-/*
- * write -- write bytes to the serial port. Ignore fd, since
- * stdout and stderr are the same. Since we have no filesystem,
- * open will only return an error.
- */
-__attribute__((weak)) sint32
-write (sint32 fd, char8* buf, sint32 nbytes)
-
-{
-#ifdef STDOUT_BASEADDRESS
- s32 i;
- char8* LocalBuf = buf;
-
- (void)fd;
- for (i = 0; i < nbytes; i++) {
- if(LocalBuf != NULL) {
- LocalBuf += i;
- }
- if(LocalBuf != NULL) {
- if (*LocalBuf == '\n') {
- outbyte ('\r');
- }
- outbyte (*LocalBuf);
- }
- if(LocalBuf != NULL) {
- LocalBuf -= i;
- }
- }
- return (nbytes);
-#else
- (void)fd;
- (void)buf;
- (void)nbytes;
- return 0;
-#endif
-}
-
-__attribute__((weak)) sint32
-_write (sint32 fd, char8* buf, sint32 nbytes)
-{
-#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
- sint32 length;
-
- (void)fd;
- (void)nbytes;
- length = XPVXenConsole_Write(buf);
- return length;
-#else
-#ifdef STDOUT_BASEADDRESS
- s32 i;
- char8* LocalBuf = buf;
-
- (void)fd;
- for (i = 0; i < nbytes; i++) {
- if(LocalBuf != NULL) {
- LocalBuf += i;
- }
- if(LocalBuf != NULL) {
- if (*LocalBuf == '\n') {
- outbyte ('\r');
- }
- outbyte (*LocalBuf);
- }
- if(LocalBuf != NULL) {
- LocalBuf -= i;
- }
- }
- return (nbytes);
-#else
- (void)fd;
- (void)buf;
- (void)nbytes;
- return 0;
-#endif
-#endif
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/77/4023ad565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/77/4023ad565243001d18b399c1eb9b3628
deleted file mode 100644
index a84c6a4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/77/4023ad565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,68 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2006 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file pvr.c
-*
-* This header file contains defines for structures used by the microblaze
-* PVR routines
-*
-******************************************************************************/
-#include "xparameters.h"
-#include "pvr.h"
-#include
-
-/* Definitions */
-
-/****************************************************************************/
-/**
-* @brief Populate the PVR data structure to which pvr points, with the
-* values of the hardware PVR registers.
-*
-* @param pvr- address of PVR data structure to be populated
-*
-* @return 0 - SUCCESS
-* -1 - FAILURE
-*
-****************************************************************************/
-int microblaze_get_pvr (pvr_t *pvr)
-{
- if (!pvr)
- return -1;
-
- bzero ((void*)pvr, sizeof (pvr_t));
-
-#ifdef MICROBLAZE_PVR_NONE
- return -1;
-#else
- getpvr (0, pvr->pvr[0]);
-#endif /* MICROBLAZE_PVR_NONE */
-
-#ifdef MICROBLAZE_PVR_FULL
- getpvr (1, pvr->pvr[1]);
- getpvr (2, pvr->pvr[2]);
- getpvr (3, pvr->pvr[3]);
-
- getpvr (4, pvr->pvr[4]);
- getpvr (5, pvr->pvr[5]);
- getpvr (6, pvr->pvr[6]);
- getpvr (7, pvr->pvr[7]);
-
- getpvr (8, pvr->pvr[8]);
- getpvr (9, pvr->pvr[9]);
- getpvr (10, pvr->pvr[10]);
- getpvr (11, pvr->pvr[11]);
-
-/* getpvr (12, pvr->pvr[12]); */
-/* getpvr (13, pvr->pvr[13]); */
-/* getpvr (14, pvr->pvr[14]); */
-/* getpvr (15, pvr->pvr[15]); */
-
-#endif /* MICROBLAZE_PVR_FULL */
-
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/77/d1abaa595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/77/d1abaa595243001d18b399c1eb9b3628
deleted file mode 100644
index c52d476..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/77/d1abaa595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,447 +0,0 @@
-/******************************************************************************
-* Copyright (c) 1995 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-*******************************************************************************/
-/*---------------------------------------------------*/
-/* Modified from : */
-/* Public Domain version of printf */
-/* Rud Merriam, Compsult, Inc. Houston, Tx. */
-/* For Embedded Systems Programming, 1991 */
-/* */
-/*---------------------------------------------------*/
-#include "xil_printf.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include
-#include
-#include
-
-static void padding( const s32 l_flag,const struct params_s *par);
-static void outs(const charptr lp, struct params_s *par);
-static s32 getnum( charptr* linep);
-
-typedef struct params_s {
- s32 len;
- s32 num1;
- s32 num2;
- char8 pad_character;
- s32 do_padding;
- s32 left_flag;
- s32 unsigned_flag;
-} params_t;
-
-
-/*---------------------------------------------------*/
-/* The purpose of this routine is to output data the */
-/* same as the standard printf function without the */
-/* overhead most run-time libraries involve. Usually */
-/* the printf brings in many kilobytes of code and */
-/* that is unacceptable in most embedded systems. */
-/*---------------------------------------------------*/
-
-
-/*---------------------------------------------------*/
-/* */
-/* This routine puts pad characters into the output */
-/* buffer. */
-/* */
-static void padding( const s32 l_flag, const struct params_s *par)
-{
- s32 i;
-
- if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) {
- i=(par->len);
- for (; i<(par->num1); i++) {
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( par->pad_character);
-#endif
- }
- }
-}
-
-/*---------------------------------------------------*/
-/* */
-/* This routine moves a string to the output buffer */
-/* as directed by the padding and positioning flags. */
-/* */
-static void outs(const charptr lp, struct params_s *par)
-{
- charptr LocalPtr;
- LocalPtr = lp;
- /* pad on left if needed */
- if(LocalPtr != NULL) {
- par->len = (s32)strlen( LocalPtr);
- padding( !(par->left_flag), par);
- /* Move string to the buffer */
- while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) {
- (par->num2)--;
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte(*LocalPtr);
-#endif
- LocalPtr += 1;
- }
-}
-
- /* Pad on right if needed */
- /* CR 439175 - elided next stmt. Seemed bogus. */
- /* par->len = strlen( lp) */
- padding( par->left_flag, par);
-}
-
-/*---------------------------------------------------*/
-/* */
-/* This routine moves a number to the output buffer */
-/* as directed by the padding and positioning flags. */
-/* */
-
-static void outnum( const s32 n, const s32 base, struct params_s *par)
-{
- s32 negative;
- s32 i;
- char8 outbuf[32];
- const char8 digits[] = "0123456789ABCDEF";
- u32 num;
- for(i = 0; i<32; i++) {
- outbuf[i] = '0';
- }
-
- /* Check if number is negative */
- if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
- negative = 1;
- num =(-(n));
- }
- else{
- num = n;
- negative = 0;
- }
-
- /* Build number (backwards) in outbuf */
- i = 0;
- do {
- outbuf[i] = digits[(num % base)];
- i++;
- num /= base;
- } while (num > 0);
-
- if (negative != 0) {
- outbuf[i] = '-';
- i++;
- }
-
- outbuf[i] = '\0';
- i--;
-
- /* Move the converted number to the buffer and */
- /* add in the padding where needed. */
- par->len = (s32)strlen(outbuf);
- padding( !(par->left_flag), par);
- while (&outbuf[i] >= outbuf) {
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( outbuf[i] );
-#endif
- i--;
-}
- padding( par->left_flag, par);
-}
-/*---------------------------------------------------*/
-/* */
-/* This routine moves a 64-bit number to the output */
-/* buffer as directed by the padding and positioning */
-/* flags. */
-/* */
-#if defined (__aarch64__) || defined (__arch64__)
-static void outnum1( const s64 n, const s32 base, params_t *par)
-{
- s32 negative;
- s32 i;
- char8 outbuf[64];
- const char8 digits[] = "0123456789ABCDEF";
- u64 num;
- for(i = 0; i<64; i++) {
- outbuf[i] = '0';
- }
-
- /* Check if number is negative */
- if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
- negative = 1;
- num =(-(n));
- }
- else{
- num = (n);
- negative = 0;
- }
-
- /* Build number (backwards) in outbuf */
- i = 0;
- do {
- outbuf[i] = digits[(num % base)];
- i++;
- num /= base;
- } while (num > 0);
-
- if (negative != 0) {
- outbuf[i] = '-';
- i++;
- }
-
- outbuf[i] = '\0';
- i--;
-
- /* Move the converted number to the buffer and */
- /* add in the padding where needed. */
- par->len = (s32)strlen(outbuf);
- padding( !(par->left_flag), par);
- while (&outbuf[i] >= outbuf) {
- outbyte( outbuf[i] );
- i--;
-}
- padding( par->left_flag, par);
-}
-#endif
-/*---------------------------------------------------*/
-/* */
-/* This routine gets a number from the format */
-/* string. */
-/* */
-static s32 getnum(charptr* linep)
-{
- s32 n = 0;
- s32 ResultIsDigit = 0;
- charptr cptr = *linep;
-
- while (cptr != NULL) {
- ResultIsDigit = isdigit(((s32)*cptr));
- if (ResultIsDigit == 0)
- break;
- n = ((n*10) + (((s32)*cptr) - (s32)'0'));
- cptr += 1;
- }
-
- *linep = ((charptr)(cptr));
- return(n);
-}
-
-/*---------------------------------------------------*/
-/* */
-/* This routine operates just like a printf/sprintf */
-/* routine. It outputs a set of data under the */
-/* control of a formatting string. Not all of the */
-/* standard C format control are supported. The ones */
-/* provided are primarily those needed for embedded */
-/* systems work. Primarily the floating point */
-/* routines are omitted. Other formats could be */
-/* added easily by following the examples shown for */
-/* the supported formats. */
-/* */
-
-/* void esp_printf( const func_ptr f_ptr,
- const charptr ctrl1, ...) */
-#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
-void xil_printf( const char8 *ctrl1, ...){
- XPVXenConsole_Printf(ctrl1);
-}
-#else
-void xil_printf( const char8 *ctrl1, ...)
-{
- va_list argp;
-
- va_start(argp, ctrl1);
-
- xil_vprintf(ctrl1, argp);
-
- va_end(argp);
-}
-#endif
-
-/* This routine is equivalent to vprintf routine */
-void xil_vprintf(const char8 *ctrl1, va_list argp)
-{
- s32 Check;
-#if defined (__aarch64__) || defined (__arch64__)
- s32 long_flag;
-#endif
- s32 dot_flag;
-
- params_t par;
-
- char8 ch;
- char8 *ctrl = (char8 *)ctrl1;
-
- while ((ctrl != NULL) && (*ctrl != (char8)0)) {
-
- /* move format string chars to buffer until a */
- /* format control is found. */
- if (*ctrl != '%') {
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte(*ctrl);
-#endif
- ctrl += 1;
- continue;
- }
-
- /* initialize all the flags for this format. */
- dot_flag = 0;
-#if defined (__aarch64__) || defined (__arch64__)
- long_flag = 0;
-#endif
- par.unsigned_flag = 0;
- par.left_flag = 0;
- par.do_padding = 0;
- par.pad_character = ' ';
- par.num2=32767;
- par.num1=0;
- par.len=0;
-
- try_next:
- if(ctrl != NULL) {
- ctrl += 1;
- }
- if(ctrl != NULL) {
- ch = *ctrl;
- } else {
- break;
- }
-
- if (isdigit((s32)ch) != 0) {
- if (dot_flag != 0) {
- par.num2 = getnum(&ctrl);
- }
- else {
- if (ch == '0') {
- par.pad_character = '0';
- }
- if(ctrl != NULL) {
- par.num1 = getnum(&ctrl);
- }
- par.do_padding = 1;
- }
- if(ctrl != NULL) {
- ctrl -= 1;
- }
- goto try_next;
- }
-
- switch (tolower((s32)ch)) {
- case '%':
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( '%');
-#endif
- Check = 1;
- break;
-
- case '-':
- par.left_flag = 1;
- Check = 0;
- break;
-
- case '.':
- dot_flag = 1;
- Check = 0;
- break;
-
- case 'l':
- #if defined (__aarch64__) || defined (__arch64__)
- long_flag = 1;
- #endif
- Check = 0;
- break;
-
- case 'u':
- par.unsigned_flag = 1;
- /* fall through */
- case 'i':
- case 'd':
- #if defined (__aarch64__) || defined (__arch64__)
- if (long_flag != 0){
- outnum1((s64)va_arg(argp, s64), 10L, &par);
- }
- else {
- outnum( va_arg(argp, s32), 10L, &par);
- }
- #else
- outnum( va_arg(argp, s32), 10L, &par);
- #endif
- Check = 1;
- break;
- case 'p':
- #if defined (__aarch64__) || defined (__arch64__)
- par.unsigned_flag = 1;
- outnum1((s64)va_arg(argp, s64), 16L, &par);
- Check = 1;
- break;
- #endif
- case 'X':
- case 'x':
- par.unsigned_flag = 1;
- #if defined (__aarch64__) || defined (__arch64__)
- if (long_flag != 0) {
- outnum1((s64)va_arg(argp, s64), 16L, &par);
- }
- else {
- outnum((s32)va_arg(argp, s32), 16L, &par);
- }
- #else
- outnum((s32)va_arg(argp, s32), 16L, &par);
- #endif
- Check = 1;
- break;
-
- case 's':
- outs( va_arg( argp, char *), &par);
- Check = 1;
- break;
-
- case 'c':
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( va_arg( argp, s32));
-#endif
- Check = 1;
- break;
-
- case '\\':
- switch (*ctrl) {
- case 'a':
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( ((char8)0x07));
-#endif
- break;
- case 'h':
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( ((char8)0x08));
-#endif
- break;
- case 'r':
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( ((char8)0x0D));
-#endif
- break;
- case 'n':
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( ((char8)0x0D));
- outbyte( ((char8)0x0A));
-#endif
- break;
- default:
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( *ctrl);
-#endif
- break;
- }
- ctrl += 1;
- Check = 0;
- break;
-
- default:
- Check = 1;
- break;
- }
- if(Check == 1) {
- if(ctrl != NULL) {
- ctrl += 1;
- }
- continue;
- }
- goto try_next;
- }
-}
-/*---------------------------------------------------*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/78/7075aa545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/78/7075aa545243001d18b399c1eb9b3628
deleted file mode 100644
index 5feeb49..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/78/7075aa545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,39 +0,0 @@
-DRIVER_LIB_VERSION = 1.0
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I$(INCLUDEDIR)
-
-SRCFILES:=$(wildcard *.c)
-
-OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
-
-libs: $(OBJECTS)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf $(DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/78/708cbb545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/78/708cbb545243001d18b399c1eb9b3628
deleted file mode 100644
index 363949b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/78/708cbb545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,240 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xgpiops_hw.c
-* @addtogroup gpiops_v3_9
-* @{
-*
-* This file contains low level GPIO functions.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.02a hk 08/22/13 First Release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
-* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
-* in safety mode and modified the code such as
-* Use of mixed mode arithmetic,Declared the pointer param
-* as Pointer to const,Casting operation to a pointer,
-* Literal value requires a U suffix.
-* 3.5 sne 03/14/19 Added versal support.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 4.1 asa 04/18/14 Add sleep function - first release.
-* 6.6 srm 10/18/17 Added the Register offset definitions and Control/Status
-* Register bit masks of the Axi timer.
-* 7.5 mus 04/21/21 Microblaze frequency can be changed run time. Sleep routines
-* needs to use updated frequency for delay calculation, else
-* sleep calls would result into incorrect behavior. Added
-* Xil_SetMBFrequency API to write updated frequency value to
-* MBFreq variable, and updated ITERS_PER_SEC macro to read
-* frequency value from MBFreq variable, instead of using XPARS.
-* Xil_SetMBFrequency must be called immediately after change
-* in Microblaze frequency run time, it would keep sleep
-* routines in sync with Microblaze frequency.
-* Added Xil_GetMBFrequency to read current Microbalze frequency.
-* It fixes CR#1094568.
-* 7.6 mus 08/23/21 Updated prototypes for functions which are not taking any
-* arguments with void keyword. This has been done to fix
-* compilation warnings with "-Wstrict-prototypes" flag.
-* It fixes CR#1108601.
-*
-*
-*
-* @note
-* The microblaze_sleep.h file may contain architecture-dependent items.
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-#ifndef MICROBLAZE_SLEEP_H /* prevent circular inclusions */
-#define MICROBLAZE_SLEEP_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "mb_interface.h"
-#include "xparameters.h"
-#include "sleep.h"
-
-/************************** Constant Definitions *****************************/
-
-#if defined (XSLEEP_TIMER_IS_AXI_TIMER)
-
-/** @name Register Offset Definitions
- * Register offsets within the Axi timer counter, there are multiple
- * timer counters within a single device
- * @{
- */
-#define XSLEEP_TIMER_AXITIMER_TCSR0_OFFSET 0U /**< Control/Status register */
-#define XSLEEP_TIMER_AXITIMER_TLR_OFFSET 4U /**< Load register */
-#define XSLEEP_TIMER_AXITIMER_TCR_OFFSET 8U /**< Timer counter register */
-/* @} */
-
-/** @name Control Status Register Bit Definitions
- * Control Status Register bit masks
- * Used to configure the Axi timer counter device.
- * @{
- */
-#define XSLEEP_TIMER_AXITIMER_CSR_ENABLE_TMR_MASK 0x00000080U
- /**< Enables only the specific timer */
-#define XSLEEP_TIMER_AXITIMER_CSR_AUTO_RELOAD_MASK 0x00000010U
- /**< In compare mode, configures the timer
- * counter to reload from the Load Register.
- * The default mode causes the timer counter
- * to hold when the compare value is hit. In
- * capture mode, configures the timer counter
- * to not hold the previous capture value if
- * a new event occurs. The default mode cause
- * the timer counter to hold the capture value
- * until recognized.*/
-#define XSLEEP_TIMER_AXITIMER_CSR_LOAD_MASK 0x00000020U
- /**< Loads the timer using the load value
- * provided earlier in the Load Register,
- * XSLEEP_TIMER_AXITIMER_TLR_OFFSET. */
-#define XSLEEP_TIMER_AXITIMER_CSR_INT_OCCURED_MASK 0x00000100U
- /**< If bit is set, an interrupt has occurred.
- * If set and '1' is written to this bit
- * position, bit is cleared.*/
-#define XSLEEP_TIMER_AXITIMER_CSR_ENABLE_TMR_MASK 0x00000080U
- /**< Enables only the specific timer */
-/* @} */
-
-/**************************** Type Definitions *******************************/
-/************************** Function Prototypes ******************************/
-
-static void Xil_SleepAxiTimer(u32 delay, u64 frequency);
-static void XTime_StartAxiTimer(void);
-#else
-u32 Xil_SetMBFrequency(u32 Val);
-u32 Xil_GetMBFrequency(void);
-#endif
-/**
- *@endcond
- */
-void MB_Sleep(u32 MilliSeconds) __attribute__((__deprecated__));
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup microblaze_sleep_routines".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/78/70aab6545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/78/70aab6545243001d18b399c1eb9b3628
deleted file mode 100644
index fd7f472..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/78/70aab6545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,273 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xgpiops.h
-* @addtogroup gpiops_v3_9
-* @{
-* @details
-*
-* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
-* Controller.
-*
-* The GPIO Controller supports the following features:
-* - 4 banks
-* - Masked writes (There are no masked reads)
-* - Bypass mode
-* - Configurable Interrupts (Level/Edge)
-*
-* This driver is intended to be RTOS and processor independent. Any needs for
-* dynamic memory management, threads or thread mutual exclusion, virtual
-* memory, or cache control must be satisfied by the layer above this driver.
-
-* This driver supports all the features listed above, if applicable.
-*
-* Driver Description
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate to the GPIO.
-*
-* Interrupts
-*
-* The driver provides interrupt management functions and an interrupt handler.
-* Users of this driver need to provide callback functions. An interrupt handler
-* example is available with the driver.
-*
-* Threads
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* Asserts
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* Building the driver
-*
-* The XGpioPs driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sv 01/15/10 First Release
-* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
-* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
-* relevant to Zynq device.The interrupts are disabled
-* for output pins on all banks during initialization.
-* 1.02a hk 08/22/13 Added low level reset API
-* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
-* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
-* passed to APIs. CR# 822636
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/05/17 Added tabspace for return statements in functions of
-* gpiops examples for proper documentation while
-* generating doxygen.
-* 3.3 ms 04/17/17 Added notes about gpio input and output pin description
-* for zcu102 and zc702 boards in polled and interrupt
-* example, configured Interrupt pin to input pin for
-* proper functioning of interrupt example.
-* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
-* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
-* in safety mode and modified the code such as
-* Use of mixed mode arithmetic,Declared the pointer param
-* as Pointer to const,Casting operation to a pointer,
-* Literal value requires a U suffix.
-* 3.5 sne 03/14/19 Added Versal support.
-* 3.6 mus 04/05/19 Replaced XPLAT_versal macro with XPLAT_VERSAL, to be in
-* sync with standalone BSP
-* 3.6 sne 06/12/19 Fixed IAR compiler warning.
-* 3.6 sne 08/14/19 Added interrupt handler support on versal.
-* 3.7 sne 12/04/19 Reverted versal examples support.
-* 3.8 sne 08/28/20 Modify Makefile to support parallel make execution.
-* 3.8 sne 09/17/20 Added description for Versal PS and PMC GPIO pins.
-* 3.9 sne 03/15/21 Fixed MISRA-C violations.
-*
-*
-*
-******************************************************************************/
-#ifndef XGPIOPS_H /* prevent circular inclusions */
-#define XGPIOPS_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xgpiops_hw.h"
-#include "xplatform_info.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Interrupt types
- * @{
- * The following constants define the interrupt types that can be set for each
- * GPIO pin.
- */
-#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */
-#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */
-#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */
-#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */
-#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
-/** @}*/
-
-#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
-#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
-#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
-#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
-#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
-
-#ifdef XPAR_PSU_GPIO_0_BASEADDR
-#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */
-#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */
-#endif
-
-#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a
- * Zynq Ultrascale+ MP GPIO device
- */
-#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
-
-#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
- * Zynq Ultrascale+ MP GPIO device
- * 0 - 25, Bank 0
- * 26 - 51, Bank 1
- * 52 - 77, Bank 2
- * 78 - 109, Bank 3
- * 110 - 141, Bank 4
- * 142 - 173, Bank 5
- */
-#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device
- * 0 - 31, Bank 0
- * 32 - 53, Bank 1
- * 54 - 85, Bank 2
- * 86 - 117, Bank 3
- */
-
-/**************************** Type Definitions *******************************/
-
-/****************************************************************************/
-/**
- * This handler data type allows the user to define a callback function to
- * handle the interrupts for the GPIO device. The application using this
- * driver is expected to define a handler of this type, to support interrupt
- * driven mode. The handler executes in an interrupt context such that minimal
- * processing should be performed.
- *
- * @param CallBackRef is a callback reference passed in by the upper layer
- * when setting the callback functions for a GPIO bank. It is
- * passed back to the upper layer when the callback is invoked. Its
- * type is not important to the driver component, so it is a void
- * pointer.
- * @param Bank is the bank for which the interrupt status has changed.
- * @param Status is the Interrupt status of the GPIO bank.
- *
- *****************************************************************************/
-typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
-
-/**
- * This typedef contains configuration information for a device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- UINTPTR BaseAddr; /**< Register base address */
-} XGpioPs_Config;
-
-/**
- * The XGpioPs driver instance data. The user is required to allocate a
- * variable of this type for the GPIO device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XGpioPs_Config GpioConfig; /**< Device configuration */
- u32 IsReady; /**< Device is initialized and ready */
- XGpioPs_Handler Handler; /**< Status handlers for all banks */
- void *CallBackRef; /**< Callback ref for bank handlers */
- u32 Platform; /**< Platform data */
- u32 MaxPinNum; /**< Max pins in the GPIO device */
- u8 MaxBanks; /**< Max banks in a GPIO device */
- u32 PmcGpio; /**< Flag for accessing PS GPIO for versal*/
-} XGpioPs;
-
-/************************** Variable Definitions *****************************/
-extern XGpioPs_Config XGpioPs_ConfigTable[];
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/* Functions in xgpiops.c */
-s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
- u32 EffectiveAddr);
-
-/* Bank APIs in xgpiops.c */
-u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data);
-void XGpioPs_SetDirection(const XGpioPs *InstancePtr, u8 Bank, u32 Direction);
-u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_SetOutputEnable(const XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
-u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank);
-#ifdef versal
-void XGpioPs_GetBankPin(const XGpioPs *InstancePtr,u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank);
-#else
-void XGpioPs_GetBankPin(u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank);
-#endif
-
-/* Pin APIs in xgpiops.c */
-u32 XGpioPs_ReadPin(const XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_WritePin(const XGpioPs *InstancePtr, u32 Pin, u32 Data);
-void XGpioPs_SetDirectionPin(const XGpioPs *InstancePtr, u32 Pin, u32 Direction);
-u32 XGpioPs_GetDirectionPin(const XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
-u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin);
-
-/* Diagnostic functions in xgpiops_selftest.c */
-s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr);
-
-/* Functions in xgpiops_intr.c */
-/* Bank APIs in xgpiops_intr.c */
-void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
-void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
-u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank);
-u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
-void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
- u32 IntrPolarity, u32 IntrOnAny);
-void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
- u32 *IntrPolarity, u32 *IntrOnAny);
-void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
- XGpioPs_Handler FuncPointer);
-void XGpioPs_IntrHandler(const XGpioPs *InstancePtr);
-
-/* Pin APIs in xgpiops_intr.c */
-void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
-u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin);
-
-void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin);
-u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin);
-u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin);
-
-/* Functions in xgpiops_sinit.c */
-XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/78/c19eff585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/78/c19eff585243001d18b399c1eb9b3628
deleted file mode 100644
index d2cc146..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/78/c19eff585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,104 +0,0 @@
-##############################################################################
-# Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-#
-# SPDX-License-Identifier: MIT
-#
-##############################################################################
-DRIVER_LIB_VERSION = v1.0
-
-include config.make
-
-AS=$(ASSEMBLER)
-COMPILER=$(COMPILER)
-ARCHIVER=$(ARCHIVER)
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-INCLUDEFILES=*.h
-
-SRCFILES:=$(wildcard *.c)
-
-ASSEMBLY_SRCFILES:=$(wildcard *.S)
-
-COBJS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(wildcard *.c))))
-AOBJS1 = $(RELEASEDIR)/asm_vectors.o
-AOBJS2 = $(RELEASEDIR)/boot.o
-AOBJS3 = $(RELEASEDIR)/xil-crt0.o
-AOBJS4 = $(RELEASEDIR)/cpu_init.o
-OBJS = $(COBJS) $(AOBJS1) $(AOBJS2) $(AOBJS3) $(AOBJS4)
-
-ASOURCES1 = asm_vectors.S
-ASOURCES2 = boot.S
-ASOURCES3 = xil-crt0.S
-ASOURCES4 = cpu_init.S
-
-OBJECTS = $(OBJS)
-
-libs: standalone_libs
-
-standalone_libs: ${OBJECTS}
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-ASSEMBLY_DEPFILES := $(ASSEMBLY_SRCFILES:%.S=$(RELEASEDIR)%.d)
-
-include $(wildcard $(ASSEMBLY_DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(AOBJS1): $(ASOURCES1)
-ifeq ($(findstring asm_vectors.S,$(wildcard *.S)),asm_vectors.S)
- ${COMPILER} $(INCLUDES) --target=arm-arm-none-eabi -E -o asm_vectors_post.s asm_vectors.S
-endif
- ${AS} --cpu=Cortex-R5 -o $*.o asm_vectors_post.s --depend=$*.d
-
-$(AOBJS2): $(ASOURCES2)
-ifeq ($(findstring boot.S,$(wildcard *.S)),boot.S)
- ${COMPILER} $(INCLUDES) --target=arm-arm-none-eabi -E -o boot_post.s boot.S
-endif
- ${AS} --cpu=Cortex-R5 -o $*.o boot_post.s --depend=$*.d
-
-$(AOBJS3): $(ASOURCES3)
-ifeq ($(findstring xil-crt0.S,$(wildcard *.S)),xil-crt0.S)
- ${COMPILER} $(INCLUDES) --target=arm-arm-none-eabi -E -o xil-crt0_post.s xil-crt0.S
-endif
- ${AS} --cpu=Cortex-R5 -o $*.o xil-crt0_post.s --depend=$*.d
-
-$(AOBJS4): $(ASOURCES4)
-ifeq ($(findstring cpu_init.S,$(wildcard *.S)),cpu_init.S)
- ${COMPILER} $(INCLUDES) --target=arm-arm-none-eabi -E -o cpu_init_post.s cpu_init.S
-endif
- ${AS} --cpu=Cortex-R5 -o $*.o cpu_init_post.s --depend=$*.d
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $<
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h)) $(addprefix $(INCLUDEDIR), $(subst includes_ps/,,$(wildcard includes_ps/*.h)))
-
-
-
-$(INCLUDEDIR)%.h: includes_ps/%.h
- $(CP) $< $@
-
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf $(DEPFILES)
- rm -rf $(ASSEMBLY_DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/78/f16a3c575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/78/f16a3c575243001d18b399c1eb9b3628
deleted file mode 100644
index 7c3753d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/78/f16a3c575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,291 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2012 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x6000;
-_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
-
-_RSA_AC_SIZE = DEFINED(_RSA_AC_SIZE) ? _RSA_AC_SIZE : 0x1000;
-
-_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
-_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
-_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
-_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
-
-/* Define Memories in the system */
-
-MEMORY
-{
- ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x00030000
- ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FE00
-}
-
-/* Specify the default entry point to the program */
-
-ENTRY(_vector_table)
-
-
-SECTIONS
-{
-.text : {
- *(.vectors)
- *(.boot)
- *(.text)
- *(.text.*)
- *(.gnu.linkonce.t.*)
- *(.plt)
- *(.gnu_warning)
- *(.gcc_execpt_table)
- *(.glue_7)
- *(.glue_7t)
- *(.vfp11_veneer)
- *(.ARM.extab)
- *(.gnu.linkonce.armextab.*)
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.note.gnu.build-id : {
- KEEP (*(.note.gnu.build-id))
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.init : {
- KEEP (*(.init))
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.fini : {
- KEEP (*(.fini))
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.rodata : {
- __rodata_start = .;
- *(.rodata)
- *(.rodata.*)
- *(.gnu.linkonce.r.*)
- __rodata_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.rodata1 : {
- __rodata1_start = .;
- *(.rodata1)
- *(.rodata1.*)
- __rodata1_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.sdata2 : {
- __sdata2_start = .;
- *(.sdata2)
- *(.sdata2.*)
- *(.gnu.linkonce.s2.*)
- __sdata2_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.sbss2 : {
- __sbss2_start = .;
- *(.sbss2)
- *(.sbss2.*)
- *(.gnu.linkonce.sb2.*)
- __sbss2_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.data : {
- __data_start = .;
- *(.data)
- *(.data.*)
- *(.gnu.linkonce.d.*)
- *(.jcr)
- *(.got)
- *(.got.plt)
- __data_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.data1 : {
- __data1_start = .;
- *(.data1)
- *(.data1.*)
- __data1_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.got : {
- *(.got)
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.ctors : {
- __CTOR_LIST__ = .;
- ___CTORS_LIST___ = .;
- KEEP (*crtbegin.o(.ctors))
- KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- __CTOR_END__ = .;
- ___CTORS_END___ = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.dtors : {
- __DTOR_LIST__ = .;
- ___DTORS_LIST___ = .;
- KEEP (*crtbegin.o(.dtors))
- KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- __DTOR_END__ = .;
- ___DTORS_END___ = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.fixup : {
- __fixup_start = .;
- *(.fixup)
- __fixup_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.eh_frame : {
- *(.eh_frame)
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.eh_framehdr : {
- __eh_framehdr_start = .;
- *(.eh_framehdr)
- __eh_framehdr_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.gcc_except_table : {
- *(.gcc_except_table)
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.mmu_tbl (ALIGN(0x4000)): {
- __mmu_tbl_start = .;
- *(.mmu_tbl)
- __mmu_tbl_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.ARM.exidx : {
- __exidx_start = .;
- *(.ARM.exidx*)
- *(.gnu.linkonce.armexidix.*.*)
- __exidx_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.preinit_array : {
- __preinit_array_start = .;
- KEEP (*(SORT(.preinit_array.*)))
- KEEP (*(.preinit_array))
- __preinit_array_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.init_array : {
- __init_array_start = .;
- KEEP (*(SORT(.init_array.*)))
- KEEP (*(.init_array))
- __init_array_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.fini_array : {
- __fini_array_start = .;
- KEEP (*(SORT(.fini_array.*)))
- KEEP (*(.fini_array))
- __fini_array_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.rsa_ac : {
- . = ALIGN(64);
- __rsa_ac_start = .;
- . += _RSA_AC_SIZE;
- __rsa_ac_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.ARM.attributes : {
- __ARM.attributes_start = .;
- *(.ARM.attributes)
- __ARM.attributes_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.sdata : {
- __sdata_start = .;
- *(.sdata)
- *(.sdata.*)
- *(.gnu.linkonce.s.*)
- __sdata_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.sbss (NOLOAD) : {
- __sbss_start = .;
- *(.sbss)
- *(.sbss.*)
- *(.gnu.linkonce.sb.*)
- __sbss_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.tdata : {
- __tdata_start = .;
- *(.tdata)
- *(.tdata.*)
- *(.gnu.linkonce.td.*)
- __tdata_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.tbss : {
- __tbss_start = .;
- *(.tbss)
- *(.tbss.*)
- *(.gnu.linkonce.tb.*)
- __tbss_end = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.bss (NOLOAD) : {
- __bss_start = .;
- __bss_start__ = .;
- *(.bss)
- *(.bss.*)
- *(.gnu.linkonce.b.*)
- *(COMMON)
- __bss_end = .;
- __bss_end__ = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
-
-_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
-
-/* Generate Stack and Heap definitions */
-
-.heap (NOLOAD) : {
- . = ALIGN(16);
- _heap = .;
- HeapBase = .;
- _heap_start = .;
- . += _HEAP_SIZE;
- _heap_end = .;
- HeapLimit = .;
-} > ps7_ram_0_S_AXI_BASEADDR
-
-.stack (NOLOAD) : {
- . = ALIGN(16);
- _stack_end = .;
- . += _STACK_SIZE;
- _stack = .;
- __stack = _stack;
- . = ALIGN(16);
- _irq_stack_end = .;
- . += _STACK_SIZE;
- __irq_stack = .;
- _supervisor_stack_end = .;
- . += _SUPERVISOR_STACK_SIZE;
- . = ALIGN(16);
- __supervisor_stack = .;
- _abort_stack_end = .;
- . += _ABORT_STACK_SIZE;
- . = ALIGN(16);
- __abort_stack = .;
- _fiq_stack_end = .;
- . += _FIQ_STACK_SIZE;
- . = ALIGN(16);
- __fiq_stack = .;
- _undef_stack_end = .;
- . += _UNDEF_STACK_SIZE;
- . = ALIGN(16);
- __undef_stack = .;
-} > ps7_ram_1_S_AXI_BASEADDR
-
-_end = .;
-}
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/78/f1f939575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/78/f1f939575243001d18b399c1eb9b3628
deleted file mode 100644
index 568a76b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/78/f1f939575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1326 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2011 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file image_mover.c
-*
-* Move partitions to either DDR to execute or to program FPGA.
-* It performs partition walk.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a jz 05/24/11 Initial release
-* 2.00a jz 06/30/11 Updated partition header defs for 64-byte
-* alignment change in data2mem tool
-* 2.00a mb 05/25/12 Updated for standalone based bsp FSBL
-* Nand/SD encryption and review comments
-* 3.00a np 08/30/12 Added FSBL user hook calls
-* (before and after bitstream download.)
-* 4.00a sgd 02/28/13 Fix for CR#691148 Secure bootmode error in devcfg test
-* Fix for CR#695578 FSBL failed to load standalone
-* application in secure bootmode
-*
-* 4.00a sgd 04/23/13 Fix for CR#710128 FSBL failed to load standalone
-* application in secure bootmode
-* 5.00a kc 07/30/13 Fix for CR#724165 Partition Header used by FSBL
-* is not authenticated
-* Fix for CR#724166 FSBL doesn�t use PPK authenticated
-* by Boot ROM for authenticating the Partition images
-* Fix for CR#732062 FSBL fails to build if UART not
-* available
-* 7.00a kc 10/30/13 Fix for CR#755245 FSBL does not load partition
-* if eMMC has only one partition
-* 8.00a kc 01/16/13 Fix for CR#767798 FSBL MD5 Checksum failure
-* for encrypted images
-* Fix for CR#761895 FSBL should authenticate image
-* only if partition owner was not set to u-boot
-* 9.00a kc 04/16/14 Fix for CR#785778 FSBL takes 8 seconds to
-* authenticate (RSA) a bitstream on zc706
-* 10.00a kc 07/15/14 Fix for CR#804595 Zynq FSBL - Issues with
-* fallback image offset handling using MD5
-* Fix for PR#782309 Fallback support for AES
-* encryption with E-Fuse - Enhancement
-* 11.00a ka 10/12/18 Fix for CR#1006294 Zynq FSBL - Zynq FSBL does not check
-* USE_AES_ONLY eFuse
-*
-*
-*
-* @note
-* A partition is either an executable or a bitstream to program FPGA
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "fsbl.h"
-#include "image_mover.h"
-#include "xil_printf.h"
-#include "xreg_cortexa9.h"
-#include "pcap.h"
-#include "fsbl_hooks.h"
-#include "md5.h"
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-#include "xwdtps.h"
-#endif
-
-#ifdef RSA_SUPPORT
-#include "rsa.h"
-#include "xil_cache.h"
-#endif
-/************************** Constant Definitions *****************************/
-
-/* We are 32-bit machine */
-#define MAXIMUM_IMAGE_WORD_LEN 0x40000000
-#define MD5_CHECKSUM_SIZE 16
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-u32 ValidateParition(u32 StartAddr, u32 Length, u32 ChecksumOffset);
-u32 GetPartitionChecksum(u32 ChecksumOffset, u8 *Checksum);
-u32 CalcPartitionChecksum(u32 SourceAddr, u32 DataLength, u8 *Checksum);
-
-/************************** Variable Definitions *****************************/
-/*
- * Partition information flags
- */
-u8 EncryptedPartitionFlag;
-u8 PLPartitionFlag;
-u8 PSPartitionFlag;
-u8 SignedPartitionFlag;
-u8 PartitionChecksumFlag;
-u8 BitstreamFlag;
-u8 ApplicationFlag;
-
-u32 ExecutionAddress;
-ImageMoverType MoveImage;
-
-/*
- * Header array
- */
-PartHeader PartitionHeader[MAX_PARTITION_NUMBER];
-u32 PartitionCount;
-u32 FsblLength;
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-extern XWdtPs Watchdog; /* Instance of WatchDog Timer */
-#endif
-
-extern u32 Silicon_Version;
-extern u32 FlashReadBaseAddress;
-extern u8 LinearBootDeviceFlag;
-extern XDcfg *DcfgInstPtr;
-
-/*****************************************************************************/
-/**
-*
-* This function
-*
-* @param
-*
-* @return
-*
-*
-* @note None
-*
-****************************************************************************/
-u32 LoadBootImage(void)
-{
- u32 RebootStatusRegister = 0;
- u32 MultiBootReg = 0;
- u32 ImageStartAddress = 0;
- u32 PartitionNum;
- u32 PartitionDataLength;
- u32 PartitionImageLength;
- u32 PartitionTotalSize;
- u32 PartitionExecAddr;
- u32 PartitionAttr;
- u32 ExecAddress = 0;
- u32 PartitionLoadAddr;
- u32 PartitionStartAddr;
- u32 PartitionChecksumOffset;
- u8 ExecAddrFlag = 0 ;
- u32 Status;
- PartHeader *HeaderPtr;
- u32 EfuseStatusRegValue;
-#ifdef RSA_SUPPORT
- u32 HeaderSize;
-#endif
-#ifndef FORCE_USE_AES_EXCLUDE
- u32 EncOnly;
-#endif
- /*
- * Resetting the Flags
- */
- BitstreamFlag = 0;
- ApplicationFlag = 0;
-
- RebootStatusRegister = Xil_In32(REBOOT_STATUS_REG);
- fsbl_printf(DEBUG_INFO,
- "Reboot status register: 0x%08lx\r\n",RebootStatusRegister);
-
- if (Silicon_Version == SILICON_VERSION_1) {
- /*
- * Clear out fallback mask from previous run
- * We start from the first partition again
- */
- if ((RebootStatusRegister & FSBL_FAIL_MASK) ==
- FSBL_FAIL_MASK) {
- fsbl_printf(DEBUG_INFO,
- "Reboot status shows previous run falls back\r\n");
- RebootStatusRegister &= ~(FSBL_FAIL_MASK);
- Xil_Out32(REBOOT_STATUS_REG, RebootStatusRegister);
- }
-
- /*
- * Read the image start address
- */
- ImageStartAddress = *(u32 *)BASEADDR_HOLDER;
- } else {
- /*
- * read the multiboot register
- */
- MultiBootReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
- XDCFG_MULTIBOOT_ADDR_OFFSET);
-
- fsbl_printf(DEBUG_INFO,"Multiboot Register: 0x%08lx\r\n",MultiBootReg);
-
- /*
- * Compute the image start address
- */
- ImageStartAddress = (MultiBootReg & PCAP_MBOOT_REG_REBOOT_OFFSET_MASK)
- * GOLDEN_IMAGE_OFFSET;
- }
-
- fsbl_printf(DEBUG_INFO,"Image Start Address: 0x%08lx\r\n",ImageStartAddress);
-
- /*
- * Get partitions header information
- */
- Status = GetPartitionHeaderInfo(ImageStartAddress);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "Partition Header Load Failed\r\n");
- OutputStatus(GET_HEADER_INFO_FAIL);
- FsblFallback();
- }
-
- /*
- * RSA is not implemented in 1.0 and 2.0
- * silicon
- */
- if ((Silicon_Version != SILICON_VERSION_1) &&
- (Silicon_Version != SILICON_VERSION_2)) {
- /*
- * Read Efuse Status Register
- */
- EfuseStatusRegValue = Xil_In32(EFUSE_STATUS_REG);
- if (EfuseStatusRegValue & EFUSE_STATUS_RSA_ENABLE_MASK) {
- fsbl_printf(DEBUG_GENERAL,"RSA enabled for Chip\r\n");
-#ifdef RSA_SUPPORT
- /*
- * Set the Ppk
- */
- SetPpk();
-
- /*
- * Read partition header with signature
- */
- Status = GetImageHeaderAndSignature(ImageStartAddress,
- (u32 *)DDR_TEMP_START_ADDR);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,
- "Read Partition Header signature Failed\r\n");
- OutputStatus(GET_HEADER_INFO_FAIL);
- FsblFallback();
- }
- HeaderSize=TOTAL_HEADER_SIZE+RSA_SIGNATURE_SIZE;
-
- Status = AuthenticatePartition((u8 *)DDR_TEMP_START_ADDR, HeaderSize);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,
- "Partition Header signature Failed\r\n");
- OutputStatus(GET_HEADER_INFO_FAIL);
- FsblFallback();
- }
-#else
- /*
- * In case user not enabled RSA authentication feature
- */
- fsbl_printf(DEBUG_GENERAL,"RSA_SUPPORT_NOT_ENABLED_FAIL\r\n");
- OutputStatus(RSA_SUPPORT_NOT_ENABLED_FAIL);
- FsblFallback();
-#endif
- }
- }
-
-#ifdef MMC_SUPPORT
- /*
- * In case of MMC support
- * boot image preset in MMC will not have FSBL partition
- */
- PartitionNum = 0;
-#else
- /*
- * First partition header was ignored by FSBL
- * As it contain FSBL partition information
- */
- PartitionNum = 1;
-#endif
-
- while (PartitionNum < PartitionCount) {
-
- fsbl_printf(DEBUG_INFO, "Partition Number: %lu\r\n", PartitionNum);
-
- HeaderPtr = &PartitionHeader[PartitionNum];
-
- /*
- * Print partition header information
- */
- HeaderDump(HeaderPtr);
-
- /*
- * Validate partition header
- */
- Status = ValidateHeader(HeaderPtr);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "INVALID_HEADER_FAIL\r\n");
- OutputStatus(INVALID_HEADER_FAIL);
- FsblFallback();
- }
-
- /*
- * Load partition header information in to local variables
- */
- PartitionDataLength = HeaderPtr->DataWordLen;
- PartitionImageLength = HeaderPtr->ImageWordLen;
- PartitionExecAddr = HeaderPtr->ExecAddr;
- PartitionAttr = HeaderPtr->PartitionAttr;
- PartitionLoadAddr = HeaderPtr->LoadAddr;
- PartitionChecksumOffset = HeaderPtr->CheckSumOffset;
- PartitionStartAddr = HeaderPtr->PartitionStart;
- PartitionTotalSize = HeaderPtr->PartitionWordLen;
-
- /*
- * Partition owner should be FSBL to validate the partition
- */
- if ((PartitionAttr & ATTRIBUTE_PARTITION_OWNER_MASK) !=
- ATTRIBUTE_PARTITION_OWNER_FSBL) {
- /*
- * if FSBL is not the owner of partition,
- * skip this partition, continue with next partition
- */
- fsbl_printf(DEBUG_INFO, "Skipping partition %0lx\r\n",
- PartitionNum);
- /*
- * Increment partition number
- */
- PartitionNum++;
- continue;
- }
-
- if (PartitionAttr & ATTRIBUTE_PL_IMAGE_MASK) {
- fsbl_printf(DEBUG_INFO, "Bitstream\r\n");
- PLPartitionFlag = 1;
- PSPartitionFlag = 0;
- BitstreamFlag = 1;
- if (ApplicationFlag == 1) {
-#ifdef STDOUT_BASEADDRESS
- xil_printf("\r\nFSBL Warning !!!"
- "Bitstream not loaded into PL\r\n");
- xil_printf("Partition order invalid\r\n");
-#endif
- break;
- }
- }
-
- if (PartitionAttr & ATTRIBUTE_PS_IMAGE_MASK) {
- fsbl_printf(DEBUG_INFO, "Application\r\n");
- PSPartitionFlag = 1;
- PLPartitionFlag = 0;
- ApplicationFlag = 1;
- }
-
- /*
- * Encrypted partition will have different value
- * for Image length and data length
- */
- if (PartitionDataLength != PartitionImageLength) {
- fsbl_printf(DEBUG_INFO, "Encrypted\r\n");
- EncryptedPartitionFlag = 1;
- } else {
- EncryptedPartitionFlag = 0;
- }
-
-#ifndef FORCE_USE_AES_EXCLUDE
- EncOnly = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
- XDCFG_STATUS_OFFSET) &
- XDCFG_STATUS_EFUSE_SEC_EN_MASK;
- if ((EncOnly != 0) &&
- (EncryptedPartitionFlag == 0)) {
- fsbl_printf(DEBUG_GENERAL,"EFUSE_SEC_EN bit is set,"
- " Encryption is mandatory\r\n");
- OutputStatus(PARTITION_LOAD_FAIL);
- FsblFallback();
- }
-#endif
- /*
- * Check for partition checksum check
- */
- if (PartitionAttr & ATTRIBUTE_CHECKSUM_TYPE_MASK) {
- PartitionChecksumFlag = 1;
- } else {
- PartitionChecksumFlag = 0;
- }
-
- /*
- * RSA signature check
- */
- if (PartitionAttr & ATTRIBUTE_RSA_PRESENT_MASK) {
- fsbl_printf(DEBUG_INFO, "RSA Signed\r\n");
- SignedPartitionFlag = 1;
- } else {
- SignedPartitionFlag = 0;
- }
-
- /*
- * Load address check
- * Loop will break when PS load address zero and partition is
- * un-signed or un-encrypted
- */
- if ((PSPartitionFlag == 1) && (PartitionLoadAddr < DDR_START_ADDR)) {
- if ((PartitionLoadAddr == 0) &&
- (!((SignedPartitionFlag == 1) ||
- (EncryptedPartitionFlag == 1)))) {
- break;
- } else {
- fsbl_printf(DEBUG_GENERAL,
- "INVALID_LOAD_ADDRESS_FAIL\r\n");
- OutputStatus(INVALID_LOAD_ADDRESS_FAIL);
- FsblFallback();
- }
- }
-
- if (PSPartitionFlag && (PartitionLoadAddr > DDR_END_ADDR)) {
- fsbl_printf(DEBUG_GENERAL,
- "INVALID_LOAD_ADDRESS_FAIL\r\n");
- OutputStatus(INVALID_LOAD_ADDRESS_FAIL);
- FsblFallback();
- }
-
- /*
- * Load execution address of first PS partition
- */
- if (PSPartitionFlag && (!ExecAddrFlag)) {
- ExecAddrFlag++;
- ExecAddress = PartitionExecAddr;
- }
-
- /*
- * FSBL user hook call before bitstream download
- */
- if (PLPartitionFlag) {
- Status = FsblHookBeforeBitstreamDload();
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"FSBL_BEFORE_BSTREAM_HOOK_FAIL\r\n");
- OutputStatus(FSBL_BEFORE_BSTREAM_HOOK_FAIL);
- FsblFallback();
- }
- }
-
- /*
- * Move partitions from boot device
- */
- Status = PartitionMove(ImageStartAddress, HeaderPtr);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"PARTITION_MOVE_FAIL\r\n");
- OutputStatus(PARTITION_MOVE_FAIL);
- FsblFallback();
- }
-
- if ((SignedPartitionFlag) || (PartitionChecksumFlag)) {
- if(PLPartitionFlag) {
- /*
- * PL partition loaded in to DDR temporary address
- * for authentication and checksum verification
- */
- PartitionStartAddr = DDR_TEMP_START_ADDR;
- } else {
- PartitionStartAddr = PartitionLoadAddr;
- }
-
- if (PartitionChecksumFlag) {
- /*
- * Validate the partition data with checksum
- */
- Status = ValidateParition(PartitionStartAddr,
- (PartitionTotalSize << WORD_LENGTH_SHIFT),
- ImageStartAddress +
- (PartitionChecksumOffset << WORD_LENGTH_SHIFT));
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"PARTITION_CHECKSUM_FAIL\r\n");
- OutputStatus(PARTITION_CHECKSUM_FAIL);
- FsblFallback();
- }
-
- fsbl_printf(DEBUG_INFO, "Partition Validation Done\r\n");
- }
-
- /*
- * Authentication Partition
- */
- if (SignedPartitionFlag == 1 ) {
-#ifdef RSA_SUPPORT
- Xil_DCacheEnable();
- Status = AuthenticatePartition((u8*)PartitionStartAddr,
- (PartitionTotalSize << WORD_LENGTH_SHIFT));
- if (Status != XST_SUCCESS) {
- Xil_DCacheFlush();
- Xil_DCacheDisable();
- fsbl_printf(DEBUG_GENERAL,"AUTHENTICATION_FAIL\r\n");
- OutputStatus(AUTHENTICATION_FAIL);
- FsblFallback();
- }
- fsbl_printf(DEBUG_INFO,"Authentication Done\r\n");
- Xil_DCacheFlush();
- Xil_DCacheDisable();
-#else
- /*
- * In case user not enabled RSA authentication feature
- */
- fsbl_printf(DEBUG_GENERAL,"RSA_SUPPORT_NOT_ENABLED_FAIL\r\n");
- OutputStatus(RSA_SUPPORT_NOT_ENABLED_FAIL);
- FsblFallback();
-#endif
- }
-
- /*
- * Decrypt PS partition
- */
- if (EncryptedPartitionFlag && PSPartitionFlag) {
- Status = DecryptPartition(PartitionStartAddr,
- PartitionDataLength,
- PartitionImageLength);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"DECRYPTION_FAIL\r\n");
- OutputStatus(DECRYPTION_FAIL);
- FsblFallback();
- }
- }
-
- /*
- * Load Signed PL partition in Fabric
- */
- if (PLPartitionFlag) {
- Status = PcapLoadPartition((u32*)PartitionStartAddr,
- (u32*)PartitionLoadAddr,
- PartitionImageLength,
- PartitionDataLength,
- EncryptedPartitionFlag);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"BITSTREAM_DOWNLOAD_FAIL\r\n");
- OutputStatus(BITSTREAM_DOWNLOAD_FAIL);
- FsblFallback();
- }
- }
- }
-
-
- /*
- * FSBL user hook call after bitstream download
- */
- if (PLPartitionFlag) {
- Status = FsblHookAfterBitstreamDload();
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"FSBL_AFTER_BSTREAM_HOOK_FAIL\r\n");
- OutputStatus(FSBL_AFTER_BSTREAM_HOOK_FAIL);
- FsblFallback();
- }
- }
- /*
- * Increment partition number
- */
- PartitionNum++;
- }
-
- return ExecAddress;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function loads all partition header information in global array
-*
-* @param ImageAddress is the start address of the image
-*
-* @return - XST_SUCCESS if Get partition Header information successful
-* - XST_FAILURE if Get Partition Header information failed
-*
-* @note None
-*
-****************************************************************************/
-u32 GetPartitionHeaderInfo(u32 ImageBaseAddress)
-{
- u32 PartitionHeaderOffset;
- u32 Status;
-
-
- /*
- * Get the length of the FSBL from BootHeader
- */
- Status = GetFsblLength(ImageBaseAddress, &FsblLength);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "Get Header Start Address Failed\r\n");
- return XST_FAILURE;
- }
-
- /*
- * Get the start address of the partition header table
- */
- Status = GetPartitionHeaderStartAddr(ImageBaseAddress,
- &PartitionHeaderOffset);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "Get Header Start Address Failed\r\n");
- return XST_FAILURE;
- }
-
- /*
- * Header offset on flash
- */
- PartitionHeaderOffset += ImageBaseAddress;
-
- fsbl_printf(DEBUG_INFO,"Partition Header Offset:0x%08lx\r\n",
- PartitionHeaderOffset);
-
- /*
- * Load all partitions header data in to global variable
- */
- Status = LoadPartitionsHeaderInfo(PartitionHeaderOffset,
- &PartitionHeader[0]);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "Header Information Load Failed\r\n");
- return XST_FAILURE;
- }
-
- /*
- * Get partitions count from partitions header information
- */
- PartitionCount = GetPartitionCount(&PartitionHeader[0]);
-
- fsbl_printf(DEBUG_INFO, "Partition Count: %lu\r\n", PartitionCount);
-
- /*
- * Partition Count check
- */
- if (PartitionCount >= MAX_PARTITION_NUMBER) {
- fsbl_printf(DEBUG_GENERAL, "Invalid Partition Count\r\n");
- return XST_FAILURE;
-#ifndef MMC_SUPPORT
- } else if (PartitionCount <= 1) {
- fsbl_printf(DEBUG_GENERAL, "There is no partition to load\r\n");
- return XST_FAILURE;
-#endif
- }
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This function goes to the partition header of the specified partition
-*
-* @param ImageAddress is the start address of the image
-*
-* @return Offset Partition header address of the image
-*
-* @return - XST_SUCCESS if Get Partition Header start address successful
-* - XST_FAILURE if Get Partition Header start address failed
-*
-* @note None
-*
-****************************************************************************/
-u32 GetPartitionHeaderStartAddr(u32 ImageAddress, u32 *Offset)
-{
- u32 Status;
-
- Status = MoveImage(ImageAddress + IMAGE_PHDR_OFFSET, (u32)Offset, 4);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function goes to the partition header of the specified partition
-*
-* @param ImageAddress is the start address of the image
-*
-* @return Offset to Image header table address of the image
-*
-* @return - XST_SUCCESS if Get Partition Header start address successful
-* - XST_FAILURE if Get Partition Header start address failed
-*
-* @note None
-*
-****************************************************************************/
-u32 GetImageHeaderStartAddr(u32 ImageAddress, u32 *Offset)
-{
- u32 Status;
-
- Status = MoveImage(ImageAddress + IMAGE_HDR_OFFSET, (u32)Offset, 4);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-/*****************************************************************************/
-/**
-*
-* This function gets the length of the FSBL
-*
-* @param ImageAddress is the start address of the image
-*
-* @return FsblLength is the length of the fsbl
-*
-* @return - XST_SUCCESS if fsbl length reading is successful
-* - XST_FAILURE if fsbl length reading failed
-*
-* @note None
-*
-****************************************************************************/
-u32 GetFsblLength(u32 ImageAddress, u32 *FsblLength)
-{
- u32 Status;
-
- Status = MoveImage(ImageAddress + IMAGE_TOT_BYTE_LEN_OFFSET,
- (u32)FsblLength, 4);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"Move Image failed reading FsblLength\r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-#ifdef RSA_SUPPORT
-/*****************************************************************************/
-/**
-*
-* This function goes to read the image headers and its signature. Image
-* header consists of image header table, image headers, partition
-* headers
-*
-* @param ImageBaseAddress is the start address of the image header
-*
-* @return Offset Partition header address of the image
-*
-* @return - XST_SUCCESS if Get Partition Header start address successful
-* - XST_FAILURE if Get Partition Header start address failed
-*
-* @note None
-*
-****************************************************************************/
-u32 GetImageHeaderAndSignature(u32 ImageBaseAddress, u32 *Offset)
-{
- u32 Status;
- u32 ImageHeaderOffset;
-
- /*
- * Get the start address of the partition header table
- */
- Status = GetImageHeaderStartAddr(ImageBaseAddress, &ImageHeaderOffset);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "Get Header Start Address Failed\r\n");
- return XST_FAILURE;
- }
-
- Status = MoveImage(ImageBaseAddress+ImageHeaderOffset, (u32)Offset,
- TOTAL_HEADER_SIZE + RSA_SIGNATURE_SIZE);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-#endif
-/*****************************************************************************/
-/**
-*
-* This function get the header information of the all the partitions and load into
-* global array
-*
-* @param PartHeaderOffset Offset address where the header information present
-*
-* @param Header Partition header pointer
-*
-* @return - XST_SUCCESS if Load Partitions Header information successful
-* - XST_FAILURE if Load Partitions Header information failed
-*
-* @note None
-*
-****************************************************************************/
-u32 LoadPartitionsHeaderInfo(u32 PartHeaderOffset, PartHeader *Header)
-{
- u32 Status;
-
- Status = MoveImage(PartHeaderOffset, (u32)Header, sizeof(PartHeader)*MAX_PARTITION_NUMBER);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This function dumps the partition header.
-*
-* @param Header Partition header pointer
-*
-* @return None
-*
-* @note None
-*
-******************************************************************************/
-void HeaderDump(PartHeader *Header)
-{
- fsbl_printf(DEBUG_INFO, "Header Dump\r\n");
- fsbl_printf(DEBUG_INFO, "Image Word Len: 0x%08lx\r\n",
- Header->ImageWordLen);
- fsbl_printf(DEBUG_INFO, "Data Word Len: 0x%08lx\r\n",
- Header->DataWordLen);
- fsbl_printf(DEBUG_INFO, "Partition Word Len:0x%08lx\r\n",
- Header->PartitionWordLen);
- fsbl_printf(DEBUG_INFO, "Load Addr: 0x%08lx\r\n",
- Header->LoadAddr);
- fsbl_printf(DEBUG_INFO, "Exec Addr: 0x%08lx\r\n",
- Header->ExecAddr);
- fsbl_printf(DEBUG_INFO, "Partition Start: 0x%08lx\r\n",
- Header->PartitionStart);
- fsbl_printf(DEBUG_INFO, "Partition Attr: 0x%08lx\r\n",
- Header->PartitionAttr);
- fsbl_printf(DEBUG_INFO, "Partition Checksum Offset: 0x%08lx\r\n",
- Header->CheckSumOffset);
- fsbl_printf(DEBUG_INFO, "Section Count: 0x%08lx\r\n",
- Header->SectionCount);
- fsbl_printf(DEBUG_INFO, "Checksum: 0x%08lx\r\n",
- Header->CheckSum);
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function calculates the partitions count from header information
-*
-* @param Header Partition header pointer
-*
-* @return Count Partition count
-*
-* @note None
-*
-*******************************************************************************/
-u32 GetPartitionCount(PartHeader *Header)
-{
- u32 Count=0;
- struct HeaderArray *Hap;
-
- for(Count = 0; Count < MAX_PARTITION_NUMBER; Count++) {
- Hap = (struct HeaderArray *)&Header[Count];
- if(IsLastPartition(Hap)!=XST_FAILURE)
- break;
- }
-
- return Count;
-}
-
-/******************************************************************************/
-/**
-* This function check whether the current partition is the end of partitions
-*
-* The partition is the end of the partitions if it looks like this:
-* 0x00000000
-* 0x00000000
-* ....
-* 0x00000000
-* 0x00000000
-* 0xFFFFFFFF
-*
-* @param H is a pointer to struct HeaderArray
-*
-* @return
-* - XST_SUCCESS if it is the last partition
-* - XST_FAILURE if it is not last partition
-*
-****************************************************************************/
-u32 IsLastPartition(struct HeaderArray *H)
-{
- int Index;
-
- if (H->Fields[PARTITION_HDR_CHECKSUM_WORD_COUNT] != 0xFFFFFFFF) {
- return XST_FAILURE;
- }
-
- for (Index = 0; Index < PARTITION_HDR_WORD_COUNT - 1; Index++) {
-
- if (H->Fields[Index] != 0x0) {
- return XST_FAILURE;
- }
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function validates the partition header.
-*
-* @param Header Partition header pointer
-*
-* @return
-* - XST_FAILURE if bad header.
-* - XST_SUCCESS if successful.
-*
-* @note None
-*
-*******************************************************************************/
-u32 ValidateHeader(PartHeader *Header)
-{
- struct HeaderArray *Hap;
-
- Hap = (struct HeaderArray *)Header;
-
- /*
- * If there are no partitions to load, fail
- */
- if (IsEmptyHeader(Hap) == XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "IMAGE_HAS_NO_PARTITIONS\r\n");
- return XST_FAILURE;
- }
-
- /*
- * Validate partition header checksum
- */
- if (ValidatePartitionHeaderChecksum(Hap) != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "PARTITION_HEADER_CORRUPTION\r\n");
- return XST_FAILURE;
- }
-
- /*
- * Validate partition data size
- */
- if (Header->ImageWordLen > MAXIMUM_IMAGE_WORD_LEN) {
- fsbl_printf(DEBUG_GENERAL, "INVALID_PARTITION_LENGTH\r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-* This function check whether the current partition header is empty.
-* A partition header is considered empty if image word length is 0 and the
-* last word is 0.
-*
-* @param H is a pointer to struct HeaderArray
-*
-* @return
-* - XST_SUCCESS , If the partition header is empty
-* - XST_FAILURE , If the partition header is NOT empty
-*
-* @note Caller is responsible to make sure the address is valid.
-*
-*
-****************************************************************************/
-u32 IsEmptyHeader(struct HeaderArray *H)
-{
- int Index;
-
- for (Index = 0; Index < PARTITION_HDR_WORD_COUNT; Index++) {
- if (H->Fields[Index] != 0x0) {
- return XST_FAILURE;
- }
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function checks the header checksum If the header checksum is not valid
-* XST_FAILURE is returned.
-*
-* @param H is a pointer to struct HeaderArray
-*
-* @return
-* - XST_SUCCESS is header checksum is ok
-* - XST_FAILURE if the header checksum is not correct
-*
-* @note None.
-*
-****************************************************************************/
-u32 ValidatePartitionHeaderChecksum(struct HeaderArray *H)
-{
- u32 Checksum;
- u32 Count;
-
- Checksum = 0;
-
- for (Count = 0; Count < PARTITION_HDR_CHECKSUM_WORD_COUNT; Count++) {
- /*
- * Read the word from the header
- */
- Checksum += H->Fields[Count];
- }
-
- /*
- * Invert checksum, last bit of error checking
- */
- Checksum ^= 0xFFFFFFFF;
-
- /*
- * Validate the checksum
- */
- if (H->Fields[PARTITION_HDR_CHECKSUM_WORD_COUNT] != Checksum) {
- fsbl_printf(DEBUG_GENERAL, "Error: Checksum 0x%8.8lx != 0x%8.8lx\r\n",
- Checksum, H->Fields[PARTITION_HDR_CHECKSUM_WORD_COUNT]);
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function load the partition from boot device
-*
-* @param ImageBaseAddress Base address on flash
-* @param Header Partition header pointer
-*
-* @return
-* - XST_SUCCESS if partition move successful
-* - XST_FAILURE if check failed move failed
-*
-* @note None
-*
-*******************************************************************************/
-u32 PartitionMove(u32 ImageBaseAddress, PartHeader *Header)
-{
- u32 SourceAddr;
- u32 Status;
- u8 SecureTransferFlag = 0;
- u32 LoadAddr;
- u32 ImageWordLen;
- u32 DataWordLen;
-
- SourceAddr = ImageBaseAddress;
- SourceAddr += Header->PartitionStart<LoadAddr;
- ImageWordLen = Header->ImageWordLen;
- DataWordLen = Header->DataWordLen;
-
- /*
- * Add flash base address for linear boot devices
- */
- if (LinearBootDeviceFlag) {
- SourceAddr += FlashReadBaseAddress;
- }
-
- /*
- * Partition encrypted
- */
- if(EncryptedPartitionFlag) {
- SecureTransferFlag = 1;
- }
-
- /*
- * For Signed or checksum enabled partition,
- * Total partition image need to copied to DDR
- */
- if (SignedPartitionFlag || PartitionChecksumFlag) {
- ImageWordLen = Header->PartitionWordLen;
- DataWordLen = Header->PartitionWordLen;
- }
-
- /*
- * Encrypted and Signed PS partition need to be loaded on to DDR
- * without decryption
- */
- if (PSPartitionFlag &&
- (SignedPartitionFlag || PartitionChecksumFlag) &&
- EncryptedPartitionFlag) {
- SecureTransferFlag = 0;
- }
-
- /*
- * CPU is used for data transfer in case of non-linear
- * boot device
- */
- if (!LinearBootDeviceFlag) {
- /*
- * PL partition copied to DDR temporary location
- */
- if (PLPartitionFlag) {
- LoadAddr = DDR_TEMP_START_ADDR;
- }
-
- Status = MoveImage(SourceAddr,
- LoadAddr,
- (ImageWordLen << WORD_LENGTH_SHIFT));
- if(Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "Move Image Failed\r\n");
- return XST_FAILURE;
- }
-
- /*
- * As image present at load address
- */
- SourceAddr = LoadAddr;
- }
-
- if ((LinearBootDeviceFlag && PLPartitionFlag &&
- (SignedPartitionFlag || PartitionChecksumFlag)) ||
- (LinearBootDeviceFlag && PSPartitionFlag) ||
- ((!LinearBootDeviceFlag) && PSPartitionFlag && SecureTransferFlag)) {
- /*
- * PL signed partition copied to DDR temporary location
- * using non-secure PCAP for linear boot device
- */
- if(PLPartitionFlag){
- SecureTransferFlag = 0;
- LoadAddr = DDR_TEMP_START_ADDR;
- }
-
- /*
- * Data transfer using PCAP
- */
- Status = PcapDataTransfer((u32*)SourceAddr,
- (u32*)LoadAddr,
- ImageWordLen,
- DataWordLen,
- SecureTransferFlag);
- if(Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "PCAP Data Transfer Failed\r\n");
- return XST_FAILURE;
- }
-
- /*
- * As image present at load address
- */
- SourceAddr = LoadAddr;
- }
-
- /*
- * Load Bitstream partition in to fabric only
- * if checksum and authentication bits are not set
- */
- if (PLPartitionFlag && (!(SignedPartitionFlag || PartitionChecksumFlag))) {
- Status = PcapLoadPartition((u32*)SourceAddr,
- (u32*)Header->LoadAddr,
- Header->ImageWordLen,
- Header->DataWordLen,
- EncryptedPartitionFlag);
- if(Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL, "PCAP Bitstream Download Failed\r\n");
- return XST_FAILURE;
- }
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function load the decrypts partition
-*
-* @param StartAddr Source start address
-* @param DataLength Data length in words
-* @param ImageLength Image length in words
-*
-* @return
-* - XST_SUCCESS if decryption successful
-* - XST_FAILURE if decryption failed
-*
-* @note None
-*
-*******************************************************************************/
-u32 DecryptPartition(u32 StartAddr, u32 DataLength, u32 ImageLength)
-{
- u32 Status;
- u8 SecureTransferFlag =1;
-
- /*
- * Data transfer using PCAP
- */
- Status = PcapDataTransfer((u32*)StartAddr,
- (u32*)StartAddr,
- ImageLength,
- DataLength,
- SecureTransferFlag);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"PCAP Data Transfer failed \r\n");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************/
-/**
-*
-* This function Validate Partition Data by using checksum preset in image
-*
-* @param Partition header pointer
-* @param Partition check sum offset
-* @return
-* - XST_SUCCESS if partition data is ok
-* - XST_FAILURE if partition data is corrupted
-*
-* @note None
-*
-*******************************************************************************/
-u32 ValidateParition(u32 StartAddr, u32 Length, u32 ChecksumOffset)
-{
- u8 Checksum[MD5_CHECKSUM_SIZE];
- u8 CalcChecksum[MD5_CHECKSUM_SIZE];
- u32 Status;
- u32 Index;
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
- /*
- * Prevent WDT reset
- */
- XWdtPs_RestartWdt(&Watchdog);
-#endif
-
- /*
- * Get checksum from flash
- */
- Status = GetPartitionChecksum(ChecksumOffset, &Checksum[0]);
- if(Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- fsbl_printf(DEBUG_INFO, "Actual checksum\r\n");
-
- for (Index = 0; Index < MD5_CHECKSUM_SIZE; Index++) {
- fsbl_printf(DEBUG_INFO, "0x%0x ",Checksum[Index]);
- }
-
- fsbl_printf(DEBUG_INFO, "\r\n");
-
- /*
- * Calculate checksum for the partition
- */
- Status = CalcPartitionChecksum(StartAddr, Length, &CalcChecksum[0]);
- if(Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- fsbl_printf(DEBUG_INFO, "Calculated checksum\r\n");
-
- for (Index = 0; Index < MD5_CHECKSUM_SIZE; Index++) {
- fsbl_printf(DEBUG_INFO, "0x%0x ",CalcChecksum[Index]);
- }
-
- fsbl_printf(DEBUG_INFO, "\r\n");
-
- /*
- * Compare actual checksum with the calculated checksum
- */
- for (Index = 0; Index < MD5_CHECKSUM_SIZE; Index++) {
- if(Checksum[Index] != CalcChecksum[Index]) {
- fsbl_printf(DEBUG_GENERAL, "Error: "
- "Partition DataChecksum 0x%0x!= 0x%0x\r\n",
- Checksum[Index], CalcChecksum[Index]);
- return XST_FAILURE;
- }
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function gets partition checksum from flash
-*
-* @param Check sum offset
-* @param Checksum pointer
-* @return
-* - XST_SUCCESS if checksum read success
-* - XST_FAILURE if unable get checksum
-*
-* @note None
-*
-*******************************************************************************/
-u32 GetPartitionChecksum(u32 ChecksumOffset, u8 *Checksum)
-{
- u32 Status;
-
- Status = MoveImage(ChecksumOffset, (u32)Checksum, MD5_CHECKSUM_SIZE);
- if(Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function calculates the checksum preset in image
-*
-* @param Start address
-* @param Length of the data
-* @param Checksum pointer
-*
-* @return
-* - XST_SUCCESS if Checksum calculate successful
-* - XST_FAILURE if Checksum calculate failed
-*
-* @note None
-*
-*******************************************************************************/
-u32 CalcPartitionChecksum(u32 SourceAddr, u32 DataLength, u8 *Checksum)
-{
- /*
- * Calculate checksum using MD5 algorithm
- */
- md5((u8*)SourceAddr, DataLength, Checksum, 0 );
-
- return XST_SUCCESS;
-}
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/79/100900585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/79/100900585243001d18b399c1eb9b3628
deleted file mode 100644
index f0fec68..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/79/100900585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,33 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 2021.2
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2022 Xilinx, Inc. All Rights Reserved.
-* SPDX-License-Identifier: MIT
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xqspips.h"
-
-/*
-* The configuration table for devices
-*/
-
-XQspiPs_Config XQspiPs_ConfigTable[XPAR_XQSPIPS_NUM_INSTANCES] =
-{
- {
- XPAR_PS7_QSPI_0_DEVICE_ID,
- XPAR_PS7_QSPI_0_BASEADDR,
- XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ,
- XPAR_PS7_QSPI_0_QSPI_MODE
- }
-};
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/79/13dcce565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/79/13dcce565243001d18b399c1eb9b3628
deleted file mode 100644
index 99b1375..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/79/13dcce565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,113 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xbasic_types.h
-*
-*
-* @note Dummy File for backwards compatibility
-*
-
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
-* 7.0 aru 01/21/19 Modified the typedef of u32,u16,u8
-* 7.0 aru 02/06/19 Included stdint.h and stddef.h
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
-#define XBASIC_TYPES_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include
-#include
-
-/** @name Legacy types
- * Deprecated legacy types.
- * @{
- */
-typedef uint8_t Xuint8; /**< unsigned 8-bit */
-typedef char Xint8; /**< signed 8-bit */
-typedef uint16_t Xuint16; /**< unsigned 16-bit */
-typedef short Xint16; /**< signed 16-bit */
-typedef uint32_t Xuint32; /**< unsigned 32-bit */
-typedef long Xint32; /**< signed 32-bit */
-typedef float Xfloat32; /**< 32-bit floating point */
-typedef double Xfloat64; /**< 64-bit double precision FP */
-typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
-
-#if !defined __XUINT64__
-typedef struct
-{
- Xuint32 Upper;
- Xuint32 Lower;
-} Xuint64;
-#endif
-
-/** @name New types
- * New simple types.
- * @{
- */
-#ifndef __KERNEL__
-#ifndef XIL_TYPES_H
-typedef Xuint32 u32;
-typedef Xuint16 u16;
-typedef Xuint8 u8;
-#endif
-#else
-#include
-#endif
-
-#ifndef TRUE
-# define TRUE 1U
-#endif
-
-#ifndef FALSE
-# define FALSE 0U
-#endif
-
-#ifndef NULL
-#define NULL 0U
-#endif
-
-/*
- * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
- * Please use NULL, TRUE and FALSE
- */
-#define XNULL NULL
-#define XTRUE TRUE
-#define XFALSE FALSE
-
-/*
- * This file is deprecated and users
- * should use xil_types.h and xil_assert.h\n\r
- */
-#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
-#warning Please refer the Standalone BSP UG647 for further details
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/79/301764575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/79/301764575243001d18b399c1eb9b3628
deleted file mode 100644
index 6719ab0..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/79/301764575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,62 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file vectors.h
-*
-* This file contains the C level vector prototypes for the ARM Cortex A9 core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 10/20/10 Initial version, moved over from bsp area
-* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 7.2 sd 12/11/19 First release
-* 7.2 sd 03/20/20 Added checking for isolation case
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00 hbm 08/13/10 First Release
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xstatus.h"
-#include "xparameters.h"
-#include "xdmaps.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Variable Definitions ****************************/
-extern XDmaPs_Config XDmaPs_ConfigTable[];
-
-/************************** Function Prototypes *****************************/
-
-/****************************************************************************/
-/**
-*
-* Looks up the device configuration based on the unique device ID. The table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId contains the ID of the device
-*
-* @return
-*
-* A pointer to the configuration structure or NULL if the specified device
-* is not in the system.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId)
-{
- XDmaPs_Config *CfgPtr = NULL;
-
- int i;
-
- for (i = 0; i < XPAR_XDMAPS_NUM_INSTANCES; i++) {
- if (XDmaPs_ConfigTable[i].DeviceId == DeviceId) {
- CfgPtr = &XDmaPs_ConfigTable[i];
- break;
- }
- }
-
- return CfgPtr;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/79/80a050555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/79/80a050555243001d18b399c1eb9b3628
deleted file mode 100644
index b8ea1ea..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/79/80a050555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,163 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xreg_cortexa53.h
-*
-* This header file contains definitions for using inline assembler code. It is
-* written specifically for the GNU compiler.
-*
-* All of the ARM Cortex A53 GPRs, SPRs, and Debug Registers are defined along
-* with the positions of the bits within the registers.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/29/14 First release
-*
-*
-******************************************************************************/
-#ifndef XREG_CORTEXA53_H
-#define XREG_CORTEXA53_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/**
- *@cond nocomments
- */
-
-/* GPRs */
-#define XREG_GPR0 x0
-#define XREG_GPR1 x1
-#define XREG_GPR2 x2
-#define XREG_GPR3 x3
-#define XREG_GPR4 x4
-#define XREG_GPR5 x5
-#define XREG_GPR6 x6
-#define XREG_GPR7 x7
-#define XREG_GPR8 x8
-#define XREG_GPR9 x9
-#define XREG_GPR10 x10
-#define XREG_GPR11 x11
-#define XREG_GPR12 x12
-#define XREG_GPR13 x13
-#define XREG_GPR14 x14
-#define XREG_GPR15 x15
-#define XREG_GPR16 x16
-#define XREG_GPR17 x17
-#define XREG_GPR18 x18
-#define XREG_GPR19 x19
-#define XREG_GPR20 x20
-#define XREG_GPR21 x21
-#define XREG_GPR22 x22
-#define XREG_GPR23 x23
-#define XREG_GPR24 x24
-#define XREG_GPR25 x25
-#define XREG_GPR26 x26
-#define XREG_GPR27 x27
-#define XREG_GPR28 x28
-#define XREG_GPR29 x29
-#define XREG_GPR30 x30
-#define XREG_CPSR cpsr
-
-/* Current Processor Status Register (CPSR) Bits */
-#define XREG_CPSR_MODE_BITS 0x1FU
-#define XREG_CPSR_EL3h_MODE 0xDU
-#define XREG_CPSR_EL3t_MODE 0xCU
-#define XREG_CPSR_EL2h_MODE 0x9U
-#define XREG_CPSR_EL2t_MODE 0x8U
-#define XREG_CPSR_EL1h_MODE 0x5U
-#define XREG_CPSR_EL1t_MODE 0x4U
-#define XREG_CPSR_EL0t_MODE 0x0U
-
-#define XREG_CPSR_IRQ_ENABLE 0x80U
-#define XREG_CPSR_FIQ_ENABLE 0x40U
-
-#define XREG_CPSR_N_BIT 0x80000000U
-#define XREG_CPSR_Z_BIT 0x40000000U
-#define XREG_CPSR_C_BIT 0x20000000U
-#define XREG_CPSR_V_BIT 0x10000000U
-
-/* FPSID bits */
-#define XREG_FPSID_IMPLEMENTER_BIT (24U)
-#define XREG_FPSID_IMPLEMENTER_MASK (0x000000FFU << FPSID_IMPLEMENTER_BIT)
-#define XREG_FPSID_SOFTWARE (0X00000001U<<23U)
-#define XREG_FPSID_ARCH_BIT (16U)
-#define XREG_FPSID_ARCH_MASK (0x0000000FU << FPSID_ARCH_BIT)
-#define XREG_FPSID_PART_BIT (8U)
-#define XREG_FPSID_PART_MASK (0x000000FFU << FPSID_PART_BIT)
-#define XREG_FPSID_VARIANT_BIT (4U)
-#define XREG_FPSID_VARIANT_MASK (0x0000000FU << FPSID_VARIANT_BIT)
-#define XREG_FPSID_REV_BIT (0U)
-#define XREG_FPSID_REV_MASK (0x0000000FU << FPSID_REV_BIT)
-
-/* FPSCR bits */
-#define XREG_FPSCR_N_BIT (0X00000001U << 31U)
-#define XREG_FPSCR_Z_BIT (0X00000001U << 30U)
-#define XREG_FPSCR_C_BIT (0X00000001U << 29U)
-#define XREG_FPSCR_V_BIT (0X00000001U << 28U)
-#define XREG_FPSCR_QC (0X00000001U << 27U)
-#define XREG_FPSCR_AHP (0X00000001U << 26U)
-#define XREG_FPSCR_DEFAULT_NAN (0X00000001U << 25U)
-#define XREG_FPSCR_FLUSHTOZERO (0X00000001U << 24U)
-#define XREG_FPSCR_ROUND_NEAREST (0X00000000U << 22U)
-#define XREG_FPSCR_ROUND_PLUSINF (0X00000001U << 22U)
-#define XREG_FPSCR_ROUND_MINUSINF (0X00000002U << 22U)
-#define XREG_FPSCR_ROUND_TOZERO (0X00000003U << 22U)
-#define XREG_FPSCR_RMODE_BIT (22U)
-#define XREG_FPSCR_RMODE_MASK (0X00000003U << FPSCR_RMODE_BIT)
-#define XREG_FPSCR_STRIDE_BIT (20U)
-#define XREG_FPSCR_STRIDE_MASK (0X00000003U << FPSCR_STRIDE_BIT)
-#define XREG_FPSCR_LENGTH_BIT (16U)
-#define XREG_FPSCR_LENGTH_MASK (0X00000007U << FPSCR_LENGTH_BIT)
-#define XREG_FPSCR_IDC (0X00000001U << 7U)
-#define XREG_FPSCR_IXC (0X00000001U << 4U)
-#define XREG_FPSCR_UFC (0X00000001U << 3U)
-#define XREG_FPSCR_OFC (0X00000001U << 2U)
-#define XREG_FPSCR_DZC (0X00000001U << 1U)
-#define XREG_FPSCR_IOC (0X00000001U << 0U)
-
-/* MVFR0 bits */
-#define XREG_MVFR0_RMODE_BIT (28U)
-#define XREG_MVFR0_RMODE_MASK (0x0000000FU << XREG_MVFR0_RMODE_BIT)
-#define XREG_MVFR0_SHORT_VEC_BIT (24U)
-#define XREG_MVFR0_SHORT_VEC_MASK (0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT)
-#define XREG_MVFR0_SQRT_BIT (20U)
-#define XREG_MVFR0_SQRT_MASK (0x0000000FU << XREG_MVFR0_SQRT_BIT)
-#define XREG_MVFR0_DIVIDE_BIT (16U)
-#define XREG_MVFR0_DIVIDE_MASK (0x0000000FU << XREG_MVFR0_DIVIDE_BIT)
-#define XREG_MVFR0_EXEC_TRAP_BIT (0X00000012U)
-#define XREG_MVFR0_EXEC_TRAP_MASK (0X0000000FU << XREG_MVFR0_EXEC_TRAP_BIT)
-#define XREG_MVFR0_DP_BIT (8U)
-#define XREG_MVFR0_DP_MASK (0x0000000FU << XREG_MVFR0_DP_BIT)
-#define XREG_MVFR0_SP_BIT (4U)
-#define XREG_MVFR0_SP_MASK (0x0000000FU << XREG_MVFR0_SP_BIT)
-#define XREG_MVFR0_A_SIMD_BIT (0U)
-#define XREG_MVFR0_A_SIMD_MASK (0x0000000FU << MVFR0_A_SIMD_BIT)
-
-/* FPEXC bits */
-#define XREG_FPEXC_EX (0X00000001U << 31U)
-#define XREG_FPEXC_EN (0X00000001U << 30U)
-#define XREG_FPEXC_DEX (0X00000001U << 29U)
-
-
-#define XREG_CONTROL_DCACHE_BIT (0X00000001U<<2U)
-#define XREG_CONTROL_ICACHE_BIT (0X00000001U<<12U)
-
-/**
- *@endcond
- */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XREG_CORTEXA53_H */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/79/f2054a545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/79/f2054a545243001d18b399c1eb9b3628
deleted file mode 100644
index 7e29233..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/79/f2054a545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,165 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_testmem.h
-* @addtogroup common_test_utils Test Utilities for Memory and Caches
-*
-* - Cache test: xil_testcache.h contains utility functions to test cache.
-*
-* - I/O test: The Xil_testio.h file contains endian related memory IO functions. A
-* subset of the memory tests can be selected or all of the tests can be run in order.
-* If there is an error detected by a subtest, the test stops and the failure code is
-* returned. Further tests are not run even if all of the tests are selected.
-*
-* - Memory test: The xil_testmem.h file contains utility functions to test memory.
-* A subset of the memory tests can be selected or all of the tests can be run
-* in order. If there is an error detected by a subtest, the test stops and the
-* failure code is returned. Further tests are not run even if all of the tests are selected.
-*
-*
-* Following list describes the supported memory tests:
-*
-* - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
-*
-* - XIL_TESTMEM_INCREMENT: This test
-* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
-* test value for memory.
-*
-* - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
-* uses a walking '1' as the test value for memory.
-* @code
-* location 1 = 0x00000001
-* location 2 = 0x00000002
-* ...
-* @endcode
-*
-* - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
-* This test uses the inverse value of the walking ones test
-* as the test value for memory.
-* @code
-* location 1 = 0xFFFFFFFE
-* location 2 = 0xFFFFFFFD
-* ...
-*@endcode
-*
-* - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
-* This test uses the inverse of the address of the location under test
-* as the test value for memory.
-*
-* - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
-* This test uses the provided patters as the test value for memory.
-* If zero is provided as the pattern the test uses '0xDEADBEEF".
-*
-* @warning
-* The tests are DESTRUCTIVE. Run before any initialized memory spaces
-* have been set up.
-* The address provided to the memory tests is not checked for
-* validity except for the NULL case. It is possible to provide a code-space
-* pointer for this test to start with and ultimately destroy executable code
-* causing random failures.
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 08/25/09 First release
-* 7.5 mus 03/10/21 Added new set of Xil_TestMem32, Xil_TestMem16 and
-* Xil_TestMem8 APIs to support memory test for memory
-* regions mapped at extended addresses
-* (addresses > 4 GB). These new set of APIs would be
-* compiled only for 32 bit Microblaze processor, if
-* XPAR_MICROBLAZE_ADDR_SIZE is greater than 32.
-* It fixes CR#1089129.
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_TESTMEM_H /* prevent circular inclusions */
-#define XIL_TESTMEM_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-/* xutil_memtest defines */
-
-#define XIL_TESTMEM_INIT_VALUE 1U
-
-/** @name Memory subtests
- * @{
- */
-/**
- * See the detailed description of the subtests in the file description.
- */
-#define XIL_TESTMEM_ALLMEMTESTS 0x00U
-#define XIL_TESTMEM_INCREMENT 0x01U
-#define XIL_TESTMEM_WALKONES 0x02U
-#define XIL_TESTMEM_WALKZEROS 0x03U
-#define XIL_TESTMEM_INVERSEADDR 0x04U
-#define XIL_TESTMEM_FIXEDPATTERN 0x05U
-#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN
-/* @} */
-
-#if !defined(__aarch64__) && !defined(__arch64__)
-#define NUM_OF_BITS_IN_BYTE 8U
-#define NUM_OF_BYTES_IN_HW 2U
-#define NUM_OF_BITS_IN_HW 16U
-#define NUM_OF_BYTES_IN_WORD 4U
-#define NUM_OF_BITS_IN_WORD 32U
-#endif
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**
- *@endcond
- */
-
-/************************** Function Prototypes ******************************/
-
-/* xutil_testmem prototypes */
-#if defined(__MICROBLAZE__) && !defined(__arch64__) && (XPAR_MICROBLAZE_ADDR_SIZE > 32)
-extern s32 Xil_TestMem32(u32 AddrLow, u32 AddrHigh, u32 Words, u32 Pattern, u8 Subtest);
-extern s32 Xil_TestMem16(u32 AddrLow, u32 AddrHigh, u32 Words, u16 Pattern, u8 Subtest);
-extern s32 Xil_TestMem8(u32 AddrLow, u32 AddrHigh, u32 Words, u8 Pattern, u8 Subtest);
-#else
-extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
-extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
-extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_test_utils".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/79/f2764c545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/79/f2764c545243001d18b399c1eb9b3628
deleted file mode 100644
index 31156ee..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/79/f2764c545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,96 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xl2cc_counter.h
-*
-* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions
-*
-* xl2cc_counter.h contains APIs for configuring and controlling the event
-* counters in PL310 L2 cache controller.
-* PL310 has two event counters which can be used to count variety of events
-* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions
-* for different configurations which can be used for the event counters to
-* count a set of events.
-*
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
-* inside the APIs
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 7.3 dp 06/25/20 Initial version for armclang
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 First release
-* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
-* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
-* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
-* Define LONG and ULONG datatypes and mask values
-* 7.00 mus 01/07/19 Add cpp extern macro
-* 7.1 aru 08/19/19 Shift the value in UPPER_32_BITS only if it
-* is 64-bit processor
-*
-* MODIFICATION HISTORY :
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 6.6 srm 11/02/17 Added processor specific sleep routines
-* function prototypes.
-*
-*
-*
-******************************************************************************/
-
-#ifndef SLEEP_H
-#define SLEEP_H
-
-#include "xil_types.h"
-#include "xil_io.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*****************************************************************************/
-/**
-*
-* This macro polls an address periodically until a condition is met or till the
-* timeout occurs.
-* The minimum timeout for calling this macro is 100us. If the timeout is less
-* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
-* If the timeout is not a multiple of 100us, it waits for a timeout of
-* the next usec value which is a multiple of 100us.
-*
-* @param IO_func - accessor function to read the register contents.
-* Depends on the register width.
-* @param ADDR - Address to be polled
-* @param VALUE - variable to read the value
-* @param COND - Condition to checked (usually involves VALUE)
-* @param TIMEOUT_US - timeout in micro seconds
-*
-* @return 0 - when the condition is met
-* -1 - when the condition is not met till the timeout period
-*
-* @note none
-*
-*****************************************************************************/
-#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
- ( { \
- u64 timeout = TIMEOUT_US/100; \
- if(TIMEOUT_US%100!=0) \
- timeout++; \
- for(;;) { \
- VALUE = IO_func(ADDR); \
- if(COND) \
- break; \
- else { \
- usleep(100); \
- timeout--; \
- if(timeout==0) \
- break; \
- } \
- } \
- (timeout>0) ? 0 : -1; \
- } )
-
-void usleep(unsigned long useconds);
-void sleep(unsigned int seconds);
-int usleep_R5(unsigned long useconds);
-unsigned sleep_R5(unsigned int seconds);
-int usleep_MB(unsigned long useconds);
-unsigned sleep_MB(unsigned int seconds);
-int usleep_A53(unsigned long useconds);
-unsigned sleep_A53(unsigned int seconds);
-int usleep_A9(unsigned long useconds);
-unsigned sleep_A9(unsigned int seconds);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7b/b0aad6535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7b/b0aad6535243001d18b399c1eb9b3628
deleted file mode 100644
index ce4b290..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7b/b0aad6535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,597 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xscugic.h
-* @addtogroup scugic_v4_6
-* @{
-* @details
-*
-* The generic interrupt controller driver component.
-*
-* The interrupt controller driver uses the idea of priority for the various
-* handlers. Priority is an integer within the range of 1 and 31 inclusive with
-* default of 1 being the highest priority interrupt source. The priorities
-* of the various sources can be dynamically altered as needed through
-* hardware configuration.
-*
-* The generic interrupt controller supports the following
-* features:
-*
-* - specific individual interrupt enabling/disabling
-* - specific individual interrupt acknowledging
-* - attaching specific callback function to handle interrupt source
-* - assigning desired priority to interrupt source if default is not
-* acceptable.
-*
-* Details about connecting the interrupt handler of the driver are contained
-* in the source file specific to interrupt processing, xscugic_intr.c.
-*
-* This driver is intended to be RTOS and processor independent. It works with
-* physical addresses only. Any needs for dynamic memory management, threads
-* or thread mutual exclusion, virtual memory, or cache control must be
-* satisfied by the layer above this driver.
-*
-* Interrupt Vector Tables
-*
-* The device ID of the interrupt controller device is used by the driver as a
-* direct index into the configuration data table. The user should populate the
-* vector table with handlers and callbacks at run-time using the
-* XScuGic_Connect() and XScuGic_Disconnect() functions.
-*
-* Each vector table entry corresponds to a device that can generate an
-* interrupt. Each entry contains an interrupt handler function and an
-* argument to be passed to the handler when an interrupt occurs. The
-* user must use XScuGic_Connect() when the interrupt handler takes an
-* argument other than the base address.
-*
-* Nested Interrupts Processing
-*
-* Nested interrupts are not supported by this driver.
-*
-* NOTE:
-* The generic interrupt controller is not a part of the snoop control unit
-* as indicated by the prefix "scu" in the name of the driver.
-* It is an independent module in APU.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------------
-* 1.00a drg 01/19/00 First release
-* 1.01a sdm 11/09/11 The XScuGic and XScuGic_Config structures have changed.
-* The HandlerTable (of type XScuGic_VectorTableEntry) is
-* moved to XScuGic_Config structure from XScuGic structure.
-*
-* The "Config" entry in XScuGic structure is made as
-* pointer for better efficiency.
-*
-* A new file named as xscugic_hw.c is now added. It is
-* to implement low level driver routines without using
-* any xscugic instance pointer. They are useful when the
-* user wants to use xscugic through device id or
-* base address. The driver routines provided are explained
-* below.
-* XScuGic_DeviceInitialize that takes device id as
-* argument and initializes the device (without calling
-* XScuGic_CfgInitialize).
-* XScuGic_DeviceInterruptHandler that takes device id
-* as argument and calls appropriate handlers from the
-* HandlerTable.
-* XScuGic_RegisterHandler that registers a new handler
-* by taking xscugic hardware base address as argument.
-* LookupConfigByBaseAddress is used to return the
-* corresponding config structure from XScuGic_ConfigTable
-* based on the scugic base address passed.
-* 1.02a sdm 12/20/11 Removed AckBeforeService from the XScuGic_Config
-* structure.
-* 1.03a srt 02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
-* *_hw.h
-* Added APIs
-* - XScuGic_SetPriTrigTypeByDistAddr()
-* - XScuGic_GetPriTrigTypeByDistAddr()
-* (CR 702687)
-* Added support to direct interrupts to the appropriate CPU. Earlier
-* interrupts were directed to CPU1 (hard coded). Now depending
-* upon the CPU selected by the user (xparameters.h), interrupts
-* will be directed to the relevant CPU. This fixes CR 699688.
-* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
-* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
-* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
-* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
-* This is fix for CR#705621.
-* 1.05a hk 06/26/13 Modified tcl to export external interrupts correctly to
-* xparameters.h. Fix for CR's 690505, 708928 & 719359.
-* 2.0 adk 12/10/13 Updated as per the New Tcl API's
-* 2.1 adk 25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.2 asa 02/29/16 Modified DistributorInit function for Zynq AMP case. The
-* distributor is left uninitialized for Zynq AMP. It is assumed
-* that the distributor will be initialized by Linux master. However
-* for CortexR5 case, the earlier code is left unchanged where the
-* the interrupt processor target registers in the distributor is
-* initialized with the corresponding CPU ID on which the application
-* built over the scugic driver runs.
-* These changes fix CR#937243.
-*
-* 3.4 asa 04/07/16 Created a new static function DoDistributorInit to simplify
-* the flow and avoid code duplication. Changes are made for
-* USE_AMP use case for R5. In a scenario (in R5 split mode) when
-* one R5 is operating with A53 in open amp config and other
-* R5 running baremetal app, the existing code
-* had the potential to stop the whole AMP solution to work (if
-* for some reason the R5 running the baremetal app tasked to
-* initialize the Distributor hangs or crashes before initializing).
-* Changes are made so that the R5 under AMP first checks if
-* the distributor is enabled or not and if not, it does the
-* standard Distributor initialization.
-* This fixes the CR#952962.
-* 3.6 ms 01/23/17 Modified xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* kvn 02/17/17 Add support for changing GIC CPU master at run time.
-* kvn 02/28/17 Make the CpuId as static variable and Added new
-* XScugiC_GetCpuId to access CpuId.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 3.7 ms 04/11/17 Modified tcl file to add suffix U for all macro
-* definitions of scugic in xparameters.h
-* 3.8 mus 07/05/17 Updated scugic.tcl to add support for interrupts connected
-* through util_reduced_vector IP(OR gate)
-* mus 07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize
-* the HandlerTable in XScuGic_ConfigTable to 0, it removes
-* the compilation warning in xscugic_g.c. Fix for CR#978736.
-* mus 07/25/17 Updated xdefine_gic_params proc to export correct canonical
-* definitions for pl to ps interrupts.Fix for CR#980534
-* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
-* XScuGic_InterruptUnmapFromCpu, These API's can be used
-* by applications to unmap specific/all interrupts from
-* target CPU.
-* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
-* 4.0 mus 11/22/18 Fixed bugs in software interrupt generation through
-* XScuGic_SoftwareIntr API
-* 4.1 asa 03/30/19 Made changes not to direct each interrupt to all
-* available CPUs by default. This was breaking AMP
-* behavior. Instead every time an interrupt enable
-* request is received, the interrupt was mapped to
-* the respective CPU. There were several other changes
-* made to implement this. This set of changes was to
-* fix CR-1024716.
-* 4.1 mus 06/19/19 Added API's XScuGic_MarkCoreAsleep and
-* XScuGic_MarkCoreAwake to mark processor core as
-* asleep or awake. Fix for CR#1027220.
-* 4.5 asa 03/07/21 Included a header file xil_spinlock.h to ensure that
-* GIC driver can use newly introduced spinlock
-* functionality.
-* 4.6 sk 08/05/21 Fix scugic misrac violations.
-*
-*
-*
-******************************************************************************/
-
-#ifndef XSCUGIC_H /* prevent circular inclusions */
-#define XSCUGIC_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xil_io.h"
-#include "xscugic_hw.h"
-#include "xil_exception.h"
-#include "xil_spinlock.h"
-
-/************************** Constant Definitions *****************************/
-
-#define EFUSE_STATUS_OFFSET 0x10
-#define EFUSE_STATUS_CPU_MASK 0x80
-
-#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
-#define ARMA9
-#endif
-
-#define XSCUGIC500_DCTLR_ARE_NS_ENABLE 0x20
-#define XSCUGIC500_DCTLR_ARE_S_ENABLE 0x10
-/**************************** Type Definitions *******************************/
-
-/* The following data type defines each entry in an interrupt vector table.
- * The callback reference is the base address of the interrupting device
- * for the low level driver and an instance pointer for the high level driver.
- */
-typedef struct
-{
- Xil_InterruptHandler Handler;
- void *CallBackRef;
-} XScuGic_VectorTableEntry;
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct
-{
- u16 DeviceId; /**< Unique ID of device */
- u32 CpuBaseAddress; /**< CPU Interface Register base address */
- u32 DistBaseAddress; /**< Distributor Register base address */
- XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
- Vector table of interrupt handlers */
-} XScuGic_Config;
-
-/**
- * The XScuGic driver instance data. The user is required to allocate a
- * variable of this type for every intc device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct
-{
- XScuGic_Config *Config; /**< Configuration table entry */
- u32 IsReady; /**< Device is initialized and ready */
- u32 UnhandledInterrupts; /**< Intc Statistics */
-} XScuGic;
-
-/************************** Variable Definitions *****************************/
-
-extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Write the given CPU Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
- ((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given CPU Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
- (XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given Distributor Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
- ((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given Distributor Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
-(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given ReDistributor Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_ReDistWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress)+ \
- XSCUGIC_RDIST_OFFSET, (RegOffset), ((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given ReDistributor Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_ReDistReadReg(InstancePtr, RegOffset) \
-(XScuGic_ReadReg((((InstancePtr)->Config->DistBaseAddress)+ \
-XSCUGIC_RDIST_OFFSET), (RegOffset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given ReDistributor SGI PPI Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_ReDistSGIPPIWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress)+ \
- XSCUGIC_RDIST_SGI_PPI_OFFSET, (RegOffset), ((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given ReDistributor SGI PPI Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_ReDistSGIPPIReadReg(InstancePtr, RegOffset) \
-(XScuGic_ReadReg((((InstancePtr)->Config->DistBaseAddress)+ \
- XSCUGIC_RDIST_SGI_PPI_OFFSET), (RegOffset)))
-
-/****************************************************************************/
-/**
-* This function enables system register interface for GIC CPU Interface
-*
-* @param value to be written
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_Enable_SystemReg_CPU_Interface_EL3() mtcp(S3_6_C12_C12_5, 0xF);
-#define XScuGic_Enable_SystemReg_CPU_Interface_EL1() mtcp(S3_0_C12_C12_5, 0xF);
-/****************************************************************************/
-/**
-* This function enables Grou0 interrupts
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_Enable_Group0_Interrupts() mtcp(S3_0_C12_C12_6,0x1);
-/****************************************************************************/
-/**
-* This function enables Group1 interrupts
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#if defined (__aarch64__)
-#if EL1_NONSECURE
-#define XScuGic_Enable_Group1_Interrupts() \
- mtcp (S3_0_C12_C12_7, 0x1 | mfcp(S3_0_C12_C12_7) );
-#else
-#define XScuGic_Enable_Group1_Interrupts() \
- mtcp (S3_6_C12_C12_7, 0x1 | mfcp(S3_6_C12_C12_7) );
-#endif
-#endif
-/****************************************************************************/
-/**
-* This function writes to ICC_SGI0R_EL1
-*
-* @param value to be written
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_WriteICC_SGI0R_EL1(val) mtcp(S3_0_C12_C11_7,val)
-
-/****************************************************************************/
-/**
-* This function writes to ICC_SGI1R_EL1
-*
-* @param value to be written
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_WriteICC_SGI1R_EL1(val) mtcp(S3_0_C12_C11_5,val)
-
-/****************************************************************************/
-/**
-* This function reads ICC_SGI1R_EL1 register
-*
-* @param None
-*
-* @return Value of ICC_SGI1R_EL1 register
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_ReadICC_SGI1R_EL1() mfcp(S3_0_C12_C11_5)
-/****************************************************************************/
-/**
-* This function sets interrupt priority filter
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_set_priority_filter(val) __asm__ __volatile__("msr S3_0_C4_C6_0,%0" : : "r" (val))
-/****************************************************************************/
-/**
-* This function returns interrupt id of highest priority pending interrupt
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#if defined (__aarch64__)
-#if EL3
-#define XScuGic_get_IntID() mfcp(S3_0_C12_C8_0)
-#else
-#define XScuGic_get_IntID() mfcp(S3_0_C12_C12_0)
-#endif
-#endif
-/****************************************************************************/
-/**
-* This function acks the interrupt
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#if defined (__aarch64__)
-#if EL3
-#define XScuGic_ack_Int(val) mtcp(S3_0_C12_C8_1,val)
-#else
-#define XScuGic_ack_Int(val) mtcp(S3_0_C12_C12_1,val)
-#endif
-#endif
-/****************************************************************************/
-/**
-* This macro returns bit position for the specific interrupt's trigger type
-* configuration within GICR_ICFGR0/GICR_ICFGR1 register
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_Get_Rdist_Int_Trigger_Index(IntrId) (((Int_Id%16) & 0x1f) << 2) +1
-/************************** Function Prototypes ******************************/
-
-/*
- * Required functions in xscugic.c
- */
-
-s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
- Xil_InterruptHandler Handler, void *CallBackRef);
-void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id);
-
-void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id);
-void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id);
-
-s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr,
- u32 EffectiveAddr);
-
-s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Identifier);
-
-void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
- u8 *Priority, u8 *Trigger);
-void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
- u8 Priority, u8 Trigger);
-void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Identifier, u32 Int_Id);
-void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Identifier, u32 Int_Id);
-void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Identifier);
-void XScuGic_Stop(XScuGic *InstancePtr);
-void XScuGic_SetCpuID(u32 CpuCoreId);
-u32 XScuGic_GetCpuID(void);
-/*
- * Initialization functions in xscugic_sinit.c
- */
-XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
-
-/*
- * Interrupt functions in xscugic_intr.c
- */
-void XScuGic_InterruptHandler(XScuGic *InstancePtr);
-
-/*
- * Self-test functions in xscugic_selftest.c
- */
-s32 XScuGic_SelfTest(XScuGic *InstancePtr);
-
-#if defined (GICv3)
-void XScuGic_MarkCoreAsleep(XScuGic *InstancePtr);
-void XScuGic_MarkCoreAwake(XScuGic *InstancePtr);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7b/d14f13525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7b/d14f13525243001d18b399c1eb9b3628
deleted file mode 100644
index eda2e2e..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7b/d14f13525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __PLATFORM_CONFIG_H_
-#define __PLATFORM_CONFIG_H_
-
-#define STDOUT_IS_PS7_UART
-#define UART_DEVICE_ID 0
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7b/f0a9e7585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7b/f0a9e7585243001d18b399c1eb9b3628
deleted file mode 100644
index 994854a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7b/f0a9e7585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,59 +0,0 @@
-###############################################################################
-# Copyright (c) 2011 - 2020 Xilinx, Inc. All rights reserved.
-# SPDX-License-Identifier: MIT
-###############################################################################
-DRIVER_LIB_VERSION = v1.0
-
-include config.make
-
-AS=$(ASSEMBLER)
-COMPILER=$(COMPILER)
-ARCHIVER=$(ARCHIVER)
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-ECC_FLAGS += --fpu=VFPv3
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-
-INCLUDES=-I./. -I${INCLUDEDIR}
-INCLUDEFILES=*.h
-
-SRCFILES:=$(wildcard *.c)
-
-ASSEMBLY_SRCFILES:=$(wildcard *.S)
-
-OBJECTS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(wildcard *.c))))
-OBJECTS += $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(wildcard *.s))))
-
-libs: $(LIBS)
-standalone_libs: ${OBJECTS}
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.s
- ${AS} --cpu Cortex-A9 --fpu VFPv3 $(INCLUDES) -o $@ $<
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $<
-
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf $(DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7c/50be64585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7c/50be64585243001d18b399c1eb9b3628
deleted file mode 100644
index fa7d3f2..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7c/50be64585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,539 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2018 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file translation_table.s
-*
-* @addtogroup a53_64_boot_code
-* @{
-*
translation_table.S
-* The translation_table.S contains a static page table required by MMU for
-* cortex-A72. This translation table is flat mapped (input address = output
-* address) with default memory attributes defined for Versal
-* architecture. It utilizes translation granual size of 4KB with 2MB section
-* size for initial 5GB memory and 1GB section size for memory after 5GB.
-* The overview of translation table memory attributes is described below.
-*
-*| Name | Memory Range | Def. in Translation Table |
-*|-----------------------|-----------------------------------|-----------------------------|
-*| DDR | 0x000_0000_0000 - 0x000_7FFF_FFFF | Normal WB Cacheable |
-*| LPD_AFI_FS | 0x000_8000_0000 - 0x000_9FFF_FFFF | Strongly Ordered |
-*| Reserved | 0x000_A000_0000 - 0x000_A3FF_FFFF | Unassigned |
-*| FPD_AFI_0 | 0x000_A400_0000 - 0x000_AFFF_FFFF | Strongly Ordered |
-*| FPD_AFI_1 | 0x000_B000_0000 - 0x000_BFFF_FFFF | Strongly Ordered |
-*| QSPI | 0x000_C000_0000 - 0x000_DFFF_FFFF | Strongly Ordered |
-*| PCIE region 0 | 0x000_E000_0000 - 0x000_EFFF_FFFF | Strongly Ordered |
-*| PMC | 0x000_F000_0000 - 0x000_F7FF_FFFF | Strongly Ordered |
-*| STM_CORESIGHT | 0x000_F800_0000 - 0x000_F8FF_FFFF | Strongly Ordered |
-*| GIC | 0x000_F900_0000 - 0x000_F90F_FFFF | Strongly Ordered |
-*| Reserved | 0x000_F910_0000 - 0x000_FBFF_FFFF | Unassigned |
-*| CPM | 0x000_FC00_0000 - 0x000_FCFF_FFFF | Strongly Ordered |
-*| FPD slaves | 0x000_FD00_0000 - 0x000_FDFF_FFFF | Strongly Ordered |
-*| LPD slaves | 0x000_FE00_0000 - 0x000_FFDF_FFFF | Strongly Ordered |
-*| OCM | 0x000_FFE0_0000 - 0xFFF_FFFF_FFFF | Normal WB Cacheable |
-*| PMC region 0-3 | 0x001_0000_0000 - 0x001_1FFF_FFFF | Strongly Ordered |
-*| Reserved | 0x001_2000_0000 - 0x001_FFFF_FFFF | Unassigned |
-*| ME Array 0-3 | 0x002_0000_0000 - 0x002_FFFF_FFFF | Strongly Ordered |
-*| Reserved | 0x003_0000_0000 - 0x003_FFFF_FFFF | Unassigned |
-*| PL- via PS | 0x004_0000_0000 - 0x005_FFFF_FFFF | Strongly Ordered |
-*| PCIe region 1 | 0x006_0000_0000 - 0x007_FFFF_FFFF | Strongly Ordered |
-*| DDR | 0x008_0000_0000 - 0x00F_FFFF_FFFF | Normal WB Cacheable |
-*| Reserved | 0x010_0000_0000 - 0x03F_FFFF_FFFF | Unassigned |
-*| HBM 0-3 | 0x040_0000_0000 - 0x07F_FFFF_FFFF | Strongly Ordered |
-*| PCIe region 2 | 0x080_0000_0000 - 0x0BF_FFFF_FFFF | Strongly Ordered |
-*| DDR | 0x0C0_0000_0000 - 0x1B7_7FFF_FFFF | Normal WB Cacheable |
-*| Reserved | 0x1B7_8000_0000 - 0x1FF_FFFF_FFFF | Unassigned |
-*| PL- Via NoC | 0x200_0000_0000 - 0x3FF_FFFF_FFFF | Strongly Ordered |
-*| PL- Via PS | 0x400_0000_0000 - 0x4FF_FFFF_FFFF | Strongly Ordered |
-*| DDR CH1-CH3 | 0x500_0000_0000 - 0x7FF_FFFF_FFFF | Normal WB Cacheable |
-*| PL- Via NoC | 0x800_0000_0000 - 0xFFF_FFFF_FFFF | Strongly Ordered |
-*
-* @note
-*
-* For DDR region 0x0000000000 - 0x007FFFFFFF, a system where DDR is less than
-* 2GB, region after DDR and before PL is marked as undefined/reserved in
-* translation table. Region 0xF9100000 - 0xF91FFFFF is reserved memory in
-* 0x00F9000000 - 0x00F91FFFFF range, but it is marked as strongly ordered
-* because minimum section size in translation table section is 2MB.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 7.00 mus 05/21/14 Initial version
-* 7.00 mus 03/16/19 Updated translation table to mark DDR regions as
-* memory, based on the DDR size in hdf
-* 7.1 mus 08/29/19 Updated translation table entries for DDR_CH_1,
-* DDR_CH_2 and DDR_CH_3 based on respective size in hdf
-* 7.3 mus 09/10/20 Updated translation table entries for DDR regions, to
-* support HW designs, where DDR memory is mapped at
-* address other than DDR region base address. It fixes
-* CR#1073099.
-*
-*
-******************************************************************************/
-#include "xparameters.h"
-#include "bspconfig.h"
-
- .globl MMUTableL0
- .globl MMUTableL1
- .globl MMUTableL2
-
- .set UNDEF_START, 0
-
- /* Base addresses for all DDR regions in Versal SoC */
- .set DDR_LOW_0_REGION_START_ADDR, 0x0000000000 /* 0x0000_0000_0000 */
- .set DDR_LOW_1_REGION_START_ADDR, 0x800000000 /* 0x0008_0000_0000 */
- .set DDR_LOW_2_REGION_START_ADDR, 0xC000000000 /* 0x00C0_0000_0000 */
- .set DDR_LOW_3_REGION_START_ADDR, 0x10000000000 /* 0x0100_0000_0000 */
- .set DDR_CH_1_REGION_START_ADDR, 0x50000000000 /* 0x0500_0000_0000 */
- .set DDR_CH_2_REGION_START_ADDR, 0x60000000000 /* 0x0600_0000_0000 */
- .set DDR_CH_3_REGION_START_ADDR, 0x70000000000 /* 0x0700_0000_0000 */
-
- .set reserved, 0x0 /* Fault*/
- #if EL1_NONSECURE
- .set Memory, 0x405 | (2 << 8) | (0x0) /* normal writeback write allocate outer shared read write */
- #else
- .set Memory, 0x405 | (3 << 8) | (0x0) /* normal writeback write allocate inner shared read write */
- #endif
- .set Device, 0x409 | (1 << 53)| (1 << 54) |(0x0) /* strongly ordered read write non executable*/
- .section .mmu_tbl0,"a"
-
-MMUTableL0:
-
-.set SECT, MMUTableL1 /* 0x0000_0000 - 0x7F_FFFF_FFFF */
-.8byte SECT + 0x3
-
-.rept 0x1f
-.set SECT, SECT + 0x1000 /* 0x80_0000_0000 - 0xFFF_FFFF_FFFF */
-.8byte SECT + 0x3
-.endr
-
-
- .section .mmu_tbl1,"a"
-
-MMUTableL1:
-
-.set SECT, MMUTableL2 /* 0x0000_0000 - 0x3FFF_FFFF */
-.8byte SECT + 0x3 /* 1GB DDR */
-
-.rept 0x4 /* 0x4000_0000 - 0x1_3FFF_FFFF */
-.set SECT, SECT + 0x1000 /*1GB DDR, 512MB LPD_AFI_FS, 448MB FPD_AFI_0, 512MB QSPI,
- 256MB PCIe region 0, PMC 128MB, GIC 1 MB, reserved 47MB,
- 2GB other devices and memory, 512 MB PMC */
-.8byte SECT + 0x3
-.endr
-
-.set SECT,0x140000000
-
-.rept 0x3 /* 0x1_4000_0000 - 0x1_FFFF_FFFF */
-.8byte SECT + reserved /* 3GB Reserved */
-.set SECT, SECT + 0x40000000
-.endr
-
-.rept 0x4 /* 0x2_0000_0000 - 0x2_FFFF_FFFF */
-.8byte SECT + Device /* 4GB ME Array 0-3*/
-.set SECT, SECT + 0x40000000
-.endr
-
-.rept 0x4 /* 0x3_0000_0000 - 0x3_FFFF_FFFF */
-.8byte SECT + reserved /* 4GB Reserved */
-.set SECT, SECT + 0x40000000
-.endr
-
-.rept 0x10 /* 0x4_0000_0000 - 0x7_FFFF_FFFF */
-.8byte SECT + Device /* 8GB PL - via PS, 8GB PCIe region1 */
-.set SECT, SECT + 0x40000000
-.endr
-
-.set UNDEF_START, 0
-#ifdef XPAR_AXI_NOC_DDR_LOW_1_BASEADDR
-.set DDR_1_START, XPAR_AXI_NOC_DDR_LOW_1_BASEADDR
-.set DDR_1_END, XPAR_AXI_NOC_DDR_LOW_1_HIGHADDR
-
-.if DDR_1_START > DDR_LOW_1_REGION_START_ADDR
-.set UNDEF_START, (DDR_1_START - DDR_LOW_1_REGION_START_ADDR)
-.set UNDEF_START, (UNDEF_START)/0x40000000
-.endif
-
-.set DDR_1_SIZE, (DDR_1_END - DDR_1_START)+1
-.if DDR_1_SIZE > 0x800000000
-/* If DDR size is larger than 32GB, truncate to 32GB */
-.set DDR_1_REG, 0x20
-.else
-.set DDR_1_REG, DDR_1_SIZE/0x40000000
-.endif
-#else
-.set DDR_1_REG, 0
-#warning "There's no DDR_1 in the HW design. MMU translation table marks 32 GB DDR address space as undefined"
-#endif
-
-.set UNDEF_1_REG, (0x20 - DDR_1_REG - UNDEF_START)
-
-.rept UNDEF_START /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-
-.rept DDR_1_REG /* DDR based on size in hdf*/
-.8byte SECT + Memory
-.set SECT, SECT+0x40000000
-.endr
-
-.rept UNDEF_1_REG /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-.rept 0xC0 /* 0x10_0000_0000 - 0x3F_FFFF_FFFF */
-.8byte SECT + reserved /* 192GB Reserved */
-.set SECT, SECT + 0x40000000
-.endr
-
-.rept 0x100 /* 0x40_0000_0000 - 0x7F_FFFF_FFFF */
-.8byte SECT + Device /* 256GB HBM 0-3*/
-.set SECT, SECT + 0x40000000
-.endr
-
-.rept 0x100 /* 0x80_0000_0000 - 0xBF_FFFF_FFFF */
-.8byte SECT + Device /* 256GB PCIe 2 */
-.set SECT, SECT + 0x40000000
-.endr
-
-.set UNDEF_START, 0
-#ifdef XPAR_AXI_NOC_DDR_LOW_2_BASEADDR
-.set DDR_2_START, XPAR_AXI_NOC_DDR_LOW_2_BASEADDR
-.set DDR_2_END, XPAR_AXI_NOC_DDR_LOW_2_HIGHADDR
-
-.if DDR_2_START > DDR_LOW_2_REGION_START_ADDR
-.set UNDEF_START, (DDR_2_START - DDR_LOW_2_REGION_START_ADDR)
-.set UNDEF_START, (UNDEF_START)/0x40000000
-.endif
-
-.set DDR_2_SIZE, (DDR_2_END - DDR_2_START)+1
-.if DDR_2_SIZE > 0x4000000000
-/* If DDR size is larger than 256 GB, truncate to 256GB */
-.set DDR_2_REG, 0x100
-.else
-.set DDR_2_REG, DDR_2_SIZE/0x40000000
-.endif
-#else
-.set DDR_2_REG, 0
-#warning "There's no DDR_LOW_2 in the HW design. MMU translation table marks 256 GB DDR address space as undefined"
-#endif
-
-.set UNDEF_2_REG, (0x100 - DDR_2_REG - UNDEF_START)
-
-.rept UNDEF_START /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-
-.rept DDR_2_REG /* DDR based on size in hdf 0xC0_0000_0000 - 0xFF_FFFF_FFFF */
-.8byte SECT + Memory /* Maximum DDR region size - 256GB */
-.set SECT, SECT + 0x40000000
-.endr
-
-.rept UNDEF_2_REG /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-
-.set UNDEF_START, 0
-#ifdef XPAR_AXI_NOC_DDR_LOW_3_BASEADDR
-.set DDR_3_START, XPAR_AXI_NOC_DDR_LOW_3_BASEADDR
-.set DDR_3_END, XPAR_AXI_NOC_DDR_LOW_3_HIGHADDR
-
-.if DDR_3_START > DDR_LOW_3_REGION_START_ADDR
-.set UNDEF_START, (DDR_3_START - DDR_LOW_3_REGION_START_ADDR)
-.set UNDEF_START, (UNDEF_START)/0x40000000
-.endif
-
-.set DDR_3_SIZE, (DDR_3_END - DDR_3_START)+1
-.if DDR_3_SIZE > 0xB780000000
-/* If DDR size is larger than 734 GB, truncate to 734GB */
-.set DDR_3_REG, 0x2de
-.else
-.set DDR_3_REG, DDR_3_SIZE/0x40000000
-.endif
-#else
-.set DDR_3_REG, 0
-#warning "There's no DDR_LOW_3 in the HW design. MMU translation table marks 734 GB DDR address space as undefined"
-#endif
-
-.set UNDEF_3_REG, (0x2de - DDR_3_REG - UNDEF_START)
-
-.rept UNDEF_START /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-
-.rept DDR_3_REG /* DDR based on size in hdf 0x100_0000_0000 - 0x1B7_7FFF_FFFF */
-.8byte SECT + Memory /* Maximum DDR region size - 734GB DDR */
-.set SECT, SECT + 0x40000000
-.endr
-
-.rept UNDEF_3_REG /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-
-.rept 0x122 /* 0x1B7_8000_0000 - 0x1FF_FFFF_FFFF */
-.8byte SECT + reserved /* 290GB reserved */
-.set SECT, SECT + 0x40000000
-.endr
-
-.rept 0x800 /* 0x200_0000_0000 - 0x3FF_FFFF_FFFF */
-.8byte SECT + Device /* 2TB PL- via NoC */
-.set SECT, SECT + 0x40000000
-.endr
-
-.rept 0x400 /* 0x400_0000_0000 - 0x4FF_FFFF_FFFF */
-.8byte SECT + Device /* 1TB PL- via PS */
-.set SECT, SECT + 0x40000000
-.endr
-
-.set UNDEF_START, 0
-#ifdef XPAR_AXI_NOC_DDR_CH_1_BASEADDR
-.set DDR_CH_1_START, XPAR_AXI_NOC_DDR_CH_1_BASEADDR
-.set DDR_CH_1_END, XPAR_AXI_NOC_DDR_CH_1_HIGHADDR
-
-.if DDR_CH_1_START > DDR_CH_1_REGION_START_ADDR
-.set UNDEF_START, (DDR_CH_1_START - DDR_CH_1_REGION_START_ADDR)
-.set UNDEF_START, (UNDEF_START)/0x40000000
-.endif
-
-.set DDR_CH_1_SIZE, (DDR_CH_1_END - DDR_CH_1_START)+1
-.if DDR_CH_1_SIZE > 0x010000000000
-/* If DDR size is larger than 1TB, truncate to 1 TB */
-.set DDR_CH_1_REG, 0x400 /* 0x500_0000_0000 - 0x5FF_FFFF_FFFF */
-.else
-.set DDR_CH_1_REG, DDR_CH_1_SIZE/0x40000000
-.endif
-#else
-.set DDR_CH_1_REG, 0
-#warning "There's no DDR_CH_1 in the HW design. MMU translation table marks 1 TB DDR address space as undefined"
-#endif
-
-.set UNDEF_CH_1_REG, (0x400 - DDR_CH_1_REG - UNDEF_START)
-
-.rept UNDEF_START /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-
-.rept DDR_CH_1_REG /* DDR based on size in hdf, Max size 1 TB*/
-.8byte SECT + Memory
-.set SECT, SECT+0x40000000
-.endr
-
-.rept UNDEF_CH_1_REG /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-
-.set UNDEF_START, 0
-#ifdef XPAR_AXI_NOC_DDR_CH_2_BASEADDR
-.set DDR_CH_2_START, XPAR_AXI_NOC_DDR_CH_2_BASEADDR
-.set DDR_CH_2_END, XPAR_AXI_NOC_DDR_CH_2_HIGHADDR
-
-.if DDR_CH_2_START > DDR_CH_2_REGION_START_ADDR
-.set UNDEF_START, (DDR_CH_2_START - DDR_CH_2_REGION_START_ADDR)
-.set UNDEF_START, (UNDEF_START)/0x40000000
-.endif
-
-.set DDR_CH_2_SIZE, (DDR_CH_2_END - DDR_CH_2_START)+1
-.if DDR_CH_2_SIZE > 0x010000000000
-/* If DDR_CH_2 size is larger than 1TB, truncate to 1 TB */
-.set DDR_CH_2_REG, 0x400 /* 0x600_0000_0000 - 0x6FF_FFFF_FFFF */
-.else
-.set DDR_CH_2_REG, DDR_CH_2_SIZE/0x40000000
-.endif
-#else
-.set DDR_CH_2_REG, 0
-#warning "There's no DDR_CH_2 in the HW design. MMU translation table marks 1 TB DDR address space as undefined"
-#endif
-
-.set UNDEF_CH_2_REG, (0x400 - DDR_CH_2_REG - UNDEF_START)
-
-.rept UNDEF_START /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-
-.rept DDR_CH_2_REG /* DDR based on size in hdf, Max size 1 TB*/
-.8byte SECT + Memory
-.set SECT, SECT+0x40000000
-.endr
-
-.rept UNDEF_CH_2_REG /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-
-.set UNDEF_START, 0
-#ifdef XPAR_AXI_NOC_DDR_CH_3_BASEADDR
-.set DDR_CH_3_START, XPAR_AXI_NOC_DDR_CH_3_BASEADDR
-.set DDR_CH_3_END, XPAR_AXI_NOC_DDR_CH_3_HIGHADDR
-
-.if DDR_CH_3_START > DDR_CH_3_REGION_START_ADDR
-.set UNDEF_START, (DDR_CH_3_START - DDR_CH_3_REGION_START_ADDR)
-.set UNDEF_START, (UNDEF_START)/0x40000000
-.endif
-
-.set DDR_CH_3_SIZE, (DDR_CH_3_END - DDR_CH_3_START)+1
-.if DDR_CH_3_SIZE > 0x010000000000
-/* If DDR_CH_3 size is larger than 1TB, truncate to 1 TB */
-.set DDR_CH_3_REG, 0x400 /* 0x700_0000_0000 - 0x7FF_FFFF_FFFF */
-.else
-.set DDR_CH_3_REG, DDR_CH_3_SIZE/0x40000000
-.endif
-#else
-.set DDR_CH_3_REG, 0
-#warning "There's no DDR_CH_3 in the HW design. MMU translation table marks 1 TB DDR address space as undefined"
-#endif
-
-.set UNDEF_CH_3_REG, (0x400 - DDR_CH_3_REG - UNDEF_START)
-
-.rept UNDEF_START /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-
-.rept DDR_CH_3_REG /* DDR based on size in hdf, Max size 1 TB*/
-.8byte SECT + Memory
-.set SECT, SECT+0x40000000
-.endr
-
-.rept UNDEF_CH_3_REG /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-
-
-.rept 0x2000 /* 0x800_0000_0000 - 0xFFF_FFFF_FFFF */
-.8byte SECT + Device /* 8TB PL- via NoC*/
-.set SECT, SECT + 0x40000000
-.endr
-
-.section .mmu_tbl2,"a"
-
-MMUTableL2:
-
-.set SECT, 0
-
-.set UNDEF_START, 0
-#ifdef XPAR_AXI_NOC_DDR_LOW_0_BASEADDR
-.set DDR_0_START, XPAR_AXI_NOC_DDR_LOW_0_BASEADDR
-.set DDR_0_END, XPAR_AXI_NOC_DDR_LOW_0_HIGHADDR
-
-.if DDR_0_START > DDR_LOW_0_REGION_START_ADDR
-.set UNDEF_START, (DDR_0_START - DDR_LOW_0_REGION_START_ADDR)
-.set UNDEF_START, (UNDEF_START)/0x200000
-.endif
-
-.set DDR_0_SIZE, (DDR_0_END - DDR_0_START)+1
-.if DDR_0_SIZE > 0x80000000
-/* If DDR size is larger than 2GB, truncate to 2GB */
-.set DDR_0_REG, 0x400
-.else
-.set DDR_0_REG, DDR_0_SIZE/0x200000
-.endif
-#else
-.set DDR_0_REG, 0
-#warning "There's no DDR_0 in the HW design. MMU translation table marks 2 GB DDR address space as undefined"
-#endif
-
-.set UNDEF_0_REG, (0x400 - DDR_0_REG - UNDEF_START)
-
-.rept UNDEF_START /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x200000
-.endr
-
-.rept DDR_0_REG /* DDR based on size in hdf*/
-.8byte SECT + Memory
-.set SECT, SECT+0x200000
-.endr
-
-.rept UNDEF_0_REG /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x200000
-.endr
-
-
-.rept 0x0100 /* 0x8000_0000 - 0xBFFF_FFFF */
-.8byte SECT + Device /* 512MB LPD AFI */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x020 /* 0xA000_0000 - 0xA3FF_FFFF */
-.8byte SECT + reserved /* 64MB reserved*/
-.set SECT, SECT+0x200000
-.endr
-
-
-.rept 0x60 /* 0xA400_0000 - 0xAFFF_FFFF */
-.8byte SECT + Device /* 192MB FPD AFI 0 */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x80 /* 0xB000_0000 - 0xBFFF_FFFF */
-.8byte SECT + Device /* 192MB FPD AFI 1 */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x100 /* 0xC000_0000 - 0xDFFF_FFFF */
-.8byte SECT + Device /* 512MB QSPI */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x080 /* 0xE000_0000 - 0xEFFF_FFFF */
-.8byte SECT + Device /* 256MB lower PCIe */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x040 /* 0xF000_0000 - 0xF7FF_FFFF */
-.8byte SECT + Device /* 128MB PMC */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x08 /* 0xF800_0000 - 0xF8FF_FFFF */
-.8byte SECT + Device /* 16MB coresight */
-.set SECT, SECT+0x200000
-.endr
-
-/* 1MB GIC is marked for 2MB region as the minimum block size in
- translation table is 2MB and adjacent 47MB reserved region is
- converted to 46MB */
-.8byte SECT + Device /* 0xF910_0000 - 0xF90F_FFFF */
-
-/* Reserved 46MB 0xF91FFFFF - 0xFBFFFFFF*/
-.rept 0x17 /* 0xF91F_FFFF - 0xFBFF_FFFF */
-.set SECT, SECT+0x200000
-.8byte SECT + reserved /* 46MB reserved */
-.endr
-
-.rept 0x1F /* 0xFC00_0000 - 0xFFDF_FFFF */
-.set SECT, SECT+0x200000
-.8byte SECT + Device /* 16MB CPM,16MB FPS, 30MB LPS slaves */
-.endr
-
-.set SECT, SECT+0x200000 /* 0xFFE0_0000 - 0xFFFF_FFFF*/
-.8byte SECT + Memory /*2MB OCM/TCM*/
-
-.rept 0x100 /* 0x1_0000_0000 - 0x1_1FFF_FFFF */
-.set SECT, SECT+0x200000
-.8byte SECT + Device /* 512MB PMC 0-3 */
-.endr
-
-.rept 0x100 /* 0x1_2000_0000 - 0x1_3FFF_FFFF */
-.set SECT, SECT+0x200000
-.8byte SECT + reserved /* 512MB reserved */
-.endr
-.end
-/**
-* @} End of "addtogroup a53_64_boot_code".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7c/b0c2ba575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7c/b0c2ba575243001d18b399c1eb9b3628
deleted file mode 100644
index 3c23a5f..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7c/b0c2ba575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,25 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xcpu_cortexa9.h
-* @addtogroup cpu_cortexa9_v2_11
-* @{
-* @details
-*
-* dummy file
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------------
-* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID
-* parameter of cpu_cortexa9 in xparameters.h
-# 2.7 mus 07/03/18 Updated tcl to not to add default flags forcefully into
-# extra compiler flags. Now, user can remove default flags
-# from extra compiler flags. It fixes CR#998768.
-******************************************************************************/
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7c/b23deb565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7c/b23deb565243001d18b399c1eb9b3628
deleted file mode 100644
index 5a1bda3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7c/b23deb565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,76 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_testio.h
-*
-* @addtogroup common_test_utils Test Utilities for Memory and Caches
-*
I/O test
-* The xil_testio.h file contains utility functions to test endian related memory
-* IO functions.
-*
-* A subset of the memory tests can be selected or all of the tests can be run
-* in order. If there is an error detected by a subtest, the test stops and the
-* failure code is returned. Further tests are not run even if all of the tests
-* are selected.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00 hbm 08/05/09 First release
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 12/11/09 Initial release
-*
-*
-*
-* @note
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_CACHE_VXWORKS_H
-#define XIL_CACHE_VXWORKS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "vxWorks.h"
-#include "vxLib.h"
-#include "sysLibExtra.h"
-#include "cacheLib.h"
-
-#if (CPU_FAMILY==PPC)
-
-#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
-
-#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
-
-#define Xil_DCacheInvalidateRange(Addr, Len) \
- cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
-
-#define Xil_DCacheFlushRange(Addr, Len) \
- cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
-
-#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
-
-#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
-
-#define Xil_ICacheInvalidateRange(Addr, Len) \
- cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
-
-
-#else
-#error "Unknown processor / architecture. Must be PPC for VxWorks."
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
- *@endcond
- */
\ No newline at end of file
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7d/40e472575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7d/40e472575243001d18b399c1eb9b3628
deleted file mode 100644
index b733141..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7d/40e472575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,215 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xemacps_bdring.h
-* @addtogroup emacps_v3_15
-* @{
-*
-* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
-* DMA functionalities.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 First release
-* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
-* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
-* changed to volatile.
-*
-*
-*
-******************************************************************************/
-
-#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */
-#define XEMACPS_BDRING_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/**************************** Type Definitions *******************************/
-
-/** This is an internal structure used to maintain the DMA list */
-typedef struct {
- UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
- UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */
- UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */
- u32 Length; /**< Total size of ring in bytes */
- u32 RunState; /**< Flag to indicate DMA is started */
- u32 Separation; /**< Number of bytes between the starting address
- of adjacent BDs */
- XEmacPs_Bd *FreeHead;
- /**< First BD in the free group */
- XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
- XEmacPs_Bd *HwHead; /**< First BD in the work group */
- XEmacPs_Bd *HwTail; /**< Last BD in the work group */
- XEmacPs_Bd *PostHead;
- /**< First BD in the post-work group */
- XEmacPs_Bd *BdaRestart;
- /**< BDA to load when channel is started */
-
- volatile u32 HwCnt; /**< Number of BDs in work group */
- u32 PreCnt; /**< Number of BDs in pre-work group */
- u32 FreeCnt; /**< Number of allocatable BDs in the free group */
- u32 PostCnt; /**< Number of BDs in post-work group */
- u32 AllCnt; /**< Total Number of BDs for channel */
-} XEmacPs_BdRing;
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
-* Use this macro at initialization time to determine how many BDs will fit
-* in a BD list within the given memory constraints.
-*
-* The results of this macro can be provided to XEmacPs_BdRingCreate().
-*
-* @param Alignment specifies what byte alignment the BDs must fall on and
-* must be a power of 2 to get an accurate calculation (32, 64, 128,...)
-* @param Bytes is the number of bytes to be used to store BDs.
-*
-* @return Number of BDs that can fit in the given memory area
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
-*
-******************************************************************************/
-#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \
- (u32)((Bytes) / (sizeof(XEmacPs_Bd)))
-
-/*****************************************************************************/
-/**
-* Use this macro at initialization time to determine how many bytes of memory
-* is required to contain a given number of BDs at a given alignment.
-*
-* @param Alignment specifies what byte alignment the BDs must fall on. This
-* parameter must be a power of 2 to get an accurate calculation (32, 64,
-* 128,...)
-* @param NumBd is the number of BDs to calculate memory size requirements for
-*
-* @return The number of bytes of memory required to create a BD list with the
-* given memory constraints.
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
-*
-******************************************************************************/
-#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \
- (u32)(sizeof(XEmacPs_Bd) * (NumBd))
-
-/****************************************************************************/
-/**
-* Return the total number of BDs allocated by this channel with
-* XEmacPs_BdRingCreate().
-*
-* @param RingPtr is the DMA channel to operate on.
-*
-* @return The total number of BDs allocated for this channel.
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
-
-/****************************************************************************/
-/**
-* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
-* processing.
-*
-* @param RingPtr is the DMA channel to operate on.
-*
-* @return The number of BDs currently allocatable.
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt)
-
-/****************************************************************************/
-/**
-* Return the next BD from BdPtr in a list.
-*
-* @param RingPtr is the DMA channel to operate on.
-* @param BdPtr is the BD to operate on.
-*
-* @return The next BD in the list relative to the BdPtr parameter.
-*
-* @note
-* C-style signature:
-* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
-* XEmacPs_Bd *BdPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingNext(RingPtr, BdPtr) \
- (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ? \
- (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) : \
- (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
-
-/****************************************************************************/
-/**
-* Return the previous BD from BdPtr in the list.
-*
-* @param RingPtr is the DMA channel to operate on.
-* @param BdPtr is the BD to operate on
-*
-* @return The previous BD in the list relative to the BdPtr parameter.
-*
-* @note
-* C-style signature:
-* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
-* XEmacPs_Bd *BdPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \
- (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \
- (XEmacPs_Bd*)(RingPtr)->HighBdAddr : \
- (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Scatter gather DMA related functions in xemacps_bdring.c
- */
-LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
- UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
-LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
- u8 Direction);
-LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd ** BdSetPtr);
-LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr);
-LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr);
-LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr);
-u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
- XEmacPs_Bd ** BdSetPtr);
-u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
- XEmacPs_Bd ** BdSetPtr);
-LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
-
-void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* end of protection macros */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7d/61d379555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7d/61d379555243001d18b399c1eb9b3628
deleted file mode 100644
index 454e534..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7d/61d379555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,92 +0,0 @@
-/*******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-*******************************************************************************/
-
-
-#ifndef __XFPD_XMPU_SINK_H__
-#define __XFPD_XMPU_SINK_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *@cond nocomments
- */
-
-/**
- * XfpdXmpuSink Base Address
- */
-#define XFPD_XMPU_SINK_BASEADDR 0xFD4F0000UL
-
-/**
- * Register: XfpdXmpuSinkErrSts
- */
-#define XFPD_XMPU_SINK_ERR_STS ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF00UL )
-#define XFPD_XMPU_SINK_ERR_STS_RSTVAL 0x00000000UL
-
-#define XFPD_XMPU_SINK_ERR_STS_RDWR_SHIFT 31UL
-#define XFPD_XMPU_SINK_ERR_STS_RDWR_WIDTH 1UL
-#define XFPD_XMPU_SINK_ERR_STS_RDWR_MASK 0x80000000UL
-#define XFPD_XMPU_SINK_ERR_STS_RDWR_DEFVAL 0x0UL
-
-#define XFPD_XMPU_SINK_ERR_STS_ADDR_SHIFT 0UL
-#define XFPD_XMPU_SINK_ERR_STS_ADDR_WIDTH 12UL
-#define XFPD_XMPU_SINK_ERR_STS_ADDR_MASK 0x00000fffUL
-#define XFPD_XMPU_SINK_ERR_STS_ADDR_DEFVAL 0x0UL
-
-/**
- * Register: XfpdXmpuSinkIsr
- */
-#define XFPD_XMPU_SINK_ISR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF10UL )
-#define XFPD_XMPU_SINK_ISR_RSTVAL 0x00000000UL
-
-#define XFPD_XMPU_SINK_ISRADDRDECDERR_SHIFT 0UL
-#define XFPD_XMPU_SINK_ISRADDRDECDERR_WIDTH 1UL
-#define XFPD_XMPU_SINK_ISRADDRDECDERR_MASK 0x00000001UL
-#define XFPD_XMPU_SINK_ISRADDRDECDERR_DEFVAL 0x0UL
-
-/**
- * Register: XfpdXmpuSinkImr
- */
-#define XFPD_XMPU_SINK_IMR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF14UL )
-#define XFPD_XMPU_SINK_IMR_RSTVAL 0x00000001UL
-
-#define XFPD_XMPU_SINK_IMRADDRDECDERR_SHIFT 0UL
-#define XFPD_XMPU_SINK_IMRADDRDECDERR_WIDTH 1UL
-#define XFPD_XMPU_SINK_IMRADDRDECDERR_MASK 0x00000001UL
-#define XFPD_XMPU_SINK_IMRADDRDECDERR_DEFVAL 0x1UL
-
-/**
- * Register: XfpdXmpuSinkIer
- */
-#define XFPD_XMPU_SINK_IER ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF18UL )
-#define XFPD_XMPU_SINK_IER_RSTVAL 0x00000000UL
-
-#define XFPD_XMPU_SINK_IERADDRDECDERR_SHIFT 0UL
-#define XFPD_XMPU_SINK_IERADDRDECDERR_WIDTH 1UL
-#define XFPD_XMPU_SINK_IERADDRDECDERR_MASK 0x00000001UL
-#define XFPD_XMPU_SINK_IERADDRDECDERR_DEFVAL 0x0UL
-
-/**
- * Register: XfpdXmpuSinkIdr
- */
-#define XFPD_XMPU_SINK_IDR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF1CUL )
-#define XFPD_XMPU_SINK_IDR_RSTVAL 0x00000000UL
-
-#define XFPD_XMPU_SINK_IDRADDRDECDERR_SHIFT 0UL
-#define XFPD_XMPU_SINK_IDRADDRDECDERR_WIDTH 1UL
-#define XFPD_XMPU_SINK_IDRADDRDECDERR_MASK 0x00000001UL
-#define XFPD_XMPU_SINK_IDRADDRDECDERR_DEFVAL 0x0UL
-
-/**
- *@endcond
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XFPD_XMPU_SINK_H__ */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7d/a0e3c0545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7d/a0e3c0545243001d18b399c1eb9b3628
deleted file mode 100644
index 5feeb49..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7d/a0e3c0545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,39 +0,0 @@
-DRIVER_LIB_VERSION = 1.0
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I$(INCLUDEDIR)
-
-SRCFILES:=$(wildcard *.c)
-
-OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
-
-libs: $(OBJECTS)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf $(DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7d/a1165c595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7d/a1165c595243001d18b399c1eb9b3628
deleted file mode 100644
index 59f64c3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7d/a1165c595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,55 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-* @file microblaze_enable_interrupts.S
-*
-* @addtogroup microblaze_pseudo_asm_macro
-* @{
-*
microblaze_enable_interrupts.S
-* - API to Enable Interrupts: void microblaze_enable_interrupts(void)
-*
-* This API Enables interrupts on the MicroBlaze processor. When the MicroBlaze
-* processor starts up, interrupts are disabled. Interrupts must be explicitly
-* turned on using this function.
-*
-*
-*
-* File : microblaze_enable_interrupts.s
-* Date : 2002, March 20.
-* Company: Xilinx
-* Group : Emerging Software Technologies
-*
-* Summary:
-* Enable interrupts on the microblaze.
-*
-*
-******************************************************************************/
-
-#include "xparameters.h"
-
- .text
- .globl microblaze_enable_interrupts
- .ent microblaze_enable_interrupts
- .align 2
-microblaze_enable_interrupts:
-#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
- rtsd r15, 8
- msrset r0, 0x2
- nop
-#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- #Read the MSR register
- mfs r12, rmsr
- #Set the interrupt enable bit
- ori r12, r12, 0x2
- #Save the MSR register
- mts rmsr, r12
- #Return
- rtsd r15, 8
- nop
-#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- .end microblaze_enable_interrupts
-/**
-* @} End of "addtogroup microblaze_pseudo_asm_macro".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7d/b107ee575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7d/b107ee575243001d18b399c1eb9b3628
deleted file mode 100644
index 61b2fae..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7d/b107ee575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,832 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xgpiops.c
-* @addtogroup gpiops_v3_9
-* @{
-*
-* The XGpioPs driver. Functions in this file are the minimum required functions
-* for this driver. See xgpiops.h for a detailed description of the driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sv 01/15/10 First Release
-* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
-* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
-* relevant to Zynq device. The interrupts are disabled
-* for output pins on all banks during initialization.
-* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
-* 3.1 aru 07/13/18 Resolved doxygen reported warnings. CR# 1006331.
-* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
-* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
-* in safety mode and modified the code such as
-* Use of mixed mode arithmetic,Declared the pointer param
-* as Pointer to const,Casting operation to a pointer,
-* Literal value requires a U suffix.
-* 3.5 sne 03/13/19 Added Versal support.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xgpiops.h"
-
-/************************** Constant Definitions *****************************/
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-
-/************************** Function Prototypes ******************************/
-
-void StubHandler(void *CallBackRef, u32 Bank, u32 Status); /**< Stub handler */
-
-/*****************************************************************************/
-/**
-*
-* This function initializes a XGpioPs instance/driver.
-* All members of the XGpioPs instance structure are initialized and
-* StubHandlers are assigned to the Bank Status Handlers.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param ConfigPtr points to the XGpioPs device configuration structure.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. If the address translation is not used then the
-* physical address should be passed.
-* Unexpected errors may occur if the address mapping is changed
-* after this function is invoked.
-*
-* @return XST_SUCCESS always.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
- u32 EffectiveAddr)
-{
- s32 Status = (s32)0;
- u8 i;
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
- Xil_AssertNonvoid(EffectiveAddr != (u32)0);
- /*
- * Set some default values for instance data, don't indicate the device
- * is ready to use until everything has been initialized successfully.
- */
- InstancePtr->IsReady = 0U;
- InstancePtr->GpioConfig.BaseAddr = EffectiveAddr;
- InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId;
- InstancePtr->Handler = (XGpioPs_Handler)StubHandler;
- InstancePtr->Platform = XGetPlatform_Info();
-
- /* Initialize the Bank data based on platform */
- if (InstancePtr->Platform == (u32)XPLAT_ZYNQ_ULTRA_MP) {
- /*
- * Max pins in the ZynqMP GPIO device
- * 0 - 25, Bank 0
- * 26 - 51, Bank 1
- * 52 - 77, Bank 2
- * 78 - 109, Bank 3
- * 110 - 141, Bank 4
- * 142 - 173, Bank 5
- */
- InstancePtr->MaxPinNum = (u32)174;
- InstancePtr->MaxBanks = (u8)6;
- }
- else if (InstancePtr->Platform == (u32)XPLAT_VERSAL)
- {
- if(InstancePtr->PmcGpio == (u32)FALSE)
- {
- /* Max pins in the PS_GPIO devices
- * 0 -25, Bank 0
- * 26-57, Bank 3
- */
- InstancePtr->MaxPinNum = (u32)58;
- InstancePtr->MaxBanks = (u8)4;
- }
- else
- {
- /* Max pins in the PMC_GPIO devices
- * 0 - 25,Bank 0
- * 26 - 51,Bank 1
- * 52 - 83,Bank 3
- * 84 - 115, Bank 4
- */
- InstancePtr->MaxPinNum = (u32)116;
- InstancePtr->MaxBanks = (u8)5;
- }
- }
- else {
- /*
- * Max pins in the GPIO device
- * 0 - 31, Bank 0
- * 32 - 53, Bank 1
- * 54 - 85, Bank 2
- * 86 - 117, Bank 3
- */
- InstancePtr->MaxPinNum = (u32)118;
- InstancePtr->MaxBanks = (u8)4;
- }
-
- /*
- * By default, interrupts are not masked in GPIO. Disable
- * interrupts for all pins in all the 4 banks.
- */
- for (i=(u8)0U;iMaxBanks;i++) {
- if (InstancePtr->Platform == XPLAT_VERSAL){
- if(InstancePtr->PmcGpio == (u32)FALSE)
- {
- if((i== (u8)XGPIOPS_ONE)||(i== (u8)XGPIOPS_TWO))
- {
- continue;
- }
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
- }
- else
- {
- if(i==(u32)XGPIOPS_TWO)
- {
- continue;
- }
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
-
- }
- }
- else
- {
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
- }
- }
-
- /* Indicate the component is now ready to use. */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* Read the Data register of the specified GPIO bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-*
-* @return Current value of the Data register.
-*
-* @note This function is used for reading the state of all the GPIO pins
-* of specified bank.
-*
-*****************************************************************************/
-u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertNonvoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
- XGPIOPS_DATA_RO_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* Read Data from the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number for which the data has to be read.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-* See xgpiops.h for the mapping of the pin numbers in the banks.
-*
-* @return Current value of the Pin (0 or 1).
-*
-* @note This function is used for reading the state of the specified
-* GPIO pin.
-*
-*****************************************************************************/
-u32 XGpioPs_ReadPin(const XGpioPs *InstancePtr, u32 Pin)
-{
- u8 Bank;
- u8 PinNumber;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
- return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
- XGPIOPS_DATA_RO_OFFSET) >> (u32)PinNumber) & (u32)1;
-
-}
-
-/****************************************************************************/
-/**
-*
-* Write to the Data register of the specified GPIO bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param Data is the value to be written to the Data register.
-*
-* @return None.
-*
-* @note This function is used for writing to all the GPIO pins of
-* the bank. The previous state of the pins is not maintained.
-*
-*****************************************************************************/
-void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertVoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
- XGPIOPS_DATA_OFFSET, Data);
-}
-
-/****************************************************************************/
-/**
-*
-* Write data to the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number to which the Data is to be written.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-* @param Data is the data to be written to the specified pin (0 or 1).
-*
-* @return None.
-*
-* @note This function does a masked write to the specified pin of
-* the specified GPIO bank. The previous state of other pins
-* is maintained.
-*
-*****************************************************************************/
-void XGpioPs_WritePin(const XGpioPs *InstancePtr, u32 Pin, u32 Data)
-{
- u32 RegOffset;
- u32 Value;
- u8 Bank;
- u8 PinNumber;
- u32 DataVar = Data;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
-
- if (PinNumber > 15U) {
- /* There are only 16 data bits in bit maskable register. */
- PinNumber -= (u8)16;
- RegOffset = XGPIOPS_DATA_MSW_OFFSET;
- } else {
- RegOffset = XGPIOPS_DATA_LSW_OFFSET;
- }
-
- /*
- * Get the 32 bit value to be written to the Mask/Data register where
- * the upper 16 bits is the mask and lower 16 bits is the data.
- */
- DataVar &= (u32)0x01;
- Value = ~((u32)1 << (PinNumber + 16U)) & ((DataVar << PinNumber) | 0xFFFF0000U);
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_DATA_MASK_OFFSET) +
- RegOffset, Value);
-
-}
-
-
-
-/****************************************************************************/
-/**
-*
-* Set the Direction of the pins of the specified GPIO Bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param Direction is the 32 bit mask of the Pin direction to be set for
-* all the pins in the Bank. Bits with 0 are set to Input mode,
-* bits with 1 are set to Output Mode.
-*
-* @return None.
-*
-* @note This function is used for setting the direction of all the pins
-* in the specified bank. The previous state of the pins is
-* not maintained.
-*
-*****************************************************************************/
-void XGpioPs_SetDirection(const XGpioPs *InstancePtr, u8 Bank, u32 Direction)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertVoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_DIRM_OFFSET, Direction);
-}
-
-/****************************************************************************/
-/**
-*
-* Set the Direction of the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number to which the Data is to be written.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-* @param Direction is the direction to be set for the specified pin.
-* Valid values are 0 for Input Direction, 1 for Output Direction.
-*
-* @return None.
-*
-*****************************************************************************/
-void XGpioPs_SetDirectionPin(const XGpioPs *InstancePtr, u32 Pin, u32 Direction)
-{
- u8 Bank;
- u8 PinNumber;
- u32 DirModeReg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
- Xil_AssertVoid(Direction <= (u32)1);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
- DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_DIRM_OFFSET);
-
- if (Direction!=(u32)0) { /* Output Direction */
- DirModeReg |= ((u32)1 << (u32)PinNumber);
- } else { /* Input Direction */
- DirModeReg &= ~ ((u32)1 << (u32)PinNumber);
- }
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_DIRM_OFFSET, DirModeReg);
-}
-
-/****************************************************************************/
-/**
-*
-* Get the Direction of the pins of the specified GPIO Bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-*
-* @return Returns a 32 bit mask of the Direction register. Bits with 0 are
-* in Input mode, bits with 1 are in Output Mode.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertNonvoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_DIRM_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* Get the Direction of the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number for which the Direction is to be
-* retrieved.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*
-* @return Direction of the specified pin.
-* - 0 for Input Direction
-* - 1 for Output Direction
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpioPs_GetDirectionPin(const XGpioPs *InstancePtr, u32 Pin)
-{
- u8 Bank;
- u8 PinNumber;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
-
- return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_DIRM_OFFSET) >> (u32)PinNumber) & (u32)1;
-}
-
-/****************************************************************************/
-/**
-*
-* Set the Output Enable of the pins of the specified GPIO Bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param OpEnable is the 32 bit mask of the Output Enables to be set for
-* all the pins in the Bank. The Output Enable of bits with 0 are
-* disabled, the Output Enable of bits with 1 are enabled.
-*
-* @return None.
-*
-* @note This function is used for setting the Output Enables of all the
-* pins in the specified bank. The previous state of the Output
-* Enables is not maintained.
-*
-*****************************************************************************/
-void XGpioPs_SetOutputEnable(const XGpioPs *InstancePtr, u8 Bank, u32 OpEnable)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertVoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_OUTEN_OFFSET, OpEnable);
-}
-
-/****************************************************************************/
-/**
-*
-* Set the Output Enable of the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number to which the Data is to be written.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-* @param OpEnable specifies whether the Output Enable for the specified
-* pin should be enabled.
-* Valid values are 0 for Disabling Output Enable,
-* 1 for Enabling Output Enable.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnable)
-{
- u8 Bank;
- u8 PinNumber;
- u32 OpEnableReg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
- Xil_AssertVoid(OpEnable <= (u32)1);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
-
- OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_OUTEN_OFFSET);
-
- if (OpEnable != (u32)0) { /* Enable Output Enable */
- OpEnableReg |= ((u32)1 << (u32)PinNumber);
- } else { /* Disable Output Enable */
- OpEnableReg &= ~ ((u32)1 << (u32)PinNumber);
- }
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_OUTEN_OFFSET, OpEnableReg);
-}
-/****************************************************************************/
-/**
-*
-* Get the Output Enable status of the pins of the specified GPIO Bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-*
-* @return Returns a a 32 bit mask of the Output Enable register.
-* Bits with 0 are in Disabled state, bits with 1 are in
-* Enabled State.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertNonvoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_OUTEN_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* Get the Output Enable status of the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number for which the Output Enable status is to
-* be retrieved.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*
-* @return Output Enable of the specified pin.
-* - 0 if Output Enable is disabled for this pin
-* - 1 if Output Enable is enabled for this pin
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin)
-{
- u8 Bank;
- u8 PinNumber;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
-
- return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_OUTEN_OFFSET) >> (u32)PinNumber) & (u32)1;
-}
-
-/****************************************************************************/
-/**
-*
-* Get the Bank number and the Pin number in the Bank, for the given PinNumber
-* in the GPIO device.
-*
-* @param PinNumber is the Pin number in the GPIO device.
-* @param BankNumber returns the Bank in which this GPIO pin is present.
-* Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
-* @param PinNumberInBank returns the Pin Number within the Bank.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#ifdef versal
-void XGpioPs_GetBankPin(const XGpioPs *InstancePtr,u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
-#else
-void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
-#endif
-{
- u32 XGpioPsPinTable[6] = {0};
-#ifdef versal
- u8 i=(u8)0;
-#endif
- u32 Platform = XGetPlatform_Info();
-
- if (Platform == (u32)XPLAT_ZYNQ_ULTRA_MP) {
- /*
- * This structure defines the mapping of the pin numbers to the banks when
- * the driver APIs are used for working on the individual pins.
- */
-
- XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
- XGpioPsPinTable[1] = (u32)51; /* 26 - 51, Bank 1 */
- XGpioPsPinTable[2] = (u32)77; /* 52 - 77, Bank 2 */
- XGpioPsPinTable[3] = (u32)109; /* 78 - 109, Bank 3 */
- XGpioPsPinTable[4] = (u32)141; /* 110 - 141, Bank 4 */
- XGpioPsPinTable[5] = (u32)173; /* 142 - 173 Bank 5 */
-
- *BankNumber = 0U;
- while (*BankNumber < XGPIOPS_SIX) {
- if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
- break;
- }
- (*BankNumber)++;
- }
- }
-#ifdef versal
- else if(Platform == XPLAT_VERSAL)
- {
- if(InstancePtr->PmcGpio == (u32)(FALSE))
- {
- XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
- XGpioPsPinTable[1] = (u32)57; /* 26 - 57, Bank 3 */
- *BankNumber =0U;
- if(PinNumber <= XGpioPsPinTable[*BankNumber])
- {
- *BankNumber = (u8)XGPIOPS_ZERO;
- }
- else
- {
- *BankNumber = (u8)XGPIOPS_THREE;
- }
-
- }
- else
- {
- XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
- XGpioPsPinTable[1] = (u32)51; /* 26 - 51, Bank 1 */
- XGpioPsPinTable[2] = (u32)83; /* 52 - 83, Bank 3 */
- XGpioPsPinTable[3] = (u32)115; /*84 - 115, Bank 4 */
-
- *BankNumber =0U;
- while(i < XGPIOPS_FOUR)
- {
- if(i <= (u8)XGPIOPS_ONE)
- {
- if (PinNumber <= XGpioPsPinTable[i])
- {
- *BankNumber = (u8)i;
- break;
- }
- i++;
- }
- else
- {
- if (PinNumber <= XGpioPsPinTable[i])
- {
- *BankNumber = (u8)i+1U;
- break;
- }
- i++;
- }
-
- }
- }
-
- }
-#endif
- else {
- XGpioPsPinTable[0] = (u32)31; /* 0 - 31, Bank 0 */
- XGpioPsPinTable[1] = (u32)53; /* 32 - 53, Bank 1 */
- XGpioPsPinTable[2] = (u32)85; /* 54 - 85, Bank 2 */
- XGpioPsPinTable[3] = (u32)117; /* 86 - 117 Bank 3 */
-
- *BankNumber = 0U;
- while (*BankNumber < XGPIOPS_FOUR) {
- if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
- break;
- }
- (*BankNumber)++;
- }
- }
- if (*BankNumber == (u8)0) {
- *PinNumberInBank = PinNumber;
- }
-
-#ifdef versal
- else if(Platform == XPLAT_VERSAL)
- {
- if(InstancePtr->PmcGpio == (u32)(FALSE))
- {
- *PinNumberInBank = (u8)((u32)PinNumber - (XGpioPsPinTable[0] + (u32)1));
- }
- else {
- if((*BankNumber ==(u8)XGPIOPS_THREE) || (*BankNumber ==(u8)XGPIOPS_FOUR))
- {
- *PinNumberInBank = (u8)((u32)PinNumber %
- (XGpioPsPinTable[*BankNumber - (u8)XGPIOPS_TWO] + (u32)1));
- }
- else
- {
- *PinNumberInBank = (u8)((u32)PinNumber %
- (XGpioPsPinTable[*BankNumber - (u8)1] + (u32)1));
- }
- }
-
- }
-#endif
-
- else {
- *PinNumberInBank = (u8)((u32)PinNumber %
- (XGpioPsPinTable[*BankNumber - (u8)1] + (u32)1));
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* This is a stub for the status callback. The stub is here in case the upper
-* layers do not set the handler.
-*
-* @param CallBackRef is a pointer to the upper layer callback reference
-* @param Bank is the GPIO Bank in which an interrupt occurred.
-* @param Status is the Interrupt status of the GPIO bank.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void StubHandler(void *CallBackRef, u32 Bank, u32 Status)
-{
- (void) CallBackRef;
- (void) Bank;
- (void) Status;
-
- Xil_AssertVoidAlways();
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7d/e1b4af595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7d/e1b4af595243001d18b399c1eb9b3628
deleted file mode 100644
index e40988e..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7d/e1b4af595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,366 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_spinlock.c
-*
-* Implements a spinlocking mechanism using ARM load-exclusive and
-* store-exclusive instructions.
-*
-* spinlocks in baremetal world are useful mainly for AMP kind of use cases
-* where different applications run in different CPUs in a CPU cluster and
-* they have a common resource to work with.
-* A simple yet common example is:
-* R5-0 and R5-1 have separate applications and at runtime they try to access a
-* shared register space (GIC) or shared memory space. Mutual exclusion is
-* really needed for such use cases.
-* Similar use case applies for Zynq CortexA9-0 and CortesA9-1.
-*
-* The spinlock mechanism provided with this file is very simple to cater to
-* baremetal world requirements.
-*
-* A) Unlike OS type of use cases, at any point of time, only a single lock
-* can be used. There is no way in BM world we can support multiple locks
-* at the same time.
-* B) The spinlocking is available for ARM v7 (Cortex-R5 and Cortex-A9).
-* C) Users need to provide a lock (essentially a shared address), and a flag
-* (also a shared address) for spinlocking to work. These shared addresses
-* must be agreed upon by apps running on both CPUs. Needless to say,
-* the linker scripts must change accordingly so that apps running on both
-* CPUs can have a shared DDR region from which address can be used for
-* spinlocking.
-* D) The address that is used for spinlocking and the address that is used
-* as flag address must be in a memory region that is strongly-ordered
-* or device memory.
-* E) Like any similar standard use cases, one application running in any
-* of the CPUs must create the spinlock address. It is advisable that the
-* the same application must destroy or release the spinlock address,
-* though nothing stops the other CPU in destroying and releasing the
-* spinlock addresses. There has to be understanding between applications
-* running on both the CPUs to ensure that correct ordering is followed.
-* Once a spinlock is released, it spinlock APIs cannot be used anymore.
-* F) Once a spinlock address is created it can be used any number of times
-* to protect critical sections as long as a certain set of rules are
-* followed and a certain set of sequences are followed. More about the
-* sequences later in this description.
-* G) To re-iterate, the spinlocking mechanism provided through this file is
-* pretty rudimentary. Users can always improvise. The use case that
-* the whole mechanism is trying to solve is: common register space
-* being accesses in an AMP scenario by independent applications running
-* at multiple CPUs.
-*
-* The usage of APIs provided in this file are summarized below.
-* A) Applications running at both the CPUs ensure that they allocate shared
-* memory space to be used for locking and flag maintenance.
-* B) The memory allocated as shared should be of minimum size 1 MB. This
-* limitation is because the way translation tables/memory map is setup
-* for R5 or A9. In future, this limitation can be brought down 4 KB.
-* C) The spinlock and the flag address must be uncached. Users need to c
-* all Xilinx provided API Xil_SetTlbAttributes to mark the shared
-* 1 MB memory space as strongly ordered or device memory.
-* D) Both the applications must call the API Xil_InitializeSpinLock with
-* the spinlock address, flag address and flag value to be used. Currently
-* only one flag value is supported (i.e. XIL_SPINLOCK_ENABLE with
-* a value of 1).
-* Only if the Xil_InitializeSpinLock returns success, should they
-* proceed to use Xil_SpinLock and Xil_SpinUnlock.
-* F) Afterwards applications can start using the APIs Xil_SpinLock() and
-* Xil_SpinUnlock() to protect the critical sections.
-* G) It is highly suggested to use Xil_IsSpinLockEnabled() as a check
-* before using Xil_SpinLock() or Xil_SpinUnlock(). Refer to the code
-* snippet below.
-* H) If spinlock is no more needed by an application, they can use the API
-* Xil_ReleaseSpinLock().
-* I) Once a spinlock is created it can be used as many numbers of time as
-* needed.
-*
-* A typical code snippet with R5 as an example and lock address falling
-* in the 1 MB memory region (0x300000 to 0x400000) is given below.
-*
-* Code snippet for R5-0 (that runs first):
-* int main()
-* {
-* u32 *sharedlockaddr = (int *)0x300008;
-* u32 *sharedlockflagaddr = int *)0x30000C;
-* Xil_SetTlbAttributes(0x300000,STRONG_ORDERD_SHARED | PRIV_RW_USER_RW);
-* Xil_InitializeSpinLock((UINTPTR)sharedlockaddr,(UINTPTR)sharedlockflagaddr,
-* XIL_SPINLOCK_ENABLE);
-* ....
-* ....
-* if (Xil_IsSpinLockEnabled())
-* Xil_SpinLock();
-* // Critical Section
-* ....
-* ....
-* if (Xil_IsSpinLockEnabled())
-* Xil_SpinUnlock();
-* .....
-* .....
-* Xil_ReleaseSpinLock();
-* } // End of main
-*
-* * Code snippet for R5-1 (that runs second):
-* int main()
-* {
-* u32 *sharedlockaddr = (int *)0x300008;
-* u32 *sharedlockflagaddr = int *)0x30000C;
-* Xil_SetTlbAttributes(0x300000,STRONG_ORDERD_SHARED | PRIV_RW_USER_RW);
-* Xil_InitializeSpinLock((UINTPTR)sharedlockaddr,(UINTPTR)sharedlockflagaddr,
-* XIL_SPINLOCK_ENABLE);
-* ....
-* if (Xil_IsSpinLockEnabled())
-* Xil_SpinLock();
-* // Critical Section
-* ....
-* ....
-* if (Xil_IsSpinLockEnabled())
-* Xil_SpinUnlock();
-* .....
-* .....
-* Xil_ReleaseSpinLock();
-* } // End of main
-*
-* Xil_SpinLock() and Xil_SpinLock() return XST_FAILURE if the spinlock
-* is initialized. Instead of calling Xil_IsSpinLockEnabled before using
-* Xil_SpinLock() or Xil_SpinLock(), users can also check the return
-* value of Xil_SpinLock and Xil_SpinLock. If a lock is not initialized,
-* Xil_SpinLock will just return failure and not perform load-exclusive
-* operations.
-*
-* Guidelines on when to use the spinlocking mechanism in Xilinx baremetal
-* environment:
-* A) Spinlocking mechanism can only be used for Cortex-R5s (split mode)
-* and Cortex-A9s (Zynq).
-* B) In Cortex-R5 split mode or Cortex-A9 cluster, applications running on
-* both the CPUs, by design should never be sharing the same peripheral.
-* It is impossible to support such use cases reliably.
-* Hence none of the peripheral drivers (except GIC driver) have
-* spinlocking support added into their APIs.
-* C) GIC register space is shared by both the CPUs (R5 split mode, A9s).
-* The GIC driver APIs have spinlocking mechanism added to the relevant
-* APIs. Users need to follow the guidelines stated earlier to enable
-* the spinlocks and use them.
-* It is really advisable to use spinlock mechanism for use cases where
-* applications running on multiple CPUs can simultaneously access
-* GIC register space through driver APIs.
-* D) The spinlock mechanism can be used to protect any critical region
-* implemented through shared memory space.
-*
-* IMPORTANT NOTE: Circular spinlocks are not allowed (as expected).
-* Use case where an application calls Xil_SpinLock back to back without
-* calling Xil_SpinUnlock in between will/may result in a deadlock
-* condition.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 7.5 asa 02/23/21 First release
-* 7.5 asa 04/28/21 Fixed bug Xil_IsSpinLockEnabled to avoid
-* dereferencing to address zero.
-*
-*
-******************************************************************************/
-
-
-/***************************** Include Files ********************************/
-#if !defined (__aarch64__) && defined(__GNUC__) && !defined(__clang__)
-#include "xil_spinlock.h"
-
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-
-/************************** Variable Definitions ****************************/
-static UINTPTR Xil_Spinlock_Addr = 0x0;
-static UINTPTR Xil_Spinlock_Flag_Addr = 0x0;
-
-/************************** Function Prototypes *****************************/
-
-/****************************************************************************/
-/**
-*
-* @brief Used at the beginning of a critical section. This API takes the
-* lock using load-exclusive and store-exclusive operations. In
-* case the lock is not available (being held by an application
-* running at the other CPU and doing operations inside the
-* critical section, the control will never go out from the API
-* till the other CPU releases the lock.
-*
-* @param None.
-*
-* @return XST_FAILURE: If spinlock is not properly initialized.
-* XST_SUCCESS: If the lock was successfully obtained.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 Xil_SpinLock(void)
-{
- UINTPTR lockaddr = Xil_Spinlock_Addr;
- u32 LockTempVar;
-
- if (Xil_Spinlock_Addr == 0) {
- return XST_FAILURE;
- }
-
- __asm__ __volatile__(
- "1: ldrex %0, [%1] \n"
- " teq %0, %3 \n"
- " strexeq %0, %2, [%1] \n"
- " teqeq %0, #0 \n"
- " bne 1b \n"
- " dmb \n"
- : "=&r" (LockTempVar)
- : "r" (lockaddr), "r"(XIL_SPINLOCK_LOCKVAL), "r"(XIL_SPINLOCK_RESETVAL)
- : "cc");
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* @brief Used to release a lock previously held by calling Xil_SpinLock.
-*
-* @param None.
-*
-* @return XST_FAILURE: If spinlock is not properly initialized.
-* XST_SUCCESS: If the lock was successfully obtained.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 Xil_SpinUnlock(void)
-{
- UINTPTR lockaddr = Xil_Spinlock_Addr;
-
- if (Xil_Spinlock_Addr == 0) {
- return XST_FAILURE;
- }
- __asm__ __volatile__(
- "dmb \n"
- "str %1, [%0] \n"
- :
- : "r" (lockaddr), "r" (XIL_SPINLOCK_RESETVAL)
- : "cc");
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-* @brief Used to initialize a spinlock.
-*
-* @param lockaddr: Address of the lock variable. The address must be in
-* a shared memory region.
-* lockflagaddr: Address of the flag variable. The address must be
-* in a shared memory region.
-* lockflag: The value of the flag. Currently only one value
-* is supported, which is XIL_SPINLOCK_ENABLE.
-*
-* @return XST_SUCCESS, if the initialization succeeded.
-* XST_FAILURE, if the initialization failed
-*
-* @note None.
-*
-*****************************************************************************/
-u32 Xil_InitializeSpinLock(UINTPTR lockaddr, UINTPTR lockflagaddr,
- u32 lockflag)
-{
- if (Xil_Spinlock_Flag_Addr == 0) {
- Xil_Spinlock_Flag_Addr = lockflagaddr;
- if (*(u32 *)Xil_Spinlock_Flag_Addr == XIL_SPINLOCK_ENABLED) {
- /*
- * spinlock is already initialized by one of the CPUs, just update
- * the local variable Xil_Spinlock_Addr with the passed address
- * and dont write to the lock value as it might be currently
- * getting used.
- */
- /*
- * Ensure to update the global variable Xil_Spinlock_Addr only
- * if it is zero. A non-zero value may mean that there is something
- * wrong.
- */
- if (Xil_Spinlock_Addr == 0) {
- Xil_Spinlock_Addr = lockaddr;
- } else {
- /*
- * May be spinlock is already initialized and the user has not
- * called Xil_ReleaseSpinLock before calling Xil_InitializeSpinLock.
- */
- return XST_FAILURE;
- }
- } else {
- /* All good, do the necessary initializations */
- Xil_Spinlock_Addr = lockaddr;
- *(u32 *)(Xil_Spinlock_Addr) = XIL_SPINLOCK_RESETVAL;
- *(u32 *)(Xil_Spinlock_Flag_Addr) = lockflag;
- }
- return XST_SUCCESS;
- } else {
- /*
- * Most probably spinlock is already initialized and the user has not
- * called Xil_ReleaseSpinLock before calling Xil_InitializeSpinLock.
- */
- return XST_FAILURE;
- }
-}
-
-
-/****************************************************************************/
-/**
-* @brief Used to release the spinlock. Typically called by the application
-* once spinlock feature is no more required.
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void Xil_ReleaseSpinLock(void)
-{
- Xil_Spinlock_Addr = 0;
- Xil_Spinlock_Flag_Addr = 0;
-}
-
-/****************************************************************************/
-/**
-* @brief Used to know if the spinlock feature has been enabled. To ensure
-* that spinlock feature does not break use cases where lock is
-* not initialized, the application must call this API first to know
-* if it can use spinlock. If this API returns non-zero value, an
-* application should then use Xil_SpinLock or Xil_SpinUnlock.
-*
-* @param None
-*
-* @return Non-zero, if spinlock is already initialized and can be used.
-* Zero, if spinlock is not initialized.
-*
-* @note
-*
-*****************************************************************************/
-u32 Xil_IsSpinLockEnabled(void)
-{
- u32 retVal = FALSE;
-
- if (Xil_Spinlock_Flag_Addr != 0) {
- if (*(u32 *)(Xil_Spinlock_Flag_Addr) == XIL_SPINLOCK_ENABLED) {
- retVal = TRUE;
- }
- }
- return retVal;
-}
-#endif /* !(__aarch64__) && (__GNUC__) && !(__clang__)*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7e/30fc3b545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7e/30fc3b545243001d18b399c1eb9b3628
deleted file mode 100644
index 4b289a7..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7e/30fc3b545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,43 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_hal.h
-*
-* Contains all the HAL header files.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/28/09 Initial release
-*
-*
-*
-* @note
-*
-******************************************************************************/
-
-#ifndef XIL_HAL_H
-#define XIL_HAL_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xil_cache.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-#include "xil_exception.h"
-#include "xil_types.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7e/315f6a545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7e/315f6a545243001d18b399c1eb9b3628
deleted file mode 100644
index 9d17f5c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7e/315f6a545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,86 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xtime_l.h
-* @addtogroup a9_time_apis Cortex A9 Time Functions
-*
-* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This
-* counter increases by one at every two processor cycles. These functions can
-* be used to get/set time in the global timer.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 1.00a rp/sdm 11/03/09 Initial release.
-* 3.06a sgd 05/15/12 Updated get/set time functions to make use Global Timer
-* 3.06a asa 06/17/12 Reverted back the changes to make use Global Timer.
-* 3.07a sgd 07/05/12 Updated get/set time functions to make use Global Timer
-* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep
-* implementation
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
-* displaying same warnings multiple times. It fixes CR#1090562.
-*
-*
-******************************************************************************/
-
-/**
-*@cond nocomments
-*/
-
-#ifndef XTIME_H /* prevent circular inclusions */
-#define XTIME_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xparameters.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-typedef u64 XTime;
-
-/************************** Constant Definitions *****************************/
-#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR
-#define GTIMER_COUNTER_LOWER_OFFSET 0x00U
-#define GTIMER_COUNTER_UPPER_OFFSET 0x04U
-#define GTIMER_CONTROL_OFFSET 0x08U
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY)
-#else
-/* Global Timer is always clocked at half of the CPU frequency */
-#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
-#endif
-/************************** Variable Definitions *****************************/
-
-/**
-*@endcond
-*/
-
-/************************** Function Prototypes ******************************/
-
-void XTime_SetTime(XTime Xtime_Global);
-void XTime_GetTime(XTime *Xtime_Global);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XTIME_H */
-/**
-* @} End of "addtogroup a9_time_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7e/50cf0b555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7e/50cf0b555243001d18b399c1eb9b3628
deleted file mode 100644
index 3438d96..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7e/50cf0b555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1 +0,0 @@
-collect (PROJECT_LIB_HEADERS xparameters_ps.h)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7e/6021ea555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7e/6021ea555243001d18b399c1eb9b3628
deleted file mode 100644
index 125fe7f..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7e/6021ea555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,202 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file translation_table.S
-*
-* @addtogroup a9_boot_code
-* @{
-*
translation_table.S
-* The translation_table.S contains a static page table required by MMU for
-* cortex-A9. This translation table is flat mapped (input address = output
-* address) with default memory attributes defined for zynq architecture. It
-* utilizes short descriptor translation table format with each section defining
-* 1 MB of memory.
-*
-* The overview of translation table memory attributes is described below.
-*
-*| | Memory Range | Definition in Translation Table |
-*|-----------------------|-------------------------|-----------------------------------|
-*| DDR | 0x00000000 - 0x3FFFFFFF | Normal write-back Cacheable |
-*| PL | 0x40000000 - 0xBFFFFFFF | Strongly Ordered |
-*| Reserved | 0xC0000000 - 0xDFFFFFFF | Unassigned |
-*| Memory mapped devices | 0xE0000000 - 0xE02FFFFF | Device Memory |
-*| Reserved | 0xE0300000 - 0xE0FFFFFF | Unassigned |
-*| NAND, NOR | 0xE1000000 - 0xE3FFFFFF | Device memory |
-*| SRAM | 0xE4000000 - 0xE5FFFFFF | Normal write-back Cacheable |
-*| Reserved | 0xE6000000 - 0xF7FFFFFF | Unassigned |
-*| AMBA APB Peripherals | 0xF8000000 - 0xF8FFFFFF | Device Memory |
-*| Reserved | 0xF9000000 - 0xFBFFFFFF | Unassigned |
-*| Linear QSPI - XIP | 0xFC000000 - 0xFDFFFFFF | Normal write-through cacheable |
-*| Reserved | 0xFE000000 - 0xFFEFFFFF | Unassigned |
-*| OCM | 0xFFF00000 - 0xFFFFFFFF | Normal inner write-back cacheable |
-*
-* For region 0x00000000 - 0x3FFFFFFF, a system where DDR is less than 1 GB,
-* region after DDR and before PL is marked as undefined/reserved in translation
-* table. In 0xF8000000 - 0xF8FFFFFF, 0xF8000C00 - 0xF8000FFF, 0xF8010000 -
-* 0xF88FFFFF and 0xF8F03000 to 0xF8FFFFFF are reserved but due to granual size
-* of 1 MB, it is not possible to define separate regions for them. For region
-* 0xFFF00000 - 0xFFFFFFFF, 0xFFF00000 to 0xFFFB0000 is reserved but due to 1MB
-* granual size, it is not possible to define separate region for it.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 10/20/09 Initial version
-* 3.04a sdm 01/13/12 Updated MMU table to mark DDR memory as Shareable
-* 3.07a sgd 07/05/2012 Configuring device address spaces as shareable device
-* instead of strongly-ordered.
-* 3.07a asa 07/17/2012 Changed the property of the ".mmu_tbl" section.
-* 4.2 pkp 09/02/2014 added entries for 0xfe000000 to 0xffefffff as reserved
-* and 0xe0000000 - 0xe1ffffff is broken down into
-* 0xe0000000 - 0xe02fffff (memory mapped divides)
-* 0xe0300000 - 0xe0ffffff (reserved) and
-* 0xe1000000 - 0xe1ffffff (NAND)
-* 5.2 pkp 06/08/2015 put a check for XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm
-* if DDR is present or not and accordingly generate the
-* translation table
-* 6.1 pkp 07/11/2016 Corrected comments for memory attributes
-* 6.8 mus 07/12/2018 Mark DDR memory as inner cacheable, if BSP is built
-* with the USE_AMP flag.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.0 hk 27/01/14 First release
-* 1.4 vns 07/06/17 Added dooxygen tags.
-*
-*
-*
-* @note
-*
-******************************************************************************/
-#ifndef ___XIL_RSA_H___
-#define ___XIL_RSA_H___
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/***************************** Include Files *********************************/
-
-/*
- * Digit size selection (32 or 16-bit). If supported by the CPU/compiler,
- * 32-bit digits are approximately 4 times faster
- */
-
-//#define RSA_DIGIT_16
-#define RSA_DIGIT_32
-
-/*
- * RSA loop unrolling selection
- * RSA main loop can be unrolled 2, 4 or 8 ways
- */
-#define RSA_UNROLL 1
-
-/*
- * Select if ARM-optimized code is to be used. Only GCC for ARM is supported
- */
-//#define RSA_ARM_OPTIMIZED
-
-/*
- * Check the compatibility of the selection
- */
-#if defined(RSA_DIGIT_16) && defined(RSA_DIGIT_32)
- #error Please select a digit size
-#endif
-#if !defined(RSA_DIGIT_16) && !defined(RSA_DIGIT_32)
- #error Please select just one digit size
-#endif
-#if (!defined(__GNUC__) || !defined(__arm__)) && defined(RSA_ARM_OPTIMIZED)
- #error Assembly level code is only supported for the GCC/ARM combination
-#endif
-#if (RSA_UNROLL != 1) && (RSA_UNROLL != 2) && (RSA_UNROLL != 4) && (RSA_UNROLL != 8)
- #error Only 1, 2, 4, and 8 unrolling are supported
-#endif
-
-#ifdef RSA_DIGIT_16
-#define RSA_DIGIT unsigned short
-#define RSA_SDIGIT short
-#define RSA_DDIGIT unsigned long
-#endif
-#ifdef RSA_DIGIT_32
-#define RSA_DIGIT unsigned long
-#define RSA_SDIGIT long
-#define RSA_DDIGIT unsigned long long
-#endif
-
-#define RSA_NUMBER RSA_DIGIT *
-#define RSA_NBITS 2048
-#define RSA_NDIGITS (RSA_NBITS/(sizeof(RSA_DIGIT)*8))
-#define RSA_NBYTES (RSA_NDIGITS*sizeof(RSA_DIGIT))
-
-/*
- * Double-digit to single digit conversion
- */
-#define RSA_MSB(x) (x >> (sizeof(RSA_DIGIT)*8))
-#define RSA_LSB(x) (x & (RSA_DIGIT)~0)
-
-#define SHA_BLKSIZE 512
-#define SHA_BLKBYTES (SHA_BLKSIZE/8)
-#define SHA_BLKWORDS (SHA_BLKBYTES/4)
-
-#define SHA_VALSIZE 256
-#define SHA_VALBYTES (SHA_VALSIZE/8)
-#define SHA_VALWORDS (SHA_VALBYTES/4)
-
-/*
- * SHA-256 context structure
- * Includes SHA-256 state, coalescing buffer to collect the processed strings, and
- * total byte length counter (used both to manage the buffer and for padding)
- */
- //! [sha2_context]
-typedef struct
-{
- unsigned int state[8];
- unsigned char buffer[SHA_BLKBYTES];
- unsigned long long bytes;
-} sha2_context;
-//! [sha2_context]
-/** @}
-@endcond */
-
-/*
- * RSA-2048 user interfaces
- */
-/*****************************************************************************/
-/**
- * @brief
- * This function is used to encrypt the data using 2048 bit private key.
- *
- * @param modular A char pointer which contains the key modulus
- * @param modular_ext A char pointer which contains the key modulus
- * extension
- * @param exponent A char pointer which contains the private key
- * exponent
- * @param result A char pointer which contains the encrypted data
- *
- * @return None
- *
- ******************************************************************************/
-void rsa2048_exp(const unsigned char *base, const unsigned char * modular,
- const unsigned char *modular_ext, const unsigned char *exponent,
- unsigned char *result);
-/*****************************************************************************/
-/**
- * @brief
- * This function is used to decrypt the data using 2048 bit public key
- *
- * @param a RSA_NUMBER containing the decrypted data.
- * @param x RSA_NUMBER containing the input data
- * @param e Unsigned number containing the public key exponent
- * @param m RSA_NUMBER containing the public key modulus
- * @param rrm RSA_NUMBER containing the public key modulus extension.
- *
- * @return None
- *
- ******************************************************************************/
-void rsa2048_pubexp(RSA_NUMBER a, RSA_NUMBER x,
- unsigned long e, RSA_NUMBER m, RSA_NUMBER rrm);
-
-/*
- * SHA-256 user interfaces
- */
-/*****************************************************************************/
-/**
- * @brief
- * This function calculates the hash for the input data using SHA-256
- * algorithm. This function internally calls the sha2_init, updates and
- * finishes functions and updates the result.
- *
- * @param In Char pointer which contains the input data.
- * @param Size Length of the input data
- * @param Out Pointer to location where resulting hash will be
- * written.
- *
- * @return None
- *
- ******************************************************************************/
-void sha_256(const unsigned char *in, const unsigned int size, unsigned char *out);
-/*****************************************************************************/
-/**
- * @brief
- * This function initializes the SHA2 context.
- *
- * @param ctx Pointer to sha2_context structure that stores status and
- * buffer.
- *
- * @return None
- *
- ******************************************************************************/
-void sha2_starts(sha2_context *ctx);
-/*****************************************************************************/
-/**
- * @brief
- * This function adds the input data to SHA256 calculation.
- *
- * @param ctx Pointer to sha2_context structure that stores status and
- * buffer.
- * @param input Pointer to the data to add.
- * @param Out Length of the input data.
- *
- * @return None
- *
- ******************************************************************************/
-void sha2_update(sha2_context *ctx, unsigned char* input, unsigned int ilen);
-/*****************************************************************************/
-/**
- * @brief
- * This function finishes the SHA calculation.
- *
- * @param ctx Pointer to sha2_context structure that stores status and
- * buffer.
- * @param output Pointer to the calculated hash data.
- *
- * @return None
- *
- *
- ******************************************************************************/
-void sha2_finish(sha2_context *ctx, unsigned char* output);
-
-/*
- * Preprocessing interface (pre-computation of R*R mod M)
- */
-/**@cond xilrsa_internal */
-void modular_ext(const unsigned char *modular, unsigned char *res);
-/** @}
-@endcond */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ___XIL_RSA_H___ */
-/** @} */
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7e/d05eba555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7e/d05eba555243001d18b399c1eb9b3628
deleted file mode 100644
index fffd926..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7e/d05eba555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,159 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm_iccarm.h
-*
-* This header file contains macros for using inline assembler code. It is
-* written specifically for the IAR C/C++ compiler.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm 10/28/09 First release
-* 3.12a asa 11/02/13 Removed the macro mfcpsr to make it a function.
-* 5.3 pkp 10/09/15 Modified dsb, dmb and isb definitions
-* 5.4 pkp 03/02/16 Included header file intrinsic.h for assembly
-* instructions definitions
-* 6.2 kvn 03/03/17 Added support thumb mode
-* 7.2 asa 04/03/20 Renamed the str macro to strw.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 6.0 mus 27/07/16 Added Undefined exception handler
-* 6.4 mus 25/07/17 Added support for hard floating point
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-
-.org 0
-.text
-
-.globl _boot
-.globl _vector_table
-
-.globl FIQInterrupt
-.globl IRQInterrupt
-.globl SWInterrupt
-.globl DataAbortInterrupt
-.globl PrefetchAbortInterrupt
-
-.globl IRQHandler
-.globl prof_pc
-
-.section .vectors, "a"
-_vector_table:
- B _boot
- B Undefined
- B SVCHandler
- B PrefetchAbortHandler
- B DataAbortHandler
- NOP /* Placeholder for address exception vector*/
- B IRQHandler
- B FIQHandler
-
-
-IRQHandler: /* IRQ vector handler */
-
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/
- vpush {d0-d7}
- vpush {d16-d31}
- vmrs r1, FPSCR
- push {r1}
- vmrs r1, FPEXC
- push {r1}
-
- bl IRQInterrupt /* IRQ vector */
- pop {r1}
- vmsr FPEXC, r1
- pop {r1}
- vmsr FPSCR, r1
- vpop {d16-d31}
- vpop {d0-d7}
-
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
-
- subs pc, lr, #4 /* adjust return */
-
-
-FIQHandler: /* FIQ vector handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
-
- vpush {d0-d7}
- vpush {d16-d31}
- vmrs r1, FPSCR
- push {r1}
- vmrs r1, FPEXC
- push {r1}
-FIQLoop:
- bl FIQInterrupt /* FIQ vector */
-
- pop {r1}
- vmsr FPEXC, r1
- pop {r1}
- vmsr FPSCR, r1
- vpop {d16-d31}
- vpop {d0-d7}
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
- subs pc, lr, #4 /* adjust return */
-
-
-Undefined: /* Undefined handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- ldr r0, =UndefinedExceptionAddr
- sub r1, lr, #4
- str r1, [r0] /* Store address of instruction causing undefined exception */
-
- bl UndefinedException /* UndefinedException: call C function here */
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
- movs pc, lr
-
-
-SVCHandler: /* SWI handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
-
- tst r0, #0x20 /* check the T bit */
- ldrneh r0, [lr,#-2] /* Thumb mode */
- bicne r0, r0, #0xff00 /* Thumb mode */
- ldreq r0, [lr,#-4] /* ARM mode */
- biceq r0, r0, #0xff000000 /* ARM mode */
-
- bl SWInterrupt /* SWInterrupt: call C function here */
-
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
- movs pc, lr /*return to the next instruction after the SWI instruction */
-
-
-DataAbortHandler: /* Data Abort handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- ldr r0, =DataAbortAddr
- sub r1, lr, #8
- str r1, [r0] /* Stores instruction causing data abort */
- bl DataAbortInterrupt /*DataAbortInterrupt :call C function here */
-
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
- subs pc, lr, #8 /* points to the instruction that caused the Data Abort exception */
-
-PrefetchAbortHandler: /* Prefetch Abort handler */
-
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- ldr r0, =PrefetchAbortAddr
- sub r1, lr, #4
- str r1, [r0] /* Stores instruction causing prefetch abort */
-
- bl PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */
-
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
- subs pc, lr, #4 /* points to the instruction that caused the Prefetch Abort exception */
-
-
-.end
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7f/210613565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7f/210613565243001d18b399c1eb9b3628
deleted file mode 100644
index 5db2e71..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7f/210613565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,83 +0,0 @@
-###############################################################################
-# Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
-# SPDX-License-Identifier: MIT
-###############################################################################
-DRIVER_LIB_VERSION = v1.0
-
-include config.make
-CC=$(COMPILER)
-AR=$(ARCHIVER)
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS))
-ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS))
-
-ifeq ($(notdir $(CC)), armr5-none-eabi-gcc)
-ECC_FLAGS += -nostartfiles
-endif
-ECC_FLAGS_NO_FLTO1 = $(subst -flto,,$(ECC_FLAGS))
-ECC_FLAGS_NO_FLTO = $(subst -ffat-lto-objects,,$(ECC_FLAGS_NO_FLTO1))
-
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-SRCFILES:=$(wildcard *.c)
-
-ASSEMBLY_SRCFILES:=$(wildcard *.S)
-
-OBJECTS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(filter-out _exit.c, $(wildcard *.c)))))
-ASSEMBLY_OBJECTS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(wildcard *.S))))
-
-NON_LTO_OBJECTS = $(addprefix $(RELEASEDIR),$(addsuffix .o,$(basename _exit.c)))
-
-INCLUDEFILES=*.h
-INCLUDEFILES+=includes_ps/*.h
-
-libs: $(LIBS)
-
-standalone_libs: $(OBJECTS) $(ASSEMBLY_OBJECTS) $(NON_LTO_OBJECTS)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-ASSEMBLY_DEPFILES := $(ASSEMBLY_SRCFILES:%.S=$(RELEASEDIR)%.d)
-
-include $(wildcard $(ASSEMBLY_DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)_exit.o: _exit.c
- $(CC) $(CC_FLAGS) $(ECC_FLAGS_NO_FLTO) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $<
-
-$(RELEASEDIR)%.o: %.S
- $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $<
-
-$(RELEASEDIR)%.o: %.c
- $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $<
-
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h)) $(addprefix $(INCLUDEDIR), $(subst includes_ps/,,$(wildcard includes_ps/*.h)))
-
-
-
-$(INCLUDEDIR)%.h: includes_ps/%.h
- $(CP) $< $@
-
-
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf ${ASSEMBLY_OBJECTS}
- rm -rf $(DEPFILES)
- rm -rf $(ASSEMBLY_DEPFILES)
- rm -rf $(NON_LTO_OBJECTS)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7f/247695595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7f/247695595243001d18b399c1eb9b3628
deleted file mode 100644
index d8aef59..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7f/247695595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,169 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xenv.h
-*
-* Defines common services that are typically found in a host operating.
-* environment. This include file simply includes an OS specific file based
-* on the compile-time constant BUILD_ENV_*, where * is the name of the target
-* environment.
-*
-* All services are defined as macros.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b ch 10/24/02 Added XENV_LINUX
-* 1.00a rmm 04/17/02 First release
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XENV_H /* prevent circular inclusions */
-#define XENV_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * Select which target environment we are operating under
- */
-
-/* VxWorks target environment */
-#if defined XENV_VXWORKS
-#include "xenv_vxworks.h"
-
-/* Linux target environment */
-#elif defined XENV_LINUX
-#include "xenv_linux.h"
-
-/* Unit test environment */
-#elif defined XENV_UNITTEST
-#include "ut_xenv.h"
-
-/* Integration test environment */
-#elif defined XENV_INTTEST
-#include "int_xenv.h"
-
-/* Standalone environment selected */
-#else
-#include "xenv_standalone.h"
-#endif
-
-
-/*
- * The following comments specify the types and macro wrappers that are
- * expected to be defined by the target specific header files
- */
-
-/**************************** Type Definitions *******************************/
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP
- *
- * A structure that contains a time stamp used by other time stamp macros
- * defined below. This structure is processor dependent.
- */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- *
- * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
- *
- * Copies a non-overlapping block of memory.
- *
- * @param DestPtr is the destination address to copy data to.
- * @param SrcPtr is the source address to copy data from.
- * @param Bytes is the number of bytes to copy.
- *
- * @return None
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
- *
- * Fills an area of memory with constant data.
- *
- * @param DestPtr is the destination address to set.
- * @param Data contains the value to set.
- * @param Bytes is the number of bytes to set.
- *
- * @return None
- */
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
- *
- * Samples the processor's or external timer's time base counter.
- *
- * @param StampPtr is the storage for the retrieved time stamp.
- *
- * @return None
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
- *
- * Computes the delta between the two time stamps.
- *
- * @param Stamp1Ptr - First sampled time stamp.
- * @param Stamp1Ptr - Sedond sampled time stamp.
- *
- * @return An unsigned int value with units of microseconds.
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
- *
- * Computes the delta between the two time stamps.
- *
- * @param Stamp1Ptr - First sampled time stamp.
- * @param Stamp1Ptr - Sedond sampled time stamp.
- *
- * @return An unsigned int value with units of milliseconds.
- */
-
-/*****************************************************************************//**
- *
- * XENV_USLEEP(unsigned delay)
- *
- * Delay the specified number of microseconds.
- *
- * @param delay is the number of microseconds to delay.
- *
- * @return None
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7f/b0c1e7535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7f/b0c1e7535243001d18b399c1eb9b3628
deleted file mode 100644
index 2de567a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7f/b0c1e7535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1410 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xsdps_hw.h
-* @addtogroup sdps_v3_13
-* @{
-*
-* This header file contains the identifiers and basic HW access driver
-* functions (or macros) that can be used to access the device. Other driver
-* functions are defined in xsdps.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a hk/sg 10/17/13 Initial release
-* 2.5 sg 07/09/15 Added SD 3.0 features
-* kvn 07/15/15 Modified the code according to MISRAC-2012.
-* 2.7 sk 12/10/15 Added support for MMC cards.
-* sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
-* 2.8 sk 04/20/16 Added new workaround for auto tuning.
-* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
-* sk 07/16/16 Added support for UHS modes.
-* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
-* operating modes.
-* 3.1 sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
-* 3.2 sk 03/20/17 Add support for EL1 non-secure mode.
-* 3.3 mn 08/22/17 Updated for Word Access System support
-* mn 09/06/17 Added support for ARMCC toolchain
-* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
-* 3.6 mn 07/06/18 Fix Doxygen warnings for sdps driver
-* 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
-* mn 05/21/19 Set correct tap delays for Versal
-* mn 05/21/19 Disable DLL Reset code for Versal
-* mn 07/03/19 Update Input Tap Delays for Versal
-* 3.9 mn 03/03/20 Restructured the code for more readability and modularity
-*
-*
-*
-******************************************************************************/
-
-#ifndef SD_HW_H_
-#define SD_HW_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets from the base address of an SD device.
- * @{
- */
-
-#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address
- Register */
-#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET
- /**< SDMA System Address
- Low Register */
-#define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */
-#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address
- High Register */
-#define XSDPS_ARGMT2_HI_OFFSET 0x02U /**< Argument2 High Register */
-
-#define XSDPS_BLK_SIZE_OFFSET 0x04U /**< Block Size Register */
-#define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */
-#define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */
-#define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET
- /**< Argument1 Register */
-#define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */
-
-#define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */
-#define XSDPS_CMD_OFFSET 0x0EU /**< Command Register */
-#define XSDPS_RESP0_OFFSET 0x10U /**< Response0 Register */
-#define XSDPS_RESP1_OFFSET 0x14U /**< Response1 Register */
-#define XSDPS_RESP2_OFFSET 0x18U /**< Response2 Register */
-#define XSDPS_RESP3_OFFSET 0x1CU /**< Response3 Register */
-#define XSDPS_BUF_DAT_PORT_OFFSET 0x20U /**< Buffer Data Port */
-#define XSDPS_PRES_STATE_OFFSET 0x24U /**< Present State */
-#define XSDPS_HOST_CTRL1_OFFSET 0x28U /**< Host Control 1 */
-#define XSDPS_POWER_CTRL_OFFSET 0x29U /**< Power Control */
-#define XSDPS_BLK_GAP_CTRL_OFFSET 0x2AU /**< Block Gap Control */
-#define XSDPS_WAKE_UP_CTRL_OFFSET 0x2BU /**< Wake Up Control */
-#define XSDPS_CLK_CTRL_OFFSET 0x2CU /**< Clock Control */
-#define XSDPS_TIMEOUT_CTRL_OFFSET 0x2EU /**< Timeout Control */
-#define XSDPS_SW_RST_OFFSET 0x2FU /**< Software Reset */
-#define XSDPS_NORM_INTR_STS_OFFSET 0x30U /**< Normal Interrupt
- Status Register */
-#define XSDPS_ERR_INTR_STS_OFFSET 0x32U /**< Error Interrupt
- Status Register */
-#define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34U /**< Normal Interrupt
- Status Enable Register */
-#define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36U /**< Error Interrupt
- Status Enable Register */
-#define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38U /**< Normal Interrupt
- Signal Enable Register */
-#define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3AU /**< Error Interrupt
- Signal Enable Register */
-
-#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3CU /**< Auto CMD12 Error Status
- Register */
-#define XSDPS_HOST_CTRL2_OFFSET 0x3EU /**< Host Control2 Register */
-#define XSDPS_CAPS_OFFSET 0x40U /**< Capabilities Register */
-#define XSDPS_CAPS_EXT_OFFSET 0x44U /**< Capabilities Extended */
-#define XSDPS_MAX_CURR_CAPS_OFFSET 0x48U /**< Maximum Current
- Capabilities Register */
-#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4CU /**< Maximum Current
- Capabilities Ext Register */
-#define XSDPS_FE_ERR_INT_STS_OFFSET 0x52U /**< Force Event for
- Error Interrupt Status */
-#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50U /**< Auto CM12 Error Interrupt
- Status Register */
-#define XSDPS_ADMA_ERR_STS_OFFSET 0x54U /**< ADMA Error Status
- Register */
-#define XSDPS_ADMA_SAR_OFFSET 0x58U /**< ADMA System Address
- Register */
-#define XSDPS_ADMA_SAR_EXT_OFFSET 0x5CU /**< ADMA System Address
- Extended Register */
-#define XSDPS_PRE_VAL_1_OFFSET 0x60U /**< Preset Value Register */
-#define XSDPS_PRE_VAL_2_OFFSET 0x64U /**< Preset Value Register */
-#define XSDPS_PRE_VAL_3_OFFSET 0x68U /**< Preset Value Register */
-#define XSDPS_PRE_VAL_4_OFFSET 0x6CU /**< Preset Value Register */
-#define XSDPS_BOOT_TOUT_CTRL_OFFSET 0x70U /**< Boot timeout control
- register */
-
-#define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0U /**< Shared Bus Control
- Register */
-#define XSDPS_SLOT_INTR_STS_OFFSET 0xFCU /**< Slot Interrupt Status
- Register */
-#define XSDPS_HOST_CTRL_VER_OFFSET 0xFEU /**< Host Controller Version
- Register */
-
-/** @} */
-
-/** @name Control Register - Host control, Power control,
- * Block Gap control and Wakeup control
- *
- * This register contains bits for various configuration options of
- * the SD host controller. Read/Write apart from the reserved bits.
- * @{
- */
-
-#define XSDPS_HC_LED_MASK 0x00000001U /**< LED Control */
-#define XSDPS_HC_WIDTH_MASK 0x00000002U /**< Bus width */
-#define XSDPS_HC_BUS_WIDTH_4 0x00000002U
-#define XSDPS_HC_SPEED_MASK 0x00000004U /**< High Speed */
-#define XSDPS_HC_DMA_MASK 0x00000018U /**< DMA Mode Select */
-#define XSDPS_HC_DMA_SDMA_MASK 0x00000000U /**< SDMA Mode */
-#define XSDPS_HC_DMA_ADMA1_MASK 0x00000008U /**< ADMA1 Mode */
-#define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010U /**< ADMA2 Mode - 32 bit */
-#define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018U /**< ADMA2 Mode - 64 bit */
-#define XSDPS_HC_EXT_BUS_WIDTH 0x00000020U /**< Bus width - 8 bit */
-#define XSDPS_HC_CARD_DET_TL_MASK 0x00000040U /**< Card Detect Tst Lvl */
-#define XSDPS_HC_CARD_DET_SD_MASK 0x00000080U /**< Card Detect Sig Det */
-
-#define XSDPS_PC_BUS_PWR_MASK 0x00000001U /**< Bus Power Control */
-#define XSDPS_PC_BUS_VSEL_MASK 0x0000000EU /**< Bus Voltage Select */
-#define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000EU /**< Bus Voltage 3.3V */
-#define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000CU /**< Bus Voltage 3.0V */
-#define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000AU /**< Bus Voltage 1.8V */
-#define XSDPS_PC_EMMC_HW_RST_MASK 0x00000010U /**< HW reset for eMMC */
-
-#define XSDPS_BGC_STP_REQ_MASK 0x00000001U /**< Block Gap Stop Req */
-#define XSDPS_BGC_CNT_REQ_MASK 0x00000002U /**< Block Gap Cont Req */
-#define XSDPS_BGC_RWC_MASK 0x00000004U /**< Block Gap Rd Wait */
-#define XSDPS_BGC_INTR_MASK 0x00000008U /**< Block Gap Intr */
-#define XSDPS_BGC_SPI_MODE_MASK 0x00000010U /**< Block Gap SPI Mode */
-#define XSDPS_BGC_BOOT_EN_MASK 0x00000020U /**< Block Gap Boot Enb */
-#define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040U /**< Block Gap Alt BootEn */
-#define XSDPS_BGC_BOOT_ACK_MASK 0x00000080U /**< Block Gap Boot Ack */
-
-#define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001U /**< Wakeup Card Intr */
-#define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002U /**< Wakeup Card Insert */
-#define XSDPS_WC_WUP_ON_REM_MASK 0x00000004U /**< Wakeup Card Removal */
-
-/** @} */
-
-/** @name Control Register - Clock control, Timeout control & Software reset
- *
- * This register contains bits for configuration options of clock, timeout and
- * software reset.
- * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
- * @{
- */
-
-#define XSDPS_CC_INT_CLK_EN_MASK 0x00000001U /**< INT clk enable */
-#define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002U /**< INT clk stable */
-#define XSDPS_CC_SD_CLK_EN_MASK 0x00000004U /**< SD clk enable */
-#define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020U /**< SD clk gen selection */
-#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x00000003U /**< SD clk freq sel upper */
-#define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x000000FFU /**< SD clk freq sel */
-#define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000U /**< Divider 256 */
-#define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000U /**< Divider 128 */
-#define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000U /**< Divider 64 */
-#define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000U /**< Divider 32 */
-#define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800U /**< Divider 16 */
-#define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400U /**< Divider 8 */
-#define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200U /**< Divider 4 */
-#define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100U /**< Divider 2 */
-#define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000U /**< Base clock */
-#define XSDPS_CC_MAX_DIV_CNT 256U /**< Max divider count */
-#define XSDPS_CC_EXT_MAX_DIV_CNT 2046U /**< Max extended divider count */
-#define XSDPS_CC_EXT_DIV_SHIFT 6U /**< Ext divider shift */
-
-#define XSDPS_TC_CNTR_VAL_MASK 0x0000000FU /**< Data timeout counter */
-
-#define XSDPS_SWRST_ALL_MASK 0x00000001U /**< Software Reset All */
-#define XSDPS_SWRST_CMD_LINE_MASK 0x00000002U /**< Software reset for CMD line */
-#define XSDPS_SWRST_DAT_LINE_MASK 0x00000004U /**< Software reset for DAT line */
-
-#define XSDPS_CC_MAX_NUM_OF_DIV 9U /**< Max number of Clock dividers */
-#define XSDPS_CC_DIV_SHIFT 8U /**< Clock Divider shift */
-
-/** @} */
-
-/** @name SD Interrupt Registers
- *
- * Normal and Error Interrupt Status Register
- * This register shows the normal and error interrupt status.
- * Status enable register affects reads of this register.
- * If Signal enable register is set and the corresponding status bit is set,
- * interrupt is generated.
- * Write to clear except
- * Error_interrupt and Card_Interrupt bits - Read only
- *
- * Normal and Error Interrupt Status Enable Register
- * Setting this register bits enables Interrupt status.
- * Read/Write except Fixed_to_0 bit (Read only)
- *
- * Normal and Error Interrupt Signal Enable Register
- * This register is used to select which interrupt status is
- * indicated to the Host System as the interrupt.
- * Read/Write except Fixed_to_0 bit (Read only)
- *
- * All three registers have same bit definitions
- * @{
- */
-
-#define XSDPS_INTR_CC_MASK 0x00000001U /**< Command Complete */
-#define XSDPS_INTR_TC_MASK 0x00000002U /**< Transfer Complete */
-#define XSDPS_INTR_BGE_MASK 0x00000004U /**< Block Gap Event */
-#define XSDPS_INTR_DMA_MASK 0x00000008U /**< DMA Interrupt */
-#define XSDPS_INTR_BWR_MASK 0x00000010U /**< Buffer Write Ready */
-#define XSDPS_INTR_BRR_MASK 0x00000020U /**< Buffer Read Ready */
-#define XSDPS_INTR_CARD_INSRT_MASK 0x00000040U /**< Card Insert */
-#define XSDPS_INTR_CARD_REM_MASK 0x00000080U /**< Card Remove */
-#define XSDPS_INTR_CARD_MASK 0x00000100U /**< Card Interrupt */
-#define XSDPS_INTR_INT_A_MASK 0x00000200U /**< INT A Interrupt */
-#define XSDPS_INTR_INT_B_MASK 0x00000400U /**< INT B Interrupt */
-#define XSDPS_INTR_INT_C_MASK 0x00000800U /**< INT C Interrupt */
-#define XSDPS_INTR_RE_TUNING_MASK 0x00001000U /**< Re-Tuning Interrupt */
-#define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00002000U /**< Boot Ack Recv
- Interrupt */
-#define XSDPS_INTR_BOOT_TERM_MASK 0x00004000U /**< Boot Terminate
- Interrupt */
-#define XSDPS_INTR_ERR_MASK 0x00008000U /**< Error Interrupt */
-#define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFFU
-
-#define XSDPS_INTR_ERR_CT_MASK 0x00000001U /**< Command Timeout
- Error */
-#define XSDPS_INTR_ERR_CCRC_MASK 0x00000002U /**< Command CRC Error */
-#define XSDPS_INTR_ERR_CEB_MASK 0x00000004U /**< Command End Bit
- Error */
-#define XSDPS_INTR_ERR_CI_MASK 0x00000008U /**< Command Index Error */
-#define XSDPS_INTR_ERR_DT_MASK 0x00000010U /**< Data Timeout Error */
-#define XSDPS_INTR_ERR_DCRC_MASK 0x00000020U /**< Data CRC Error */
-#define XSDPS_INTR_ERR_DEB_MASK 0x00000040U /**< Data End Bit Error */
-#define XSDPS_INTR_ERR_CUR_LMT_MASK 0x00000080U /**< Current Limit Error */
-#define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100U /**< Auto CMD12 Error */
-#define XSDPS_INTR_ERR_ADMA_MASK 0x00000200U /**< ADMA Error */
-#define XSDPS_INTR_ERR_TR_MASK 0x00001000U /**< Tuning Error */
-#define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000U /**< Vendor Specific
- Error */
-#define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FFU /**< Mask for error bits */
-/** @} */
-
-/** @name Block Size and Block Count Register
- *
- * This register contains the block count for current transfer,
- * block size and SDMA buffer size.
- * Read/Write except for reserved bits.
- * @{
- */
-
-#define XSDPS_BLK_SIZE_MASK 0x00000FFFU /**< Transfer Block Size */
-#define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000U /**< Host SDMA Buffer Size */
-#define XSDPS_BLK_SIZE_1024 0x400U
-#define XSDPS_BLK_SIZE_2048 0x800U
-#define XSDPS_BLK_CNT_MASK 0x0000FFFFU /**< Block Count for
- Current Transfer */
-
-/** @} */
-
-/** @name Transfer Mode and Command Register
- *
- * The Transfer Mode register is used to control the data transfers and
- * Command register is used for command generation
- * Read/Write except for reserved bits.
- * @{
- */
-
-#define XSDPS_TM_DMA_EN_MASK 0x00000001U /**< DMA Enable */
-#define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002U /**< Block Count Enable */
-#define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004U /**< Auto CMD12 Enable */
-#define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010U /**< Data Transfer
- Direction Select */
-#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020U /**< Multi/Single
- Block Select */
-
-#define XSDPS_CMD_RESP_SEL_MASK 0x00000003U /**< Response Type
- Select */
-#define XSDPS_CMD_RESP_NONE_MASK 0x00000000U /**< No Response */
-#define XSDPS_CMD_RESP_L136_MASK 0x00000001U /**< Response length 138 */
-#define XSDPS_CMD_RESP_L48_MASK 0x00000002U /**< Response length 48 */
-#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003U /**< Response length 48 &
- check busy after
- response */
-#define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008U /**< Command CRC Check
- Enable */
-#define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010U /**< Command Index Check
- Enable */
-#define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020U /**< Data Present Select */
-#define XSDPS_CMD_TYPE_MASK 0x000000C0U /**< Command Type */
-#define XSDPS_CMD_TYPE_NORM_MASK 0x00000000U /**< CMD Type - Normal */
-#define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040U /**< CMD Type - Suspend */
-#define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080U /**< CMD Type - Resume */
-#define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0U /**< CMD Type - Abort */
-#define XSDPS_CMD_MASK 0x00003F00U /**< Command Index Mask -
- Set to CMD0-63,
- AMCD0-63 */
-
-/** @} */
-
-/** @name Auto CMD Error Status Register
- *
- * This register is read only register which contains
- * information about the error status of Auto CMD 12 and 23.
- * Read Only
- * @{
- */
-#define XSDPS_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
- executed */
-#define XSDPS_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
- Error */
-#define XSDPS_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
-#define XSDPS_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
- Error */
-#define XSDPS_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
-#define XSDPS_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
- Auto CMD12 Error */
-/** @} */
-
-/** @name Host Control2 Register
- *
- * This register contains extended configuration bits.
- * Read Write
- * @{
- */
-#define XSDPS_HC2_UHS_MODE_MASK 0x0007U /**< UHS Mode select bits */
-#define XSDPS_HC2_UHS_MODE_SDR12_MASK 0x0000U /**< SDR12 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_SDR25_MASK 0x0001U /**< SDR25 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_SDR50_MASK 0x0002U /**< SDR50 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_SDR104_MASK 0x0003U /**< SDR104 UHS Mode */
-#define XSDPS_HC2_UHS_MODE_DDR50_MASK 0x0004U /**< DDR50 UHS Mode */
-#define XSDPS_HC2_1V8_EN_MASK 0x0008U /**< 1.8V Signal Enable */
-#define XSDPS_HC2_DRV_STR_SEL_MASK 0x0030U /**< Driver Strength
- Selection */
-#define XSDPS_HC2_DRV_STR_B_MASK 0x0000U /**< Driver Strength B */
-#define XSDPS_HC2_DRV_STR_A_MASK 0x0010U /**< Driver Strength A */
-#define XSDPS_HC2_DRV_STR_C_MASK 0x0020U /**< Driver Strength C */
-#define XSDPS_HC2_DRV_STR_D_MASK 0x0030U /**< Driver Strength D */
-#define XSDPS_HC2_EXEC_TNG_MASK 0x0040U /**< Execute Tuning */
-#define XSDPS_HC2_SAMP_CLK_SEL_MASK 0x0080U /**< Sampling Clock
- Selection */
-#define XSDPS_HC2_ASYNC_INTR_EN_MASK 0x4000U /**< Asynchronous Interrupt
- Enable */
-#define XSDPS_HC2_PRE_VAL_EN_MASK 0x8000U /**< Preset Value Enable */
-
-/** @} */
-
-/** @name Capabilities Register
- *
- * Capabilities register is a read only register which contains
- * information about the host controller.
- * Sufficient if read once after power on.
- * Read Only
- * @{
- */
-#define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003FU /**< Timeout clock freq
- select */
-#define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080U /**< Timeout clock unit -
- MHz/KHz */
-#define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000U /**< Max block length */
-#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000U /**< Max block 512 bytes */
-#define XSDPS_CAP_MAX_BL_LN_1024_MASK 0x00010000U /**< Max block 1024 bytes */
-#define XSDPS_CAP_MAX_BL_LN_2048_MASK 0x00020000U /**< Max block 2048 bytes */
-#define XSDPS_CAP_MAX_BL_LN_4096_MASK 0x00030000U /**< Max block 4096 bytes */
-
-#define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000U /**< Extended media bus */
-#define XSDPS_CAP_ADMA2_MASK 0x00080000U /**< ADMA2 support */
-#define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000U /**< High speed support */
-#define XSDPS_CAP_SDMA_MASK 0x00400000U /**< SDMA support */
-#define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000U /**< Suspend/Resume
- support */
-#define XSDPS_CAP_VOLT_3V3_MASK 0x01000000U /**< 3.3V support */
-#define XSDPS_CAP_VOLT_3V0_MASK 0x02000000U /**< 3.0V support */
-#define XSDPS_CAP_VOLT_1V8_MASK 0x04000000U /**< 1.8V support */
-
-#define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000U /**< 64 bit system bus
- support */
-/* Spec 2.0 */
-#define XSDPS_CAP_INTR_MODE_MASK 0x08000000U /**< Interrupt mode
- support */
-#define XSDPS_CAP_SPI_MODE_MASK 0x20000000U /**< SPI mode */
-#define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x40000000U /**< SPI block mode */
-
-
-/* Spec 3.0 */
-#define XSDPS_CAPS_ASYNC_INTR_MASK 0x20000000U /**< Async Interrupt
- support */
-#define XSDPS_CAPS_SLOT_TYPE_MASK 0xC0000000U /**< Slot Type */
-#define XSDPS_CAPS_REM_CARD 0x00000000U /**< Removable Slot */
-#define XSDPS_CAPS_EMB_SLOT 0x40000000U /**< Embedded Slot */
-#define XSDPS_CAPS_SHR_BUS 0x80000000U /**< Shared Bus Slot */
-
-#define XSDPS_ECAPS_SDR50_MASK 0x00000001U /**< SDR50 Mode support */
-#define XSDPS_ECAPS_SDR104_MASK 0x00000002U /**< SDR104 Mode support */
-#define XSDPS_ECAPS_DDR50_MASK 0x00000004U /**< DDR50 Mode support */
-#define XSDPS_ECAPS_DRV_TYPE_A_MASK 0x00000010U /**< DriverType A support */
-#define XSDPS_ECAPS_DRV_TYPE_C_MASK 0x00000020U /**< DriverType C support */
-#define XSDPS_ECAPS_DRV_TYPE_D_MASK 0x00000040U /**< DriverType D support */
-#define XSDPS_ECAPS_TMR_CNT_MASK 0x00000F00U /**< Timer Count for
- Re-tuning */
-#define XSDPS_ECAPS_USE_TNG_SDR50_MASK 0x00002000U /**< SDR50 Mode needs
- tuning */
-#define XSDPS_ECAPS_RE_TNG_MODES_MASK 0x0000C000U /**< Re-tuning modes
- support */
-#define XSDPS_ECAPS_RE_TNG_MODE1_MASK 0x00000000U /**< Re-tuning mode 1 */
-#define XSDPS_ECAPS_RE_TNG_MODE2_MASK 0x00004000U /**< Re-tuning mode 2 */
-#define XSDPS_ECAPS_RE_TNG_MODE3_MASK 0x00008000U /**< Re-tuning mode 3 */
-#define XSDPS_ECAPS_CLK_MULT_MASK 0x00FF0000U /**< Clock Multiplier value
- for Programmable clock
- mode */
-#define XSDPS_ECAPS_SPI_MODE_MASK 0x01000000U /**< SPI mode */
-#define XSDPS_ECAPS_SPI_BLK_MODE_MASK 0x02000000U /**< SPI block mode */
-
-/** @} */
-
-/** @name Present State Register
- *
- * Gives the current status of the host controller
- * Read Only
- * @{
- */
-
-#define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001U /**< Command inhibit - CMD */
-#define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002U /**< Command Inhibit - DAT */
-#define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004U /**< DAT line active */
-#define XSDPS_PSR_RE_TUNING_REQ_MASK 0x00000008U /**< Re-tuning request */
-#define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100U /**< Write transfer active */
-#define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200U /**< Read transfer active */
-#define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400U /**< Buffer write enable */
-#define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800U /**< Buffer read enable */
-#define XSDPS_PSR_CARD_INSRT_MASK 0x00010000U /**< Card inserted */
-#define XSDPS_PSR_CARD_STABLE_MASK 0x00020000U /**< Card state stable */
-#define XSDPS_PSR_CARD_DPL_MASK 0x00040000U /**< Card detect pin level */
-#define XSDPS_PSR_WPS_PL_MASK 0x00080000U /**< Write protect switch
- pin level */
-#define XSDPS_PSR_DAT30_SG_LVL_MASK 0x00F00000U /**< Data 3:0 signal lvl */
-#define XSDPS_PSR_CMD_SG_LVL_MASK 0x01000000U /**< Cmd Line signal lvl */
-#define XSDPS_PSR_DAT74_SG_LVL_MASK 0x1E000000U /**< Data 7:4 signal lvl */
-
-/** @} */
-
-/** @name Maximum Current Capabilities Register
- *
- * This register is read only register which contains
- * information about current capabilities at each voltage levels.
- * Read Only
- * @{
- */
-#define XSDPS_MAX_CUR_CAPS_1V8_MASK 0x00000F00U /**< Maximum Current
- Capability at 1.8V */
-#define XSDPS_MAX_CUR_CAPS_3V0_MASK 0x000000F0U /**< Maximum Current
- Capability at 3.0V */
-#define XSDPS_MAX_CUR_CAPS_3V3_MASK 0x0000000FU /**< Maximum Current
- Capability at 3.3V */
-/** @} */
-
-
-/** @name Force Event for Auto CMD Error Status Register
- *
- * This register is write only register which contains
- * control bits to generate events for Auto CMD error status.
- * Write Only
- * @{
- */
-#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not
- executed */
-#define XSDPS_FE_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout
- Error */
-#define XSDPS_FE_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */
-#define XSDPS_FE_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit
- Error */
-#define XSDPS_FE_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */
-#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by
- Auto CMD12 Error */
-/** @} */
-
-
-
-/** @name Force Event for Error Interrupt Status Register
- *
- * This register is write only register which contains
- * control bits to generate events of error interrupt status register.
- * Write Only
- * @{
- */
-#define XSDPS_FE_INTR_ERR_CT_MASK 0x0001U /**< Command Timeout
- Error */
-#define XSDPS_FE_INTR_ERR_CCRC_MASK 0x0002U /**< Command CRC Error */
-#define XSDPS_FE_INTR_ERR_CEB_MASK 0x0004U /**< Command End Bit
- Error */
-#define XSDPS_FE_INTR_ERR_CI_MASK 0x0008U /**< Command Index Error */
-#define XSDPS_FE_INTR_ERR_DT_MASK 0x0010U /**< Data Timeout Error */
-#define XSDPS_FE_INTR_ERR_DCRC_MASK 0x0020U /**< Data CRC Error */
-#define XSDPS_FE_INTR_ERR_DEB_MASK 0x0040U /**< Data End Bit Error */
-#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK 0x0080U /**< Current Limit Error */
-#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK 0x0100U /**< Auto CMD Error */
-#define XSDPS_FE_INTR_ERR_ADMA_MASK 0x0200U /**< ADMA Error */
-#define XSDPS_FE_INTR_ERR_TR_MASK 0x1000U /**< Target Response */
-#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK 0xE000U /**< Vendor Specific
- Error */
-
-/** @} */
-
-/** @name ADMA Error Status Register
- *
- * This register is read only register which contains
- * status information about ADMA errors.
- * Read Only
- * @{
- */
-#define XSDPS_ADMA_ERR_MM_LEN_MASK 0x04U /**< ADMA Length Mismatch
- Error */
-#define XSDPS_ADMA_ERR_STATE_MASK 0x03U /**< ADMA Error State */
-#define XSDPS_ADMA_ERR_STATE_STOP_MASK 0x00U /**< ADMA Error State
- STOP */
-#define XSDPS_ADMA_ERR_STATE_FDS_MASK 0x01U /**< ADMA Error State
- FDS */
-#define XSDPS_ADMA_ERR_STATE_TFR_MASK 0x03U /**< ADMA Error State
- TFR */
-/** @} */
-
-/** @name Preset Values Register
- *
- * This register is read only register which contains
- * preset values for each of speed modes.
- * Read Only
- * @{
- */
-#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK 0x03FFU /**< SDCLK Frequency
- Select Value */
-#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK 0x0400U /**< Clock Generator
- Mode Select */
-#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK 0xC000U /**< Driver Strength
- Select Value */
-
-/** @} */
-
-/** @name Slot Interrupt Status Register
- *
- * This register is read only register which contains
- * interrupt slot signal for each slot.
- * Read Only
- * @{
- */
-#define XSDPS_SLOT_INTR_STS_INT_MASK 0x0007U /**< Interrupt Signal
- mask */
-
-/** @} */
-
-/** @name Host Controller Version Register
- *
- * This register is read only register which contains
- * Host Controller and Vendor Specific version.
- * Read Only
- * @{
- */
-#define XSDPS_HC_VENDOR_VER 0xFF00U /**< Vendor
- Specification
- version mask */
-#define XSDPS_HC_SPEC_VER_MASK 0x00FFU /**< Host
- Specification
- version mask */
-#define XSDPS_HC_SPEC_V3 0x0002U /**< HC spec version 3 */
-#define XSDPS_HC_SPEC_V2 0x0001U /**< HC spec version 2 */
-#define XSDPS_HC_SPEC_V1 0x0000U /**< HC spec version 1 */
-/** @} */
-
-/** @name Block size mask for 512 bytes
- *
- * Block size mask for 512 bytes - This is the default block size.
- * @{
- */
-
-#define XSDPS_BLK_SIZE_512_MASK 0x200U /**< Blk Size 512 */
-
-/** @} */
-
-/** @name Commands
- *
- * Constant definitions for commands and response related to SD
- * @{
- */
-/**
- * Command/Response related to SD/eMMC
- */
-
-#define XSDPS_APP_CMD_PREFIX 0x8000U
-#define CMD0 0x0000U
-#define CMD1 0x0100U
-#define CMD2 0x0200U
-#define CMD3 0x0300U
-#define CMD4 0x0400U
-#define CMD5 0x0500U
-#define CMD6 0x0600U
-#define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600U)
-#define CMD7 0x0700U
-#define CMD8 0x0800U
-#define CMD9 0x0900U
-#define CMD10 0x0A00U
-#define CMD11 0x0B00U
-#define CMD12 0x0C00U
-#define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00U)
-#define CMD16 0x1000U
-#define CMD17 0x1100U
-#define CMD18 0x1200U
-#define CMD19 0x1300U
-#define CMD21 0x1500U
-#define CMD23 0x1700U
-#define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700U)
-#define CMD24 0x1800U
-#define CMD25 0x1900U
-#define CMD41 0x2900U
-#define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900U)
-#define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00U)
-#define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300U)
-#define CMD52 0x3400U
-#define CMD55 0x3700U
-#define CMD58 0x3A00U
-
-#define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK
-#define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
- (u32)XSDPS_CMD_INX_CHK_EN_MASK
-
-#define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
- (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
-
-#define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
-#define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK
-
-#define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
- (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
-
-/** @} */
-
-/**
- * @name Card Interface
- * @{
- */
-/**
- * Card Interface Conditions Definitions
- */
-#define XSDPS_CIC_CHK_PATTERN 0xAAU
-#define XSDPS_CIC_VOLT_MASK (0xFU<<8)
-#define XSDPS_CIC_VOLT_2V7_3V6 (1U<<8)
-#define XSDPS_CIC_VOLT_LOW (1U<<9)
-/** @} */
-
-/**
- * @name OCR
- * @{
- */
-/**
- * Operation Conditions Register Definitions
- */
-#define XSDPS_OCR_PWRUP_STS (1U<<31)
-#define XSDPS_OCR_CC_STS (1U<<30)
-#define XSDPS_OCR_S18 (1U<<24)
-#define XSDPS_OCR_3V5_3V6 (1U<<23)
-#define XSDPS_OCR_3V4_3V5 (1U<<22)
-#define XSDPS_OCR_3V3_3V4 (1U<<21)
-#define XSDPS_OCR_3V2_3V3 (1U<<20)
-#define XSDPS_OCR_3V1_3V2 (1U<<19)
-#define XSDPS_OCR_3V0_3V1 (1U<<18)
-#define XSDPS_OCR_2V9_3V0 (1U<<17)
-#define XSDPS_OCR_2V8_2V9 (1U<<16)
-#define XSDPS_OCR_2V7_2V8 (1U<<15)
-#define XSDPS_OCR_1V7_1V95 (1U<<7)
-#define XSDPS_OCR_HIGH_VOL 0x00FF8000U
-#define XSDPS_OCR_LOW_VOL 0x00000080U
-/** @} */
-
-/**
- * @name Card Configuration
- * @{
- */
-/**
- * SD Card Configuration Register Definitions
- */
-#define XSDPS_SCR_REG_LEN 8U
-#define XSDPS_SCR_STRUCT_MASK (0xFU<<28)
-#define XSDPS_SCR_SPEC_MASK (0xFU<<24)
-#define XSDPS_SCR_SPEC_1V0 0U
-#define XSDPS_SCR_SPEC_1V1 (1U<<24)
-#define XSDPS_SCR_SPEC_2V0_3V0 (2U<<24)
-#define XSDPS_SCR_MEM_VAL_AF_ERASE (1U<<23)
-#define XSDPS_SCR_SEC_SUPP_MASK (7U<<20)
-#define XSDPS_SCR_SEC_SUPP_NONE 0U
-#define XSDPS_SCR_SEC_SUPP_1V1 (2U<<20)
-#define XSDPS_SCR_SEC_SUPP_2V0 (3U<<20)
-#define XSDPS_SCR_SEC_SUPP_3V0 (4U<<20)
-#define XSDPS_SCR_BUS_WIDTH_MASK (0xFU<<16)
-#define XSDPS_SCR_BUS_WIDTH_1 (1U<<16)
-#define XSDPS_SCR_BUS_WIDTH_4 (4U<<16)
-#define XSDPS_SCR_SPEC3_MASK (1U<<12)
-#define XSDPS_SCR_SPEC3_2V0 0U
-#define XSDPS_SCR_SPEC3_3V0 (1U<<12)
-#define XSDPS_SCR_CMD_SUPP_MASK 0x3U
-#define XSDPS_SCR_CMD23_SUPP (1U<<1)
-#define XSDPS_SCR_CMD20_SUPP (1U<<0)
-/** @} */
-
-/**
- * @name Card Status
- * @{
- */
-/**
- * Card Status Register Definitions
- */
-#define XSDPS_CD_STS_OUT_OF_RANGE (1U<<31)
-#define XSDPS_CD_STS_ADDR_ERR (1U<<30)
-#define XSDPS_CD_STS_BLK_LEN_ERR (1U<<29)
-#define XSDPS_CD_STS_ER_SEQ_ERR (1U<<28)
-#define XSDPS_CD_STS_ER_PRM_ERR (1U<<27)
-#define XSDPS_CD_STS_WP_VIO (1U<<26)
-#define XSDPS_CD_STS_IS_LOCKED (1U<<25)
-#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL (1U<<24)
-#define XSDPS_CD_STS_CMD_CRC_ERR (1U<<23)
-#define XSDPS_CD_STS_ILGL_CMD (1U<<22)
-#define XSDPS_CD_STS_CARD_ECC_FAIL (1U<<21)
-#define XSDPS_CD_STS_CC_ERR (1U<<20)
-#define XSDPS_CD_STS_ERR (1U<<19)
-#define XSDPS_CD_STS_CSD_OVRWR (1U<<16)
-#define XSDPS_CD_STS_WP_ER_SKIP (1U<<15)
-#define XSDPS_CD_STS_CARD_ECC_DIS (1U<<14)
-#define XSDPS_CD_STS_ER_RST (1U<<13)
-#define XSDPS_CD_STS_CUR_STATE (0xFU<<9)
-#define XSDPS_CD_STS_RDY_FOR_DATA (1U<<8)
-#define XSDPS_CD_STS_APP_CMD (1U<<5)
-#define XSDPS_CD_STS_AKE_SEQ_ERR (1U<<2)
-/** @} */
-
-/**
- * @name Switch function
- * @{
- */
-/**
- * Switch Function Definitions CMD6
- */
-#define XSDPS_SWITCH_SD_RESP_LEN 64U
-
-#define XSDPS_SWITCH_FUNC_SWITCH (1U<<31)
-#define XSDPS_SWITCH_FUNC_CHECK 0U
-/** @} */
-
-/**
- * @name Mode Function
- * @{
- */
-/**
- * Mode function groups definitions.
- */
-#define XSDPS_MODE_FUNC_GRP1 1U
-#define XSDPS_MODE_FUNC_GRP2 2U
-#define XSDPS_MODE_FUNC_GRP3 3U
-#define XSDPS_MODE_FUNC_GRP4 4U
-#define XSDPS_MODE_FUNC_GRP5 5U
-#define XSDPS_MODE_FUNC_GRP6 6U
-
-#define XSDPS_FUNC_GRP_DEF_VAL 0xFU
-#define XSDPS_FUNC_ALL_GRP_DEF_VAL 0xFFFFFFU
-/** @} */
-
-/**
- * @name Operating modes
- * @{
- */
-/**
- * SD operating modes in UHS.
- */
-#define XSDPS_ACC_MODE_DEF_SDR12 0U
-#define XSDPS_ACC_MODE_HS_SDR25 1U
-#define XSDPS_ACC_MODE_SDR50 2U
-#define XSDPS_ACC_MODE_SDR104 3U
-#define XSDPS_ACC_MODE_DDR50 4U
-/** @} */
-
-/**
- * @name General definitions
- * @{
- */
-/**
- * Definitions related to Driver strength, Current limit and
- * CSD specific data.
- */
-#define XSDPS_CMD_SYS_ARG_SHIFT 4U
-#define XSDPS_CMD_SYS_DEF 0U
-#define XSDPS_CMD_SYS_eC 1U
-#define XSDPS_CMD_SYS_OTP 3U
-#define XSDPS_CMD_SYS_ASSD 4U
-#define XSDPS_CMD_SYS_VEND 5U
-
-#define XSDPS_DRV_TYPE_ARG_SHIFT 8U
-#define XSDPS_DRV_TYPE_B 0U
-#define XSDPS_DRV_TYPE_A 1U
-#define XSDPS_DRV_TYPE_C 2U
-#define XSDPS_DRV_TYPE_D 3U
-
-#define XSDPS_CUR_LIM_ARG_SHIFT 12U
-#define XSDPS_CUR_LIM_200 0U
-#define XSDPS_CUR_LIM_400 1U
-#define XSDPS_CUR_LIM_600 2U
-#define XSDPS_CUR_LIM_800 3U
-
-#define CSD_SPEC_VER_MASK 0x3C0000U
-#define READ_BLK_LEN_MASK 0x00000F00U
-#define C_SIZE_MULT_MASK 0x00000380U
-#define C_SIZE_LOWER_MASK 0xFFC00000U
-#define C_SIZE_UPPER_MASK 0x00000003U
-#define CSD_STRUCT_MASK 0x00C00000U
-#define CSD_V2_C_SIZE_MASK 0x3FFFFF00U
-/** @} */
-
-/**
- * @name Extended Card Specific Data
- * @{
- */
-/**
- * EXT_CSD field definitions
- */
-#define XSDPS_EXT_CSD_SIZE 512U
-
-#define EXT_CSD_WR_REL_PARAM_EN (1U<<2)
-
-#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40U)
-#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10U)
-#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04U)
-#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01U)
-
-#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7U)
-#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1U)
-#define EXT_CSD_PART_CONFIG_ACC_BOOT1 (0x2U)
-#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U)
-#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U)
-#define EXT_CSD_PART_CONFIG_BYTE (179U)
-#define XSDPS_MMC_PART_CFG_0_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
- | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
- | ((u32)(0U) << 8U))
-
-#define XSDPS_MMC_PART_CFG_1_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
- | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
- | ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT0 << 8U))
-
-#define XSDPS_MMC_PART_CFG_2_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24U) \
- | ((u32)EXT_CSD_PART_CONFIG_BYTE << 16U) \
- | ((u32)EXT_CSD_PART_CONFIG_ACC_BOOT1 << 8U))
-
-#define EXT_CSD_PART_SUPPORT_PART_EN (0x1U)
-
-#define EXT_CSD_CMD_SET_NORMAL (1U<<0)
-#define EXT_CSD_CMD_SET_SECURE (1U<<1)
-#define EXT_CSD_CMD_SET_CPSECURE (1U<<2)
-
-#define EXT_CSD_CARD_TYPE_26 (1U<<0) /* Card can run at 26MHz */
-#define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */
-#define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */
-#define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */
- /* DDR mode @1.8V or 3V I/O */
-#define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */
- /* DDR mode @1.2V I/O */
-#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
- | EXT_CSD_CARD_TYPE_DDR_1_2V)
-#define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */
-#define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */
- /* SDR mode @1.2V I/O */
-#define EXT_CSD_BUS_WIDTH_BYTE 183U
-#define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */
-#define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */
-#define EXT_CSD_BUS_WIDTH_8_BIT 2U /* Card is in 8 bit mode */
-#define EXT_CSD_BUS_WIDTH_DDR_4_BIT 5U /* Card is in 4 bit DDR mode */
-#define EXT_CSD_BUS_WIDTH_DDR_8_BIT 6U /* Card is in 8 bit DDR mode */
-
-#define EXT_CSD_HS_TIMING_BYTE 185U
-#define EXT_CSD_HS_TIMING_DEF 0U
-#define EXT_CSD_HS_TIMING_HIGH 1U /* Card is in high speed mode */
-#define EXT_CSD_HS_TIMING_HS200 2U /* Card is in HS200 mode */
-
-#define EXT_CSD_RST_N_FUN_BYTE 162U
-#define EXT_CSD_RST_N_FUN_TEMP_DIS 0U /* RST_n signal is temporarily disabled */
-#define EXT_CSD_RST_N_FUN_PERM_EN 1U /* RST_n signal is permanently enabled */
-#define EXT_CSD_RST_N_FUN_PERM_DIS 2U /* RST_n signal is permanently disabled */
-
-#define XSDPS_EXT_CSD_CMD_SET 0U
-#define XSDPS_EXT_CSD_SET_BITS 1U
-#define XSDPS_EXT_CSD_CLR_BITS 2U
-#define XSDPS_EXT_CSD_WRITE_BYTE 3U
-/** @} */
-
-/**
- * @name SD/eMMC Bus Speed and Bus Width Arguments
- * @{
- */
-/**
- * SD/MMC Arguments for Bus Speed and Bus Width.
- */
-#define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
- | ((u32)EXT_CSD_HS_TIMING_DEF << 8))
-
-#define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
- | ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
-
-#define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
- | ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
-
-#define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8))
-
-#define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
-
-#define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
-
-#define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
-
-#define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
- | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
-
-#define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
- | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
- | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
-
-#define XSDPS_MMC_DELAY_FOR_SWITCH 1000U
-
-/** @} */
-
-/**
- * @name General Delay definitions
- * @{
- */
-/**
- * @400KHz, in usec
- */
-#define XSDPS_74CLK_DELAY 2960U
-#define XSDPS_100CLK_DELAY 4000U
-#define XSDPS_INIT_DELAY 10000U
-/** @} */
-
-#define XSDPS_DEF_VOLT_LVL XSDPS_PC_BUS_VSEL_3V0_MASK /**< Default voltage level */
-#define XSDPS_CARD_DEF_ADDR 0x1234U /**< Card Default address */
-
-#define XSDPS_CARD_SD 1U /**< SD card */
-#define XSDPS_CARD_MMC 2U /**< MMC card */
-#define XSDPS_CARD_SDIO 3U /**< SDIO card */
-#define XSDPS_CARD_SDCOMBO 4U /**< SDCOMBO card */
-#define XSDPS_CHIP_EMMC 5U /**< EMMC chip */
-
-
-/**
- *@name ADMA2 Descriptor related definitions
- * @{
- */
-/**
- * ADMA2 Descriptor related definitions
- */
-#define XSDPS_DESC_MAX_LENGTH 65536U
-
-#define XSDPS_DESC_VALID (0x1U << 0)
-#define XSDPS_DESC_END (0x1U << 1)
-#define XSDPS_DESC_INT (0x1U << 2)
-#define XSDPS_DESC_TRAN (0x2U << 4)
-
-/** @} */
-
-/* For changing clock frequencies */
-#define XSDPS_CLK_400_KHZ 400000U /**< 400 KHZ */
-#define XSDPS_CLK_50_MHZ 50000000U /**< 50 MHZ */
-#define XSDPS_CLK_52_MHZ 52000000U /**< 52 MHZ */
-#define XSDPS_SD_VER_1_0 0x1U /**< SD ver 1 */
-#define XSDPS_SD_VER_2_0 0x2U /**< SD ver 2 */
-#define XSDPS_SCR_BLKCNT 1U /**< SCR Block Count */
-#define XSDPS_SCR_BLKSIZE 8U /**< SCR Block Size */
-#define XSDPS_1_BIT_WIDTH 0x1U /**< Bus Width 1 */
-#define XSDPS_4_BIT_WIDTH 0x2U /**< Bus Width 4 */
-#define XSDPS_8_BIT_WIDTH 0x3U /**< Bus Width 8 */
-#define XSDPS_UHS_SPEED_MODE_SDR12 0x0U /**< SDR12 mode */
-#define XSDPS_UHS_SPEED_MODE_SDR25 0x1U /**< SDR25 mode */
-#define XSDPS_UHS_SPEED_MODE_SDR50 0x2U /**< SDR50 mode */
-#define XSDPS_UHS_SPEED_MODE_SDR104 0x3U /**< SDR104 mode */
-#define XSDPS_UHS_SPEED_MODE_DDR50 0x4U /**< DDR50 mode */
-#define XSDPS_HIGH_SPEED_MODE 0x5U /**< High Speed mode */
-#define XSDPS_DEFAULT_SPEED_MODE 0x6U /**< Default speed mode */
-#define XSDPS_HS200_MODE 0x7U /**< eMMC HS200 mode */
-#define XSDPS_DDR52_MODE 0x4U /**< eMMC DDR52 mode */
-#define XSDPS_SWITCH_CMD_BLKCNT 1U /**< Blk cnt for SWITCH cmd */
-#define XSDPS_SWITCH_CMD_BLKSIZE 64U /**< Blk sz for SWITCH cmd */
-#define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U /**< SWITCH cmd to Get HS */
-#define XSDPS_SWITCH_CMD_HS_SET 0x80FFFFF1U /**< SWITCH cmd to Set HS */
-#define XSDPS_SWITCH_CMD_SDR12_SET 0x80FFFFF0U /**< SWITCH cmd to Set SDR12 */
-#define XSDPS_SWITCH_CMD_SDR25_SET 0x80FFFFF1U /**< SWITCH cmd to Set SDR25 */
-#define XSDPS_SWITCH_CMD_SDR50_SET 0x80FFFFF2U /**< SWITCH cmd to Set SDR50 */
-#define XSDPS_SWITCH_CMD_SDR104_SET 0x80FFFFF3U /**< SWITCH cmd to Set SDR104 */
-#define XSDPS_SWITCH_CMD_DDR50_SET 0x80FFFFF4U /**< SWITCH cmd to Set DDR50 */
-#define XSDPS_EXT_CSD_CMD_BLKCNT 1U /**< Blk Cnt for EXT CSD */
-#define XSDPS_EXT_CSD_CMD_BLKSIZE 512U /**< Blk Sz for EXT CSD */
-#define XSDPS_TUNING_CMD_BLKCNT 1U /**< Blk Cnt for Tuning cmd */
-#define XSDPS_TUNING_CMD_BLKSIZE 64U /**< Blk Sz for Tuning cmd */
-#define XSDPS_SD_STATUS_BLKCNT 1U /**< Blk Cnt for SD status */
-#define XSDPS_SD_STATUS_BLKSIZE 64U /**< Blk Sz for SD status */
-
-#define XSDPS_HIGH_SPEED_MAX_CLK 50000000U /**< Max clk for HS mode */
-#define XSDPS_UHS_SDR104_MAX_CLK 208000000U /**< Max clk for SDR104 mode */
-#define XSDPS_UHS_SDR50_MAX_CLK 100000000U /**< Max clk for SDR50 mode */
-#define XSDPS_UHS_DDR50_MAX_CLK 50000000U /**< Max clk for DDR50 mode */
-#define XSDPS_UHS_SDR25_MAX_CLK 50000000U /**< Max clk for SDR25 mode */
-#define XSDPS_UHS_SDR12_MAX_CLK 25000000U /**< Max clk for SDR12 mode */
-
-#define SD_DRIVER_TYPE_B 0x01U /**< Driver Type B */
-#define SD_DRIVER_TYPE_A 0x02U /**< Driver Type A */
-#define SD_DRIVER_TYPE_C 0x04U /**< Driver Type C */
-#define SD_DRIVER_TYPE_D 0x08U /**< Driver Type D */
-#define SD_SET_CURRENT_LIMIT_200 0U /**< Current limit 200mA */
-#define SD_SET_CURRENT_LIMIT_400 1U /**< Current limit 400mA */
-#define SD_SET_CURRENT_LIMIT_600 2U /**< Current limit 600mA */
-#define SD_SET_CURRENT_LIMIT_800 3U /**< Current limit 800mA */
-
-#define SD_MAX_CURRENT_200 (1U << SD_SET_CURRENT_LIMIT_200) /**< Current limit 200mA Arg */
-#define SD_MAX_CURRENT_400 (1U << SD_SET_CURRENT_LIMIT_400) /**< Current limit 400mA Arg */
-#define SD_MAX_CURRENT_600 (1U << SD_SET_CURRENT_LIMIT_600) /**< Current limit 600mA Arg */
-#define SD_MAX_CURRENT_800 (1U << SD_SET_CURRENT_LIMIT_800) /**< Current limit 800mA Arg */
-
-#define XSDPS_SD_SDR12_MAX_CLK 25000000U /**< Max clk for SDR12 mode */
-#define XSDPS_SD_SDR25_MAX_CLK 50000000U /**< Max clk for SDR25 mode */
-#define XSDPS_SD_SDR50_MAX_CLK 100000000U /**< Max clk for SDR50 mode */
-#define XSDPS_SD_DDR50_MAX_CLK 50000000U /**< Max clk for DDR50 mode */
-#define XSDPS_SD_SDR104_MAX_CLK 208000000U /**< Max clk for SDR104 mode */
-/**
- * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller
- * than the clock value coming from the core. This value is kept to safely
- * switch to SDR104 mode if the SD card supports it.
- */
-#define XSDPS_SD_INPUT_MAX_CLK 175000000U
-
-#define XSDPS_MMC_HS200_MAX_CLK 200000000U /**< Max clk for MMC HS200 mode */
-#define XSDPS_MMC_HSD_MAX_CLK 52000000U /**< Max clk for MMC HSD mode */
-#define XSDPS_MMC_DDR_MAX_CLK 52000000U /**< Max clk for MMC DDR52 mode */
-
-/**
- * @name Card states
- * @{
- */
-/**
- * Definition for Card state.
- */
-#define XSDPS_CARD_STATE_IDLE 0U
-#define XSDPS_CARD_STATE_RDY 1U
-#define XSDPS_CARD_STATE_IDEN 2U
-#define XSDPS_CARD_STATE_STBY 3U
-#define XSDPS_CARD_STATE_TRAN 4U
-#define XSDPS_CARD_STATE_DATA 5U
-#define XSDPS_CARD_STATE_RCV 6U
-#define XSDPS_CARD_STATE_PROG 7U
-#define XSDPS_CARD_STATE_DIS 8U
-#define XSDPS_CARD_STATE_BTST 9U
-#define XSDPS_CARD_STATE_SLP 10U
-/** @} */
-
-#define XSDPS_SLOT_REM 0U /**< Removable slot */
-#define XSDPS_SLOT_EMB 1U /**< Embedded slot */
-
-#define XSDPS_WIDTH_8 8U /**< Bus width 8 */
-#define XSDPS_WIDTH_4 4U /**< Bus width 4 */
-
-/**
- * @name Tap delays
- * @{
- */
-/**
- * SD/eMMC ITAP and OTAP delays for different operating modes
- * for both Versal and ZynqMP platforms.
- */
-#ifdef versal
-#define SD_ITAPDLY_SEL_MASK 0x000000FFU
-#define SD_OTAPDLY_SEL_MASK 0x0000003FU
-#define SD_ITAPDLY 0x0000F0F8U
-#define SD_OTAPDLY 0x0000F0FCU
-#define SD0_DLL_CTRL 0x00000448U
-#define SD1_DLL_CTRL 0x000004C8U
-#define SD_DLL_RST 0x00000004U
-#define SD_ITAPCHGWIN 0x00000200U
-#define SD_ITAPDLYENA 0x00000100U
-#define SD_OTAPDLYENA 0x00000040U
-#define SD_OTAPDLYSEL_HS200_B0 0x00000002U
-#define SD_OTAPDLYSEL_HS200_B2 0x00000002U
-#define SD_ITAPDLYSEL_SD50 0x0000000EU
-#define SD_OTAPDLYSEL_SD50 0x00000003U
-#define SD_ITAPDLYSEL_SD_DDR50 0x00000036U
-#define SD_ITAPDLYSEL_EMMC_DDR50 0x0000001EU
-#define SD_OTAPDLYSEL_SD_DDR50 0x00000003U
-#define SD_OTAPDLYSEL_EMMC_DDR50 0x00000005U
-#define SD_ITAPDLYSEL_HSD 0x0000002CU
-#define SD_OTAPDLYSEL_SD_HSD 0x00000004U
-#define SD_OTAPDLYSEL_EMMC_HSD 0x00000005U
-#else
-#define SD0_ITAPDLY_SEL_MASK 0x000000FFU
-#define SD0_OTAPDLY_SEL_MASK 0x0000003FU
-#define SD1_ITAPDLY_SEL_MASK 0x00FF0000U
-#define SD1_OTAPDLY_SEL_MASK 0x003F0000U
-#define SD_DLL_CTRL 0x00000358U
-#define SD_ITAPDLY 0x00000314U
-#define SD_OTAPDLY 0x00000318U
-#define SD0_DLL_RST 0x00000004U
-#define SD1_DLL_RST 0x00040000U
-#define SD0_ITAPCHGWIN 0x00000200U
-#define SD0_ITAPDLYENA 0x00000100U
-#define SD0_OTAPDLYENA 0x00000040U
-#define SD1_ITAPCHGWIN 0x02000000U
-#define SD1_ITAPDLYENA 0x01000000U
-#define SD1_OTAPDLYENA 0x00400000U
-#define SD_OTAPDLYSEL_HS200_B0 0x00000003U
-#define SD_OTAPDLYSEL_HS200_B2 0x00000002U
-#define SD_ITAPDLYSEL_SD50 0x00000014U
-#define SD_OTAPDLYSEL_SD50 0x00000003U
-#define SD_ITAPDLYSEL_SD_DDR50 0x0000003DU
-#define SD_ITAPDLYSEL_EMMC_DDR50 0x00000012U
-#define SD_OTAPDLYSEL_SD_DDR50 0x00000004U
-#define SD_OTAPDLYSEL_EMMC_DDR50 0x00000006U
-#define SD_ITAPDLYSEL_HSD 0x00000015U
-#define SD_OTAPDLYSEL_SD_HSD 0x00000005U
-#define SD_OTAPDLYSEL_EMMC_HSD 0x00000006U
-#endif
-/** @} */
-
-#ifdef __MICROBLAZE__
-#define XPS_SYS_CTRL_BASEADDR 0xFF180000U /**< System controller Baseaddress */
-#endif
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#define XSdPs_In64 Xil_In64 /**< Low level 64-bit data read */
-#define XSdPs_Out64 Xil_Out64 /**< Low level 64-bit data write */
-
-#define XSdPs_In32 Xil_In32 /**< Low level 32-bit data read */
-#define XSdPs_Out32 Xil_Out32 /**< Low level 32-bit data write */
-
-#define XSdPs_In16 Xil_In16 /**< Low level 16-bit data read */
-#define XSdPs_Out16 Xil_Out16 /**< Low level 16-bit data write */
-
-#define XSdPs_In8 Xil_In8 /**< Low level 8-bit data read */
-#define XSdPs_Out8 Xil_Out8 /**< Low level 8-bit data write */
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param InstancePtr is the pointer to the sdps instance.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
-*
-******************************************************************************/
-#define XSdPs_ReadReg64(InstancePtr, RegOffset) \
- XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset)
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param InstancePtr is the pointer to the sdps instance.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
-* u64 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
- XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
- (RegisterValue))
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-#define XSdPs_ReadReg(BaseAddress, RegOffset) \
- XSdPs_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u32 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg >>= ((RegOffset & 0x3)*8);
- return (u16)Reg;
-#else
- return XSdPs_In16((BaseAddress) + (RegOffset));
-#endif
-}
-
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u16 RegisterValue)
-*
-******************************************************************************/
-
-static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg &= ~(0xFFFFU<<((RegOffset & 0x3)*8));
- Reg |= RegisterValue <<((RegOffset & 0x3)*8);
- XSdPs_Out32(BaseAddress, Reg);
-#else
- XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue));
-#endif
-}
-
-/****************************************************************************/
-/**
-* Read a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to the target register.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
-*
-******************************************************************************/
-static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg >>= ((RegOffset & 0x3)*8);
- return (u8)Reg;
-#else
- return XSdPs_In8((BaseAddress) + (RegOffset));
-#endif
-}
-/***************************************************************************/
-/**
-* Write to a register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the 1st register of the
-* device to target register.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u8 RegisterValue)
-*
-******************************************************************************/
-static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue)
-{
-#if defined (__MICROBLAZE__)
- u32 Reg;
- BaseAddress += RegOffset & 0xFC;
- Reg = XSdPs_In32(BaseAddress);
- Reg &= ~(0xFFU<<((RegOffset & 0x3)*8));
- Reg |= RegisterValue <<((RegOffset & 0x3)*8);
- XSdPs_Out32(BaseAddress, Reg);
-#else
- XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue));
-#endif
-}
-/***************************************************************************/
-/**
-* Macro to get present status register
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u8 RegisterValue)
-*
-******************************************************************************/
-#define XSdPs_GetPresentStatusReg(BaseAddress) \
- XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SD_HW_H_ */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7f/d1839f555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7f/d1839f555243001d18b399c1eb9b3628
deleted file mode 100644
index 82dd34a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/7f/d1839f555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,24 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) sint32 unlink(char8 *path);
-}
-#endif
-/*
- * unlink -- since we have no file system,
- * we just return an error.
- */
-__attribute__((weak)) sint32 unlink(char8 *path)
-{
- (void) path;
- errno = EIO;
- return (-1);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8/319476545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8/319476545243001d18b399c1eb9b3628
deleted file mode 100644
index 9fb0e23..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8/319476545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,164 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xcoresightpsdcc.c
-* @addtogroup coresightps_dcc_v1_8
-* @{
-*
-* Functions in this file are the minimum required functions for the
-* XCoreSightPs driver.
-*
-* @note None.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------
-* 1.00 kvn 02/14/15 First release
-* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
-* kvn 08/18/15 Modified Makefile according to compiler changes.
-* 1.2 kvn 10/09/15 Add support for IAR Compiler.
-* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
-* for MB BSPs. Instead it throws up a warning. This
-* fixes the CR#953056.
-* 1.5 sne 01/19/19 Fixed MISRA-C Violations CR#1025101.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#ifdef __MICROBLAZE__
-#warning "The driver is supported only for ARM architecture"
-#else
-
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#include "xcoresightpsdcc.h"
-
-#ifdef __ICCARM__
-#define INLINE
-#else
-#define INLINE __inline
-#endif
-
-/* DCC Status Bits */
-#define XCORESIGHTPS_DCC_STATUS_RX (1 << 30)
-#define XCORESIGHTPS_DCC_STATUS_TX (1 << 29)
-
-static INLINE u32 XCoresightPs_DccGetStatus(void);
-
-/****************************************************************************/
-/**
-*
-* This functions sends a single byte using the DCC. It is blocking in that it
-* waits for the transmitter to become non-full before it writes the byte to
-* the transmit register.
-*
-* @param BaseAddress is a dummy parameter to match the function proto
-* of functions for other stdio devices.
-* @param Data is the byte of data to send
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data)
-{
- (void) BaseAddress;
- while (XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_TX)
- {dsb();}
-#ifdef __aarch64__
- asm volatile ("msr dbgdtrtx_el0, %0" : : "r" (Data));
-#elif defined (__GNUC__) || defined (__ICCARM__)
- asm volatile("mcr p14, 0, %0, c0, c5, 0"
- : : "r" (Data));
-#else
- {
- volatile register u32 Reg __asm("cp14:0:c0:c5:0");
- Reg = Data;
- }
-#endif
- isb();
-
-}
-
-/****************************************************************************/
-/**
-*
-* This functions receives a single byte using the DCC. It is blocking in that
-* it waits for the receiver to become non-empty before it reads from the
-* receive register.
-*
-* @param BaseAddress is a dummy parameter to match the function proto
-* of functions for other stdio devices.
-*
-* @return The byte of data received.
-*
-* @note None.
-*
-******************************************************************************/
-u8 XCoresightPs_DccRecvByte(u32 BaseAddress)
-{
- u8 Data = 0U;
- (void) BaseAddress;
-
- while (!(XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_RX))
- {dsb();}
-
-#ifdef __aarch64__
- asm volatile ("mrs %0, dbgdtrrx_el0" : "=r" (Data));
-#elif defined (__GNUC__) || defined (__ICCARM__)
- asm volatile("mrc p14, 0, %0, c0, c5, 0"
- : "=r" (Data));
-#else
- {
- volatile register u32 Reg __asm("cp14:0:c0:c5:0");
- Data = Reg;
- }
-#endif
- isb();
-
- return Data;
-}
-
-
-/****************************************************************************/
-/**INLINE
-*
-* This functions read the status register of the DCC.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return The contents of the Status Register.
-*
-* @note None.
-*
-******************************************************************************/
-static INLINE u32 XCoresightPs_DccGetStatus(void)
-{
- u32 Status = 0U;
-
-#ifdef __aarch64__
- asm volatile ("mrs %0, mdccsr_el0" : "=r" (Status));
-#elif defined (__GNUC__) || defined (__ICCARM__)
- asm volatile("mrc p14, 0, %0, c0, c1, 0"
- : "=r" (Status) : : "cc");
-#else
- {
- volatile register u32 Reg __asm("cp14:0:c0:c1:0");
- Status = Reg;
- }
-#endif
- return Status;
-}
-#endif
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8/900de6565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8/900de6565243001d18b399c1eb9b3628
deleted file mode 100644
index 60f4ba3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8/900de6565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,53 +0,0 @@
-/******************************************************************************
-* Copyright (c) 1995 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-*******************************************************************************/
- #ifndef XIL_PRINTF_H
- #define XIL_PRINTF_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include
-#include
-#include
-#include "xil_types.h"
-#include "xparameters.h"
-#include "bspconfig.h"
-#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
-#include "xen_console.h"
-#endif
-
-/*----------------------------------------------------*/
-/* Use the following parameter passing structure to */
-/* make xil_printf re-entrant. */
-/*----------------------------------------------------*/
-
-struct params_s;
-
-
-/*---------------------------------------------------*/
-/* The purpose of this routine is to output data the */
-/* same as the standard printf function without the */
-/* overhead most run-time libraries involve. Usually */
-/* the printf brings in many kilobytes of code and */
-/* that is unacceptable in most embedded systems. */
-/*---------------------------------------------------*/
-
-typedef char8* charptr;
-typedef s32 (*func_ptr)(int c);
-
-/* */
-
-void xil_printf( const char8 *ctrl1, ...);
-void xil_vprintf(const char8 *ctrl1, va_list argp);
-void print( const char8 *ptr);
-extern void outbyte (char8 c);
-extern char8 inbyte(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8/a1b59e545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8/a1b59e545243001d18b399c1eb9b3628
deleted file mode 100644
index bf2516a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8/a1b59e545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1076 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xemacps_bdring.c
-* @addtogroup emacps_v3_15
-* @{
-*
-* This file implements buffer descriptor ring related functions.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 First release
-* 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx is modified.
-* Earlier it used to search in "BdLimit" number of BDs to
-* know which BDs are processed. Now one more check is
-* added. It looks for BDs till the current BD pointer
-* reaches HwTail. By doing this processing time is saved.
-* 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
-* xemacps_bdring.c is modified. Now start of packet is
-* searched for returning the number of BDs processed.
-* 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
-* removed. It is expected that all BDs are allocated in
-* from uncached area. Fix for CR #663885.
-* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
-* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.6 rb 09/08/17 Add XEmacPs_BdRingPtrReset() API to reset BD ring
-* pointers
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xil_cache.h"
-#include "xemacps_hw.h"
-#include "xemacps_bd.h"
-#include "xemacps_bdring.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************
- * Compute the virtual address of a descriptor from its physical address
- *
- * @param BdPtr is the physical address of the BD
- *
- * @returns Virtual address of BdPtr
- *
- * @note Assume BdPtr is always a valid BD in the ring
- ****************************************************************************/
-#define XEMACPS_PHYS_TO_VIRT(BdPtr) \
- ((UINTPTR)(BdPtr) + (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr))
-
-/****************************************************************************
- * Compute the physical address of a descriptor from its virtual address
- *
- * @param BdPtr is the physical address of the BD
- *
- * @returns Physical address of BdPtr
- *
- * @note Assume BdPtr is always a valid BD in the ring
- ****************************************************************************/
-#define XEMACPS_VIRT_TO_PHYS(BdPtr) \
- ((UINTPTR)(BdPtr) - (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr))
-
-/****************************************************************************
- * Move the BdPtr argument ahead an arbitrary number of BDs wrapping around
- * to the beginning of the ring if needed.
- *
- * We know if a wrapaound should occur if the new BdPtr is greater than
- * the high address in the ring OR if the new BdPtr crosses over the
- * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not
- * allow a BD space to span this boundary.
- *
- * @param RingPtr is the ring BdPtr appears in
- * @param BdPtr on input is the starting BD position and on output is the
- * final BD position
- * @param NumBd is the number of BD spaces to increment
- *
- ****************************************************************************/
-#define XEMACPS_RING_SEEKAHEAD(RingPtr, BdPtr, NumBd) \
- { \
- UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \
- \
- Addr += ((RingPtr)->Separation * (NumBd)); \
- if ((Addr > (RingPtr)->HighBdAddr) || ((UINTPTR)(void *)(BdPtr) > Addr)) \
- { \
- Addr -= (RingPtr)->Length; \
- } \
- \
- (BdPtr) = (XEmacPs_Bd*)(void *)Addr; \
- }
-
-/****************************************************************************
- * Move the BdPtr argument backwards an arbitrary number of BDs wrapping
- * around to the end of the ring if needed.
- *
- * We know if a wrapaound should occur if the new BdPtr is less than
- * the base address in the ring OR if the new BdPtr crosses over the
- * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not
- * allow a BD space to span this boundary.
- *
- * @param RingPtr is the ring BdPtr appears in
- * @param BdPtr on input is the starting BD position and on output is the
- * final BD position
- * @param NumBd is the number of BD spaces to increment
- *
- ****************************************************************************/
-#define XEMACPS_RING_SEEKBACK(RingPtr, BdPtr, NumBd) \
- { \
- UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \
- \
- Addr -= ((RingPtr)->Separation * (NumBd)); \
- if ((Addr < (RingPtr)->BaseBdAddr) || ((UINTPTR)(void*)(BdPtr) < Addr)) \
- { \
- Addr += (RingPtr)->Length; \
- } \
- \
- (BdPtr) = (XEmacPs_Bd*)(void*)Addr; \
- }
-
-
-/************************** Function Prototypes ******************************/
-
-static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr);
-static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr);
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
- * Using a memory segment allocated by the caller, create and setup the BD list
- * for the given DMA channel.
- *
- * @param RingPtr is the instance to be worked on.
- * @param PhysAddr is the physical base address of user memory region.
- * @param VirtAddr is the virtual base address of the user memory region. If
- * address translation is not being utilized, then VirtAddr should be
- * equivalent to PhysAddr.
- * @param Alignment governs the byte alignment of individual BDs. This function
- * will enforce a minimum alignment of 4 bytes with no maximum as long
- * as it is specified as a power of 2.
- * @param BdCount is the number of BDs to setup in the user memory region. It
- * is assumed the region is large enough to contain the BDs.
- *
- * @return
- *
- * - XST_SUCCESS if initialization was successful
- * - XST_NO_FEATURE if the provided instance is a non DMA type
- * channel.
- * - XST_INVALID_PARAM under any of the following conditions:
- * 1) PhysAddr and/or VirtAddr are not aligned to the given Alignment
- * parameter.
- * 2) Alignment parameter does not meet minimum requirements or is not a
- * power of 2 value.
- * 3) BdCount is 0.
- * - XST_DMA_SG_LIST_ERROR if the memory segment containing the list spans
- * over address 0x00000000 in virtual address space.
- *
- * @note
- * Make sure to pass in the right alignment value.
- *****************************************************************************/
-LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
- UINTPTR VirtAddr, u32 Alignment, u32 BdCount)
-{
- u32 i;
- UINTPTR BdVirtAddr;
- UINTPTR BdPhyAddr;
- UINTPTR VirtAddrLoc = VirtAddr;
-
- /* In case there is a failure prior to creating list, make sure the
- * following attributes are 0 to prevent calls to other functions
- * from doing anything.
- */
- RingPtr->AllCnt = 0U;
- RingPtr->FreeCnt = 0U;
- RingPtr->HwCnt = 0U;
- RingPtr->PreCnt = 0U;
- RingPtr->PostCnt = 0U;
-
- /* Make sure Alignment parameter meets minimum requirements */
- if (Alignment < (u32)XEMACPS_DMABD_MINIMUM_ALIGNMENT) {
- return (LONG)(XST_INVALID_PARAM);
- }
-
- /* Make sure Alignment is a power of 2 */
- if (((Alignment - 0x00000001U) & Alignment)!=0x00000000U) {
- return (LONG)(XST_INVALID_PARAM);
- }
-
- /* Make sure PhysAddr and VirtAddr are on same Alignment */
- if (((PhysAddr % Alignment)!=(u32)0) || ((VirtAddrLoc % Alignment)!=(u32)0)) {
- return (LONG)(XST_INVALID_PARAM);
- }
-
- /* Is BdCount reasonable? */
- if (BdCount == 0x00000000U) {
- return (LONG)(XST_INVALID_PARAM);
- }
-
- /* Figure out how many bytes will be between the start of adjacent BDs */
- RingPtr->Separation = ((u32)sizeof(XEmacPs_Bd));
-
- /* Must make sure the ring doesn't span address 0x00000000. If it does,
- * then the next/prev BD traversal macros will fail.
- */
- if (VirtAddrLoc > ((VirtAddrLoc + (RingPtr->Separation * BdCount)) - (u32)1)) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- /* Initial ring setup:
- * - Clear the entire space
- * - Setup each BD's BDA field with the physical address of the next BD
- */
- (void)memset((void *) VirtAddrLoc, 0, (RingPtr->Separation * BdCount));
-
- BdVirtAddr = VirtAddrLoc;
- BdPhyAddr = PhysAddr + RingPtr->Separation;
- for (i = 1U; i < BdCount; i++) {
- BdVirtAddr += RingPtr->Separation;
- BdPhyAddr += RingPtr->Separation;
- }
-
- /* Setup and initialize pointers and counters */
- RingPtr->RunState = (u32)(XST_DMA_SG_IS_STOPPED);
- RingPtr->BaseBdAddr = VirtAddrLoc;
- RingPtr->PhysBaseAddr = PhysAddr;
- RingPtr->HighBdAddr = BdVirtAddr;
- RingPtr->Length =
- ((RingPtr->HighBdAddr - RingPtr->BaseBdAddr) + RingPtr->Separation);
- RingPtr->AllCnt = (u32)BdCount;
- RingPtr->FreeCnt = (u32)BdCount;
- RingPtr->FreeHead = (XEmacPs_Bd *)(void *)VirtAddrLoc;
- RingPtr->PreHead = (XEmacPs_Bd *)VirtAddrLoc;
- RingPtr->HwHead = (XEmacPs_Bd *)VirtAddrLoc;
- RingPtr->HwTail = (XEmacPs_Bd *)VirtAddrLoc;
- RingPtr->PostHead = (XEmacPs_Bd *)VirtAddrLoc;
- RingPtr->BdaRestart = (XEmacPs_Bd *)(void *)PhysAddr;
-
- return (LONG)(XST_SUCCESS);
-}
-
-
-/*****************************************************************************/
-/**
- * Clone the given BD into every BD in the list.
- * every field of the source BD is replicated in every BD of the list.
- *
- * This function can be called only when all BDs are in the free group such as
- * they are immediately after initialization with XEmacPs_BdRingCreate().
- * This prevents modification of BDs while they are in use by hardware or the
- * user.
- *
- * @param RingPtr is the pointer of BD ring instance to be worked on.
- * @param SrcBdPtr is the source BD template to be cloned into the list. This
- * BD will be modified.
- * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
- * which direction.
- *
- * @return
- * - XST_SUCCESS if the list was modified.
- * - XST_DMA_SG_NO_LIST if a list has not been created.
- * - XST_DMA_SG_LIST_ERROR if some of the BDs in this channel are under
- * hardware or user control.
- * - XST_DEVICE_IS_STARTED if the DMA channel has not been stopped.
- *
- *****************************************************************************/
-LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
- u8 Direction)
-{
- u32 i;
- UINTPTR CurBd;
-
- /* Can't do this function if there isn't a ring */
- if (RingPtr->AllCnt == 0x00000000U) {
- return (LONG)(XST_DMA_SG_NO_LIST);
- }
-
- /* Can't do this function with the channel running */
- if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
- return (LONG)(XST_DEVICE_IS_STARTED);
- }
-
- /* Can't do this function with some of the BDs in use */
- if (RingPtr->FreeCnt != RingPtr->AllCnt) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
- return (LONG)(XST_INVALID_PARAM);
- }
-
- /* Starting from the top of the ring, save BD.Next, overwrite the entire
- * BD with the template, then restore BD.Next
- */
- CurBd = RingPtr->BaseBdAddr;
- for (i = 0U; i < RingPtr->AllCnt; i++) {
- memcpy((void *)CurBd, SrcBdPtr, sizeof(XEmacPs_Bd));
- CurBd += RingPtr->Separation;
- }
-
- CurBd -= RingPtr->Separation;
-
- if (Direction == XEMACPS_RECV) {
- XEmacPs_BdSetRxWrap(CurBd);
- }
- else {
- XEmacPs_BdSetTxWrap(CurBd);
- }
-
- return (LONG)(XST_SUCCESS);
-}
-
-
-/*****************************************************************************/
-/**
- * Reserve locations in the BD list. The set of returned BDs may be modified
- * in preparation for future DMA transaction(s). Once the BDs are ready to be
- * submitted to hardware, the user must call XEmacPs_BdRingToHw() in the same
- * order which they were allocated here. Example:
- *
- *
- * NumBd = 2,
- * Status = XEmacPs_BdRingAlloc(MyRingPtr, NumBd, &MyBdSet),
- *
- * if (Status != XST_SUCCESS)
- * {
- * *Not enough BDs available for the request*
- * }
- *
- * CurBd = MyBdSet,
- * for (i=0; i
- *
- * A more advanced use of this function may allocate multiple sets of BDs.
- * They must be allocated and given to hardware in the correct sequence:
- *
- *
- * Use the API defined in xemacps_bd.h to modify individual BDs. Traversal
- * of the BD set can be done using XEmacPs_BdRingNext() and
- * XEmacPs_BdRingPrev().
- *
- * @param RingPtr is a pointer to the BD ring instance to be worked on.
- * @param NumBd is the number of BDs to allocate
- * @param BdSetPtr is an output parameter, it points to the first BD available
- * for modification.
- *
- * @return
- * - XST_SUCCESS if the requested number of BDs was returned in the BdSetPtr
- * parameter.
- * - XST_FAILURE if there were not enough free BDs to satisfy the request.
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- * call that modifies the BD space. It is the caller's responsibility to
- * provide a mutual exclusion mechanism.
- *
- * @note Do not modify more BDs than the number requested with the NumBd
- * parameter. Doing so will lead to data corruption and system
- * instability.
- *
- *****************************************************************************/
-LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd ** BdSetPtr)
-{
- LONG Status;
- /* Enough free BDs available for the request? */
- if (RingPtr->FreeCnt < NumBd) {
- Status = (LONG)(XST_FAILURE);
- } else {
- /* Set the return argument and move FreeHead forward */
- *BdSetPtr = RingPtr->FreeHead;
- XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->FreeHead, NumBd);
- RingPtr->FreeCnt -= NumBd;
- RingPtr->PreCnt += NumBd;
- Status = (LONG)(XST_SUCCESS);
- }
- return Status;
-}
-
-/*****************************************************************************/
-/**
- * Fully or partially undo an XEmacPs_BdRingAlloc() operation. Use this
- * function if all the BDs allocated by XEmacPs_BdRingAlloc() could not be
- * transferred to hardware with XEmacPs_BdRingToHw().
- *
- * This function helps out in situations when an unrelated error occurs after
- * BDs have been allocated but before they have been given to hardware.
- * An example of this type of error would be an OS running out of resources.
- *
- * This function is not the same as XEmacPs_BdRingFree(). The Free function
- * returns BDs to the free list after they have been processed by hardware,
- * while UnAlloc returns them before being processed by hardware.
- *
- * There are two scenarios where this function can be used. Full UnAlloc or
- * Partial UnAlloc. A Full UnAlloc means all the BDs Alloc'd will be returned:
- *
- *
- * Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
- * ...
- * if (Error)
- * {
- * Status = XEmacPs_BdRingUnAlloc(MyRingPtr, 10, &BdPtr),
- * }
- *
- *
- * A partial UnAlloc means some of the BDs Alloc'd will be returned:
- *
- *
- *
- * A partial UnAlloc must include the last BD in the list that was Alloc'd.
- *
- * @param RingPtr is a pointer to the instance to be worked on.
- * @param NumBd is the number of BDs to allocate
- * @param BdSetPtr is an output parameter, it points to the first BD available
- * for modification.
- *
- * @return
- * - XST_SUCCESS if the BDs were unallocated.
- * - XST_FAILURE if NumBd parameter was greater that the number of BDs in
- * the preprocessing state.
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- * call that modifies the BD space. It is the caller's responsibility to
- * provide a mutual exclusion mechanism.
- *
- *****************************************************************************/
-LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr)
-{
- LONG Status;
- (void) BdSetPtr;
- Xil_AssertNonvoid(RingPtr != NULL);
- Xil_AssertNonvoid(BdSetPtr != NULL);
-
- /* Enough BDs in the free state for the request? */
- if (RingPtr->PreCnt < NumBd) {
- Status = (LONG)(XST_FAILURE);
- } else {
- /* Set the return argument and move FreeHead backward */
- XEMACPS_RING_SEEKBACK(RingPtr, (RingPtr->FreeHead), NumBd);
- RingPtr->FreeCnt += NumBd;
- RingPtr->PreCnt -= NumBd;
- Status = (LONG)(XST_SUCCESS);
- }
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Enqueue a set of BDs to hardware that were previously allocated by
- * XEmacPs_BdRingAlloc(). Once this function returns, the argument BD set goes
- * under hardware control. Any changes made to these BDs after this point will
- * corrupt the BD list leading to data corruption and system instability.
- *
- * The set will be rejected if the last BD of the set does not mark the end of
- * a packet (see XEmacPs_BdSetLast()).
- *
- * @param RingPtr is a pointer to the instance to be worked on.
- * @param NumBd is the number of BDs in the set.
- * @param BdSetPtr is the first BD of the set to commit to hardware.
- *
- * @return
- * - XST_SUCCESS if the set of BDs was accepted and enqueued to hardware.
- * - XST_FAILURE if the set of BDs was rejected because the last BD of the set
- * did not have its "last" bit set.
- * - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
- * XEmacPs_BdRingAlloc().
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- * call that modifies the BD space. It is the caller's responsibility to
- * provide a mutual exclusion mechanism.
- *
- *****************************************************************************/
-LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr)
-{
- XEmacPs_Bd *CurBdPtr;
- u32 i;
- LONG Status;
- /* if no bds to process, simply return. */
- if (0U == NumBd){
- Status = (LONG)(XST_SUCCESS);
- } else {
- /* Make sure we are in sync with XEmacPs_BdRingAlloc() */
- if ((RingPtr->PreCnt < NumBd) || (RingPtr->PreHead != BdSetPtr)) {
- Status = (LONG)(XST_DMA_SG_LIST_ERROR);
- } else {
- CurBdPtr = BdSetPtr;
- for (i = 0U; i < NumBd; i++) {
- CurBdPtr = (XEmacPs_Bd *)((void *)XEmacPs_BdRingNext(RingPtr, CurBdPtr));
- }
- /* Adjust ring pointers & counters */
- XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PreHead, NumBd);
- RingPtr->PreCnt -= NumBd;
- RingPtr->HwTail = CurBdPtr;
- RingPtr->HwCnt += NumBd;
-
- Status = (LONG)(XST_SUCCESS);
- }
- }
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Returns a set of BD(s) that have been processed by hardware. The returned
- * BDs may be examined to determine the outcome of the DMA transaction(s).
- * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
- * in the same order which they were retrieved here. Example:
- *
- *
- * NumBd = XEmacPs_BdRingFromHwTx(MyRingPtr, MaxBd, &MyBdSet),
- * if (NumBd == 0)
- * {
- * * hardware has nothing ready for us yet*
- * }
- *
- * CurBd = MyBdSet,
- * for (i=0; i
- *
- * A more advanced use of this function may allocate multiple sets of BDs.
- * They must be retrieved from hardware and freed in the correct sequence:
- *
- *
- * If hardware has only partially completed a packet spanning multiple BDs,
- * then none of the BDs for that packet will be included in the results.
- *
- * @param RingPtr is a pointer to the instance to be worked on.
- * @param BdLimit is the maximum number of BDs to return in the set.
- * @param BdSetPtr is an output parameter, it points to the first BD available
- * for examination.
- *
- * @return
- * The number of BDs processed by hardware. A value of 0 indicates that no
- * data is available. No more than BdLimit BDs will be returned.
- *
- * @note Treat BDs returned by this function as read-only.
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- * call that modifies the BD space. It is the caller's responsibility to
- * provide a mutual exclusion mechanism.
- *
- *****************************************************************************/
-u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
- XEmacPs_Bd ** BdSetPtr)
-{
- XEmacPs_Bd *CurBdPtr;
- u32 BdStr = 0U;
- u32 BdCount;
- u32 BdPartialCount;
- u32 Sop = 0U;
- u32 Status;
- u32 BdLimitLoc = BdLimit;
- CurBdPtr = RingPtr->HwHead;
- BdCount = 0U;
- BdPartialCount = 0U;
-
- /* If no BDs in work group, then there's nothing to search */
- if (RingPtr->HwCnt == 0x00000000U) {
- *BdSetPtr = NULL;
- Status = 0U;
- } else {
-
- if (BdLimitLoc > RingPtr->HwCnt){
- BdLimitLoc = RingPtr->HwCnt;
- }
- /* Starting at HwHead, keep moving forward in the list until:
- * - A BD is encountered with its new/used bit set which means
- * hardware has not completed processing of that BD.
- * - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
- * - The number of requested BDs has been processed
- */
- while (BdCount < BdLimitLoc) {
- /* Read the status */
- if(CurBdPtr != NULL){
- BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
- }
-
- if ((Sop == 0x00000000U) && ((BdStr & XEMACPS_TXBUF_USED_MASK)!=0x00000000U)){
- Sop = 1U;
- }
- if (Sop == 0x00000001U) {
- BdCount++;
- BdPartialCount++;
- }
-
- /* hardware has processed this BD so check the "last" bit.
- * If it is clear, then there are more BDs for the current
- * packet. Keep a count of these partial packet BDs.
- */
- if ((Sop == 0x00000001U) && ((BdStr & XEMACPS_TXBUF_LAST_MASK)!=0x00000000U)) {
- Sop = 0U;
- BdPartialCount = 0U;
- }
-
- /* Move on to next BD in work group */
- CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
- }
-
- /* Subtract off any partial packet BDs found */
- BdCount -= BdPartialCount;
-
- /* If BdCount is non-zero then BDs were found to return. Set return
- * parameters, update pointers and counters, return success
- */
- if (BdCount > 0x00000000U) {
- *BdSetPtr = RingPtr->HwHead;
- RingPtr->HwCnt -= BdCount;
- RingPtr->PostCnt += BdCount;
- XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
- Status = (BdCount);
- } else {
- *BdSetPtr = NULL;
- Status = 0U;
- }
- }
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Returns a set of BD(s) that have been processed by hardware. The returned
- * BDs may be examined to determine the outcome of the DMA transaction(s).
- * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
- * in the same order which they were retrieved here. Example:
- *
- *
- * NumBd = XEmacPs_BdRingFromHwRx(MyRingPtr, MaxBd, &MyBdSet),
- *
- * if (NumBd == 0)
- * {
- * *hardware has nothing ready for us yet*
- * }
- *
- * CurBd = MyBdSet,
- * for (i=0; i
- *
- * A more advanced use of this function may allocate multiple sets of BDs.
- * They must be retrieved from hardware and freed in the correct sequence:
- *
- *
- * If hardware has only partially completed a packet spanning multiple BDs,
- * then none of the BDs for that packet will be included in the results.
- *
- * @param RingPtr is a pointer to the instance to be worked on.
- * @param BdLimit is the maximum number of BDs to return in the set.
- * @param BdSetPtr is an output parameter, it points to the first BD available
- * for examination.
- *
- * @return
- * The number of BDs processed by hardware. A value of 0 indicates that no
- * data is available. No more than BdLimit BDs will be returned.
- *
- * @note Treat BDs returned by this function as read-only.
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- * call that modifies the BD space. It is the caller's responsibility to
- * provide a mutual exclusion mechanism.
- *
- *****************************************************************************/
-u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
- XEmacPs_Bd ** BdSetPtr)
-{
- XEmacPs_Bd *CurBdPtr;
- u32 BdStr = 0U;
- u32 BdCount;
- u32 BdPartialCount;
- u32 Status;
-
- CurBdPtr = RingPtr->HwHead;
- BdCount = 0U;
- BdPartialCount = 0U;
-
- /* If no BDs in work group, then there's nothing to search */
- if (RingPtr->HwCnt == 0x00000000U) {
- *BdSetPtr = NULL;
- Status = 0U;
- } else {
-
- /* Starting at HwHead, keep moving forward in the list until:
- * - A BD is encountered with its new/used bit set which means
- * hardware has completed processing of that BD.
- * - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
- * - The number of requested BDs has been processed
- */
- while (BdCount < BdLimit) {
-
- /* Read the status */
- if(CurBdPtr!=NULL){
- BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
- }
- if ((!(XEmacPs_BdIsRxNew(CurBdPtr)))==TRUE) {
- break;
- }
-
- BdCount++;
-
- /* hardware has processed this BD so check the "last" bit. If
- * it is clear, then there are more BDs for the current packet.
- * Keep a count of these partial packet BDs.
- */
- if ((BdStr & XEMACPS_RXBUF_EOF_MASK)!=0x00000000U) {
- BdPartialCount = 0U;
- } else {
- BdPartialCount++;
- }
-
- /* Move on to next BD in work group */
- CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
- }
-
- /* Subtract off any partial packet BDs found */
- BdCount -= BdPartialCount;
-
- /* If BdCount is non-zero then BDs were found to return. Set return
- * parameters, update pointers and counters, return success
- */
- if (BdCount > 0x00000000U) {
- *BdSetPtr = RingPtr->HwHead;
- RingPtr->HwCnt -= BdCount;
- RingPtr->PostCnt += BdCount;
- XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
- Status = (BdCount);
- }
- else {
- *BdSetPtr = NULL;
- Status = 0U;
- }
-}
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Frees a set of BDs that had been previously retrieved with
- * XEmacPs_BdRingFromHw().
- *
- * @param RingPtr is a pointer to the instance to be worked on.
- * @param NumBd is the number of BDs to free.
- * @param BdSetPtr is the head of a list of BDs returned by
- * XEmacPs_BdRingFromHw().
- *
- * @return
- * - XST_SUCCESS if the set of BDs was freed.
- * - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
- * XEmacPs_BdRingFromHw().
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- * call that modifies the BD space. It is the caller's responsibility to
- * provide a mutual exclusion mechanism.
- *
- *****************************************************************************/
-LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr)
-{
- LONG Status;
- /* if no bds to process, simply return. */
- if (0x00000000U == NumBd){
- Status = (LONG)(XST_SUCCESS);
- } else {
- /* Make sure we are in sync with XEmacPs_BdRingFromHw() */
- if ((RingPtr->PostCnt < NumBd) || (RingPtr->PostHead != BdSetPtr)) {
- Status = (LONG)(XST_DMA_SG_LIST_ERROR);
- } else {
- /* Update pointers and counters */
- RingPtr->FreeCnt += NumBd;
- RingPtr->PostCnt -= NumBd;
- XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PostHead, NumBd);
- Status = (LONG)(XST_SUCCESS);
- }
- }
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Check the internal data structures of the BD ring for the provided channel.
- * The following checks are made:
- *
- * - Is the BD ring linked correctly in physical address space.
- * - Do the internal pointers point to BDs in the ring.
- * - Do the internal counters add up.
- *
- * The channel should be stopped prior to calling this function.
- *
- * @param RingPtr is a pointer to the instance to be worked on.
- * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
- * which direction.
- *
- * @return
- * - XST_SUCCESS if the set of BDs was freed.
- * - XST_DMA_SG_NO_LIST if the list has not been created.
- * - XST_IS_STARTED if the channel is not stopped.
- * - XST_DMA_SG_LIST_ERROR if a problem is found with the internal data
- * structures. If this value is returned, the channel should be reset to
- * avoid data corruption or system instability.
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- * call that modifies the BD space. It is the caller's responsibility to
- * provide a mutual exclusion mechanism.
- *
- *****************************************************************************/
-LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction)
-{
- UINTPTR AddrV, AddrP;
- u32 i;
-
- if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
- return (LONG)(XST_INVALID_PARAM);
- }
-
- /* Is the list created */
- if (RingPtr->AllCnt == 0x00000000U) {
- return (LONG)(XST_DMA_SG_NO_LIST);
- }
-
- /* Can't check if channel is running */
- if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
- return (LONG)(XST_IS_STARTED);
- }
-
- /* RunState doesn't make sense */
- if (RingPtr->RunState != (u32)XST_DMA_SG_IS_STOPPED) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- /* Verify internal pointers point to correct memory space */
- AddrV = (UINTPTR) RingPtr->FreeHead;
- if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- AddrV = (UINTPTR) RingPtr->PreHead;
- if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- AddrV = (UINTPTR) RingPtr->HwHead;
- if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- AddrV = (UINTPTR) RingPtr->HwTail;
- if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- AddrV = (UINTPTR) RingPtr->PostHead;
- if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- /* Verify internal counters add up */
- if ((RingPtr->HwCnt + RingPtr->PreCnt + RingPtr->FreeCnt +
- RingPtr->PostCnt) != RingPtr->AllCnt) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- /* Verify BDs are linked correctly */
- AddrV = RingPtr->BaseBdAddr;
- AddrP = RingPtr->PhysBaseAddr + RingPtr->Separation;
-
- for (i = 1U; i < RingPtr->AllCnt; i++) {
- /* Check BDA for this BD. It should point to next physical addr */
- if (XEmacPs_BdRead(AddrV, XEMACPS_BD_ADDR_OFFSET) != AddrP) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- /* Move on to next BD */
- AddrV += RingPtr->Separation;
- AddrP += RingPtr->Separation;
- }
-
- /* Last BD should have wrap bit set */
- if (XEMACPS_SEND == Direction) {
- if ((!XEmacPs_BdIsTxWrap(AddrV))==TRUE) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
- }
- else { /* XEMACPS_RECV */
- if ((!XEmacPs_BdIsRxWrap(AddrV))==TRUE) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
- }
-
- /* No problems found */
- return (LONG)(XST_SUCCESS);
-}
-
-/*****************************************************************************/
-/**
- * Set this bit to mark the last descriptor in the receive buffer descriptor
- * list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr)
-{
- u32 DataValueRx;
- u32 *TempPtr;
-
- BdPtr += (u32)(XEMACPS_BD_ADDR_OFFSET);
- TempPtr = (u32 *)BdPtr;
- if(TempPtr != NULL) {
- DataValueRx = *TempPtr;
- DataValueRx |= XEMACPS_RXBUF_WRAP_MASK;
- *TempPtr = DataValueRx;
- }
-}
-
-/*****************************************************************************/
-/**
- * Sets this bit to mark the last descriptor in the transmit buffer
- * descriptor list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr)
-{
- u32 DataValueTx;
- u32 *TempPtr;
-
- BdPtr += (u32)(XEMACPS_BD_STAT_OFFSET);
- TempPtr = (u32 *)BdPtr;
- if(TempPtr != NULL) {
- DataValueTx = *TempPtr;
- DataValueTx |= XEMACPS_TXBUF_WRAP_MASK;
- *TempPtr = DataValueTx;
- }
-}
-
-/*****************************************************************************/
-/**
- * Reset BD ring head and tail pointers.
- *
- * @param RingPtr is the instance to be worked on.
- * @param virtaddrloc is the virtual base address of the user memory region.
- *
- * @note
- * Should be called after XEmacPs_Stop()
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc)
- *
- *****************************************************************************/
-void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc)
-{
- RingPtr->FreeHead = virtaddrloc;
- RingPtr->PreHead = virtaddrloc;
- RingPtr->HwHead = virtaddrloc;
- RingPtr->HwTail = virtaddrloc;
- RingPtr->PostHead = virtaddrloc;
-}
-
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8/b25f8c575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8/b25f8c575243001d18b399c1eb9b3628
deleted file mode 100644
index a283595..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8/b25f8c575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,655 +0,0 @@
-#ifndef XPARAMETERS_H /* prevent circular inclusions */
-#define XPARAMETERS_H /* by using protection macros */
-
-/* Definition for CPU ID */
-#define XPAR_CPU_ID 0U
-
-/* Definitions for peripheral PS7_CORTEXA9_0 */
-#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_CORTEXA9_0 */
-#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
-
-
-/******************************************************************/
-
-#include "xparameters_ps.h"
-
-#define STDIN_BASEADDRESS 0xE0001000
-#define STDOUT_BASEADDRESS 0xE0001000
-
-/******************************************************************/
-
-/* Platform specific definitions */
-#define PLATFORM_ZYNQ
-
-/* Definitions for sleep timer configuration */
-#define XSLEEP_TIMER_IS_DEFAULT_TIMER
-
-
-/******************************************************************/
-
-/* Definitions for peripheral PS7_DDR_0 */
-#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
-#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
-
-
-/******************************************************************/
-
-/* Definitions for driver DEVCFG */
-#define XPAR_XDCFG_NUM_INSTANCES 1U
-
-/* Definitions for peripheral PS7_DEV_CFG_0 */
-#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0U
-#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000U
-#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FFU
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_DEV_CFG_0 */
-#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
-#define XPAR_XDCFG_0_BASEADDR 0xF8007000U
-#define XPAR_XDCFG_0_HIGHADDR 0xF80070FFU
-
-
-/******************************************************************/
-
-/* Definitions for driver DMAPS */
-#define XPAR_XDMAPS_NUM_INSTANCES 2
-
-/* Definitions for peripheral PS7_DMA_NS */
-#define XPAR_PS7_DMA_NS_DEVICE_ID 0
-#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
-#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
-
-
-/* Definitions for peripheral PS7_DMA_S */
-#define XPAR_PS7_DMA_S_DEVICE_ID 1
-#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
-#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_DMA_NS */
-#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
-#define XPAR_XDMAPS_0_BASEADDR 0xF8004000
-#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
-
-/* Canonical definitions for peripheral PS7_DMA_S */
-#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
-#define XPAR_XDMAPS_1_BASEADDR 0xF8003000
-#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
-
-
-/******************************************************************/
-
-/* Definitions for driver EMACPS */
-#define XPAR_XEMACPS_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_ETHERNET_0 */
-#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0
-#define XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000
-#define XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF
-#define XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 125000000
-#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8
-#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1
-#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8
-#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5
-#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8
-#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50
-#define XPAR_PS7_ETHERNET_0_ENET_TSU_CLK_FREQ_HZ 0
-
-
-/******************************************************************/
-
-#define XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT 0
-#define XPAR_XEMACPS_0_IS_CACHE_COHERENT 0
-/* Canonical definitions for peripheral PS7_ETHERNET_0 */
-#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID
-#define XPAR_XEMACPS_0_BASEADDR 0xE000B000
-#define XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF
-#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 125000000
-#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8
-#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
-#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 8
-#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5
-#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8
-#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50
-#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 0
-
-
-/******************************************************************/
-
-
-/* Peripheral Definitions for peripheral PS7_AFI_0 */
-#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
-#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
-
-
-/* Peripheral Definitions for peripheral PS7_AFI_1 */
-#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
-#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
-
-
-/* Peripheral Definitions for peripheral PS7_AFI_2 */
-#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
-#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
-
-
-/* Peripheral Definitions for peripheral PS7_AFI_3 */
-#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
-#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
-
-
-/* Peripheral Definitions for peripheral PS7_DDRC_0 */
-#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
-#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
-
-
-/* Peripheral Definitions for peripheral PS7_GLOBALTIMER_0 */
-#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
-#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
-
-
-/* Peripheral Definitions for peripheral PS7_GPV_0 */
-#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
-#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
-
-
-/* Peripheral Definitions for peripheral PS7_INTC_DIST_0 */
-#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
-#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
-
-
-/* Peripheral Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
-#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
-#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
-
-
-/* Peripheral Definitions for peripheral PS7_L2CACHEC_0 */
-#define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000
-#define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF
-
-
-/* Peripheral Definitions for peripheral PS7_OCMC_0 */
-#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
-#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
-
-
-/* Peripheral Definitions for peripheral PS7_PL310_0 */
-#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
-#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
-
-
-/* Peripheral Definitions for peripheral PS7_PMU_0 */
-#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
-#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
-#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
-#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
-
-
-/* Peripheral Definitions for peripheral PS7_QSPI_LINEAR_0 */
-#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
-#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF
-
-
-/* Peripheral Definitions for peripheral PS7_RAM_0 */
-#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
-#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
-
-
-/* Peripheral Definitions for peripheral PS7_RAM_1 */
-#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
-#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
-
-
-/* Peripheral Definitions for peripheral PS7_SCUC_0 */
-#define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000
-#define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC
-
-
-/* Peripheral Definitions for peripheral PS7_SLCR_0 */
-#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
-#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
-
-
-/******************************************************************/
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-/******************************************************************/
-
-/* Definitions for driver GPIO */
-#define XPAR_XGPIO_NUM_INSTANCES 12
-
-/* Definitions for peripheral AXI_GPIO_0 */
-#define XPAR_AXI_GPIO_0_BASEADDR 0x41250000
-#define XPAR_AXI_GPIO_0_HIGHADDR 0x4125FFFF
-#define XPAR_AXI_GPIO_0_DEVICE_ID 0
-#define XPAR_AXI_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_AXI_GPIO_0_IS_DUAL 1
-
-
-/* Definitions for peripheral AXI_GPIO_1 */
-#define XPAR_AXI_GPIO_1_BASEADDR 0x41260000
-#define XPAR_AXI_GPIO_1_HIGHADDR 0x4126FFFF
-#define XPAR_AXI_GPIO_1_DEVICE_ID 1
-#define XPAR_AXI_GPIO_1_INTERRUPT_PRESENT 0
-#define XPAR_AXI_GPIO_1_IS_DUAL 1
-
-
-/* Definitions for peripheral HIER_0_AXI_GPIO_0 */
-#define XPAR_HIER_0_AXI_GPIO_0_BASEADDR 0x41200000
-#define XPAR_HIER_0_AXI_GPIO_0_HIGHADDR 0x4120FFFF
-#define XPAR_HIER_0_AXI_GPIO_0_DEVICE_ID 2
-#define XPAR_HIER_0_AXI_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_HIER_0_AXI_GPIO_0_IS_DUAL 1
-
-
-/* Definitions for peripheral HIER_1_AXI_GPIO_0 */
-#define XPAR_HIER_1_AXI_GPIO_0_BASEADDR 0x41210000
-#define XPAR_HIER_1_AXI_GPIO_0_HIGHADDR 0x4121FFFF
-#define XPAR_HIER_1_AXI_GPIO_0_DEVICE_ID 3
-#define XPAR_HIER_1_AXI_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_HIER_1_AXI_GPIO_0_IS_DUAL 1
-
-
-/* Definitions for peripheral HIER_2_AXI_GPIO_0 */
-#define XPAR_HIER_2_AXI_GPIO_0_BASEADDR 0x41220000
-#define XPAR_HIER_2_AXI_GPIO_0_HIGHADDR 0x4122FFFF
-#define XPAR_HIER_2_AXI_GPIO_0_DEVICE_ID 4
-#define XPAR_HIER_2_AXI_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_HIER_2_AXI_GPIO_0_IS_DUAL 1
-
-
-/* Definitions for peripheral HIER_3_AXI_GPIO_0 */
-#define XPAR_HIER_3_AXI_GPIO_0_BASEADDR 0x41230000
-#define XPAR_HIER_3_AXI_GPIO_0_HIGHADDR 0x4123FFFF
-#define XPAR_HIER_3_AXI_GPIO_0_DEVICE_ID 5
-#define XPAR_HIER_3_AXI_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_HIER_3_AXI_GPIO_0_IS_DUAL 1
-
-
-/* Definitions for peripheral HIER_4_AXI_GPIO_0 */
-#define XPAR_HIER_4_AXI_GPIO_0_BASEADDR 0x41240000
-#define XPAR_HIER_4_AXI_GPIO_0_HIGHADDR 0x4124FFFF
-#define XPAR_HIER_4_AXI_GPIO_0_DEVICE_ID 6
-#define XPAR_HIER_4_AXI_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_HIER_4_AXI_GPIO_0_IS_DUAL 1
-
-
-/* Definitions for peripheral HIER_5_AXI_GPIO_0 */
-#define XPAR_HIER_5_AXI_GPIO_0_BASEADDR 0x41270000
-#define XPAR_HIER_5_AXI_GPIO_0_HIGHADDR 0x4127FFFF
-#define XPAR_HIER_5_AXI_GPIO_0_DEVICE_ID 7
-#define XPAR_HIER_5_AXI_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_HIER_5_AXI_GPIO_0_IS_DUAL 1
-
-
-/* Definitions for peripheral HIER_6_AXI_GPIO_0 */
-#define XPAR_HIER_6_AXI_GPIO_0_BASEADDR 0x41280000
-#define XPAR_HIER_6_AXI_GPIO_0_HIGHADDR 0x4128FFFF
-#define XPAR_HIER_6_AXI_GPIO_0_DEVICE_ID 8
-#define XPAR_HIER_6_AXI_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_HIER_6_AXI_GPIO_0_IS_DUAL 1
-
-
-/* Definitions for peripheral HIER_7_AXI_GPIO_0 */
-#define XPAR_HIER_7_AXI_GPIO_0_BASEADDR 0x41290000
-#define XPAR_HIER_7_AXI_GPIO_0_HIGHADDR 0x4129FFFF
-#define XPAR_HIER_7_AXI_GPIO_0_DEVICE_ID 9
-#define XPAR_HIER_7_AXI_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_HIER_7_AXI_GPIO_0_IS_DUAL 1
-
-
-/* Definitions for peripheral HIER_8_AXI_GPIO_0 */
-#define XPAR_HIER_8_AXI_GPIO_0_BASEADDR 0x412A0000
-#define XPAR_HIER_8_AXI_GPIO_0_HIGHADDR 0x412AFFFF
-#define XPAR_HIER_8_AXI_GPIO_0_DEVICE_ID 10
-#define XPAR_HIER_8_AXI_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_HIER_8_AXI_GPIO_0_IS_DUAL 1
-
-
-/* Definitions for peripheral HIER_9_AXI_GPIO_0 */
-#define XPAR_HIER_9_AXI_GPIO_0_BASEADDR 0x412B0000
-#define XPAR_HIER_9_AXI_GPIO_0_HIGHADDR 0x412BFFFF
-#define XPAR_HIER_9_AXI_GPIO_0_DEVICE_ID 11
-#define XPAR_HIER_9_AXI_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_HIER_9_AXI_GPIO_0_IS_DUAL 1
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral AXI_GPIO_0 */
-#define XPAR_GPIO_0_BASEADDR 0x41250000
-#define XPAR_GPIO_0_HIGHADDR 0x4125FFFF
-#define XPAR_GPIO_0_DEVICE_ID XPAR_AXI_GPIO_0_DEVICE_ID
-#define XPAR_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_0_IS_DUAL 1
-
-/* Canonical definitions for peripheral AXI_GPIO_1 */
-#define XPAR_GPIO_1_BASEADDR 0x41260000
-#define XPAR_GPIO_1_HIGHADDR 0x4126FFFF
-#define XPAR_GPIO_1_DEVICE_ID XPAR_AXI_GPIO_1_DEVICE_ID
-#define XPAR_GPIO_1_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_1_IS_DUAL 1
-
-/* Canonical definitions for peripheral HIER_0_AXI_GPIO_0 */
-#define XPAR_GPIO_2_BASEADDR 0x41200000
-#define XPAR_GPIO_2_HIGHADDR 0x4120FFFF
-#define XPAR_GPIO_2_DEVICE_ID XPAR_HIER_0_AXI_GPIO_0_DEVICE_ID
-#define XPAR_GPIO_2_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_2_IS_DUAL 1
-
-/* Canonical definitions for peripheral HIER_1_AXI_GPIO_0 */
-#define XPAR_GPIO_3_BASEADDR 0x41210000
-#define XPAR_GPIO_3_HIGHADDR 0x4121FFFF
-#define XPAR_GPIO_3_DEVICE_ID XPAR_HIER_1_AXI_GPIO_0_DEVICE_ID
-#define XPAR_GPIO_3_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_3_IS_DUAL 1
-
-/* Canonical definitions for peripheral HIER_2_AXI_GPIO_0 */
-#define XPAR_GPIO_4_BASEADDR 0x41220000
-#define XPAR_GPIO_4_HIGHADDR 0x4122FFFF
-#define XPAR_GPIO_4_DEVICE_ID XPAR_HIER_2_AXI_GPIO_0_DEVICE_ID
-#define XPAR_GPIO_4_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_4_IS_DUAL 1
-
-/* Canonical definitions for peripheral HIER_3_AXI_GPIO_0 */
-#define XPAR_GPIO_5_BASEADDR 0x41230000
-#define XPAR_GPIO_5_HIGHADDR 0x4123FFFF
-#define XPAR_GPIO_5_DEVICE_ID XPAR_HIER_3_AXI_GPIO_0_DEVICE_ID
-#define XPAR_GPIO_5_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_5_IS_DUAL 1
-
-/* Canonical definitions for peripheral HIER_4_AXI_GPIO_0 */
-#define XPAR_GPIO_6_BASEADDR 0x41240000
-#define XPAR_GPIO_6_HIGHADDR 0x4124FFFF
-#define XPAR_GPIO_6_DEVICE_ID XPAR_HIER_4_AXI_GPIO_0_DEVICE_ID
-#define XPAR_GPIO_6_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_6_IS_DUAL 1
-
-/* Canonical definitions for peripheral HIER_5_AXI_GPIO_0 */
-#define XPAR_GPIO_7_BASEADDR 0x41270000
-#define XPAR_GPIO_7_HIGHADDR 0x4127FFFF
-#define XPAR_GPIO_7_DEVICE_ID XPAR_HIER_5_AXI_GPIO_0_DEVICE_ID
-#define XPAR_GPIO_7_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_7_IS_DUAL 1
-
-/* Canonical definitions for peripheral HIER_6_AXI_GPIO_0 */
-#define XPAR_GPIO_8_BASEADDR 0x41280000
-#define XPAR_GPIO_8_HIGHADDR 0x4128FFFF
-#define XPAR_GPIO_8_DEVICE_ID XPAR_HIER_6_AXI_GPIO_0_DEVICE_ID
-#define XPAR_GPIO_8_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_8_IS_DUAL 1
-
-/* Canonical definitions for peripheral HIER_7_AXI_GPIO_0 */
-#define XPAR_GPIO_9_BASEADDR 0x41290000
-#define XPAR_GPIO_9_HIGHADDR 0x4129FFFF
-#define XPAR_GPIO_9_DEVICE_ID XPAR_HIER_7_AXI_GPIO_0_DEVICE_ID
-#define XPAR_GPIO_9_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_9_IS_DUAL 1
-
-/* Canonical definitions for peripheral HIER_8_AXI_GPIO_0 */
-#define XPAR_GPIO_10_BASEADDR 0x412A0000
-#define XPAR_GPIO_10_HIGHADDR 0x412AFFFF
-#define XPAR_GPIO_10_DEVICE_ID XPAR_HIER_8_AXI_GPIO_0_DEVICE_ID
-#define XPAR_GPIO_10_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_10_IS_DUAL 1
-
-/* Canonical definitions for peripheral HIER_9_AXI_GPIO_0 */
-#define XPAR_GPIO_11_BASEADDR 0x412B0000
-#define XPAR_GPIO_11_HIGHADDR 0x412BFFFF
-#define XPAR_GPIO_11_DEVICE_ID XPAR_HIER_9_AXI_GPIO_0_DEVICE_ID
-#define XPAR_GPIO_11_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_11_IS_DUAL 1
-
-
-/******************************************************************/
-
-/* Definitions for driver GPIOPS */
-#define XPAR_XGPIOPS_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_GPIO_0 */
-#define XPAR_PS7_GPIO_0_DEVICE_ID 0
-#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
-#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_GPIO_0 */
-#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
-#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
-#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
-
-
-/******************************************************************/
-
-/* Definitions for driver QSPIPS */
-#define XPAR_XQSPIPS_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_QSPI_0 */
-#define XPAR_PS7_QSPI_0_DEVICE_ID 0
-#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000
-#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
-#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000
-#define XPAR_PS7_QSPI_0_QSPI_MODE 0
-#define XPAR_PS7_QSPI_0_QSPI_BUS_WIDTH 2
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_QSPI_0 */
-#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID
-#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000
-#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
-#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000
-#define XPAR_XQSPIPS_0_QSPI_MODE 0
-#define XPAR_XQSPIPS_0_QSPI_BUS_WIDTH 2
-
-
-/******************************************************************/
-
-/* Definitions for driver SCUGIC */
-#define XPAR_XSCUGIC_NUM_INSTANCES 1U
-
-/* Definitions for peripheral PS7_SCUGIC_0 */
-#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0U
-#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100U
-#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FFU
-#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_SCUGIC_0 */
-#define XPAR_SCUGIC_0_DEVICE_ID 0U
-#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100U
-#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FFU
-#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
-
-
-/******************************************************************/
-
-/* Definitions for driver SCUTIMER */
-#define XPAR_XSCUTIMER_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_SCUTIMER_0 */
-#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
-#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
-#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_SCUTIMER_0 */
-#define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID
-#define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600
-#define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F
-
-
-/******************************************************************/
-
-/* Definitions for driver SCUWDT */
-#define XPAR_XSCUWDT_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_SCUWDT_0 */
-#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
-#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
-#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_SCUWDT_0 */
-#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
-#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
-#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
-
-
-/******************************************************************/
-
-/* Definitions for driver SDPS */
-#define XPAR_XSDPS_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_SD_0 */
-#define XPAR_PS7_SD_0_DEVICE_ID 0
-#define XPAR_PS7_SD_0_BASEADDR 0xE0100000
-#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
-#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
-#define XPAR_PS7_SD_0_HAS_CD 1
-#define XPAR_PS7_SD_0_HAS_WP 0
-#define XPAR_PS7_SD_0_BUS_WIDTH 0
-#define XPAR_PS7_SD_0_MIO_BANK 0
-#define XPAR_PS7_SD_0_HAS_EMIO 0
-
-
-/******************************************************************/
-
-#define XPAR_PS7_SD_0_IS_CACHE_COHERENT 0
-/* Canonical definitions for peripheral PS7_SD_0 */
-#define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID
-#define XPAR_XSDPS_0_BASEADDR 0xE0100000
-#define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF
-#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000
-#define XPAR_XSDPS_0_HAS_CD 1
-#define XPAR_XSDPS_0_HAS_WP 0
-#define XPAR_XSDPS_0_BUS_WIDTH 0
-#define XPAR_XSDPS_0_MIO_BANK 0
-#define XPAR_XSDPS_0_HAS_EMIO 0
-#define XPAR_XSDPS_0_IS_CACHE_COHERENT 0
-
-
-/******************************************************************/
-
-/* Definitions for driver UARTPS */
-#define XPAR_XUARTPS_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_UART_1 */
-#define XPAR_PS7_UART_1_DEVICE_ID 0
-#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
-#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
-#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 100000000
-#define XPAR_PS7_UART_1_HAS_MODEM 0
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_UART_1 */
-#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
-#define XPAR_XUARTPS_0_BASEADDR 0xE0001000
-#define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF
-#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 100000000
-#define XPAR_XUARTPS_0_HAS_MODEM 0
-
-
-/******************************************************************/
-
-/* Definition for input Clock */
-/* Definitions for driver USBPS */
-#define XPAR_XUSBPS_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_USB_0 */
-#define XPAR_PS7_USB_0_DEVICE_ID 0
-#define XPAR_PS7_USB_0_BASEADDR 0xE0002000
-#define XPAR_PS7_USB_0_HIGHADDR 0xE0002FFF
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_USB_0 */
-#define XPAR_XUSBPS_0_DEVICE_ID XPAR_PS7_USB_0_DEVICE_ID
-#define XPAR_XUSBPS_0_BASEADDR 0xE0002000
-#define XPAR_XUSBPS_0_HIGHADDR 0xE0002FFF
-
-
-/******************************************************************/
-
-/* Definitions for driver XADCPS */
-#define XPAR_XADCPS_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_XADC_0 */
-#define XPAR_PS7_XADC_0_DEVICE_ID 0
-#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100
-#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_XADC_0 */
-#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
-#define XPAR_XADCPS_0_BASEADDR 0xF8007100
-#define XPAR_XADCPS_0_HIGHADDR 0xF8007120
-
-
-/******************************************************************/
-
-/* Xilinx FAT File System Library (XilFFs) User Settings */
-#define FILE_SYSTEM_INTERFACE_SD
-#define FILE_SYSTEM_USE_MKFS
-#define FILE_SYSTEM_NUM_LOGIC_VOL 2
-#define FILE_SYSTEM_USE_STRFUNC 0
-#define FILE_SYSTEM_SET_FS_RPATH 0
-#define FILE_SYSTEM_WORD_ACCESS
-#endif /* end of protection macro */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8/c15180575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8/c15180575243001d18b399c1eb9b3628
deleted file mode 100644
index 853ef6b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8/c15180575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,412 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_io.h
-*
-* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
-*
-* The xil_io.h file contains the interface for the general I/O component, which
-* encapsulates the Input/Output functions for the processors that do not
-* require any special I/O handling.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/29/14 First release
-* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
-* ARM processors
-* 7.20 har 01/03/20 Added Xil_SecureOut32 for avoiding blindwrite for
-* CR-1049218
-* 7.30 kpt 09/21/20 Moved Xil_EndianSwap16 and Xil_EndianSwap32 to
-* xil_io.h and made them as static inline
-* am 10/13/20 Changed the return type of Xil_SecureOut32 function
-* from u32 to int
-* 7.50 dp 02/12/21 Fix compilation error in Xil_EndianSwap32() that occur
-* when -Werror=conversion compiler flag is enabled
-* 7.5 mus 05/17/21 Update the functions with comments. It fixes CR#1067739.
-*
-*
-******************************************************************************/
-
-#ifndef XIL_IO_H /* prevent circular inclusions */
-#define XIL_IO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_printf.h"
-#include "xstatus.h"
-
-#if defined (__MICROBLAZE__)
-#include "mb_interface.h"
-#else
-#include "xpseudo_asm.h"
-#endif
-
-/************************** Function Prototypes ******************************/
-#ifdef ENABLE_SAFETY
-extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
-#endif
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#if defined __GNUC__
-#if defined (__MICROBLAZE__)
-# define INST_SYNC mbar(0)
-# define DATA_SYNC mbar(1)
-# else
-# define SYNCHRONIZE_IO dmb()
-# define INST_SYNC isb()
-# define DATA_SYNC dsb()
-# endif
-#else
-# define SYNCHRONIZE_IO
-# define INST_SYNC
-# define DATA_SYNC
-# define INST_SYNC
-# define DATA_SYNC
-#endif
-
-#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
-#define INLINE inline
-#else
-#define INLINE __inline
-#endif
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading
-* from the specified address and returning the 8 bit Value read from
-* that address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 8 bit Value read from the specified input address.
-
-*
-******************************************************************************/
-static INLINE u8 Xil_In8(UINTPTR Addr)
-{
- return *(volatile u8 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading from
-* the specified address and returning the 16 bit Value read from that
-* address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 16 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u16 Xil_In16(UINTPTR Addr)
-{
- return *(volatile u16 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by
-* reading from the specified address and returning the 32 bit Value
-* read from that address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 32 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u32 Xil_In32(UINTPTR Addr)
-{
- return *(volatile u32 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading the
-* 64 bit Value read from that address.
-*
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 64 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u64 Xil_In64(UINTPTR Addr)
-{
- return *(volatile u64 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for an memory location by
-* writing the 8 bit Value to the the specified address.
-*
-* @param Addr: contains the address to perform the output operation
-* @param Value: contains the 8 bit Value to be written at the specified
-* address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
-{
- /* write 8 bit value to specified address */
- volatile u8 *LocalAddr = (volatile u8 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 16 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains the Value to be written at the specified address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
-{
- /* write 16 bit value to specified address */
- volatile u16 *LocalAddr = (volatile u16 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 32 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains the 32 bit Value to be written at the specified
-* address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
-{
- /* write 32 bit value to specified address */
-#ifndef ENABLE_SAFETY
- volatile u32 *LocalAddr = (volatile u32 *)Addr;
- *LocalAddr = Value;
-#else
- XStl_RegUpdate(Addr, Value);
-#endif
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 64 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains 64 bit Value to be written at the specified address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
-{
- /* write 64 bit value to specified address */
- volatile u64 *LocalAddr = (volatile u64 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
- *
- * @brief Performs an output operation for a memory location by writing the
- * 32 bit Value to the the specified address and then reading it
- * back to verify the value written in the register.
- *
- * @param Addr contains the address to perform the output operation
- * @param Value contains 32 bit Value to be written at the specified address
- *
- * @return Returns Status
- * - XST_SUCCESS on success
- * - XST_FAILURE on failure
- *
- *****************************************************************************/
-static INLINE int Xil_SecureOut32(UINTPTR Addr, u32 Value)
-{
- int Status = XST_FAILURE;
- u32 ReadReg;
- u32 ReadRegTemp;
-
- /* writing 32 bit value to specified address */
- Xil_Out32(Addr, Value);
-
- /* verify value written to specified address with multiple reads */
- ReadReg = Xil_In32(Addr);
- ReadRegTemp = Xil_In32(Addr);
-
- if( (ReadReg == Value) && (ReadRegTemp == Value) ) {
- Status = XST_SUCCESS;
- }
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a 16-bit endian conversion.
-*
-* @param Data: 16 bit value to be converted
-*
-* @return 16 bit Data with converted endianness
-*
-******************************************************************************/
-static INLINE __attribute__((always_inline)) u16 Xil_EndianSwap16(u16 Data)
-{
- return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a 32-bit endian conversion.
-*
-* @param Data: 32 bit value to be converted
-*
-* @return 32 bit data with converted endianness
-*
-******************************************************************************/
-static INLINE __attribute__((always_inline)) u32 Xil_EndianSwap32(u32 Data)
-{
- u16 LoWord;
- u16 HiWord;
-
- /* get each of the half words from the 32 bit word */
-
- LoWord = (u16) (Data & 0x0000FFFFU);
- HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
-
- /* byte swap each of the 16 bit half words */
-
- LoWord = (u16)(((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
- HiWord = (u16)(((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
-
- /* swap the half words before returning the value */
-
- return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-# define Xil_In16LE Xil_In16
-# define Xil_In32LE Xil_In32
-# define Xil_Out16LE Xil_Out16
-# define Xil_Out32LE Xil_Out32
-# define Xil_Htons Xil_EndianSwap16
-# define Xil_Htonl Xil_EndianSwap32
-# define Xil_Ntohs Xil_EndianSwap16
-# define Xil_Ntohl Xil_EndianSwap32
-# else
-# define Xil_In16BE Xil_In16
-# define Xil_In32BE Xil_In32
-# define Xil_Out16BE Xil_Out16
-# define Xil_Out32BE Xil_Out32
-# define Xil_Htons(Data) (Data)
-# define Xil_Htonl(Data) (Data)
-# define Xil_Ntohs(Data) (Data)
-# define Xil_Ntohl(Data) (Data)
-#endif
-#else
-# define Xil_In16LE Xil_In16
-# define Xil_In32LE Xil_In32
-# define Xil_Out16LE Xil_Out16
-# define Xil_Out32LE Xil_Out32
-# define Xil_Htons Xil_EndianSwap16
-# define Xil_Htonl Xil_EndianSwap32
-# define Xil_Ntohs Xil_EndianSwap16
-# define Xil_Ntohl Xil_EndianSwap32
-#endif
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE u16 Xil_In16BE(UINTPTR Addr)
-#else
-static INLINE u16 Xil_In16LE(UINTPTR Addr)
-#endif
-#else
-static INLINE u16 Xil_In16BE(UINTPTR Addr)
-#endif
-{
- u16 value = Xil_In16(Addr);
- return Xil_EndianSwap16(value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE u32 Xil_In32BE(UINTPTR Addr)
-#else
-static INLINE u32 Xil_In32LE(UINTPTR Addr)
-#endif
-#else
-static INLINE u32 Xil_In32BE(UINTPTR Addr)
-#endif
-{
- u32 value = Xil_In32(Addr);
- return Xil_EndianSwap32(value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
-#else
-static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
-#endif
-#else
-static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
-#endif
-{
- Value = Xil_EndianSwap16(Value);
- Xil_Out16(Addr, Value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
-#else
-static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
-#endif
-#else
-static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
-#endif
-{
- Value = Xil_EndianSwap32(Value);
- Xil_Out32(Addr, Value);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_io_interfacing_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8/d021f1515243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8/d021f1515243001d18b399c1eb9b3628
deleted file mode 100644
index f8a0a6a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8/d021f1515243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,88 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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-
-
-
-
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-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/80/00914b585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/80/00914b585243001d18b399c1eb9b3628
deleted file mode 100644
index 2bedeb1..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/80/00914b585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,85 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file usleep.c
-*
-* This function provides a microsecond delay using the Generic counter register in
-* the ARM Cortex A53 MPcore.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 5.4 pkp 28/01/16 Modified the usleep API to configure Time Stamp
-* generator only when disable using frequency from
-* xparamters.h instead of hardcoding
-* 5.05 pkp 13/04/16 Modified usleep routine to call XTime_StartTimer
-* which enables timer only when it is disabled and
-* read counter value directly from register instead
-* of calling XTime_GetTime for optimization
-* 6.0 mus 08/18/16 Updated the usleep signature. Fix for CR#956899
-* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
-* implementation. Now sleep routines will use Timer
-* specified by the user (i.e. Global timer/TTC timer)
-* 7.5 dp 01/05/21 Updated COUNTS_PER_USECOND macros to round it off to
-* nearest possible value so that delta error in time
-* calculations can be minimized.
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "sleep.h"
-#include "xtime_l.h"
-#include "xparameters.h"
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#include "xil_sleeptimer.h"
-#endif
-
-/**************************** Constant Definitions ************************/
-
-/* Global Timer is always clocked at half of the CPU frequency */
-#define COUNTS_PER_USECOND ((COUNTS_PER_SECOND + 500000)/1000000)
-
-/*****************************************************************************/
-/**
-*
-* This API gives a delay in microseconds
-*
-* @param useconds requested
-*
-* @return 0.
-*
-* @note None.
-*
-****************************************************************************/
-int usleep_A53(unsigned long useconds)
-{
-
-#if defined (SLEEP_TIMER_BASEADDR)
- Xil_SleepTTCCommon(useconds, COUNTS_PER_USECOND);
-#else
- XTime tEnd, tCur;
- /* Start global timer counter, it will only be enabled if it is disabled */
- XTime_StartTimer();
-
- tCur = arch_counter_get_cntvct();
- tEnd = tCur + (((XTime) useconds) * COUNTS_PER_USECOND);
- do
- {
- tCur = arch_counter_get_cntvct();
- } while (tCur < tEnd);
-#endif
-
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/80/805c0e545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/80/805c0e545243001d18b399c1eb9b3628
deleted file mode 100644
index 4f19088..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/80/805c0e545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1 +0,0 @@
-{"platformName":"phased_array_platform","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"phased_array_platform","platHandOff":"/home/dylan/Documents/FPGA/phased_array/design_1_wrapper.xsa","platIntHandOff":"/hw/design_1_wrapper.xsa","deviceType":"zynq","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","fsblExtraCompilerFlags":"-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"phased_array_platform","systems":[{"systemName":"phased_array_platform","systemDesc":"phased_array_platform","sysIsBootAutoGen":"true","systemDispName":"phased_array_platform","sysActiveDom":"standalone_domain","sysDefaultDom":"standalone_domain","domains":[{"domainName":"zynq_fsbl","domainDispName":"zynq_fsbl","domainDesc":"FSBL Application BSP - Auto Generated.","processors":"ps7_cortexa9_0","os":"standalone","sdxOs":"standalone","debugEnable":"","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"7.6","mssFile":"","md5Digest":"3ad66e6342e47cdeb46ebdacd606f8ba","compatibleApp":"zynq_fsbl","domType":"bootDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["xilffs:4.6","xilrsa:1.6"],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_domain","domainDispName":"standalone on ps7_cortexa9_0","domainDesc":"standalone_domain","processors":"ps7_cortexa9_0","os":"standalone","sdxOs":"standalone","qemuArgs":"/hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt","qemuData":"/hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"7.6","mssFile":"","md5Digest":"8f4cd5b2e4c0f3d4481583b0fc9b267f","compatibleApp":"","domType":"mssDomain","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":[],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/80/905e29545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/80/905e29545243001d18b399c1eb9b3628
deleted file mode 100644
index 33822bf..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/80/905e29545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,843 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
- *
- * @file xemacps.h
-* @addtogroup emacps_v3_15
-* @{
-* @details
- *
- * The Xilinx Embedded Processor Block Ethernet driver.
- *
- * For a full description of XEMACPS features, please see the hardware spec.
- * This driver supports the following features:
- * - Memory mapped access to host interface registers
- * - Statistics counter registers for RMON/MIB
- * - API for interrupt driven frame transfers for hardware configured DMA
- * - Virtual memory support
- * - Unicast, broadcast, and multicast receive address filtering
- * - Full and half duplex operation
- * - Automatic PAD & FCS insertion and stripping
- * - Flow control
- * - Support up to four 48bit addresses
- * - Address checking for four specific 48bit addresses
- * - VLAN frame support
- * - Pause frame support
- * - Large frame support up to 1536 bytes
- * - Checksum offload
- *
- * Driver Description
- *
- * The device driver enables higher layer software (e.g., an application) to
- * communicate to the XEmacPs. The driver handles transmission and reception
- * of Ethernet frames, as well as configuration and control. No pre or post
- * processing of frame data is performed. The driver does not validate the
- * contents of an incoming frame in addition to what has already occurred in
- * hardware.
- * A single device driver can support multiple devices even when those devices
- * have significantly different configurations.
- *
- * Initialization & Configuration
- *
- * The XEmacPs_Config structure is used by the driver to configure itself.
- * This configuration structure is typically created by the tool-chain based
- * on hardware build properties.
- *
- * The driver instance can be initialized in
- *
- * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a
- * configuration structure provided by the caller. If running in a system
- * with address translation, the provided virtual memory base address
- * replaces the physical address present in the configuration structure.
- *
- * The device supports DMA only as current development plan. No FIFO mode is
- * supported. The driver expects to start the DMA channels and expects that
- * the user has set up the buffer descriptor lists.
- *
- * Interrupts and Asynchronous Callbacks
- *
- * The driver has no dependencies on the interrupt controller. When an
- * interrupt occurs, the handler will perform a small amount of
- * housekeeping work, determine the source of the interrupt, and call the
- * appropriate callback function. All callbacks are registered by the user
- * level application.
- *
- * Virtual Memory
- *
- * All virtual to physical memory mappings must occur prior to accessing the
- * driver API.
- *
- * For DMA transactions, user buffers supplied to the driver must be in terms
- * of their physical address.
- *
- * DMA
- *
- * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
- * These BDs are typically chained together into a list the hardware follows
- * when transferring data in and out of the packet buffers. Each BD describes
- * a memory region containing either a full or partial Ethernet packet.
- *
- * Interrupt coalescing is not supported from this built-in DMA engine.
- *
- * This API requires the user to understand how the DMA operates. The
- * following paragraphs provide some explanation, but the user is encouraged
- * to read documentation in xemacps_bdring.h as well as study example code
- * that accompanies this driver.
- *
- * The API is designed to get BDs to and from the DMA engine in the most
- * efficient means possible. The first step is to establish a memory region
- * to contain all BDs for a specific channel. This is done with
- * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
- * follow as BDs are processed. The ring will consist of a user defined number
- * of BDs which will all be partially initialized. For example on the transmit
- * channel, the driver will initialize all BDs' so that they are configured
- * for transmit. The more fields that can be permanently setup at
- * initialization, then the fewer accesses will be needed to each BD while
- * the DMA engine is in operation resulting in better throughput and CPU
- * utilization. The best case initialization would require the user to set
- * only a frame buffer address and length prior to submitting the BD to the
- * engine.
- *
- * BDs move through the engine with the help of functions
- * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
- * and XEmacPs_BdRingFree().
- * All these functions handle BDs that are in place. That is, there are no
- * copies of BDs kept anywhere and any BD the user interacts with is an actual
- * BD from the same ring hardware accesses.
- *
- * BDs in the ring go through a series of states as follows:
- * 1. Idle. The driver controls BDs in this state.
- * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
- * reserve BD(s). Once allocated, the user may setup the BD(s) with
- * frame buffer address, length, and other attributes. The user controls
- * BDs in this state.
- * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
- * in this state are either waiting to be processed by hardware, are in
- * process, or have been processed. The DMA engine controls BDs in this
- * state.
- * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
- * user. Once retrieved, the user can examine each BD for the outcome of
- * the DMA transfer. The user controls BDs in this state. After examining
- * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
- * into state 1.
- *
- * Each of the four BD accessor functions operate on a set of BDs. A set is
- * defined as a segment of the BD ring consisting of one or more BDs. The user
- * views the set as a pointer to the first BD along with the number of BDs for
- * that set. The set can be navigated by using macros XEmacPs_BdNext(). The
- * user must exercise extreme caution when changing BDs in a set as there is
- * nothing to prevent doing a mBdNext past the end of the set and modifying a
- * BD out of bounds.
- *
- * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
- * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
- * tandem. The same BD set retrieved with BdRingAlloc should be the same one
- * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
- * BdRIngFree.
- *
- * Alignment & Data Cache Restrictions
- *
- * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
- * aligned. Please reference xemacps_bd.h for cache related macros.
- *
- * DMA Tx:
- *
- * - If frame buffers exist in cached memory, then they must be flushed
- * prior to committing them to hardware.
- *
- * DMA Rx:
- *
- * - If frame buffers exist in cached memory, then the cache must be
- * invalidated for the memory region containing the frame prior to data
- * access
- *
- * Both cache invalidate/flush are taken care of in driver code.
- *
- * Buffer Copying
- *
- * The driver is designed for a zero-copy buffer scheme. That is, the driver
- * will not copy buffers. This avoids potential throughput bottlenecks within
- * the driver. If byte copying is required, then the transfer will take longer
- * to complete.
- *
- * Checksum Offloading
- *
- * The Embedded Processor Block Ethernet can be configured to perform IP, TCP
- * and UDP checksum offloading in both receive and transmit directions.
- *
- * IP packets contain a 16-bit checksum field, which is the 16-bit 1s
- * complement of the 1s complement sum of all 16-bit words in the header.
- * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
- * 1s complement of the 1s complement sum of all 16-bit words in the header,
- * the data and a conceptual pseudo header.
- *
- * To calculate these checksums in software requires each byte of the packet
- * to be read. For TCP and UDP this can use a large amount of processing power.
- * Offloading the checksum calculation to hardware can result in significant
- * performance improvements.
- *
- * The transmit checksum offload is only available to use DMA in packet buffer
- * mode. This is because the complete frame to be transmitted must be read
- * into the packet buffer memory before the checksum can be calculated and
- * written to the header at the beginning of the frame.
- *
- * For IP, TCP or UDP receive checksum offload to be useful, the operating
- * system containing the protocol stack must be aware that this offload is
- * available so that it can make use of the fact that the hardware has verified
- * the checksum.
- *
- * When receive checksum offloading is enabled in the hardware, the IP header
- * checksum is checked, where the packet meets the following criteria:
- *
- * 1. If present, the VLAN header must be four octets long and the CFI bit
- * must not be set.
- * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
- * encoding.
- * 3. IP v4 packet.
- * 4. IP header is of a valid length.
- * 5. Good IP header checksum.
- * 6. No IP fragmentation.
- * 7. TCP or UDP packet.
- *
- * When an IP, TCP or UDP frame is received, the receive buffer descriptor
- * gives an indication if the hardware was able to verify the checksums.
- * There is also an indication if the frame had SNAP encapsulation. These
- * indication bits will replace the type ID match indication bits when the
- * receive checksum offload is enabled.
- *
- * If any of the checksums are verified incorrect by the hardware, the packet
- * is discarded and the appropriate statistics counter incremented.
- *
- * PHY Interfaces
- *
- * RGMII 1.3 is the only interface supported.
- *
- * Asserts
- *
- * Asserts are used within all Xilinx drivers to enforce constraints on
- * parameters. Asserts can be turned off on a system-wide basis by defining,
- * at compile time, the NDEBUG identifier. By default, asserts are turned on
- * and it is recommended that users leave asserts on during development. For
- * deployment use -DNDEBUG compiler switch to remove assert code.
- *
- * @note
- *
- * Xilinx drivers are typically composed of two parts, one is the driver
- * and the other is the adapter. The driver is independent of OS and processor
- * and is intended to be highly portable. The adapter is OS-specific and
- * facilitates communication between the driver and an OS.
- * This driver is intended to be RTOS and processor independent. Any needs for
- * dynamic memory management, threads or thread mutual exclusion, or cache
- * control must be satisfied bythe layer above this driver.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -------------------------------------------------------
- * 1.00a wsy 01/10/10 First release
- * 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file
- * xemacps_bdring.c is modified. Earlier it was checking for
- * "BdLimit"(passed argument) number of BDs for finding out
- * which BDs are successfully processed. Now one more check
- * is added. It looks for BDs till the current BD pointer
- * reaches HwTail. By doing this processing time is saved.
- * 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
- * xemacps_bdring.c is modified. Now start of packet is
- * searched for returning the number of BDs processed.
- * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
- * registers. Added a new API to set the bust length.
- * Added some new hash-defines.
- * 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for
- * Rx errors. Under heavy Rx traffic, there will be a large
- * number of errors related to receive buffer not available.
- * Because of a HW bug (SI #692601), under such heavy errors,
- * the Rx data path can become unresponsive. To reduce the
- * probabilities for hitting this HW bug, the SW writes to
- * bit 18 to flush a packet from Rx DPRAM immediately. The
- * changes for it are done in the function
- * XEmacPs_IntrHandler.
- * 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
- * removed. It is expected that all BDs are allocated in
- * from uncached area.
- * 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
- * to 0x1fff. This fixes the CR#744902.
- * Made changes in example file xemacps_example.h to fix compilation
- * issues with iarcc compiler.
- * 2.0 adk 10/12/13 Updated as per the New Tcl API's
- * 2.1 adk 11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
- * 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy
- * address in xparameters.h when GMII to RGMII converter
- * is present in hw.
- * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
- * changes.
- * 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
- * 1000BASE-X mode export proper values to the xparameters.h
- * file. Changes are made in the driver tcl file.
- * 3.0 adk 08/1/15 Don't include gem in peripheral test when gem is
- * configured with PCS/PMA Core. Changes are made in the
- * test app tcl(CR:827686).
- * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
- * 3.0 hk 03/18/15 Added support for jumbo frames. Increase AHB burst.
- * Disable extended mode. Perform all 64 bit changes under
- * check for arch64.
- * Remove "used bit set" from TX error interrupt masks.
- * 3.1 hk 07/27/15 Do not call error handler with '0' error code when
- * there is no error. CR# 869403
- * 08/10/15 Update upper 32 bit tx and rx queue ptr registers.
- * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
- * 3.4 ms 01/23/17 Modified xil_printf statement in main function for all
- * examples to ensure that "Successfully ran" and "Failed"
- * strings are available in all examples. This is a fix
- * for CR-965028.
- * ms 03/17/17 Modified text file in examples folder for doxygen
- * generation.
- * ms 04/05/17 Added tabspace for return statements in functions of
- * xemacps_ieee1588_example.c for proper documentation
- * while generating doxygen.
- * 3.5 hk 08/14/17 Update cache coherency information of the interface in
- * its config structure.
- * 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
- * changed to volatile.
- * Add API XEmacPs_BdRingPtrReset() to reset pointers
- * 3.8 hk 07/19/18 Fixed CPP, GCC and doxygen warnings - CR-1006327
- * hk 09/17/18 Fix PTP interrupt masks and cleanup comments.
- * 3.9 hk 01/23/19 Add RX watermark support
- * 3.11 sd 02/14/20 Add clock support
- * 3.13 nsk 12/14/20 Updated the tcl to not to use the instance names.
- *
- *
- *
- ****************************************************************************/
-
-#ifndef XEMACPS_H /* prevent circular inclusions */
-#define XEMACPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xemacps_hw.h"
-#include "xemacps_bd.h"
-#include "xemacps_bdring.h"
-#if defined (XCLOCKING)
-#include "xil_clocking.h"
-#endif
-
-/************************** Constant Definitions ****************************/
-
-/*
- * Device information
- */
-#define XEMACPS_DEVICE_NAME "xemacps"
-#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC"
-
-
-/** @name Configuration options
- *
- * Device configuration options. See the XEmacPs_SetOptions(),
- * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
- * use options.
- *
- * The default state of the options are noted and are what the device and
- * driver will be set to after calling XEmacPs_Reset() or
- * XEmacPs_Initialize().
- *
- * @{
- */
-
-#define XEMACPS_PROMISC_OPTION 0x00000001U
-/**< Accept all incoming packets.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_FRAME1536_OPTION 0x00000002U
-/**< Frame larger than 1516 support for Tx & Rx.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_VLAN_OPTION 0x00000004U
-/**< VLAN Rx & Tx frame support.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U
-/**< Enable recognition of flow control frames on Rx
- * This option defaults to enabled (set) */
-
-#define XEMACPS_FCS_STRIP_OPTION 0x00000020U
-/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
- * stripped.
- * This option defaults to enabled (set) */
-
-#define XEMACPS_FCS_INSERT_OPTION 0x00000040U
-/**< Generate FCS field and add PAD automatically for outgoing frames.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U
-/**< Enable Length/Type error checking for incoming frames. When this option is
- * set, the MAC will filter frames that have a mismatched type/length field
- * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
- * types of frames are encountered. When this option is cleared, the MAC will
- * allow these types of frames to be received.
- *
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U
-/**< Enable the transmitter.
- * This option defaults to enabled (set) */
-
-#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U
-/**< Enable the receiver
- * This option defaults to enabled (set) */
-
-#define XEMACPS_BROADCAST_OPTION 0x00000400U
-/**< Allow reception of the broadcast address
- * This option defaults to enabled (set) */
-
-#define XEMACPS_MULTICAST_OPTION 0x00000800U
-/**< Allows reception of multicast addresses programmed into hash
- * This option defaults to disabled (clear) */
-
-#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U
-/**< Enable the RX checksum offload
- * This option defaults to enabled (set) */
-
-#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U
-/**< Enable the TX checksum offload
- * This option defaults to enabled (set) */
-
-#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U
-#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U
-
-#define XEMACPS_DEFAULT_OPTIONS \
- ((u32)XEMACPS_FLOW_CONTROL_OPTION | \
- (u32)XEMACPS_FCS_INSERT_OPTION | \
- (u32)XEMACPS_FCS_STRIP_OPTION | \
- (u32)XEMACPS_BROADCAST_OPTION | \
- (u32)XEMACPS_LENTYPE_ERR_OPTION | \
- (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
- (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
- (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
- (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
-
-/**< Default options set when device is initialized or reset */
-/*@}*/
-
-/** @name Callback identifiers
- *
- * These constants are used as parameters to XEmacPs_SetHandler()
- * @{
- */
-#define XEMACPS_HANDLER_DMASEND 1U
-#define XEMACPS_HANDLER_DMARECV 2U
-#define XEMACPS_HANDLER_ERROR 3U
-/*@}*/
-
-/* Constants to determine the configuration of the hardware device. They are
- * used to allow the driver to verify it can operate with the hardware.
- */
-#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */
-
-/* The next few constants help upper layers determine the size of memory
- * pools used for Ethernet buffers and descriptor lists.
- */
-#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */
-
-#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */
-#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */
-#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */
-#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
-#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
-#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
- XEMACPS_TRL_SIZE)
-#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
- XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
-#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
- XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
-
-/* DMACR Bust length hash defines */
-
-#define XEMACPS_SINGLE_BURST 0x00000001
-#define XEMACPS_4BYTE_BURST 0x00000004
-#define XEMACPS_8BYTE_BURST 0x00000008
-#define XEMACPS_16BYTE_BURST 0x00000010
-
-
-/**************************** Type Definitions ******************************/
-/** @name Typedefs for callback functions
- *
- * These callbacks are invoked in interrupt context.
- * @{
- */
-/**
- * Callback invoked when frame(s) have been sent or received in interrupt
- * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
- *
- * @param CallBackRef is user data assigned when the callback was set.
- *
- * @note
- * See xemacps_hw.h for bitmasks definitions and the device hardware spec for
- * further information on their meaning.
- *
- */
-typedef void (*XEmacPs_Handler) (void *CallBackRef);
-
-/**
- * Callback when an asynchronous error occurs. To set this callback, invoke
- * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
- * parameter.
- *
- * @param CallBackRef is user data assigned when the callback was set.
- * @param Direction defines either receive or transmit error(s) has occurred.
- * @param ErrorWord definition varies with Direction
- *
- */
-typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
- u32 ErrorWord);
-
-/*@}*/
-
-/**
- * This typedef contains configuration information for a device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
- u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
- * describes whether Cache Coherent or not */
-#if defined (XCLOCKING)
- u32 RefClk; /**< Input clock */
-#endif
- u16 S1GDiv0; /**< 1Gbps Clock Divider 0 */
- u8 S1GDiv1; /**< 1Gbps Clock Divider 1 */
- u16 S100MDiv0; /**< 100Mbps Clock Divider 0 */
- u8 S100MDiv1; /**< 100Mbps Clock Divider 1 */
- u16 S10MDiv0; /**< 10Mbps Clock Divider 0 */
- u8 S10MDiv1; /**< 10Mbps Clock Divider 1 */
-} XEmacPs_Config;
-
-
-/**
- * The XEmacPs driver instance data. The user is required to allocate a
- * structure of this type for every XEmacPs device in the system. A pointer
- * to a structure of this type is then passed to the driver API functions.
- */
-typedef struct XEmacPs_Instance {
- XEmacPs_Config Config; /* Hardware configuration */
- u32 IsStarted; /* Device is currently started */
- u32 IsReady; /* Device is initialized and ready */
- u32 Options; /* Current options word */
-
- XEmacPs_BdRing TxBdRing; /* Transmit BD ring */
- XEmacPs_BdRing RxBdRing; /* Receive BD ring */
-
- XEmacPs_Handler SendHandler;
- XEmacPs_Handler RecvHandler;
- void *SendRef;
- void *RecvRef;
-
- XEmacPs_ErrHandler ErrorHandler;
- void *ErrorRef;
- u32 Version;
- u32 RxBufMask;
- u32 MaxMtuSize;
- u32 MaxFrameSize;
- u32 MaxVlanFrameSize;
-
-} XEmacPs;
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* Retrieve the Tx ring object. This object can be used in the various Ring
-* API functions.
-*
-* @param InstancePtr is the DMA channel to operate on.
-*
-* @return TxBdRing attribute
-*
-* @note
-* C-style signature:
-* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
-
-/****************************************************************************/
-/**
-* Retrieve the Rx ring object. This object can be used in the various Ring
-* API functions.
-*
-* @param InstancePtr is the DMA channel to operate on.
-*
-* @return RxBdRing attribute
-*
-* @note
-* C-style signature:
-* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
-
-/****************************************************************************/
-/**
-*
-* Enable interrupts specified in Mask. The corresponding interrupt for
-* each bit set to 1 in Mask, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to enable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntEnable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_IER_OFFSET, \
- ((Mask) & XEMACPS_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Disable interrupts specified in Mask. The corresponding interrupt for
-* each bit set to 1 in Mask, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to disable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntDisable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_IDR_OFFSET, \
- ((Mask) & XEMACPS_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Enable interrupts specified in Mask. The corresponding interrupt for
-* each bit set to 1 in Mask, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to enable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_INTQ1_IER_OFFSET, \
- ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Disable interrupts specified in Mask. The corresponding interrupt for
-* each bit set to 1 in Mask, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to disable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_INTQ1_IDR_OFFSET, \
- ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* This macro triggers trasmit circuit to send data currently in TX buffer(s).
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return
-*
-* @note
-*
-* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_Transmit(InstancePtr) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_NWCTRL_OFFSET, \
- (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
-
-/****************************************************************************/
-/**
-*
-* This macro determines if the device is configured with checksum offloading
-* on the receive channel
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return
-*
-* Boolean TRUE if the device is configured with checksum offloading, or
-* FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_IsRxCsum(InstancePtr) \
- ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
- ? TRUE : FALSE)
-
-/****************************************************************************/
-/**
-*
-* This macro determines if the device is configured with checksum offloading
-* on the transmit channel
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return
-*
-* Boolean TRUE if the device is configured with checksum offloading, or
-* FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_IsTxCsum(InstancePtr) \
- ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
- ? TRUE : FALSE)
-
-/************************** Function Prototypes *****************************/
-
-/****************************************************************************/
-/**
-*
-* This macro sets RX watermark register.
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-* @param High is the non-zero RX high watermark value. When SRAM fill level
-* is above this, a pause frame will be sent.
-* @param Low is the non-zero RX low watermark value. When SRAM fill level
-* is below this, a zero length pause frame will be sent IF the last
-* pause frame sent was non-zero.
-*
-* @return None
-*
-* @note
-*
-* Signature: void XEmacPs_SetRXWatermark(XEmacPs *InstancePtr, u16 High,
-* u16 Low)
-*
-*****************************************************************************/
-#define XEmacPs_SetRXWatermark(InstancePtr, High, Low) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_RXWATERMARK_OFFSET, \
- (High & XEMACPS_RXWM_HIGH_MASK) | \
- ((Low << XEMACPS_RXWM_LOW_SHFT_MSK) & XEMACPS_RXWM_LOW_MASK) |)
-
-/****************************************************************************/
-/**
-*
-* This macro gets RX watermark register.
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return RX watermark register value
-*
-* @note
-*
-* Signature: void XEmacPs_GetRXWatermark(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_GetRXWatermark(InstancePtr) \
- XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_RXWATERMARK_OFFSET)
-/*
- * Initialization functions in xemacps.c
- */
-LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
- UINTPTR EffectiveAddress);
-void XEmacPs_Start(XEmacPs *InstancePtr);
-void XEmacPs_Stop(XEmacPs *InstancePtr);
-void XEmacPs_Reset(XEmacPs *InstancePtr);
-void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
- u16 Direction);
-
-/*
- * Lookup configuration in xemacps_sinit.c
- */
-XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
-
-/*
- * Interrupt-related functions in xemacps_intr.c
- * DMA only and FIFO is not supported. This DMA does not support coalescing.
- */
-LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
- void *FuncPointer, void *CallBackRef);
-void XEmacPs_IntrHandler(void *XEmacPsPtr);
-
-/*
- * MAC configuration/control functions in XEmacPs_control.c
- */
-LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
-LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
-u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
-
-LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
-LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
-void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
-
-LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
-void XEmacPs_ClearHash(XEmacPs *InstancePtr);
-void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
-
-void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
- XEmacPs_MdcDiv Divisor);
-void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
-u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
-LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
- u32 RegisterNum, u16 *PhyDataPtr);
-LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
- u32 RegisterNum, u16 PhyData);
-LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
-
-LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
-void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/80/a0b50f575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/80/a0b50f575243001d18b399c1eb9b3628
deleted file mode 100644
index 99727bc..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/80/a0b50f575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,147 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xuartps_selftest.c
-* @addtogroup uartps_v3_11
-* @{
-*
-* This file contains the self-test functions for the XUartPs driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00 drg/jz 01/13/10 First Release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.9 sd 02/06/20 Added clock support
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xuartps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XUARTPS_TOTAL_BYTES (u8)32
-
-/************************** Variable Definitions *****************************/
-
-static u8 TestString[XUARTPS_TOTAL_BYTES]="abcdefghABCDEFGH012345677654321";
-static u8 ReturnString[XUARTPS_TOTAL_BYTES];
-
-/************************** Function Prototypes ******************************/
-
-
-/****************************************************************************/
-/**
-*
-* This function runs a self-test on the driver and hardware device. This self
-* test performs a local loopback and verifies data can be sent and received.
-*
-* The time for this test is proportional to the baud rate that has been set
-* prior to calling this function.
-*
-* The mode and control registers are restored before return.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-*
-* @return
-* - XST_SUCCESS if the test was successful
-* - XST_UART_TEST_FAIL if the test failed looping back the data
-*
-* @note
-*
-* This function can hang if the hardware is not functioning properly.
-*
-******************************************************************************/
-s32 XUartPs_SelfTest(XUartPs *InstancePtr)
-{
- s32 Status = XST_SUCCESS;
- u32 IntrRegister;
- u32 ModeRegister;
- u8 Index;
- u32 ReceiveDataResult;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-#if defined (XCLOCKING)
- Xil_ClockEnable(InstancePtr->Config.RefClk);
-#endif
-
- /* Disable all interrupts in the interrupt disable register */
- IntrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IMR_OFFSET);
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
- XUARTPS_IXR_MASK);
-
- /* Setup for local loopback */
- ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_MR_OFFSET);
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
- ((ModeRegister & (u32)(~XUARTPS_MR_CHMODE_MASK)) |
- (u32)XUARTPS_MR_CHMODE_L_LOOP));
-
- /* Send a number of bytes and receive them, one at a time. */
- for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
- /*
- * Send out the byte and if it was not sent then the failure
- * will be caught in the comparison at the end
- */
- (void)XUartPs_Send(InstancePtr, &TestString[Index], 1U);
-
- /*
- * Wait until the byte is received. This can hang if the HW
- * is broken. Watch for the FIFO empty flag to be false.
- */
- ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
- XUARTPS_SR_RXEMPTY;
- while (ReceiveDataResult == XUARTPS_SR_RXEMPTY ) {
- ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
- XUARTPS_SR_RXEMPTY;
- }
-
- /* Receive the byte */
- (void)XUartPs_Recv(InstancePtr, &ReturnString[Index], 1U);
- }
-
- /*
- * Compare the bytes received to the bytes sent to verify the exact data
- * was received
- */
- for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
- if (TestString[Index] != ReturnString[Index]) {
- Status = XST_UART_TEST_FAIL;
- }
- }
-
- /*
- * Restore the registers which were altered to put into polling and
- * loopback modes so that this test is not destructive
- */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
- IntrRegister);
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
- ModeRegister);
-
-#if defined (XCLOCKING)
- Xil_ClockDisable(InstancePtr->Config.RefClk);
-#endif
- return Status;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/80/c0b4ae575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/80/c0b4ae575243001d18b399c1eb9b3628
deleted file mode 100644
index b924726..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/80/c0b4ae575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,507 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
- *
- * @file xusbps_endpoint.h
-* @addtogroup usbps_v2_7
-* @{
- *
- * This is an internal file containung the definitions for endpoints. It is
- * included by the xusbps_endpoint.c which is implementing the endpoint
- * functions and by xusbps_intr.c.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- --------------------------------------------------------
- * 1.00a wgr 10/10/10 First release
- * 2.5 pm 02/20/20 Added multiplier bit for ISO frame handling.
- *
- *
- ******************************************************************************/
-#ifndef XUSBPS_ENDPOINT_H
-#define XUSBPS_ENDPOINT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xusbps.h"
-#include "xil_types.h"
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-
-/**
- * Endpoint Device Transfer Descriptor
- *
- * The dTD describes to the device controller the location and quantity of data
- * to be sent/received for given transfer. The driver does not attempt to
- * modify any field in an active dTD except the Next Link Pointer.
- */
-#define XUSBPS_dTDNLP 0x00 /**< Pointer to the next descriptor */
-#define XUSBPS_dTDTOKEN 0x04 /**< Descriptor Token */
-#define XUSBPS_dTDBPTR0 0x08 /**< Buffer Pointer 0 */
-#define XUSBPS_dTDBPTR1 0x0C /**< Buffer Pointer 1 */
-#define XUSBPS_dTDBPTR2 0x10 /**< Buffer Pointer 2 */
-#define XUSBPS_dTDBPTR3 0x14 /**< Buffer Pointer 3 */
-#define XUSBPS_dTDBPTR4 0x18 /**< Buffer Pointer 4 */
-#define XUSBPS_dTDBPTR(n) (XUSBPS_dTDBPTR0 + (n) * 0x04)
-#define XUSBPS_dTDRSRVD 0x1C /**< Reserved field */
-
-/* We use the reserved field in the dTD to store user data. */
-#define XUSBPS_dTDUSERDATA XUSBPS_dTDRSRVD /**< Reserved field */
-
-
-/** @name dTD Next Link Pointer (dTDNLP) bit positions.
- * @{
- */
-#define XUSBPS_dTDNLP_T_MASK 0x00000001
- /**< USB dTD Next Link Pointer Terminate Bit */
-#define XUSBPS_dTDNLP_ADDR_MASK 0xFFFFFFE0
- /**< USB dTD Next Link Pointer Address [31:5] */
-/* @} */
-
-
-/** @name dTD Token (dTDTOKEN) bit positions.
- * @{
- */
-#define XUSBPS_dTDTOKEN_XERR_MASK 0x00000008 /**< dTD Transaction Error */
-#define XUSBPS_dTDTOKEN_BUFERR_MASK 0x00000020 /**< dTD Data Buffer Error */
-#define XUSBPS_dTDTOKEN_HALT_MASK 0x00000040 /**< dTD Halted Flag */
-#define XUSBPS_dTDTOKEN_ACTIVE_MASK 0x00000080 /**< dTD Active Bit */
-#define XUSBPS_dTDTOKEN_MULTO_MASK 0x00000C00 /**< Multiplier Override Field [1:0] */
-#define XUSBPS_dTDTOKEN_IOC_MASK 0x00008000 /**< Interrupt on Complete Bit */
-#define XUSBPS_dTDTOKEN_LEN_MASK 0x7FFF0000 /**< Transfer Length Field */
-/* @} */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- *
- * IMPORTANT NOTE:
- * ===============
- *
- * Many of the following macros modify Device Queue Head (dQH) data structures
- * and Device Transfer Descriptor (dTD) data structures. Those structures can
- * potentially reside in CACHED memory. Therefore, it's the callers
- * responsibility to ensure cache coherency by using provided
- *
- * XUsbPs_dQHInvalidateCache()
- * XUsbPs_dQHFlushCache()
- * XUsbPs_dTDInvalidateCache()
- * XUsbPs_dTDFlushCache()
- *
- * function calls.
- *
- ******************************************************************************/
-#define XUsbPs_dTDInvalidateCache(dTDPtr) \
- Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
-
-#define XUsbPs_dTDFlushCache(dTDPtr) \
- Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
-
-#define XUsbPs_dQHInvalidateCache(dQHPtr) \
- Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
-
-#define XUsbPs_dQHFlushCache(dQHPtr) \
- Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Transfer Length for the given Transfer Descriptor.
- *
- * @param dTDPtr is pointer to the dTD element.
- * @param Len is the length to be set. Range: 0..16384
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetTransferLen(dTDPtr, Len) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
- ~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16))
-
-
-/*****************************************************************************/
-/**
- *
- * This macro gets the Next Link pointer of the given Transfer Descriptor.
- *
- * @param dTDPtr is pointer to the dTD element.
- *
- * @return TransferLength field of the descriptor.
- *
- * @note C-style signature:
- * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDGetNLP(dTDPtr) \
- (XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\
- & XUSBPS_dTDNLP_ADDR_MASK))
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Next Link pointer of the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- * @param NLP is the Next Link Pointer
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetNLP(dTDPtr, NLP) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
- (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
- ~XUSBPS_dTDNLP_ADDR_MASK) | \
- ((NLP) & XUSBPS_dTDNLP_ADDR_MASK))
-
-
-/*****************************************************************************/
-/**
- *
- * This macro gets the Transfer Length for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @return TransferLength field of the descriptor.
- *
- * @note C-style signature:
- * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDGetTransferLen(dTDPtr) \
- (u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) \
- & XUSBPS_dTDTOKEN_LEN_MASK) >> 16)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Interrupt On Complete (IOC) bit for the given Transfer
- * Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetIOC(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetIOC(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
- XUSBPS_dTDTOKEN_IOC_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Terminate bit for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetTerminate(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetTerminate(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) | \
- XUSBPS_dTDNLP_T_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro clears the Terminate bit for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDClrTerminate(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDClrTerminate(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
- ~XUSBPS_dTDNLP_T_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro checks if the given descriptor is active.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @return
- * - TRUE: The buffer is active.
- * - FALSE: The buffer is not active.
- *
- * @note C-style signature:
- * int XUsbPs_dTDIsActive(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDIsActive(dTDPtr) \
- ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
- XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Active bit for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetActive(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetActive(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
- XUSBPS_dTDTOKEN_ACTIVE_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the multiplier bit for the Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- * @param val is the multiplier value.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetMultO(u32 dTDPtr, u32 val)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetMultO(dTDPtr, val) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
- (~XUSBPS_dTDTOKEN_MULTO_MASK)) | val)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro reads the content of a field in a Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- * @param Id is the field ID inside the dTD element to read.
- *
- * @note C-style signature:
- * u32 XUsbPs_ReaddTD(u32 dTDPtr, u32 Id)
- *
- ******************************************************************************/
-#define XUsbPs_ReaddTD(dTDPtr, Id) (*(u32 *)((u32)(dTDPtr) + (u32)(Id)))
-
-/*****************************************************************************/
-/**
- *
- * This macro writes a value to a field in a Transfer Descriptor.
- *
- * @param dTDPtr is pointer to the dTD element.
- * @param Id is the field ID inside the dTD element to read.
- * @param Val is the value to write to the field.
- *
- * @note C-style signature:
- * u32 XUsbPs_WritedTD(u32 dTDPtr, u32 Id, u32 Val)
- *
- ******************************************************************************/
-#define XUsbPs_WritedTD(dTDPtr, Id, Val) \
- (*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val))
-
-
-/******************************************************************************/
-/**
- * Endpoint Device Queue Head
- *
- * Device queue heads are arranged in an array in a continuous area of memory
- * pointed to by the ENDPOINTLISTADDR pointer. The device controller will index
- * into this array based upon the endpoint number received from the USB bus.
- * All information necessary to respond to transactions for all primed
- * transfers is contained in this list so the Device Controller can readily
- * respond to incoming requests without having to traverse a linked list.
- *
- * The device Endpoint Queue Head (dQH) is where all transfers are managed. The
- * dQH is a 48-byte data structure, but must be aligned on a 64-byte boundary.
- * During priming of an endpoint, the dTD (device transfer descriptor) is
- * copied into the overlay area of the dQH, which starts at the nextTD pointer
- * DWord and continues through the end of the buffer pointers DWords. After a
- * transfer is complete, the dTD status DWord is updated in the dTD pointed to
- * by the currentTD pointer. While a packet is in progress, the overlay area of
- * the dQH is used as a staging area for the dTD so that the Device Controller
- * can access needed information with little minimal latency.
- *
- * @note
- * Software must ensure that no interface data structure reachable by the
- * Device Controller spans a 4K-page boundary. The first element of the
- * Endpoint Queue Head List must be aligned on a 4K boundary.
- */
-#define XUSBPS_dQHCFG 0x00 /**< dQH Configuration */
-#define XUSBPS_dQHCPTR 0x04 /**< dQH Current dTD Pointer */
-#define XUSBPS_dQHdTDNLP 0x08 /**< dTD Next Link Ptr in dQH
- overlay */
-#define XUSBPS_dQHdTDTOKEN 0x0C /**< dTD Token in dQH overlay */
-#define XUSBPS_dQHSUB0 0x28 /**< USB dQH Setup Buffer 0 */
-#define XUSBPS_dQHSUB1 0x2C /**< USB dQH Setup Buffer 1 */
-
-
-/** @name dQH Configuration (dQHCFG) bit positions.
- * @{
- */
-#define XUSBPS_dQHCFG_IOS_MASK 0x00008000
- /**< USB dQH Interrupt on Setup Bit */
-#define XUSBPS_dQHCFG_MPL_MASK 0x07FF0000
- /**< USB dQH Maximum Packet Length
- * Field [10:0] */
-#define XUSBPS_dQHCFG_MPL_SHIFT 16
-#define XUSBPS_dQHCFG_ZLT_MASK 0x20000000
- /**< USB dQH Zero Length Termination
- * Select Bit */
-#define XUSBPS_dQHCFG_MULT_MASK 0xC0000000
- /* USB dQH Number of Transactions Field
- * [1:0] */
-#define XUSBPS_dQHCFG_MULT_SHIFT 30
-/* @} */
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Maximum Packet Length field of the give Queue Head.
- *
- * @param dQHPtr is a pointer to the dQH element.
- * @param Len is the length to be set.
- *
- * @note C-style signature:
- * void XUsbPs_dQHSetMaxPacketLen(u32 dQHPtr, u32 Len)
- *
- ******************************************************************************/
-#define XUsbPs_dQHSetMaxPacketLen(dQHPtr, Len) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
- ~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16))
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Interrupt On Setup (IOS) bit for an endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHSetIOS(u32 dQHPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dQHSetIOS(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
- XUSBPS_dQHCFG_IOS_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro clears the Interrupt On Setup (IOS) bit for an endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHClrIOS(u32 dQHPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dQHClrIOS(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
- ~XUSBPS_dQHCFG_IOS_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro enables Zero Length Termination for the endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHEnableZLT(u32 dQHPtr)
- *
- *
- ******************************************************************************/
-#define XUsbPs_dQHEnableZLT(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
- ~XUSBPS_dQHCFG_ZLT_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro disables Zero Length Termination for the endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHDisableZLT(u32 dQHPtr)
- *
- *
- ******************************************************************************/
-#define XUsbPs_dQHDisableZLT(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
- XUSBPS_dQHCFG_ZLT_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro reads the content of a field in a Queue Head.
- *
- * @param dQHPtr is a pointer to the dQH element.
- * @param Id is the Field ID inside the dQH element to read.
- *
- * @note C-style signature:
- * u32 XUsbPs_ReaddQH(u32 dQHPtr, u32 Id)
- *
- ******************************************************************************/
-#define XUsbPs_ReaddQH(dQHPtr, Id) (*(u32 *)((u32)(dQHPtr) + (u32) (Id)))
-
-/*****************************************************************************/
-/**
- *
- * This macro writes a value to a field in a Queue Head.
- *
- * @param dQHPtr is a pointer to the dQH element.
- * @param Id is the Field ID inside the dQH element to read.
- * @param Val is the Value to write to the field.
- *
- * @note C-style signature:
- * u32 XUsbPs_WritedQH(u32 dQHPtr, u32 Id, u32 Val)
- *
- ******************************************************************************/
-#define XUsbPs_WritedQH(dQHPtr, Id, Val) \
- (*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val))
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XUSBPS_ENDPOINT_H */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/80/d1f4a1555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/80/d1f4a1555243001d18b399c1eb9b3628
deleted file mode 100644
index d986349..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/80/d1f4a1555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,240 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm_gcc.h
-*
-* This header file contains macros for using inline assembler code. It is
-* written specifically for the GNU compiler.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/21/14 First release
-* 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors
-* 7.2 asa 04/03/20 Renamed the str macro to strw.
-* 7.2 dp 04/30/20 Added clobber "cc" to mtcpsr for aarch32 processors
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.00 pkp 02/20/14 First release
-* 6.2 mus 01/27/17 Updated to support IAR compiler
-*
-*
-******************************************************************************/
-#ifndef XIL_CACHE_H
-#define XIL_CACHE_H
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *@cond nocomments
- */
-
-#if defined (__GNUC__)
-#define asm_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
- XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param))
-
-#define asm_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
- XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param))
-
-#define asm_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
- XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param))
-
-#define asm_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
- XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param))
-#elif defined (__ICCARM__)
-#define asm_inval_dc_line_mva_poc(param) __asm volatile("mcr " \
- XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param))
-
-#define asm_clean_inval_dc_line_sw(param) __asm volatile("mcr " \
- XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param))
-
-#define asm_clean_inval_dc_line_mva_poc(param) __asm volatile("mcr " \
- XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param))
-
-#define asm_inval_ic_line_mva_pou(param) __asm volatile("mcr " \
- XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param))
-#endif
-
-/**
- *@endcond
- */
-
-void Xil_DCacheEnable(void);
-void Xil_DCacheDisable(void);
-void Xil_DCacheInvalidate(void);
-void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
-void Xil_DCacheFlush(void);
-void Xil_DCacheFlushRange(INTPTR adr, u32 len);
-void Xil_DCacheInvalidateLine(INTPTR adr);
-void Xil_DCacheFlushLine(INTPTR adr);
-void Xil_DCacheStoreLine(INTPTR adr);
-
-void Xil_ICacheEnable(void);
-void Xil_ICacheDisable(void);
-void Xil_ICacheInvalidate(void);
-void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
-void Xil_ICacheInvalidateLine(INTPTR adr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-* @} End of "addtogroup r5_cache_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/81/00aacd535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/81/00aacd535243001d18b399c1eb9b3628
deleted file mode 100644
index edf6684..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/81/00aacd535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,558 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpm_counter.h
-*
-* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions
-*
-* Cortex A9 event counter functions can be utilized to configure and control
-* the Cortex-A9 performance monitor events.
-*
-* Cortex-A9 performance monitor has six event counters which can be used to
-* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines
-* configurations XPM_CNTRCFGx which can be used to program the event counters
-* to count a set of events.
-*
-* @note
-* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
-* being used for time keeping.
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-*
-******************************************************************************/
-
-/**
-*@cond nocomments
-*/
-
-#ifndef XPMCOUNTER_H /* prevent circular inclusions */
-#define XPMCOUNTER_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/************************** Constant Definitions ****************************/
-
-/* Number of performance counters */
-#define XPM_CTRCOUNT 6U
-
-/* The following constants define the Cortex-A9 Performance Monitor Events */
-
-/*
- * Software increment. The register is incremented only on writes to the
- * Software Increment Register
- */
-#define XPM_EVENT_SOFTINCR 0x00U
-
-/*
- * Instruction fetch that causes a refill at (at least) the lowest level(s) of
- * instruction or unified cache. Includes the speculative linefills in the
- * count
- */
-#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
-
-/*
- * Instruction fetch that causes a TLB refill at (at least) the lowest level of
- * TLB. Includes the speculative requests in the count
- */
-#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
-
-/*
- * Data read or write operation that causes a refill at (at least) the lowest
- * level(s)of data or unified cache. Counts the number of allocations performed
- * in the Data Cache due to a read or a write
- */
-#define XPM_EVENT_DATA_CACHEREFILL 0x03U
-
-/*
- * Data read or write operation that causes a cache access at (at least) the
- * lowest level(s) of data or unified cache. This includes speculative reads
- */
-#define XPM_EVENT_DATA_CACHEACCESS 0x04U
-
-/*
- * Data read or write operation that causes a TLB refill at (at least) the
- * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
- * CP15 Cache operation by MVA and CP15 VA to PA operations
- */
-#define XPM_EVENT_DATA_TLBREFILL 0x05U
-
-/*
- * Data read architecturally executed. Counts the number of data read
- * instructions accepted by the Load Store Unit. This includes counting the
- * speculative and aborted LDR/LDM, as well as the reads due to the SWP
- * instructions
- */
-#define XPM_EVENT_DATA_READS 0x06U
-
-/*
- * Data write architecturally executed. Counts the number of data write
- * instructions accepted by the Load Store Unit. This includes counting the
- * speculative and aborted STR/STM, as well as the writes due to the SWP
- * instructions
- */
-#define XPM_EVENT_DATA_WRITE 0x07U
-
-/* Exception taken. Counts the number of exceptions architecturally taken.*/
-#define XPM_EVENT_EXCEPTION 0x09U
-
-/* Exception return architecturally executed.*/
-#define XPM_EVENT_EXCEPRETURN 0x0AU
-
-/*
- * Change to ContextID retired. Counts the number of instructions
- * architecturally executed writing into the ContextID Register
- */
-#define XPM_EVENT_CHANGECONTEXT 0x0BU
-
-/*
- * Software change of PC, except by an exception, architecturally executed.
- * Count the number of PC changes architecturally executed, excluding the PC
- * changes due to taken exceptions
- */
-#define XPM_EVENT_SW_CHANGEPC 0x0CU
-
-/*
- * Immediate branch architecturally executed (taken or not taken). This includes
- * the branches which are flushed due to a previous load/store which aborts
- * late
- */
-#define XPM_EVENT_IMMEDBRANCH 0x0DU
-
-/*
- * Unaligned access architecturally executed. Counts the number of aborted
- * unaligned accessed architecturally executed, and the number of not-aborted
- * unaligned accesses, including the speculative ones
- */
-#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
-
-/*
- * Branch mispredicted/not predicted. Counts the number of mispredicted or
- * not-predicted branches executed. This includes the branches which are flushed
- * due to a previous load/store which aborts late
- */
-#define XPM_EVENT_BRANCHMISS 0x10U
-
-/*
- * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
- * event is not exported on the PMUEVENT bus
- */
-#define XPM_EVENT_CLOCKCYCLES 0x11U
-
-/*
- * Branches or other change in program flow that could have been predicted by
- * the branch prediction resources of the processor. This includes the branches
- * which are flushed due to a previous load/store which aborts late
- */
-#define XPM_EVENT_BRANCHPREDICT 0x12U
-
-/*
- * Java bytecode execute. Counts the number of Java bytecodes being decoded,
- * including speculative ones
- */
-#define XPM_EVENT_JAVABYTECODE 0x40U
-
-/*
- * Software Java bytecode executed. Counts the number of software java bytecodes
- * being decoded, including speculative ones
- */
-#define XPM_EVENT_SWJAVABYTECODE 0x41U
-
-/*
- * Jazelle backward branches executed. Counts the number of Jazelle taken
- * branches being executed. This includes the branches which are flushed due
- * to a previous load/store which aborts late
- */
-#define XPM_EVENT_JAVABACKBRANCH 0x42U
-
-/*
- * Coherent linefill miss Counts the number of coherent linefill requests
- * performed by the Cortex-A9 processor which also miss in all the other
- * Cortex-A9 processors, meaning that the request is sent to the external
- * memory
- */
-#define XPM_EVENT_COHERLINEMISS 0x50U
-
-/*
- * Coherent linefill hit. Counts the number of coherent linefill requests
- * performed by the Cortex-A9 processor which hit in another Cortex-A9
- * processor, meaning that the linefill data is fetched directly from the
- * relevant Cortex-A9 cache
- */
-#define XPM_EVENT_COHERLINEHIT 0x51U
-
-/*
- * Instruction cache dependent stall cycles. Counts the number of cycles where
- * the processor is ready to accept new instructions, but does not receive any
- * due to the instruction side not being able to provide any and the
- * instruction cache is currently performing at least one linefill
- */
-#define XPM_EVENT_INSTRSTALL 0x60U
-
-/*
- * Data cache dependent stall cycles. Counts the number of cycles where the core
- * has some instructions that it cannot issue to any pipeline, and the Load
- * Store unit has at least one pending linefill request, and no pending
- */
-#define XPM_EVENT_DATASTALL 0x61U
-
-/*
- * Main TLB miss stall cycles. Counts the number of cycles where the processor
- * is stalled waiting for the completion of translation table walks from the
- * main TLB. The processor stalls can be due to the instruction side not being
- * able to provide the instructions, or to the data side not being able to
- * provide the necessary data, due to them waiting for the main TLB translation
- * table walk to complete
- */
-#define XPM_EVENT_MAINTLBSTALL 0x62U
-
-/*
- * Counts the number of STREX instructions architecturally executed and
- * passed
- */
-#define XPM_EVENT_STREXPASS 0x63U
-
-/*
- * Counts the number of STREX instructions architecturally executed and
- * failed
- */
-#define XPM_EVENT_STREXFAIL 0x64U
-
-/*
- * Data eviction. Counts the number of eviction requests due to a linefill in
- * the data cache
- */
-#define XPM_EVENT_DATAEVICT 0x65U
-
-/*
- * Counts the number of cycles where the issue stage does not dispatch any
- * instruction because it is empty or cannot dispatch any instructions
- */
-#define XPM_EVENT_NODISPATCH 0x66U
-
-/*
- * Counts the number of cycles where the issue stage is empty
- */
-#define XPM_EVENT_ISSUEEMPTY 0x67U
-
-/*
- * Counts the number of instructions going through the Register Renaming stage.
- * This number is an approximate number of the total number of instructions
- * speculatively executed, and even more approximate of the total number of
- * instructions architecturally executed. The approximation depends mainly on
- * the branch misprediction rate.
- * The renaming stage can handle two instructions in the same cycle so the event
- * is two bits long:
- * - b00 no instructions renamed
- * - b01 one instruction renamed
- * - b10 two instructions renamed
- */
-#define XPM_EVENT_INSTRRENAME 0x68U
-
-/*
- * Counts the number of procedure returns whose condition codes do not fail,
- * excluding all returns from exception. This count includes procedure returns
- * which are flushed due to a previous load/store which aborts late.
- * Only the following instructions are reported:
- * - BX R14
- * - MOV PC LR
- * - POP {..,pc}
- * - LDR pc,[sp],#offset
- * The following instructions are not reported:
- * - LDMIA R9!,{..,PC} (ThumbEE state only)
- * - LDR PC,[R9],#offset (ThumbEE state only)
- * - BX R0 (Rm != R14)
- * - MOV PC,R0 (Rm != R14)
- * - LDM SP,{...,PC} (writeback not specified)
- * - LDR PC,[SP,#offset] (wrong addressing mode)
- */
-#define XPM_EVENT_PREDICTFUNCRET 0x6EU
-
-/*
- * Counts the number of instructions being executed in the main execution
- * pipeline of the processor, the multiply pipeline and arithmetic logic unit
- * pipeline. The counted instructions are still speculative
- */
-#define XPM_EVENT_MAINEXEC 0x70U
-
-/*
- * Counts the number of instructions being executed in the processor second
- * execution pipeline (ALU). The counted instructions are still speculative
- */
-#define XPM_EVENT_SECEXEC 0x71U
-
-/*
- * Counts the number of instructions being executed in the Load/Store unit. The
- * counted instructions are still speculative
- */
-#define XPM_EVENT_LDRSTR 0x72U
-
-/*
- * Counts the number of Floating-point instructions going through the Register
- * Rename stage. Instructions are still speculative in this stage.
- *Two floating-point instructions can be renamed in the same cycle so the event
- * is two bitslong:
- *0b00 no floating-point instruction renamed
- *0b01 one floating-point instruction renamed
- *0b10 two floating-point instructions renamed
- */
-#define XPM_EVENT_FLOATRENAME 0x73U
-
-/*
- * Counts the number of Neon instructions going through the Register Rename
- * stage.Instructions are still speculative in this stage.
- * Two NEON instructions can be renamed in the same cycle so the event is two
- * bits long:
- *0b00 no NEON instruction renamed
- *0b01 one NEON instruction renamed
- *0b10 two NEON instructions renamed
- */
-#define XPM_EVENT_NEONRENAME 0x74U
-
-/*
- * Counts the number of cycles where the processor is stalled because PLD slots
- * are all full
- */
-#define XPM_EVENT_PLDSTALL 0x80U
-
-/*
- * Counts the number of cycles when the processor is stalled and the data side
- * is stalled too because it is full and executing writes to the external
- * memory
- */
-#define XPM_EVENT_WRITESTALL 0x81U
-
-/*
- * Counts the number of stall cycles due to main TLB misses on requests issued
- * by the instruction side
- */
-#define XPM_EVENT_INSTRTLBSTALL 0x82U
-
-/*
- * Counts the number of stall cycles due to main TLB misses on requests issued
- * by the data side
- */
-#define XPM_EVENT_DATATLBSTALL 0x83U
-
-/*
- * Counts the number of stall cycles due to micro TLB misses on the instruction
- * side. This event does not include main TLB miss stall cycles that are already
- * counted in the corresponding main TLB event
- */
-#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
-
-/*
- * Counts the number of stall cycles due to micro TLB misses on the data side.
- * This event does not include main TLB miss stall cycles that are already
- * counted in the corresponding main TLB event
- */
-#define XPM_EVENT_DATA_uTLBSTALL 0x85U
-
-/*
- * Counts the number of stall cycles because of the execution of a DMB memory
- * barrier. This includes all DMB instructions being executed, even
- * speculatively
- */
-#define XPM_EVENT_DMB_STALL 0x86U
-
-/*
- * Counts the number of cycles during which the integer core clock is enabled
- */
-#define XPM_EVENT_INT_CLKEN 0x8AU
-
-/*
- * Counts the number of cycles during which the Data Engine clock is enabled
- */
-#define XPM_EVENT_DE_CLKEN 0x8BU
-
-/*
- * Counts the number of ISB instructions architecturally executed
- */
-#define XPM_EVENT_INSTRISB 0x90U
-
-/*
- * Counts the number of DSB instructions architecturally executed
- */
-#define XPM_EVENT_INSTRDSB 0x91U
-
-/*
- * Counts the number of DMB instructions speculatively executed
- */
-#define XPM_EVENT_INSTRDMB 0x92U
-
-/*
- * Counts the number of external interrupts executed by the processor
- */
-#define XPM_EVENT_EXTINT 0x93U
-
-/*
- * PLE cache line request completed
- */
-#define XPM_EVENT_PLE_LRC 0xA0U
-
-/*
- * PLE cache line request skipped
- */
-#define XPM_EVENT_PLE_LRS 0xA1U
-
-/*
- * PLE FIFO flush
- */
-#define XPM_EVENT_PLE_FLUSH 0xA2U
-
-/*
- * PLE request complete
- */
-#define XPM_EVENT_PLE_CMPL 0xA3U
-
-/*
- * PLE FIFO overflow
- */
-#define XPM_EVENT_PLE_OVFL 0xA4U
-
-/*
- * PLE request programmed
- */
-#define XPM_EVENT_PLE_PROG 0xA5U
-
-/*
- * The following constants define the configurations for Cortex-A9 Performance
- * Monitor Events. Each configuration configures the event counters for a set
- * of events.
- * -----------------------------------------------
- * Config PmCtr0... PmCtr5
- * -----------------------------------------------
- * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR,
- * XPM_EVENT_INSRFETCH_CACHEREFILL,
- * XPM_EVENT_INSTRFECT_TLBREFILL,
- * XPM_EVENT_DATA_CACHEREFILL,
- * XPM_EVENT_DATA_CACHEACCESS,
- * XPM_EVENT_DATA_TLBREFILL }
- *
- * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS,
- * XPM_EVENT_DATA_WRITE,
- * XPM_EVENT_EXCEPTION,
- * XPM_EVENT_EXCEPRETURN,
- * XPM_EVENT_CHANGECONTEXT,
- * XPM_EVENT_SW_CHANGEPC }
- *
- * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH,
- * XPM_EVENT_UNALIGNEDACCESS,
- * XPM_EVENT_BRANCHMISS,
- * XPM_EVENT_CLOCKCYCLES,
- * XPM_EVENT_BRANCHPREDICT,
- * XPM_EVENT_JAVABYTECODE }
- *
- * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE,
- * XPM_EVENT_JAVABACKBRANCH,
- * XPM_EVENT_COHERLINEMISS,
- * XPM_EVENT_COHERLINEHIT,
- * XPM_EVENT_INSTRSTALL,
- * XPM_EVENT_DATASTALL }
- *
- * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL,
- * XPM_EVENT_STREXPASS,
- * XPM_EVENT_STREXFAIL,
- * XPM_EVENT_DATAEVICT,
- * XPM_EVENT_NODISPATCH,
- * XPM_EVENT_ISSUEEMPTY }
- *
- * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME,
- * XPM_EVENT_PREDICTFUNCRET,
- * XPM_EVENT_MAINEXEC,
- * XPM_EVENT_SECEXEC,
- * XPM_EVENT_LDRSTR,
- * XPM_EVENT_FLOATRENAME }
- *
- * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME,
- * XPM_EVENT_PLDSTALL,
- * XPM_EVENT_WRITESTALL,
- * XPM_EVENT_INSTRTLBSTALL,
- * XPM_EVENT_DATATLBSTALL,
- * XPM_EVENT_INSTR_uTLBSTALL }
- *
- * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL,
- * XPM_EVENT_DMB_STALL,
- * XPM_EVENT_INT_CLKEN,
- * XPM_EVENT_DE_CLKEN,
- * XPM_EVENT_INSTRISB,
- * XPM_EVENT_INSTRDSB }
- *
- * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB,
- * XPM_EVENT_EXTINT,
- * XPM_EVENT_PLE_LRC,
- * XPM_EVENT_PLE_LRS,
- * XPM_EVENT_PLE_FLUSH,
- * XPM_EVENT_PLE_CMPL }
- *
- * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL,
- * XPM_EVENT_PLE_PROG,
- * XPM_EVENT_PLE_LRC,
- * XPM_EVENT_PLE_LRS,
- * XPM_EVENT_PLE_FLUSH,
- * XPM_EVENT_PLE_CMPL }
- *
- * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL,
- * XPM_EVENT_INSRFETCH_CACHEREFILL,
- * XPM_EVENT_INSTRFECT_TLBREFILL,
- * XPM_EVENT_DATA_CACHEREFILL,
- * XPM_EVENT_DATA_CACHEACCESS,
- * XPM_EVENT_DATA_TLBREFILL }
- */
-#define XPM_CNTRCFG1 0
-#define XPM_CNTRCFG2 1
-#define XPM_CNTRCFG3 2
-#define XPM_CNTRCFG4 3
-#define XPM_CNTRCFG5 4
-#define XPM_CNTRCFG6 5
-#define XPM_CNTRCFG7 6
-#define XPM_CNTRCFG8 7
-#define XPM_CNTRCFG9 8
-#define XPM_CNTRCFG10 9
-#define XPM_CNTRCFG11 10
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/**
-*@endcond
-*/
-
-/************************** Function Prototypes *****************************/
-
-/* Interface functions to access performance counters from abstraction layer */
-void Xpm_SetEvents(s32 PmcrCfg);
-void Xpm_GetEventCounters(u32 *PmCtrValue);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-* @} End of "addtogroup a9_event_counter_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/81/619783555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/81/619783555243001d18b399c1eb9b3628
deleted file mode 100644
index 2c32839..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/81/619783555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,92 +0,0 @@
-/*******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-*******************************************************************************/
-
-
-#ifndef __XLPD_XPPU_SINK_H__
-#define __XLPD_XPPU_SINK_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *@cond nocomments
- */
-
-/**
- * XlpdXppuSink Base Address
- */
-#define XLPD_XPPU_SINK_BASEADDR 0xFF9C0000UL
-
-/**
- * Register: XlpdXppuSinkErrSts
- */
-#define XLPD_XPPU_SINK_ERR_STS ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF00UL )
-#define XLPD_XPPU_SINK_ERR_STS_RSTVAL 0x00000000UL
-
-#define XLPD_XPPU_SINK_ERR_STS_RDWR_SHIFT 31UL
-#define XLPD_XPPU_SINK_ERR_STS_RDWR_WIDTH 1UL
-#define XLPD_XPPU_SINK_ERR_STS_RDWR_MASK 0x80000000UL
-#define XLPD_XPPU_SINK_ERR_STS_RDWR_DEFVAL 0x0UL
-
-#define XLPD_XPPU_SINK_ERR_STS_ADDR_SHIFT 0UL
-#define XLPD_XPPU_SINK_ERR_STS_ADDR_WIDTH 12UL
-#define XLPD_XPPU_SINK_ERR_STS_ADDR_MASK 0x00000fffUL
-#define XLPD_XPPU_SINK_ERR_STS_ADDR_DEFVAL 0x0UL
-
-/**
- * Register: XlpdXppuSinkIsr
- */
-#define XLPD_XPPU_SINK_ISR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF10UL )
-#define XLPD_XPPU_SINK_ISR_RSTVAL 0x00000000UL
-
-#define XLPD_XPPU_SINK_ISRADDRDECDERR_SHIFT 0UL
-#define XLPD_XPPU_SINK_ISRADDRDECDERR_WIDTH 1UL
-#define XLPD_XPPU_SINK_ISRADDRDECDERR_MASK 0x00000001UL
-#define XLPD_XPPU_SINK_ISRADDRDECDERR_DEFVAL 0x0UL
-
-/**
- * Register: XlpdXppuSinkImr
- */
-#define XLPD_XPPU_SINK_IMR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF14UL )
-#define XLPD_XPPU_SINK_IMR_RSTVAL 0x00000001UL
-
-#define XLPD_XPPU_SINK_IMRADDRDECDERR_SHIFT 0UL
-#define XLPD_XPPU_SINK_IMRADDRDECDERR_WIDTH 1UL
-#define XLPD_XPPU_SINK_IMRADDRDECDERR_MASK 0x00000001UL
-#define XLPD_XPPU_SINK_IMRADDRDECDERR_DEFVAL 0x1UL
-
-/**
- * Register: XlpdXppuSinkIer
- */
-#define XLPD_XPPU_SINK_IER ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF18UL )
-#define XLPD_XPPU_SINK_IER_RSTVAL 0x00000000UL
-
-#define XLPD_XPPU_SINK_IERADDRDECDERR_SHIFT 0UL
-#define XLPD_XPPU_SINK_IERADDRDECDERR_WIDTH 1UL
-#define XLPD_XPPU_SINK_IERADDRDECDERR_MASK 0x00000001UL
-#define XLPD_XPPU_SINK_IERADDRDECDERR_DEFVAL 0x0UL
-
-/**
- * Register: XlpdXppuSinkIdr
- */
-#define XLPD_XPPU_SINK_IDR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF1CUL )
-#define XLPD_XPPU_SINK_IDR_RSTVAL 0x00000000UL
-
-#define XLPD_XPPU_SINK_IDRADDRDECDERR_SHIFT 0UL
-#define XLPD_XPPU_SINK_IDRADDRDECDERR_WIDTH 1UL
-#define XLPD_XPPU_SINK_IDRADDRDECDERR_MASK 0x00000001UL
-#define XLPD_XPPU_SINK_IDRADDRDECDERR_DEFVAL 0x0UL
-
-/**
- *@endcond
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XLPD_XPPU_SINK_H__ */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/81/c0f78e575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/81/c0f78e575243001d18b399c1eb9b3628
deleted file mode 100644
index d1bd537..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/81/c0f78e575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,320 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xparameters_ps.h
-*
-* This file contains the address definitions for the hard peripherals
-* attached to the ARM Cortex A9 core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 1.00a ecm/sdm 02/01/10 Initial version
-* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
-* driver tcl
-* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
-* 6.6 srm 10/18/17 Added ARMA9 macro to identify CortexA9
-*
-*
-* The boot.S file contains a minimal set of code for transferring control from the processor
-* reset location of the processor to the start of the application.
-* The boot code performs minimum configuration which is required for an
-* application to run starting from reset state of the processor. Below is a
-* sequence illustrating what all configuration is performed before control
-* reaches to main function.
-*
-* 1. Program vector table base for exception handling
-* 2. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine,
-* abort, system)
-* 3. Disable instruction cache, data cache and MPU
-* 4. Invalidate instruction and data cache
-* 5. Configure MPU with short descriptor translation table format and program
-* base address of translation table
-* 6. Enable data cache, instruction cache and MPU
-* 7. Enable Floating point unit
-* 8. Transfer control to _start which clears BSS sections and jumping to main
-* application
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00 pkp 02/10/14 Initial version
-* 5.04 pkp 09/11/15 Disabled ACTLR.DBWR bit to avoid potential R5 deadlock
-* for errata 780125
-* 5.04 pkp 02/04/16 Enabled the fault log for lock-step mode
-* 5.04 pkp 02/25/16 Initialized the banked registers for various modes,
-* initialized floating point registers and enabled the
-* cache ECC check before enabling the fault log for
-* lock step mode
-* 5.04 pkp 03/24/16 Reset the dbg_lpd_reset before enabling the fault log
-* to avoid intervention for lock-step mode
-* 5.05 pkp 04/11/16 Enable the comparators for non-JTAG boot mode for
-* lock-step to avoid putting debug logic to reset
-* 6.02 pkp 02/13/17 Added support for hard float
-* 6.6 mus 02/23/17 Enable/Disable the debug logic in non-JTAG boot mode(when
-* processor is in lockstep configuration), based
-* on the mld parameter "lockstep_mode_debug".
-* 6.8 mus 09/20/18 Clear VINITHI field in RPU_0_CFG/RPU_1_CFG
-* registers to initialize CortexR5 core with LOVEC
-* on reset. It fixes CR#1010656.
-* 7.1 mus 03/27/19 Skip reading/writing to the RPU address space registers,
-* in case if processor is nonsecure and RPU
-* address space is secure. CR#1015725.
-* 7.2 mus 10/11/19 Resetting the r5_0 and r5_1 debug logic is sufficient
-* to avoid intervention for lock-step mode. So, removed
-* code which resets dbg_lpd_reset, to unblock debugger
-* access to LPD. Fix for CR#1027983.
-*
-*
-******************************************************************************/
-
-#include "xparameters.h"
-
-
-.global _prestart
-.global _boot
-.global __stack
-.global __irq_stack
-.global __supervisor_stack
-.global __abort_stack
-.global __fiq_stack
-.global __undef_stack
-.global _vector_table
-
-
-/* Stack Pointer locations for boot code */
-.set Undef_stack, __undef_stack
-.set FIQ_stack, __fiq_stack
-.set Abort_stack, __abort_stack
-.set SPV_stack, __supervisor_stack
-.set IRQ_stack, __irq_stack
-.set SYS_stack, __stack
-
-.set vector_base, _vector_table
-
-.set RPU_GLBL_CNTL, 0xFF9A0000
-.set RPU_ERR_INJ, 0xFF9A0020
-.set RPU_0_CFG, 0xFF9A0100
-.set RPU_1_CFG, 0xFF9A0200
-#if defined(versal)
-.set RST_LPD_DBG, 0xFF5E0338
-.set BOOT_MODE_USER, 0xF1260200
-#else
-.set RST_LPD_DBG, 0xFF5E0240
-.set BOOT_MODE_USER, 0xFF5E0200
-#endif
-.set fault_log_enable, 0x101
-
-/*
- * 0th bit of PROCESSOR_ACCESS_VALUE macro signifies trustzone
- * setting for RPU address space
- */
-#define RPU_TZ_MASK 0x1
-
-.section .boot,"axS"
-
-
-/* this initializes the various processor modes */
-
-_prestart:
-_boot:
-
-OKToRun:
-
-/* Initialize processor registers to 0 */
- mov r0,#0
- mov r1,#0
- mov r2,#0
- mov r3,#0
- mov r4,#0
- mov r5,#0
- mov r6,#0
- mov r7,#0
- mov r8,#0
- mov r9,#0
- mov r10,#0
- mov r11,#0
- mov r12,#0
-
-/* Initialize stack pointer and banked registers for various mode */
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the irq stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x12 /* IRQ mode */
- msr cpsr, r2
- ldr r13,=IRQ_stack /* IRQ stack pointer */
- mov r14,#0
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the supervisor stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x13 /* supervisor mode */
- msr cpsr, r2
- ldr r13,=SPV_stack /* Supervisor stack pointer */
- mov r14,#0
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the Abort stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x17 /* Abort mode */
- msr cpsr, r2
- ldr r13,=Abort_stack /* Abort stack pointer */
- mov r14,#0
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the FIQ stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x11 /* FIQ mode */
- msr cpsr, r2
- mov r8, #0
- mov r9, #0
- mov r10, #0
- mov r11, #0
- mov r12, #0
- ldr r13,=FIQ_stack /* FIQ stack pointer */
- mov r14,#0
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the Undefine stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x1b /* Undefine mode */
- msr cpsr, r2
- ldr r13,=Undef_stack /* Undefine stack pointer */
- mov r14,#0
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the system stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x1F /* SYS mode */
- msr cpsr, r2
- ldr r13,=SYS_stack /* SYS stack pointer */
- mov r14,#0
-
-/*
- * Enable access to VFP by enabling access to Coprocessors 10 and 11.
- * Enables Full Access i.e. in both privileged and non privileged modes
- */
- mrc p15, 0, r0, c1, c0, 2 /* Read Coprocessor Access Control Register (CPACR) */
- orr r0, r0, #(0xF << 20) /* Enable access to CP 10 & 11 */
- mcr p15, 0, r0, c1, c0, 2 /* Write Coprocessor Access Control Register (CPACR) */
- isb
-
-/* enable fpu access */
- vmrs r3, FPEXC
- orr r1, r3, #(1<<30)
- vmsr FPEXC, r1
-
-/* clear the floating point register*/
- mov r1,#0
- vmov d0,r1,r1
- vmov d1,r1,r1
- vmov d2,r1,r1
- vmov d3,r1,r1
- vmov d4,r1,r1
- vmov d5,r1,r1
- vmov d6,r1,r1
- vmov d7,r1,r1
- vmov d8,r1,r1
- vmov d9,r1,r1
- vmov d10,r1,r1
- vmov d11,r1,r1
- vmov d12,r1,r1
- vmov d13,r1,r1
- vmov d14,r1,r1
- vmov d15,r1,r1
-
-#ifdef __SOFTFP__
-/* Disable the FPU if SOFTFP is defined*/
- vmsr FPEXC,r3
-#endif
-
-/* Disable MPU and caches */
- mrc p15, 0, r0, c1, c0, 0 /* Read CP15 Control Register*/
- bic r0, r0, #0x05 /* Disable MPU (M bit) and data cache (C bit) */
- bic r0, r0, #0x1000 /* Disable instruction cache (I bit) */
- dsb /* Ensure all previous loads/stores have completed */
- mcr p15, 0, r0, c1, c0, 0 /* Write CP15 Control Register */
- isb /* Ensure subsequent insts execute wrt new MPU settings */
-
-/* Disable Branch prediction, TCM ECC checks */
- mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR */
- orr r0, r0, #(0x1 << 17) /* Enable RSDIS bit 17 to disable the return stack */
- orr r0, r0, #(0x1 << 16) /* Clear BP bit 15 and set BP bit 16:*/
- bic r0, r0, #(0x1 << 15) /* Branch always not taken and history table updates disabled*/
- orr r0, r0, #(0x1 << 27) /* Enable B1TCM ECC check */
- orr r0, r0, #(0x1 << 26) /* Enable B0TCM ECC check */
- orr r0, r0, #(0x1 << 25) /* Enable ATCM ECC check */
- bic r0, r0, #(0x1 << 5) /* Generate abort on parity errors, with [5:3]=b 000*/
- bic r0, r0, #(0x1 << 4)
- bic r0, r0, #(0x1 << 3)
- mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/
- dsb /* Complete all outstanding explicit memory operations*/
-
-/* Invalidate caches */
- mov r0,#0 /* r0 = 0 */
- dsb
- mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
- mcr p15, 0, r0, c15, c5, 0 /* Invalidate entire data cache*/
- isb
-#if LOCKSTEP_MODE_DEBUG == 0 && (PROCESSOR_ACCESS_VALUE & RPU_TZ_MASK)
-/* enable fault log for lock step */
- ldr r0,=RPU_GLBL_CNTL
- ldr r1, [r0]
- ands r1, r1, #0x8
-/* branch to initialization if split mode*/
- bne init
-/* check for boot mode if in lock step, branch to init if JTAG boot mode*/
- ldr r0,=BOOT_MODE_USER
- ldr r1, [r0]
- ands r1, r1, #0xF
- beq init
-/* reset the debug logic */
- ldr r0,=RST_LPD_DBG
- ldr r1, [r0]
- orr r1, r1, #(0x1 << 4)
- orr r1, r1, #(0x1 << 5)
- str r1, [r0]
-/* enable fault log */
- ldr r0,=RPU_ERR_INJ
- ldr r1,=fault_log_enable
- ldr r2, [r0]
- orr r2, r2, r1
- str r2, [r0]
- nop
- nop
-#endif
-
-init:
- bl Init_MPU /* Initialize MPU */
-
-/* Enable Branch prediction */
- mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/
- bic r0, r0, #(0x1 << 17) /* Clear RSDIS bit 17 to enable return stack*/
- bic r0, r0, #(0x1 << 16) /* Clear BP bit 15 and BP bit 16:*/
- bic r0, r0, #(0x1 << 15) /* Normal operation, BP is taken from the global history table.*/
- orr r0, r0, #(0x1 << 14) /* Disable DBWR for errata 780125 */
- mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/
-
-/* Enable icahce and dcache */
- mrc p15,0,r1,c1,c0,0
- ldr r0, =0x1005
- orr r1,r1,r0
- dsb
- mcr p15,0,r1,c1,c0,0 /* Enable cache */
- isb /* isb flush prefetch buffer */
-
-/* Warning message to be removed after 2016.1 */
-/* USEAMP was introduced in 2015.4 with ZynqMP and caused confusion with USE_AMP */
-#ifdef USEAMP
-#warning "-DUSEAMP=1 is deprecated, use -DVEC_TABLE_IN_OCM instead to set vector table in OCM"
-#endif
-
-/* Set vector table in TCM/LOVEC */
-#ifndef VEC_TABLE_IN_OCM
- mrc p15, 0, r0, c1, c0, 0
- mvn r1, #0x2000
- and r0, r0, r1
- mcr p15, 0, r0, c1, c0, 0
-
-/* Check if processor is having access to RPU address space */
-#if (PROCESSOR_ACCESS_VALUE & RPU_TZ_MASK)
-/* Clear VINITHI to enable LOVEC on reset */
-#if XPAR_CPU_ID == 0
- ldr r0, =RPU_0_CFG
-#else
- ldr r0, =RPU_1_CFG
-#endif
- ldr r1, [r0]
- bic r1, r1, #(0x1 << 2)
- str r1, [r0]
-#endif
-#endif
-/* enable asynchronous abort exception */
- mrs r0, cpsr
- bic r0, r0, #0x100
- msr cpsr_xsf, r0
-
- b _startup /* jump to C startup code */
-
-
-.Ldone: b .Ldone /* Paranoia: we should never get here */
-
-
-.end
-/**
-* @} End of "addtogroup r5_boot_code".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/82/1118c5565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/82/1118c5565243001d18b399c1eb9b3628
deleted file mode 100644
index 46c83f2..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/82/1118c5565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,18 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-// based on "ARM Profiling Implementation" from Sourcery G++ Lite for ARM EABI
-
-.globl __gnu_mcount_nc
-.type __gnu_mcount_nc, %function
-
-__gnu_mcount_nc:
- push {r0, r1, r2, r3, lr}
- subs r1, lr, #0 /* callee - current lr */
- ldr r0, [sp, #20] /* caller - at the top of the stack */
- bl mcount /* when __gnu_mcount_nc is called */
- pop {r0, r1, r2, r3, ip, lr}
- bx ip
-
- .end __gnu_mcount_nc
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/82/3099ef585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/82/3099ef585243001d18b399c1eb9b3628
deleted file mode 100644
index b828612..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/82/3099ef585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1534 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.c
-*
-* Contains required functions for the ARM cache functionality.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 01/29/10 First release
-* 1.00a ecm 06/24/10 Moved the L1 and L2 specific function prototypes
-* to xil_cache_mach.h to give access to sophisticated users
-* 3.02a sdm 04/07/11 Updated Flush/InvalidateRange APIs to flush/invalidate
-* L1 and L2 caches in a single loop and used dsb, L2 sync
-* at the end of the loop.
-* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
-* APIs.
-* 3.07a asa 07/16/12 Corrected the L1 and L2 cache invalidation order.
-* 3.07a sgd 09/18/12 Corrected the L2 cache enable and disable sequence.
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-* 3.10a asa 05/13/13 Modified cache disable APIs. The L2 cache disable
-* operation was being done with L1 Data cache disabled. This is
-* fixed so that L2 cache disable operation happens independent of
-* L1 cache disable operation. This fixes CR #706464.
-* Changes are done to do a L2 cache sync (poll reg7_?cache_?sync).
-* This is done to fix the CR #700542.
-* 3.11a asa 09/23/13 Modified the Xil_DCacheFlushRange and
-* Xil_DCacheInvalidateRange to fix potential issues. Fixed other
-* relevant cache APIs to disable and enable back the interrupts.
-* This fixes CR #663885.
-* 3.11a asa 09/28/13 Made changes for L2 cache sync operation. It is found
-* out that for L2 cache flush/clean/invalidation by cache lines
-* does not need a cache sync as these are atomic nature. Similarly
-* figured out that for complete L2 cache flush/invalidation by way
-* we need to wait for some more time in a loop till the status
-* shows that the cache operation is completed.
-* 4.00 pkp 24/01/14 Modified Xil_DCacheInvalidateRange to fix the bug. Few
-* cache lines were missed to invalidate when unaligned address
-* invalidation was accommodated. That fixes CR #766768.
-* Also in Xil_L1DCacheInvalidate, while invalidating all L1D cache
-* stack memory which contains return address was invalidated. So
-* stack memory was flushed first and then L1D cache is invalidated.
-* This is done to fix CR #763829
-* 4.01 asa 05/09/14 Made changes in cortexa9/xil_cache.c to fix CR# 798230.
-* 4.02 pkp 06/27/14 Added notes to Xil_L1DCacheInvalidateRange function for
-* explanation of CR#785243
-* 5.00 kvn 12/15/14 Xil_L2CacheInvalidate was modified to fix CR# 838835. L2 Cache
-* has stack memory which has return address. Before invalidating
-* cache, stack memory was flushed first and L2 Cache is invalidated.
-* 5.01 pkp 05/12/15 Xil_DCacheInvalidateRange and Xil_DCacheFlushRange is modified
-* to remove unnecessary dsb in the APIs. Instead of using dsb
-* for L2 Cache, L2CacheSync has been used for each L2 cache line
-* and single dsb has been used for L1 cache. Also L2CacheSync is
-* added into Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate
-* and Xil_L2CacheInvalidate APIs are modified to flush the complete
-* stack instead of just System Stack
-* 5.03 pkp 10/07/15 L2 Cache functionalities are avoided for the OpenAMP slave
-* application(when USE_AMP flag is defined for BSP) as master CPU
-* would be utilizing L2 cache for its operation
-* 6.6 mus 12/07/17 Errata 753970 is not applicable for the PL130 cache controller
-* version r0p2, which is present in zynq. So,removed the handling
-* related to same.It fixes CR#989132.
-* 6.6 asa 16/01/18 Changes made in Xil_L1DCacheInvalidate and Xil_L2CacheInvalidate
-* routines to ensure the stack data flushed only when the respective
-* caches are enabled. This fixes CR-992023.
-* 7.5 mus 01/19/21 Implement workaround for errata#588369 in Xil_DCacheFlushRange.
-* It fixes CR#1086022.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xil_cache_l.h"
-#include "xil_io.h"
-#include "xpseudo_asm.h"
-#include "xparameters.h"
-#include "xreg_cortexa9.h"
-#include "xl2cc.h"
-#include "xil_errata.h"
-#include "xil_exception.h"
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#define IRQ_FIQ_MASK 0xC0U /* Mask IRQ and FIQ interrupts in cpsr */
-
-#ifdef __GNUC__
- extern s32 _stack_end;
- extern s32 __undef_stack;
-#endif
-
-#ifndef USE_AMP
-/****************************************************************************
-*
-* Access L2 Debug Control Register.
-*
-* @param Value, value to be written to Debug Control Register.
-*
-* @return None.
-*
-****************************************************************************/
-#ifdef __GNUC__
-static inline void Xil_L2WriteDebugCtrl(u32 Value)
-#else
-static void Xil_L2WriteDebugCtrl(u32 Value)
-#endif
-{
-#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DEBUG_CTRL_OFFSET, Value);
-#else
- (void)(Value);
-#endif
-}
-
-/****************************************************************************
-*
-* Perform L2 Cache Sync Operation.
-*
-* @return None.
-*
-****************************************************************************/
-#ifdef __GNUC__
-static inline void Xil_L2CacheSync(void)
-#else
-static void Xil_L2CacheSync(void)
-#endif
-{
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0U);
-}
-#endif
-/****************************************************************************/
-/**
-* @brief Enable the Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheEnable(void)
-{
- Xil_L1DCacheEnable();
-#ifndef USE_AMP
- Xil_L2CacheEnable();
-#endif
-}
-
-/****************************************************************************/
-/**
-* @brief Disable the Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheDisable(void)
-{
-#ifndef USE_AMP
- Xil_L2CacheDisable();
-#endif
- Xil_L1DCacheDisable();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the entire Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheInvalidate(void)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-#ifndef USE_AMP
- Xil_L2CacheInvalidate();
-#endif
- Xil_L1DCacheInvalidate();
-
- mtcpsr(currmask);
-}
-
-/*****************************************************************************/
-/**
-* @brief Invalidate a Data cache line. If the byte specified by the address
-* (adr) is cached by the Data cache, the cacheline containing that
-* byte is invalidated. If the cacheline is modified (dirty), the
-* modified contents are lost and are NOT written to the system memory
-* before the line is invalidated.
-*
-* @param adr: 32bit address of the data to be flushed.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_DCacheInvalidateLine(u32 adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-#ifndef USE_AMP
- Xil_L2CacheInvalidateLine(adr);
-#endif
- Xil_L1DCacheInvalidateLine(adr);
-
- mtcpsr(currmask);
-}
-
-
-/*****************************************************************************/
-/**
-* Invalidate the Data cache for the given address range.
-* If the bytes specified by the address range are cached by the Data
-* cache, the cachelines containing those bytes are invalidated. If
-* the cachelines are modified (dirty), the modified contents are lost
-* and NOT written to the system memory before the lines are
-* invalidated.
-*
-* In this function, if start address or end address is not aligned to
-* cache-line, particular cache-line containing unaligned start or end
-* address is flush first and then invalidated the others as
-* invalidating the same unaligned cache line may result into loss of
-* data. This issue raises few possibilities.
-*
-* If the address to be invalidated is not cache-line aligned, the
-* following choices are available:
-* 1. Invalidate the cache line when required and do not bother much
-* for the side effects. Though it sounds good, it can result in
-* hard-to-debug issues. The problem is, if some other variable are
-* allocated in the same cache line and had been recently updated
-* (in cache), the invalidation would result in loss of data.
-* 2. Flush the cache line first. This will ensure that if any other
-* variable present in the same cache line and updated recently are
-* flushed out to memory. Then it can safely be invalidated. Again it
-* sounds good, but this can result in issues. For example, when the
-* invalidation happens in a typical ISR (after a DMA transfer has
-* updated the memory), then flushing the cache line means, losing
-* data that were updated recently before the ISR got invoked.
-*
-* Linux prefers the second one. To have uniform implementation
-* (across standalone and Linux), the second option is implemented.
-* This being the case, following needs to be taken care of:
-* 1. Whenever possible, the addresses must be cache line aligned.
-* Please nore that, not just start address, even the end address must
-* be cache line aligned. If that is taken care of, this will always
-* work.
-* 2. Avoid situations where invalidation has to be done after the
-* data is updated by peripheral/DMA directly into the memory. It is
-* not tough to achieve (may be a bit risky). The common use case to
-* do invalidation is when a DMA happens. Generally for such use
-* cases, buffers can be allocated first and then start the DMA. The
-* practice that needs to be followed here is, immediately after
-* buffer allocation and before starting the DMA, do the invalidation.
-* With this approach, invalidation need not to be done after the DMA
-* transfer is over.
-*
-* This is going to always work if done carefully.
-* However, the concern is, there is no guarantee that invalidate has
-* not needed to be done after DMA is complete. For example, because
-* of some reasons if the first cache line or last cache line
-* (assuming the buffer in question comprises of multiple cache lines)
-* are brought into cache (between the time it is invalidated and DMA
-* completes) because of some speculative prefetching or reading data
-* for a variable present in the same cache line, then we will have to
-* invalidate the cache after DMA is complete.
-*
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
-{
- const u32 cacheline = 32U;
- u32 end;
- u32 tempadr = adr;
- u32 tempend;
- u32 currmask;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INVLD_PA_OFFSET);
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- end = tempadr + len;
- tempend = end;
- /* Select L1 Data cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
-
- if ((tempadr & (cacheline-1U)) != 0U) {
- tempadr &= (~(cacheline - 1U));
-
- Xil_L1DCacheFlushLine(tempadr);
-#ifndef USE_AMP
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
- Xil_L2CacheFlushLine(tempadr);
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- Xil_L2CacheSync();
-#endif
- tempadr += cacheline;
- }
- if ((tempend & (cacheline-1U)) != 0U) {
- tempend &= (~(cacheline - 1U));
-
- Xil_L1DCacheFlushLine(tempend);
-#ifndef USE_AMP
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
- Xil_L2CacheFlushLine(tempend);
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- Xil_L2CacheSync();
-#endif
- }
-
- while (tempadr < tempend) {
-#ifndef USE_AMP
- /* Invalidate L2 cache line */
- *L2CCOffset = tempadr;
- Xil_L2CacheSync();
-#endif
-
- /* Invalidate L1 Data cache line */
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_dc_line_mva_poc(tempadr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
- Reg = tempadr; }
-#endif
- tempadr += cacheline;
- }
- }
-
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the entire Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheFlush(void)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- Xil_L1DCacheFlush();
-#ifndef USE_AMP
- Xil_L2CacheFlush();
-#endif
- mtcpsr(currmask);
-}
-
-
-/****************************************************************************/
-/**
-* @brief Flush a Data cache line. If the byte specified by the address (adr)
-* is cached by the Data cache, the cacheline containing that byte is
-* invalidated. If the cacheline is modified (dirty), the entire
-* contents of the cacheline are written to system memory before the
-* line is invalidated.
-*
-* @param adr: 32bit address of the data to be flushed.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_DCacheFlushLine(u32 adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- Xil_L1DCacheFlushLine(adr);
-#ifndef USE_AMP
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
-
- Xil_L2CacheFlushLine(adr);
-
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- Xil_L2CacheSync();
-#endif
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the Data cache for the given address range.
-* If the bytes specified by the address range are cached by the
-* data cache, the cachelines containing those bytes are invalidated.
-* If the cachelines are modified (dirty), they are written to the
-* system memory before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be flushed.
-* @param len: Length of the range to be flushed in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheFlushRange(INTPTR adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- u32 currmask;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr &= ~(cacheline - 1U);
-#ifndef USE_AMP
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
-#endif
- while (LocalAddr < end) {
-
- /* Flush L1 Data cache line */
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
- Reg = LocalAddr; }
-#endif
-#ifndef USE_AMP
- /* Flush L2 cache line */
- *L2CCOffset = LocalAddr;
- Xil_L2CacheSync();
-#endif
- LocalAddr += cacheline;
- }
-#ifndef USE_AMP
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
-#endif
- }
- dsb();
- mtcpsr(currmask);
-}
-/****************************************************************************/
-/**
-* @brief Store a Data cache line. If the byte specified by the address (adr)
-* is cached by the Data cache and the cacheline is modified (dirty),
-* the entire contents of the cacheline are written to system memory.
-* After the store completes, the cacheline is marked as unmodified
-* (not dirty).
-*
-* @param adr: 32bit address of the data to be stored.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_DCacheStoreLine(u32 adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- Xil_L1DCacheStoreLine(adr);
-#ifndef USE_AMP
- Xil_L2CacheStoreLine(adr);
-#endif
- mtcpsr(currmask);
-}
-
-/***************************************************************************/
-/**
-* @brief Enable the instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ICacheEnable(void)
-{
- Xil_L1ICacheEnable();
-#ifndef USE_AMP
- Xil_L2CacheEnable();
-#endif
-}
-
-/***************************************************************************/
-/**
-* @brief Disable the instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ICacheDisable(void)
-{
-#ifndef USE_AMP
- Xil_L2CacheDisable();
-#endif
- Xil_L1ICacheDisable();
-}
-
-
-/****************************************************************************/
-/**
-* @brief Invalidate the entire instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ICacheInvalidate(void)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-#ifndef USE_AMP
- Xil_L2CacheInvalidate();
-#endif
- Xil_L1ICacheInvalidate();
-
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate an instruction cache line. If the instruction specified
-* by the address is cached by the instruction cache, the cacheline
-* containing that instruction is invalidated.
-*
-* @param adr: 32bit address of the instruction to be invalidated.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_ICacheInvalidateLine(u32 adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-#ifndef USE_AMP
- Xil_L2CacheInvalidateLine(adr);
-#endif
- Xil_L1ICacheInvalidateLine(adr);
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the instruction cache for the given address range.
-* If the instructions specified by the address range are cached by
-* the instrunction cache, the cachelines containing those
-* instructions are invalidated.
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INVLD_PA_OFFSET);
-
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Select cache L0 I-cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
-
- while (LocalAddr < end) {
-#ifndef USE_AMP
- /* Invalidate L2 cache line */
- *L2CCOffset = LocalAddr;
- dsb();
-#endif
-
- /* Invalidate L1 I-cache line */
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_ic_line_mva_pou(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
- Reg = LocalAddr; }
-#endif
-
- LocalAddr += cacheline;
- }
- }
-
- /* Wait for L1 and L2 invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Enable the level 1 Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1DCacheEnable(void)
-{
- register u32 CtrlReg;
-
- /* enable caches only if they are disabled */
-#ifdef __GNUC__
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
- CtrlReg = Reg; }
-#endif
- if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) {
- return;
- }
-
- /* clean and invalidate the Data cache */
- Xil_L1DCacheInvalidate();
-
- /* enable the Data cache */
- CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/***************************************************************************/
-/**
-* @brief Disable the level 1 Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1DCacheDisable(void)
-{
- register u32 CtrlReg;
-
- /* clean and invalidate the Data cache */
- Xil_L1DCacheFlush();
-
-#ifdef __GNUC__
- /* disable the Data cache */
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
- CtrlReg = Reg; }
-#endif
-
- CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the level 1 Data cache.
-*
-* @return None.
-*
-* @note In Cortex A9, there is no cp instruction for invalidating
-* the whole D-cache. This function invalidates each line by
-* set/way.
-*
-****************************************************************************/
-void Xil_L1DCacheInvalidate(void)
-{
- register u32 CsidReg, C7Reg;
- u32 CacheSize, LineSize, NumWays;
- u32 Way, WayIndex, Set, SetIndex, NumSet;
- u32 currmask;
-
-#ifdef __GNUC__
- u32 stack_start,stack_end,stack_size;
- register u32 CtrlReg;
-#endif
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
-#ifdef __GNUC__
- stack_end = (u32)&_stack_end;
- stack_start = (u32)&__undef_stack;
- stack_size=stack_start-stack_end;
-
- /* Check for the cache status. If cache is enabled, then only
- * flush stack memory to save return address. If cache is disabled,
- * don't flush anything as it might result in flushing stale date into
- * memory which is undesirable.
- * */
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) {
- Xil_DCacheFlushRange(stack_end, stack_size);
- }
-#endif
-
- /* Select cache level 0 and D cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
-
-#ifdef __GNUC__
- CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID);
- CsidReg = Reg; }
-#endif
- /* Determine Cache Size */
- CacheSize = (CsidReg >> 13U) & 0x1FFU;
- CacheSize +=1U;
- CacheSize *=128U; /* to get number of bytes */
-
- /* Number of Ways */
- NumWays = (CsidReg & 0x3ffU) >> 3U;
- NumWays += 1U;
-
- /* Get the cacheline size, way size, index size from csidr */
- LineSize = (CsidReg & 0x07U) + 4U;
-
- NumSet = CacheSize/NumWays;
- NumSet /= (0x00000001U << LineSize);
-
- Way = 0U;
- Set = 0U;
-
- /* Invalidate all the cachelines */
- for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set;
-
- /* Invalidate by Set/Way */
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_dc_line_sw(C7Reg);
-#else
- /*mtcp(XREG_CP15_INVAL_DC_LINE_SW, C7Reg), */
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_DC_LINE_SW);
- Reg = C7Reg; }
-#endif
- Set += (0x00000001U << LineSize);
- }
- Set=0U;
- Way += 0x40000000U;
- }
-
- /* Wait for L1 invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate a level 1 Data cache line. If the byte specified by the
-* address (Addr) is cached by the Data cache, the cacheline
-* containing that byte is invalidated. If the cacheline is modified
-* (dirty), the modified contents are lost and are NOT written to
-* system memory before the line is invalidated.
-*
-* @param adr: 32bit address of the data to be invalidated.
-*
-* @return None.
-*
-* @note The bottom 5 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L1DCacheInvalidateLine(u32 adr)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
- mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU)));
-
- /* Wait for L1 invalidate to complete */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the level 1 Data cache for the given address range.
-* If the bytes specified by the address range are cached by the Data
-* cache, the cachelines containing those bytes are invalidated. If the
-* cachelines are modified (dirty), the modified contents are lost and
-* NOT written to the system memory before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1DCacheInvalidateRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Select cache L0 D-cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
-
- while (LocalAddr < end) {
-
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_dc_line_mva_poc(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
- Reg = LocalAddr; }
-#endif
- LocalAddr += cacheline;
- }
- }
-
- /* Wait for L1 invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the level 1 Data cache.
-*
-* @return None.
-*
-* @note In Cortex A9, there is no cp instruction for flushing
-* the whole D-cache. Need to flush each line.
-*
-****************************************************************************/
-void Xil_L1DCacheFlush(void)
-{
- register u32 CsidReg, C7Reg;
- u32 CacheSize, LineSize, NumWays;
- u32 Way;
- u32 WayIndex, Set, SetIndex, NumSet;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- /* Select cache level 0 and D cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
-
-#ifdef __GNUC__
- CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID);
- CsidReg = Reg; }
-#endif
-
- /* Determine Cache Size */
-
- CacheSize = (CsidReg >> 13U) & 0x1FFU;
- CacheSize +=1U;
- CacheSize *=128U; /* to get number of bytes */
-
- /* Number of Ways */
- NumWays = (CsidReg & 0x3ffU) >> 3U;
- NumWays += 1U;
-
- /* Get the cacheline size, way size, index size from csidr */
- LineSize = (CsidReg & 0x07U) + 4U;
-
- NumSet = CacheSize/NumWays;
- NumSet /= (0x00000001U << LineSize);
-
- Way = 0U;
- Set = 0U;
-
- /* Invalidate all the cachelines */
- for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set;
- /* Flush by Set/Way */
-
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_clean_inval_dc_line_sw(C7Reg);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_SW);
- Reg = C7Reg; }
-#endif
- Set += (0x00000001U << LineSize);
- }
- Set = 0U;
- Way += 0x40000000U;
- }
-
- /* Wait for L1 flush to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush a level 1 Data cache line. If the byte specified by the
-* address (adr) is cached by the Data cache, the cacheline containing
-* that byte is invalidated. If the cacheline is modified (dirty), the
-* entire contents of the cacheline are written to system memory
-* before the line is invalidated.
-*
-* @param adr: 32bit address of the data to be flushed.
-*
-* @return None.
-*
-* @note The bottom 5 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L1DCacheFlushLine(u32 adr)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
- mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU)));
-
- /* Wait for L1 flush to complete */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the level 1 Data cache for the given address range.
-* If the bytes specified by the address range are cached by the Data
-* cache, the cacheline containing those bytes are invalidated. If the
-* cachelines are modified (dirty), they are written to system memory
-* before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be flushed.
-* @param len: Length of the range to be flushed in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1DCacheFlushRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Select cache L0 D-cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
-
- while (LocalAddr < end) {
-
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
- Reg = LocalAddr; }
-#endif
- LocalAddr += cacheline;
- }
- }
-
- /* Wait for L1 flush to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Store a level 1 Data cache line. If the byte specified by the
-* address (adr) is cached by the Data cache and the cacheline is
-* modified (dirty), the entire contents of the cacheline are written
-* to system memory. After the store completes, the cacheline is
-* marked as unmodified (not dirty).
-*
-* @param adr: Address to be stored.
-*
-* @return None.
-*
-* @note The bottom 5 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L1DCacheStoreLine(u32 adr)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
- mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1FU)));
-
- /* Wait for L1 store to complete */
- dsb();
-}
-
-
-/****************************************************************************/
-/**
-* @brief Enable the level 1 instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1ICacheEnable(void)
-{
- register u32 CtrlReg;
-
- /* enable caches only if they are disabled */
-#ifdef __GNUC__
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
- CtrlReg = Reg; }
-#endif
- if ((CtrlReg & (XREG_CP15_CONTROL_I_BIT)) != 0U) {
- return;
- }
-
- /* invalidate the instruction cache */
- mtcp(XREG_CP15_INVAL_IC_POU, 0U);
-
- /* enable the instruction cache */
- CtrlReg |= (XREG_CP15_CONTROL_I_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/****************************************************************************/
-/**
-* @brief Disable level 1 the instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1ICacheDisable(void)
-{
- register u32 CtrlReg;
-
- dsb();
-
- /* invalidate the instruction cache */
- mtcp(XREG_CP15_INVAL_IC_POU, 0U);
-
- /* disable the instruction cache */
-#ifdef __GNUC__
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
- CtrlReg = Reg; }
-#endif
- CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the entire level 1 instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1ICacheInvalidate(void)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
- /* invalidate the instruction cache */
- mtcp(XREG_CP15_INVAL_IC_POU, 0U);
-
- /* Wait for L1 invalidate to complete */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate a level 1 instruction cache line. If the instruction
-* specified by the address is cached by the instruction cache, the
-* cacheline containing that instruction is invalidated.
-*
-* @param adr: 32bit address of the instruction to be invalidated.
-*
-* @return None.
-*
-* @note The bottom 5 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L1ICacheInvalidateLine(u32 adr)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
- mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1FU)));
-
- /* Wait for L1 invalidate to complete */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the level 1 instruction cache for the given address
-* range. If the instrucions specified by the address range are cached
-* by the instruction cache, the cacheline containing those bytes are
-* invalidated.
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1ICacheInvalidateRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Select cache L0 I-cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
-
- while (LocalAddr < end) {
-
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_ic_line_mva_pou(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
- Reg = LocalAddr; }
-#endif
- LocalAddr += cacheline;
- }
- }
-
- /* Wait for L1 invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-#ifndef USE_AMP
-/****************************************************************************/
-/**
-* @brief Enable the L2 cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L2CacheEnable(void)
-{
- register u32 L2CCReg;
-
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
-
- /* only enable if L2CC is currently disabled */
- if ((L2CCReg & 0x01U) == 0U) {
- /* set up the way size and latencies */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
- XPS_L2CC_AUX_CNTRL_OFFSET);
- L2CCReg &= XPS_L2CC_AUX_REG_ZERO_MASK;
- L2CCReg |= XPS_L2CC_AUX_REG_DEFAULT_MASK;
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_AUX_CNTRL_OFFSET,
- L2CCReg);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_TAG_RAM_CNTRL_OFFSET,
- XPS_L2CC_TAG_RAM_DEFAULT_MASK);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DATA_RAM_CNTRL_OFFSET,
- XPS_L2CC_DATA_RAM_DEFAULT_MASK);
-
- /* Clear the pending interrupts */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
- XPS_L2CC_ISR_OFFSET);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_IAR_OFFSET, L2CCReg);
-
- Xil_L2CacheInvalidate();
- /* Enable the L2CC */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
- XPS_L2CC_CNTRL_OFFSET);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
- (L2CCReg | (0x01U)));
-
- Xil_L2CacheSync();
- /* synchronize the processor */
- dsb();
-
- }
-}
-
-/****************************************************************************/
-/**
-* @brief Disable the L2 cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L2CacheDisable(void)
-{
- register u32 L2CCReg;
-
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
-
- if((L2CCReg & 0x1U) != 0U) {
-
- /* Clean and Invalidate L2 Cache */
- Xil_L2CacheFlush();
-
- /* Disable the L2CC */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
- (L2CCReg & (~0x01U)));
- /* Wait for the cache operations to complete */
-
- dsb();
- }
-}
-
-/*****************************************************************************/
-/**
-* @brief Invalidate the entire level 2 cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L2CacheInvalidate(void)
-{
- #ifdef __GNUC__
- u32 stack_start,stack_end,stack_size;
- register u32 L2CCReg;
- stack_end = (u32)&_stack_end;
- stack_start = (u32)&__undef_stack;
- stack_size=stack_start-stack_end;
-
- /* Check for the cache status. If cache is enabled, then only
- * flush stack memory to save return address. If cache is disabled,
- * don't flush anything as it might result in flushing stale date into
- * memory which is undesirable.
- */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
- if ((L2CCReg & 0x01U) != 0U) {
- /*Flush stack memory to save return address*/
- Xil_DCacheFlushRange(stack_end, stack_size);
- }
-
- #endif
- u32 ResultDCache;
- /* Invalidate the caches */
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET,
- 0x0000FFFFU);
- ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)
- & 0x0000FFFFU;
- while(ResultDCache != (u32)0U) {
- ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)
- & 0x0000FFFFU;
- }
-
- /* Wait for the invalidate to complete */
- Xil_L2CacheSync();
-
- /* synchronize the processor */
- dsb();
-}
-
-/*****************************************************************************/
-/**
-* @brief Invalidate a level 2 cache line. If the byte specified by the
-* address (adr) is cached by the Data cache, the cacheline containing
-* that byte is invalidated. If the cacheline is modified (dirty),
-* the modified contents are lost and are NOT written to system memory
-* before the line is invalidated.
-*
-* @param adr: 32bit address of the data/instruction to be invalidated.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L2CacheInvalidateLine(u32 adr)
-{
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, (u32)adr);
- /* synchronize the processor */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the level 2 cache for the given address range.
-* If the bytes specified by the address range are cached by the L2
-* cache, the cacheline containing those bytes are invalidated. If the
-* cachelines are modified (dirty), the modified contents are lost and
-* are NOT written to system memory before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L2CacheInvalidateRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INVLD_PA_OFFSET);
-
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
-
- while (LocalAddr < end) {
- *L2CCOffset = LocalAddr;
- Xil_L2CacheSync();
- LocalAddr += cacheline;
- }
-
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- }
-
- /* synchronize the processor */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the entire level 2 cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L2CacheFlush(void)
-{
- u32 ResultL2Cache;
-
- /* Flush the caches */
-
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
-
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET,
- 0x0000FFFFU);
- ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
- & 0x0000FFFFU;
-
- while(ResultL2Cache != (u32)0U) {
- ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
- & 0x0000FFFFU;
- }
-
- Xil_L2CacheSync();
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
-
- /* synchronize the processor */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Flush a level 2 cache line. If the byte specified by the address
-* (adr) is cached by the L2 cache, the cacheline containing that
-* byte is invalidated. If the cacheline is modified (dirty), the
-* entire contents of the cacheline are written to system memory
-* before the line is invalidated.
-*
-* @param adr: 32bit address of the data/instruction to be flushed.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L2CacheFlushLine(u32 adr)
-{
-#ifdef CONFIG_PL310_ERRATA_588369
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, adr);
-#else
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET, adr);
-#endif
- /* synchronize the processor */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the level 2 cache for the given address range.
-* If the bytes specified by the address range are cached by the L2
-* cache, the cacheline containing those bytes are invalidated. If the
-* cachelines are modified (dirty), they are written to the system
-* memory before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be flushed.
-* @param len: Length of the range to be flushed in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L2CacheFlushRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
-
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
-
- while (LocalAddr < end) {
- *L2CCOffset = LocalAddr;
- Xil_L2CacheSync();
- LocalAddr += cacheline;
- }
-
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- }
- /* synchronize the processor */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Store a level 2 cache line. If the byte specified by the address
-* (adr) is cached by the L2 cache and the cacheline is modified
-* (dirty), the entire contents of the cacheline are written to
-* system memory. After the store completes, the cacheline is marked
-* as unmodified (not dirty).
-*
-* @param adr: 32bit address of the data/instruction to be stored.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L2CacheStoreLine(u32 adr)
-{
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
- /* synchronize the processor */
- dsb();
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/82/30cc37565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/82/30cc37565243001d18b399c1eb9b3628
deleted file mode 100644
index 36c9ff8..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/82/30cc37565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,114 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xtime_l.c
-*
-* This file contains low level functions to get/set time from the Global Timer
-* register in the ARM Cortex R5 core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 5.00 pkp 08/29/14 First release
-* 5.04 pkp 02/19/16 XTime_StartTimer API is added to configure TTC3 timer
-* when present. XTime_GetTime is modified to give 64bit
-* output using timer overflow when TTC3 present.
-* XTime_SetTime is modified to configure TTC3 counter
-* value when present.
-* 5.04 pkp 03/11/16 XTime_StartTimer is modified to avoid enabling the
-* overflow interrupt and XTime_GetTime & XTime_SetTime
-* are modified to read and write TTC counter value
-* respectively
-* 5.04 pkp
-* 6.0 mus 08/11/16 Removed implementation of XTime_SetTime API, since
-* TTC counter value register is read only.
-* 6.6 srm 10/18/17 Removed XTime_StartTimer API and made XTime_GetTime,
-* XTime_SetTime applicable for all the instances of TTC
-* 7.2 mus 01/29/20 Updated XTime_GetTime to use CortexR5 PMU cycle
-* counter, in case sleep timer (ttc3/ttc2) is not
-* present in the HW design. It fixes CR#1051591.
-* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
-* displaying same warnings multiple times. It fixes CR#1090562.
-*
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "xtime_l.h"
-#include "xpseudo_asm.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xdebug.h"
-#include "xpm_counter.h"
-#include "xil_sleeptimer.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-#if defined (SLEEP_TIMER_BASEADDR)
-#pragma message ("For the sleep routines, TTC3/TTC2 is used")
-#elif !defined (DONT_USE_PMU_FOR_SLEEP_ROUTINES)
-#pragma message ("For the sleep routines, CortexR5 PMU cycle counter is used")
-#else
-#pragma message ("For the sleep routines, machine cycles are used")
-#endif
-
-/****************************************************************************/
-/**
-* @brief TTC Timer runs continuously and the time can not be set as
-* desired. This API doesn't contain anything. It is defined to have
-* uniformity across platforms.
-*
-* @param Xtime_Global: 32 bit value to be written to the timer counter
-* register.
-*
-* @return None.
-*
-* @note In multiprocessor environment reference time will reset/lost for
-* all processors, when this function called by any one processor.
-*
-****************************************************************************/
-void XTime_SetTime(XTime Xtime_Global)
-{
- (void) Xtime_Global;
-/*Timer cannot be set to desired value, so the API is left unimplemented*/
- xdbg_printf(XDBG_DEBUG_GENERAL,
- "XTime_SetTime:Timer cannot be set to desired value,so API is not implemented\n");
-}
-
-/****************************************************************************/
-/**
-* @brief Get the time from the timer counter register.
-*
-* @param Xtime_Global: Pointer to the 32 bit location to be updated with
-* the time current value of timer counter register.
-*
-* @return None.
-*
-****************************************************************************/
-void XTime_GetTime(XTime *Xtime_Global)
-{
-#if defined (SLEEP_TIMER_BASEADDR)
- *Xtime_Global = Xil_In32(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET);
-#elif !defined (DONT_USE_PMU_FOR_SLEEP_ROUTINES)
- #if defined (__GNUC__)
- *Xtime_Global = Xpm_ReadCycleCounterVal();
- #elif defined (__ICCARM__)
- Xpm_ReadCycleCounterVal(*Xtime_Global);
- #endif
-#endif
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/82/5029fd545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/82/5029fd545243001d18b399c1eb9b3628
deleted file mode 100644
index 8c81985..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/82/5029fd545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,848 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xsdps_options.c
-* @addtogroup sdps_v3_13
-* @{
-*
-* Contains API's for changing the various options in host and card.
-* See xsdps.h for a detailed description of the device and driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a hk/sg 10/17/13 Initial release
-* 2.1 hk 04/18/14 Increase sleep for eMMC switch command.
-* Add sleep for microblaze designs. CR# 781117.
-* 2.3 sk 09/23/14 Use XSdPs_Change_ClkFreq API whenever changing
-* clock.CR# 816586.
-* 2.5 sg 07/09/15 Added SD 3.0 features
-* kvn 07/15/15 Modified the code according to MISRAC-2012.
-* 2.7 sk 01/08/16 Added workaround for issue in auto tuning mode
-* of SDR50, SDR104 and HS200.
-* sk 02/16/16 Corrected the Tuning logic.
-* sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
-* 2.8 sk 04/20/16 Added new workaround for auto tuning.
-* 3.0 sk 07/07/16 Used usleep API for both arm and microblaze.
-* sk 07/16/16 Added support for UHS modes.
-* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
-* operating modes.
-* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
-* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
-* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value.
-* 3.2 sk 02/01/17 Added HSD and DDR mode support for eMMC.
-* sk 02/01/17 Consider bus width parameter from design for switching
-* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
-* vns 03/13/17 Fixed MISRAC mandatory violation
-* sk 03/20/17 Add support for EL1 non-secure mode.
-* 3.3 mn 07/25/17 Removed SD0_OTAPDLYENA and SD1_OTAPDLYENA bits
-* mn 08/07/17 Properly set OTAPDLY value by clearing previous bit
-* settings
-* mn 08/17/17 Added CCI support for A53 and disabled data cache
-* operations when it is enabled.
-* mn 08/22/17 Updated for Word Access System support
-* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines
-* 3.6 mn 07/06/18 Fix Cppcheck warnings for sdps driver
-* 3.7 aru 03/12/19 Modified the code according to MISRAC-2012.
-* mn 03/27/19 Disable calls to dll_reset API for versal SPP Platforms
-* 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
-* mn 05/21/19 Set correct tap delays for Versal
-* mn 05/21/19 Disable DLL Reset code for Versal
-* mn 08/29/19 Add call to Cache Invalidation API in XSdPs_Get_BusWidth
-* 3.9 mn 03/03/20 Restructured the code for more readability and modularity
-* mn 03/16/20 Move XSdPs_Select_Card API to User APIs
-* 3.10 mn 06/05/20 Modified code for SD Non-Blocking Read support
-* 3.12 sk 01/28/21 Added support for non-blocking write.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xsdps_core.h"
-/************************** Constant Definitions *****************************/
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to change clock freq to given value.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param SelFreq - Clock frequency in Hz.
-*
-* @return None
-*
-* @note This API will change clock frequency to the value less than
-* or equal to the given value using the permissible dividors.
-*
-******************************************************************************/
-s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
- /* Program the Tap delays */
- XSdPs_SetTapDelay(InstancePtr);
- }
-
- Status = XSdPs_SetClock(InstancePtr, SelFreq);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* Update Block size for read/write operations.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param BlkSize - Block size passed by the user.
-*
-* @return None
-*
-******************************************************************************/
-s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- Status = XSdPs_CheckBusIdle(InstancePtr, (XSDPS_PSR_INHIBIT_CMD_MASK
- | XSDPS_PSR_INHIBIT_DAT_MASK
- | XSDPS_PSR_WR_ACTIVE_MASK
- | XSDPS_PSR_RD_ACTIVE_MASK));
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- /* Send block write command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD16, BlkSize, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Set block size to the value passed */
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
- BlkSize & XSDPS_BLK_SIZE_MASK);
-
- InstancePtr->BlkSize = BlkSize;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to get bus width support by card.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param ReadBuff - buffer to store SCR register returned by card.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *ReadBuff)
-{
- s32 Status;
- u16 BlkCnt;
- u16 BlkSize;
- s32 LoopCnt;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- for (LoopCnt = 0; LoopCnt < 8; LoopCnt++) {
- ReadBuff[LoopCnt] = 0U;
- }
-
- /* Send block write command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
- InstancePtr->RelCardAddr, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- BlkCnt = XSDPS_SCR_BLKCNT;
- BlkSize = XSDPS_SCR_BLKSIZE;
-
- XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, ReadBuff);
-
- Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0U, BlkCnt);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Check for transfer done */
- Status = XSdps_CheckTransferDone(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- if (InstancePtr->Config.IsCacheCoherent == 0U) {
- Xil_DCacheInvalidateRange((INTPTR)ReadBuff,
- (INTPTR)BlkCnt * BlkSize);
- }
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to set bus width to 4-bit in card and host
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr)
-{
- s32 Status;
- u32 StatusReg;
- u32 Arg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * check for bus width for 3.0 controller and return if
- * bus width is <4
- */
- if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
- (InstancePtr->Config.BusWidth < XSDPS_WIDTH_4)) {
- Status = XST_SUCCESS;
- goto RETURN_PATH;
- }
-
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr,
- 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, (u32)InstancePtr->BusWidth, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } else {
- if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
- if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
- Arg = XSDPS_MMC_DDR_8_BIT_BUS_ARG;
- } else {
- Arg = XSDPS_MMC_8_BIT_BUS_ARG;
- }
- } else {
- if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
- Arg = XSDPS_MMC_DDR_4_BIT_BUS_ARG;
- } else {
- Arg = XSDPS_MMC_4_BIT_BUS_ARG;
- }
- }
-
- Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, Arg);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
-
- StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL1_OFFSET);
-
- /* Width setting in controller */
- if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
- StatusReg |= XSDPS_HC_EXT_BUS_WIDTH;
- } else {
- StatusReg |= XSDPS_HC_WIDTH_MASK;
- }
-
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL1_OFFSET,
- (u8)StatusReg);
-
- if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
- StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET);
- StatusReg &= (u32)(~XSDPS_HC2_UHS_MODE_MASK);
- StatusReg |= InstancePtr->Mode;
- XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL2_OFFSET, (u16)StatusReg);
- }
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to get bus speed supported by card.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param ReadBuff - buffer to store function group support data
-* returned by card.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff)
-{
- s32 Status;
- u32 Arg;
- u16 BlkCnt;
- u16 BlkSize;
- s32 LoopCnt;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- for (LoopCnt = 0; LoopCnt < 64; LoopCnt++) {
- ReadBuff[LoopCnt] = 0U;
- }
-
- BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
- BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
-
- XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, ReadBuff);
-
- Arg = XSDPS_SWITCH_CMD_HS_GET;
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Check for transfer done */
- Status = XSdps_CheckTransferDone(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- if (InstancePtr->Config.IsCacheCoherent == 0U) {
- Xil_DCacheInvalidateRange((INTPTR)ReadBuff,
- (INTPTR)BlkCnt * BlkSize);
- }
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to get SD card status information.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param SdStatReg - buffer to store status data returned by card.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Get_Status(XSdPs *InstancePtr, u8 *SdStatReg)
-{
- s32 Status;
- u16 BlkCnt;
- u16 BlkSize;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Send block write command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
- InstancePtr->RelCardAddr, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- BlkCnt = XSDPS_SD_STATUS_BLKCNT;
- BlkSize = XSDPS_SD_STATUS_BLKSIZE;
-
- XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, SdStatReg);
-
- Status = XSdPs_CmdTransfer(InstancePtr, ACMD13, 0U, BlkCnt);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Check for transfer done */
- Status = XSdps_CheckTransferDone(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- if (InstancePtr->Config.IsCacheCoherent == 0U) {
- Xil_DCacheInvalidateRange((INTPTR)SdStatReg,
- (INTPTR)BlkCnt * BlkSize);
- }
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to set high speed in card and host. Changes clock in host accordingly.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
-{
- s32 Status;
- u32 StatusReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
- Status = XSdPs_Change_SdBusSpeed(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } else {
- Status = XSdPs_Change_MmcBusSpeed(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if ((InstancePtr->Mode == XSDPS_HS200_MODE) ||
- (InstancePtr->Mode == XSDPS_UHS_SPEED_MODE_SDR104) ||
- (InstancePtr->Mode == XSDPS_UHS_SPEED_MODE_SDR50)) {
- Status = XSdPs_Execute_Tuning(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
- usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
-
- StatusReg = (u32)XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL1_OFFSET);
- StatusReg |= XSDPS_HC_SPEED_MASK;
- XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg);
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to get EXT_CSD register of eMMC.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param ReadBuff - buffer to store EXT_CSD
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
-{
- s32 Status;
- u32 Arg = 0U;
- u16 BlkCnt;
- u16 BlkSize;
- s32 LoopCnt;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- for (LoopCnt = 0; LoopCnt < 512; LoopCnt++) {
- ReadBuff[LoopCnt] = 0U;
- }
-
- BlkCnt = XSDPS_EXT_CSD_CMD_BLKCNT;
- BlkSize = XSDPS_EXT_CSD_CMD_BLKSIZE;
-
- XSdPs_SetupReadDma(InstancePtr, BlkCnt, BlkSize, ReadBuff);
-
- /* Send SEND_EXT_CSD command */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Check for transfer done */
- Status = XSdps_CheckTransferDone(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- if (InstancePtr->Config.IsCacheCoherent == 0U) {
- Xil_DCacheInvalidateRange((INTPTR)ReadBuff,
- (INTPTR)BlkCnt * BlkSize);
- }
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to write EXT_CSD register of eMMC.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param Arg is the argument to be sent along with the command
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Check for transfer done */
- Status = XSdps_CheckTransferDone(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to send pullup command to card before using DAT line 3(using 4-bit bus)
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Pullup(XSdPs *InstancePtr)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
- InstancePtr->RelCardAddr, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XSdPs_CmdTransfer(InstancePtr, ACMD42, 0U, 0U);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- Status = XST_SUCCESS;
-
- RETURN_PATH:
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* Selects card and sets default block size
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_FAILURE if fail.
-* - XSDPS_CT_ERROR if Command Transfer fail.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Select_Card (XSdPs *InstancePtr)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Send CMD7 - Select card */
- Status = XSdPs_CmdTransfer(InstancePtr, CMD7,
- InstancePtr->RelCardAddr, 0U);
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function performs SD read in polled mode.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Arg is the address passed by the user that is to be sent as
-* argument along with the command.
-* @param BlkCnt - Block count passed by the user.
-* @param Buff - Pointer to the data buffer for a DMA transfer.
-*
-* @return
-* - XST_SUCCESS if Transfer initialization was successful
-* - XST_FAILURE if failure - could be because another transfer
-* is in progress or command or data inhibit is set
-*
-******************************************************************************/
-s32 XSdPs_StartReadTransfer(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- if (InstancePtr->IsBusy == TRUE) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Setup the Read Transfer */
- Status = XSdPs_SetupTransfer(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Read from the card */
- Status = XSdPs_Read(InstancePtr, Arg, BlkCnt, Buff);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- InstancePtr->IsBusy = TRUE;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function start SD write transfer.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Arg is the address passed by the user that is to be sent as
-* argument along with the command.
-* @param BlkCnt - Block count passed by the user.
-* @param Buff - Pointer to the data buffer for a DMA transfer.
-*
-* @return
-* - XST_SUCCESS if Transfer initialization was successful
-* - XST_FAILURE if failure - could be because another transfer
-* is in progress or command or data inhibit is set
-*
-******************************************************************************/
-s32 XSdPs_StartWriteTransfer(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- if (InstancePtr->IsBusy == TRUE) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Setup the Write Transfer */
- Status = XSdPs_SetupTransfer(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* write to the card */
- Status = XSdPs_Write(InstancePtr, Arg, BlkCnt, Buff);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- }
-
- InstancePtr->IsBusy = TRUE;
-
-RETURN_PATH:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to check if the transfer is completed successfully.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if transfer was successful
-* - XST_FAILURE if failure
-* - XST_DEVICE_BUSY - if the transfer is still in progress
-*
-******************************************************************************/
-s32 XSdPs_CheckReadTransfer(XSdPs *InstancePtr)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- Status = XSdPs_CheckTransferComplete(InstancePtr);
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function is used to check for the write transfer completed.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if transfer was successful
-* - XST_FAILURE if failure
-* - XST_DEVICE_BUSY - if the transfer is still in progress
-*
-******************************************************************************/
-s32 XSdPs_CheckWriteTransfer(XSdPs *InstancePtr)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- Status = XSdPs_CheckTransferComplete(InstancePtr);
-
- return Status;
-}
-
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/82/509bf0535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/82/509bf0535243001d18b399c1eb9b3628
deleted file mode 100644
index 5c01051..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/82/509bf0535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1132 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
- *
- * @file xusbps.h
-* @addtogroup usbps_v2_7
-* @{
-* @details
- *
- * This file contains the implementation of the XUsbPs driver. It is the
- * driver for an USB controller in DEVICE or HOST mode.
- *
- *
Introduction
- *
- * The Spartan-3AF Embedded Peripheral Block contains a USB controller for
- * communication with serial peripherals or hosts. The USB controller supports
- * Host, Device and On the Go (OTG) applications.
- *
- *
USB Controller Features
- *
- * - Supports Low Speed USB 1.1 (1.5Mbps), Full Speed USB 1.1 (12Mbps), and
- * High Speed USB 2.0 (480Mbps) data speeds
- * - Supports Device, Host and OTG operational modes
- * - ULPI transceiver interface for USB 2.0 operation
- * - Integrated USB Full and Low speed serial transceiver interfaces for lowest
- * cost connections
- *
- *
Initialization & Configuration
- *
- * The configuration of the USB driver happens in multiple stages:
- *
- * - (a) Configuration of the basic parameters:
- * In this stage the basic parameters for the driver are configured,
- * including the base address and the controller ID.
- *
- * - (b) Configuration of the DEVICE endpoints (if applicable):
- * If DEVICE mode is desired, the endpoints of the controller need to be
- * configured using the XUsbPs_DeviceConfig data structure. Once the
- * endpoint configuration is set up in the data structure, The user then
- * needs to allocate the required amount of DMAable memory and
- * finalize the configuration of the XUsbPs_DeviceConfig data structure,
- * e.g. setting the DMAMemVirt and DMAMemPhys members.
- *
- * - (c) Configuration of the DEVICE modes:
- * In the second stage the parameters for DEVICE are configured.
- * The caller only needs to configure the modes that are
- * actually used. Configuration is done with the:
- * XUsbPs_ConfigureDevice()
- * Configuration parameters are defined and passed
- * into these functions using the:
- * XUsbPs_DeviceConfig data structures.
- *
- *
- *
USB Device Endpoints
- *
- * The USB core supports up to 4 endpoints. Each endpoint has two directions,
- * an OUT (RX) and an IN (TX) direction. Note that the direction is viewed from
- * the host's perspective. Endpoint 0 defaults to be the control endpoint and
- * does not need to be set up. Other endpoints need to be configured and set up
- * depending on the application. Only endpoints that are actuelly used by the
- * application need to be initialized.
- * See the example code (xusbps_intr_example.c) for more information.
- *
- *
- *
Interrupt Handling
- *
- * The USB core uses one interrupt line to report interrupts to the CPU.
- * Interrupts are handled by the driver's interrupt handler function
- * XUsbPs_IntrHandler().
- * It has to be registered with the OS's interrupt subsystem. The driver's
- * interrupt handler divides incoming interrupts into two categories:
- *
- * - General device interrupts
- * - Endopint related interrupts
- *
- * The user (typically the adapter layer) can register general interrupt
- * handler functions and endpoint specific interrupt handler functions with the
- * driver to receive those interrupts by calling the
- * XUsbPs_IntrSetHandler()
- * and
- * XUsbPs_EpSetHandler()
- * functions respectively. Calling these functions with a NULL pointer as the
- * argument for the function pointer will "clear" the handler function.
- *
- * The user can register one handler function for the generic interrupts and
- * two handler functions for each endpoint, one for the RX (OUT) and one for
- * the TX (IN) direction. For some applications it may be useful to register a
- * single endpoint handler function for muliple endpoints/directions.
- *
- * When a callback function is called by the driver, parameters identifying the
- * type of the interrupt will be passed into the handler functions. For general
- * interrupts the interrupt mask will be passed into the handler function. For
- * endpoint interrupts the parameters include the number of the endpoint, the
- * direction (OUT/IN) and the type of the interrupt.
- *
- *
- *
Data buffer handling
- *
- * Data buffers are sent to and received from endpoint using the
- * XUsbPs_EpBufferSend(), XUsbPs_EpBufferSendWithZLT()
- * and
- * XUsbPs_EpBufferReceive()
- * functions.
- *
- * User data buffer size is limited to 16 Kbytes. If the user wants to send a
- * data buffer that is bigger than this limit it needs to break down the data
- * buffer into multiple fragments and send the fragments individually.
- *
- * From the controller perspective Data buffers can be aligned at any boundary.
- * if the buffers are from cache region then the buffer and buffer size should
- * be aligned to cache line aligned
- *
- *
- *
Zero copy
- *
- * The driver uses a zero copy mechanism which imposes certain restrictions to
- * the way the user can handle the data buffers.
- *
- * One restriction is that the user needs to release a buffer after it is done
- * processing the data in the buffer.
- *
- * Similarly, when the user sends a data buffer it MUST not re-use the buffer
- * until it is notified by the driver that the buffer has been transmitted. The
- * driver will notify the user via the registered endpoint interrupt handling
- * function by sending a XUSBPS_EP_EVENT_DATA_TX event.
- *
- *
- *
DMA
- *
- * The driver uses DMA internally to move data from/to memory. This behaviour
- * is transparent to the user. Keeping the DMA handling hidden from the user
- * has the advantage that the same API can be used with USB cores that do not
- * support DMA.
- *
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- ----------------------------------------------------------
- * 1.00a wgr 10/10/10 First release
- * 1.02a wgr 05/16/12 Removed comments as they are showing up in SDK
- * Tabs for CR 657898
- * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet
- * handling.
- * 1.04a nm 10/23/12 Fixed CR# 679106.
- * 11/02/12 Fixed CR# 683931. Mult bits are set properly in dQH.
- * 2.00a kpc 04/03/14 Fixed CR#777763. Corrected the setup tripwire macro val.
- * 2.1 kpc 04/28/14 Removed unused function prototypes
- * 2.2 kpc 08/23/14 Exported XUsbPs_DeviceReset API as global for calling in
- * code coverage tests.
- * 2.3 kpc 02/19/14 Fixed CR#873972, CR#873974. Corrected the logic for proper
- * moving of dTD Head/Tail Pointers. Invalidate the cache
- * after buffer receive in Endpoint Buffer Handler.
- * 2.4 sg 04/26/16 Fixed CR#949693, Corrected the logic for EP flush
- * ms 03/17/17 Added readme.txt file in examples folder for doxygen
- * generation.
- * ms 04/10/17 Modified filename tag to include the file in doxygen
- * examples.
- * 2.5 pm 02/20/20 Added ISO support for usb 2.0 and ch9 common framework
- * calls.
- *
- *
- ******************************************************************************/
-
-#ifndef XUSBPS_H
-#define XUSBPS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xusbps_hw.h"
-#include "xil_types.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions *****************************/
-
-/**
- * @name System hang prevention Timeout counter value.
- *
- * This value is used throughout the code to initialize a Timeout counter that
- * is used when hard polling a register. The ides is to initialize the Timeout
- * counter to a value that is longer than any expected Timeout but short enough
- * so the system will continue to work and report an error while the user is
- * still paying attention. A reasonable Timeout time would be about 10 seconds.
- * The XUSBPS_TIMEOUT_COUNTER value should be chosen so a polling loop would
- * run about 10 seconds before a Timeout is detected. For example:
- *
- * int Timeout = XUSBPS_TIMEOUT_COUNTER;
- * while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- * XUSBPS_CMD_OFFSET) &
- * XUSBPS_CMD_RST_MASK) && --Timeout) {
- * ;
- * }
- * if (0 == Timeout) {
- * return XST_FAILURE;
- * }
- *
- */
-#define XUSBPS_TIMEOUT_COUNTER 1000000
-
-
-/**
- * @name Endpoint Direction (bitmask)
- * Definitions to be used with Endpoint related function that require a
- * 'Direction' parameter.
- *
- * NOTE:
- * The direction is always defined from the perspective of the HOST! This
- * means that an IN endpoint on the controller is used for sending data while
- * the OUT endpoint on the controller is used for receiving data.
- * @{
- */
-#define XUSBPS_EP_DIRECTION_IN 0x01 /**< Endpoint direction IN. */
-#define XUSBPS_EP_DIRECTION_OUT 0x02 /**< Endpoint direction OUT. */
-/* @} */
-
-
-/**
- * @name Endpoint Type
- * Definitions to be used with Endpoint related functions that require a 'Type'
- * parameter.
- * @{
- */
-#define XUSBPS_EP_TYPE_NONE 0 /**< Endpoint is not used. */
-#define XUSBPS_EP_TYPE_CONTROL 1 /**< Endpoint for Control Transfers */
-#define XUSBPS_EP_TYPE_ISOCHRONOUS 2 /**< Endpoint for isochronous data */
-#define XUSBPS_EP_TYPE_BULK 3 /**< Endpoint for BULK Transfers. */
-#define XUSBPS_EP_TYPE_INTERRUPT 4 /**< Endpoint for interrupt Transfers */
-/* @} */
-
-/**
- * Endpoint Max Packet Length in DeviceConfig is a coded value, ch9.6.6.
- *
- * @{
- */
-#define ENDPOINT_MAXP_LENGTH 0x400
-#define ENDPOINT_MAXP_MULT_MASK 0xC00
-#define ENDPOINT_MAXP_MULT_SHIFT 10
-/* @} */
-
-/**
- * @name Field names for status retrieval
- * Definitions for the XUsbPs_GetStatus() function call 'StatusType'
- * parameter.
- * @{
- */
-#define XUSBPS_EP_STS_ADDRESS 1 /**< Address of controller. */
-#define XUSBPS_EP_STS_CONTROLLER_STATE 2 /**< Current controller state. */
-/* @} */
-
- /*
- * Device Speeds
- */
- #define XUSBPS_SPEED_UNKNOWN 0U
- #define XUSBPS_SPEED_LOW 1U
- #define XUSBPS_SPEED_FULL 2U
- #define XUSBPS_SPEED_HIGH 3U
-
-/**
- * @name USB Default alternate setting
- *
- * @{
- */
-#define XUSBPS_DEFAULT_ALT_SETTING 0 /**< The default alternate setting is 0 */
-/* @} */
-
- /*
- * Device States
- */
- #define XUSBPS_STATE_ATTACHED 0U
- #define XUSBPS_STATE_POWERED 1U
- #define XUSBPS_STATE_DEFAULT 2U
- #define XUSBPS_STATE_ADDRESS 3U
- #define XUSBPS_STATE_CONFIGURED 4U
- #define XUSBPS_STATE_SUSPENDED 5U
-
-/**
- * @name Endpoint event types
- * Definitions that are used to identify events that occur on endpoints. Passed
- * to the endpoint event handler functions registered with
- * XUsbPs_EpSetHandler().
- * @{
- */
-#define XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED 0x01
- /**< Setup data has been received on the endpoint. */
-#define XUSBPS_EP_EVENT_DATA_RX 0x02
- /**< Data frame has been received on the endpoint. */
-#define XUSBPS_EP_EVENT_DATA_TX 0x03
- /**< Data frame has been sent on the endpoint. */
-/* @} */
-
-
-/*
- * Maximum packet size for endpoint, 1024
- * @{
- */
-#define XUSBPS_MAX_PACKET_SIZE 1024
- /**< Maximum value can be put into the queue head */
-/* @} */
-/**************************** Type Definitions *******************************/
-
-/******************************************************************************
- * This data type defines the callback function to be used for Endpoint
- * handlers.
- *
- * @param CallBackRef is the Callback reference passed in by the upper
- * layer when setting the handler, and is passed back to the upper
- * layer when the handler is called.
- * @param EpNum is the Number of the endpoint that caused the event.
- * @param EventType is the type of the event that occurred on the endpoint.
- * @param Data is a pointer to user data pointer specified when callback
- * was registered.
- */
-typedef void (*XUsbPs_EpHandlerFunc)(void *CallBackRef,
- u8 EpNum, u8 EventType, void *Data);
-
-/******************************************************************************
- * This data type defines the callback function to be used for Endpoint
- * handlers.
- *
- * @param CallBackRef is the Callback reference passed in by the upper
- * layer when setting the handler, and is passed back to the upper
- * layer when the handler is called.
- * @param RequestedBytes is the number of bytes requested to transfer.
- * @param BytesTxed is the actual number of bytes to be transfer.
- */
-typedef void (*XUsbPs_EpIsoHandlerFunc)(void *CallBackRef,
- u32 RequestedBytes, u32 BytesTxed);
-
-/******************************************************************************
- * This data type defines the callback function to be used for the general
- * interrupt handler.
- *
- * @param CallBackRef is the Callback reference passed in by the upper
- * layer when setting the handler, and is passed back to the upper
- * layer when the handler is called.
- * @param IrqMask is the Content of the interrupt status register. This
- * value can be used by the callback function to distinguish the
- * individual interrupt types.
- */
-typedef void (*XUsbPs_IntrHandlerFunc)(void *CallBackRef, u32 IrqMask);
-
-
-/******************************************************************************/
-
-/* The following type definitions are used for referencing Queue Heads and
- * Transfer Descriptors. The structures themselves are not used, however, the
- * types are used in the API to avoid using (void *) pointers.
- */
-typedef u8 XUsbPs_dQH[XUSBPS_dQH_ALIGN];
-typedef u8 XUsbPs_dTD[XUSBPS_dTD_ALIGN];
-
-
-/**
- * The following data structures are used internally by the L0/L1 driver.
- * Their contents MUST NOT be changed by the upper layers.
- */
-
-/**
- * The following data structure represents OUT endpoint.
- */
-typedef struct {
- XUsbPs_dQH *dQH;
- /**< Pointer to the Queue Head structure of the endpoint. */
-
- XUsbPs_dTD *dTDs;
- /**< Pointer to the first dTD of the dTD list for this
- * endpoint. */
-
- XUsbPs_dTD *dTDCurr;
- /**< Buffer to the currently processed descriptor. */
-
- u8 *dTDBufs;
- /**< Pointer to the first buffer of the buffer list for this
- * endpoint. */
-
- XUsbPs_EpHandlerFunc HandlerFunc;
- XUsbPs_EpIsoHandlerFunc HandlerIsoFunc;
- /**< Handler function for this endpoint. */
- void *HandlerRef;
- /**< User data reference for the handler. */
- u32 RequestedBytes; /**< RequestedBytes for transfer */
- u32 BytesTxed; /**< Actual Bytes transferred */
- u8 *BufferPtr; /**< Buffer location */
- u8 MemAlloted; /**< Mem alloted and data is not received */
- u32 Interval; /**< Data transfer service interval */
-} XUsbPs_EpOut;
-
-
-/**
- * The following data structure represents IN endpoint.
- */
-typedef struct {
- XUsbPs_dQH *dQH;
- /**< Pointer to the Queue Head structure of the endpoint. */
-
- XUsbPs_dTD *dTDs;
- /**< List of pointers to the Transfer Descriptors of the
- * endpoint. */
-
- XUsbPs_dTD *dTDHead;
- /**< Buffer to the next available descriptor in the list. */
-
- XUsbPs_dTD *dTDTail;
- /**< Buffer to the last unsent descriptor in the list*/
-
- XUsbPs_EpHandlerFunc HandlerFunc;
- XUsbPs_EpIsoHandlerFunc HandlerIsoFunc;
- /**< Handler function for this endpoint. */
- void *HandlerRef;
- /**< User data reference for the handler. */
- u32 RequestedBytes; /**< RequestedBytes for transfer */
- u32 BytesTxed; /**< Actual Bytes transferred */
- u8 *BufferPtr; /**< Buffer location */
- u32 Interval; /**< Data transfer service interval */
-} XUsbPs_EpIn;
-
-
-/**
- * The following data structure represents an endpoint used internally
- * by the L0/L1 driver.
- */
-typedef struct {
- /* Each endpoint has an OUT and an IN component.
- */
- XUsbPs_EpOut Out; /**< OUT endpoint structure */
- XUsbPs_EpIn In; /**< IN endpoint structure */
-} XUsbPs_Endpoint;
-
-
-
-/**
- * The following structure is used by the user to receive Setup Data from an
- * endpoint. Using this structure simplifies the process of interpreting the
- * setup data in the core's data fields.
- *
- * The naming scheme for the members of this structure is different from the
- * naming scheme found elsewhere in the code. The members of this structure are
- * defined in the Chapter 9 USB reference guide. Using this naming scheme makes
- * it easier for people familiar with the standard to read the code.
- */
-typedef struct {
- u8 bmRequestType; /**< bmRequestType in setup data */
- u8 bRequest; /**< bRequest in setup data */
- u16 wValue; /**< wValue in setup data */
- u16 wIndex; /**< wIndex in setup data */
- u16 wLength; /**< wLength in setup data */
-}
-XUsbPs_SetupData;
-
-
-/**
- * Data structures used to configure endpoints.
- */
-typedef struct {
- u32 Type;
- /**< Endpoint type:
- - XUSBPS_EP_TYPE_CONTROL
- - XUSBPS_EP_TYPE_ISOCHRONOUS
- - XUSBPS_EP_TYPE_BULK
- - XUSBPS_EP_TYPE_INTERRUPT */
-
- u32 NumBufs;
- /**< Number of buffers to be handled by this endpoint. */
- u32 BufSize;
- /**< Buffer size. Only relevant for OUT (receive) Endpoints. */
-
- u16 MaxPacketSize;
- /**< Maximum packet size for this endpoint. This number will
- * define the maximum number of bytes sent on the wire per
- * transaction. Range: 0..1024 */
-} XUsbPs_EpSetup;
-
-
-/**
- * Endpoint configuration structure.
- */
-typedef struct {
- XUsbPs_EpSetup Out; /**< OUT component of endpoint. */
- XUsbPs_EpSetup In; /**< IN component of endpoint. */
-} XUsbPs_EpConfig;
-
-
-/**
- * The XUsbPs_DeviceConfig structure contains the configuration information to
- * configure the USB controller for DEVICE mode. This data structure is used
- * with the XUsbPs_ConfigureDevice() function call.
- */
-typedef struct {
- u8 NumEndpoints; /**< Number of Endpoints for the controller.
- This number depends on the runtime
- configuration of driver. The driver may
- configure fewer endpoints than are available
- in the core. */
-
- XUsbPs_EpConfig EpCfg[XUSBPS_MAX_ENDPOINTS];
- /**< List of endpoint configurations. */
-
-
- u32 DMAMemPhys; /**< Physical base address of DMAable memory
- allocated for the driver. */
-
- /* The following members are used internally by the L0/L1 driver. They
- * MUST NOT be accesses and/or modified in any way by the upper layers.
- *
- * The reason for having these members is that we generally try to
- * avoid allocating memory in the L0/L1 driver as we want to be OS
- * independent. In order to avoid allocating memory for this data
- * structure wihin L0/L1 we put it into the XUsbPs_DeviceConfig
- * structure which is allocated by the caller.
- */
- XUsbPs_Endpoint Ep[XUSBPS_MAX_ENDPOINTS];
- /**< List of endpoint metadata structures. */
-
- u32 PhysAligned; /**< 64 byte aligned base address of the DMA
- memory block. Will be computed and set by
- the L0/L1 driver. */
-} XUsbPs_DeviceConfig;
-
-
-/**
- * The XUsbPs_Config structure contains configuration information for the USB
- * controller.
- *
- * This structure only contains the basic configuration for the controller. The
- * caller also needs to initialize the controller for the DEVICE mode
- * using the XUsbPs_DeviceConfig data structures with the
- * XUsbPs_ConfigureDevice() function call
- */
-typedef struct {
- u16 DeviceID; /**< Unique ID of controller. */
- u32 BaseAddress; /**< Core register base address. */
-} XUsbPs_Config;
-
-typedef XUsbPs_Config Usb_Config;
-
-struct Usb_DevData {
- u8 Speed;
- u8 State;
-
- void *PrivateData;
-};
-
-/**
- * The XUsbPs driver instance data. The user is required to allocate a
- * variable of this type for every USB controller in the system. A pointer to a
- * variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XUsbPs_SetupData SetupData;
- /**< Setup Packet buffer */
- XUsbPs_Config Config; /**< Configuration structure */
-
- int CurrentAltSetting; /**< Current alternative setting of interface */
-
- void *UserDataPtr; /**< Data pointer to be used by upper layers to
- store application dependent data structures.
- The upper layers are responsible to allocated
- and free the memory. The driver will not
- mofidy this data pointer. */
-
- /**
- * The following structures hold the configuration for DEVICE mode
- * of the controller. They are initialized using the
- * XUsbPs_ConfigureDevice() function call.
- */
- XUsbPs_DeviceConfig DeviceConfig;
- /**< Configuration for the DEVICE mode. */
-
- XUsbPs_IntrHandlerFunc HandlerFunc;
- /**< Handler function for the controller. */
- void *HandlerRef;
- /**< User data reference for the handler. */
- u32 HandlerMask;
- /**< User interrupt mask. Defines which interrupts will cause
- * the callback to be called. */
- struct Usb_DevData *AppData;
- u8 IsConfigDone;
- void *data_ptr; /* pointer for storing applications data */
-} XUsbPs;
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/******************************************************************************
- *
- * USB CONTROLLER RELATED MACROS
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
- * This macro returns the current frame number.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @return The current frame number.
- *
- * @note C-style signature:
- * u32 XUsbPs_GetFrameNum(const XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_GetFrameNum(InstancePtr) \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, XUSBPS_FRAME_OFFSET)
-
-
-/*****************************************************************************/
-/**
- * This macro starts the USB engine.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @note C-style signature:
- * void XUsbPs_Start(XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_Start(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
-
-
-/*****************************************************************************/
-/**
- * This macro stops the USB engine.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @note C-style signature:
- * void XUsbPs_Stop(XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_Stop(InstancePtr) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
-
-
-/*****************************************************************************/
-/**
- * This macro forces the USB engine to be in Full Speed (FS) mode.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @note C-style signature:
- * void XUsbPs_ForceFS(XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_ForceFS(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
- XUSBPS_PORTSCR_PFSC_MASK)
-
-
-/*****************************************************************************/
-/**
- * This macro starts the USB Timer 0, with repeat option for period of
- * one second.
- *
- * @param InstancePtr is a pointer to XUsbPs instance of the controller.
- * @param Interval is the interval for Timer0 to generate an interrupt
- *
- * @note C-style signature:
- * void XUsbPs_StartTimer0(XUsbPs *InstancePtr, u32 Interval)
- *
- ******************************************************************************/
-#define XUsbPs_StartTimer0(InstancePtr, Interval) \
-{ \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_TIMER0_LD_OFFSET, (Interval)); \
- XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
- XUSBPS_TIMER_RUN_MASK | \
- XUSBPS_TIMER_RESET_MASK | \
- XUSBPS_TIMER_REPEAT_MASK); \
-} \
-
-
-/*****************************************************************************/
-/**
-* This macro stops Timer 0.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_StopTimer0(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_StopTimer0(InstancePtr) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
- XUSBPS_TIMER_RUN_MASK)
-
-
-/*****************************************************************************/
-/**
-* This macro reads Timer 0.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_ReadTimer0(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_ReadTimer0(InstancePtr) \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_TIMER0_CTL_OFFSET) & \
- XUSBPS_TIMER_COUNTER_MASK
-
-
-/*****************************************************************************/
-/**
-* This macro force remote wakeup on host
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_RemoteWakeup(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_RemoteWakeup(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
- XUSBPS_PORTSCR_FPR_MASK)
-
-
-/******************************************************************************
- *
- * ENDPOINT RELATED MACROS
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
-* This macro enables the given endpoint for the given direction.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is number of the endpoint to enable.
-* @param Dir is direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpEnable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpEnable(InstancePtr, EpNum, Dir) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro disables the given endpoint for the given direction.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is the number of the endpoint to disable.
-* @param Dir is the direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpDisable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpDisable(InstancePtr, EpNum, Dir) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro stalls the given endpoint for the given direction, and flush
-* the buffers.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is number of the endpoint to stall.
-* @param Dir is the direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpStall(InstancePtr, EpNum, Dir) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro unstalls the given endpoint for the given direction.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is the Number of the endpoint to unstall.
-* @param Dir is the Direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpUnStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpUnStall(InstancePtr, EpNum, Dir) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro flush an endpoint upon interface disable
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is the number of the endpoint to flush.
-* @param Dir is the direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpFlush(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpFlush(InstancePtr, EpNum, Dir) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPFLUSH_OFFSET, \
- 1 << (EpNum + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? \
- XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT))) \
-
-/*****************************************************************************/
-/**
-* This macro enables the interrupts defined by the bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param IntrMask is the Bit mask of interrupts to be enabled.
-*
-* @note C-style signature:
-* void XUsbPs_IntrEnable(XUsbPs *InstancePtr, u32 IntrMask)
-*
-******************************************************************************/
-#define XUsbPs_IntrEnable(InstancePtr, IntrMask) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
-
-
-/*****************************************************************************/
-/**
-* This function disables the interrupts defined by the bit mask.
-*
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param IntrMask is a Bit mask of interrupts to be disabled.
-*
-* @note C-style signature:
-* void XUsbPs_IntrDisable(XUsbPs *InstancePtr, u32 IntrMask)
-*
-******************************************************************************/
-#define XUsbPs_IntrDisable(InstancePtr, IntrMask) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
-
-
-/*****************************************************************************/
-/**
-* This macro enables the endpoint NAK interrupts defined by the bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be
-* enabled.
-* @note C-style signature:
-* void XUsbPs_NakIntrEnable(XUsbPs *InstancePtr, u32 NakIntrMask)
-*
-******************************************************************************/
-#define XUsbPs_NakIntrEnable(InstancePtr, NakIntrMask) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
-
-
-/*****************************************************************************/
-/**
-* This macro disables the endpoint NAK interrupts defined by the bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param NakIntrMask is a Bit mask of endpoint NAK interrupts to be
-* disabled.
-*
-* @note
-* C-style signature:
-* void XUsbPs_NakIntrDisable(XUsbPs *InstancePtr, u32 NakIntrMask)
-*
-******************************************************************************/
-#define XUsbPs_NakIntrDisable(InstancePtr, NakIntrMask) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
-
-
-/*****************************************************************************/
-/**
-* This function clears the endpoint NAK interrupts status defined by the
-* bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be cleared.
-*
-* @note C-style signature:
-* void XUsbPs_NakIntrClear(XUsbPs *InstancePtr, u32 NakIntrMask)
-*
-******************************************************************************/
-#define XUsbPs_NakIntrClear(InstancePtr, NakIntrMask) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_EPNAKISR_OFFSET, NakIntrMask)
-
-
-
-/*****************************************************************************/
-/**
-* This macro sets the Interrupt Threshold value in the control register
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param Threshold is the Interrupt threshold to be set.
-* Allowed values:
-* - XUSBPS_CMD_ITHRESHOLD_0 - Immediate interrupt
-* - XUSBPS_CMD_ITHRESHOLD_1 - 1 Frame
-* - XUSBPS_CMD_ITHRESHOLD_2 - 2 Frames
-* - XUSBPS_CMD_ITHRESHOLD_4 - 4 Frames
-* - XUSBPS_CMD_ITHRESHOLD_8 - 8 Frames
-* - XUSBPS_CMD_ITHRESHOLD_16 - 16 Frames
-* - XUSBPS_CMD_ITHRESHOLD_32 - 32 Frames
-* - XUSBPS_CMD_ITHRESHOLD_64 - 64 Frames
-*
-* @note
-* C-style signature:
-* void XUsbPs_SetIntrThreshold(XUsbPs *InstancePtr, u8 Threshold)
-*
-******************************************************************************/
-#define XUsbPs_SetIntrThreshold(InstancePtr, Threshold) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_CMD_OFFSET, (Threshold))\
-
-
-/*****************************************************************************/
-/**
-* This macro sets the Tripwire bit in the USB command register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_SetTripwire(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_SetSetupTripwire(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, \
- XUSBPS_CMD_SUTW_MASK)
-
-
-/*****************************************************************************/
-/**
-* This macro clears the Tripwire bit in the USB command register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_ClrTripwire(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_ClrSetupTripwire(InstancePtr) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, \
- XUSBPS_CMD_SUTW_MASK)
-
-
-/*****************************************************************************/
-/**
-* This macro checks if the Tripwire bit in the USB command register is set.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @return
-* - TRUE: The tripwire bit is still set.
-* - FALSE: The tripwire bit has been cleared.
-*
-* @note C-style signature:
-* int XUsbPs_TripwireIsSet(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_SetupTripwireIsSet(InstancePtr) \
- (XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_CMD_OFFSET) & \
- XUSBPS_CMD_SUTW_MASK ? TRUE : FALSE)
-
-
-/******************************************************************************
-*
-* GENERAL REGISTER / BIT MANIPULATION MACROS
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-* This macro sets the given bit mask in the register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param RegOffset is the register offset to be written.
-* @param Bits is the Bits to be set in the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XUsbPs_SetBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
-*
-*****************************************************************************/
-#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- RegOffset) | (Bits));
-
-
-/****************************************************************************/
-/**
-*
-* This macro clears the given bits in the register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param RegOffset is the register offset to be written.
-* @param Bits are the bits to be cleared in the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XUsbPs_ClrBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
-*
-*****************************************************************************/
-#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- RegOffset) & ~(Bits));
-
-
-/************************** Function Prototypes ******************************/
-
-/**
- * Setup / Initialize functions.
- *
- * Implemented in file xusbps.c
- */
-int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
- const XUsbPs_Config *ConfigPtr, u32 BaseAddress);
-
-int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr,
- const XUsbPs_DeviceConfig *CfgPtr);
-
-/**
- * Common functions used for DEVICE/HOST mode.
- */
-int XUsbPs_Reset(XUsbPs *InstancePtr);
-
-void XUsbPs_DeviceReset(XUsbPs *InstancePtr);
-
-/**
- * DEVICE mode specific functions.
- */
-int XUsbPs_BusReset(XUsbPs *InstancePtr);
-int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address);
-
-
-/**
- * Handling Suspend and Resume.
- *
- * Implemented in xusbps.c
- */
-int XUsbPs_Suspend(const XUsbPs *InstancePtr);
-int XUsbPs_Resume(const XUsbPs *InstancePtr);
-int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr);
-
-
-/*
- * Functions for managing Endpoints / Transfers
- *
- * Implemented in file xusbps_endpoint.c
- */
-int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum,
- const u8 *BufferPtr, u32 BufferLen);
-int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum,
- const u8 *BufferPtr, u32 BufferLen);
-int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
- u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle);
-void XUsbPs_EpBufferRelease(u32 Handle);
-
-int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
- XUsbPs_EpHandlerFunc CallBackFunc,
- void *CallBackRef);
-s32 XUsbPs_EpSetIsoHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
- XUsbPs_EpIsoHandlerFunc CallBackFunc);
-int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum,
- XUsbPs_SetupData *SetupDataPtr);
-
-int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction);
-
-int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr,
- int EpNum, unsigned short NewDirection, int DirectionChanged);
-
-/*
- * Interrupt handling functions
- *
- * Implemented in file xusbps_intr.c
- */
-void XUsbPs_IntrHandler(void *InstancePtr);
-
-int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
- XUsbPs_IntrHandlerFunc CallBackFunc,
- void *CallBackRef, u32 Mask);
-void XUsbPs_EpGetData(XUsbPs *InstancePtr, u8 EpNum, u32 BufferLen);
-
-s32 XUsbPs_EpDataBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
- u8 *BufferPtr, u32 BufferLen);
-/*
- * Helper functions for static configuration.
- * Implemented in xusbps_sinit.c
- */
-XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceId);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XUSBPS_H */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/82/815de1575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/82/815de1575243001d18b399c1eb9b3628
deleted file mode 100644
index 1a0f044..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/82/815de1575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,242 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xemacps_intr.c
-* @addtogroup emacps_v3_15
-* @{
-*
-* Functions in this file implement general purpose interrupt processing related
-* functionality. See xemacps.h for a detailed description of the driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 First release
-* 1.03a asa 01/24/13 Fix for CR #692702 which updates error handling for
-* Rx errors. Under heavy Rx traffic, there will be a large
-* number of errors related to receive buffer not available.
-* Because of a HW bug (SI #692601), under such heavy errors,
-* the Rx data path can become unresponsive. To reduce the
-* probabilities for hitting this HW bug, the SW writes to
-* bit 18 to flush a packet from Rx DPRAM immediately. The
-* changes for it are done in the function
-* XEmacPs_IntrHandler.
-* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification
-* and 64-bit changes.
-* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 hk 07/27/15 Do not call error handler with '0' error code when
-* there is no error. CR# 869403
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xemacps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
- * Install an asynchronous handler function for the given HandlerType:
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param HandlerType indicates what interrupt handler type is.
- * XEMACPS_HANDLER_DMASEND, XEMACPS_HANDLER_DMARECV and
- * XEMACPS_HANDLER_ERROR.
- * @param FuncPointer is the pointer to the callback function
- * @param CallBackRef is the upper layer callback reference passed back when
- * when the callback function is invoked.
- *
- * @return
- *
- * None.
- *
- * @note
- * There is no assert on the CallBackRef since the driver doesn't know what
- * it is.
- *
- *****************************************************************************/
-LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
- void *FuncPointer, void *CallBackRef)
-{
- LONG Status;
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(FuncPointer != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- switch (HandlerType) {
- case XEMACPS_HANDLER_DMASEND:
- Status = (LONG)(XST_SUCCESS);
- InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
- InstancePtr->SendRef = CallBackRef;
- break;
- case XEMACPS_HANDLER_DMARECV:
- Status = (LONG)(XST_SUCCESS);
- InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
- InstancePtr->RecvRef = CallBackRef;
- break;
- case XEMACPS_HANDLER_ERROR:
- Status = (LONG)(XST_SUCCESS);
- InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
- InstancePtr->ErrorRef = CallBackRef;
- break;
- default:
- Status = (LONG)(XST_INVALID_PARAM);
- break;
- }
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* Master interrupt handler for EMAC driver. This routine will query the
-* status of the device, bump statistics, and invoke user callbacks.
-*
-* This routine must be connected to an interrupt controller using OS/BSP
-* specific methods.
-*
-* @param XEmacPsPtr is a pointer to the XEMACPS instance that has caused the
-* interrupt.
-*
-******************************************************************************/
-void XEmacPs_IntrHandler(void *XEmacPsPtr)
-{
- u32 RegISR;
- u32 RegSR;
- u32 RegCtrl;
- u32 RegQ1ISR = 0U;
- XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-
- /* This ISR will try to handle as many interrupts as it can in a single
- * call. However, in most of the places where the user's error handler
- * is called, this ISR exits because it is expected that the user will
- * reset the device in nearly all instances.
- */
- RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_ISR_OFFSET);
-
- /* Read Transmit Q1 ISR */
-
- if (InstancePtr->Version > 2)
- RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_INTQ1_STS_OFFSET);
-
- /* Clear the interrupt status register */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
- RegISR);
-
- /* Receive complete interrupt */
- if ((RegISR & XEMACPS_IXR_FRAMERX_MASK) != 0x00000000U) {
- /* Clear RX status register RX complete indication but preserve
- * error bits if there is any */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_RXSR_OFFSET,
- ((u32)XEMACPS_RXSR_FRAMERX_MASK |
- (u32)XEMACPS_RXSR_BUFFNA_MASK));
- InstancePtr->RecvHandler(InstancePtr->RecvRef);
- }
-
- /* Transmit Q1 complete interrupt */
- if ((InstancePtr->Version > 2) &&
- ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
- /* Clear TX status register TX complete indication but preserve
- * error bits if there is any */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_INTQ1_STS_OFFSET,
- XEMACPS_INTQ1SR_TXCOMPL_MASK);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_TXSR_OFFSET,
- ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
- (u32)XEMACPS_TXSR_USEDREAD_MASK));
- InstancePtr->SendHandler(InstancePtr->SendRef);
- }
-
- /* Transmit complete interrupt */
- if ((RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U) {
- /* Clear TX status register TX complete indication but preserve
- * error bits if there is any */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_TXSR_OFFSET,
- ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
- (u32)XEMACPS_TXSR_USEDREAD_MASK));
- InstancePtr->SendHandler(InstancePtr->SendRef);
- }
-
- /* Receive error conditions interrupt */
- if ((RegISR & XEMACPS_IXR_RX_ERR_MASK) != 0x00000000U) {
- /* Clear RX status register */
- RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_RXSR_OFFSET);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_RXSR_OFFSET, RegSR);
-
- /* Fix for CR # 692702. Write to bit 18 of net_ctrl
- * register to flush a packet out of Rx SRAM upon
- * an error for receive buffer not available. */
- if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
- RegCtrl =
- XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET);
- RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCTRL_OFFSET, RegCtrl);
- }
-
- if(RegSR != 0) {
- InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
- XEMACPS_RECV, RegSR);
- }
- }
-
- /* When XEMACPS_IXR_TXCOMPL_MASK is flagged, XEMACPS_IXR_TXUSED_MASK
- * will be asserted the same time.
- * Have to distinguish this bit to handle the real error condition.
- */
- /* Transmit Q1 error conditions interrupt */
- if ((InstancePtr->Version > 2) &&
- ((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
- ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
- /* Clear Interrupt Q1 status register */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_INTQ1_STS_OFFSET, RegQ1ISR);
- InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
- RegQ1ISR);
- }
-
- /* Transmit error conditions interrupt */
- if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
- (!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
- /* Clear TX status register */
- RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_TXSR_OFFSET);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_TXSR_OFFSET, RegSR);
- InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
- RegSR);
- }
-
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/82/90ea53575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/82/90ea53575243001d18b399c1eb9b3628
deleted file mode 100644
index 841a52b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/82/90ea53575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,53 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file sd.h
-*
-* This file contains the interface for the Secure Digital (SD) card
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a bh 03/10/11 Initial release
-* 7.00a kc 10/18/13 Integrated SD/MMC driver
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00 drg/jz 01/12/10 First Release
-* 1.03a sg 09/04/12 Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
-* and XUARTPS_IXR_TTRIG.
-* Modified the names of these defines
-* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
-* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
-* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
-* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
-* 1.05a hk 08/22/13 Added prototype for uart reset and related
-* constant definitions.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
-* 3.6 ms 02/16/18 Updates flow control mode offset value in
-* modem control register.
-*
-*
-*
-******************************************************************************/
-#ifndef XUARTPS_HW_H /* prevent circular inclusions */
-#define XUARTPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets for the UART.
- * @{
- */
-#define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */
-#define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */
-#define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */
-#define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */
-#define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */
-#define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/
-#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */
-#define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */
-#define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */
-#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */
-#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */
-#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */
-#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */
-#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */
-#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */
-#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */
-#define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */
-/* @} */
-
-/** @name Control Register
- *
- * The Control register (CR) controls the major functions of the device.
- *
- * Control Register Bit Definition
- */
-
-#define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */
-#define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */
-#define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */
-#define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */
-#define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */
-#define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */
-#define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */
-#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */
-#define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */
-#define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */
-/* @}*/
-
-
-/** @name Mode Register
- *
- * The mode register (MR) defines the mode of transfer as well as the data
- * format. If this register is modified during transmission or reception,
- * data validity cannot be guaranteed.
- *
- * Mode Register Bit Definition
- * @{
- */
-#define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */
-#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */
-#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */
-#define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */
-#define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */
-#define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */
-#define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */
-#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */
-#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */
-#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */
-#define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */
-#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */
-#define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */
-#define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */
-#define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */
-#define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */
-#define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */
-#define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */
-#define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */
-#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */
-#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */
-#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */
-#define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */
-#define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */
-#define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */
-/* @} */
-
-
-/** @name Interrupt Registers
- *
- * Interrupt control logic uses the interrupt enable register (IER) and the
- * interrupt disable register (IDR) to set the value of the bits in the
- * interrupt mask register (IMR). The IMR determines whether to pass an
- * interrupt to the interrupt status register (ISR).
- * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
- * interrupt. IMR and ISR are read only, and IER and IDR are write only.
- * Reading either IER or IDR returns 0x00.
- *
- * All four registers have the same bit definitions.
- *
- * @{
- */
-#define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */
-#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */
-#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */
-#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */
-#define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */
-#define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */
-#define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */
-#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */
-#define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */
-#define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */
-#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */
-#define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */
-#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */
-#define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */
-#define XUARTPS_IXR_MASK 0x00003FFFU /**< Valid bit mask */
-/* @} */
-
-
-/** @name Baud Rate Generator Register
- *
- * The baud rate generator control register (BRGR) is a 16 bit register that
- * controls the receiver bit sample clock and baud rate.
- * Valid values are 1 - 65535.
- *
- * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
- * in the MR register.
- * @{
- */
-#define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */
-#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */
-#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */
-
-/** @name Baud Divisor Rate register
- *
- * The baud rate divider register (BDIV) controls how much the bit sample
- * rate is divided by. It sets the baud rate.
- * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
- *
- * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
- * the MR_CCLK bit in the MR register.
- * @{
- */
-#define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */
-#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */
-/* @} */
-
-
-/** @name Receiver Timeout Register
- *
- * Use the receiver timeout register (RTR) to detect an idle condition on
- * the receiver data line.
- *
- * @{
- */
-#define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */
-#define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */
-
-/** @name Receiver FIFO Trigger Level Register
- *
- * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
- * which the RX FIFO triggers an interrupt event.
- * @{
- */
-
-#define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */
-#define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */
-#define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */
-/* @} */
-
-/** @name Transmit FIFO Trigger Level Register
- *
- * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
- * which the TX FIFO triggers an interrupt event.
- * @{
- */
-
-#define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */
-#define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */
-/* @} */
-
-/** @name Modem Control Register
- *
- * This register (MODEMCR) controls the interface with the modem or data set,
- * or a peripheral device emulating a modem.
- *
- * @{
- */
-#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */
-#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */
-#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */
-/* @} */
-
-/** @name Modem Status Register
- *
- * This register (MODEMSR) indicates the current state of the control lines
- * from a modem, or another peripheral device, to the CPU. In addition, four
- * bits of the modem status register provide change information. These bits
- * are set to a logic 1 whenever a control input from the modem changes state.
- *
- * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
- * status interrupt is generated and this is reflected in the modem status
- * register.
- *
- * @{
- */
-#define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */
-#define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */
-#define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */
-#define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */
-#define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */
-#define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */
-#define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */
-#define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */
-#define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */
-/* @} */
-
-/** @name Channel Status Register
- *
- * The channel status register (CSR) is provided to enable the control logic
- * to monitor the status of bits in the channel interrupt status register,
- * even if these are masked out by the interrupt mask register.
- *
- * @{
- */
-#define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */
-#define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */
-#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */
-#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */
-#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */
-#define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */
-#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */
-#define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */
-#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */
-#define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */
-/* @} */
-
-/** @name Flow Delay Register
- *
- * Operation of the flow delay register (FLOWDEL) is very similar to the
- * receive FIFO trigger register. An internal trigger signal activates when the
- * FIFO is filled to the level set by this register. This trigger will not
- * cause an interrupt, although it can be read through the channel status
- * register. In hardware flow control mode, RTS is deactivated when the trigger
- * becomes active. RTS only resets when the FIFO level is four less than the
- * level of the flow delay trigger and the flow delay trigger is not activated.
- * A value less than 4 disables the flow delay.
- * @{
- */
-#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */
-/* @} */
-
-/** @name Receiver FIFO Byte Status Register
- *
- * The Receiver FIFO Status register is used to have a continuous
- * monitoring of the raw unmasked byte status information. The register
- * contains frame, parity and break status information for the top
- * four bytes in the RX FIFO.
- *
- * Receiver FIFO Byte Status Register Bit Definition
- * @{
- */
-#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /**< Byte3 Break Error */
-#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /**< Byte3 Frame Error */
-#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /**< Byte3 Parity Error */
-#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /**< Byte2 Break Error */
-#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /**< Byte2 Frame Error */
-#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /**< Byte2 Parity Error */
-#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /**< Byte1 Break Error */
-#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /**< Byte1 Frame Error */
-#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /**< Byte1 Parity Error */
-#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /**< Byte0 Break Error */
-#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /**< Byte0 Frame Error */
-#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /**< Byte0 Parity Error */
-#define XUARTPS_RXBS_MASK 0x00000007U /**< 3 bit RX byte status mask */
-/* @} */
-
-
-/*
- * Defines for backwards compatibility, will be removed
- * in the next version of the driver
- */
-#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD
-#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI
-#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR
-#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS
-
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-* Read a UART register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the base address of the
-* device.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
-*
-******************************************************************************/
-#define XUartPs_ReadReg(BaseAddress, RegOffset) \
- Xil_In32((BaseAddress) + (u32)(RegOffset))
-
-/***************************************************************************/
-/**
-* Write a UART register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the base address of the
-* device.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u16 RegisterValue)
-*
-******************************************************************************/
-#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
-
-/****************************************************************************/
-/**
-* Determine if there is receive data in the receiver and/or FIFO.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return TRUE if there is receive data, FALSE otherwise.
-*
-* @note C-Style signature:
-* u32 XUartPs_IsReceiveData(u32 BaseAddress)
-*
-******************************************************************************/
-#define XUartPs_IsReceiveData(BaseAddress) \
- !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
- (u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
-
-/****************************************************************************/
-/**
-* Determine if a byte of data can be sent with the transmitter.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the
-* FIFO.
-*
-* @note C-Style signature:
-* u32 XUartPs_IsTransmitFull(u32 BaseAddress)
-*
-******************************************************************************/
-#define XUartPs_IsTransmitFull(BaseAddress) \
- ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
- (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
-
-/************************** Function Prototypes ******************************/
-
-void XUartPs_SendByte(u32 BaseAddress, u8 Data);
-
-u8 XUartPs_RecvByte(u32 BaseAddress);
-
-void XUartPs_ResetHw(u32 BaseAddress);
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/83/1084a1595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/83/1084a1595243001d18b399c1eb9b3628
deleted file mode 100644
index 4b289a7..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/83/1084a1595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,43 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_hal.h
-*
-* Contains all the HAL header files.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/28/09 Initial release
-*
-*
-*
-* @note
-*
-******************************************************************************/
-
-#ifndef XIL_HAL_H
-#define XIL_HAL_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xil_cache.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-#include "xil_exception.h"
-#include "xil_types.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/83/b0afde555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/83/b0afde555243001d18b399c1eb9b3628
deleted file mode 100644
index a224878..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/83/b0afde555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,454 +0,0 @@
-;******************************************************************************
-; Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-; SPDX-License-Identifier: MIT
-;*****************************************************************************
-;****************************************************************************
-;**
-; @file boot.S
-;
-; This file contains the initial startup code for the Cortex A9 processor
-;
-;
-; MODIFICATION HISTORY:
-;
-; Ver Who Date Changes
-; ----- ------- -------- ---------------------------------------------------
-; 1.00a ecm/sdm 10/20/09 Initial version
-; 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
-; 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
-; register settings.
-; 3.06a asa 06/17/12 Modified the TTBR settings and L2 Cache auxiliary
-; register settings.
-; 3.07a sgd 07/05/12 Updated with reset and start Global Timer
-; 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
-; 4.2 pkp 06/19/14 Enabled asynchronous abort exception
-; 4.2 pkp 08/04/14 Removed PEEP board related code which contained
-; initialization of uart smc nor and sram
-; 5.0 pkp 16/12/14 Modified initialization code to enable scu after
-; MMU is enabled and removed incorrect initialization
-; of TLB lockdown register to fix CR#830580
-; 5.1 pkp 05/13/15 Changed the initialization order so to first invalidate
-; caches and TLB, enable MMU and caches, then enable SMP
-; bit in ACTLR. L2Cache invalidation and enabling of L2Cache
-; is done later.
-; 5.4 asa 12/06/15 Added code to initialize SPSR for all relevant modes.
-; 6.0 mus 04/08/16 Added code to detect zynq-7000 base silicon configuration and
-; attempt to enable dual core behavior on single cpu zynq-7000s devices
-; is prevented from corrupting system behavior.
-; 6.0 mus 24/08/16 Check CPU core before putting cpu1 to reset for single core
-; zynq-7000s devices
-; 6.6 srm 10/25/17 Added timer configuration using XTime_StartTTCTimer API.
-* Now the TTC instance as specified by the user will be
-* started.
-;
-;
-; @note
-;
-; None.
-;
-;****************************************************************************
-
-
-
-#include "xparameters.h"
-#include "xil_errata.h"
-
-#define UART_BAUDRATE 115200
-
- EXPORT _prestart
- EXPORT _boot
-
- IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
- IMPORT |Image$$IRQ_STACK$$ZI$$Limit|
- IMPORT |Image$$SPV_STACK$$ZI$$Limit|
- IMPORT |Image$$ABORT_STACK$$ZI$$Limit|
- IMPORT MMUTable
- IMPORT _vector_table
- IMPORT __main
- IMPORT Xil_ExceptionInit
- IMPORT XTime_SetTime
-#if defined SLEEP_TIMER_BASEADDR
- IMPORT XTime_StartTTCTimer
-#endif
-
-PSS_L2CC_BASE_ADDR EQU 0xF8F02000
-PSS_SLCR_BASE_ADDR EQU 0xF8000000
-
-L2CCWay EQU (PSS_L2CC_BASE_ADDR + 0x077C) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)
-L2CCSync EQU (PSS_L2CC_BASE_ADDR + 0x0730) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)
-L2CCCrtl EQU (PSS_L2CC_BASE_ADDR + 0x0100) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)
-L2CCAuxCrtl EQU (PSS_L2CC_BASE_ADDR + 0x0104) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)
-L2CCTAGLatReg EQU (PSS_L2CC_BASE_ADDR + 0x0108) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)
-L2CCDataLatReg EQU (PSS_L2CC_BASE_ADDR + 0x010C) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)
-L2CCIntClear EQU (PSS_L2CC_BASE_ADDR + 0x0220) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)
-L2CCIntRaw EQU (PSS_L2CC_BASE_ADDR + 0x021C) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)
-
-SLCRlockReg EQU (PSS_SLCR_BASE_ADDR + 0x04) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/
-SLCRUnlockReg EQU (PSS_SLCR_BASE_ADDR + 0x08) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/
-SLCRL2cRamReg EQU (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/
-SLCRCPURSTReg EQU (0xF8000000 + 0x244) ;(XPS_SYS_CTRL_BASEADDR + A9_CPU_RST_CTRL_OFFSET)
-EFUSEStaus EQU (0xF800D000 + 0x10) ;(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)
-
-SLCRlockKey EQU 0x767B /* SLCR lock key */
-SLCRUnlockKey EQU 0xDF0D /* SLCR unlock key */
-SLCRL2cRamConfig EQU 0x00020202 /* SLCR L2C ram configuration */
-
-CRValMmuCac EQU 2_01000000000101 ; Enable IDC, and MMU
-CRValHiVectorAddr EQU 2_10000000000000 ; Set the Vector address to high, 0xFFFF0000
-
-L2CCAuxControl EQU 0x72360000 ; Enable all prefetching, Way Size (16 KB) and High Priority for SO and Dev Reads Enable
-L2CCControl EQU 0x01 ; Enable L2CC
-L2CCTAGLatency EQU 0x0111 ; 7 Cycles of latency for TAG RAM
-L2CCDataLatency EQU 0x0121 ; 7 Cycles of latency for DATA RAM
-
-FPEXC_EN EQU 0x40000000 ; FPU enable bit, (1 << 30)
-
- AREA |.boot|, CODE
- PRESERVE8
-
-
-; this initializes the various processor modes
-
-_prestart
-_boot
-
-#if XPAR_CPU_ID==0
-; only allow cp0 through
- mrc p15,0,r1,c0,c0,5
- and r1, r1, #0xf
- cmp r1, #0
- beq CheckEFUSE
-EndlessLoop0
- wfe
- b EndlessLoop0
-
-CheckEFUSE
- ldr r0,=EFUSEStaus
- ldr r1,[r0] ; Read eFuse setting
- ands r1,r1,#0x80 ; Check whether device is having single core
- beq OKToRun
- ; Single core device, reset CPU1
- ldr r0,=SLCRUnlockReg ; Load SLCR base address base + unlock register
- ldr r1,=SLCRUnlockKey ; set unlock key
- str r1, [r0] ; Unlock SLCR
-
- ldr r0,=SLCRCPURSTReg
- ldr r1,[r0] ; Read CPU Software Reset Control register
- orr r1,r1,#0x22
- str r1,[r0] ; Reset CPU1
-
- ldr r0,=SLCRlockReg ; Load SLCR base address base + lock register
- ldr r1,=SLCRlockKey ; set lock key
- str r1, [r0] ; lock SLCR
-
-#elif XPAR_CPU_ID==1
-; only allow cpu1 through
- mrc p15,0,r1,c0,c0,5
- and r1, r1, #0xf
- cmp r1, #1
- beq CheckEFUSE1
- b EndlessLoop1
-
-CheckEFUSE1
- ldr r0,=EFUSEStaus
- ldr r1,[r0] ; Read eFuse setting
- ands r1,r1,#0x80 ; Check whether device is having single core
- beq OKToRun
-EndlessLoop1
- wfe
- b EndlessLoop1
-#endif
-
-OKToRun
- mrc p15, 0, r0, c0, c0, 0 /* Get the revision */
- and r5, r0, #0x00f00000
- and r6, r0, #0x0000000f
- orr r6, r6, r5, lsr #20-4
-
-#ifdef CONFIG_ARM_ERRATA_742230
- cmp r6, #0x22 /* only present up to r2p2 */
- mrcle p15, 0, r10, c15, c0, 1 /* read diagnostic register */
- orrle r10, r10, #1 << 4 /* set bit #4 */
- mcrle p15, 0, r10, c15, c0, 1 /* write diagnostic register */
-#endif
-
-#ifdef CONFIG_ARM_ERRATA_743622
- teq r5, #0x00200000 /* only present in r2p* */
- mrceq p15, 0, r10, c15, c0, 1 /* read diagnostic register */
- orreq r10, r10, #1 << 6 /* set bit #6 */
- mcreq p15, 0, r10, c15, c0, 1 /* write diagnostic register */
-#endif
-
- /* set VBAR to the _vector_table address in scatter file */
- ldr r0, =_vector_table
- mcr p15, 0, r0, c12, c0, 0
-
- ;invalidate scu
- ldr r7, =0xf8f0000c
- ldr r6, =0xffff
- str r6, [r7]
-
- ;Invalidate caches and TLBs
- mov r0,#0 ; r0 = 0
- mcr p15, 0, r0, c8, c7, 0 ; invalidate TLBs
- mcr p15, 0, r0, c7, c5, 0 ; invalidate icache
- mcr p15, 0, r0, c7, c5, 6 ; Invalidate branch predictor array
- bl invalidate_dcache ; invalidate dcache
-
- ; Disable MMU, if enabled
- mrc p15, 0, r0, c1, c0, 0 ; read CP15 register 1
- bic r0, r0, #0x1 ; clear bit 0
- mcr p15, 0, r0, c1, c0, 0 ; write value back
-
-#ifdef SHAREABLE_DDR
- ; Mark the entire DDR memory as shareable
- ldr r3, =0x3ff ; 1024 entries to cover 1G DDR
- ldr r0, =TblBase ; MMU Table address in memory
- ldr r2, =0x15de6 ; S=1, TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1
-shareable_loop:
- str r2, [r0] ; write the entry to MMU table
- add r0, r0, #0x4 ; next entry in the table
- add r2, r2, #0x100000 ; next section
- subs r3, r3, #1
- bge shareable_loop ; loop till 1G is covered
-#endif
-
- mrs r0, cpsr ; get the current PSR
- mvn r1, #0x1f ; set up the irq stack pointer
- and r2, r1, r0
- orr r2, r2, #0x12 ; IRQ mode
- msr apsr, r2 ; was cpsr, apsr is considered synonym
- ldr r13,=|Image$$IRQ_STACK$$ZI$$Limit| ; IRQ stack pointer
- bic r2, r2, #(0x1 << 9) ; Set EE bit to little-endian
- msr spsr_fsxc,r2
-
- mrs r0, cpsr ; get the current PSR
- mvn r1, #0x1f ; set up the supervisor stack pointer
- and r2, r1, r0
- orr r2, r2, #0x13 ; supervisor mode
- msr apsr, r2 ; was cpsr, apsr is considered synonym
- ldr r13,=|Image$$SPV_STACK$$ZI$$Limit| ; Supervisor stack pointer
- bic r2, r2, #(0x1 << 9) ; Set EE bit to little-endian
- msr spsr_fsxc,r2
-
- mrs r0, cpsr ; get the current PSR
- mvn r1, #0x1f ; set up the Abort stack pointer
- and r2, r1, r0
- orr r2, r2, #0x17 ; Abort mode
- msr apsr, r2 ; was cpsr, apsr is considered synonym
- ldr r13,=|Image$$ABORT_STACK$$ZI$$Limit| ; Abort stack pointer
- bic r2, r2, #(0x1 << 9) ; Set EE bit to little-endian
- msr spsr_fsxc,r2
-
- mrs r0, cpsr ; get the current PSR
- mvn r1, #0x1f ; set up the system stack pointer
- and r2, r1, r0
- orr r2, r2, #0x1f ; SYS mode
- msr apsr, r2 ; was cpsr, apsr is considered synonym
- ldr r13,=|Image$$ARM_LIB_STACK$$ZI$$Limit| ; SYS stack pointer
-
- ;set scu enable bit in scu
- ldr r7, =0xf8f00000
- ldr r0, [r7]
- orr r0, r0, #0x1
- str r0, [r7]
-
- ; enable MMU and cache
-
- ldr r0,=MMUTable ; Load MMU translation table base
- orr r0, r0, #0x5B ; Outer-cacheable, WB
- mcr p15, 0, r0, c2, c0, 0 ; TTB0
-
- mvn r0,#0
- mcr p15,0,r0,c3,c0,0
-
- ; Enable mmu, icahce and dcache
- ldr r0,=CRValMmuCac
-
- mcr p15,0,r0,c1,c0,0 ; Enable cache and MMU
- dsb ; dsb allow the MMU to start up
- isb ; isb flush prefetch buffer
-
-
- ; Write to ACTLR
- mrc p15, 0,r0, c1, c0, 1 ; Read ACTLR
- orr r0, r0, #(0x01 << 6) ; SMP bit
- orr r0, r0, #(0x01 ) ; Cache/TLB maintenance broadcast
- mcr p15, 0,r0, c1, c0, 1 ; Write ACTLR
-
-; Invalidate L2 Cache and initialize L2 Cache
-; For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux)
-#if USE_AMP!=1
- ldr r0,=L2CCCrtl ; Load L2CC base address base + control register
- mov r1, #0 ; force the disable bit
- str r1, [r0] ; disable the L2 Caches
-
- ldr r0,=L2CCAuxCrtl ; Load L2CC base address base + Aux control register
- ldr r1,[r0] ; read the register
- ldr r2,=L2CCAuxControl ; set the default bits
- orr r1,r1,r2
- str r1, [r0] ; store the Aux Control Register
-
- ldr r0,=L2CCTAGLatReg ; Load L2CC base address base + TAG Latency address
- ldr r1,=L2CCTAGLatency ; set the latencies for the TAG
- str r1, [r0] ; store the TAG Latency register Register
-
- ldr r0,=L2CCDataLatReg ; Load L2CC base address base + Data Latency address
- ldr r1,=L2CCDataLatency ; set the latencies for the Data
- str r1, [r0] ; store the Data Latency register Register
-
- ldr r0,=L2CCWay ; Load L2CC base address base + way register
- ldr r2, =0xFFFF
- str r2, [r0] ; force invalidate
-
- ldr r0,=L2CCSync ; need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET
- ; Load L2CC base address base + sync register
- ; poll for completion
-Sync
- ldr r1, [r0]
- cmp r1, #0
- bne Sync
-
- ldr r0,=L2CCIntRaw ; clear pending interrupts
- ldr r1,[r0]
- ldr r0,=L2CCIntClear
- str r1,[r0]
-
- ldr r0,=SLCRUnlockReg ;Load SLCR base address base + unlock register
- ldr r1,=SLCRUnlockKey ;set unlock key
- str r1, [r0] ;Unlock SLCR
-
- ldr r0,=SLCRL2cRamReg ;Load SLCR base address base + l2c Ram Control register
- ldr r1,=SLCRL2cRamConfig ;set the configuration value
- str r1, [r0] ;store the L2c Ram Control Register
-
- ldr r0,=SLCRlockReg ;Load SLCR base address base + lock register
- ldr r1,=SLCRlockKey ;set lock key
- str r1, [r0] ;lock SLCR
-
- ldr r0,=L2CCCrtl ; Load L2CC base address base + control register
- ldr r1,[r0] ; read the register
- mov r2, #L2CCControl ; set the enable bit
- orr r1,r1,r2
- str r1, [r0] ; enable the L2 Caches
-#endif
-
- mov r0, r0
- mrc p15, 0, r1, c1, c0, 2 ; read cp access control register (CACR) into r1
- orr r1, r1, #(0xf << 20) ; enable full access for p10 & p11
- mcr p15, 0, r1, c1, c0, 2 ; write back into CACR
-
- ; enable vfp
- fmrx r1, FPEXC ; read the exception register
- orr r1,r1, #FPEXC_EN ; set VFP enable bit, leave the others in orig state
- fmxr FPEXC, r1 ; write back the exception register
-
- mrc p15, 0, r0, c1, c0, 0 ; flow prediction enable
- orr r0, r0, #(0x01 << 11) ; #0x8000
- mcr p15,0,r0,c1,c0,0
-
- mrc p15, 0, r0, c1, c0, 1 ; read Auxiliary Control Register
- orr r0, r0, #(0x1 << 2) ; enable Dside prefetch
- orr r0, r0, #(0x1 << 1) ; enable L2 prefetch
- mcr p15, 0, r0, c1, c0, 1 ; write Auxiliary Control Register
-
- mrs r0, cpsr /* get the current PSR */
- bic r0, r0, #0x100 /* enable asynchronous abort exception */
- msr cpsr_xsf, r0
-
-; Clear cp15 regs with unknown reset values
- mov r0, #0x0
- mcr p15, 0, r0, c5, c0, 0 ; DFSR
- mcr p15, 0, r0, c5, c0, 1 ; IFSR
- mcr p15, 0, r0, c6, c0, 0 ; DFAR
- mcr p15, 0, r0, c6, c0, 2 ; IFAR
- mcr p15, 0, r0, c9, c13, 2 ; PMXEVCNTR
- mcr p15, 0, r0, c13, c0, 2 ; TPIDRURW
- mcr p15, 0, r0, c13, c0, 3 ; TPIDRURO
-
-; Reset and start Cycle Counter
- mov r2, #0x80000000 ; clear overflow
- mcr p15, 0, r2, c9, c12, 3
- mov r2, #0xd ; D, C, E
- mcr p15, 0, r2, c9, c12, 0
- mov r2, #0x80000000 ; enable cycle counter
- mcr p15, 0, r2, c9, c12, 1
-
-; Reset and start Global Timer
- mov r0, #0x0
- mov r1, #0x0
- bl XTime_SetTime
-
-; Reset and start Triple Timer counter
- #if defined SLEEP_TIMER_BASEADDR
- bl XTime_StartTTCTimer
- #endif
-
-#ifdef PROFILING /* defined in Makefile */
- /* Setup profiling stuff */
- bl _profile_init
-#endif /* PROFILING */
-
-; make sure argc and argv are valid
- mov r0, #0
- mov r1, #0
- b __main ; jump to C startup code
- and r0, r0, r0 ; no op
-
-Ldone b Ldone ; Paranoia: we should never get here
-
-
-; *************************************************************************
-; *
-; * invalidate_dcache - invalidate the entire d-cache by set/way
-; *
-; * Note: for Cortex-A9, there is no cp instruction for invalidating
-; * the whole D-cache. Need to invalidate each line.
-; *
-; *************************************************************************
-
-invalidate_dcache
- mrc p15, 1, r0, c0, c0, 1 ; read CLIDR
- ands r3, r0, #0x7000000
- mov r3, r3, lsr #23 ; cache level value (naturally aligned)
- beq finished
- mov r10, #0 ; start with level 0
-loop1
- add r2, r10, r10, lsr #1 ; work out 3xcachelevel
- mov r1, r0, lsr r2 ; bottom 3 bits are the Cache type for this level
- and r1, r1, #7 ; get those 3 bits alone
- cmp r1, #2
- blt skip ; no cache or only instruction cache at this level
- mcr p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register
- isb ; isb to sync the change to the CacheSizeID reg
- mrc p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register
- and r2, r1, #7 ; extract the line length field
- add r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
- ldr r4, =0x3ff
- ands r4, r4, r1, lsr #3 ; r4 is the max number on the way size (right aligned)
- clz r5, r4 ; r5 is the bit position of the way size increment
- ldr r7, =0x7fff
- ands r7, r7, r1, lsr #13 ; r7 is the max number of the index size (right aligned)
-loop2
- mov r9, r4 ; r9 working copy of the max way size (right aligned)
-loop3
- orr r11, r10, r9, lsl r5 ; factor in the way number and cache number into r11
- orr r11, r11, r7, lsl r2 ; factor in the index number
- mcr p15, 0, r11, c7, c6, 2 ; invalidate by set/way
- subs r9, r9, #1 ; decrement the way number
- bge loop3
- subs r7, r7, #1 ; decrement the index
- bge loop2
-skip
- add r10, r10, #2 ; increment the cache number
- cmp r3, r10
- bgt loop1
-
-finished
- mov r10, #0 ; switch back to cache level 0
- mcr p15, 2, r10, c0, c0, 0 ; select current cache level in cssr
- isb
-
- bx lr
-
- END
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/83/b1b384565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/83/b1b384565243001d18b399c1eb9b3628
deleted file mode 100644
index c38e742..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/83/b1b384565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,29 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-* Disable exceptions on microblaze.
-*
-*
-******************************************************************************/
-
-#include "xparameters.h"
-
- .text
- .globl microblaze_disable_exceptions
- .ent microblaze_disable_exceptions
- .align 2
-microblaze_disable_exceptions:
-#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
- rtsd r15, 8
- msrclr r0, 0x100
-#else
- mfs r4, rmsr;
- andi r4, r4, ~(0x100); /* Turn OFF the EE bit */
- mts rmsr, r4;
- rtsd r15, 8;
- nop;
-#endif
-.end microblaze_disable_exceptions
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/83/e0f6bc555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/83/e0f6bc555243001d18b399c1eb9b3628
deleted file mode 100644
index becf67e..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/83/e0f6bc555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,169 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file vectors.c
-*
-* This file contains the C level vectors for the ARM Cortex A9 core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 10/20/09 Initial version, moved over from bsp area
-* 6.0 mus 27/07/16 Consolidated vectors for a53,a9 and r5 processor
-* and added UndefinedException for a53 32 bit and r5
-* processor
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "xil_exception.h"
-#include "vectors.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-typedef struct {
- Xil_ExceptionHandler Handler;
- void *Data;
-} XExc_VectorTableEntry;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-extern XExc_VectorTableEntry XExc_VectorTable[];
-
-/************************** Function Prototypes ******************************/
-
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the FIQ interrupt called from the vectors.s
-* file.
-*
-* @return None.
-*
-******************************************************************************/
-void FIQInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[
- XIL_EXCEPTION_ID_FIQ_INT].Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the IRQ interrupt called from the vectors.s
-* file.
-*
-* @return None.
-*
-******************************************************************************/
-void IRQInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[
- XIL_EXCEPTION_ID_IRQ_INT].Data);
-}
-
-#if !defined (__aarch64__)
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the Undefined exception called from the
-* vectors.s file.
-*
-* @return None.
-*
-******************************************************************************/
-void UndefinedException(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_UNDEFINED_INT].Handler(XExc_VectorTable[
- XIL_EXCEPTION_ID_UNDEFINED_INT].Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the SW Interrupt called from the vectors.s
-* file.
-*
-* @return None.
-*
-******************************************************************************/
-void SWInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_SWI_INT].Handler(XExc_VectorTable[
- XIL_EXCEPTION_ID_SWI_INT].Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the DataAbort Interrupt called from the
-* vectors.s file.
-*
-* @return None.
-*
-******************************************************************************/
-void DataAbortInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Handler(
- XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the PrefetchAbort Interrupt called from the
-* vectors.s file.
-*
-* @return None.
-*
-******************************************************************************/
-void PrefetchAbortInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler(
- XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data);
-}
-#else
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the Synchronous Interrupt called from the vectors.s
-* file.
-*
-* @return None.
-*
-******************************************************************************/
-void SynchronousInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_SYNC_INT].Handler(XExc_VectorTable[
- XIL_EXCEPTION_ID_SYNC_INT].Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the SError Interrupt called from the
-* vectors.s file.
-*
-* @return None.
-*
-******************************************************************************/
-void SErrorInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Handler(
- XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Data);
-}
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/83/f0e0f3515243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/83/f0e0f3515243001d18b399c1eb9b3628
deleted file mode 100644
index 8b31d48..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/83/f0e0f3515243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,19 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/84/10cd09585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/84/10cd09585243001d18b399c1eb9b3628
deleted file mode 100644
index 0e77af1..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/84/10cd09585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1305 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xscugic.c
-* @addtogroup scugic_v4_6
-* @{
-*
-* Contains required functions for the XScuGic driver for the Interrupt
-* Controller. See xscugic.h for a detailed description of the driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- --------------------------------------------------------
-* 1.00a drg 01/19/10 First release
-* 1.01a sdm 11/09/11 Changes are made in function XScuGic_CfgInitialize
-* Since entry is now made as pointer in the XScuGic
-* structure, necessary changes are made.
-* The HandlerTable can now be populated through the low
-* level routine XScuGic_RegisterHandler added in this
-* release. Hence necessary checks are added not to
-* overwrite the HandlerTable entries in function
-* XScuGic_CfgInitialize.
-* 1.03a srt 02/27/13 Added APIs
-* -XScuGic_SetPriTrigTypeByDistAddr()
-* -XScuGic_GetPriTrigTypeByDistAddr()
-* Removed Offset calculation macros, defined in _hw.h
-* (CR 702687)
-* added support to direct interrupts to the appropriate
-* CPU Earlier interrupts were directed to CPU1
-* (hard coded).Now depending upon the CPU selected by the
-* user(xparameters.h), interrupts will be directed to
-* the relevant CPU. This fixes CR 699688.
-*
-* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
-* XScuGic_CfgInitialize. Fix for CR#704400 to remove
-* warnings.
-* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
-* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
-* This is fix for CR#705621.
-* 1.06a asa 16/11/13 Fix for CR#749178. Assignment for EffectiveAddr
-* in function XScuGic_CfgInitialize is removed as it was
-* a bug.
-* 3.00 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
-* 3.01 pkp 06/19/15 Added XScuGic_InterruptMaptoCpu API for an interrupt
-* target CPU mapping
-* 3.02 pkp 11/09/15 Modified DistributorInit function for AMP case to add
-* the current cpu to interrupt processor targets registers
-* 3.2 asa 02/29/16 Modified DistributorInit function for Zynq AMP case. The
-* distributor is left uninitialized for Zynq AMP. It is
-* assumed that the distributor will be initialized by
-* Linux master. However for CortexR5 case, the earlier code
-* is left unchanged where the interrupt processor target
-* registers in the distributor is initialized with the
-* corresponding CPU ID on which the application built over
-* the scugic driver runs. These changes fix CR#937243.
-* 3.3 pkp 05/12/16 Modified XScuGic_InterruptMaptoCpu to write proper value
-* to interrupt target register to fix CR#951848
-*
-* 3.4 asa 04/07/16 Created a new static function DoDistributorInit to
-* simplify the flow and avoid code duplication. Changes are
-* made for USE_AMP use case for R5. In a scenario
-* (in R5 split mode) when one R5 is operating with A53 in
-* open amp config and other R5 running baremetal app, the
-* existing code had the potential to stop the whole AMP
-* solution to work (if for some reason the R5 running the
-* baremetal app tasked to initialize the Distributor hangs
-* or crashes before initializing).Changes are made so that
-* the R5 under AMP first checks if the distributor is
-* enabled or not and if not, it does the standard
-* Distributor initialization.This fixes the CR#952962.
-* 3.4 mus 09/08/16 Added assert to avoid invalid access of GIC from CPUID 1
-* for single core zynq-7000s
-* 3.5 mus 10/05/16 Modified DistributorInit function to avoid
-* re-initialization of distributor, If it is already
-* initialized by other CPU.
-* 3.5 pkp 10/17/16 Modified XScuGic_InterruptMaptoCpu to correct the CPU Id
-* value and properly mask interrupt target processor value
-* to modify interrupt target processor register for a given
-* interrupt ID and cpu ID
-* 3.6 pkp 20/01/17 Added new API XScuGic_Stop to Disable distributor and
-* interrupts in case they are being used only by current
-* cpu. It also removes current cpu from interrupt target
-* registers for all interrupts.
-* kvn 02/17/17 Add support for changing GIC CPU master at run time.
-* kvn 02/28/17 Make the CpuId as static variable and Added new
-* XScugiC_GetCpuId to access CpuId.
-* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
-* XScuGic_InterruptUnmapFromCpu, These API's can be used
-* by applications to unmap specific/all interrupts from
-* target CPU. It fixes CR#992490.
-* 3.10 mus 07/17/18 Updated file to fix the various coding style issues
-* reported by checkpatch. It fixes CR#1006344.
-* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
-* It fixes CR#1007753.
-* 3.10 mus 09/19/18 Fix cppcheck warnings
-* 4.0 mus 11/22/18 Fixed bugs in software interrupt generation through
-* XScuGic_SoftwareIntr API
-* 4.1 asa 03/30/19 Made changes not to direct each interrupt to all
-* available CPUs by default. This was breaking AMP
-* behavior. Instead every time an interrupt enable
-* request is received, the interrupt was mapped to
-* the respective CPU. There were several other changes
-* made to implement this. This set of changes was to
-* fix CR-1024716.
-* 4.1 mus 06/19/19 Added API's XScuGic_MarkCoreAsleep and
-* XScuGic_MarkCoreAwake to mark processor core as
-* asleep or awake. Fix for CR#1027220.
-* 4.3 mus 10/14/20 Updated XScuGic_Stop for scenarios where USE_AMP flag
-* is set to 1. Now, XScuGic_Stop would not disable
-* distributor for USE_AMP=1, even when SPI interrupts
-* are not being used by other CPU. This update is needed
-* to support scenarios, where master CPU is using only
-* SGI/PPI interrupts. It fixes CR#1079241.
-* 4.5 asa 03/07/21 Added spinlock protection for critical sections in the
-* code. The sections are critical when applications
-* running on separate CPUs (R5s or A9s) try to update
-* the same register. The spinlock mechanism used here
-* used exclusive load and store instructions. To ensure
-* that legacy behavior is not broken, unless someone
-* enables spinlocks explicitely in their applications
-* the existing flow will remain unchanged. On how to
-* enable spinlocks, please refer to the documentations
-* at: lib/bsp/standalone/src/arm/common/gcc/xil_spinlock.c
-* 4.6 sk 08/05/21 Fix scugic Misra-c violations.
-* 4.7 sk 09/14/21 Fix gcc compiler warnings for A72 processor.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xscugic.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-static u32 CpuId = XPAR_CPU_ID; /**< CPU Core identifier */
-
-/************************** Function Prototypes ******************************/
-
-static void StubHandler(void *CallBackRef);
-
-/*****************************************************************************/
-/**
-*
-* DoDistributorInit initializes the distributor of the GIC. The
-* initialization entails:
-*
-* - Write the trigger mode, priority
-* - All interrupt sources are disabled
-* - Enable the distributor
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-static void DoDistributorInit(const XScuGic *InstancePtr)
-{
- u32 Int_Id;
-
-#if defined (GICv3)
- u32 Temp;
-
- Temp = XScuGic_DistReadReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET);
- Temp = (XSCUGIC500_DCTLR_ARE_NS_ENABLE | XSCUGIC500_DCTLR_ARE_S_ENABLE);
- Temp &= ~(XSCUGIC_EN_INT_MASK);
- XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, Temp);
-#else
- XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U);
-#endif
-
- /*
- * Set the security domains in the int_security registers for
- * non-secure interrupts
- * All are secure, so leave at the default. Set to 1 for non-secure
- * interrupts.
- */
-
- /*
- * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
- */
-
- /*
- * 1. The trigger mode in the int_config register
- * Only write to the SPI interrupts, so start at 32
- */
- for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
- Int_Id = Int_Id+16U) {
- /*
- * Each INT_ID uses two bits, or 16 INT_ID per register
- * Set them all to be level sensitive, active HIGH.
- */
- XScuGic_DistWriteReg(InstancePtr,
- XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
- 0U);
- }
-
-
-#define DEFAULT_PRIORITY 0xa0a0a0a0U
- for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
- Int_Id = Int_Id+4U) {
- /*
- * 2. The priority using int the priority_level register
- * The priority_level and spi_target registers use one byte per
- * INT_ID.
- * Write a default value that can be changed elsewhere.
- */
- XScuGic_DistWriteReg(InstancePtr,
- XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
- DEFAULT_PRIORITY);
- }
-
-#if defined (GICv3)
- for (Int_Id = 0U; Int_IdBaseAddress for this parameters, passing the physical
-* address instead.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-*
-* @note None.
-*
-******************************************************************************/
-s32 XScuGic_CfgInitialize(XScuGic *InstancePtr,
- XScuGic_Config *ConfigPtr,
- u32 EffectiveAddr)
-{
- u32 Int_Id;
- (void) EffectiveAddr;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
- /*
- * Check Zynq-7000 base silicon configuration.
- * If it is single CPU configuration then invoke assert for CPU ID 1.
- */
-#ifdef ARMA9
- if (XPAR_CPU_ID == 0x01) {
- Xil_AssertNonvoid((Xil_In32(XPS_EFUSE_BASEADDR
- + EFUSE_STATUS_OFFSET) & EFUSE_STATUS_CPU_MASK) == 0);
- }
-#endif
-
- if(InstancePtr->IsReady != XIL_COMPONENT_IS_READY) {
-
- InstancePtr->IsReady = 0U;
- InstancePtr->Config = ConfigPtr;
-
-
- for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
- Int_Id++) {
- /*
- * Initialize the handler to point to a stub to handle an
- * interrupt which has not been connected to a handler
- * Only initialize it if the handler is 0 which means it
- * was not initialized statically by the tools/user. Set
- * the callback reference to this instance so that
- * unhandled interrupts can be tracked.
- */
- if ((InstancePtr->Config->HandlerTable[Int_Id].Handler
- == (Xil_InterruptHandler)NULL)) {
- InstancePtr->Config->HandlerTable[Int_Id].Handler
- = (Xil_InterruptHandler)StubHandler;
- }
- InstancePtr->Config->HandlerTable[Int_Id].CallBackRef =
- InstancePtr;
- }
-#if defined (GICv3)
- u32 Waker_State;
- Waker_State = XScuGic_ReDistReadReg(InstancePtr,XSCUGIC_RDIST_WAKER_OFFSET);
- XScuGic_ReDistWriteReg(InstancePtr,XSCUGIC_RDIST_WAKER_OFFSET,
- Waker_State & (~ XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK));
- /* Enable system reg interface through ICC_SRE_EL1 */
- #if EL3
- XScuGic_Enable_SystemReg_CPU_Interface_EL3();
- #endif
- XScuGic_Enable_SystemReg_CPU_Interface_EL1();
- isb();
-#endif
- XScuGic_Stop(InstancePtr);
- DistributorInit(InstancePtr);
-#if defined (GICv3)
- XScuGic_set_priority_filter(0xff);
-#else
- CPUInitialize(InstancePtr);
-#endif
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Makes the connection between the Int_Id of the interrupt source and the
-* associated handler that is to run when the interrupt is recognized. The
-* argument provided in this call as the Callbackref is used as the argument
-* for the handler when it is called.
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-* @param Int_Id contains the ID of the interrupt source and should be
-* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-* @param Handler to the handler for that interrupt.
-* @param CallBackRef is the callback reference, usually the instance
-* pointer of the connecting driver.
-*
-* @return
-*
-* - XST_SUCCESS if the handler was connected correctly.
-*
-* @note
-*
-* WARNING: The handler provided as an argument will overwrite any handler
-* that was previously connected.
-*
-****************************************************************************/
-s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
- Xil_InterruptHandler Handler, void *CallBackRef)
-{
- /*
- * Assert the arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
- Xil_AssertNonvoid(Handler != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * The Int_Id is used as an index into the table to select the proper
- * handler
- */
- InstancePtr->Config->HandlerTable[Int_Id].Handler = (Xil_InterruptHandler)Handler;
- InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = CallBackRef;
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Updates the interrupt table with the Null Handler and NULL arguments at the
-* location pointed at by the Int_Id. This effectively disconnects that interrupt
-* source from any handler. The interrupt is disabled also.
-*
-* @param InstancePtr is a pointer to the XScuGic instance to be worked on.
-* @param Int_Id contains the ID of the interrupt source and should
-* be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id)
-{
- u32 Mask;
-
- /*
- * Assert the arguments
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
-
- /*
- * The Int_Id is used to create the appropriate mask for the
- * desired bit position. Int_Id currently limited to 0 - 31
- */
- Mask = (u32)0x00000001U << (Int_Id % 32U);
-
- /*
- * Disable the interrupt such that it won't occur while disconnecting
- * the handler, only disable the specified interrupt id without
- * modifying the other interrupt ids
- */
- XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
- ((Int_Id / 32U) * 4U), Mask);
-
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
- /*
- * Disconnect the handler and connect a stub, the callback reference
- * must be set to this instance to allow unhandled interrupts to be
- * tracked
- */
- InstancePtr->Config->HandlerTable[Int_Id].Handler = (Xil_InterruptHandler)StubHandler;
- InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = InstancePtr;
-}
-
-/*****************************************************************************/
-/**
-*
-* Enables the interrupt source provided as the argument Int_Id. Any pending
-* interrupt condition for the specified Int_Id will occur after this function is
-* called.
-* This API also maps the interrupt to the requesting CPU.
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-* @param Int_Id contains the ID of the interrupt source and should be
-* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id)
-{
- u32 Mask;
- u8 Cpu_Identifier = (u8)CpuId;
-
-#if defined (GICv3)
- u32 Temp;
-#endif
- /*
- * Assert the arguments
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-#if defined (GICv3)
- if (Int_Id < XSCUGIC_SPI_INT_ID_START) {
- XScuGic_InterruptMaptoCpu(InstancePtr, Cpu_Identifier, Int_Id);
-
- Int_Id &= 0x1f;
- Int_Id = 1 << Int_Id;
-
- Temp = XScuGic_ReDistSGIPPIReadReg(InstancePtr,XSCUGIC_RDIST_ISENABLE_OFFSET);
- Temp |= Int_Id;
- XScuGic_ReDistSGIPPIWriteReg(InstancePtr,XSCUGIC_RDIST_ISENABLE_OFFSET,Temp);
- }
-#endif
- XScuGic_InterruptMaptoCpu(InstancePtr, Cpu_Identifier, Int_Id);
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
- /*
- * The Int_Id is used to create the appropriate mask for the
- * desired bit position.
- */
- Mask = (u32)0x00000001U << (Int_Id % 32U);
- /*
- * Enable the selected interrupt source by setting the
- * corresponding bit in the Enable Set register.
- */
- XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_ENABLE_SET_OFFSET +
- ((Int_Id / 32U) * 4U), Mask);
-
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-}
-
-/*****************************************************************************/
-/**
-*
-* Disables the interrupt source provided as the argument Int_Id such that the
-* interrupt controller will not cause interrupts for the specified Int_Id. The
-* interrupt controller will continue to hold an interrupt condition for the
-* Int_Id, but will not cause an interrupt.
-* This API also unmaps the interrupt for the requesting CPU.
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-* @param Int_Id contains the ID of the interrupt source and should be
-* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id)
-{
- u32 Mask;
- u8 Cpu_Identifier = (u8)CpuId;
-#if defined (GICv3)
- u32 Temp;
-#endif
-
- /*
- * Assert the arguments
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-#if defined (GICv3)
- if (Int_Id < XSCUGIC_SPI_INT_ID_START) {
-
- XScuGic_InterruptUnmapFromCpu(InstancePtr, Cpu_Identifier, Int_Id);
-
- Int_Id &= 0x1f;
- Int_Id = 1 << Int_Id;
-
- Temp = XScuGic_ReDistSGIPPIReadReg(InstancePtr,XSCUGIC_RDIST_ISENABLE_OFFSET);
- Temp &= ~Int_Id;
- XScuGic_ReDistSGIPPIWriteReg(InstancePtr,XSCUGIC_RDIST_ISENABLE_OFFSET,Temp);
- }
-#endif
- XScuGic_InterruptUnmapFromCpu(InstancePtr, Cpu_Identifier, Int_Id);
-
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
- /*
- * The Int_Id is used to create the appropriate mask for the
- * desired bit position. Int_Id currently limited to 0 - 31
- */
- Mask = (u32)0x00000001U << (Int_Id % 32U);
-
- /*
- * Disable the selected interrupt source by setting the
- * corresponding bit in the IDR.
- */
- XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
- ((Int_Id / 32U) * 4U), Mask);
-
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-}
-
-/*****************************************************************************/
-/**
-*
-* Allows software to simulate an interrupt in the interrupt controller. This
-* function will only be successful when the interrupt controller has been
-* started in simulation mode. A simulated interrupt allows the interrupt
-* controller to be tested without any device to drive an interrupt input
-* signal into it.
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-* @param Int_Id is the software interrupt ID to simulate an interrupt.
-* @param Cpu_Identifier is the list of CPUs to send the interrupt.
-*
-* @return
-*
-* XST_SUCCESS if successful, or XST_FAILURE if the interrupt could not be
-* simulated
-*
-* @note None.
-*
-******************************************************************************/
-s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Identifier)
-{
- u32 Mask;
-
- /*
- * Assert the arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Int_Id <= 15U);
- Xil_AssertNonvoid(Cpu_Identifier <= 255U);
-
-#if defined (GICv3)
- Mask = (Cpu_Identifier | (Int_Id << XSCUGIC_SGIR_EL1_INITID_SHIFT));
-#if EL3
- XScuGic_WriteICC_SGI0R_EL1(Mask);
-#else
- XScuGic_WriteICC_SGI1R_EL1(Mask);
-#endif
-#else
-
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
-
- /*
- * The Int_Id is used to create the appropriate mask for the
- * desired interrupt. Int_Id currently limited to 0 - 15
- * Use the target list for the Cpu ID.
- */
- Mask = ((Cpu_Identifier << 16U) | Int_Id) &
- (XSCUGIC_SFI_TRIG_CPU_MASK | XSCUGIC_SFI_TRIG_INTID_MASK);
-
- /*
- * Write to the Software interrupt trigger register. Use the appropriate
- * CPU Int_Id.
- */
- XScuGic_DistWriteReg(InstancePtr, XSCUGIC_SFI_TRIG_OFFSET, Mask);
-
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-
- /* Indicate the interrupt was successfully simulated */
-#endif
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* A stub for the asynchronous callback. The stub is here in case the upper
-* layers forget to set the handler.
-*
-* @param CallBackRef is a pointer to the upper layer callback reference
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-static void StubHandler(void *CallBackRef)
-{
- /*
- * verify that the inputs are valid
- */
- Xil_AssertVoid(CallBackRef != NULL);
-
- /*
- * Indicate another unhandled interrupt for stats
- */
- ((XScuGic *)((void *)CallBackRef))->UnhandledInterrupts++;
-}
-
-/****************************************************************************/
-/**
-* Sets the interrupt priority and trigger type for the specificd IRQ source.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Int_Id is the IRQ source number to modify
-* @param Priority is the new priority for the IRQ source. 0 is highest
-* priority, 0xF8(248) is lowest. There are 32 priority levels
-* supported with a step of 8. Hence the supported priorities are
-* 0, 8, 16, 32, 40 ..., 248.
-* @param Trigger is the new trigger type for the IRQ source.
-* Each bit pair describes the configuration for an INT_ID.
-* SFI Read Only b10 always
-* PPI Read Only depending on how the PPIs are configured.
-* b01 Active HIGH level sensitive
-* b11 Rising edge sensitive
-* SPI LSB is read only.
-* b01 Active HIGH level sensitive
-* b11 Rising edge sensitive/
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
- u8 Priority, u8 Trigger)
-{
- u32 RegValue;
-#if defined (GICv3)
- u32 Temp;
- u32 Index;
-#endif
- u8 LocalPriority;
- LocalPriority = Priority;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(Trigger <= (u8)XSCUGIC_INT_CFG_MASK);
- Xil_AssertVoid(LocalPriority <= (u8)XSCUGIC_MAX_INTR_PRIO_VAL);
-#if defined (GICv3)
- if (Int_Id < XSCUGIC_SPI_INT_ID_START )
- {
- XScuGic_ReDistSGIPPIWriteReg(InstancePtr,XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(Int_Id),Priority);
- Temp = XScuGic_ReDistSGIPPIReadReg(InstancePtr,XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(Int_Id));
- Index = XScuGic_Get_Rdist_Int_Trigger_Index(Int_Id);
- Temp |= (Trigger << Index);
- XScuGic_ReDistSGIPPIWriteReg(InstancePtr,XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(Int_Id),Temp);
- return;
- }
-#endif
-
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
- /*
- * Determine the register to write to using the Int_Id.
- */
- RegValue = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
-
- /*
- * The priority bits are Bits 7 to 3 in GIC Priority Register. This
- * means the number of priority levels supported are 32 and they are
- * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
- * The lower order 3 bits are masked before putting it in the register.
- */
- LocalPriority = LocalPriority & (u8)XSCUGIC_INTR_PRIO_MASK;
- /*
- * Shift and Mask the correct bits for the priority and trigger in the
- * register
- */
- RegValue &= ~((u32)XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
- RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
-
- /*
- * Write the value back to the register.
- */
- XScuGic_DistWriteReg(InstancePtr, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
- RegValue);
-
- /*
- * Determine the register to write to using the Int_Id.
- */
- RegValue = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id));
-
- /*
- * Shift and Mask the correct bits for the priority and trigger in the
- * register
- */
- RegValue &= ~((u32)XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
- RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
-
- /*
- * Write the value back to the register.
- */
- XScuGic_DistWriteReg(InstancePtr, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
- RegValue);
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-}
-
-/****************************************************************************/
-/**
-* Gets the interrupt priority and trigger type for the specificd IRQ source.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Int_Id is the IRQ source number to modify
-* @param Priority is a pointer to the value of the priority of the IRQ
-* source. This is a return value.
-* @param Trigger is pointer to the value of the trigger of the IRQ
-* source. This is a return value.
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
- u8 *Priority, u8 *Trigger)
-{
- u32 RegValue;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(Priority != NULL);
- Xil_AssertVoid(Trigger != NULL);
-
- /*
- * Determine the register to read to using the Int_Id.
- */
- RegValue = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
-
- /*
- * Shift and Mask the correct bits for the priority and trigger in the
- * register
- */
- RegValue = RegValue >> ((Int_Id%4U)*8U);
- *Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
-
- /*
- * Determine the register to read to using the Int_Id.
- */
- RegValue = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id));
-
- /*
- * Shift and Mask the correct bits for the priority and trigger in the
- * register
- */
- RegValue = RegValue >> ((Int_Id%16U)*2U);
-
- *Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
-}
-/****************************************************************************/
-/**
-* Sets the target CPU for the interrupt of a peripheral
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Cpu_Identifier is a CPU number for which the interrupt has to be targeted
-* @param Int_Id is the IRQ source number to modify
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Identifier, u32 Int_Id)
-{
- u32 RegValue;
-
-#if defined (GICv3)
- u32 Temp;
- Xil_AssertVoid(InstancePtr != NULL);
- if (Int_Id >= 32) {
- Temp = Int_Id - 32;
- RegValue = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_IROUTER_OFFSET_CALC(Temp));
- RegValue |= Cpu_Identifier;
- XScuGic_DistWriteReg(InstancePtr, XSCUGIC_IROUTER_OFFSET_CALC(Temp),
- (Cpu_Identifier-1));
- }
-#else
- u8 Cpu_CoreId;
- u32 Offset;
- Xil_AssertVoid(InstancePtr != NULL);
-
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
-
- RegValue = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
-
- Offset = (Int_Id & 0x3U);
- Cpu_CoreId = (0x1U << Cpu_Identifier);
-
- RegValue |= (u32)(Cpu_CoreId) << (Offset*8U);
- XScuGic_DistWriteReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
- RegValue);
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-#endif
-}
-/****************************************************************************/
-/**
-* Unmaps specific SPI interrupt from the target CPU
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Cpu_Identifier is a CPU number from which the interrupt has to be
-* unmapped
-* @param Int_Id is the IRQ source number to modify
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Identifier, u32 Int_Id)
-{
- u32 RegValue;
-
-#if defined (GICv3)
- u32 Temp;
- Xil_AssertVoid(InstancePtr != NULL);
- if (Int_Id >= 32) {
- Temp = Int_Id - 32;
- RegValue = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_IROUTER_OFFSET_CALC(Temp));
- RegValue &= ~Cpu_Identifier;
- XScuGic_DistWriteReg(InstancePtr, XSCUGIC_IROUTER_OFFSET_CALC(Temp),
- (Cpu_Identifier-1));
- }
-#else
- u32 Cpu_CoreId;
- u32 Offset;
- Xil_AssertVoid(InstancePtr != NULL);
-
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
-
- RegValue = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
-
- Offset = (Int_Id & 0x3U);
- Cpu_CoreId = ((u32)0x1U << Cpu_Identifier);
-
- RegValue &= ~(Cpu_CoreId << (Offset*8U));
- XScuGic_DistWriteReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
- RegValue);
-
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-#endif
-}
-/****************************************************************************/
-/**
-* Unmaps all SPI interrupts from the target CPU
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Cpu_Identifier is a CPU number from which the interrupts has to be
-* unmapped
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Identifier)
-{
- u32 Int_Id;
- u32 Target_Cpu;
- u32 LocalCpuID = ((u32)1U << Cpu_Identifier);
-
- Xil_AssertVoid(InstancePtr != NULL);
-
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
-
- LocalCpuID |= LocalCpuID << 8U;
- LocalCpuID |= LocalCpuID << 16U;
-
- for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
- Int_Id = Int_Id+4U) {
-
- Target_Cpu = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
- /* Remove LocalCpuID from interrupt target register */
- Target_Cpu &= (~LocalCpuID);
- XScuGic_DistWriteReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu);
-
- }
-
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-}
-/****************************************************************************/
-/**
-* It checks if the interrupt target register contains all interrupts to be
-* targeted for current CPU. If they are programmed to be forwarded to current
-* cpu, this API disable all interrupts and disable GIC distributor.
-* This API also removes current CPU from interrupt target registers for all
-* interrupt.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_Stop(XScuGic *InstancePtr)
-{
- u32 Int_Id;
- u32 RegValue;
- u32 Target_Cpu;
- #if (defined (USE_AMP) && (USE_AMP==1))
- u32 DistDisable = 0; /* Do not disable distributor */
- #else
- u32 DistDisable = 1; /* Track distributor status*/
- #endif
- u32 LocalCpuID = ((u32)0x1 << CpuId);
-
- Xil_AssertVoid(InstancePtr != NULL);
-
- /* If distributor is already disabled, no need to do anything */
- RegValue = XScuGic_DistReadReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET);
- if ((RegValue & XSCUGIC_EN_INT_MASK) == 0U) {
- return;
- }
-
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
-
- LocalCpuID |= LocalCpuID << 8U;
- LocalCpuID |= LocalCpuID << 16U;
-
- /*
- * Check if the interrupt are targeted to current cpu only or not.
- * Also remove current cpu from interrupt target register for all
- * interrupts.
- */
- for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
- Int_Id = Int_Id+4U) {
-
- Target_Cpu = XScuGic_DistReadReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
- if ((Target_Cpu != LocalCpuID) && (Target_Cpu != (u32)0)) {
- /*
- * If any other CPU is also programmed to target
- * register, GIC distributor can not be disabled.
- */
- DistDisable = 0;
- }
-
- /* Remove current CPU from interrupt target register */
- Target_Cpu &= (~LocalCpuID);
- XScuGic_DistWriteReg(InstancePtr,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu);
-
- }
-
- /*
- * If GIC distributor is safe to be disabled, disable all the interrupt
- * and then disable distributor.
- */
- if (DistDisable == (u32)1) {
- for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
- Int_Id = Int_Id+32U) {
- /*
- * Disable all the interrupts
- */
- XScuGic_DistWriteReg(InstancePtr,
- XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET,
- Int_Id),
- 0xFFFFFFFFU);
- }
- XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U);
- }
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-}
-
-/****************************************************************************/
-/**
-* This updates the CpuId global variable.
-*
-* @param CpuCoreId is the CPU core number.
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_SetCpuID(u32 CpuCoreId)
-{
- Xil_AssertVoid(CpuCoreId <= 1U);
-
- CpuId = CpuCoreId;
-}
-
-/****************************************************************************/
-/**
-* This function returns the CpuId variable.
-*
-* @return The CPU core number.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XScuGic_GetCpuID(void)
-{
- return CpuId;
-}
-
-#if defined (GICv3)
-/****************************************************************************/
-/**
-* It marks processor core which calls this API as asleep
-*
-* @return None.
-*
-* @note It should be called before suspending processor core. Once this
-* API is invoked, pending interrupts for processor core asserts
-* WakeRequest, to indicate that the PE is to have its power
-* restored In case of Versal SoC, WakeRequest will be consumed by
-* psv_psm processor and psmfw will wake up APU processor core.
-*
-*****************************************************************************/
-void XScuGic_MarkCoreAsleep(XScuGic *InstancePtr)
-{
- u32 Waker_State;
-
- Waker_State = XScuGic_ReDistReadReg(InstancePtr,XSCUGIC_RDIST_WAKER_OFFSET);
- XScuGic_ReDistWriteReg(InstancePtr,XSCUGIC_RDIST_WAKER_OFFSET,
- Waker_State |
- XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK);
-}
-
-/****************************************************************************/
-/**
-* It marks processor core which calls this API as awake
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_MarkCoreAwake(XScuGic *InstancePtr)
-{
- u32 Waker_State;
-
- Waker_State = XScuGic_ReDistReadReg(InstancePtr,
- XSCUGIC_RDIST_WAKER_OFFSET);
- XScuGic_ReDistWriteReg(InstancePtr,XSCUGIC_RDIST_WAKER_OFFSET,
- Waker_State &
- (~ XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK));
-}
-#endif
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/84/31767b545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/84/31767b545243001d18b399c1eb9b3628
deleted file mode 100644
index 5feeb49..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/84/31767b545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,39 +0,0 @@
-DRIVER_LIB_VERSION = 1.0
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I$(INCLUDEDIR)
-
-SRCFILES:=$(wildcard *.c)
-
-OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
-
-libs: $(OBJECTS)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf $(DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/84/4039cd575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/84/4039cd575243001d18b399c1eb9b3628
deleted file mode 100644
index 227d6a5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/84/4039cd575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,35 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 2021.2
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2022 Xilinx, Inc. All Rights Reserved.
-* SPDX-License-Identifier: MIT
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xdmaps.h"
-
-/*
-* The configuration table for devices
-*/
-
-XDmaPs_Config XDmaPs_ConfigTable[XPAR_XDMAPS_NUM_INSTANCES] =
-{
- {
- XPAR_PS7_DMA_NS_DEVICE_ID,
- XPAR_PS7_DMA_NS_BASEADDR
- },
- {
- XPAR_PS7_DMA_S_DEVICE_ID,
- XPAR_PS7_DMA_S_BASEADDR
- }
-};
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/84/42e7b6565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/84/42e7b6565243001d18b399c1eb9b3628
deleted file mode 100644
index da7e768..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/84/42e7b6565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,36 +0,0 @@
-/* print.c -- print a string on the output device.
- *
- * Copyright (c) 1995 Cygnus Support
- *
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- *
- */
-
-/*
- * print -- do a raw print of a string
- */
-#include "xil_printf.h"
-
-void print(const char8 *ptr)
-{
-#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
- XPVXenConsole_Write(ptr);
-#else
-#ifdef STDOUT_BASEADDRESS
- while (*ptr != (char8)0) {
- outbyte (*ptr);
- ptr++;
- }
-#else
-(void)ptr;
-#endif
-#endif
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/84/8035d6535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/84/8035d6535243001d18b399c1eb9b3628
deleted file mode 100644
index 2a4fff2..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/84/8035d6535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,573 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xreg_cortexa9.h
-*
-* This header file contains definitions for using inline assembler code. It is
-* written specifically for the GNU, ARMCC compiler.
-*
-* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
-* with the positions of the bits within the registers.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm 10/20/09 First release
-*
-*
-******************************************************************************/
-#ifndef XREG_CORTEXA9_H
-#define XREG_CORTEXA9_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/**
- *@cond nocomments
- */
-
-/* GPRs */
-#define XREG_GPR0 r0
-#define XREG_GPR1 r1
-#define XREG_GPR2 r2
-#define XREG_GPR3 r3
-#define XREG_GPR4 r4
-#define XREG_GPR5 r5
-#define XREG_GPR6 r6
-#define XREG_GPR7 r7
-#define XREG_GPR8 r8
-#define XREG_GPR9 r9
-#define XREG_GPR10 r10
-#define XREG_GPR11 r11
-#define XREG_GPR12 r12
-#define XREG_GPR13 r13
-#define XREG_GPR14 r14
-#define XREG_GPR15 r15
-#define XREG_CPSR cpsr
-
-/* Coprocessor number defines */
-#define XREG_CP0 0
-#define XREG_CP1 1
-#define XREG_CP2 2
-#define XREG_CP3 3
-#define XREG_CP4 4
-#define XREG_CP5 5
-#define XREG_CP6 6
-#define XREG_CP7 7
-#define XREG_CP8 8
-#define XREG_CP9 9
-#define XREG_CP10 10
-#define XREG_CP11 11
-#define XREG_CP12 12
-#define XREG_CP13 13
-#define XREG_CP14 14
-#define XREG_CP15 15
-
-/* Coprocessor control register defines */
-#define XREG_CR0 cr0
-#define XREG_CR1 cr1
-#define XREG_CR2 cr2
-#define XREG_CR3 cr3
-#define XREG_CR4 cr4
-#define XREG_CR5 cr5
-#define XREG_CR6 cr6
-#define XREG_CR7 cr7
-#define XREG_CR8 cr8
-#define XREG_CR9 cr9
-#define XREG_CR10 cr10
-#define XREG_CR11 cr11
-#define XREG_CR12 cr12
-#define XREG_CR13 cr13
-#define XREG_CR14 cr14
-#define XREG_CR15 cr15
-
-/* Current Processor Status Register (CPSR) Bits */
-#define XREG_CPSR_THUMB_MODE 0x20
-#define XREG_CPSR_MODE_BITS 0x1F
-#define XREG_CPSR_SYSTEM_MODE 0x1F
-#define XREG_CPSR_UNDEFINED_MODE 0x1B
-#define XREG_CPSR_DATA_ABORT_MODE 0x17
-#define XREG_CPSR_SVC_MODE 0x13
-#define XREG_CPSR_IRQ_MODE 0x12
-#define XREG_CPSR_FIQ_MODE 0x11
-#define XREG_CPSR_USER_MODE 0x10
-
-#define XREG_CPSR_IRQ_ENABLE 0x80
-#define XREG_CPSR_FIQ_ENABLE 0x40
-
-#define XREG_CPSR_N_BIT 0x80000000
-#define XREG_CPSR_Z_BIT 0x40000000
-#define XREG_CPSR_C_BIT 0x20000000
-#define XREG_CPSR_V_BIT 0x10000000
-
-
-/* CP15 defines */
-#if defined (__GNUC__) || defined (__ICCARM__)
-/* C0 Register defines */
-#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"
-#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"
-#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2"
-#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3"
-#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5"
-
-#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0"
-#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1"
-#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2"
-#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4"
-#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5"
-#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6"
-#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7"
-
-#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0"
-#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1"
-#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2"
-#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3"
-#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4"
-
-#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0"
-#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1"
-#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7"
-
-#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0"
-
-/* C1 Register Defines */
-#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0"
-#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1"
-#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2"
-
-#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0"
-#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1"
-#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2"
-#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3"
-
-#else /* RVCT */
-/* C0 Register defines */
-#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0"
-#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1"
-#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2"
-#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3"
-#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5"
-
-#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0"
-#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1"
-#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2"
-#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4"
-#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5"
-#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6"
-#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7"
-
-#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0"
-#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1"
-#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2"
-#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3"
-#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4"
-
-#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0"
-#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1"
-#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7"
-
-#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0"
-
-/* C1 Register Defines */
-#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0"
-#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1"
-#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2"
-
-#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0"
-#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1"
-#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2"
-#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3"
-#endif
-
-/* XREG_CP15_CONTROL bit defines */
-#define XREG_CP15_CONTROL_TE_BIT 0x40000000U
-#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U
-#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U
-#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U
-#define XREG_CP15_CONTROL_EE_BIT 0x02000000U
-#define XREG_CP15_CONTROL_HA_BIT 0x00020000U
-#define XREG_CP15_CONTROL_RR_BIT 0x00004000U
-#define XREG_CP15_CONTROL_V_BIT 0x00002000U
-#define XREG_CP15_CONTROL_I_BIT 0x00001000U
-#define XREG_CP15_CONTROL_Z_BIT 0x00000800U
-#define XREG_CP15_CONTROL_SW_BIT 0x00000400U
-#define XREG_CP15_CONTROL_B_BIT 0x00000080U
-#define XREG_CP15_CONTROL_C_BIT 0x00000004U
-#define XREG_CP15_CONTROL_A_BIT 0x00000002U
-#define XREG_CP15_CONTROL_M_BIT 0x00000001U
-
-#if defined (__GNUC__) || defined (__ICCARM__)
-/* C2 Register Defines */
-#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0"
-#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1"
-#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2"
-
-/* C3 Register Defines */
-#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0"
-
-/* C4 Register Defines */
-/* Not Used */
-
-/* C5 Register Defines */
-#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0"
-#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1"
-
-#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0"
-#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1"
-
-/* C6 Register Defines */
-#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0"
-#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2"
-
-/* C7 Register Defines */
-#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4"
-
-#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0"
-#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6"
-
-#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0"
-
-#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0"
-#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1"
-
-/* The CP15 register access below has been deprecated in favor of the new
- * isb instruction in Cortex A9.
- */
-#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4"
-#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6"
-
-#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1"
-#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2"
-
-#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0"
-#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1"
-#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2"
-#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3"
-
-#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4"
-#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5"
-#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6"
-#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7"
-
-#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1"
-#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2"
-
-/* The next two CP15 register accesses below have been deprecated in favor
- * of the new dsb and dmb instructions in Cortex A9.
- */
-#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4"
-#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5"
-
-#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1"
-
-#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1"
-
-#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1"
-#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2"
-
-/* C8 Register Defines */
-#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0"
-#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1"
-#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2"
-#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3"
-
-#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0"
-#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1"
-#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2"
-
-#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0"
-#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1"
-#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2"
-
-#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0"
-#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1"
-#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2"
-#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3"
-
-/* C9 Register Defines */
-#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0"
-#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1"
-#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2"
-#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3"
-#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4"
-#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5"
-
-#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0"
-#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1"
-#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2"
-
-#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0"
-#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1"
-#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2"
-
-/* C10 Register Defines */
-#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0"
-
-#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0"
-#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1"
-
-/* C11 Register Defines */
-/* Not used */
-
-/* C12 Register Defines */
-#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0"
-#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1"
-
-#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0"
-#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1"
-
-/* C13 Register Defines */
-#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1"
-#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2"
-#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3"
-#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4"
-
-/* C14 Register Defines */
-/* not used */
-
-/* C15 Register Defines */
-#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0"
-#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0"
-
-#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2"
-#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4"
-
-#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2"
-
-#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2"
-
-#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2"
-
-#else
-/* C2 Register Defines */
-#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0"
-#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1"
-#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2"
-
-/* C3 Register Defines */
-#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0"
-
-/* C4 Register Defines */
-/* Not Used */
-
-/* C5 Register Defines */
-#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0"
-#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1"
-
-#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0"
-#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1"
-
-/* C6 Register Defines */
-#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0"
-#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2"
-
-/* C7 Register Defines */
-#define XREG_CP15_NOP "cp15:0:c7:c0:4"
-
-#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0"
-#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6"
-
-#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0"
-
-#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0"
-#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1"
-
-/* The CP15 register access below has been deprecated in favor of the new
- * isb instruction in Cortex A9.
- */
-#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4"
-#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6"
-
-#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1"
-#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2"
-
-#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0"
-#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1"
-#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2"
-#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3"
-
-#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4"
-#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5"
-#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6"
-#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7"
-
-#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1"
-#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2"
-
-/* The next two CP15 register accesses below have been deprecated in favor
- * of the new dsb and dmb instructions in Cortex A9.
- */
-#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4"
-#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5"
-
-#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1"
-
-#define XREG_CP15_NOP2 "cp15:0:c7:c13:1"
-
-#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1"
-#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2"
-
-/* C8 Register Defines */
-#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0"
-#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1"
-#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2"
-#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3"
-
-#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0"
-#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1"
-#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2"
-
-#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0"
-#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1"
-#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2"
-
-#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0"
-#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1"
-#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2"
-#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3"
-
-/* C9 Register Defines */
-#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0"
-#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1"
-#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2"
-#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3"
-#define XREG_CP15_SW_INC "cp15:0:c9:c12:4"
-#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5"
-
-#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0"
-#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1"
-#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2"
-
-#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0"
-#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1"
-#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2"
-
-/* C10 Register Defines */
-#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0"
-
-#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0"
-#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1"
-
-/* C11 Register Defines */
-/* Not used */
-
-/* C12 Register Defines */
-#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0"
-#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1"
-
-#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0"
-#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1"
-
-/* C13 Register Defines */
-#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1"
-#define USER_RW_THREAD_PID "cp15:0:c13:c0:2"
-#define USER_RO_THREAD_PID "cp15:0:c13:c0:3"
-#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4"
-
-/* C14 Register Defines */
-/* not used */
-
-/* C15 Register Defines */
-#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0"
-#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0"
-
-#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2"
-#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4"
-
-#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2"
-
-#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2"
-
-#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2"
-#endif
-
-
-/* MPE register definitions */
-#define XREG_FPSID c0
-#define XREG_FPSCR c1
-#define XREG_MVFR1 c6
-#define XREG_MVFR0 c7
-#define XREG_FPEXC c8
-#define XREG_FPINST c9
-#define XREG_FPINST2 c10
-
-/* FPSID bits */
-#define XREG_FPSID_IMPLEMENTER_BIT (24)
-#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT)
-#define XREG_FPSID_SOFTWARE (1<<23)
-#define XREG_FPSID_ARCH_BIT (16)
-#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
-#define XREG_FPSID_PART_BIT (8)
-#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
-#define XREG_FPSID_VARIANT_BIT (4)
-#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
-#define XREG_FPSID_REV_BIT (0)
-#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT)
-
-/* FPSCR bits */
-#define XREG_FPSCR_N_BIT (1 << 31)
-#define XREG_FPSCR_Z_BIT (1 << 30)
-#define XREG_FPSCR_C_BIT (1 << 29)
-#define XREG_FPSCR_V_BIT (1 << 28)
-#define XREG_FPSCR_QC (1 << 27)
-#define XREG_FPSCR_AHP (1 << 26)
-#define XREG_FPSCR_DEFAULT_NAN (1 << 25)
-#define XREG_FPSCR_FLUSHTOZERO (1 << 24)
-#define XREG_FPSCR_ROUND_NEAREST (0 << 22)
-#define XREG_FPSCR_ROUND_PLUSINF (1 << 22)
-#define XREG_FPSCR_ROUND_MINUSINF (2 << 22)
-#define XREG_FPSCR_ROUND_TOZERO (3 << 22)
-#define XREG_FPSCR_RMODE_BIT (22)
-#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
-#define XREG_FPSCR_STRIDE_BIT (20)
-#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
-#define XREG_FPSCR_LENGTH_BIT (16)
-#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
-#define XREG_FPSCR_IDC (1 << 7)
-#define XREG_FPSCR_IXC (1 << 4)
-#define XREG_FPSCR_UFC (1 << 3)
-#define XREG_FPSCR_OFC (1 << 2)
-#define XREG_FPSCR_DZC (1 << 1)
-#define XREG_FPSCR_IOC (1 << 0)
-
-/* MVFR0 bits */
-#define XREG_MVFR0_RMODE_BIT (28)
-#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT)
-#define XREG_MVFR0_SHORT_VEC_BIT (24)
-#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT)
-#define XREG_MVFR0_SQRT_BIT (20)
-#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT)
-#define XREG_MVFR0_DIVIDE_BIT (16)
-#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT)
-#define XREG_MVFR0_EXEC_TRAP_BIT (12)
-#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT)
-#define XREG_MVFR0_DP_BIT (8)
-#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT)
-#define XREG_MVFR0_SP_BIT (4)
-#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT)
-#define XREG_MVFR0_A_SIMD_BIT (0)
-#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT)
-
-/* FPEXC bits */
-#define XREG_FPEXC_EX (1 << 31)
-#define XREG_FPEXC_EN (1 << 30)
-#define XREG_FPEXC_DEX (1 << 29)
-
-
-/**
- *@endcond
- */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XREG_CORTEXA9_H */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/84/a082e5545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/84/a082e5545243001d18b399c1eb9b3628
deleted file mode 100644
index 8d11ff8..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/84/a082e5545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,365 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xscuwdt.h
-* @addtogroup scuwdt_v2_4
-* @{
-* @details
-*
-* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private
-* watchdog timer hardware.
-*
-* The XScuWdt driver supports the following features:
-* - Watchdog mode
-* - Timer mode
-* - Auto reload (timer mode only)
-*
-* The watchdog counter register is a down counter and starts decrementing when
-* the watchdog is started.
-* In watchdog mode, when the counter reaches 0, the Reset flag is set in the
-* Reset status register and the WDRESETREQ pin is asserted, causing a system
-* reset. The Reset flag is not reset by normal processor reset and is cleared
-* when written with a value of 1. This enables the user to differentiate a
-* normal reset and a reset caused by watchdog time-out. The user needs to call
-* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out.
-*
-* The IsWdtExpired function can be used to check if the watchdog was the cause
-* of the last reset. In this situation, call Initialize then call IsWdtExpired.
-* If the result is true, watchdog timeout caused the last system reset. The
-* application then needs to clear the Reset flag.
-*
-* In timer mode, when the counter reaches 0, the Event flag is set in the
-* Interrupt status register and if interrupts are enabled, interrupt ID 30 is
-* set as pending in the interrupt distributor. The IsTimerExpired function
-* is used to check if the watchdog counter has decremented to 0 in timer mode.
-* If auto-reload mode is enabled, the Counter register is automatically reloaded
-* from the Load register.
-*
-* Initialization and Configuration
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate with the Watchdog Timer.
-*
-* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The
-* user needs to first call the XScuWdt_LookupConfig() API which returns
-* the Configuration structure pointer which is passed as a parameter to
-* the XScuWdt_CfgInitialize() API.
-*
-* Interrupts
-*
-* The SCU Watchdog Timer supports interrupts in Timer mode.
-*
-* This driver does not provide a Interrupt Service Routine (ISR) for the device.
-* It is the responsibility of the application to provide one if needed. Refer to
-* the interrupt example provided with this driver for details on using the
-* Timer in interrupt mode.
-*
-* Virtual Memory
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-* Threads
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* Asserts
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* Building the driver
-*
-* The XScuWdt driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-*
-*
-* NOTE:
-* The watchdog timer is not a part of the snoop control unit as indicated
-* by the prefix "scu" in the name of the driver.
-* It is an independent module in APU.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 2.3 mus 08/31/20 Updated makefile to support parallel make and
-* incremental builds. It would help to reduce compilaton
-* time.
-* 2.3 sne 09/16/20 Fixed MISRA-C violations.
-* 2.4 sne 02/04/21 Fixed Doxygen warnings.
-*
-*
-******************************************************************************/
-#ifndef XSCUWDT_H /**< prevent circular inclusions */
-#define XSCUWDT_H /**< by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xscuwdt_hw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddr; /**< Base address of the device */
-} XScuWdt_Config;
-
-/**
- * The XScuWdt driver instance data. The user is required to allocate a
- * variable of this type for every watchdog/timer device in the system.
- * A pointer to a variable of this type is then passed to the driver API
- * functions.
- */
-typedef struct {
- XScuWdt_Config Config;/**< Hardware Configuration */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStarted; /**< Device watchdog timer is running */
-} XScuWdt;
-
-/************************** Variable Definitions *****************************/
-extern XScuWdt_Config XScuWdt_ConfigTable[];
-
-/***************** Macros (Inline Functions) Definitions *********************/
-/****************************************************************************/
-/**
-*
-* This function is used to check if the watchdog has timed-out and the last
-* reset was caused by the watchdog reset.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return
-* - TRUE if the watchdog has expired.
-* - FALSE if the watchdog has not expired.
-*
-* @note C-style signature:
-* int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_IsWdtExpired(InstancePtr) \
- ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_RST_STS_OFFSET) & \
- XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
-
-/****************************************************************************/
-/**
-*
-* This function is used to check if the watchdog counter has reached 0 in timer
-* mode.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return
-* - TRUE if the watchdog has expired.
-* - FALSE if the watchdog has not expired.
-*
-* @note C-style signature:
-* int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_IsTimerExpired(InstancePtr) \
- ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_ISR_OFFSET) & \
- XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
-
-/****************************************************************************/
-/**
-*
-* Re-start the watchdog timer. This macro will read the watchdog load register
-* and write the same value to load register to update the counter register.
-* An application needs to call this function periodically to keep the watchdog
-* from asserting the WDRESETREQ reset request output pin.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_RestartWdt(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_RestartWdt(InstancePtr) \
- XScuWdt_LoadWdt((InstancePtr), \
- (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_LOAD_OFFSET)))
-
-/****************************************************************************/
-/**
-*
-* Write to the watchdog timer load register. This will also update the
-* watchdog counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-* @param Value is the value to be written to the Watchdog Load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value)
-*
-******************************************************************************/
-#define XScuWdt_LoadWdt(InstancePtr, Value) \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_LOAD_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the
-* Watchdog control register.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_SetWdMode(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_SetWdMode(InstancePtr) \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET, \
- (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET) | \
- (XSCUWDT_CONTROL_WD_MODE_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321
-* successively to the Watchdog Disable Register.
-* The software must write 0x12345678 and 0x87654321 successively to the
-* Watchdog Disable Register so that the watchdog mode bit in the Watchdog
-* Control Register is set to zero.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_SetTimerMode(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_SetTimerMode(InstancePtr) \
-{ \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_DISABLE_OFFSET, \
- XSCUWDT_DISABLE_VALUE1); \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_DISABLE_OFFSET, \
- XSCUWDT_DISABLE_VALUE2); \
-}
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the watchdog control register.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return Contents of the watchdog control register.
-*
-* @note C-style signature:
- u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_GetControlReg(InstancePtr) \
- XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the watchdog control register.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-* @param ControlReg is the value to be written to the watchdog control
-* register.
-*
-* @return None.
-*
-* @note C-style signature:
- void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg)
-*
-******************************************************************************/
-#define XScuWdt_SetControlReg(InstancePtr, ControlReg) \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET, (ControlReg))
-
-/****************************************************************************/
-/**
-*
-* Enable auto-reload mode.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_EnableAutoReload(InstancePtr) \
- XScuWdt_SetControlReg((InstancePtr), \
- (XScuWdt_GetControlReg(InstancePtr) | \
- XSCUWDT_CONTROL_AUTO_RELOAD_MASK))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Lookup configuration in xscuwdt_sinit.c.
- */
-XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId);
-
-/*
- * Selftest function in xscuwdt_selftest.c
- */
-s32 XScuWdt_SelfTest(XScuWdt *InstancePtr);
-
-/*
- * Interface functions in xscuwdt.c
- */
-s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
- XScuWdt_Config *ConfigPtr, u32 EffectiveAddress);
-
-void XScuWdt_Start(XScuWdt *InstancePtr);
-
-void XScuWdt_Stop(XScuWdt *InstancePtr);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/84/a0af16565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/84/a0af16565243001d18b399c1eb9b3628
deleted file mode 100644
index eb5eb30..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/84/a0af16565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,117 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file asm_vectors.S
-*
-* This file contains the initial vector table for the Cortex R5 processor
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 5.00 pkp 02/10/14 Initial version
-* 6.0 mus 27/07/16 Added UndefinedException handler
-* 6.3 pkp 02/13/17 Added support for hard float
-*
-*
-******************************************************************************/
-.org 0
-.text
-
-.globl _boot
-.globl _vector_table
-
-.globl FIQInterrupt
-.globl IRQInterrupt
-.globl SWInterrupt
-.globl DataAbortInterrupt
-.globl PrefetchAbortInterrupt
-
-.globl IRQHandler
-.globl prof_pc
-
-.section .vectors, "a"
-_vector_table:
- ldr pc,=_boot
- ldr pc,=Undefined
- ldr pc,=SVCHandler
- ldr pc,=PrefetchAbortHandler
- ldr pc,=DataAbortHandler
- NOP /* Placeholder for address exception vector*/
- ldr pc,=IRQHandler
- ldr pc,=FIQHandler
-
-.text
-IRQHandler: /* IRQ vector handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/
-#ifndef __SOFTFP__
-
- vpush {d0-d7} /* Store floating point registers */
- vmrs r1, FPSCR
- push {r1}
- vmrs r1, FPEXC
- push {r1}
-#endif
- bl IRQInterrupt /* IRQ vector */
-#ifndef __SOFTFP__
-
- pop {r1} /* Restore floating point registers */
- vmsr FPEXC, r1
- pop {r1}
- vmsr FPSCR, r1
- vpop {d0-d7}
-#endif
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
- subs pc, lr, #4 /* adjust return */
-FIQHandler: /* FIQ vector handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
-FIQLoop:
- bl FIQInterrupt /* FIQ vector */
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
- subs pc, lr, #4 /* adjust return */
-
-Undefined: /* Undefined handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- ldr r0, =UndefinedExceptionAddr
- sub r1, lr, #4
- str r1, [r0] /* Store address of instruction causing undefined exception */
-
- bl UndefinedException /* UndefinedException: call C function here */
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
- movs pc, lr
-
-SVCHandler: /* SWI handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- tst r0, #0x20 /* check the T bit */
- ldrneh r0, [lr,#-2] /* Thumb mode */
- bicne r0, r0, #0xff00 /* Thumb mode */
- ldreq r0, [lr,#-4] /* ARM mode */
- biceq r0, r0, #0xff000000 /* ARM mode */
- bl SWInterrupt /* SWInterrupt: call C function here */
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
- movs pc, lr /* adjust return */
-
-DataAbortHandler: /* Data Abort handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- ldr r0, =DataAbortAddr
- sub r1, lr, #8
- str r1, [r0] /* Stores instruction causing data abort */
- bl DataAbortInterrupt /*DataAbortInterrupt :call C function here */
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
- subs pc, lr, #8 /* adjust return */
-
-PrefetchAbortHandler: /* Prefetch Abort handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- ldr r0, =PrefetchAbortAddr
- sub r1, lr, #4
- str r1, [r0] /* Stores instruction causing prefetch abort */
- bl PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
- subs pc, lr, #4 /* adjust return */
-
-
-.end
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/84/d186c5595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/84/d186c5595243001d18b399c1eb9b3628
deleted file mode 100644
index f958643..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/84/d186c5595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,630 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xuartps.c
-* @addtogroup uartps_v3_11
-* @{
-*
-* This file contains the implementation of the interface functions for XUartPs
-* driver. Refer to the header file xuartps.h for more detailed information.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00 drg/jz 01/13/10 First Release
-* 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing
-* baud rate. CR# 804281.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
-* 3.5 NK 09/26/17 Fix the RX Buffer Overflow issue.
-* 3.7 aru 08/17/18 Resolved MISRA-C mandatory violations.(CR#1007755)
-* 3.9 sd 02/06/20 Added clock support
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xstatus.h"
-#include "xuartps.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ****************************/
-
-/* The following constant defines the amount of error that is allowed for
- * a specified baud rate. This error is the difference between the actual
- * baud rate that will be generated using the specified clock and the
- * desired baud rate.
- */
-#define XUARTPS_MAX_BAUD_ERROR_RATE 3U /* max % error allowed */
-
-/**************************** Type Definitions ******************************/
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Function Prototypes *****************************/
-
-static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
- u32 ByteCount);
-
-u32 XUartPs_SendBuffer(XUartPs *InstancePtr);
-
-u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
-
-/************************** Variable Definitions ****************************/
-
-/****************************************************************************/
-/**
-*
-* Initializes a specific XUartPs instance such that it is ready to be used.
-* The data format of the device is setup for 8 data bits, 1 stop bit, and no
-* parity by default. The baud rate is set to a default value specified by
-* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The
-* receive FIFO threshold is set for 8 bytes. The default operating mode of the
-* driver is polled mode.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param Config is a reference to a structure containing information
-* about a specific XUartPs driver.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. The caller is responsible for keeping the address
-* mapping from EffectiveAddr to the device physical base address
-* unchanged once this function is invoked. Unexpected errors may
-* occur if the address mapping changes after this function is
-* called. If address translation is not used, pass in the physical
-* address instead.
-*
-* @return
-*
-* - XST_SUCCESS if initialization was successful
-* - XST_UART_BAUD_ERROR if the baud rate is not possible because
-* the inputclock frequency is not divisible with an acceptable
-* amount of error
-*
-* @note
-*
-* The default configuration for the UART after initialization is:
-*
-* - 19,200 bps or XPAR_DFT_BAUDRATE if defined
-* - 8 data bits
-* - 1 stop bit
-* - no parity
-* - FIFO's are enabled with a receive threshold of 8 bytes
-* - The RX timeout is enabled with a timeout of 1 (4 char times)
-*
-* All interrupts are disabled.
-*
-*****************************************************************************/
-s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
- XUartPs_Config * Config, u32 EffectiveAddr)
-{
- s32 Status;
- u32 ModeRegister;
- u32 BaudRate;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(Config != NULL);
-
- /* Setup the driver instance using passed in parameters */
- InstancePtr->Config.BaseAddress = EffectiveAddr;
- InstancePtr->Config.InputClockHz = Config->InputClockHz;
-#if defined (XCLOCKING)
- InstancePtr->Config.RefClk = Config->RefClk;
-#endif
- InstancePtr->Config.ModemPinsConnected = Config->ModemPinsConnected;
-
- /* Initialize other instance data to default values */
- InstancePtr->Handler = (XUartPs_Handler)XUartPs_StubHandler;
-
- InstancePtr->SendBuffer.NextBytePtr = NULL;
- InstancePtr->SendBuffer.RemainingBytes = 0U;
- InstancePtr->SendBuffer.RequestedBytes = 0U;
-
- InstancePtr->ReceiveBuffer.NextBytePtr = NULL;
- InstancePtr->ReceiveBuffer.RemainingBytes = 0U;
- InstancePtr->ReceiveBuffer.RequestedBytes = 0U;
-
- /* Initialize the platform data */
- InstancePtr->Platform = XGetPlatform_Info();
-
- InstancePtr->is_rxbs_error = 0U;
-
- /* Flag that the driver instance is ready to use */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- /*
- * Set the default baud rate here, can be changed prior to
- * starting the device
- */
- BaudRate = (u32)XUARTPS_DFT_BAUDRATE;
- Status = XUartPs_SetBaudRate(InstancePtr, BaudRate);
- if (Status != (s32)XST_SUCCESS) {
- InstancePtr->IsReady = 0U;
- } else {
-
- /*
- * Set up the default data format: 8 bit data, 1 stop bit, no
- * parity
- */
- ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_MR_OFFSET);
-
- /* Mask off what's already there */
- ModeRegister &= (~((u32)XUARTPS_MR_CHARLEN_MASK |
- (u32)XUARTPS_MR_STOPMODE_MASK |
- (u32)XUARTPS_MR_PARITY_MASK));
-
- /* Set the register value to the desired data format */
- ModeRegister |= ((u32)XUARTPS_MR_CHARLEN_8_BIT |
- (u32)XUARTPS_MR_STOPMODE_1_BIT |
- (u32)XUARTPS_MR_PARITY_NONE);
-
- /* Write the mode register out */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
- ModeRegister);
-
- /* Set the RX FIFO trigger at 8 data bytes. */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_RXWM_OFFSET, 0x08U);
-
- /* Set the RX timeout to 1, which will be 4 character time */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_RXTOUT_OFFSET, 0x01U);
-
- /* Disable all interrupts, polled mode is the default */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
- XUARTPS_IXR_MASK);
-
- Status = XST_SUCCESS;
- }
- return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* This functions sends the specified buffer using the device in either
-* polled or interrupt driven mode. This function is non-blocking, if the device
-* is busy sending data, it will return and indicate zero bytes were sent.
-* Otherwise, it fills the TX FIFO as much as it can, and return the number of
-* bytes sent.
-*
-* In a polled mode, this function will only send as much data as TX FIFO can
-* buffer. The application may need to call it repeatedly to send the entire
-* buffer.
-*
-* In interrupt mode, this function will start sending the specified buffer,
-* then the interrupt handler will continue sending data until the entire
-* buffer has been sent. A callback function, as specified by the application,
-* will be called to indicate the completion of sending.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param BufferPtr is pointer to a buffer of data to be sent.
-* @param NumBytes contains the number of bytes to be sent. A value of
-* zero will stop a previous send operation that is in progress
-* in interrupt mode. Any data that was already put into the
-* transmit FIFO will be sent.
-*
-* @return The number of bytes actually sent.
-*
-* @note
-*
-* The number of bytes is not asserted so that this function may be called with
-* a value of zero to stop an operation that is already in progress.
-*
-*
-*****************************************************************************/
-u32 XUartPs_Send(XUartPs *InstancePtr, u8 *BufferPtr,
- u32 NumBytes)
-{
- u32 BytesSent;
-
- /* Asserts validate the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(BufferPtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-#if defined (XCLOCKING)
- Xil_ClockEnable(InstancePtr->Config.RefClk);
-#endif
- /*
- * Disable the UART transmit interrupts to allow this call to stop a
- * previous operation that may be interrupt driven.
- */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
- (XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_TXFULL));
-
- /* Setup the buffer parameters */
- InstancePtr->SendBuffer.RequestedBytes = NumBytes;
- InstancePtr->SendBuffer.RemainingBytes = NumBytes;
- InstancePtr->SendBuffer.NextBytePtr = BufferPtr;
-
- /*
- * Transmit interrupts will be enabled in XUartPs_SendBuffer(), after
- * filling the TX FIFO.
- */
- BytesSent = XUartPs_SendBuffer(InstancePtr);
-
- return BytesSent;
-}
-
-/****************************************************************************/
-/**
-*
-* This function attempts to receive a specified number of bytes of data
-* from the device and store it into the specified buffer. This function works
-* for both polled or interrupt driven modes. It is non-blocking.
-*
-* In a polled mode, this function will only receive the data already in the
-* RX FIFO. The application may need to call it repeatedly to receive the
-* entire buffer. Polled mode is the default mode of operation for the device.
-*
-* In interrupt mode, this function will start the receiving, if not the entire
-* buffer has been received, the interrupt handler will continue receiving data
-* until the entire buffer has been received. A callback function, as specified
-* by the application, will be called to indicate the completion of the
-* receiving or error conditions.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-* @param BufferPtr is pointer to buffer for data to be received into
-* @param NumBytes is the number of bytes to be received. A value of zero
-* will stop a previous receive operation that is in progress in
-* interrupt mode.
-*
-* @return The number of bytes received.
-*
-* @note
-*
-* The number of bytes is not asserted so that this function may be called
-* with a value of zero to stop an operation that is already in progress.
-*
-*****************************************************************************/
-u32 XUartPs_Recv(XUartPs *InstancePtr,
- u8 *BufferPtr, u32 NumBytes)
-{
- u32 ReceivedCount;
- u32 ImrRegister;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(BufferPtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-#if defined (XCLOCKING)
- Xil_ClockEnable(InstancePtr->Config.RefClk);
-#endif
- /*
- * Disable all the interrupts.
- * This stops a previous operation that may be interrupt driven
- */
- ImrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IMR_OFFSET);
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
- XUARTPS_IXR_MASK);
-
- /* Setup the buffer parameters */
- InstancePtr->ReceiveBuffer.RequestedBytes = NumBytes;
- InstancePtr->ReceiveBuffer.RemainingBytes = NumBytes;
- InstancePtr->ReceiveBuffer.NextBytePtr = BufferPtr;
-
- /* Receive the data from the device */
- ReceivedCount = XUartPs_ReceiveBuffer(InstancePtr);
-
- /* Restore the interrupt state */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
- ImrRegister);
-
- return ReceivedCount;
-}
-
-/****************************************************************************/
-/*
-*
-* This function sends a buffer that has been previously specified by setting
-* up the instance variables of the instance. This function is an internal
-* function for the XUartPs driver such that it may be called from a shell
-* function that sets up the buffer or from an interrupt handler.
-*
-* This function sends the specified buffer in either polled or interrupt
-* driven modes. This function is non-blocking.
-*
-* In a polled mode, this function only sends as much data as the TX FIFO
-* can buffer. The application may need to call it repeatedly to send the
-* entire buffer.
-*
-* In interrupt mode, this function starts the sending of the buffer, if not
-* the entire buffer has been sent, then the interrupt handler continues the
-* sending until the entire buffer has been sent. A callback function, as
-* specified by the application, will be called to indicate the completion of
-* sending.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-*
-* @return The number of bytes actually sent
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XUartPs_SendBuffer(XUartPs *InstancePtr)
-{
- u32 SentCount = 0U;
- u32 ImrRegister;
-
- /*
- * If the TX FIFO is full, send nothing.
- * Otherwise put bytes into the TX FIFO unil it is full, or all of the
- * data has been put into the FIFO.
- */
- while ((!XUartPs_IsTransmitFull(InstancePtr->Config.BaseAddress)) &&
- (InstancePtr->SendBuffer.RemainingBytes > SentCount)) {
-
- /* Fill the FIFO from the buffer */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_FIFO_OFFSET,
- ((u32)InstancePtr->SendBuffer.
- NextBytePtr[SentCount]));
-
- /* Increment the send count. */
- SentCount++;
- }
-
- /* Update the buffer to reflect the bytes that were sent from it */
- InstancePtr->SendBuffer.NextBytePtr += SentCount;
- InstancePtr->SendBuffer.RemainingBytes -= SentCount;
-
- /*
- * If interrupts are enabled as indicated by the receive interrupt, then
- * enable the TX FIFO empty interrupt, so further action can be taken
- * for this sending.
- */
- ImrRegister =
- XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IMR_OFFSET);
- if (((ImrRegister & XUARTPS_IXR_RXFULL) != (u32)0) ||
- ((ImrRegister & XUARTPS_IXR_RXEMPTY) != (u32)0)||
- ((ImrRegister & XUARTPS_IXR_RXOVR) != (u32)0)) {
-
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IER_OFFSET,
- ImrRegister | (u32)XUARTPS_IXR_TXEMPTY);
- }
-
- return SentCount;
-}
-
-/****************************************************************************/
-/*
-*
-* This function receives a buffer that has been previously specified by setting
-* up the instance variables of the instance. This function is an internal
-* function, and it may be called from a shell function that sets up the buffer
-* or from an interrupt handler.
-*
-* This function attempts to receive a specified number of bytes from the
-* device and store it into the specified buffer. This function works for
-* either polled or interrupt driven modes. It is non-blocking.
-*
-* In polled mode, this function only receives as much data as in the RX FIFO.
-* The application may need to call it repeatedly to receive the entire buffer.
-* Polled mode is the default mode for the driver.
-*
-* In interrupt mode, this function starts the receiving, if not the entire
-* buffer has been received, the interrupt handler will continue until the
-* entire buffer has been received. A callback function, as specified by the
-* application, will be called to indicate the completion of the receiving or
-* error conditions.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-*
-* @return The number of bytes received.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr)
-{
- u32 CsrRegister;
- u32 ReceivedCount = 0U;
- u32 ByteStatusValue, EventData;
- u32 Event;
-
- /*
- * Read the Channel Status Register to determine if there is any data in
- * the RX FIFO
- */
- CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_SR_OFFSET);
-
- /*
- * Loop until there is no more data in RX FIFO or the specified
- * number of bytes has been received
- */
- while((ReceivedCount < InstancePtr->ReceiveBuffer.RemainingBytes)&&
- (((CsrRegister & XUARTPS_SR_RXEMPTY) == (u32)0))){
-
- if (InstancePtr->is_rxbs_error) {
- ByteStatusValue = XUartPs_ReadReg(
- InstancePtr->Config.BaseAddress,
- XUARTPS_RXBS_OFFSET);
- if((ByteStatusValue & XUARTPS_RXBS_MASK)!= (u32)0) {
- EventData = ByteStatusValue;
- Event = XUARTPS_EVENT_PARE_FRAME_BRKE;
- /*
- * Call the application handler to indicate that there is a receive
- * error or a break interrupt, if the application cares about the
- * error it call a function to get the last errors.
- */
- InstancePtr->Handler(InstancePtr->CallBackRef,
- Event, EventData);
- }
- }
-
- InstancePtr->ReceiveBuffer.NextBytePtr[ReceivedCount] =
- XUartPs_ReadReg(InstancePtr->Config.
- BaseAddress,
- XUARTPS_FIFO_OFFSET);
-
- ReceivedCount++;
-
- CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_SR_OFFSET);
- }
- InstancePtr->is_rxbs_error = 0;
- /*
- * Update the receive buffer to reflect the number of bytes just
- * received
- */
- if(InstancePtr->ReceiveBuffer.NextBytePtr != NULL){
- InstancePtr->ReceiveBuffer.NextBytePtr += ReceivedCount;
- }
- InstancePtr->ReceiveBuffer.RemainingBytes -= ReceivedCount;
-
- return ReceivedCount;
-}
-
-/*****************************************************************************/
-/**
-*
-* Sets the baud rate for the device. Checks the input value for
-* validity and also verifies that the requested rate can be configured to
-* within the maximum error range specified by XUARTPS_MAX_BAUD_ERROR_RATE.
-* If the provided rate is not possible, the current setting is unchanged.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-* @param BaudRate to be set
-*
-* @return
-* - XST_SUCCESS if everything configured as expected
-* - XST_UART_BAUD_ERROR if the requested rate is not available
-* because there was too much error
-*
-* @note None.
-*
-*****************************************************************************/
-s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate)
-{
- u32 IterBAUDDIV; /* Iterator for available baud divisor values */
- u32 BRGR_Value; /* Calculated value for baud rate generator */
- u32 CalcBaudRate; /* Calculated baud rate */
- u32 BaudError; /* Diff between calculated and requested baud rate */
- u32 Best_BRGR = 0U; /* Best value for baud rate generator */
- u8 Best_BAUDDIV = 0U; /* Best value for baud divisor */
- u32 Best_Error = 0xFFFFFFFFU;
- u32 PercentError;
- u32 ModeReg;
- u32 InputClk;
-
- /* Asserts validate the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(BaudRate <= (u32)XUARTPS_MAX_RATE);
- Xil_AssertNonvoid(BaudRate >= (u32)XUARTPS_MIN_RATE);
-
- /*
- * Make sure the baud rate is not impossilby large.
- * Fastest possible baud rate is Input Clock / 2.
- */
- if ((BaudRate * 2) > InstancePtr->Config.InputClockHz) {
- return XST_UART_BAUD_ERROR;
- }
- /* Check whether the input clock is divided by 8 */
- ModeReg = XUartPs_ReadReg( InstancePtr->Config.BaseAddress,
- XUARTPS_MR_OFFSET);
-
- InputClk = InstancePtr->Config.InputClockHz;
- if(ModeReg & XUARTPS_MR_CLKSEL) {
- InputClk = InstancePtr->Config.InputClockHz / 8;
- }
-
- /*
- * Determine the Baud divider. It can be 4to 254.
- * Loop through all possible combinations
- */
- for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++) {
-
- /* Calculate the value for BRGR register */
- BRGR_Value = InputClk / (BaudRate * (IterBAUDDIV + 1));
-
- /* Calculate the baud rate from the BRGR value */
- CalcBaudRate = InputClk/ (BRGR_Value * (IterBAUDDIV + 1));
-
- /* Avoid unsigned integer underflow */
- if (BaudRate > CalcBaudRate) {
- BaudError = BaudRate - CalcBaudRate;
- }
- else {
- BaudError = CalcBaudRate - BaudRate;
- }
-
- /* Find the calculated baud rate closest to requested baud rate. */
- if (Best_Error > BaudError) {
-
- Best_BRGR = BRGR_Value;
- Best_BAUDDIV = IterBAUDDIV;
- Best_Error = BaudError;
- }
- }
-
- /* Make sure the best error is not too large. */
- PercentError = (Best_Error * 100) / BaudRate;
- if (XUARTPS_MAX_BAUD_ERROR_RATE < PercentError) {
- return XST_UART_BAUD_ERROR;
- }
-
- /* Disable TX and RX to avoid glitches when setting the baud rate. */
- XUartPs_DisableUart(InstancePtr);
-
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_BAUDGEN_OFFSET, Best_BRGR);
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_BAUDDIV_OFFSET, Best_BAUDDIV);
-
- /* RX and TX SW reset */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
- XUARTPS_CR_TXRST | XUARTPS_CR_RXRST);
-
- /* Enable device */
- XUartPs_EnableUart(InstancePtr);
-
- InstancePtr->BaudRate = BaudRate;
-
- return XST_SUCCESS;
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function is a stub handler that is the default handler such that if the
-* application has not set the handler when interrupts are enabled, this
-* function will be called.
-*
-* @param CallBackRef is unused by this function.
-* @param Event is unused by this function.
-* @param ByteCount is unused by this function.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
- u32 ByteCount)
-{
- (void) CallBackRef;
- (void) Event;
- (void) ByteCount;
- /* Assert occurs always since this is a stub and should never be called */
- Xil_AssertVoidAlways();
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/85/00b2a8525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/85/00b2a8525243001d18b399c1eb9b3628
deleted file mode 100644
index fd7f472..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/85/00b2a8525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,273 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xgpiops.h
-* @addtogroup gpiops_v3_9
-* @{
-* @details
-*
-* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
-* Controller.
-*
-* The GPIO Controller supports the following features:
-* - 4 banks
-* - Masked writes (There are no masked reads)
-* - Bypass mode
-* - Configurable Interrupts (Level/Edge)
-*
-* This driver is intended to be RTOS and processor independent. Any needs for
-* dynamic memory management, threads or thread mutual exclusion, virtual
-* memory, or cache control must be satisfied by the layer above this driver.
-
-* This driver supports all the features listed above, if applicable.
-*
-* Driver Description
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate to the GPIO.
-*
-* Interrupts
-*
-* The driver provides interrupt management functions and an interrupt handler.
-* Users of this driver need to provide callback functions. An interrupt handler
-* example is available with the driver.
-*
-* Threads
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* Asserts
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* Building the driver
-*
-* The XGpioPs driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sv 01/15/10 First Release
-* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
-* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
-* relevant to Zynq device.The interrupts are disabled
-* for output pins on all banks during initialization.
-* 1.02a hk 08/22/13 Added low level reset API
-* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
-* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
-* passed to APIs. CR# 822636
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/05/17 Added tabspace for return statements in functions of
-* gpiops examples for proper documentation while
-* generating doxygen.
-* 3.3 ms 04/17/17 Added notes about gpio input and output pin description
-* for zcu102 and zc702 boards in polled and interrupt
-* example, configured Interrupt pin to input pin for
-* proper functioning of interrupt example.
-* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
-* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
-* in safety mode and modified the code such as
-* Use of mixed mode arithmetic,Declared the pointer param
-* as Pointer to const,Casting operation to a pointer,
-* Literal value requires a U suffix.
-* 3.5 sne 03/14/19 Added Versal support.
-* 3.6 mus 04/05/19 Replaced XPLAT_versal macro with XPLAT_VERSAL, to be in
-* sync with standalone BSP
-* 3.6 sne 06/12/19 Fixed IAR compiler warning.
-* 3.6 sne 08/14/19 Added interrupt handler support on versal.
-* 3.7 sne 12/04/19 Reverted versal examples support.
-* 3.8 sne 08/28/20 Modify Makefile to support parallel make execution.
-* 3.8 sne 09/17/20 Added description for Versal PS and PMC GPIO pins.
-* 3.9 sne 03/15/21 Fixed MISRA-C violations.
-*
-*
-*
-******************************************************************************/
-#ifndef XGPIOPS_H /* prevent circular inclusions */
-#define XGPIOPS_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xgpiops_hw.h"
-#include "xplatform_info.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Interrupt types
- * @{
- * The following constants define the interrupt types that can be set for each
- * GPIO pin.
- */
-#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */
-#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */
-#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */
-#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */
-#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
-/** @}*/
-
-#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
-#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
-#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
-#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
-#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
-
-#ifdef XPAR_PSU_GPIO_0_BASEADDR
-#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */
-#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */
-#endif
-
-#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a
- * Zynq Ultrascale+ MP GPIO device
- */
-#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
-
-#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
- * Zynq Ultrascale+ MP GPIO device
- * 0 - 25, Bank 0
- * 26 - 51, Bank 1
- * 52 - 77, Bank 2
- * 78 - 109, Bank 3
- * 110 - 141, Bank 4
- * 142 - 173, Bank 5
- */
-#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device
- * 0 - 31, Bank 0
- * 32 - 53, Bank 1
- * 54 - 85, Bank 2
- * 86 - 117, Bank 3
- */
-
-/**************************** Type Definitions *******************************/
-
-/****************************************************************************/
-/**
- * This handler data type allows the user to define a callback function to
- * handle the interrupts for the GPIO device. The application using this
- * driver is expected to define a handler of this type, to support interrupt
- * driven mode. The handler executes in an interrupt context such that minimal
- * processing should be performed.
- *
- * @param CallBackRef is a callback reference passed in by the upper layer
- * when setting the callback functions for a GPIO bank. It is
- * passed back to the upper layer when the callback is invoked. Its
- * type is not important to the driver component, so it is a void
- * pointer.
- * @param Bank is the bank for which the interrupt status has changed.
- * @param Status is the Interrupt status of the GPIO bank.
- *
- *****************************************************************************/
-typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
-
-/**
- * This typedef contains configuration information for a device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- UINTPTR BaseAddr; /**< Register base address */
-} XGpioPs_Config;
-
-/**
- * The XGpioPs driver instance data. The user is required to allocate a
- * variable of this type for the GPIO device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XGpioPs_Config GpioConfig; /**< Device configuration */
- u32 IsReady; /**< Device is initialized and ready */
- XGpioPs_Handler Handler; /**< Status handlers for all banks */
- void *CallBackRef; /**< Callback ref for bank handlers */
- u32 Platform; /**< Platform data */
- u32 MaxPinNum; /**< Max pins in the GPIO device */
- u8 MaxBanks; /**< Max banks in a GPIO device */
- u32 PmcGpio; /**< Flag for accessing PS GPIO for versal*/
-} XGpioPs;
-
-/************************** Variable Definitions *****************************/
-extern XGpioPs_Config XGpioPs_ConfigTable[];
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/* Functions in xgpiops.c */
-s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
- u32 EffectiveAddr);
-
-/* Bank APIs in xgpiops.c */
-u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data);
-void XGpioPs_SetDirection(const XGpioPs *InstancePtr, u8 Bank, u32 Direction);
-u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_SetOutputEnable(const XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
-u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank);
-#ifdef versal
-void XGpioPs_GetBankPin(const XGpioPs *InstancePtr,u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank);
-#else
-void XGpioPs_GetBankPin(u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank);
-#endif
-
-/* Pin APIs in xgpiops.c */
-u32 XGpioPs_ReadPin(const XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_WritePin(const XGpioPs *InstancePtr, u32 Pin, u32 Data);
-void XGpioPs_SetDirectionPin(const XGpioPs *InstancePtr, u32 Pin, u32 Direction);
-u32 XGpioPs_GetDirectionPin(const XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
-u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin);
-
-/* Diagnostic functions in xgpiops_selftest.c */
-s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr);
-
-/* Functions in xgpiops_intr.c */
-/* Bank APIs in xgpiops_intr.c */
-void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
-void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
-u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank);
-u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
-void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
- u32 IntrPolarity, u32 IntrOnAny);
-void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
- u32 *IntrPolarity, u32 *IntrOnAny);
-void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
- XGpioPs_Handler FuncPointer);
-void XGpioPs_IntrHandler(const XGpioPs *InstancePtr);
-
-/* Pin APIs in xgpiops_intr.c */
-void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
-u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin);
-
-void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin);
-u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin);
-u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin);
-
-/* Functions in xgpiops_sinit.c */
-XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/85/00ca1b545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/85/00ca1b545243001d18b399c1eb9b3628
deleted file mode 100644
index 1b601db..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/85/00ca1b545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,96 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file smc.h
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 11/03/09 Initial release.
-* 4.2 pkp 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
-* as smc.c is removed
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- -----------------------------------------------
-* 1.00 drg/jz 01/13/10 First Release
-* 1.00 sdm 09/27/11 Fixed a bug in XUartPs_SetFlowDelay where the input
-* value was not being written to the register.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.2 rk 07/20/16 Modified the logic for transmission break bit set
-*
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xuartps.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-/*
- * The following data type is a map from an option to the offset in the
- * register to which it belongs as well as its bit mask in that register.
- */
-typedef struct {
- u16 Option;
- u16 RegisterOffset;
- u32 Mask;
-} Mapping;
-
-/*
- * Create the table which contains options which are to be processed to get/set
- * the options. These options are table driven to allow easy maintenance and
- * expansion of the options.
- */
-
-static Mapping OptionsTable[] = {
- {XUARTPS_OPTION_SET_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STARTBRK},
- {XUARTPS_OPTION_STOP_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STOPBRK},
- {XUARTPS_OPTION_RESET_TMOUT, XUARTPS_CR_OFFSET, XUARTPS_CR_TORST},
- {XUARTPS_OPTION_RESET_TX, XUARTPS_CR_OFFSET, XUARTPS_CR_TXRST},
- {XUARTPS_OPTION_RESET_RX, XUARTPS_CR_OFFSET, XUARTPS_CR_RXRST},
- {XUARTPS_OPTION_ASSERT_RTS, XUARTPS_MODEMCR_OFFSET,
- XUARTPS_MODEMCR_RTS},
- {XUARTPS_OPTION_ASSERT_DTR, XUARTPS_MODEMCR_OFFSET,
- XUARTPS_MODEMCR_DTR},
- {XUARTPS_OPTION_SET_FCM, XUARTPS_MODEMCR_OFFSET, XUARTPS_MODEMCR_FCM}
-};
-
-/* Create a constant for the number of entries in the table */
-
-#define XUARTPS_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(Mapping))
-
-/************************** Function Prototypes *****************************/
-
-/****************************************************************************/
-/**
-*
-* Gets the options for the specified driver instance. The options are
-* implemented as bit masks such that multiple options may be enabled or
-* disabled simultaneously.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-*
-* The current options for the UART. The options are bit masks that are
-* contained in the file xuartps.h and named XUARTPS_OPTION_*.
-*
-* @note None.
-*
-*****************************************************************************/
-u16 XUartPs_GetOptions(XUartPs *InstancePtr)
-{
- u16 Options = 0U;
- u32 Register;
- u32 Index;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Loop through the options table to map the physical options in the
- * registers of the UART to the logical options to be returned
- */
- for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
- Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- OptionsTable[Index].
- RegisterOffset);
-
- /*
- * If the bit in the register which correlates to the option
- * is set, then set the corresponding bit in the options,
- * ignoring any bits which are zero since the options variable
- * is initialized to zero
- */
- if ((Register & OptionsTable[Index].Mask) != (u32)0) {
- Options |= OptionsTable[Index].Option;
- }
- }
-
- return Options;
-}
-
-/****************************************************************************/
-/**
-*
-* Sets the options for the specified driver instance. The options are
-* implemented as bit masks such that multiple options may be enabled or
-* disabled simultaneously.
-*
-* The GetOptions function may be called to retrieve the currently enabled
-* options. The result is ORed in the desired new settings to be enabled and
-* ANDed with the inverse to clear the settings to be disabled. The resulting
-* value is then used as the options for the SetOption function call.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param Options contains the options to be set which are bit masks
-* contained in the file xuartps.h and named XUARTPS_OPTION_*.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options)
-{
- u32 Index;
- u32 Register;
-
- /* Assert validates the input arguments */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Loop through the options table to map the logical options to the
- * physical options in the registers of the UART.
- */
- for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
-
- /*
- * Read the register which contains option so that the register
- * can be changed without destoying any other bits of the
- * register.
- */
- Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- OptionsTable[Index].
- RegisterOffset);
-
- /*
- * If the option is set in the input, then set the corresponding
- * bit in the specified register, otherwise clear the bit in
- * the register.
- */
- if ((Options & OptionsTable[Index].Option) != (u16)0) {
- if(OptionsTable[Index].Option == XUARTPS_OPTION_SET_BREAK)
- Register &= ~XUARTPS_CR_STOPBRK;
- Register |= OptionsTable[Index].Mask;
- }
- else {
- Register &= ~OptionsTable[Index].Mask;
- }
-
- /* Write the new value to the register to set the option */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- OptionsTable[Index].RegisterOffset,
- Register);
- }
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the receive FIFO trigger level. The receive trigger
-* level indicates the number of bytes in the receive FIFO that cause a receive
-* data event (interrupt) to be generated.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return The current receive FIFO trigger level. This is a value
-* from 0-31.
-*
-* @note None.
-*
-*****************************************************************************/
-u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr)
-{
- u8 RtrigRegister;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the value of the FIFO control register so that the threshold
- * can be retrieved, this read takes special register processing
- */
- RtrigRegister = (u8) XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_RXWM_OFFSET);
-
- /* Return only the trigger level from the register value */
-
- RtrigRegister &= (u8)XUARTPS_RXWM_MASK;
- return RtrigRegister;
-}
-
-/****************************************************************************/
-/**
-*
-* This functions sets the receive FIFO trigger level. The receive trigger
-* level specifies the number of bytes in the receive FIFO that cause a receive
-* data event (interrupt) to be generated.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param TriggerLevel contains the trigger level to set.
-*
-* @return None
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel)
-{
- u32 RtrigRegister;
-
- /* Assert validates the input arguments */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(TriggerLevel <= (u8)XUARTPS_RXWM_MASK);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- RtrigRegister = ((u32)TriggerLevel) & (u32)XUARTPS_RXWM_MASK;
-
- /*
- * Write the new value for the FIFO control register to it such that the
- * threshold is changed
- */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_RXWM_OFFSET, RtrigRegister);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the modem status from the specified UART. The modem
-* status indicates any changes of the modem signals. This function allows
-* the modem status to be read in a polled mode. The modem status is updated
-* whenever it is read such that reading it twice may not yield the same
-* results.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-*
-* The modem status which are bit masks that are contained in the file
-* xuartps.h and named XUARTPS_MODEM_*.
-*
-* @note
-*
-* The bit masks used for the modem status are the exact bits of the modem
-* status register with no abstraction.
-*
-*****************************************************************************/
-u16 XUartPs_GetModemStatus(XUartPs *InstancePtr)
-{
- u32 ModemStatusRegister;
- u16 TmpRegister;
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Read the modem status register to return
- */
- ModemStatusRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_MODEMSR_OFFSET);
- TmpRegister = (u16)ModemStatusRegister;
- return TmpRegister;
-}
-
-/****************************************************************************/
-/**
-*
-* This function determines if the specified UART is sending data.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-* - TRUE if the UART is sending data
-* - FALSE if UART is not sending data
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XUartPs_IsSending(XUartPs *InstancePtr)
-{
- u32 ChanStatRegister;
- u32 ChanTmpSRegister;
- u32 ActiveResult;
- u32 EmptyResult;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the channel status register to determine if the transmitter is
- * active
- */
- ChanStatRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_SR_OFFSET);
-
- /*
- * If the transmitter is active, or the TX FIFO is not empty, then indicate
- * that the UART is still sending some data
- */
- ActiveResult = ChanStatRegister & ((u32)XUARTPS_SR_TACTIVE);
- EmptyResult = ChanStatRegister & ((u32)XUARTPS_SR_TXEMPTY);
- ChanTmpSRegister = (((u32)XUARTPS_SR_TACTIVE) == ActiveResult) ||
- (((u32)XUARTPS_SR_TXEMPTY) != EmptyResult);
-#if defined (XCLOCKING)
- if (!ChanTmpSRegister)
- Xil_ClockDisable(InstancePtr->Config.RefClk);
-#endif
- return ChanTmpSRegister;
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the operational mode of the UART. The UART can operate
-* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
-* echo.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-*
-* The operational mode is specified by constants defined in xuartps.h. The
-* constants are named XUARTPS_OPER_MODE_*
-*
-* @note None.
-*
-*****************************************************************************/
-u8 XUartPs_GetOperMode(XUartPs *InstancePtr)
-{
- u32 ModeRegister;
- u8 OperMode;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Read the Mode register. */
- ModeRegister =
- XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_MR_OFFSET);
-
- ModeRegister &= (u32)XUARTPS_MR_CHMODE_MASK;
- /* Return the constant */
- switch (ModeRegister) {
- case XUARTPS_MR_CHMODE_NORM:
- OperMode = XUARTPS_OPER_MODE_NORMAL;
- break;
- case XUARTPS_MR_CHMODE_ECHO:
- OperMode = XUARTPS_OPER_MODE_AUTO_ECHO;
- break;
- case XUARTPS_MR_CHMODE_L_LOOP:
- OperMode = XUARTPS_OPER_MODE_LOCAL_LOOP;
- break;
- case XUARTPS_MR_CHMODE_R_LOOP:
- OperMode = XUARTPS_OPER_MODE_REMOTE_LOOP;
- break;
- default:
- OperMode = (u8) ((ModeRegister & (u32)XUARTPS_MR_CHMODE_MASK) >>
- XUARTPS_MR_CHMODE_SHIFT);
- break;
- }
-
- return OperMode;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the operational mode of the UART. The UART can operate
-* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
-* echo.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param OperationMode is the mode of the UART.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode)
-{
- u32 ModeRegister;
-
- /* Assert validates the input arguments. */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(OperationMode <= XUARTPS_OPER_MODE_REMOTE_LOOP);
-
- /* Read the Mode register. */
- ModeRegister =
- XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_MR_OFFSET);
-
- /* Set the correct value by masking the bits, then ORing the const. */
- ModeRegister &= (u32)(~XUARTPS_MR_CHMODE_MASK);
-
- switch (OperationMode) {
- case XUARTPS_OPER_MODE_NORMAL:
- ModeRegister |= (u32)XUARTPS_MR_CHMODE_NORM;
- break;
- case XUARTPS_OPER_MODE_AUTO_ECHO:
- ModeRegister |= (u32)XUARTPS_MR_CHMODE_ECHO;
- break;
- case XUARTPS_OPER_MODE_LOCAL_LOOP:
- ModeRegister |= (u32)XUARTPS_MR_CHMODE_L_LOOP;
- break;
- case XUARTPS_OPER_MODE_REMOTE_LOOP:
- ModeRegister |= (u32)XUARTPS_MR_CHMODE_R_LOOP;
- break;
- default:
- /* Default case made for MISRA-C Compliance. */
- break;
- }
-
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
- ModeRegister);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the Flow Delay.
-* 0 - 3: Flow delay inactive
-* 4 - 32: If Flow Control mode is enabled, UART_rtsN is deactivated when the
-* receive FIFO fills to this level.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-*
-* The Flow Delay is specified by constants defined in xuartps_hw.h. The
-* constants are named XUARTPS_FLOWDEL*
-*
-* @note None.
-*
-*****************************************************************************/
-u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr)
-{
- u32 FdelTmpRegister;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Read the Mode register. */
- FdelTmpRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_FLOWDEL_OFFSET);
-
- /* Return the contents of the flow delay register */
- FdelTmpRegister = (u8)(FdelTmpRegister & (u32)XUARTPS_FLOWDEL_MASK);
- return FdelTmpRegister;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the Flow Delay.
-* 0 - 3: Flow delay inactive
-* 4 - 63: If Flow Control mode is enabled, UART_rtsN is deactivated when the
-* receive FIFO fills to this level.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param FlowDelayValue is the Setting for the flow delay.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue)
-{
- u32 FdelRegister;
-
- /* Assert validates the input arguments */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(FlowDelayValue > (u8)XUARTPS_FLOWDEL_MASK);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Set the correct value by shifting the input constant, then masking
- * the bits
- */
- FdelRegister = ((u32)FlowDelayValue) & (u32)XUARTPS_FLOWDEL_MASK;
-
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_FLOWDEL_OFFSET, FdelRegister);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the Receive Timeout of the UART.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return The current setting for receive time out.
-*
-* @note None.
-*
-*****************************************************************************/
-u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr)
-{
- u32 RtoRegister;
- u8 RtoRTmpRegister;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Read the Receive Timeout register. */
- RtoRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_RXTOUT_OFFSET);
-
- /* Return the contents of the mode register shifted appropriately */
- RtoRTmpRegister = (u8)(RtoRegister & (u32)XUARTPS_RXTOUT_MASK);
- return RtoRTmpRegister;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the Receive Timeout of the UART.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param RecvTimeout setting allows the UART to detect an idle connection
-* on the receiver data line.
-* Timeout duration = RecvTimeout x 4 x Bit Period. 0 disables the
-* timeout function.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout)
-{
- u32 RtoRegister;
-
- /* Assert validates the input arguments */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Set the correct value by masking the bits */
- RtoRegister = ((u32)RecvTimeout & (u32)XUARTPS_RXTOUT_MASK);
-
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_RXTOUT_OFFSET, RtoRegister);
-
- /* Configure CR to restart the receiver timeout counter */
- RtoRegister =
- XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_CR_OFFSET);
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
- (RtoRegister | XUARTPS_CR_TORST));
-
-}
-/****************************************************************************/
-/**
-*
-* Sets the data format for the device. The data format includes the
-* baud rate, number of data bits, number of stop bits, and parity. It is the
-* caller's responsibility to ensure that the UART is not sending or receiving
-* data when this function is called.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param FormatPtr is a pointer to a format structure containing the data
-* format to be set.
-*
-* @return
-* - XST_SUCCESS if the data format was successfully set.
-* - XST_UART_BAUD_ERROR indicates the baud rate could not be
-* set because of the amount of error with the baud rate and
-* the input clock frequency.
-* - XST_INVALID_PARAM if one of the parameters was not valid.
-*
-* @note
-*
-* The data types in the format type, data bits and parity, are 32 bit fields
-* to prevent a compiler warning.
-* The asserts in this function will cause a warning if these fields are
-* bytes.
-*
-*
-*****************************************************************************/
-s32 XUartPs_SetDataFormat(XUartPs *InstancePtr,
- XUartPsFormat * FormatPtr)
-{
- s32 Status;
- u32 ModeRegister;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(FormatPtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Verify the inputs specified are valid */
- if ((FormatPtr->DataBits > ((u32)XUARTPS_FORMAT_6_BITS)) ||
- (FormatPtr->StopBits > ((u8)XUARTPS_FORMAT_2_STOP_BIT)) ||
- (FormatPtr->Parity > ((u32)XUARTPS_FORMAT_NO_PARITY))) {
- Status = XST_INVALID_PARAM;
- } else {
-
- /*
- * Try to set the baud rate and if it's not successful then don't
- * continue altering the data format, this is done first to avoid the
- * format from being altered when an error occurs
- */
- Status = XUartPs_SetBaudRate(InstancePtr, FormatPtr->BaudRate);
- if (Status != (s32)XST_SUCCESS) {
- ;
- } else {
-
- ModeRegister =
- XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_MR_OFFSET);
-
- /*
- * Set the length of data (8,7,6) by first clearing out the bits
- * that control it in the register, then set the length in the register
- */
- ModeRegister &= (u32)(~XUARTPS_MR_CHARLEN_MASK);
- ModeRegister |= (FormatPtr->DataBits << XUARTPS_MR_CHARLEN_SHIFT);
-
- /*
- * Set the number of stop bits in the mode register by first clearing
- * out the bits that control it in the register, then set the number
- * of stop bits in the register.
- */
- ModeRegister &= (u32)(~XUARTPS_MR_STOPMODE_MASK);
- ModeRegister |= (((u32)FormatPtr->StopBits) << XUARTPS_MR_STOPMODE_SHIFT);
-
- /*
- * Set the parity by first clearing out the bits that control it in the
- * register, then set the bits in the register, the default is no parity
- * after clearing the register bits
- */
- ModeRegister &= (u32)(~XUARTPS_MR_PARITY_MASK);
- ModeRegister |= (FormatPtr->Parity << XUARTPS_MR_PARITY_SHIFT);
-
- /* Update the mode register */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
- ModeRegister);
-
- Status = XST_SUCCESS;
- }
- }
- return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* Gets the data format for the specified UART. The data format includes the
-* baud rate, number of data bits, number of stop bits, and parity.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param FormatPtr is a pointer to a format structure that will contain
-* the data format after this call completes.
-*
-* @return None.
-*
-* @note None.
-*
-*
-*****************************************************************************/
-void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr)
-{
- u32 ModeRegister;
-
-
- /* Assert validates the input arguments */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(FormatPtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Get the baud rate from the instance, this is not retrieved from the
- * hardware because it is only kept as a divisor such that it is more
- * difficult to get back to the baud rate
- */
- FormatPtr->BaudRate = InstancePtr->BaudRate;
-
- ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_MR_OFFSET);
-
- /* Get the length of data (8,7,6,5) */
- FormatPtr->DataBits =
- ((ModeRegister & (u32)XUARTPS_MR_CHARLEN_MASK) >>
- XUARTPS_MR_CHARLEN_SHIFT);
-
- /* Get the number of stop bits */
- FormatPtr->StopBits =
- (u8)((ModeRegister & (u32)XUARTPS_MR_STOPMODE_MASK) >>
- XUARTPS_MR_STOPMODE_SHIFT);
-
- /* Determine what parity is */
- FormatPtr->Parity =
- (u32)((ModeRegister & (u32)XUARTPS_MR_PARITY_MASK) >>
- XUARTPS_MR_PARITY_SHIFT);
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/85/60a9fd555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/85/60a9fd555243001d18b399c1eb9b3628
deleted file mode 100644
index 85a1af4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/85/60a9fd555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,202 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2012 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_mmu.c
-*
-* This file provides APIs for enabling/disabling MMU and setting the memory
-* attributes for sections, in the MMU translation table.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 01/12/12 Initial version
-* 3.05a asa 03/10/12 Modified the Xil_EnableMMU to invalidate the caches
-* before enabling back.
-* 3.05a asa 04/15/12 Modified the Xil_SetTlbAttributes routine so that
-* translation table and branch predictor arrays are
-* invalidated, D-cache flushed before the attribute
-* change is applied. This is done so that the user
-* need not call Xil_DisableMMU before calling
-* Xil_SetTlbAttributes.
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-* 3.11a asa 09/23/13 Modified Xil_SetTlbAttributes to flush the complete
-* D cache after the translation table update. Removed the
-* redundant TLB invalidation in the same API at the beginning.
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-* It fixes CR#1008309.
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-#include "xil_mmu.h"
-#include "xil_errata.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-#define ARM_AR_MEM_TTB_SECT_SIZE 1024*1024
-#define ARM_AR_MEM_TTB_SECT_SIZE_MASK (~(ARM_AR_MEM_TTB_SECT_SIZE-1UL))
-/************************** Variable Definitions *****************************/
-
-extern u32 MMUTable;
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-* @brief This function sets the memory attributes for a section covering 1MB
-* of memory in the translation table.
-*
-* @param Addr: 32-bit address for which memory attributes need to be set.
-* @param attrib: Attribute for the given memory region. xil_mmu.h contains
-* definitions of commonly used memory attributes which can be
-* utilized for this function.
-*
-*
-* @return None.
-*
-* @note The MMU or D-cache does not need to be disabled before changing a
-* translation table entry.
-*
-******************************************************************************/
-void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib)
-{
- u32 *ptr;
- u32 section;
-
- section = Addr / 0x100000U;
- ptr = &MMUTable;
- ptr += section;
- if(ptr != NULL) {
- *ptr = (Addr & 0xFFF00000U) | attrib;
- }
-
- Xil_DCacheFlush();
-
- mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
- /* Invalidate all branch predictors */
- mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
-
- dsb(); /* ensure completion of the BP and TLB invalidation */
- isb(); /* synchronize context on this processor */
-}
-
-/*****************************************************************************/
-/**
-* @brief Enable MMU for cortex A9 processor. This function invalidates the
-* instruction and data caches, and then enables MMU.
-*
-* @return None.
-*
-******************************************************************************/
-void Xil_EnableMMU(void)
-{
- u32 Reg;
- Xil_DCacheInvalidate();
- Xil_ICacheInvalidate();
-
-#ifdef __GNUC__
- Reg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, Reg);
-#else
- { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
- Reg = Cp15Reg; }
-#endif
- Reg |= (u32)0x05U;
- mtcp(XREG_CP15_SYS_CONTROL, Reg);
-
- dsb();
- isb();
-}
-
-/*****************************************************************************/
-/**
-* @brief Disable MMU for Cortex A9 processors. This function invalidates
-* the TLBs, Branch Predictor Array and flushed the D Caches before
-* disabling the MMU.
-*
-* @return None.
-*
-* @note When the MMU is disabled, all the memory accesses are treated as
-* strongly ordered.
-******************************************************************************/
-void Xil_DisableMMU(void)
-{
- u32 Reg;
-
- mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
- mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
- Xil_DCacheFlush();
-
-#ifdef __GNUC__
- Reg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, Reg);
-#else
- { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
- Reg = Cp15Reg; }
-#endif
- Reg &= (u32)(~0x05U);
-#ifdef CONFIG_ARM_ERRATA_794073
- /* Disable Branch Prediction */
- Reg &= (u32)(~0x800U);
-#endif
- mtcp(XREG_CP15_SYS_CONTROL, Reg);
-}
-
-/*****************************************************************************/
-/**
-* @brief Memory mapping for Cortex A9 processor.
-*
-* @param PhysAddr is physical address.
-* @param size is size of region.
-* @param flags is flags used to set translation table.
-*
-* @return Pointer to virtual address.
-*
-* @note: Previously this was implemented in libmetal. Move to embeddedsw as this
-* functionality is specific to A9 processor.
-*
-******************************************************************************/
-void* Xil_MemMap(UINTPTR PhysAddr, size_t size, u32 flags)
-{
- u32 Sectionoffset;
- u32 Ttbaddr;
-
- if (!flags)
- return (void*)PhysAddr;
-
- /* Ensure alignment on a section boundary */
- PhysAddr &= ARM_AR_MEM_TTB_SECT_SIZE_MASK;
-
- /* Loop through entire region of memory (one MMU section at a time).
- Each section requires a TTB entry. */
- for (Sectionoffset = 0; Sectionoffset < size;
- Sectionoffset += ARM_AR_MEM_TTB_SECT_SIZE) {
- /* Calculate translation table entry for this memory section */
- Ttbaddr = (PhysAddr + Sectionoffset);
-
- /* Write translation table entry value to entry address */
- Xil_SetTlbAttributes(Ttbaddr, flags);
- }
- return (void*)PhysAddr;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/85/b0d9cb575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/85/b0d9cb575243001d18b399c1eb9b3628
deleted file mode 100644
index 179c840..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/85/b0d9cb575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,329 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xdmaps.h
-* @addtogroup dmaps_v2_8
-* @{
-* @details
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00 hbm 08/19/10 First Release
-* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
-* the maximum number of channels.
-* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
-* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
-* Added the tcl file to automatically generate the
-* xparameters.h
-* 1.02a sg 05/16/12 Made changes for doxygen and moved some function
-* header from the xdmaps.h file to xdmaps.c file
-* Other cleanup for coding guidelines and CR 657109
-* and CR 657898
-* The xdmaps_example_no_intr.c example is removed
-* as it is using interrupts and is similar to
-* the interrupt example - CR 652477
-* 1.03a sg 07/16/2012 changed inline to __inline for CR665681
-* 1.04a nm 10/22/2012 Fixed CR# 681671.
-* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled
-* with -Wall and -Wextra option in bsp.
-* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
-* function description.
-* Fixed CR# 704396. Removed unused variables
-* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
-* function.
-* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc.
-* Removed the PDBG prints. By default they were always
-* defined out and never used. The PDBG is non-standard for
-* Xilinx drivers and no other driver does something similar.
-* Since there is no easy way to fix compilation issues with
-* the IARCC compiler around PDBG, it is better to remove it.
-* Users can always use xil_printfs if they want to debug.
-* 2.0 adk 10/12/13 Updated as per the New Tcl API's
-* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
-* 2.2 mus 08/12/16 Declared all inline functions in xdmaps.c as extern, to avoid
-* linker error for IAR compiler
-* 2.3 ms 01/23/17 Modified xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 2.4 adk 13/08/18 Fixed armcc compiler warnings in the driver CR-1008310.
-* 2.8 sk 05/18/21 Modify all inline functions declarations from extern inline
-* to static inline to avoid the linkage conflict for IAR compiler.
-*
-*
-*****************************************************************************/
-
-#ifndef XDMAPS_H /* prevent circular inclusions */
-#define XDMAPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xparameters.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-
-#include "xdmaps_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of device (IPIF) */
-} XDmaPs_Config;
-
-
-/** DMA channle control structure. It's for AXI bus transaction.
- * This struct will be translated into a 32-bit channel control register value.
- */
-typedef struct {
- unsigned int EndianSwapSize; /**< Endian swap size. */
- unsigned int DstCacheCtrl; /**< Destination cache control */
- unsigned int DstProtCtrl; /**< Destination protection control */
- unsigned int DstBurstLen; /**< Destination burst length */
- unsigned int DstBurstSize; /**< Destination burst size */
- unsigned int DstInc; /**< Destination incrementing or fixed
- * address */
- unsigned int SrcCacheCtrl; /**< Source cache control */
- unsigned int SrcProtCtrl; /**< Source protection control */
- unsigned int SrcBurstLen; /**< Source burst length */
- unsigned int SrcBurstSize; /**< Source burst size */
- unsigned int SrcInc; /**< Source incrementing or fixed
- * address */
-} XDmaPs_ChanCtrl;
-
-/** DMA block descriptor stucture.
- */
-typedef struct {
- u32 SrcAddr; /**< Source starting address */
- u32 DstAddr; /**< Destination starting address */
- unsigned int Length; /**< Number of bytes for the block */
-} XDmaPs_BD;
-
-/**
- * A DMA command consisits of a channel control struct, a block descriptor,
- * a user defined program, a pointer pointing to generated DMA program, and
- * execution result.
- *
- */
-typedef struct {
- XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */
- XDmaPs_BD BD; /**< Together with SgLength field,
- * it's a scatter-gather list.
- */
- void *UserDmaProg; /**< If user wants the driver to
- * execute their own DMA program,
- * this field points to the DMA
- * program.
- */
- int UserDmaProgLength; /**< The length of user defined
- * DMA program.
- */
-
- void *GeneratedDmaProg; /**< The DMA program genreated
- * by the driver. This field will be
- * set if a user invokes the DMA
- * program generation function. Or
- * the DMA command is finished and
- * a user informs the driver not to
- * release the program buffer.
- * This field has two purposes, one
- * is to ask the driver to generate
- * a DMA program while the DMAC is
- * performaning DMA transactions. The
- * other purpose is to debug the
- * driver.
- */
- int GeneratedDmaProgLength; /**< The length of the DMA program
- * generated by the driver
- */
- int DmaStatus; /**< 0 on success, otherwise error code
- */
- u32 ChanFaultType; /**< Channel fault type in case of fault
- */
- u32 ChanFaultPCAddr; /**< Channel fault PC address
- */
-} XDmaPs_Cmd;
-
-/**
- * It's the done handler a user can set for a channel
- */
-typedef void (*XDmaPsDoneHandler) (unsigned int Channel,
- XDmaPs_Cmd *DmaCmd,
- void *CallbackRef);
-
-/**
- * It's the fault handler a user can set for a channel
- */
-typedef void (*XDmaPsFaultHandler) (unsigned int Channel,
- XDmaPs_Cmd *DmaCmd,
- void *CallbackRef);
-
-#define XDMAPS_MAX_CHAN_BUFS 2
-#define XDMAPS_CHAN_BUF_LEN 128
-
-/**
- * The XDmaPs_ProgBuf is the struct for a DMA program buffer.
- */
-typedef struct {
- char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the
- * content */
- unsigned Len; /**< The actual length of the DMA
- * program in bytes. */
- int Allocated; /**< A tag indicating whether the
- * buffer is allocated or not */
-} XDmaPs_ProgBuf;
-
-/**
- * The XDmaPs_ChannelData is a struct to book keep individual channel of
- * the DMAC.
- */
-typedef struct {
- unsigned DevId; /**< Device id indicating which DMAC */
- unsigned ChanId; /**< Channel number of the DMAC */
- XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of
- program buffers*/
- XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */
- void *DoneRef; /**< Done interrupt callback data */
- XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */
- XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished.
- * This field is for debugging purpose
- */
- int HoldDmaProg; /**< A tag indicating whether to hold the
- * DMA program after the DMA is done.
- */
-
-} XDmaPs_ChannelData;
-
-/**
- * The XDmaPs driver instance data structure. A pointer to an instance data
- * structure is passed around by functions to refer to a specific driver
- * instance.
- */
-typedef struct {
- XDmaPs_Config Config; /**< Configuration data structure */
- int IsReady; /**< Device is Ready */
- int CacheLength; /**< icache length */
- XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */
- void *FaultRef; /**< fault call back data */
- XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV];
- /**<
- * channel data
- */
-} XDmaPs;
-
-/*
- * Functions implemented in xdmaps.c
- */
-int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
- XDmaPs_Config *Config,
- u32 EffectiveAddr);
-
-int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
- XDmaPs_Cmd *Cmd,
- int HoldDmaProg);
-
-int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel);
-int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel,
- XDmaPs_Cmd *Cmd);
-int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel,
- XDmaPs_Cmd *Cmd);
-void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
-
-
-int XDmaPs_ResetManager(XDmaPs *InstPtr);
-int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel);
-
-
-int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
- unsigned Channel,
- XDmaPsDoneHandler DoneHandler,
- void *CallbackRef);
-
-int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
- XDmaPsFaultHandler FaultHandler,
- void *CallbackRef);
-
-void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
-int XDmaPs_Instr_DMARMB(char *DmaProg);
-int XDmaPs_Instr_DMAWMB(char *DmaProg);
-
-/**
- * To avoid linkage error,modify all inline functions from extern
- * inline to static inline for IAR compiler
- */
-#ifdef __ICCARM__
-static INLINE int XDmaPs_Instr_DMAEND(char *DmaProg);
-static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src);
-static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
- u32 Imm, unsigned int Ns);
-static INLINE int XDmaPs_Instr_DMALD(char *DmaProg);
-static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
- unsigned LoopIterations);
-static INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc);
-static INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm);
-static INLINE int XDmaPs_Instr_DMANOP(char *DmaProg);
-static INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber);
-static INLINE int XDmaPs_Instr_DMAST(char *DmaProg);
-static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize);
-static INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize);
-#endif
-
-/**
- * Driver done interrupt service routines for the channels.
- * We need this done ISR mainly because the driver needs to release the
- * DMA program buffer. This is the one that connects the GIC
- */
-void XDmaPs_DoneISR_0(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_1(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_2(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_3(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_4(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_5(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_6(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_7(XDmaPs *InstPtr);
-
-/**
- * Driver fault interrupt service routine
- */
-void XDmaPs_FaultISR(XDmaPs *InstPtr);
-
-
-/*
- * Static loopup function implemented in xdmaps_sinit.c
- */
-XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId);
-
-
-/*
- * self-test functions in xdmaps_selftest.c
- */
-int XDmaPs_SelfTest(XDmaPs *InstPtr);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/85/b2341f595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/85/b2341f595243001d18b399c1eb9b3628
deleted file mode 100644
index 06fa5cc..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/85/b2341f595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,115 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_mmu.h
-*
-* @addtogroup r5_mpu_apis Cortex R5 Processor MPU specific APIs
-*
-* MPU functions provides access to MPU operations such as enable MPU, disable
-* MPU and set attribute for section of memory.
-* Boot code invokes Init_MPU function to configure the MPU. A total of 10 MPU
-* regions are allocated with another 6 being free for users. Overview of the
-* memory attributes for different MPU regions is as given below,
-*
-*| | Memory Range | Attributes of MPURegion |
-*|-----------------------|-------------------------|-----------------------------|
-*| DDR | 0x00000000 - 0x7FFFFFFF | Normal write-back Cacheable |
-*| PL | 0x80000000 - 0xBFFFFFFF | Strongly Ordered |
-*| QSPI | 0xC0000000 - 0xDFFFFFFF | Device Memory |
-*| PCIe | 0xE0000000 - 0xEFFFFFFF | Device Memory |
-*| STM_CORESIGHT | 0xF8000000 - 0xF8FFFFFF | Device Memory |
-*| RPU_R5_GIC | 0xF9000000 - 0xF90FFFFF | Device memory |
-*| FPS | 0xFD000000 - 0xFDFFFFFF | Device Memory |
-*| LPS | 0xFE000000 - 0xFFFFFFFF | Device Memory |
-*| OCM | 0xFFFC0000 - 0xFFFFFFFF | Normal write-back Cacheable |
-*
-*
-* @note
-* For a system where DDR is less than 2GB, region after DDR and before PL is
-* marked as undefined in translation table. Memory range 0xFE000000-0xFEFFFFFF is
-* allocated for upper LPS slaves, where as memory region 0xFF000000-0xFFFFFFFF is
-* allocated for lower LPS slaves.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00 pkp 02/10/14 Initial version
-* 6.4 asa 08/16/17 Added many APIs for MPU access to make MPU usage
-* user-friendly. The APIs added are: Xil_UpdateMPUConfig,
-* Xil_GetMPUConfig, Xil_GetNumOfFreeRegions,
-* Xil_GetNextMPURegion, Xil_DisableMPURegionByRegNum,
-* Xil_GetMPUFreeRegMask, Xil_SetMPURegionByRegNum, and
-* Xil_InitializeExistingMPURegConfig.
-* Added a new array of structure of type XMpuConfig to
-* represent the MPU configuration table.
-*
-*
-
-*
-*
-******************************************************************************/
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_MPU_H
-#define XIL_MPU_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-#include "xil_types.h"
-/***************************** Include Files *********************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#define MPU_REG_DISABLED 0U
-#define MPU_REG_ENABLED 1U
-#define MAX_POSSIBLE_MPU_REGS 16U
-/**************************** Type Definitions *******************************/
-struct XMpuConfig{
- u32 RegionStatus; /* Enabled or disabled */
- INTPTR BaseAddress;/* MPU region base address */
- u64 Size; /* MPU region size address */
- u32 Attribute; /* MPU region size attribute */
-};
-
-typedef struct XMpuConfig XMpu_Config[MAX_POSSIBLE_MPU_REGS];
-
-extern XMpu_Config Mpu_Config;
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-/**
- *@endcond
- */
-
-void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
-void Xil_EnableMPU(void);
-void Xil_DisableMPU(void);
-u32 Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib);
-u32 Xil_UpdateMPUConfig(u32 reg_num, INTPTR address, u32 size, u32 attrib);
-void Xil_GetMPUConfig (XMpu_Config mpuconfig);
-u32 Xil_GetNumOfFreeRegions (void);
-u32 Xil_GetNextMPURegion(void);
-u32 Xil_DisableMPURegionByRegNum (u32 reg_num);
-u16 Xil_GetMPUFreeRegMask (void);
-u32 Xil_SetMPURegionByRegNum (u32 reg_num, INTPTR addr, u64 size, u32 attrib);
-void* Xil_MemMap(UINTPTR Physaddr, size_t size, u32 flags);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_MPU_H */
-/**
-* @} End of "addtogroup r5_mpu_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/86/015555585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/86/015555585243001d18b399c1eb9b3628
deleted file mode 100644
index 61da4bc..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/86/015555585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,7 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/* Stub call for argv veneer */
-void __ARM_argv_veneer(void) {};
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/86/40eea0565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/86/40eea0565243001d18b399c1eb9b3628
deleted file mode 100644
index 6f419fb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/86/40eea0565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,69 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2008 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-* microblaze_invalidate_dcache()
-*
-* Invalidate the entire L1 DCache
-*
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-#include "microblaze_instructions.h"
-
-#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
-#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
-
-#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
-#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
-#endif
-
-#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
-#define MB_VERSION_LT_v720
-#endif
-
- .text
- .globl microblaze_invalidate_dcache
- .ent microblaze_invalidate_dcache
- .align 2
-
-microblaze_invalidate_dcache:
-#if (XPAR_MICROBLAZE_USE_DCACHE==1) && (XPAR_MICROBLAZE_ALLOW_DCACHE_WR==1)
-
-#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
- mfs r9, rmsr
- andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
- mts rmsr, r10
-#endif
- ADDIK r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN))
- ADDIK r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */
-
-L_start:
- wdc r5, r0 /* Invalidate the Cache */
-
- CMPU r18, r5, r6 /* Are we at the end? */
- BLEI r18, L_done
-
-#if defined (__arch64__ )
- addlik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the address by 4 */
- breai L_start
-#else
- brid L_start /* Branch to the beginning of the loop */
- addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the address by 4 (delay slot) */
-#endif
-L_done:
- rtsd r15, 8 /* Return */
-#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
- mts rmsr, r9
-#else
- nop
-#endif
-
-#else
- rtsd r15, 8 /* Return */
- nop
-#endif
- .end microblaze_invalidate_dcache
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/86/519d43545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/86/519d43545243001d18b399c1eb9b3628
deleted file mode 100644
index 878d575..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/86/519d43545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,261 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_misc_psreset_api.h
-*
-* This file contains the various register definitions and function prototypes for
-* implementing the reset functionality of zynq ps devices
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00b kpc 03/07/13 First release.
-*
-*
-******************************************************************************/
-
-#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */
-#define XIL_MISC_RESET_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/**
- *@cond nocomments
- */
-
-#define XDDRC_CTRL_BASEADDR 0xF8006000U
-#define XSLCR_BASEADDR 0xF8000000U
-/**< OCM configuration register */
-#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U)
-/**< SLCR unlock register */
-#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U)
-/**< SLCR GEM0 rx clock control register */
-#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U)
-/**< SLCR GEM1 rx clock control register */
-#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU)
-/**< SLCR GEM0 clock control register */
-#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U)
-/**< SLCR GEM1 clock control register */
-#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U)
-/**< SLCR SMC clock control register */
-#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U)
-/**< SLCR GEM reset control register */
-#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)
-/**< SLCR USB0 clock control register */
-#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U)
-/**< SLCR USB1 clock control register */
-#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U)
-/**< SLCR USB1 reset control register */
-#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)
-/**< SLCR SMC reset control register */
-#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)
-/**< SLCR Level shifter enable register */
-#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U)
-/**< SLCR ARM pll control register */
-#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U)
-/**< SLCR DDR pll control register */
-#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U)
-/**< SLCR IO pll control register */
-#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U)
-/**< SLCR ARM pll configuration register */
-#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U)
-/**< SLCR DDR pll configuration register */
-#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U)
-/**< SLCR IO pll configuration register */
-#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U)
-/**< SLCR ARM clock control register */
-#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U)
-/**< SLCR DDR clock control register */
-#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U)
-/**< SLCR MIO pin address register */
-#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U)
-/**< SLCR DMAC reset control address register */
-#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU)
-/**< SLCR USB reset control address register */
-/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/
-/**< SLCR GEM reset control address register */
-/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/
-/**< SLCR SDIO reset control address register */
-#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U)
-/**< SLCR SPI reset control address register */
-#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU)
-/**< SLCR CAN reset control address register */
-#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U)
-/**< SLCR I2C reset control address register */
-#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U)
-/**< SLCR UART reset control address register */
-#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U)
-/**< SLCR GPIO reset control address register */
-#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU)
-/**< SLCR LQSPI reset control address register */
-#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U)
-/**< SLCR SMC reset control address register */
-/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/
-/**< SLCR OCM reset control address register */
-#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U)
-
-/**< SMC mem controller clear config register */
-#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU
-/**< SMC idlecount configuration register */
-#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U
-#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U
-/**< SMC ECC configuration register */
-#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U
-/**< SMC ECC command 1 register */
-#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U
-/**< SMC ECC command 2 register */
-#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U
-
-/**< SLCR unlock code */
-#define XSLCR_UNLOCK_CODE 0x0000DF0DU
-
-/**< SMC mem clear configuration mask */
-#define XSMC_MEMC_CLR_CONFIG_MASK 0x000005FU
-/**< SMC ECC memconfig 1 reset value */
-#define XSMC_ECC_MEMCFG1_RESET_VAL 0x0000043U
-/**< SMC ECC memcommand 1 reset value */
-#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U
-/**< SMC ECC memcommand 2 reset value */
-#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U
-
-/**< DDR controller reset bit mask */
-#define XDDRPS_CTRL_RESET_MASK 0x00000001U
-/**< SLCR OCM configuration reset value*/
-#define XSLCR_OCM_CFG_RESETVAL 0x00000008U
-/**< SLCR OCM bank selection mask*/
-#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU
-/**< SLCR level shifter enable mask*/
-#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU
-
-/**< SLCR PLL register reset values */
-#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U
-#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U
-#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U
-#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U
-#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U
-#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U
-#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U
-#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U
-
-/**< SLCR MIO register default values */
-#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U
-#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U
-
-/**< SLCR Reset control registers default values */
-#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U
-#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U
-#define XSLCR_USB_RST_CTRL_VAL 0x00000003U
-#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U
-#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU
-#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU
-#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U
-#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U
-#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U
-#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U
-#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U
-#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U
-
-/**
- *@endcond
- */
-
-/**************************** Type Definitions *******************************/
-
-/* the following data type is used to hold a null terminated version string
- * consisting of the following format, "X.YYX"
- */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-/*
- * Performs reset operation to the ddr interface
- */
-void XDdr_ResetHw(void);
-/*
- * Map the ocm region to post bootrom state
- */
-void XOcm_Remap(void);
-/*
- * Performs the smc interface reset
- */
-void XSmc_ResetHw(u32 BaseAddress);
-/*
- * updates the MIO registers with reset values
- */
-void XSlcr_MioWriteResetValues(void);
-/*
- * updates the PLL and clock registers with reset values
- */
-void XSlcr_PllWriteResetValues(void);
-/*
- * Disables the level shifters
- */
-void XSlcr_DisableLevelShifters(void);
-/*
- * provides softreset to the GPIO interface
- */
-void XSlcr_GpioPsReset(void);
-/*
- * provides softreset to the DMA interface
- */
-void XSlcr_DmaPsReset(void);
-/*
- * provides softreset to the SMC interface
- */
-void XSlcr_SmcPsReset(void);
-/*
- * provides softreset to the CAN interface
- */
-void XSlcr_CanPsReset(void);
-/*
- * provides softreset to the Uart interface
- */
-void XSlcr_UartPsReset(void);
-/*
- * provides softreset to the I2C interface
- */
-void XSlcr_I2cPsReset(void);
-/*
- * provides softreset to the SPI interface
- */
-void XSlcr_SpiPsReset(void);
-/*
- * provides softreset to the QSPI interface
- */
-void XSlcr_QspiPsReset(void);
-/*
- * provides softreset to the USB interface
- */
-void XSlcr_UsbPsReset(void);
-/*
- * provides softreset to the GEM interface
- */
-void XSlcr_EmacPsReset(void);
-/*
- * provides softreset to the OCM interface
- */
-void XSlcr_OcmReset(void);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_MISC_RESET_H */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/86/51cbd6565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/86/51cbd6565243001d18b399c1eb9b3628
deleted file mode 100644
index 21c8ced..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/86/51cbd6565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,75 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache_l.h
-*
-* Contains L1 and L2 specific functions for the ARM cache functionality
-* used by xcache.c. This functionality is being made available here for
-* more sophisticated users.
-*
-* @addtogroup a9_cache_apis
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 01/24/10 First release
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-*
-******************************************************************************/
-#ifndef XIL_CACHE_MACH_H
-#define XIL_CACHE_MACH_H
-
-#include "xil_types.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Function Prototypes ******************************/
-
-void Xil_DCacheInvalidateLine(u32 adr);
-void Xil_DCacheFlushLine(u32 adr);
-void Xil_DCacheStoreLine(u32 adr);
-void Xil_ICacheInvalidateLine(u32 adr);
-
-void Xil_L1DCacheEnable(void);
-void Xil_L1DCacheDisable(void);
-void Xil_L1DCacheInvalidate(void);
-void Xil_L1DCacheInvalidateLine(u32 adr);
-void Xil_L1DCacheInvalidateRange(u32 adr, u32 len);
-void Xil_L1DCacheFlush(void);
-void Xil_L1DCacheFlushLine(u32 adr);
-void Xil_L1DCacheFlushRange(u32 adr, u32 len);
-void Xil_L1DCacheStoreLine(u32 adr);
-
-void Xil_L1ICacheEnable(void);
-void Xil_L1ICacheDisable(void);
-void Xil_L1ICacheInvalidate(void);
-void Xil_L1ICacheInvalidateLine(u32 adr);
-void Xil_L1ICacheInvalidateRange(u32 adr, u32 len);
-
-void Xil_L2CacheEnable(void);
-void Xil_L2CacheDisable(void);
-void Xil_L2CacheInvalidate(void);
-void Xil_L2CacheInvalidateLine(u32 adr);
-void Xil_L2CacheInvalidateRange(u32 adr, u32 len);
-void Xil_L2CacheFlush(void);
-void Xil_L2CacheFlushLine(u32 adr);
-void Xil_L2CacheFlushRange(u32 adr, u32 len);
-void Xil_L2CacheStoreLine(u32 adr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-* @} End of "addtogroup a9_cache_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/86/6194b0585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/86/6194b0585243001d18b399c1eb9b3628
deleted file mode 100644
index 8eb4638..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/86/6194b0585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,24 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf);
-}
-#endif
-/*
- * fstat -- Since we have no file system, we just return an error.
- */
-__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf)
-{
- (void)fd;
- buf->st_mode = S_IFCHR; /* Always pretend to be a tty */
-
- return (0);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/87/60cc8f555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/87/60cc8f555243001d18b399c1eb9b3628
deleted file mode 100644
index 9d97c3a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/87/60cc8f555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,41 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: MIT
-*
-******************************************************************************/
-#include "xil_printf.h"
-#include "xparameters.h"
-
-__attribute__((weak)) s32 _sys_write(__attribute__((unused)) u32 fh,
- const u8 *buf, u32 len,
- __attribute__((unused)) s32 mode)
-{
-#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
- return XPVXenConsole_Write(buf);
-#else
-#ifdef STDOUT_BASEADDRESS
- char8* LocalBuf = (char8 *)buf;
- u32 i;
-
- for (i = 0; i < len; i++) {
- /* wait if TNFUL */
- if(LocalBuf != NULL) {
- LocalBuf += i;
- }
- if(LocalBuf != NULL) {
- if (*LocalBuf == '\n') {
- outbyte('\r');
- }
- outbyte(*LocalBuf);
- }
- if(LocalBuf != NULL) {
- LocalBuf -= i;
- }
- }
-
- return len;
-#endif
-#endif
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/87/7257af545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/87/7257af545243001d18b399c1eb9b3628
deleted file mode 100644
index 8731605..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/87/7257af545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,268 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xgpio_intr.c
-* @addtogroup gpio_v4_8
-* @{
-*
-* Implements GPIO interrupt processing functions for the XGpio driver.
-* See xgpio.h for more information about the driver.
-*
-* The functions in this file require the hardware device to be built with
-* interrupt capabilities. The functions will assert if called using hardware
-* that does not have interrupt capabilities.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 2.00a jhl 11/26/03 Initial release
-* 2.11a mta 03/21/07 Updated to new coding style
-* 2.12a sv 06/05/08 Updated driver to fix the XGpio_InterruptDisable function
-* to properly update the Interrupt Enable register
-* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the macros
-* XGpio_mWriteReg to XGpio_WriteReg, and XGpio_mReadReg
-* to XGpio_ReadReg.
-
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xgpio.h"
-
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-
-/****************************************************************************/
-/**
-* Enable the interrupt output signal. Interrupts enabled through
-* XGpio_InterruptEnable() will not be passed through until the global enable
-* bit is set by this function. This function is designed to allow all
-* interrupts (both channels) to be enabled easily for exiting a critical
-* section. This function will assert if the hardware device has not been
-* built with interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpio_InterruptGlobalEnable(XGpio *InstancePtr)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
-
- XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_GIE_OFFSET,
- XGPIO_GIE_GINTR_ENABLE_MASK);
-}
-
-
-/****************************************************************************/
-/**
-* Disable the interrupt output signal. Interrupts enabled through
-* XGpio_InterruptEnable() will no longer be passed through until the global
-* enable bit is set by XGpio_InterruptGlobalEnable(). This function is
-* designed to allow all interrupts (both channels) to be disabled easily for
-* entering a critical section. This function will assert if the hardware
-* device has not been built with interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpio_InterruptGlobalDisable(XGpio *InstancePtr)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
-
-
- XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_GIE_OFFSET, 0x0);
-
-}
-
-
-/****************************************************************************/
-/**
-* Enable interrupts. The global interrupt must also be enabled by calling
-* XGpio_InterruptGlobalEnable() for interrupts to occur. This function will
-* assert if the hardware device has not been built with interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-* @param Mask is the mask to enable. Bit positions of 1 are enabled.
-* This mask is formed by OR'ing bits from XGPIO_IR* bits which
-* are contained in xgpio_l.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
-
- /*
- * Read the interrupt enable register and only enable the specified
- * interrupts without disabling or enabling any others.
- */
-
- Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
- XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET,
- Register | Mask);
-
-}
-
-
-/****************************************************************************/
-/**
-* Disable interrupts. This function allows specific interrupts for each
-* channel to be disabled. This function will assert if the hardware device
-* has not been built with interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-* @param Mask is the mask to disable. Bits set to 1 are disabled. This
-* mask is formed by OR'ing bits from XGPIO_IR* bits which are
-* contained in xgpio_l.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
-
- /*
- * Read the interrupt enable register and only disable the specified
- * interrupts without enabling or disabling any others.
- */
- Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
- XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET,
- Register & (~Mask));
-
-}
-
-/****************************************************************************/
-/**
-* Clear pending interrupts with the provided mask. This function should be
-* called after the software has serviced the interrupts that are pending.
-* This function will assert if the hardware device has not been built with
-* interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-* @param Mask is the mask to clear pending interrupts for. Bit positions
-* of 1 are cleared. This mask is formed by OR'ing bits from
-* XGPIO_IR* bits which are contained in xgpio_l.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpio_InterruptClear(XGpio * InstancePtr, u32 Mask)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
-
- /*
- * Read the interrupt status register and only clear the interrupts
- * that are specified without affecting any others. Since the register
- * is a toggle on write, make sure any bits to be written are already
- * set.
- */
- Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET);
- XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET,
- Register & Mask);
-
-
-}
-
-
-/****************************************************************************/
-/**
-* Returns the interrupt enable mask. This function will assert if the
-* hardware device has not been built with interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-*
-* @return A mask of bits made from XGPIO_IR* bits which are contained in
-* xgpio_l.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpio_InterruptGetEnabled(XGpio * InstancePtr)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(InstancePtr->InterruptPresent == TRUE);
-
- return XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
-}
-
-
-/****************************************************************************/
-/**
-* Returns the status of interrupt signals. Any bit in the mask set to 1
-* indicates that the channel associated with the bit has asserted an interrupt
-* condition. This function will assert if the hardware device has not been
-* built with interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-*
-* @return A pointer to a mask of bits made from XGPIO_IR* bits which are
-* contained in xgpio_l.h.
-*
-* @note
-*
-* The interrupt status indicates the status of the device regardless if
-* the interrupts from the devices have been enabled or not through
-* XGpio_InterruptEnable().
-*
-*****************************************************************************/
-u32 XGpio_InterruptGetStatus(XGpio * InstancePtr)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(InstancePtr->InterruptPresent == TRUE);
-
-
- return XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET);
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/87/8002ff585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/87/8002ff585243001d18b399c1eb9b3628
deleted file mode 100644
index 9d17f5c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/87/8002ff585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,86 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xtime_l.h
-* @addtogroup a9_time_apis Cortex A9 Time Functions
-*
-* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This
-* counter increases by one at every two processor cycles. These functions can
-* be used to get/set time in the global timer.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 1.00a rp/sdm 11/03/09 Initial release.
-* 3.06a sgd 05/15/12 Updated get/set time functions to make use Global Timer
-* 3.06a asa 06/17/12 Reverted back the changes to make use Global Timer.
-* 3.07a sgd 07/05/12 Updated get/set time functions to make use Global Timer
-* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep
-* implementation
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
-* displaying same warnings multiple times. It fixes CR#1090562.
-*
-*
-******************************************************************************/
-
-/**
-*@cond nocomments
-*/
-
-#ifndef XTIME_H /* prevent circular inclusions */
-#define XTIME_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xparameters.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-typedef u64 XTime;
-
-/************************** Constant Definitions *****************************/
-#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR
-#define GTIMER_COUNTER_LOWER_OFFSET 0x00U
-#define GTIMER_COUNTER_UPPER_OFFSET 0x04U
-#define GTIMER_CONTROL_OFFSET 0x08U
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY)
-#else
-/* Global Timer is always clocked at half of the CPU frequency */
-#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
-#endif
-/************************** Variable Definitions *****************************/
-
-/**
-*@endcond
-*/
-
-/************************** Function Prototypes ******************************/
-
-void XTime_SetTime(XTime Xtime_Global);
-void XTime_GetTime(XTime *Xtime_Global);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XTIME_H */
-/**
-* @} End of "addtogroup a9_time_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/87/8006c3545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/87/8006c3545243001d18b399c1eb9b3628
deleted file mode 100644
index e79ba0d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/87/8006c3545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,788 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xqspips.h
-* @addtogroup qspips_v3_9
-* @{
-* @details
-*
-* This file contains the implementation of the XQspiPs driver. It supports only
-* master mode. User documentation for the driver functions is contained in this
-* file in the form of comment blocks at the front of each function.
-*
-* A QSPI device connects to an QSPI bus through a 4-wire serial interface.
-* The QSPI bus is a full-duplex, synchronous bus that facilitates communication
-* between one master and one slave. The device is always full-duplex,
-* which means that for every byte sent, one is received, and vice-versa.
-* The master controls the clock, so it can regulate when it wants to
-* send or receive data. The slave is under control of the master, it must
-* respond quickly since it has no control of the clock and must send/receive
-* data as fast or as slow as the master does.
-*
-* Linear Mode
-* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller�s
-* functionality by adding a linear addressing scheme that allows the SPI flash
-* memory subsystem to behave like a typical ROM device. The new feature hides
-* the normal SPI protocol from a master reading from the SPI flash memory. The
-* feature improves both the user friendliness and the overall read memory
-* throughput over that of the current Quad-SPI Controller by lessening the
-* amount of software overheads required and by the use of the faster AXI
-* interface.
-*
-* Initialization & Configuration
-*
-* The XQspiPs_Config structure is used by the driver to configure itself. This
-* configuration structure is typically created by the tool-chain based on HW
-* build properties.
-*
-* To support multiple runtime loading and initialization strategies employed by
-* various operating systems, the driver instance can be initialized in the
-* following way:
-* - XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find
-* static configuration structure defined in xqspips_g.c. This is setup
-* by the tools. For some operating systems the config structure will be
-* initialized by the software and this call is not needed.
-* - XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-* configuration structure provided by the caller. If running in a system
-* with address translation, the provided virtual memory base address
-* replaces the physical address present in the configuration structure.
-*
-* Multiple Masters
-*
-* More than one master can exist, but arbitration is the responsibility of
-* the higher layer software. The device driver does not perform any type of
-* arbitration.
-*
-* Modes of Operation
-*
-* There are four modes to perform a data transfer and the selection of a mode
-* is based on Chip Select(CS) and Start. These two options individually, can
-* be controlled either by software(Manual) or hardware(Auto).
-* - Auto CS: Chip select is automatically asserted as soon as the first word
-* is written into the TXFIFO and de asserted when the TXFIFO becomes
-* empty
-* - Manual CS: Software must assert and de assert CS.
-* - Auto Start: Data transmission starts as soon as there is data in the
-* TXFIFO and stalls when the TXFIFO is empty
-* - Manual Start: Software must start data transmission at the beginning of
-* the transaction or whenever the TXFIFO has become empty
-*
-* The preferred combination is Manual CS and Auto Start.
-* In this combination, the software asserts CS before loading any data into
-* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
-* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
-* data is available. If no further data, software disables CS.
-*
-* Risks/challenges of other combinations:
-* - Manual CS and Manual Start: Manual Start bit should be set after each
-* TXFIFO write otherwise there could be a race condition where the TXFIFO
-* becomes empty before the new word is written. In that case the
-* transmission stops.
-* - Auto CS with Manual or Auto Start: It is very difficult for software to
-* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted.
-* This results in a single transaction to be split into multiple pieces each
-* with its own chip select. This will result in garbage data to be sent.
-*
-* Interrupts
-*
-* The user must connect the interrupt handler of the driver,
-* XQspiPs_InterruptHandler, to an interrupt system such that it will be
-* called when an interrupt occurs. This function does not save and restore
-* the processor context such that the user must provide this processing.
-*
-* The driver handles the following interrupts:
-* - Data Transmit Register/FIFO Underflow
-* - Data Receive Register/FIFO Not Empty
-* - Data Transmit Register/FIFO Overwater
-* - Data Receive Register/FIFO Overrun
-*
-* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
-* QSPI device has transmitted the data available to transmit, and now its data
-* register and FIFO is ready to accept more data. The driver uses this
-* interrupt to indicate progress while sending data. The driver may have
-* more data to send, in which case the data transmit register and FIFO is
-* filled for subsequent transmission. When this interrupt arrives and all
-* the data has been sent, the driver invokes the status callback with a
-* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
-* all data has been sent.
-*
-* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
-* as slave, the QSPI device was required to transmit but there was no data
-* available to transmit in the transmit register (or FIFO). This may not
-* be an error if the master is not expecting data. But in the case where
-* the master is expecting data, this serves as a notification of such a
-* condition. The driver reports this condition to the upper layer
-* software through the status handler.
-*
-* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI
-* device received data and subsequently dropped the data because the data
-* receive register and FIFO was full. The driver reports this condition to the
-* upper layer software through the status handler. This likely indicates a
-* problem with the higher layer protocol, or a problem with the slave
-* performance.
-*
-*
-* Polled Operation
-*
-* Transfer in polled mode is supported through a separate interface function
-* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
-* this function blocks until all data has been sent/received.
-*
-* Device Busy
-*
-* Some operations are disallowed when the device is busy. The driver tracks
-* whether a device is busy. The device is considered busy when a data transfer
-* request is outstanding, and is considered not busy only when that transfer
-* completes (or is aborted with a mode fault error).
-*
-* Device Configuration
-*
-* The device can be configured in various ways during the FPGA implementation
-* process. Configuration parameters are stored in the xqspips_g.c file or
-* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry
-* contains configuration information for an QSPI device, including the base
-* address for the device.
-*
-* RTOS Independence
-*
-* This driver is intended to be RTOS and processor independent. It works with
-* physical addresses only. Any needs for dynamic memory management, threads or
-* thread mutual exclusion, virtual memory, or cache control must be satisfied
-* by the layer above this driver.
-*
-* NOTE: This driver was always tested with endianness set to little-endian.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
-* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
-* in xparameters.h
-* 2.00a kka 07/25/12 Added a few register defines for CR 670297
-* Removed code related to mode fault for CR 671468
-* The XQspiPs_SetSlaveSelect has been modified to remove
-* the argument of the slave select as the QSPI controller
-* only supports one slave.
-* XQspiPs_GetSlaveSelect API has been removed
-* Added a flag ShiftReadData to the instance structure
-*. and is used in the XQspiPs_GetReadData API.
-* The ShiftReadData Flag indicates whether the data
-* read from the Rx FIFO needs to be shifted
-* in cases where the data is less than 4 bytes
-* Removed the selection for the following options:
-* Master mode (XQSPIPS_MASTER_OPTION) and
-* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
-* as the QSPI driver supports the Master mode
-* and Flash Interface mode and doesnot support
-* Slave mode or the legacy mode.
-* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
-* APIs so that the last argument (IsInst) specifying whether
-* it is instruction or data has been removed. The first byte
-* in the SendBufPtr argument of these APIs specify the
-* instruction to be sent to the Flash Device.
-* This version of the driver fixes CRs 670197/663787/
-* 670297/671468.
-* Added the option for setting the Holdb_dr bit in the
-* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
-* is the option to be used for setting this bit in the
-* configuration register.
-* The XQspiPs_PolledTransfer function has been updated
-* to fill the data to fifo depth.
-* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
-* Added macros for Set/Get Rx Watermark. Changed QSPI
-* Enable/Disable macro argument from BaseAddress to
-* Instance Pointer. Added DelayNss argument to SetDelays
-* and GetDelays API's.
-* Created macros XQspiPs_IsManualStart and
-* XQspiPs_IsManualChipSelect.
-* Changed QSPI transfer logic for polled and interrupt
-* modes to be based on filled tx fifo count and receive
-* based on it. RXNEMPTY interrupt is not used.
-* Added assertions to XQspiPs_LqspiRead function.
-* SetDelays and GetDelays API's include DelayNss parameter.
-* Added defines for DelayNss,Rx Watermark,Interrupts
-* which need write to clear. Removed Read zeros mask from
-* LQSPI Config register. Renamed Fixed burst error to
-* data FSM error in LQSPI Status register.
-*
-* 2.02a hk 05/07/13 Added ConnectionMode to config structure.
-* Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
-* Added enable and disable to the XQspiPs_LqspiRead() function
-* Removed XQspi_Reset() in Set_Options() function when
-* LQSPI_MODE_OPTION is set.
-* Added instructions for bank selection, die erase and
-* flag status register to the flash instruction table
-* Handling for instructions not in flash instruction
-* table added. Checking for Tx FIFO empty when switching from
-* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
-* byte count 3 (spansion), instruction size and TXD register
-* changed accordingly. CR# 712502 and 703869.
-* Added prefix to constant definitions for ConnectionMode
-* Added (\#ifdef linear base address) in the Linear read function.
-* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to
-* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
-* XQspiPs_LqspiRead function. Fix for CR#718141.
-*
-* 2.03a hk 09/17/13 Modified polled and interrupt transfers to make use of
-* thresholds. This is to improve performance.
-* Added API's for QSPI reset and
-* linear mode initialization for boot.
-* Added RX and TX threshold reset to one in XQspiPs_Abort.
-* Added RX threshold reset(1) after transfer in polled and
-* interrupt transfers. Made changes to make sure threshold
-* change is done only when no transfer is in progress.
-* Updated linear init API for parallel and stacked modes.
-* CR#737760.
-* 3.1 hk 08/13/14 When writing to the configuration register, set/reset
-* required bits leaving reserved bits untouched. CR# 796813.
-* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
-* controller does not update FIFO status flags as expected
-* when thresholds are used.
-* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
-* to remove compilation warnings. CR# 868893.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/05/17 Modified Comment lines in functions of qspips
-* examples to recognize it as documentation block
-* and modified filename tag in
-* xqspips_dual_flash_stack_lqspi_example.c to include it in
-* doxygen examples.
-* 3.4 nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file
-* 3.5 tjs 08/21/18 Fixed compilation warnings for the ARMCC.
-* 3.5 tjs 07/16/18 Added support for low density ISSI flash parts.
-* 3.6 akm 03/28/19 Fixed memory leak issue while reading from qspi.(CR#1016357)
-* 3.6 akm 04/15/19 Modified FlashQuadEnable, FlashWrie and FlashErase APIs,
-* to wait for the on going operation to complete before
-* performing the next operation.
-* 3.6 akm 04/15/19 Modified the mask in XQspiPs_GetReadData() API to retrieve
-* configuration register values of both the Flashes in dual
-* parellel connection.
-* 3.7 akm 11/19/19 Fixed Coverity unused value warning in XQspiPs_PolledTransfer()
-* and XQspiPs_Transfer() APIs.
-* 3.7 akm 03/19/20 Modified XQspiPs_PolledTransfer(), XQspiPs_Transfer() and
-* XQspiPs_InterruptHandler() APIs to fill TX FIFO with valid
-* data when RX buffer is not NULL.
-* 3.8 akm 09/02/20 Updated the Makefile to support parallel make execution.
-*
-*
-*
-******************************************************************************/
-#ifndef XQSPIPS_H /* prevent circular inclusions */
-#define XQSPIPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xqspips_hw.h"
-#include
-
-/************************** Constant Definitions *****************************/
-
-/** @name Configuration options
- *
- * The following options are supported to enable/disable certain features of
- * an QSPI device. Each of the options is a bit mask, so more than one may be
- * specified.
- *
- *
- * The Active Low Clock option configures the device's clock polarity.
- * Setting this option means the clock is active low and the SCK signal idles
- * high. By default, the clock is active high and SCK idles low.
- *
- * The Clock Phase option configures the QSPI device for one of two
- * transfer formats. A clock phase of 0, the default, means data is valid on
- * the first SCK edge (rising or falling) after the slave select (SS) signal
- * has been asserted. A clock phase of 1 means data is valid on the second SCK
- * edge (rising or falling) after SS has been asserted.
- *
- *
- * The QSPI Force Slave Select option is used to enable manual control of
- * the slave select signal.
- * 0: The SPI_SS signal is controlled by the QSPI controller during
- * transfers. (Default)
- * 1: The SPI_SS signal is forced active (driven low) regardless of any
- * transfers in progress.
- *
- * NOTE: The driver will handle setting and clearing the Slave Select when
- * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
- * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the
- * processor cannot empty and refill the FIFOs before the TX FIFO is empty
- * When the QSPI hardware is controlling the Slave Select signals, this
- * will cause slave to be de-selected and terminate the transfer.
- *
- * The Manual Start option is used to enable manual control of
- * the Start command to perform data transfer.
- * 0: The Start command is controlled by the QSPI controller during
- * transfers(Default). Data transmission starts as soon as there is data in
- * the TXFIFO and stalls when the TXFIFO is empty
- * 1: The Start command must be issued by software to perform data transfer.
- * Bit 15 of Configuration register is used to issue Start command. This bit
- * must be set whenever TXFIFO is filled with new data.
- *
- * NOTE: The driver will set the Manual Start Enable bit in Configuration
- * Register, if Manual Start option is selected. Software will issue
- * Manual Start command whenever TXFIFO is filled with data. When there is
- * no further data, driver will clear the Manual Start Enable bit.
- *
- * @{
- */
-#define XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2 /**< Active Low Clock option */
-#define XQSPIPS_CLK_PHASE_1_OPTION 0x4 /**< Clock Phase one option */
-#define XQSPIPS_FORCE_SSELECT_OPTION 0x10 /**< Force Slave Select */
-#define XQSPIPS_MANUAL_START_OPTION 0x20 /**< Manual Start enable */
-#define XQSPIPS_LQSPI_MODE_OPTION 0x80 /**< Linear QPSI mode */
-#define XQSPIPS_HOLD_B_DRIVE_OPTION 0x100 /**< Drive HOLD_B Pin */
-/*@}*/
-
-
-/** @name QSPI Clock Prescaler options
- * The QSPI Clock Prescaler Configuration bits are used to program master mode
- * bit rate. The bit rate can be programmed in divide-by-two decrements from
- * pclk/2 to pclk/256.
- *
- * @{
- */
-#define XQSPIPS_CLK_PRESCALE_2 0x00 /**< PCLK/2 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_4 0x01 /**< PCLK/4 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_8 0x02 /**< PCLK/8 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_16 0x03 /**< PCLK/16 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_32 0x04 /**< PCLK/32 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_64 0x05 /**< PCLK/64 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_128 0x06 /**< PCLK/128 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_256 0x07 /**< PCLK/256 Prescaler */
-
-/*@}*/
-
-
-/** @name Callback events
- *
- * These constants specify the handler events that are passed to
- * a handler from the driver. These constants are not bit masks such that
- * only one will be passed at a time to the handler.
- *
- * @{
- */
-#define XQSPIPS_EVENT_TRANSFER_DONE 2 /**< Transfer done */
-#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
-#define XQSPIPS_EVENT_RECEIVE_OVERRUN 4 /**< Receive data loss because
- * RX FIFO full
- */
-/*@}*/
-
-/** @name Flash commands
- *
- * The following constants define most of the commands supported by flash
- * devices. Users can add more commands supported by the flash devices
- *
- * @{
- */
-#define XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */
-#define XQSPIPS_FLASH_OPCODE_PP 0x02 /* Page program */
-#define XQSPIPS_FLASH_OPCODE_NORM_READ 0x03 /* Normal read data bytes */
-#define XQSPIPS_FLASH_OPCODE_WRDS 0x04 /* Write disable */
-#define XQSPIPS_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */
-#define XQSPIPS_FLASH_OPCODE_WREN 0x06 /* Write enable */
-#define XQSPIPS_FLASH_OPCODE_FAST_READ 0x0B /* Fast read data bytes */
-#define XQSPIPS_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */
-#define XQSPIPS_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */
-#define XQSPIPS_FLASH_OPCODE_DUAL_READ 0x3B /* Dual read data bytes */
-#define XQSPIPS_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */
-#define XQSPIPS_FLASH_OPCODE_QUAD_READ 0x6B /* Quad read data bytes */
-#define XQSPIPS_FLASH_OPCODE_ERASE_SUS 0x75 /* Erase suspend */
-#define XQSPIPS_FLASH_OPCODE_ERASE_RES 0x7A /* Erase resume */
-#define XQSPIPS_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */
-#define XQSPIPS_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */
-#define XQSPIPS_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/
-#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */
-#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */
-#define XQSPIPS_FLASH_OPCODE_BRWR 0x17 /* Bank Register Write */
-#define XQSPIPS_FLASH_OPCODE_BRRD 0x16 /* Bank Register Read */
-/* Extende Address Register Write - Micron's equivalent of Bank Register */
-#define XQSPIPS_FLASH_OPCODE_EARWR 0xC5
-/* Extende Address Register Read - Micron's equivalent of Bank Register */
-#define XQSPIPS_FLASH_OPCODE_EARRD 0xC8
-#define XQSPIPS_FLASH_OPCODE_DIE_ERASE 0xC4
-#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR 0x70
-#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR 0x50
-#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG 0xE8 /* Lock Reg Read */
-#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG 0xE5 /* Lock Reg Write */
-
-/*@}*/
-
-/** @name Instruction size
- *
- * The following constants define numbers 1 to 4.
- * Used to identify whether TXD0,1,2 or 3 is to be used.
- *
- * @{
- */
-#define XQSPIPS_SIZE_ONE 1
-#define XQSPIPS_SIZE_TWO 2
-#define XQSPIPS_SIZE_THREE 3
-#define XQSPIPS_SIZE_FOUR 4
-
-/*@}*/
-
-/** @name ConnectionMode
- *
- * The following constants are the possible values of ConnectionMode in
- * Config structure.
- *
- * @{
- */
-#define XQSPIPS_CONNECTION_MODE_SINGLE 0
-#define XQSPIPS_CONNECTION_MODE_STACKED 1
-#define XQSPIPS_CONNECTION_MODE_PARALLEL 2
-
-/*@}*/
-
-/** @name FIFO threshold value
- *
- * This is the Rx FIFO threshold (in words) that was found to be most
- * optimal in terms of performance
- *
- * @{
- */
-#define XQSPIPS_RXFIFO_THRESHOLD_OPT 32
-
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-/**
- * The handler data type allows the user to define a callback function to
- * handle the asynchronous processing for the QSPI device. The application
- * using this driver is expected to define a handler of this type to support
- * interrupt driven mode. The handler executes in an interrupt context, so
- * only minimal processing should be performed.
- *
- * @param CallBackRef is the callback reference passed in by the upper
- * layer when setting the callback functions, and passed back to
- * the upper layer when the callback is invoked. Its type is
- * not important to the driver, so it is a void pointer.
- * @param StatusEvent holds one or more status events that have occurred.
- * See the XQspiPs_SetStatusHandler() for details on the status
- * events that can be passed in the callback.
- * @param ByteCount indicates how many bytes of data were successfully
- * transferred. This may be less than the number of bytes
- * requested if the status event indicates an error.
- */
-typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
- unsigned ByteCount);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of the device */
- u32 InputClockHz; /**< Input clock frequency */
- u8 ConnectionMode; /**< Single, Stacked and Parallel mode */
-} XQspiPs_Config;
-
-/**
- * The XQspiPs driver instance data. The user is required to allocate a
- * variable of this type for every QSPI device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XQspiPs_Config Config; /**< Configuration structure */
- u32 IsReady; /**< Device is initialized and ready */
-
- u8 *SendBufferPtr; /**< Buffer to send (state) */
- u8 *RecvBufferPtr; /**< Buffer to receive (state) */
- int RequestedBytes; /**< Number of bytes to transfer (state) */
- int RemainingBytes; /**< Number of bytes left to transfer(state) */
- u32 IsBusy; /**< A transfer is in progress (state) */
- XQspiPs_StatusHandler StatusHandler;
- void *StatusRef; /**< Callback reference for status handler */
- u32 ShiftReadData; /**< Flag to indicate whether the data
- * read from the Rx FIFO needs to be shifted
- * in cases where the data is less than 4
- * bytes
- */
-} XQspiPs;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/*
-*
-* Check in OptionsTable if Manual Start Option is enabled or disabled.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return
-* - TRUE if option is set
-* - FALSE if option is not set
-*
-* @note C-Style signature:
-* u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr);
-*
-*****************************************************************************/
-#define XQspiPs_IsManualStart(InstancePtr) \
- ((XQspiPs_GetOptions(InstancePtr) & \
- XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
-
-/****************************************************************************/
-/*
-*
-* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
-*
-* @param InstancePtr is a pointer to the XSpiPs instance.
-*
-* @return
-* - TRUE if option is set
-* - FALSE if option is not set
-*
-* @note C-Style signature:
-* u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr);
-*
-*****************************************************************************/
-#define XQspiPs_IsManualChipSelect(InstancePtr) \
- ((XQspiPs_GetOptions(InstancePtr) & \
- XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the slave idle count register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written, valid values are
-* 0-255.
-*
-* @return None
-*
-* @note C-Style signature:
-* void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr,
-* u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_SICR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_*
-* constants defined in xqspips_hw.h to interpret the bit-mask returned.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return An 8-bit value representing Slave Idle Count.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetSlaveIdle(InstancePtr) \
- XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_SICR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the transmit FIFO watermark register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written, valid values are 1-63.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr,
-* u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_TXWR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the transmit FIFO watermark register.
-* Valid values are in the range 1-63.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return A 6-bit value representing Tx Watermark level.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetTXWatermark(InstancePtr) \
- XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the receive FIFO watermark register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written, valid values are 1-63.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr,
-* u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_RXWR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the receive FIFO watermark register.
-* Valid values are in the range 1-63.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return A 6-bit value representing Rx Watermark level.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetRXWatermark(InstancePtr) \
- XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Enable the device and uninhibit master transactions.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_Enable(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_Enable(InstancePtr) \
- XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
- XQSPIPS_ER_ENABLE_MASK)
-
-/****************************************************************************/
-/**
-*
-* Disable the device.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_Disable(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_Disable(InstancePtr) \
- XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the Linear QSPI Configuration register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written to the Linear QSPI
-* configuration register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr,
-* u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the Linear QSPI Configuration register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return A 32-bit value representing the contents of the LQSPI Config
-* register.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetLqspiConfigReg(InstancePtr) \
- XQspiPs_In32((InstancePtr->Config.BaseAddress) + \
- XQSPIPS_LQSPI_CR_OFFSET)
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Initialization function, implemented in xqspips_sinit.c
- */
-XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
-
-/*
- * Functions implemented in xqspips.c
- */
-int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *Config,
- u32 EffectiveAddr);
-void XQspiPs_Reset(XQspiPs *InstancePtr);
-void XQspiPs_Abort(XQspiPs *InstancePtr);
-
-s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
- u32 ByteCount);
-s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
- u8 *RecvBufPtr, u32 ByteCount);
-int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
- u32 Address, unsigned ByteCount);
-
-int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
-
-void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
- XQspiPs_StatusHandler FuncPtr);
-void XQspiPs_InterruptHandler(void *InstancePtr);
-
-/*
- * Functions for selftest, in xqspips_selftest.c
- */
-int XQspiPs_SelfTest(XQspiPs *InstancePtr);
-
-/*
- * Functions for options, in xqspips_options.c
- */
-s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options);
-u32 XQspiPs_GetOptions(XQspiPs *InstancePtr);
-
-s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
-u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
-
-int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
- u8 DelayAfter, u8 DelayInit);
-void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
- u8 *DelayAfter, u8 *DelayInit);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/87/b0c7e0545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/87/b0c7e0545243001d18b399c1eb9b3628
deleted file mode 100644
index 4bf1905..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/87/b0c7e0545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,70 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xscutimer_sinit.c
-* @addtogroup scutimer_v2_3
-* @{
-*
-* This file contains method for static initialization (compile-time) of the
-* driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm 03/10/10 First release
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xscutimer.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions ****************************/
-extern XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES];
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-* Lookup the device configuration based on the unique device ID. The table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId is the unique device ID of the device being looked up.
-*
-* @return A pointer to the configuration table entry corresponding to the
-* given device ID, or NULL if no match is found.
-*
-* @note None.
-*
-******************************************************************************/
-XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId)
-{
- XScuTimer_Config *CfgPtr = NULL;
- u32 Index;
-
- for (Index = 0U; Index < XPAR_XSCUTIMER_NUM_INSTANCES; Index++) {
- if (XScuTimer_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XScuTimer_ConfigTable[Index];
- break;
- }
- }
-
- return (XScuTimer_Config *)CfgPtr;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/87/c15688595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/87/c15688595243001d18b399c1eb9b3628
deleted file mode 100644
index 6b51ea9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/87/c15688595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,28 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-
-#ifndef _MBLAZE_NT_TYPES_H
-#define _MBLAZE_NT_TYPES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef char byte;
-typedef short half;
-typedef int word;
-typedef unsigned char ubyte;
-typedef unsigned short uhalf;
-typedef unsigned int uword;
-typedef ubyte boolean;
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/87/f0ffc1555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/87/f0ffc1555243001d18b399c1eb9b3628
deleted file mode 100644
index a146f83..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/87/f0ffc1555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,387 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_exception.h
-*
-* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
-* For exception related functions that can be used across all Xilinx supported
-* processors, please use xil_exception.h.
-*
-* @addtogroup arm_exception_apis ARM Processor Exception Handling
-* @{
-* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
-* utilized for enabling/disabling IRQ, registering/removing handler for
-* exceptions or initializing exception vector table with null handler.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
-* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler.
-* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.
-* 7.0 mus 01/03/19 Tweak Xil_ExceptionEnableMask and
-* Xil_ExceptionDisableMask macros to support legacy
-* examples for Cortexa72 EL3 exception level.
-* 7.3 mus 04/15/20 Added Xil_EnableNestedInterrupts and
-* Xil_DisableNestedInterrupts macros for ARMv8.
-* For Cortexa72, these macro's would not be supported
-* at EL3, as Cortexa72 is using GIC-500(GICv3), which
-* triggeres only FIQ at EL3. Fix for CR#1062506
-# 7.6 mus 09/17/21 Updated flag checking to fix warning reported with
-# -Wundef compiler option CR#1110261
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
-#define XIL_EXCEPTION_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#include "bspconfig.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions ****************************/
-
-#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
-#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
-#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
-
-#define XIL_EXCEPTION_ID_FIRST 0U
-#if defined (__aarch64__)
-#define XIL_EXCEPTION_ID_SYNC_INT 1U
-#define XIL_EXCEPTION_ID_IRQ_INT 2U
-#define XIL_EXCEPTION_ID_FIQ_INT 3U
-#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
-#define XIL_EXCEPTION_ID_LAST 5U
-#else
-#define XIL_EXCEPTION_ID_RESET 0U
-#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
-#define XIL_EXCEPTION_ID_SWI_INT 2U
-#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
-#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
-#define XIL_EXCEPTION_ID_IRQ_INT 5U
-#define XIL_EXCEPTION_ID_FIQ_INT 6U
-#define XIL_EXCEPTION_ID_LAST 6U
-#endif
-
-/*
- * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
- */
-#if defined (versal) && !defined(ARMR5) && EL3
-#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_FIQ_INT
-#else
-#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
-#endif
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef is the exception handler function.
- */
-typedef void (*Xil_ExceptionHandler)(void *data);
-typedef void (*Xil_InterruptHandler)(void *data);
-
-/**
-*@endcond
-*/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* @brief Enable Exceptions.
-*
-* @param Mask: Value for enabling the exceptions.
-*
-* @return None.
-*
-* @note If bit is 0, exception is enabled.
-* C-Style signature: void Xil_ExceptionEnableMask(Mask)
-*
-******************************************************************************/
-#if defined (versal) && !defined(ARMR5) && EL3
-/*
- * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
- * only FIQ at EL3. Hence, tweaking this macro to always enable FIQ
- * ignoring argument passed by user.
- */
-#define Xil_ExceptionEnableMask(Mask) \
- mtcpsr(mfcpsr() & ~ ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
-#elif defined (__GNUC__) || defined (__ICCARM__)
-#define Xil_ExceptionEnableMask(Mask) \
- mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
-#else
-#define Xil_ExceptionEnableMask(Mask) \
- { \
- register u32 Reg __asm("cpsr"); \
- mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
- }
-#endif
-/****************************************************************************/
-/**
-* @brief Enable the IRQ exception.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-#if defined (versal) && !defined(ARMR5) && EL3
-#define Xil_ExceptionEnable() \
- Xil_ExceptionEnableMask(XIL_EXCEPTION_FIQ)
-#else
-#define Xil_ExceptionEnable() \
- Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
-#endif
-
-/****************************************************************************/
-/**
-* @brief Disable Exceptions.
-*
-* @param Mask: Value for disabling the exceptions.
-*
-* @return None.
-*
-* @note If bit is 1, exception is disabled.
-* C-Style signature: Xil_ExceptionDisableMask(Mask)
-*
-******************************************************************************/
-#if defined (versal) && !defined(ARMR5) && EL3
-/*
- * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
- * only FIQ at EL3. Hence, tweaking this macro to always disable FIQ
- * ignoring argument passed by user.
- */
-#define Xil_ExceptionDisableMask(Mask) \
- mtcpsr(mfcpsr() | ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
-#elif defined (__GNUC__) || defined (__ICCARM__)
-#define Xil_ExceptionDisableMask(Mask) \
- mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
-#else
-#define Xil_ExceptionDisableMask(Mask) \
- { \
- register u32 Reg __asm("cpsr"); \
- mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
- }
-#endif
-/****************************************************************************/
-/**
-* Disable the IRQ exception.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_ExceptionDisable() \
- Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
-
-#if ( defined (PLATFORM_ZYNQMP) && defined (EL3) && (EL3==1) )
-/****************************************************************************/
-/**
-* @brief Enable nested interrupts by clearing the I bit in DAIF.This
-* macro is defined for Cortex-A53 64 bit mode BSP configured to run
-* at EL3.. However,it is not defined for Versal Cortex-A72 BSP
-* configured to run at EL3. Reason is, Cortex-A72 is coupled
-* with GIC-500(GICv3 specifications) and it triggers only FIQ at EL3.
-*
-* @return None.
-*
-* @note This macro is supposed to be used from interrupt handlers. In the
-* interrupt handler the interrupts are disabled by default (I bit
-* is set as 1). To allow nesting of interrupts, this macro should be
-* used. It clears the I bit. Once that bit is cleared and provided the
-* preemption of interrupt conditions are met in the GIC, nesting of
-* interrupts will start happening.
-* Caution: This macro must be used with caution. Before calling this
-* macro, the user must ensure that the source of the current IRQ
-* is appropriately cleared. Otherwise, as soon as we clear the I
-* bit, there can be an infinite loop of interrupts with an
-* eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
- __asm__ __volatile__ ("mrs X1, ELR_EL3"); \
- __asm__ __volatile__ ("mrs X2, SPSR_EL3"); \
- __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-/****************************************************************************/
-/**
-* @brief Disable the nested interrupts by setting the I bit in DAIF. This
-* macro is defined for Cortex-A53 64 bit mode BSP configured to run
-* at EL3.
-*
-* @return None.
-*
-* @note This macro is meant to be called in the interrupt service routines.
-* This macro cannot be used independently. It can only be used when
-* nesting of interrupts have been enabled by using the macro
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-* point. The user then must call this macro before exiting the interrupt
-* service routine. This macro puts the ARM back in IRQ mode and
-* hence sets back the I bit.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
- __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \
- __asm__ __volatile__ ("msr ELR_EL3, X1"); \
- __asm__ __volatile__ ("msr SPSR_EL3, X2"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-#elif (defined (EL1_NONSECURE) && (EL1_NONSECURE==1))
-/****************************************************************************/
-/**
-* @brief Enable nested interrupts by clearing the I bit in DAIF.This
-* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit
-* BSP configured to run at EL1 NON SECURE
-*
-* @return None.
-*
-* @note This macro is supposed to be used from interrupt handlers. In the
-* interrupt handler the interrupts are disabled by default (I bit
-* is set as 1). To allow nesting of interrupts, this macro should be
-* used. It clears the I bit. Once that bit is cleared and provided the
-* preemption of interrupt conditions are met in the GIC, nesting of
-* interrupts will start happening.
-* Caution: This macro must be used with caution. Before calling this
-* macro, the user must ensure that the source of the current IRQ
-* is appropriately cleared. Otherwise, as soon as we clear the I
-* bit, there can be an infinite loop of interrupts with an
-* eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
- __asm__ __volatile__ ("mrs X1, ELR_EL1"); \
- __asm__ __volatile__ ("mrs X2, SPSR_EL1"); \
- __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-/****************************************************************************/
-/**
-* @brief Disable the nested interrupts by setting the I bit in DAIF. This
-* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit
-* BSP configured to run at EL1 NON SECURE
-*
-* @return None.
-*
-* @note This macro is meant to be called in the interrupt service routines.
-* This macro cannot be used independently. It can only be used when
-* nesting of interrupts have been enabled by using the macro
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-* point. The user then must call this macro before exiting the interrupt
-* service routine. This macro puts the ARM back in IRQ mode and
-* hence sets back the I bit.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
- __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \
- __asm__ __volatile__ ("msr ELR_EL1, X1"); \
- __asm__ __volatile__ ("msr SPSR_EL1, X2"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-#elif (!defined (__aarch64__) && !defined (ARMA53_32))
-/****************************************************************************/
-/**
-* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This
-* API is defined for cortex-a9 and cortex-r5.
-*
-* @return None.
-*
-* @note This macro is supposed to be used from interrupt handlers. In the
-* interrupt handler the interrupts are disabled by default (I and F
-* are 1). To allow nesting of interrupts, this macro should be
-* used. It clears the I and F bits by changing the ARM mode to
-* system mode. Once these bits are cleared and provided the
-* preemption of interrupt conditions are met in the GIC, nesting of
-* interrupts will start happening.
-* Caution: This macro must be used with caution. Before calling this
-* macro, the user must ensure that the source of the current IRQ
-* is appropriately cleared. Otherwise, as soon as we clear the I and
-* F bits, there can be an infinite loop of interrupts with an
-* eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
- __asm__ __volatile__ ("stmfd sp!, {lr}"); \
- __asm__ __volatile__ ("mrs lr, spsr"); \
- __asm__ __volatile__ ("stmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
- __asm__ __volatile__ ("stmfd sp!, {lr}");
-/****************************************************************************/
-/**
-* @brief Disable the nested interrupts by setting the I and F bits. This API
-* is defined for cortex-a9 and cortex-r5.
-*
-* @return None.
-*
-* @note This macro is meant to be called in the interrupt service routines.
-* This macro cannot be used independently. It can only be used when
-* nesting of interrupts have been enabled by using the macro
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-* point. The user then must call this macro before exiting the interrupt
-* service routine. This macro puts the ARM back in IRQ/FIQ mode and
-* hence sets back the I and F bits.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr cpsr_c, #0x92"); \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr spsr_cxsf, lr"); \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
-
-#endif
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler Handler,
- void *Data);
-
-extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
-extern void Xil_GetExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler *Handler, void **Data);
-
-extern void Xil_ExceptionInit(void);
-#if defined (__aarch64__)
-void Xil_SyncAbortHandler(void *CallBackRef);
-void Xil_SErrorAbortHandler(void *CallBackRef);
-#else
-extern void Xil_DataAbortHandler(void *CallBackRef);
-extern void Xil_PrefetchAbortHandler(void *CallBackRef);
-extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
-#endif
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_EXCEPTION_H */
-/**
-* @} End of "addtogroup arm_exception_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/88/30355f575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/88/30355f575243001d18b399c1eb9b3628
deleted file mode 100644
index cd9ec37..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/88/30355f575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,380 +0,0 @@
-/*---------------------------------------------------------------------------/
-/ FatFs - Configuration file
-/---------------------------------------------------------------------------*/
-
-
-#define FFCONF_DEF 63463 /* Revision ID */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xparameters.h"
-
-/*---------------------------------------------------------------------------/
-/ Function Configurations
-/---------------------------------------------------------------------------*/
-
-#ifdef FILE_SYSTEM_READ_ONLY
-#define FF_FS_READONLY 1 /* 1:Read only */
-#else
-#define FF_FS_READONLY 0 /* 0:Read/Write */
-#endif
-/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
-/ Read-only configuration removes writing API functions, f_write(), f_sync(),
-/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
-/ and optional writing functions as well. */
-
-
-#define FF_FS_MINIMIZE 0
-/* This option defines minimization level to remove some basic API functions.
-/
-/ 0: Basic functions are fully enabled.
-/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
-/ are removed.
-/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
-/ 3: f_lseek() function is removed in addition to 2. */
-
-
-#if FILE_SYSTEM_USE_STRFUNC == 0
-#define FF_USE_STRFUNC 0 /* 0:Disable */
-#elif FILE_SYSTEM_USE_STRFUNC == 1
-#define FF_USE_STRFUNC 1 /* 1:Enable */
-#elif FILE_SYSTEM_USE_STRFUNC == 2
-#define FF_USE_STRFUNC 2 /* 2:Enable */
-#endif
-/* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf().
-/
-/ 0: Disable string functions.
-/ 1: Enable without LF-CRLF conversion.
-/ 2: Enable with LF-CRLF conversion. */
-
-
-#define FF_USE_FIND 0
-/* This option switches filtered directory read functions, f_findfirst() and
-/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
-
-#ifdef FILE_SYSTEM_USE_MKFS
-#define FF_USE_MKFS 1 /* 1:Enable */
-#else
-#define FF_USE_MKFS 0 /* 0:Disable */
-#endif
-/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
-
-
-#define FF_USE_FASTSEEK 0
-/* This option switches fast seek function. (0:Disable or 1:Enable) */
-
-
-#define FF_USE_EXPAND 0
-/* This option switches f_expand function. (0:Disable or 1:Enable) */
-
-
-#ifdef FILE_SYSTEM_USE_CHMOD
-#define FF_USE_CHMOD 1 /* 1:Enable */
-#else
-#define FF_USE_CHMOD 0 /* 0:Disable */
-#endif
-/* This option switches attribute manipulation functions, f_chmod() and f_utime().
-/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */
-
-
-#define FF_USE_LABEL 0
-/* This option switches volume label functions, f_getlabel() and f_setlabel().
-/ (0:Disable or 1:Enable) */
-
-
-#define FF_USE_FORWARD 0
-/* This option switches f_forward() function. (0:Disable or 1:Enable) */
-
-
-/*---------------------------------------------------------------------------/
-/ Locale and Namespace Configurations
-/---------------------------------------------------------------------------*/
-
-#define FF_CODE_PAGE 932
-/* This option specifies the OEM code page to be used on the target system.
-/ Incorrect code page setting can cause a file open failure.
-/
-/ 437 - U.S.
-/ 720 - Arabic
-/ 737 - Greek
-/ 771 - KBL
-/ 775 - Baltic
-/ 850 - Latin 1
-/ 852 - Latin 2
-/ 855 - Cyrillic
-/ 857 - Turkish
-/ 860 - Portuguese
-/ 861 - Icelandic
-/ 862 - Hebrew
-/ 863 - Canadian French
-/ 864 - Arabic
-/ 865 - Nordic
-/ 866 - Russian
-/ 869 - Greek 2
-/ 932 - Japanese (DBCS)
-/ 936 - Simplified Chinese (DBCS)
-/ 949 - Korean (DBCS)
-/ 950 - Traditional Chinese (DBCS)
-/ 0 - Include all code pages above and configured by f_setcp()
-*/
-
-
-#ifdef FILE_SYSTEM_USE_LFN
-#define FF_USE_LFN FILE_SYSTEM_USE_LFN /* 0 to 3 */
-#else
-#define FF_USE_LFN 0 /* 0 to 3 */
-#endif
-#define FF_MAX_LFN 255
-/* The FF_USE_LFN switches the support for LFN (long file name).
-/
-/ 0: Disable LFN. FF_MAX_LFN has no effect.
-/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
-/ 2: Enable LFN with dynamic working buffer on the STACK.
-/ 3: Enable LFN with dynamic working buffer on the HEAP.
-/
-/ To enable the LFN, ffunicode.c needs to be added to the project. The LFN function
-/ requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and
-/ additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled.
-/ The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can
-/ be in range of 12 to 255. It is recommended to be set 255 to fully support LFN
-/ specification.
-/ When use stack for the working buffer, take care on stack overflow. When use heap
-/ memory for the working buffer, memory management functions, ff_memalloc() and
-/ ff_memfree() in ffsystem.c, need to be added to the project. */
-
-
-#define FF_LFN_UNICODE 0
-/* This option switches the character encoding on the API when LFN is enabled.
-/
-/ 0: ANSI/OEM in current CP (TCHAR = char)
-/ 1: Unicode in UTF-16 (TCHAR = WCHAR)
-/ 2: Unicode in UTF-8 (TCHAR = char)
-/ 3: Unicode in UTF-32 (TCHAR = DWORD)
-/
-/ Also behavior of string I/O functions will be affected by this option.
-/ When LFN is not enabled, this option has no effect. */
-
-
-#define FF_LFN_BUF 255
-#define FF_SFN_BUF 12
-/* This set of options defines size of file name members in the FILINFO structure
-/ which is used to read out directory items. These values should be suffcient for
-/ the file names to read. The maximum possible length of the read file name depends
-/ on character encoding. When LFN is not enabled, these options have no effect. */
-
-
-#define FF_STRF_ENCODE 3
-/* When FF_LFN_UNICODE >= 1 with LFN enabled, string I/O functions, f_gets(),
-/ f_putc(), f_puts and f_printf() convert the character encoding in it.
-/ This option selects assumption of character encoding ON THE FILE to be
-/ read/written via those functions.
-/
-/ 0: ANSI/OEM in current CP
-/ 1: Unicode in UTF-16LE
-/ 2: Unicode in UTF-16BE
-/ 3: Unicode in UTF-8
-*/
-
-
-#if FILE_SYSTEM_SET_FS_RPATH == 0
-#define FF_FS_RPATH 0U
-#elif FILE_SYSTEM_SET_FS_RPATH == 1
-#define FF_FS_RPATH 1U
-#elif FILE_SYSTEM_SET_FS_RPATH == 2
-#define FF_FS_RPATH 2U
-#endif
-/* This option configures support for relative path.
-/
-/ 0: Disable relative path and remove related functions.
-/ 1: Enable relative path. f_chdir() and f_chdrive() are available.
-/ 2: f_getcwd() function is available in addition to 1.
-*/
-
-
-/*---------------------------------------------------------------------------/
-/ Drive/Volume Configurations
-/---------------------------------------------------------------------------*/
-
-#if FILE_SYSTEM_NUM_LOGIC_VOL == 1
-#define FF_VOLUMES 1U
-#elif FILE_SYSTEM_NUM_LOGIC_VOL == 2
-#define FF_VOLUMES 2U
-#elif FILE_SYSTEM_NUM_LOGIC_VOL == 3
-#define FF_VOLUMES 3U
-#elif FILE_SYSTEM_NUM_LOGIC_VOL == 4
-#define FF_VOLUMES 4U
-#elif FILE_SYSTEM_NUM_LOGIC_VOL == 5
-#define FF_VOLUMES 5U
-#elif FILE_SYSTEM_NUM_LOGIC_VOL == 6
-#define FF_VOLUMES 6U
-#elif FILE_SYSTEM_NUM_LOGIC_VOL == 7
-#define FF_VOLUMES 7U
-#elif FILE_SYSTEM_NUM_LOGIC_VOL == 8
-#define FF_VOLUMES 8U
-#elif FILE_SYSTEM_NUM_LOGIC_VOL == 9
-#define FF_VOLUMES 9U
-#else
-#define FF_VOLUMES 10U
-#endif
-/* Number of volumes (logical drives) to be used. (1-10) */
-
-
-#define FF_STR_VOLUME_ID 0
-#define FF_VOLUME_STRS "RAM","NAND","CF","SD","SD2","USB","USB2","USB3"
-/* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings.
-/ When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive
-/ number in the path name. FF_VOLUME_STRS defines the volume ID strings for each
-/ logical drives. Number of items must not be less than FF_VOLUMES. Valid
-/ characters for the volume ID strings are A-Z, a-z and 0-9, however, they are
-/ compared in case-insensitive. If FF_STR_VOLUME_ID >= 1 and FF_VOLUME_STRS is
-/ not defined, a user defined volume string table needs to be defined as:
-/
-/ const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb",...
-*/
-
-
-#ifdef FILE_SYSTEM_MULTI_PARTITION
-#define FF_MULTI_PARTITION 1 /* 1:Enable multiple partition */
-#else
-#define FF_MULTI_PARTITION 0 /* 0:Single partition */
-#endif
-/* This option switches support for multiple volumes on the physical drive.
-/ By default (0), each logical drive number is bound to the same physical drive
-/ number and only an FAT volume found on the physical drive will be mounted.
-/ When this function is enabled (1), each logical drive number can be bound to
-/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
-/ function will be available. */
-
-
-#define FF_MIN_SS 512
-#define FF_MAX_SS 512
-/* This set of options configures the range of sector size to be supported. (512,
-/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and
-/ harddisk. But a larger value may be required for on-board flash memory and some
-/ type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured
-/ for variable sector size mode and disk_ioctl() function needs to implement
-/ GET_SECTOR_SIZE command. */
-
-
-#define FF_USE_TRIM 0
-/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable)
-/ To enable Trim function, also CTRL_TRIM command should be implemented to the
-/ disk_ioctl() function. */
-
-
-#define FF_FS_NOFSINFO 0
-/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
-/ option, and f_getfree() function at first time after volume mount will force
-/ a full FAT scan. Bit 1 controls the use of last allocated cluster number.
-/
-/ bit0=0: Use free cluster count in the FSINFO if available.
-/ bit0=1: Do not trust free cluster count in the FSINFO.
-/ bit1=0: Use last allocated cluster number in the FSINFO if available.
-/ bit1=1: Do not trust last allocated cluster number in the FSINFO.
-*/
-
-
-
-/*---------------------------------------------------------------------------/
-/ System Configurations
-/---------------------------------------------------------------------------*/
-
-#define FF_FS_TINY 0
-/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
-/ At the tiny configuration, size of file object (FIL) is shrunk FF_MAX_SS bytes.
-/ Instead of private sector buffer eliminated from the file object, common sector
-/ buffer in the filesystem object (FATFS) is used for the file data transfer. */
-
-
-#ifdef FILE_SYSTEM_FS_EXFAT
-#define FF_FS_EXFAT 1
-#else
-#define FF_FS_EXFAT 0
-#endif
-/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable)
-/ To enable exFAT, also LFN needs to be enabled.
-/ Note that enabling exFAT discards ANSI C (C89) compatibility. */
-
-
-#define FF_FS_NORTC 0
-#define FF_NORTC_MON 1
-#define FF_NORTC_MDAY 1
-#define FF_NORTC_YEAR 2018
-/* The option FF_FS_NORTC switches timestamp functiton. If the system does not have
-/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable
-/ the timestamp function. Every object modified by FatFs will have a fixed timestamp
-/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time.
-/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be
-/ added to the project to read current time form real-time clock. FF_NORTC_MON,
-/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect.
-/ These options have no effect at read-only configuration (FF_FS_READONLY = 1). */
-
-
-#define FF_FS_LOCK 0
-/* The option FF_FS_LOCK switches file lock function to control duplicated file open
-/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY
-/ is 1.
-/
-/ 0: Disable file lock function. To avoid volume corruption, application program
-/ should avoid illegal open, remove and rename to the open objects.
-/ >0: Enable file lock function. The value defines how many files/sub-directories
-/ can be opened simultaneously under file lock control. Note that the file
-/ lock control is independent of re-entrancy. */
-
-
-#define FF_FS_REENTRANT 0
-#define FF_FS_TIMEOUT 1000
-#define FF_SYNC_t HANDLE
-/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
-/ module itself. Note that regardless of this option, file access to different
-/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
-/ and f_fdisk() function, are always not re-entrant. Only file/directory access
-/ to the same volume is under control of this function.
-/
-/ 0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect.
-/ 1: Enable re-entrancy. Also user provided synchronization handlers,
-/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
-/ function, must be added to the project. Samples are available in
-/ option/syscall.c.
-/
-/ The FF_FS_TIMEOUT defines timeout period in unit of time tick.
-/ The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
-/ SemaphoreHandle_t and etc. A header file for O/S definitions needs to be
-/ included somewhere in the scope of ff.h. */
-
-/* #include // O/S definitions */
-
-#ifdef FILE_SYSTEM_WORD_ACCESS
-#define FF_WORD_ACCESS 1
-#else
-#define FF_WORD_ACCESS 0
-#endif
-/* The FF_WORD_ACCESS option is an only platform dependent option. It defines
-/ which access method is used to the word data on the FAT volume.
-/
-/ 0: Byte-by-byte access. Always compatible with all platforms.
-/ 1: Word access. Do not choose this unless under both the following conditions.
-/
-/ * Address misaligned memory access is always allowed for ALL instructions.
-/ * Byte order on the memory is little-endian.
-/
-/ If it is the case, FF_WORD_ACCESS can also be set to 1 to improve performance and
-/ reduce code size. Following table shows an example of some processor types.
-/
-/ ARM7TDMI 0 ColdFire 0 V850E 0
-/ Cortex-M3 0 Z80 0/1 V850ES 0/1
-/ Cortex-M0 0 RX600(LE) 0/1 TLCS-870 0/1
-/ AVR 0/1 RX600(BE) 0 TLCS-900 0/1
-/ AVR32 0 RL78 0 R32C 0
-/ PIC18 0/1 SH-2 0 M16C 0/1
-/ PIC24 0 H8S 0 MSP430 0
-/ PIC32 0 H8/300H 0 x86 0/1
-*/
-
-#ifdef __cplusplus
-}
-#endif
-
-/*--- End of configuration options ---*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/88/601496525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/88/601496525243001d18b399c1eb9b3628
deleted file mode 100644
index 1b7d881..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/88/601496525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,369 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xdevcfg_hw.h
-* @addtogroup devcfg_v3_7
-* @{
-*
-* This file contains the hardware interface to the Device Config Interface.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.01a nm 08/01/12 Added defines for the PS Version bits,
-* removed the FIFO Flush bits from the
-* Miscellaneous Control Reg
-* 2.03a nm 04/19/13 Fixed CR# 703728.
-* Updated the register definitions as per the latest TRM
-* version UG585 (v1.4) November 16, 2012.
-* 2.04a kpc 10/07/13 Added function prototype.
-* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 11/03/09 Initial release.
-* 4.2 pkp 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
-* as smc.c is removed
-*
-*
-* @note None.
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef SMC_H /* prevent circular inclusions */
-#define SMC_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xparameters.h"
-#include "xil_io.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/* Memory controller configuration register offset */
-#define XSMCPSS_MC_STATUS 0x000U /* Controller status reg, RO */
-#define XSMCPSS_MC_INTERFACE_CONFIG 0x004U /* Interface config reg, RO */
-#define XSMCPSS_MC_SET_CONFIG 0x008U /* Set configuration reg, WO */
-#define XSMCPSS_MC_CLR_CONFIG 0x00CU /* Clear config reg, WO */
-#define XSMCPSS_MC_DIRECT_CMD 0x010U /* Direct command reg, WO */
-#define XSMCPSS_MC_SET_CYCLES 0x014U /* Set cycles register, WO */
-#define XSMCPSS_MC_SET_OPMODE 0x018U /* Set opmode register, WO */
-#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020U /* Refresh period_0 reg, RW */
-#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024U /* Refresh period_1 reg, RW */
-
-/* Chip select configuration register offset */
-#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100U /* Interface 0 chip 0 config */
-#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120U /* Interface 0 chip 1 config */
-#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140U /* Interface 0 chip 2 config */
-#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160U /* Interface 0 chip 3 config */
-#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180U /* Interface 1 chip 0 config */
-#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0U /* Interface 1 chip 1 config */
-#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0U /* Interface 1 chip 2 config */
-#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0U /* Interface 1 chip 3 config */
-
-/* User configuration register offset */
-#define XSMCPSS_UC_STATUS_OFFSET 0x200U /* User status reg, RO */
-#define XSMCPSS_UC_CONFIG_OFFSET 0x204U /* User config reg, WO */
-
-/* Integration test register offset */
-#define XSMCPSS_IT_OFFSET 0xE00U
-
-/* ID configuration register offset */
-#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0U
-#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4U
-#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8U
-#define XSMCPSS_ID_PERIP_3_OFFSET 0xFECU
-#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0U
-#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4U
-#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8U
-#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFCU
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* SMC_H */
-
-/**
- *@endcond
- */
\ No newline at end of file
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/89/c073b0555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/89/c073b0555243001d18b399c1eb9b3628
deleted file mode 100644
index 68408ea..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/89/c073b0555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,28 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/*
- *
- * This is a template implementation of the "__open" function used by
- * the standard library. Replace it with a system-specific
- * implementation.
- *
- * The "__open" function opens the file named "filename" as specified
- * by "mode".
- * open -- open a file descriptor. We don't have a filesystem, so
- * we return an error.
- *
- */
-
-#include
-#include "xil_types.h"
-
-sint32 __open(const char8 * filename, sint32 mode);
-
-sint32 __open(const char8 * filename, sint32 mode)
-{
-return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/89/c0bdeb575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/89/c0bdeb575243001d18b399c1eb9b3628
deleted file mode 100644
index 33b33eb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/89/c0bdeb575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,167 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xgpio_l.h
-* @addtogroup gpio_v4_8
-* @{
-*
-* This header file contains identifiers and driver functions (or
-* macros) that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-*
-* The macros that are available in this file use a multiply to calculate the
-* addresses of registers. The user can control whether that multiply is done
-* at run time or at compile time. A constant passed as the channel parameter
-* will cause the multiply to be done at compile time. A variable passed as the
-* channel parameter will cause it to occur at run time.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a jhl 04/24/02 First release of low level driver
-* 2.00a jhl 11/26/03 Added support for dual channels and interrupts. This
-* change required the functions to be changed such that
-* the interface is not compatible with previous versions.
-* See the examples in the example directory for macros
-* to help compile an application that was designed for
-* previous versions of the driver. The interrupt registers
-* are accessible using the ReadReg and WriteReg macros and
-* a channel parameter was added to the other macros.
-* 2.11a mta 03/21/07 Updated to new coding style
-* 2.12a sv 11/21/07 Updated driver to support access through DCR bus.
-* 3.00a sv 11/21/09 Renamed the macros XGpio_mWriteReg to XGpio_WriteReg
-* XGpio_mReadReg to XGpio_ReadReg.
-* Removed the macros XGpio_mSetDataDirection,
-* XGpio_mGetDataReg and XGpio_mSetDataReg. Users
-* should use XGpio_WriteReg/XGpio_ReadReg to achieve the
-* same functionality.
-* 4.1 lks 11/18/15 Removed support for DCR bridge
-*
-*
-******************************************************************************/
-
-#ifndef XGPIO_L_H /* prevent circular inclusions */
-#define XGPIO_L_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-
-/************************** Constant Definitions *****************************/
-
-/** @name Registers
- *
- * Register offsets for this device.
- * @{
- */
-#define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */
-#define XGPIO_TRI_OFFSET 0x4 /**< I/O direction reg for 1st channel */
-#define XGPIO_DATA2_OFFSET 0x8 /**< Data register for 2nd channel */
-#define XGPIO_TRI2_OFFSET 0xC /**< I/O direction reg for 2nd channel */
-
-#define XGPIO_GIE_OFFSET 0x11C /**< Glogal interrupt enable register */
-#define XGPIO_ISR_OFFSET 0x120 /**< Interrupt status register */
-#define XGPIO_IER_OFFSET 0x128 /**< Interrupt enable register */
-
-/** @} */
-
-/* The following constant describes the offset of each channels data and
- * tristate register from the base address.
- */
-#define XGPIO_CHAN_OFFSET 8 /**< Channel offeset */
-
-/** @name Interrupt Status and Enable Register bitmaps and masks
- *
- * Bit definitions for the interrupt status register and interrupt enable
- * registers.
- * @{
- */
-#define XGPIO_IR_MASK 0x3 /**< Mask of all bits */
-#define XGPIO_IR_CH1_MASK 0x1 /**< Mask for the 1st channel */
-#define XGPIO_IR_CH2_MASK 0x2 /**< Mask for the 2nd channel */
-/** @}*/
-
-
-/** @name Global Interrupt Enable Register bitmaps and masks
- *
- * Bit definitions for the Global Interrupt Enable register
- * @{
- */
-#define XGPIO_GIE_GINTR_ENABLE_MASK 0x80000000 /**< Mask for Global Interrupt */
-/** @}*/
-
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XGpio_In32 Xil_In32 /**< Input Operations */
-#define XGpio_Out32 Xil_Out32 /**< Output Operations */
-
-
-/****************************************************************************/
-/**
-*
-* Write a value to a GPIO register. A 32 bit write is performed. If the
-* GPIO core is implemented in a smaller width, only the least significant data
-* is written.
-*
-* @param BaseAddress is the base address of the GPIO device.
-* @param RegOffset is the register offset from the base to write to.
-* @param Data is the data written to the register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XGpio_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
-****************************************************************************/
-#define XGpio_WriteReg(BaseAddress, RegOffset, Data) \
- XGpio_Out32((BaseAddress) + (RegOffset), (u32)(Data))
-
-/****************************************************************************/
-/**
-*
-* Read a value from a GPIO register. A 32 bit read is performed. If the
-* GPIO core is implemented in a smaller width, only the least
-* significant data is read from the register. The most significant data
-* will be read as 0.
-*
-* @param BaseAddress is the base address of the GPIO device.
-* @param RegOffset is the register offset from the base to read from.
-*
-* @return Data read from the register.
-*
-* @note C-style signature:
-* u32 XGpio_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-****************************************************************************/
-#define XGpio_ReadReg(BaseAddress, RegOffset) \
- XGpio_In32((BaseAddress) + (RegOffset))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8a/2116ab585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8a/2116ab585243001d18b399c1eb9b3628
deleted file mode 100644
index 4c55bbd..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8a/2116ab585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,18 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include "xil_types.h"
-
-/* _exit - Simple implementation. Does not return.
-*/
-__attribute__((weak)) void _exit (sint32 status)
-{
- (void)status;
- while (1) {
- ;
- }
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8a/50c730565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8a/50c730565243001d18b399c1eb9b3628
deleted file mode 100644
index fc90230..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8a/50c730565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,470 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpm_counter.c
-*
-* This file contains APIs for configuring and controlling the Cortex-R5
-* Performance Monitor Events. For more information about the event counters,
-* see xpm_counter.h.
-* The file contains APIs to setup an event, return the event counter value,
-* disable event(s), enable events, reset event counters.
-* It also provides a helper function: Xpm_SleepPerfCounter that is used to
-* implement sleep routines in non-OS environment.
-* It also contains two APIs which are being deprecated. Users are advised
-* not to use them.
-* On usage of these APIs, please refer to xpm_conter_example.c file which can
-* be found at standalone example folder.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.00 pkp 02/10/14 Initial version
-* 6.2 mus 01/27/17 Updated to support IAR compiler
-* 7.1 aru 04/15/19 Updated the events correctly
-* 7.2 mus 01/29/20 Added helper function Xpm_SleepPerfCounter for sleep
-* routines. It would be consumed by sleep routines for
-* delay generation through CortexR5 PMU cycle counter,if
-* TTC2 as well as TTC3 is not present in HW design. User
-* can add compiler flag "DONT_USE_PMU_FOR_SLEEP_ROUTINES"
-* in BSP compiler flags to avoid using PMU cycle counter
-* for sleep routines.
-* 7.2 asa 03/18/20 Add implementation for new APIs that simplifies the
-* existing event handling mechanism.
-* Older APIs are being deprecated.
-* 7.6 mus 09/16/21 PmcrEventCfg32 is declared with deprecate attribute and
-* being used in one of the deprecated function,
-* that is always resulting into complialation
-* warning. Removed deprecate attribute from PmcrEventCfg32
-* to fix un-necessary warning CR#1110990.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xpm_counter.h"
-#include "xil_sleeptimer.h"
-#include "xtime_l.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-typedef const u32 PmcrEventCfg32[XPM_CTRCOUNT];
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions *****************************/
-
-
-/******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @brief This function disables the Cortex R5 event counters.
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_DisableEventCounters(void)
-{
- u32 RegVal;
- /* Disable the event counters */
-#ifdef __GNUC__
- RegVal = mfcp(XREG_CP15_COUNT_ENABLE_CLR);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_COUNT_ENABLE_CLR, RegVal);
-#else
- { register u32 C15Reg __asm(XREG_CP15_COUNT_ENABLE_CLR);
- RegVal = C15Reg; }
-#endif
- RegVal |= XPM_EVENT_CNTRS_MASK;
- mtcp(XREG_CP15_COUNT_ENABLE_CLR, RegVal);
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function enables the Cortex R5 event counters.
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_EnableEventCounters(void)
-{
- u32 RegVal;
- /* Enable the event counters */
-#ifdef __GNUC__
- RegVal = mfcp(XREG_CP15_COUNT_ENABLE_SET);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_COUNT_ENABLE_SET, RegVal);
-#else
- { register u32 C15Reg __asm(XREG_CP15_COUNT_ENABLE_SET);
- RegVal = C15Reg; }
-#endif
- RegVal |= XPM_EVENT_CNTRS_MASK;
- mtcp(XREG_CP15_COUNT_ENABLE_SET, RegVal);
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function resets the Cortex R5 event counters.
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_ResetEventCounters(void)
-{
- u32 Reg;
-
-#ifdef __GNUC__
- Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
-#else
- { register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL);
- Reg = C15Reg; }
-#endif
- Reg |= (1U << 2U); /* reset event counters */
- mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
-}
-
-/*****************************************************************************/
-/**
- *
- * Disables the requested event counter.
- *
- *
- * @param EventCntrId: Event Counter ID. The counter ID is the same that
- * was earlier returned through a call to Xpm_SetUpAnEvent.
- * Cortex-R5 supports only 3 counters. The valid values are 0, 1,
- * or 2.
- *
- * @return
- * - XST_SUCCESS if successful.
- * - XST_FAILURE if the passed Counter ID is invalid
- * (i.e. greater than 2).
- *
- ******************************************************************************/
-u32 Xpm_DisableEvent(u32 EventCntrId)
-{
- u32 Counters;
- u32 CntrMask = 0x1U;
-
- if (EventCntrId > XPM_MAX_EVENTHANDLER_ID) {
- xil_printf("Invalid EventHandlerID\r\n");
- return XST_FAILURE;
- } else {
- CntrMask = CntrMask << EventCntrId;
-#ifdef __GNUC__
- Counters = mfcp(XREG_CP15_COUNT_ENABLE_CLR);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_COUNT_ENABLE_CLR, Counters);
-#else
- { register u32 C15Reg __asm(XREG_CP15_COUNT_ENABLE_CLR);
- Counters = C15Reg; }
-#endif
- Counters &= ~CntrMask;
- mtcp(XREG_CP15_COUNT_ENABLE_CLR, Counters);
- return XST_SUCCESS;
- }
-}
-
-/*****************************************************************************/
-/**
- *
- * Sets up one of the event counters to count events based on the Event ID
- * passed. For supported Event IDs please refer xpm_counter.h.
- * Upon invoked, the API searches for an available counter. After finding
- * one, it sets up the counter to count events for the requested event.
- *
- *
- * @param EventID: For valid values, please refer xpm_counter.h.
- *
- * @return
- * - Counter Number if successful. For Cortex-R5, valid return values are
- * 0, 1, or 2.
- * - XPM_NO_COUNTERS_AVAILABLE (0xFF) if all counters are being used
- *
- ******************************************************************************/
-u32 Xpm_SetUpAnEvent(u32 EventID)
-{
- u32 Counters;
- u32 OriginalCounters;
- u32 Index;
-
-#ifdef __GNUC__
- OriginalCounters = mfcp(XREG_CP15_COUNT_ENABLE_SET);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_COUNT_ENABLE_SET, OriginalCounters);
-#else
- { register u32 C15Reg __asm(XREG_CP15_COUNT_ENABLE_SET);
- OriginalCounters = C15Reg; }
-#endif
- OriginalCounters &= XPM_EVENT_CNTRS_BIT_MASK;
- Counters = OriginalCounters;
- if (Counters == XPM_ALL_EVENT_CNTRS_IN_USE) {
- xil_printf("No counters available\r\n");
- return XPM_NO_COUNTERS_AVAILABLE;
- } else {
- for(Index = 0U; Index < XPM_CTRCOUNT; Index++) {
- if ((Counters & 0x1U) == 0x0) {
- break;
- } else {
- Counters = Counters >> 0x1U;
- continue;
- }
- }
- }
-
- /* Select event counter */
- mtcp(XREG_CP15_EVENT_CNTR_SEL, Index);
- /* Set the event */
- mtcp(XREG_CP15_EVENT_TYPE_SEL, EventID);
- /* Enable event counter */
- mtcp(XREG_CP15_COUNT_ENABLE_SET, OriginalCounters | (1U << Index));
- return Index;
-}
-
-/*****************************************************************************/
-/**
- *
- * Reads the counter value for the requested counter ID. This is used to read
- * the number of events that has been counted for the requsted event ID.
- * This can only be called after a call to Xpm_SetUpAnEvent.
- *
- *
- * @param EventCntrId: The counter ID is the same that was earlier
- * returned through a call to Xpm_SetUpAnEvent.
- * Cortex-R5 supports only 3 counters. The valid values are 0, 1,
- * or 2.
- * @param CntVal: Pointer to a 32 bit unsigned int type. This is used to return
- * the event counter value.
- *
- * @return
- * - XST_SUCCESS if successful.
- * - XST_FAILURE if the passed Counter ID is invalid
- * (i.e. greater than 2).
- *
- ******************************************************************************/
-u32 Xpm_GetEventCounter(u32 EventCntrId, u32 *CntVal)
-{
- if (EventCntrId > XPM_MAX_EVENTHANDLER_ID) {
- xil_printf("Invalid Event Handler ID\r\n");
- return XST_FAILURE;
- } else {
- mtcp(XREG_CP15_EVENT_CNTR_SEL, EventCntrId);
-#ifdef __GNUC__
- *CntVal = mfcp(XREG_CP15_PERF_MONITOR_COUNT);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_PERF_MONITOR_COUNT, (*CntVal));
-#else
- { register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT);
- *CntVal = C15Reg; }
-#endif
- return XST_SUCCESS;
- }
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This is helper function used by sleep/usleep APIs to generate
-* delay in sec/usec
-*
-* @param delay - delay time in sec/usec
-* @param frequency - Number of countes in second/micro second
-*
-* @return None.
-*
-*****************************************************************************/
-
-void Xpm_SleepPerfCounter(u32 delay, u64 frequency)
-{
- u64 tEnd = 0U;
- u64 tCur = 0U;
- XCntrVal TimeHighVal = 0U;
- XCntrVal TimeLowVal1 = 0U;
- XCntrVal TimeLowVal2 = 0U;
-
-#if defined (__GNUC__)
- TimeLowVal1 = Xpm_ReadCycleCounterVal();
-#elif defined (__ICCARM__)
- Xpm_ReadCycleCounterVal(TimeLowVal1);
-#endif
- tEnd = (u64)TimeLowVal1 + ((u64)(delay) * frequency);
- do {
-#if defined (__GNUC__)
- TimeLowVal2 = Xpm_ReadCycleCounterVal();
-#elif defined (__ICCARM__)
- Xpm_ReadCycleCounterVal(TimeLowVal2);
-#endif
- if (TimeLowVal2 < TimeLowVal1) {
- TimeHighVal++;
- }
- TimeLowVal1 = TimeLowVal2;
- tCur = (((u64) TimeHighVal) << XSLEEP_TIMER_REG_SHIFT) |
- (u64)TimeLowVal2;
- }while (tCur < tEnd);
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function configures the Cortex R5 event counters controller,
-* with the event codes, in a configuration selected by the user and
-* enables the counters.
-*
-* @param PmcrCfg: Configuration value based on which the event counters
-* are configured.XPM_CNTRCFG* values defined in xpm_counter.h can
-* be utilized for setting configuration
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_SetEvents(s32 PmcrCfg)
-{
- u32 Counter;
- static PmcrEventCfg32 PmcrEvents[] = {
-
- {
- XPM_EVENT_SOFTINCR,
- XPM_EVENT_INSTRCACHEMISS,
- XPM_EVENT_DATACACHEMISS
- },
- {
- XPM_EVENT_DATACACHEACCESS,
- XPM_EVENT_DATAREAD,
- XPM_EVENT_DATAWRITE
- },
- {
- XPM_EVENT_INSTR,
- XPM_EVENT_DUALINSTR,
- XPM_EVENT_EXCEPTION
- },
- {
- XPM_EVENT_EXCEPTIONRET,
- XPM_EVENT_CHANGETOCONTEXID,
- XPM_EVENT_SWCHANGE
- },
- {
- XPM_EVENT_IMMEDIATEINSTR,
- XPM_EVENT_PROCEDURERET,
- XPM_EVENT_UNALIGNACCESS
- },
- {
- XPM_EVENT_BRANCHMISPREDICT,
- XPM_EVENT_CLOCKCYCLES,
- XPM_EVENT_BRANCHPREDICT
- },
- {
- XPM_EVENT_INSTRSTALL,
- XPM_EVENT_DATASTALL,
- XPM_EVENT_DATACACHEWRITE
- },
- {
- XPM_EVENT_EXTERNALMEMREQ,
- XPM_EVENT_LSUSTALL,
- XPM_EVENT_FORCEDRAINSTORE
- },
- {
- XPM_EVENT_INSTRTAGPARITY,
- XPM_EVENT_INSTRDATAPARITY,
- XPM_EVENT_DATATAGPARITY
- },
- {
- XPM_EVENT_DATADATAPARITY,
- XPM_EVENT_TCMERRORPREFETCH,
- XPM_EVENT_TCMERRORSTORE
- },
- {
- XPM_EVENT_INSTRCACHEACCESS,
- XPM_EVENT_DUALISSUEA,
- XPM_EVENT_DUALISSUEB
- },
- {
- XPM_EVENT_DUALISSUEOTHER,
- XPM_EVENT_FPA,
- XPM_EVENT_DATACACHEDATAERROR
- },
- {
- XPM_EVENT_DATACACHETAGERROR,
- XPM_EVENT_PROCESSORLIVELOCK,
- XPM_EVENT_ATCMMULTIBITERROR
- },
- {
- XPM_EVENT_B0TCMMULTIBITERROR,
- XPM_EVENT_B1TCMMULTIBITERROR,
- XPM_EVENT_ATCMSINGLEBITERROR
- },
- {
- XPM_EVENT_B0TCMSINGLEBITERROR,
- XPM_EVENT_B1TCMSINGLEBITERROR,
- XPM_EVENT_TCMERRORLSU
- },
- {
- XPM_EVENT_TCMERRORPFU,
- XPM_EVENT_TCMFATALERRORAXI,
- XPM_EVENT_TCMERRORAXI
- },
-
- };
- const u32 *ptr = PmcrEvents[PmcrCfg];
-
- Xpm_DisableEventCounters();
-
- for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
-
- /* Select event counter */
- mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
-
- /* Set the event */
- mtcp(XREG_CP15_EVENT_TYPE_SEL, ptr[Counter]);
- }
-
- Xpm_ResetEventCounters();
- Xpm_EnableEventCounters();
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function disables the event counters and returns the counter
-* values.
-*
-* @param PmCtrValue: Pointer to an array of type u32 PmCtrValue[6].
-* It is an output parameter which is used to return the PM
-* counter values.
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_GetEventCounters(u32 *PmCtrValue)
-{
- u32 Counter;
-
- Xpm_DisableEventCounters();
-
- for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
-
- mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
-#ifdef __GNUC__
- PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_PERF_MONITOR_COUNT, PmCtrValue[Counter]);
-#else
- { register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT);
- PmCtrValue[Counter] = Cp15Reg; }
-#endif
- }
-}
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8a/9012ee585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8a/9012ee585243001d18b399c1eb9b3628
deleted file mode 100644
index 26966bf..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8a/9012ee585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,81 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file usleep.c
-*
-* This function provides a microsecond delay using the Global Timer register in
-* the ARM Cortex A9 MP core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm 11/11/09 First release
-* 3.07a sgd 07/05/12 Updated micro sleep function to make use Global Timer
-* 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine as it is not
-* possible to generate timer in nanosecond due to
-* limited cpu frequency
-* 6.0 asa 08/15/16 Updated the usleep signature. Fix for CR#956899.
-* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
-* implementation. Now sleep routines will use Timer
-* specified by the user (i.e. Global timer/TTC timer)
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "sleep.h"
-#include "xtime_l.h"
-#include "xparameters.h"
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#include "xreg_cortexa9.h"
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#include "xil_sleeptimer.h"
-#endif
-
-/**************************** Constant Definitions ************************/
-#if defined (SLEEP_TIMER_BASEADDR)
-#define COUNTS_PER_USECOND (SLEEP_TIMER_FREQUENCY / 1000000)
-#else
-/* Global Timer is always clocked at half of the CPU frequency */
-#define COUNTS_PER_USECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / (2U*1000000U))
-#endif
-
-/*****************************************************************************/
-/**
-*
-* This API gives a delay in microseconds
-*
-* @param useconds requested
-*
-* @return 0 if the delay can be achieved, -1 if the requested delay
-* is out of range
-*
-* @note None.
-*
-****************************************************************************/
-int usleep_A9(unsigned long useconds)
-{
-#if defined (SLEEP_TIMER_BASEADDR)
- Xil_SleepTTCCommon(useconds, COUNTS_PER_USECOND);
-#else
- XTime tEnd, tCur;
-
- XTime_GetTime(&tCur);
- tEnd = tCur + (((XTime) useconds) * COUNTS_PER_USECOND);
- do
- {
- XTime_GetTime(&tCur);
- } while (tCur < tEnd);
-#endif
-
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8b/71c6ed515243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8b/71c6ed515243001d18b399c1eb9b3628
deleted file mode 100644
index 0fe3466..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8b/71c6ed515243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,9 +0,0 @@
-TRACE::2022-05-14.00:19:40::SCWBifWriter::Found the complete platform /home/dylan/workspace/phased_array_platform/export/phased_array_platform/phased_array_platform.xpfm
-TRACE::2022-05-14.00:19:40::SCWBifWriter::hardware databse : design_1_wrapper_21
-TRACE::2022-05-14.00:19:40::SCWBifWriter::bitstream found in the design
-TRACE::2022-05-14.00:19:40::SCWBifWriter::Found a baremetal domain, proc: ps7_cortexa9_0
-TRACE::2022-05-14.00:19:40::SCWBifWriter::proc type :
-TRACE::2022-05-14.00:19:40::SCWBifWriter::proc[0] : ps7_cortexa9_0
-TRACE::2022-05-14.00:19:40::SCWBifWriter::Device type is : zynq
-TRACE::2022-05-14.00:19:40::SCWBifWriter::Writing BIF to file : /home/dylan/workspace/phased_array_system/_ide/bootimage/template_phased_array_system.bif
-TRACE::2022-05-14.00:19:40::SCWBifWriter::Writing the Zynq Baremetal bif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8b/802773565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8b/802773565243001d18b399c1eb9b3628
deleted file mode 100644
index 48dcec3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8b/802773565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,53 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file cpu_init.S
-*
-* This file contains CPU specific initialization. Invoked from main CRT
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 1.00a ecm/sdm 10/20/09 Initial version
-* 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
-* 5.0 pkp 12/16/14 removed incorrect initialization of TLB lockdown
-* register to fix CR#830580
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
- .text
- .global __cpu_init
- .align 2
-__cpu_init:
-
-/* Clear cp15 regs with unknown reset values */
- mov r0, #0x0
- mcr p15, 0, r0, c5, c0, 0 /* DFSR */
- mcr p15, 0, r0, c5, c0, 1 /* IFSR */
- mcr p15, 0, r0, c6, c0, 0 /* DFAR */
- mcr p15, 0, r0, c6, c0, 2 /* IFAR */
- mcr p15, 0, r0, c9, c13, 2 /* PMXEVCNTR */
- mcr p15, 0, r0, c13, c0, 2 /* TPIDRURW */
- mcr p15, 0, r0, c13, c0, 3 /* TPIDRURO */
-
-/* Reset and start Cycle Counter */
- mov r2, #0x80000000 /* clear overflow */
- mcr p15, 0, r2, c9, c12, 3
- mov r2, #0xd /* D, C, E */
- mcr p15, 0, r2, c9, c12, 0
- mov r2, #0x80000000 /* enable cycle counter */
- mcr p15, 0, r2, c9, c12, 1
-
- bx lr
-
-.end
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8b/806962575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8b/806962575243001d18b399c1eb9b3628
deleted file mode 100644
index 6b51ea9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8b/806962575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,28 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-
-#ifndef _MBLAZE_NT_TYPES_H
-#define _MBLAZE_NT_TYPES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef char byte;
-typedef short half;
-typedef int word;
-typedef unsigned char ubyte;
-typedef unsigned short uhalf;
-typedef unsigned int uword;
-typedef ubyte boolean;
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8b/a031a2575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8b/a031a2575243001d18b399c1eb9b3628
deleted file mode 100644
index 8d11ff8..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8b/a031a2575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,365 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xscuwdt.h
-* @addtogroup scuwdt_v2_4
-* @{
-* @details
-*
-* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private
-* watchdog timer hardware.
-*
-* The XScuWdt driver supports the following features:
-* - Watchdog mode
-* - Timer mode
-* - Auto reload (timer mode only)
-*
-* The watchdog counter register is a down counter and starts decrementing when
-* the watchdog is started.
-* In watchdog mode, when the counter reaches 0, the Reset flag is set in the
-* Reset status register and the WDRESETREQ pin is asserted, causing a system
-* reset. The Reset flag is not reset by normal processor reset and is cleared
-* when written with a value of 1. This enables the user to differentiate a
-* normal reset and a reset caused by watchdog time-out. The user needs to call
-* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out.
-*
-* The IsWdtExpired function can be used to check if the watchdog was the cause
-* of the last reset. In this situation, call Initialize then call IsWdtExpired.
-* If the result is true, watchdog timeout caused the last system reset. The
-* application then needs to clear the Reset flag.
-*
-* In timer mode, when the counter reaches 0, the Event flag is set in the
-* Interrupt status register and if interrupts are enabled, interrupt ID 30 is
-* set as pending in the interrupt distributor. The IsTimerExpired function
-* is used to check if the watchdog counter has decremented to 0 in timer mode.
-* If auto-reload mode is enabled, the Counter register is automatically reloaded
-* from the Load register.
-*
-* Initialization and Configuration
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate with the Watchdog Timer.
-*
-* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The
-* user needs to first call the XScuWdt_LookupConfig() API which returns
-* the Configuration structure pointer which is passed as a parameter to
-* the XScuWdt_CfgInitialize() API.
-*
-* Interrupts
-*
-* The SCU Watchdog Timer supports interrupts in Timer mode.
-*
-* This driver does not provide a Interrupt Service Routine (ISR) for the device.
-* It is the responsibility of the application to provide one if needed. Refer to
-* the interrupt example provided with this driver for details on using the
-* Timer in interrupt mode.
-*
-* Virtual Memory
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-* Threads
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* Asserts
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* Building the driver
-*
-* The XScuWdt driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-*
-*
-* NOTE:
-* The watchdog timer is not a part of the snoop control unit as indicated
-* by the prefix "scu" in the name of the driver.
-* It is an independent module in APU.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 2.3 mus 08/31/20 Updated makefile to support parallel make and
-* incremental builds. It would help to reduce compilaton
-* time.
-* 2.3 sne 09/16/20 Fixed MISRA-C violations.
-* 2.4 sne 02/04/21 Fixed Doxygen warnings.
-*
-*
-******************************************************************************/
-#ifndef XSCUWDT_H /**< prevent circular inclusions */
-#define XSCUWDT_H /**< by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xscuwdt_hw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddr; /**< Base address of the device */
-} XScuWdt_Config;
-
-/**
- * The XScuWdt driver instance data. The user is required to allocate a
- * variable of this type for every watchdog/timer device in the system.
- * A pointer to a variable of this type is then passed to the driver API
- * functions.
- */
-typedef struct {
- XScuWdt_Config Config;/**< Hardware Configuration */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStarted; /**< Device watchdog timer is running */
-} XScuWdt;
-
-/************************** Variable Definitions *****************************/
-extern XScuWdt_Config XScuWdt_ConfigTable[];
-
-/***************** Macros (Inline Functions) Definitions *********************/
-/****************************************************************************/
-/**
-*
-* This function is used to check if the watchdog has timed-out and the last
-* reset was caused by the watchdog reset.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return
-* - TRUE if the watchdog has expired.
-* - FALSE if the watchdog has not expired.
-*
-* @note C-style signature:
-* int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_IsWdtExpired(InstancePtr) \
- ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_RST_STS_OFFSET) & \
- XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
-
-/****************************************************************************/
-/**
-*
-* This function is used to check if the watchdog counter has reached 0 in timer
-* mode.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return
-* - TRUE if the watchdog has expired.
-* - FALSE if the watchdog has not expired.
-*
-* @note C-style signature:
-* int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_IsTimerExpired(InstancePtr) \
- ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_ISR_OFFSET) & \
- XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
-
-/****************************************************************************/
-/**
-*
-* Re-start the watchdog timer. This macro will read the watchdog load register
-* and write the same value to load register to update the counter register.
-* An application needs to call this function periodically to keep the watchdog
-* from asserting the WDRESETREQ reset request output pin.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_RestartWdt(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_RestartWdt(InstancePtr) \
- XScuWdt_LoadWdt((InstancePtr), \
- (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_LOAD_OFFSET)))
-
-/****************************************************************************/
-/**
-*
-* Write to the watchdog timer load register. This will also update the
-* watchdog counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-* @param Value is the value to be written to the Watchdog Load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value)
-*
-******************************************************************************/
-#define XScuWdt_LoadWdt(InstancePtr, Value) \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_LOAD_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the
-* Watchdog control register.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_SetWdMode(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_SetWdMode(InstancePtr) \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET, \
- (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET) | \
- (XSCUWDT_CONTROL_WD_MODE_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321
-* successively to the Watchdog Disable Register.
-* The software must write 0x12345678 and 0x87654321 successively to the
-* Watchdog Disable Register so that the watchdog mode bit in the Watchdog
-* Control Register is set to zero.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_SetTimerMode(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_SetTimerMode(InstancePtr) \
-{ \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_DISABLE_OFFSET, \
- XSCUWDT_DISABLE_VALUE1); \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_DISABLE_OFFSET, \
- XSCUWDT_DISABLE_VALUE2); \
-}
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the watchdog control register.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return Contents of the watchdog control register.
-*
-* @note C-style signature:
- u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_GetControlReg(InstancePtr) \
- XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the watchdog control register.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-* @param ControlReg is the value to be written to the watchdog control
-* register.
-*
-* @return None.
-*
-* @note C-style signature:
- void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg)
-*
-******************************************************************************/
-#define XScuWdt_SetControlReg(InstancePtr, ControlReg) \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET, (ControlReg))
-
-/****************************************************************************/
-/**
-*
-* Enable auto-reload mode.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_EnableAutoReload(InstancePtr) \
- XScuWdt_SetControlReg((InstancePtr), \
- (XScuWdt_GetControlReg(InstancePtr) | \
- XSCUWDT_CONTROL_AUTO_RELOAD_MASK))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Lookup configuration in xscuwdt_sinit.c.
- */
-XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId);
-
-/*
- * Selftest function in xscuwdt_selftest.c
- */
-s32 XScuWdt_SelfTest(XScuWdt *InstancePtr);
-
-/*
- * Interface functions in xscuwdt.c
- */
-s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
- XScuWdt_Config *ConfigPtr, u32 EffectiveAddress);
-
-void XScuWdt_Start(XScuWdt *InstancePtr);
-
-void XScuWdt_Stop(XScuWdt *InstancePtr);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8b/c11337575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8b/c11337575243001d18b399c1eb9b3628
deleted file mode 100644
index c1014e5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8b/c11337575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,138 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/*****************************************************************************
-*
-* @file fsbl_hooks.c
-*
-* This file provides functions that serve as user hooks. The user can add the
-* additional functionality required into these routines. This would help retain
-* the normal FSBL flow unchanged.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 3.00a np 08/03/12 Initial release
-*
-*
-* @note
-*
-******************************************************************************/
-
-
-#include "fsbl.h"
-#include "xstatus.h"
-#include "fsbl_hooks.h"
-
-/************************** Variable Definitions *****************************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/******************************************************************************
-* This function is the hook which will be called before the bitstream download.
-* The user can add all the customized code required to be executed before the
-* bitstream download to this routine.
-*
-* @param None
-*
-* @return
-* - XST_SUCCESS to indicate success
-* - XST_FAILURE.to indicate failure
-*
-****************************************************************************/
-u32 FsblHookBeforeBitstreamDload(void)
-{
- u32 Status;
-
- Status = XST_SUCCESS;
-
- /*
- * User logic to be added here. Errors to be stored in the status variable
- * and returned
- */
- fsbl_printf(DEBUG_INFO,"In FsblHookBeforeBitstreamDload function \r\n");
-
- return (Status);
-}
-
-/******************************************************************************
-* This function is the hook which will be called after the bitstream download.
-* The user can add all the customized code required to be executed after the
-* bitstream download to this routine.
-*
-* @param None
-*
-* @return
-* - XST_SUCCESS to indicate success
-* - XST_FAILURE.to indicate failure
-*
-****************************************************************************/
-u32 FsblHookAfterBitstreamDload(void)
-{
- u32 Status;
-
- Status = XST_SUCCESS;
-
- /*
- * User logic to be added here.
- * Errors to be stored in the status variable and returned
- */
- fsbl_printf(DEBUG_INFO, "In FsblHookAfterBitstreamDload function \r\n");
-
- return (Status);
-}
-
-/******************************************************************************
-* This function is the hook which will be called before the FSBL does a handoff
-* to the application. The user can add all the customized code required to be
-* executed before the handoff to this routine.
-*
-* @param None
-*
-* @return
-* - XST_SUCCESS to indicate success
-* - XST_FAILURE.to indicate failure
-*
-****************************************************************************/
-u32 FsblHookBeforeHandoff(void)
-{
- u32 Status;
-
- Status = XST_SUCCESS;
-
- /*
- * User logic to be added here.
- * Errors to be stored in the status variable and returned
- */
- fsbl_printf(DEBUG_INFO,"In FsblHookBeforeHandoff function \r\n");
-
- return (Status);
-}
-
-
-/******************************************************************************
-* This function is the hook which will be called in case FSBL fall back
-*
-* @param None
-*
-* @return None
-*
-****************************************************************************/
-void FsblHookFallback(void)
-{
- /*
- * User logic to be added here.
- * Errors to be stored in the status variable and returned
- */
- fsbl_printf(DEBUG_INFO,"In FsblHookFallback function \r\n");
- while(1);
-}
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8b/f02e64525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8b/f02e64525243001d18b399c1eb9b3628
deleted file mode 100644
index 5b03910..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8b/f02e64525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,131 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010-2020
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, see
-*
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init_gpl.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 666666687
-#define DDR_FREQ 533333374
-#define DCI_FREQ 10158730
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 125000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 100000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 111111115
-#define WDT_FREQ 111111115
-#define TTC_FREQ 50000000
-#define CAN_FREQ 10000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 50000000
-#define FPGA1_FREQ 10000000
-#define FPGA2_FREQ 10000000
-#define FPGA3_FREQ 10000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8c/10dcce565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8c/10dcce565243001d18b399c1eb9b3628
deleted file mode 100644
index becf67e..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8c/10dcce565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,169 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file vectors.c
-*
-* This file contains the C level vectors for the ARM Cortex A9 core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 10/20/09 Initial version, moved over from bsp area
-* 6.0 mus 27/07/16 Consolidated vectors for a53,a9 and r5 processor
-* and added UndefinedException for a53 32 bit and r5
-* processor
-*
-;* The boot code performs minimum configuration which is required for an
-;* application to run starting from processor's reset state. Below is a
-;* sequence illustrating what all configuration is performed before control
-;* reaches to main function.
-;*
-;* 1. Program vector table base for exception handling
-;* 2. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine,
-;* abort, system)
-;* 3. Disable instruction cache, data cache and MPU
-;* 4. Invalidate instruction and data cache
-;* 5. Configure MPU with short descriptor translation table format and program
-;* base address of translation table
-;* 6. Enable data cache, instruction cache and MPU
-;* 7. Enable Floating point unit
-;* 8. Transfer control to _start which clears BSS sections and jumping to main
-;* application
-;*
-;*
-;*
-;* MODIFICATION HISTORY:
-;*
-;* Ver Who Date Changes
-;* ----- ---- -------- ---------------------------------------------------
-;* 7.3 dp 06/25/20 Initial version for armclang
-;*
-;*
-;******************************************************************************/
-#include "xparameters.h"
-
- EXPORT _prestart
- EXPORT _boot
- IMPORT |Image$$ARM_LIB_STACK$$Base|
- IMPORT |Image$$ARM_IRQ_STACK$$Base|
- IMPORT |Image$$ARM_SV_STACK$$Base|
- IMPORT |Image$$ARM_ABORT_STACK$$Base|
- IMPORT |Image$$ARM_FIQ_STACK$$Base|
- IMPORT |Image$$ARM_UNDEF_STACK$$Base|
- IMPORT Init_MPU
- IMPORT _startup
-
-RPU_GLBL_CNTL EQU 0xFF9A0000
-RPU_ERR_INJ EQU 0xFF9A0020
-RPU_0_CFG EQU 0xFF9A0100
-RPU_1_CFG EQU 0xFF9A0200
-#if defined(versal)
-RST_LPD_DBG EQU 0xFF5E0338
-BOOT_MODE_USER EQU 0xF1260200
-#else
-RST_LPD_DBG EQU 0xFF5E0240
-BOOT_MODE_USER EQU 0xFF5E0200
-#endif
-fault_log_enable EQU 0x101
-
-;0th bit of PROCESSOR_ACCESS_VALUE macro signifies trustzone
-;setting for RPU address space
-
-#define RPU_TZ_MASK 0x1
-
- AREA |.boot|, CODE
- REQUIRE8 {TRUE}
- PRESERVE8 {TRUE}
- ENTRY
-;this initializes the various processor modes
-
-_prestart
-_boot
-
-OKToRun
-
-;Initialize processor registers to 0
- mov r0,#0
- mov r1,#0
- mov r2,#0
- mov r3,#0
- mov r4,#0
- mov r5,#0
- mov r6,#0
- mov r7,#0
- mov r8,#0
- mov r9,#0
- mov r10,#0
- mov r11,#0
- mov r12,#0
-
-;Initialize stack pointer and banked registers for various mode
- mrs r0, cpsr ;get the current PSR
- mvn r1, #0x1f ;set up the irq stack pointer
- and r2, r1, r0
- orr r2, r2, #0x12 ;IRQ mode
- msr cpsr_cxsf, r2
- ldr r13,=|Image$$ARM_IRQ_STACK$$Base| ;IRQ stack pointer
- mov r14,#0
-
- mrs r0, cpsr ;get the current PSR
- mvn r1, #0x1f ;set up the supervisor stack pointer
- and r2, r1, r0
- orr r2, r2, #0x13 ;supervisor mode
- msr cpsr_cxsf, r2
- ldr r13,=|Image$$ARM_SV_STACK$$Base| ;Supervisor stack pointer
- mov r14,#0
-
- mrs r0, cpsr ;get the current PSR
- mvn r1, #0x1f ;set up the Abort stack pointer
- and r2, r1, r0
- orr r2, r2, #0x17 ;Abort mode
- msr cpsr_cxsf, r2
- ldr r13,=|Image$$ARM_ABORT_STACK$$Base| ;Abort stack pointer
- mov r14,#0
-
- mrs r0, cpsr ;get the current PSR
- mvn r1, #0x1f ;set up the FIQ stack pointer
- and r2, r1, r0
- orr r2, r2, #0x11 ;FIQ mode
- msr cpsr_cxsf, r2
- mov r8, #0
- mov r9, #0
- mov r10, #0
- mov r11, #0
- mov r12, #0
- ldr r13,=|Image$$ARM_FIQ_STACK$$Base| ;FIQ stack pointer
- mov r14,#0
-
- mrs r0, cpsr ;get the current PSR
- mvn r1, #0x1f ;set up the Undefine stack pointer
- and r2, r1, r0
- orr r2, r2, #0x1b ;Undefine mode
- msr cpsr_cxsf, r2
- ldr r13,=|Image$$ARM_UNDEF_STACK$$Base| ;Undefine stack pointer
- mov r14,#0
-
- mrs r0, cpsr ;get the current PSR
- mvn r1, #0x1f ;set up the system stack pointer
- and r2, r1, r0
- orr r2, r2, #0x1F ;SYS mode
- msr cpsr_cxsf, r2
- ldr r13,=|Image$$ARM_LIB_STACK$$Base| ;SYS stack pointer
- mov r14,#0
-
-;Enable access to VFP by enabling access to Coprocessors 10 and 11.
-;Enables Full Access i.e. in both privileged and non privileged modes
- mrc p15, 0, r0, c1, c0, 2 ;Read Coprocessor Access Control Register (CPACR)
- orr r0, r0, #(0xF << 20) ;Enable access to CP 10 & 11
- mcr p15, 0, r0, c1, c0, 2 ;Write Coprocessor Access Control Register (CPACR)
- isb
-
-;enable fpu access
- vmrs r3, FPEXC
- orr r1, r3, #(1<<30)
- vmsr FPEXC, r1
-
-;clear the floating point register
- mov r1,#0
- vmov d0,r1,r1
- vmov d1,r1,r1
- vmov d2,r1,r1
- vmov d3,r1,r1
- vmov d4,r1,r1
- vmov d5,r1,r1
- vmov d6,r1,r1
- vmov d7,r1,r1
- vmov d8,r1,r1
- vmov d9,r1,r1
- vmov d10,r1,r1
- vmov d11,r1,r1
- vmov d12,r1,r1
- vmov d13,r1,r1
- vmov d14,r1,r1
- vmov d15,r1,r1
-
-#ifdef __SOFTFP__
-;Disable the FPU if SOFTFP is defined
- vmsr FPEXC,r3
-#endif
-
-;Disable MPU and caches
- mrc p15, 0, r0, c1, c0, 0 ;Read CP15 Control Register
- bic r0, r0, #0x05 ;Disable MPU (M bit) and data cache (C bit)
- bic r0, r0, #0x1000 ;Disable instruction cache (I bit)
- dsb ;Ensure all previous loads/stores have completed
- mcr p15, 0, r0, c1, c0, 0 ;Write CP15 Control Register
- isb ;Ensure subsequent insts execute wrt new MPU settings
-
-;Disable Branch prediction, TCM ECC checks
- mrc p15, 0, r0, c1, c0, 1 ;Read ACTLR
- orr r0, r0, #(0x1 << 17) ;Enable RSDIS bit 17 to disable the return stack
- orr r0, r0, #(0x1 << 16) ;Clear BP bit 15 and set BP bit 16:
- bic r0, r0, #(0x1 << 15) ;Branch always not taken and history table updates disabled
- orr r0, r0, #(0x1 << 27) ;Enable B1TCM ECC check
- orr r0, r0, #(0x1 << 26) ;Enable B0TCM ECC check
- orr r0, r0, #(0x1 << 25) ;Enable ATCM ECC check
- bic r0, r0, #(0x1 << 5) ;Generate abort on parity errors, with [5:3]=b 000
- bic r0, r0, #(0x1 << 4)
- bic r0, r0, #(0x1 << 3)
- mcr p15, 0, r0, c1, c0, 1 ;Write ACTLR
- dsb ;Complete all outstanding explicit memory operations
-
-;Invalidate caches
- mov r0,#0 ;r0 = 0
- dsb
- mcr p15, 0, r0, c7, c5, 0 ;invalidate icache
- mcr p15, 0, r0, c15, c5, 0 ;Invalidate entire data cache
- isb
-#if LOCKSTEP_MODE_DEBUG == 0 && (PROCESSOR_ACCESS_VALUE & RPU_TZ_MASK)
-;enable fault log for lock step
- ldr r0,=RPU_GLBL_CNTL
- ldr r1, [r0]
- ands r1, r1, #0x8
-;branch to initialization if split mode
- bne init
-;check for boot mode if in lock step, branch to init if JTAG boot mode
- ldr r0,=BOOT_MODE_USER
- ldr r1, [r0]
- ands r1, r1, #0xF
- beq init
-;reset the debug logic
- ldr r0,=RST_LPD_DBG
- ldr r1, [r0]
- orr r1, r1, #(0x1 << 4)
- orr r1, r1, #(0x1 << 5)
- str r1, [r0]
-;enable fault log
- ldr r0,=RPU_ERR_INJ
- ldr r1,=fault_log_enable
- ldr r2, [r0]
- orr r2, r2, r1
- str r2, [r0]
- nop
- nop
-#endif
-
-init
- bl Init_MPU;Initialize MPU
-
-;Enable Branch prediction
- mrc p15, 0, r0, c1, c0, 1 ;Read ACTLR
- bic r0, r0, #(0x1 << 17) ;Clear RSDIS bit 17 to enable return stack
- bic r0, r0, #(0x1 << 16) ;Clear BP bit 15 and BP bit 16:
- bic r0, r0, #(0x1 << 15) ;Normal operation, BP is taken from the global history table.
- orr r0, r0, #(0x1 << 14) ;Disable DBWR for errata 780125
- mcr p15, 0, r0, c1, c0, 1 ;Write ACTLR
-
-;Enable icahce and dcache
- mrc p15,0,r1,c1,c0,0
- ldr r0, =0x1005
- orr r1,r1,r0
- dsb
- mcr p15,0,r1,c1,c0,0 ;Enable cache
- isb ;isb flush prefetch buffer
-
-;Set vector table in TCM/LOVEC
-#ifndef VEC_TABLE_IN_OCM
- mrc p15, 0, r0, c1, c0, 0
- mvn r1, #0x2000
- and r0, r0, r1
- mcr p15, 0, r0, c1, c0, 0
-
-;Check if processor is having access to RPU address space
-#if (PROCESSOR_ACCESS_VALUE & RPU_TZ_MASK)
-;Clear VINITHI to enable LOVEC on reset
-#if XPAR_CPU_ID == 0
- ldr r0, =RPU_0_CFG
-#else
- ldr r0, =RPU_1_CFG
-#endif
- ldr r1, [r0]
- bic r1, r1, #(0x1 << 2)
- str r1, [r0]
-#endif
-#endif
-;enable asynchronous abort exception
- mrs r0, cpsr
- bic r0, r0, #0x100
- msr cpsr_xsf, r0
-
- bl _startup
-
-Ldone
- b Ldone ;Paranoia: we should never get here
-
- END
-;@} End of "addtogroup r5_boot_code".
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8d/3073c6525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8d/3073c6525243001d18b399c1eb9b3628
deleted file mode 100644
index 5a1bda3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8d/3073c6525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,76 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_testio.h
-*
-* @addtogroup common_test_utils Test Utilities for Memory and Caches
-*
I/O test
-* The xil_testio.h file contains utility functions to test endian related memory
-* IO functions.
-*
-* A subset of the memory tests can be selected or all of the tests can be run
-* in order. If there is an error detected by a subtest, the test stops and the
-* failure code is returned. Further tests are not run even if all of the tests
-* are selected.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00 hbm 08/05/09 First release
-*
-; MODIFICATION HISTORY:
-;
-; Ver Who Date Changes
-; ----- ---- -------- ---------------------------------------------------
-; 5.00 mus 01/27/17 Initial version
-; 6.6 srm 10/18/17 Updated the timer configuration with XTime_StartTTCTimer.
-; Now the timer instance as specified by the user will be
-; started.
-; 6.6 mus 02/23/17 Disable the debug logic in non-JTAG boot mode(when
-; processor is in lockstep configuration), based
-; on the mld parameter "lockstep_mode_debug".
-* 6.8 mus 09/20/18 Clear VINITHI field in RPU_0_CFG/RPU_1_CFG
-* registers to initialize CortexR5 core with LOVEC
-* on reset. It fixes CR#1010656.
-* 7.0 mus 03/19/19 Disable FPU only in case of softp, otherwise enable it by
-* default. CR#1021638
-;
-;
-;
-; @note
-;
-; None.
-;
-; *****************************************************************************/
-
- MODULE ?boot
- ;; Forward declaration of sections.
- SECTION IRQ_STACK:DATA:NOROOT(3)
- SECTION FIQ_STACK:DATA:NOROOT(3)
- SECTION SVC_STACK:DATA:NOROOT(3)
- SECTION ABT_STACK:DATA:NOROOT(3)
- SECTION UND_STACK:DATA:NOROOT(3)
- SECTION CSTACK:DATA:NOROOT(3)
-
-#include "xparameters.h"
-
-#define UART_BAUDRATE 115200
- PUBLIC _prestart
- PUBLIC __iar_program_start
- IMPORT _vector_table
- IMPORT Init_MPU
-#ifdef SLEEP_TIMER_BASEADDR
- IMPORT XTime_StartTTCTimer
-#endif
- IMPORT __cmain
-vector_base EQU _vector_table
-RPU_GLBL_CNTL EQU 0xFF9A0000
-RPU_ERR_INJ EQU 0xFF9A0020
-RPU_0_CFG EQU 0xFF9A0100
-RPU_1_CFG EQU 0xFF9A0200
-RST_LPD_DBG EQU 0xFF5E0240
-BOOT_MODE_USER EQU 0xFF5E0200
-fault_log_enable EQU 0x101
-
- SECTION .boot:CODE:NOROOT(2)
-
-
-/* this initializes the various processor modes */
-
-_prestart
-__iar_program_start
-
-OKToRun
-
- REQUIRE _vector_table
-/* Initialize processor registers to 0 */
- mov r0,#0
- mov r1,#0
- mov r2,#0
- mov r3,#0
- mov r4,#0
- mov r5,#0
- mov r6,#0
- mov r7,#0
- mov r8,#0
- mov r9,#0
- mov r10,#0
- mov r11,#0
- mov r12,#0
-
-/* Initialize stack pointer and banked registers for various mode */
- mrs r0, cpsr ; get the current PSR
- mvn r1, #0x1f ; set up the irq stack pointer
- and r2, r1, r0
- orr r2, r2, #0x12 ; IRQ mode
- msr cpsr, r2
- ldr r13,=SFE(IRQ_STACK) ; IRQ stack pointer
- mov r14,#0
-
- mrs r0, cpsr ; get the current PSR
- mvn r1, #0x1f ; set up the supervisor stack pointer
- and r2, r1, r0
- orr r2, r2, #0x13 ; supervisor mode
- msr cpsr, r2
- ldr r13,=SFE(SVC_STACK) ; Supervisor stack pointer
- mov r14,#0
-
- mrs r0, cpsr ; get the current PSR
- mvn r1, #0x1f ; set up the Abort stack pointer
- and r2, r1, r0
- orr r2, r2, #0x17 ; Abort mode
- msr cpsr, r2
- ldr r13,=SFE(ABT_STACK) ; Abort stack pointer
- mov r14,#0
-
- mrs r0, cpsr ; get the current PSR
- mvn r1, #0x1f ; set up the FIQ stack pointer
- and r2, r1, r0
- orr r2, r2, #0x11 ; FIQ mode
- msr cpsr, r2
- mov r8, #0
- mov r9, #0
- mov r10, #0
- mov r11, #0
- mov r12, #0
- ldr r13,=SFE(FIQ_STACK) ; FIQ stack pointer
- mov r14,#0
-
- mrs r0, cpsr ; get the current PSR
- mvn r1, #0x1f ; set up the Undefine stack pointer
- and r2, r1, r0
- orr r2, r2, #0x1b ; Undefine mode
- msr cpsr, r2
- ldr r13,=SFE(UND_STACK) ; Undefine stack pointer
- mov r14,#0
-
- mrs r0, cpsr ; get the current PSR
- mvn r1, #0x1f ; set up the system stack pointer
- and r2, r1, r0
- orr r2, r2, #0x1F ; SYS mode
- msr cpsr, r2
- ldr r13,=SFE(CSTACK) ; SYS stack pointer
- mov r14,#0
-
- ;
- ; Enable access to VFP by enabling access to Coprocessors 10 and 11.
- ; Enables Full Access i.e. in both privileged and non privileged modes
- ;
- mrc p15, 0, r0, c1, c0, 2 ; Read Coprocessor Access Control Register (CPACR)
- orr r0, r0, #(0xF << 20) ; Enable access to CP 10 & 11
- mcr p15, 0, r0, c1, c0, 2 ; Write Coprocessor Access Control Register (CPACR)
- isb
-
-; enable fpu access
- vmrs r3, FPEXC
- orr r1, r3, #(1<<30)
- vmsr FPEXC, r1
-
- ; clear the floating point register
- mov r1,#0
- vmov d0,r1,r1
- vmov d1,r1,r1
- vmov d2,r1,r1
- vmov d3,r1,r1
- vmov d4,r1,r1
- vmov d5,r1,r1
- vmov d6,r1,r1
- vmov d7,r1,r1
- vmov d8,r1,r1
- vmov d9,r1,r1
- vmov d10,r1,r1
- vmov d11,r1,r1
- vmov d12,r1,r1
- vmov d13,r1,r1
- vmov d14,r1,r1
- vmov d15,r1,r1
-
-#ifdef __SOFTFP__
- ; Disable FPU by restoring previous value for FPU access
- vmsr FPEXC,r3
-#endif
-
- ; Disable MPU and caches
- mrc p15, 0, r0, c1, c0, 0 ; Read CP15 Control Register
- bic r0, r0, #0x05 ; Disable MPU (M bit) and data cache (C bit)
- bic r0, r0, #0x1000 ; Disable instruction cache (I bit)
- dsb ; Ensure all previous loads/stores have completed
- mcr p15, 0, r0, c1, c0, 0 ; Write CP15 Control Register
- isb ; Ensure subsequent insts execute wrt new MPU settings
-
- ; Disable Branch prediction, TCM ECC checks
- mrc p15, 0, r0, c1, c0, 1 ; Read ACTLR
- orr r0, r0, #(0x1 << 17) ; Enable RSDIS bit 17 to disable the return stack
- orr r0, r0, #(0x1 << 16) ; Clear BP bit 15 and set BP bit 16
- bic r0, r0, #(0x1 << 15) ; Branch always not taken and history table updates disabled
- bic r0, r0, #(0x1 << 27) ; Disable B1TCM ECC check
- bic r0, r0, #(0x1 << 26) ; Disable B0TCM ECC check
- bic r0, r0, #(0x1 << 25) ; Disable ATCM ECC check
- orr r0, r0, #(0x1 << 5) ; Enable ECC with no forced write through with [5:3]=b'101
- bic r0, r0, #(0x1 << 4)
- orr r0, r0, #(0x1 << 3)
- mcr p15, 0, r0, c1, c0, 1 ; Write ACTLR*/
- dsb ; Complete all outstanding explicit memory operations*/
-
- ; Invalidate caches
- mov r0,#0 ; r0 = 0
- dsb
- mcr p15, 0, r0, c7, c5, 0 ; invalidate icache
- mcr p15, 0, r0, c15, c5, 0 ; Invalidate entire data cache
- isb
-
-#if LOCKSTEP_MODE_DEBUG == 0
- ; enable fault log for lock step
- ldr r0,=RPU_GLBL_CNTL
- ldr r1, [r0]
- ands r1, r1, #0x8
- ; branch to initialization if split mode
- bne init
- ; check for boot mode if in lock step, branch to init if JTAG boot mode
- ldr r0,=BOOT_MODE_USER
- ldr r1, [r0]
- ands r1, r1, #0xF
- beq init
- ; reset the debug logic
- ldr r0,=RST_LPD_DBG
- ldr r1, [r0]
- orr r1, r1, #(0x1 << 1)
- orr r1, r1, #(0x1 << 4)
- orr r1, r1, #(0x1 << 5)
- str r1, [r0]
- ; enable fault log
- ldr r0,=RPU_ERR_INJ
- ldr r1,=fault_log_enable
- ldr r2, [r0]
- orr r2, r2, r1
- str r2, [r0]
- nop
- nop
- #endif
-
-init
- bl Init_MPU ; Initialize MPU
-
- ; Enable Branch prediction
- mrc p15, 0, r0, c1, c0, 1 ; Read ACTLR
- bic r0, r0, #(0x1 << 17) ; Clear RSDIS bit 17 to enable return stack
- bic r0, r0, #(0x1 << 16) ; Clear BP bit 15 and BP bit 16:
- bic r0, r0, #(0x1 << 15) ; Normal operation, BP is taken from the global history table.
- orr r0, r0, #(0x1 << 14) ; Disable DBWR for errata 780125
- mcr p15, 0, r0, c1, c0, 1 ; Write ACTLR
-
- ; Enable icahce and dcache
- mrc p15,0,r1,c1,c0,0
- ldr r0, =0x1005
- orr r1,r1,r0
- dsb
- mcr p15,0,r1,c1,c0,0 ; Enable cache
- isb ; isb flush prefetch buffer
-
-
-
- ; Set vector table in TCM/LOVEC
-#ifndef VEC_TABLE_IN_OCM
- mrc p15, 0, r0, c1, c0, 0
- mvn r1, #0x2000
- and r0, r0, r1
- mcr p15, 0, r0, c1, c0, 0
-
- ; Clear VINITHI to enable LOVEC on reset
-#if XPAR_CPU_ID == 0
- ldr r0, =RPU_0_CFG
-#else
- ldr r0, =RPU_1_CFG
-#endif
- ldr r1, [r0]
- bic r1, r1, #(0x1 << 2)
- str r1, [r0]
-#endif
-
- ; enable asynchronous abort exception
- mrs r0, cpsr
- bic r0, r0, #0x100
- msr cpsr_xsf, r0
-
- ; Clear cp15 regs with unknown reset values
- mov r0, #0x0
- mcr p15, 0, r0, c5, c0, 0 ; DFSR
- mcr p15, 0, r0, c5, c0, 1 ; IFSR
- mcr p15, 0, r0, c6, c0, 0 ; DFAR
- mcr p15, 0, r0, c6, c0, 2 ; IFAR
- mcr p15, 0, r0, c9, c13, 2 ; PMXEVCNTR
- mcr p15, 0, r0, c13, c0, 2 ; TPIDRURW
- mcr p15, 0, r0, c13, c0, 3 ; TPIDRURO
-
-
- ; Reset and start Cycle Counter
- mov r2, #0x80000000 ; clear overflow
- mcr p15, 0, r2, c9, c12, 3
- mov r2, #0xd ; D, C, E
- mcr p15, 0, r2, c9, c12, 0
- mov r2, #0x80000000 ; enable cycle counter
- mcr p15, 0, r2, c9, c12, 1
-
- ; configure the timer if TTC is present
- #ifdef SLEEP_TIMER_BASEADDR
- bl XTime_StartTTCTimer
- #endif
-
- ; make sure argc and argv are valid
- mov r0, #0
- mov r1, #0
-
- b __cmain ; jump to C startup code
-
-
-Ldone b Ldone ; Paranoia: we should never get here
-
-
- END
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8e/00024e585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8e/00024e585243001d18b399c1eb9b3628
deleted file mode 100644
index 0fe994b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8e/00024e585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,60 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.h
-*
-* @addtogroup a53_32_cache_apis Cortex A53 32bit Processor Cache Functions
-*
-* Cache functions provide access to cache related operations such as flush
-* and invalidate for instruction and data caches. It gives option to perform
-* the cache operations on a single cacheline, a range of memory and an entire
-* cache.
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.2 pkp 28/05/15 First release
-*
-*
-******************************************************************************/
-#ifndef XIL_CACHE_H
-#define XIL_CACHE_H
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void Xil_DCacheEnable(void);
-void Xil_DCacheDisable(void);
-void Xil_DCacheInvalidate(void);
-void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
-void Xil_DCacheFlush(void);
-void Xil_DCacheFlushRange(INTPTR adr, u32 len);
-void Xil_DCacheInvalidateLine(u32 adr);
-void Xil_DCacheFlushLine(u32 adr);
-
-void Xil_ICacheInvalidateLine(u32 adr);
-void Xil_ICacheEnable(void);
-void Xil_ICacheDisable(void);
-void Xil_ICacheInvalidate(void);
-void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-* @} End of "addtogroup a53_64_cache_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8e/0041a6525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8e/0041a6525243001d18b399c1eb9b3628
deleted file mode 100644
index 33b33eb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8e/0041a6525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,167 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xgpio_l.h
-* @addtogroup gpio_v4_8
-* @{
-*
-* This header file contains identifiers and driver functions (or
-* macros) that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-*
-* The macros that are available in this file use a multiply to calculate the
-* addresses of registers. The user can control whether that multiply is done
-* at run time or at compile time. A constant passed as the channel parameter
-* will cause the multiply to be done at compile time. A variable passed as the
-* channel parameter will cause it to occur at run time.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a jhl 04/24/02 First release of low level driver
-* 2.00a jhl 11/26/03 Added support for dual channels and interrupts. This
-* change required the functions to be changed such that
-* the interface is not compatible with previous versions.
-* See the examples in the example directory for macros
-* to help compile an application that was designed for
-* previous versions of the driver. The interrupt registers
-* are accessible using the ReadReg and WriteReg macros and
-* a channel parameter was added to the other macros.
-* 2.11a mta 03/21/07 Updated to new coding style
-* 2.12a sv 11/21/07 Updated driver to support access through DCR bus.
-* 3.00a sv 11/21/09 Renamed the macros XGpio_mWriteReg to XGpio_WriteReg
-* XGpio_mReadReg to XGpio_ReadReg.
-* Removed the macros XGpio_mSetDataDirection,
-* XGpio_mGetDataReg and XGpio_mSetDataReg. Users
-* should use XGpio_WriteReg/XGpio_ReadReg to achieve the
-* same functionality.
-* 4.1 lks 11/18/15 Removed support for DCR bridge
-*
-*
-******************************************************************************/
-
-#ifndef XGPIO_L_H /* prevent circular inclusions */
-#define XGPIO_L_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-
-/************************** Constant Definitions *****************************/
-
-/** @name Registers
- *
- * Register offsets for this device.
- * @{
- */
-#define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */
-#define XGPIO_TRI_OFFSET 0x4 /**< I/O direction reg for 1st channel */
-#define XGPIO_DATA2_OFFSET 0x8 /**< Data register for 2nd channel */
-#define XGPIO_TRI2_OFFSET 0xC /**< I/O direction reg for 2nd channel */
-
-#define XGPIO_GIE_OFFSET 0x11C /**< Glogal interrupt enable register */
-#define XGPIO_ISR_OFFSET 0x120 /**< Interrupt status register */
-#define XGPIO_IER_OFFSET 0x128 /**< Interrupt enable register */
-
-/** @} */
-
-/* The following constant describes the offset of each channels data and
- * tristate register from the base address.
- */
-#define XGPIO_CHAN_OFFSET 8 /**< Channel offeset */
-
-/** @name Interrupt Status and Enable Register bitmaps and masks
- *
- * Bit definitions for the interrupt status register and interrupt enable
- * registers.
- * @{
- */
-#define XGPIO_IR_MASK 0x3 /**< Mask of all bits */
-#define XGPIO_IR_CH1_MASK 0x1 /**< Mask for the 1st channel */
-#define XGPIO_IR_CH2_MASK 0x2 /**< Mask for the 2nd channel */
-/** @}*/
-
-
-/** @name Global Interrupt Enable Register bitmaps and masks
- *
- * Bit definitions for the Global Interrupt Enable register
- * @{
- */
-#define XGPIO_GIE_GINTR_ENABLE_MASK 0x80000000 /**< Mask for Global Interrupt */
-/** @}*/
-
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XGpio_In32 Xil_In32 /**< Input Operations */
-#define XGpio_Out32 Xil_Out32 /**< Output Operations */
-
-
-/****************************************************************************/
-/**
-*
-* Write a value to a GPIO register. A 32 bit write is performed. If the
-* GPIO core is implemented in a smaller width, only the least significant data
-* is written.
-*
-* @param BaseAddress is the base address of the GPIO device.
-* @param RegOffset is the register offset from the base to write to.
-* @param Data is the data written to the register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XGpio_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
-****************************************************************************/
-#define XGpio_WriteReg(BaseAddress, RegOffset, Data) \
- XGpio_Out32((BaseAddress) + (RegOffset), (u32)(Data))
-
-/****************************************************************************/
-/**
-*
-* Read a value from a GPIO register. A 32 bit read is performed. If the
-* GPIO core is implemented in a smaller width, only the least
-* significant data is read from the register. The most significant data
-* will be read as 0.
-*
-* @param BaseAddress is the base address of the GPIO device.
-* @param RegOffset is the register offset from the base to read from.
-*
-* @return Data read from the register.
-*
-* @note C-style signature:
-* u32 XGpio_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-****************************************************************************/
-#define XGpio_ReadReg(BaseAddress, RegOffset) \
- XGpio_In32((BaseAddress) + (RegOffset))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8f/00b630585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8f/00b630585243001d18b399c1eb9b3628
deleted file mode 100644
index d61e2b5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8f/00b630585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,118 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xsdps_core.h
-* @addtogroup sdps_v3_13
-* @{
-*
-* This header file contains the identifiers and basic HW access driver
-* functions (or macros) that can be used to access the device. Other driver
-* functions are defined in xsdps.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 3.9 mn 03/03/20 Restructured the code for more readability and modularity
-* mn 03/16/20 Move XSdPs_Select_Card API to User APIs
-* 3.12 sk 01/28/21 Added support for non-blocking write.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 5.4 pkp 18/12/15 Initialized global constructor for C++ applications
-* 6.6 srm 10/18/17 Added timer configuration using XTime_StartTTCTimer API.
-* Now the TTC instance as specified by the user will be
-* started.
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#include "xparameters.h"
- .file "xil-crt0.S"
- .section ".got2","aw"
- .align 2
-
- .text
-.Lsbss_start:
- .long __sbss_start
-
-.Lsbss_end:
- .long __sbss_end
-
-.Lbss_start:
- .long __bss_start__
-
-.Lbss_end:
- .long __bss_end__
-
-
-.Lstack:
- .long __stack
-
- .globl _startup
-_startup:
-
- mov r0, #0
-
- /* clear sbss */
- ldr r1,.Lsbss_start /* calculate beginning of the SBSS */
- ldr r2,.Lsbss_end /* calculate end of the SBSS */
-
-.Lloop_sbss:
- cmp r1,r2
- bge .Lenclsbss /* If no SBSS, no clearing required */
- str r0, [r1], #4
- b .Lloop_sbss
-
-.Lenclsbss:
- /* clear bss */
- ldr r1,.Lbss_start /* calculate beginning of the BSS */
- ldr r2,.Lbss_end /* calculate end of the BSS */
-
-.Lloop_bss:
- cmp r1,r2
- bge .Lenclbss /* If no BSS, no clearing required */
- str r0, [r1], #4
- b .Lloop_bss
-
-.Lenclbss:
- /* set stack pointer */
- ldr r13,.Lstack /* stack address */
-
- /* run global constructors */
- bl __libc_init_array
-
- /* Reset and start Triple Timer Counter */
- #if defined (SLEEP_TIMER_BASEADDR)
- bl XTime_StartTTCTimer
- #endif
-
- /* make sure argc and argv are valid */
- mov r0, #0
- mov r1, #0
-
- bl main /* Jump to main C code */
-
- /* Cleanup global constructors */
- bl __libc_fini_array
-
- bl exit
-
-.Lexit: /* should never get here */
- b .Lexit
-
-.Lstart:
- .size _startup,.Lstart-_startup
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8f/918e80595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8f/918e80595243001d18b399c1eb9b3628
deleted file mode 100644
index b248e6a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8f/918e80595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,27 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#ifndef UNDEFINE_FILE_OPS
-#include
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode);
-}
-#endif
-/*
- * open -- open a file descriptor. We don't have a filesystem, so
- * we return an error.
- */
-__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode)
-{
- (void)buf;
- (void)flags;
- (void)mode;
- errno = EIO;
- return (-1);
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8f/a0397d565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8f/a0397d565243001d18b399c1eb9b3628
deleted file mode 100644
index 12fa312..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8f/a0397d565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,125 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#ifndef FSL_H
-#define FSL_H
-/*****************************************************************************/
-/**
-*
-* @file fsl.h
-*
-* @addtogroup microblaze_fsl_macro MicroBlaze Processor FSL Macros
-*
-* Microblaze BSP includes macros to provide convenient access to accelerators
-* connected to the MicroBlaze Fast Simplex Link (FSL) Interfaces.To use these functions,
-* include the header file fsl.h in your source code
-*
-* @{
-*
-******************************************************************************/
-#include "mb_interface.h" /* Legacy reasons. We just have to include this guy who defines the FSL stuff */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *@cond nocomments
- */
-/* Extended FSL macros. These now replace all of the previous FSL macros */
-#define FSL_DEFAULT
-#define FSL_NONBLOCKING n
-#define FSL_EXCEPTION e
-#define FSL_CONTROL c
-#define FSL_ATOMIC a
-
-#define FSL_NONBLOCKING_EXCEPTION ne
-#define FSL_NONBLOCKING_CONTROL nc
-#define FSL_NONBLOCKING_ATOMIC na
-#define FSL_EXCEPTION_CONTROL ec
-#define FSL_EXCEPTION_ATOMIC ea
-#define FSL_CONTROL_ATOMIC ca
-
-#define FSL_NONBLOCKING_EXCEPTION_CONTROL nec
-#define FSL_NONBLOCKING_EXCEPTION_ATOMIC nea
-#define FSL_NONBLOCKING_CONTROL_ATOMIC nca
-#define FSL_EXCEPTION_CONTROL_ATOMIC eca
-
-#define FSL_NONBLOCKING_EXCEPTION_CONTROL_ATOMIC neca
-
- /**
- *@endcond
- */
-
-/**
-Performs a get function on an input FSL of the MicroBlaze processor
-@param val variable to sink data from get function
-@param id literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
-@param flags valid FSL macro flags
-*/
-#define getfslx(val, id, flags) asm volatile (stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
-
-/**
-Performs a put function on an input FSL of the MicroBlaze processor
-@param val variable to source data to put function
-@param id literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
-@param flags valid FSL macro flags
-*/
-#define putfslx(val, id, flags) asm volatile (stringify(flags) "put\t%0,rfsl" stringify(id) :: "d" (val))
-
-/**
-Performs a test get function on an input FSL of the MicroBlaze processor
-@param val variable to sink data from get function
-@param id literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
-@param flags valid FSL macro flags
-*/
-#define tgetfslx(val, id, flags) asm volatile ("t" stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
-
-/**
-Performs a put function on an input FSL of the MicroBlaze processor
-@param id FSL identifier
-@param flags valid FSL macro flags
-*/
-#define tputfslx(id, flags) asm volatile ("t" stringify(flags) "put\trfsl" stringify(id))
-
-/**
-Performs a getd function on an input FSL of the MicroBlaze processor
-@param val variable to sink data from getd function
-@param var literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
-@param flags valid FSL macro flags
-*/
-#define getdfslx(val, var, flags) asm volatile (stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
-
-/**
-Performs a putd function on an input FSL of the MicroBlaze processor
-@param val variable to source data to putd function
-@param var literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
-@param flags valid FSL macro flags
-*/
-#define putdfslx(val, var, flags) asm volatile (stringify(flags) "putd\t%0,%1" :: "d" (val), "d" (var))
-
-/**
-Performs a test getd function on an input FSL of the MicroBlaze processor;
-@param val variable to sink data from getd function
-@param var literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
-@param flags valid FSL macro flags
-*/
-#define tgetdfslx(val, var, flags) asm volatile ("t" stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
-
-/**
-Performs a put function on an input FSL of the MicroBlaze processor
-@param var FSL identifier
-@param flags valid FSL macro flags
-*/
-#define tputdfslx(var, flags) asm volatile ("t" stringify(flags) "putd\t%0" :: "d" (var))
-
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* FSL_H */
-/**
-* @} End of "addtogroup microblaze_fsl_macro".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8f/d02b72585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8f/d02b72585243001d18b399c1eb9b3628
deleted file mode 100644
index 03d84cd..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8f/d02b72585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * xen_console.h
- *
- * Created on: Sep 14, 2016
- * Author: jarvis
- */
-/*
-Copyright DornerWorks 2016
-
-Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-following conditions are met:
-1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
-following disclaimer.
-
-THIS SOFTWARE IS PROVIDED BY DORNERWORKS FOR USE ON THE CONTRACTED PROJECT, AND ANY EXPRESS OR IMPLIED WARRANTY
-IS LIMITED TO THIS USE. FOR ALL OTHER USES THIS SOFTWARE IS PROVIDED ''AS IS'' AND ANY EXPRESS OR IMPLIED
-WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL DORNERWORKS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-#ifndef _XEN_CONSOLE_H_
-
-typedef void (*callback_func)(char* data, int size);
-
-void printk(const char *fmt, ...);
-void init_console(void);
-void register_console_callback(callback_func fptr);
-int XPVXenConsole_Printf(const char *FormatPtr, ...);
-void XPVXenConsole_Init(void);
-int XPVXenConsole_Write(const char *BufferPtr);
-
-#define _XEN_CONSOLE_H_
-
-
-
-#endif /* _XEN_CONSOLE_H_ */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8f/e10dce555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8f/e10dce555243001d18b399c1eb9b3628
deleted file mode 100644
index 42baaee..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8f/e10dce555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,13 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#include "xil_types.h"
-/* Stuv for exit() sys-call */
-__weak void _sys_exit(s32 rc)
-{
- while(1) {
- ;
- }
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8f/e205f3565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8f/e205f3565243001d18b399c1eb9b3628
deleted file mode 100644
index 31156ee..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/8f/e205f3565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,96 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xl2cc_counter.h
-*
-* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions
-*
-* xl2cc_counter.h contains APIs for configuring and controlling the event
-* counters in PL310 L2 cache controller.
-* PL310 has two event counters which can be used to count variety of events
-* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions
-* for different configurations which can be used for the event counters to
-* count a set of events.
-*
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
-* inside the APIs
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-* The xil_testcache.h file contains utility functions to test cache.
-*
-* @{
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 07/29/09 First release
-*
-*
-******************************************************************************/
-
-/**
-*@cond nocomments
-*/
-
-#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */
-#define XIL_TESTCACHE_H /* by using protection macros */
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern s32 Xil_TestDCacheRange(void);
-extern s32 Xil_TestDCacheAll(void);
-extern s32 Xil_TestICacheRange(void);
-extern s32 Xil_TestICacheAll(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
-
-/**
-* @} End of "addtogroup common_test_utils".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/0041f9595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/0041f9595243001d18b399c1eb9b3628
deleted file mode 100644
index 266fd7f..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/0041f9595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,395 +0,0 @@
-/*----------------------------------------------------------------------------/
-/ FatFs - Generic FAT Filesystem module R0.13b /
-/-----------------------------------------------------------------------------/
-/
-/ Copyright (C) 2018, ChaN, all right reserved.
-/
-/ FatFs module is an open source software. Redistribution and use of FatFs in
-/ source and binary forms, with or without modification, are permitted provided
-/ that the following condition is met:
-
-/ 1. Redistributions of source code must retain the above copyright notice,
-/ this condition and the following disclaimer.
-/
-/ This software is provided by the copyright holder and contributors "AS IS"
-/ and any warranties related to this software are DISCLAIMED.
-/ The copyright owner or contributors be NOT LIABLE for any damages caused
-/ by use of this software.
-/
-/----------------------------------------------------------------------------*/
-
-
-#ifndef FF_DEFINED
-#define FF_DEFINED 63463 /* Revision ID */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xil_types.h"
-#include "integer.h" /* Basic integer types */
-#include "ffconf.h" /* FatFs configuration options */
-
-#if FF_DEFINED != FFCONF_DEF
-#error Wrong configuration file (ffconf.h).
-#endif
-
-
-
-/* Definitions of volume management */
-
-#if FF_MULTI_PARTITION /* Multiple partition configuration */
-typedef struct {
- BYTE pd; /* Physical drive number */
- BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */
-} PARTITION;
-extern PARTITION VolToPart[]; /* Volume - Partition resolution table */
-#endif
-
-#if FF_STR_VOLUME_ID
-#ifndef FF_VOLUME_STRS
-extern const char* VolumeStr[FF_VOLUMES]; /* User defied volume ID */
-#endif
-#endif
-
-
-
-/* Type of path name strings on FatFs API */
-
-#ifndef _INC_TCHAR
-#define _INC_TCHAR
-
-#if FF_USE_LFN && FF_LFN_UNICODE == 1 /* Unicode in UTF-16 encoding */
-typedef WCHAR TCHAR;
-#define _T(x) L ## x
-#define _TEXT(x) L ## x
-#elif FF_USE_LFN && FF_LFN_UNICODE == 2 /* Unicode in UTF-8 encoding */
-typedef char TCHAR;
-#define _T(x) u8 ## x
-#define _TEXT(x) u8 ## x
-#elif FF_USE_LFN && FF_LFN_UNICODE == 3 /* Unicode in UTF-32 encoding */
-typedef DWORD TCHAR;
-#define _T(x) U ## x
-#define _TEXT(x) U ## x
-#elif FF_USE_LFN && (FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3)
-#error Wrong FF_LFN_UNICODE setting
-#else /* ANSI/OEM code in SBCS/DBCS */
-typedef char TCHAR;
-#define _T(x) x
-#define _TEXT(x) x
-#endif
-
-#endif
-
-
-
-/* Type of file size variables */
-
-#if FF_FS_EXFAT
-typedef QWORD FSIZE_t;
-#else
-typedef DWORD FSIZE_t;
-#endif
-
-
-
-/* Filesystem object structure (FATFS) */
-
-typedef struct {
- BYTE fs_type; /* Filesystem type (0:N/A) */
- BYTE pdrv; /* Physical drive number */
- BYTE n_fats; /* Number of FATs (1 or 2) */
- BYTE wflag; /* win[] flag (b0:dirty) */
- BYTE fsi_flag; /* FSINFO flags (b7:disabled, b0:dirty) */
- WORD id; /* Volume mount ID */
- WORD n_rootdir; /* Number of root directory entries (FAT12/16) */
- WORD csize; /* Cluster size [sectors] */
-#if FF_MAX_SS != FF_MIN_SS
- WORD ssize; /* Sector size (512, 1024, 2048 or 4096) */
-#endif
-#if FF_USE_LFN
- WCHAR* lfnbuf; /* LFN working buffer */
-#endif
-#if FF_FS_EXFAT
- BYTE* dirbuf; /* Directory entry block scratchpad buffer for exFAT */
-#endif
-#if FF_FS_REENTRANT
- FF_SYNC_t sobj; /* Identifier of sync object */
-#endif
-#if !FF_FS_READONLY
- DWORD last_clst; /* Last allocated cluster */
- DWORD free_clst; /* Number of free clusters */
-#endif
-#if FF_FS_RPATH
- DWORD cdir; /* Current directory start cluster (0:root) */
-#if FF_FS_EXFAT
- DWORD cdc_scl; /* Containing directory start cluster (invalid when cdir is 0) */
- DWORD cdc_size; /* b31-b8:Size of containing directory, b7-b0: Chain status */
- DWORD cdc_ofs; /* Offset in the containing directory (invalid when cdir is 0) */
-#endif
-#endif
- DWORD n_fatent; /* Number of FAT entries (number of clusters + 2) */
- DWORD fsize; /* Size of an FAT [sectors] */
- DWORD volbase; /* Volume base sector */
- DWORD fatbase; /* FAT base sector */
- DWORD dirbase; /* Root directory base sector/cluster */
- DWORD database; /* Data base sector */
- DWORD winsect; /* Current sector appearing in the win[] */
-#ifdef __ICCARM__
-#pragma data_alignment = 32
- BYTE win[FF_MAX_SS];
-#else
-#ifdef __aarch64__
- BYTE win[FF_MAX_SS] __attribute__ ((aligned(64))); /* Disk access window for Directory, FAT (and file data at tiny cfg) */
-#else
- BYTE win[FF_MAX_SS] __attribute__ ((aligned(32))); /* Disk access window for Directory, FAT (and file data at tiny cfg) */
-#endif
-#endif
-} FATFS;
-
-
-
-/* Object ID and allocation information (FFOBJID) */
-
-typedef struct {
- FATFS* fs; /* Pointer to the hosting volume of this object */
- WORD id; /* Hosting volume mount ID */
- BYTE attr; /* Object attribute */
- BYTE stat; /* Object chain status (b1-0: =0:not contiguous, =2:contiguous, =3:flagmented in this session, b2:sub-directory stretched) */
- DWORD sclust; /* Object data start cluster (0:no cluster or root directory) */
- FSIZE_t objsize; /* Object size (valid when sclust != 0) */
-#if FF_FS_EXFAT
- DWORD n_cont; /* Size of first fragment - 1 (valid when stat == 3) */
- DWORD n_frag; /* Size of last fragment needs to be written to FAT (valid when not zero) */
- DWORD c_scl; /* Containing directory start cluster (valid when sclust != 0) */
- DWORD c_size; /* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */
- DWORD c_ofs; /* Offset in the containing directory (valid when file object and sclust != 0) */
-#endif
-#if FF_FS_LOCK
- UINT lockid; /* File lock ID origin from 1 (index of file semaphore table Files[]) */
-#endif
-} FFOBJID;
-
-
-
-/* File object structure (FIL) */
-
-typedef struct {
- FFOBJID obj; /* Object identifier (must be the 1st member to detect invalid object pointer) */
- BYTE flag; /* File status flags */
- BYTE err; /* Abort flag (error code) */
- FSIZE_t fptr; /* File read/write pointer (Zeroed on file open) */
- DWORD clust; /* Current cluster of fpter (invalid when fptr is 0) */
- DWORD sect; /* Sector number appearing in buf[] (0:invalid) */
-#if !FF_FS_READONLY
- DWORD dir_sect; /* Sector number containing the directory entry (not used at exFAT) */
- BYTE* dir_ptr; /* Pointer to the directory entry in the win[] (not used at exFAT) */
-#endif
-#if FF_USE_FASTSEEK
- DWORD* cltbl; /* Pointer to the cluster link map table (nulled on open, set by application) */
-#endif
-#if !FF_FS_TINY
-#ifdef __ICCARM__
-#pragma data_alignment = 32
- BYTE buf[FF_MAX_SS]; /* File private data read/write window */
-#else
-#ifdef __aarch64__
- BYTE buf[FF_MAX_SS] __attribute__ ((aligned(64))); /* File private data read/write window */
-#else
- BYTE buf[FF_MAX_SS] __attribute__ ((aligned(32))); /* File private data read/write window */
-#endif
-#endif
-#endif
-} FIL;
-
-
-
-/* Directory object structure (DIR) */
-
-typedef struct {
- FFOBJID obj; /* Object identifier */
- DWORD dptr; /* Current read/write offset */
- DWORD clust; /* Current cluster */
- DWORD sect; /* Current sector (0:Read operation has terminated) */
- BYTE* dir; /* Pointer to the directory item in the win[] */
- BYTE fn[12]; /* SFN (in/out) {body[8],ext[3],status[1]} */
-#if FF_USE_LFN
- DWORD blk_ofs; /* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */
-#endif
-#if FF_USE_FIND
- const TCHAR* pat; /* Pointer to the name matching pattern */
-#endif
-} DIR;
-
-
-
-/* File information structure (FILINFO) */
-
-typedef struct {
- FSIZE_t fsize; /* File size */
- WORD fdate; /* Modified date */
- WORD ftime; /* Modified time */
- BYTE fattrib; /* File attribute */
-#if FF_USE_LFN
- TCHAR altname[FF_SFN_BUF + 1];/* Altenative file name */
- TCHAR fname[FF_LFN_BUF + 1]; /* Primary file name */
-#else
- TCHAR fname[12 + 1]; /* File name */
-#endif
-} FILINFO;
-
-
-
-/* File function return code (FRESULT) */
-
-typedef enum {
- FR_OK = 0, /* (0) Succeeded */
- FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */
- FR_INT_ERR, /* (2) Assertion failed */
- FR_NOT_READY, /* (3) The physical drive cannot work */
- FR_NO_FILE, /* (4) Could not find the file */
- FR_NO_PATH, /* (5) Could not find the path */
- FR_INVALID_NAME, /* (6) The path name format is invalid */
- FR_DENIED, /* (7) Access denied due to prohibited access or directory full */
- FR_EXIST, /* (8) Access denied due to prohibited access */
- FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
- FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
- FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
- FR_NOT_ENABLED, /* (12) The volume has no work area */
- FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */
- FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any problem */
- FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
- FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */
- FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
- FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > FF_FS_LOCK */
- FR_INVALID_PARAMETER /* (19) Given parameter is invalid */
-} FRESULT;
-
-
-
-/*--------------------------------------------------------------*/
-/* FatFs module application interface */
-
-FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */
-FRESULT f_close (FIL* fp); /* Close an open file object */
-FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from the file */
-FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to the file */
-FRESULT f_lseek (FIL* fp, FSIZE_t ofs); /* Move file pointer of the file object */
-FRESULT f_truncate (FIL* fp); /* Truncate the file */
-FRESULT f_sync (FIL* fp); /* Flush cached data of the writing file */
-FRESULT f_opendir (DIR* dp, const TCHAR* path); /* Open a directory */
-FRESULT f_closedir (DIR* dp); /* Close an open directory */
-FRESULT f_readdir (DIR* dp, FILINFO* fno); /* Read a directory item */
-FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern); /* Find first file */
-FRESULT f_findnext (DIR* dp, FILINFO* fno); /* Find next file */
-FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */
-FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */
-FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */
-FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */
-FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask); /* Change attribute of a file/dir */
-FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change timestamp of a file/dir */
-FRESULT f_chdir (const TCHAR* path); /* Change current directory */
-FRESULT f_chdrive (const TCHAR* path); /* Change current drive */
-FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */
-FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */
-FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn); /* Get volume label */
-FRESULT f_setlabel (const TCHAR* label); /* Set volume label */
-FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */
-FRESULT f_expand (FIL* fp, FSIZE_t szf, BYTE opt); /* Allocate a contiguous block to the file */
-FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */
-FRESULT f_mkfs (const TCHAR* path, BYTE opt, DWORD au, void* work, UINT len); /* Create a FAT volume */
-FRESULT f_fdisk (BYTE pdrv, const DWORD* szt, void* work); /* Divide a physical drive into some partitions */
-FRESULT f_setcp (WORD cp); /* Set current code page */
-int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */
-int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */
-int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */
-TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */
-
-#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize))
-#define f_error(fp) ((fp)->err)
-#define f_tell(fp) ((fp)->fptr)
-#define f_size(fp) ((fp)->obj.objsize)
-#define f_rewind(fp) f_lseek((fp), 0)
-#define f_rewinddir(dp) f_readdir((dp), 0)
-#define f_rmdir(path) f_unlink(path)
-#define f_unmount(path) f_mount(NULL, path, 0)
-
-#ifndef EOF
-#define EOF (-1)
-#endif
-
-
-
-
-/*--------------------------------------------------------------*/
-/* Additional user defined functions */
-
-/* RTC function */
-#if !FF_FS_READONLY && !FF_FS_NORTC
-DWORD get_fattime (void);
-#endif
-
-/* LFN support functions */
-#if FF_USE_LFN >= 1 /* Code conversion (defined in unicode.c) */
-WCHAR ff_oem2uni (WCHAR oem, WORD cp); /* OEM code to Unicode conversion */
-WCHAR ff_uni2oem (DWORD uni, WORD cp); /* Unicode to OEM code conversion */
-DWORD ff_wtoupper (DWORD uni); /* Unicode upper-case conversion */
-#endif
-#if FF_USE_LFN == 3 /* Dynamic memory allocation */
-void* ff_memalloc (UINT msize); /* Allocate memory block */
-void ff_memfree (void* mblock); /* Free memory block */
-#endif
-
-/* Sync functions */
-#if FF_FS_REENTRANT
-int ff_cre_syncobj (BYTE vol, FF_SYNC_t* sobj); /* Create a sync object */
-int ff_req_grant (FF_SYNC_t sobj); /* Lock sync object */
-void ff_rel_grant (FF_SYNC_t sobj); /* Unlock sync object */
-int ff_del_syncobj (FF_SYNC_t sobj); /* Delete a sync object */
-#endif
-
-
-
-
-/*--------------------------------------------------------------*/
-/* Flags and offset address */
-
-
-/* File access mode and open method flags (3rd argument of f_open) */
-#define FA_READ 0x01
-#define FA_WRITE 0x02
-#define FA_OPEN_EXISTING 0x00
-#define FA_CREATE_NEW 0x04
-#define FA_CREATE_ALWAYS 0x08
-#define FA_OPEN_ALWAYS 0x10
-#define FA_OPEN_APPEND 0x30
-
-/* Fast seek controls (2nd argument of f_lseek) */
-#define CREATE_LINKMAP ((FSIZE_t)0 - 1)
-
-/* Format options (2nd argument of f_mkfs) */
-#define FM_FAT 0x01
-#define FM_FAT32 0x02
-#define FM_EXFAT 0x04
-#define FM_ANY 0x07
-#define FM_SFD 0x08
-
-/* Filesystem type (FATFS.fs_type) */
-#define FS_FAT12 1
-#define FS_FAT16 2
-#define FS_FAT32 3
-#define FS_EXFAT 4
-
-/* File attribute bits for directory entry (FILINFO.fattrib) */
-#define AM_RDO 0x01 /* Read only */
-#define AM_HID 0x02 /* Hidden */
-#define AM_SYS 0x04 /* System */
-#define AM_DIR 0x10 /* Directory */
-#define AM_ARC 0x20 /* Archive */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* FF_DEFINED */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/109c32565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/109c32565243001d18b399c1eb9b3628
deleted file mode 100644
index 46b7045..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/109c32565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,60 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm.h
-*
-* @addtogroup r5_specific Cortex R5 Processor Specific Include Files
-*
-* The xpseudo_asm.h includes xreg_cortexr5.h and xpseudo_asm_gcc.h.
-*
-* The xreg_cortexr5.h file contains definitions for inline assembler code.
-* It provides inline definitions for Cortex R5 GPRs, SPRs,co-processor
-* registers and Debug register
-*
-* The xpseudo_asm_gcc.h contains the definitions for the most often used
-* inline assembler instructions, available as macros. These can be very
-* useful for tasks such as setting or getting special purpose registers,
-* synchronization,or cache manipulation. These inline assembler instructions
-* can be used from drivers and user applications written in C.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.00 pkp 02/10/14 Initial version
-* 6.2 mus 01/27/17 Updated to support IAR compiler
-* 7.3 dp 06/25/20 Initial version for armclang
-*
-*
-******************************************************************************/
-#ifndef XPSEUDO_ASM_H /* prevent circular inclusions */
-#define XPSEUDO_ASM_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xreg_cortexr5.h"
-#if defined (__clang__)
-#include "xpseudo_asm_armclang.h"
-#elif defined (__GNUC__)
-#include "xpseudo_asm_gcc.h"
-#elif defined (__ICCARM__)
-#include "xpseudo_asm_iccarm.h"
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XPSEUDO_ASM_H */
-/**
-* @} End of "addtogroup r5_specific".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/11dcce565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/11dcce565243001d18b399c1eb9b3628
deleted file mode 100644
index 6719ab0..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/11dcce565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,62 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file vectors.h
-*
-* This file contains the C level vector prototypes for the ARM Cortex A9 core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 10/20/10 Initial version, moved over from bsp area
-* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#ifndef _VECTORS_H_
-#define _VECTORS_H_
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void FIQInterrupt(void);
-void IRQInterrupt(void);
-#if !defined (__aarch64__)
-void SWInterrupt(void);
-void DataAbortInterrupt(void);
-void PrefetchAbortInterrupt(void);
-void UndefinedException(void);
-#else
-void SynchronousInterrupt(void);
-void SErrorInterrupt(void);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* protection macro */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/40fb12555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/40fb12555243001d18b399c1eb9b3628
deleted file mode 100644
index 2bedeb1..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/40fb12555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,85 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file usleep.c
-*
-* This function provides a microsecond delay using the Generic counter register in
-* the ARM Cortex A53 MPcore.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 5.4 pkp 28/01/16 Modified the usleep API to configure Time Stamp
-* generator only when disable using frequency from
-* xparamters.h instead of hardcoding
-* 5.05 pkp 13/04/16 Modified usleep routine to call XTime_StartTimer
-* which enables timer only when it is disabled and
-* read counter value directly from register instead
-* of calling XTime_GetTime for optimization
-* 6.0 mus 08/18/16 Updated the usleep signature. Fix for CR#956899
-* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
-* implementation. Now sleep routines will use Timer
-* specified by the user (i.e. Global timer/TTC timer)
-* 7.5 dp 01/05/21 Updated COUNTS_PER_USECOND macros to round it off to
-* nearest possible value so that delta error in time
-* calculations can be minimized.
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "sleep.h"
-#include "xtime_l.h"
-#include "xparameters.h"
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#include "xil_sleeptimer.h"
-#endif
-
-/**************************** Constant Definitions ************************/
-
-/* Global Timer is always clocked at half of the CPU frequency */
-#define COUNTS_PER_USECOND ((COUNTS_PER_SECOND + 500000)/1000000)
-
-/*****************************************************************************/
-/**
-*
-* This API gives a delay in microseconds
-*
-* @param useconds requested
-*
-* @return 0.
-*
-* @note None.
-*
-****************************************************************************/
-int usleep_A53(unsigned long useconds)
-{
-
-#if defined (SLEEP_TIMER_BASEADDR)
- Xil_SleepTTCCommon(useconds, COUNTS_PER_USECOND);
-#else
- XTime tEnd, tCur;
- /* Start global timer counter, it will only be enabled if it is disabled */
- XTime_StartTimer();
-
- tCur = arch_counter_get_cntvct();
- tEnd = tCur + (((XTime) useconds) * COUNTS_PER_USECOND);
- do
- {
- tCur = arch_counter_get_cntvct();
- } while (tCur < tEnd);
-#endif
-
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/42c2d1565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/42c2d1565243001d18b399c1eb9b3628
deleted file mode 100644
index 25fc262..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/42c2d1565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,132 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xil-crt0.S
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 10/20/09 Initial version
-* 3.05a sdm 02/02/12 Added code for profiling
-* 3.06a sgd 05/16/12 Added global constructors and cleanup code
-* Uart initialization based on compiler flag
-* 3.07a sgd 07/05/12 Updated with reset and start Global Timer
-* 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
-* 4.2 pkp 08/04/14 Removed PEEP board related code which contained
-* initialization of uart smc nor and sram
-* 5.3 pkp 10/07/15 Added support for OpenAMP by not initializing global
-* timer when USE_AMP flag is defined
-* 6.6 srm 10/18/17 Added timer configuration using XTime_StartTTCTimer API.
-* Now the TTC instance as specified by the user will be
-* started.
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#include "bspconfig.h"
-
- .file "xil-crt0.S"
- .section ".got2","aw"
- .align 2
-
- .text
-.Lsbss_start:
- .long __sbss_start
-
-.Lsbss_end:
- .long __sbss_end
-
-.Lbss_start:
- .long __bss_start
-
-.Lbss_end:
- .long __bss_end
-
-.Lstack:
- .long __stack
-
-
- .globl _start
-_start:
- bl __cpu_init /* Initialize the CPU first (BSP provides this) */
-
- mov r0, #0
-
- /* clear sbss */
- ldr r1,.Lsbss_start /* calculate beginning of the SBSS */
- ldr r2,.Lsbss_end /* calculate end of the SBSS */
-
-.Lloop_sbss:
- cmp r1,r2
- bge .Lenclsbss /* If no SBSS, no clearing required */
- str r0, [r1], #4
- b .Lloop_sbss
-
-.Lenclsbss:
- /* clear bss */
- ldr r1,.Lbss_start /* calculate beginning of the BSS */
- ldr r2,.Lbss_end /* calculate end of the BSS */
-
-.Lloop_bss:
- cmp r1,r2
- bge .Lenclbss /* If no BSS, no clearing required */
- str r0, [r1], #4
- b .Lloop_bss
-
-.Lenclbss:
-
- /* set stack pointer */
- ldr r13,.Lstack /* stack address */
-
- /* Reset and start Global Timer */
- mov r0, #0x0
- mov r1, #0x0
-
- /* Reset and start Triple Timer Counter */
- #if defined SLEEP_TIMER_BASEADDR
- bl XTime_StartTTCTimer
- #endif
-
-#if USE_AMP != 1
- bl XTime_SetTime
-#endif
-
-#ifdef PROFILING /* defined in Makefile */
- /* Setup profiling stuff */
- bl _profile_init
-#endif /* PROFILING */
-
- /* run global constructors */
- bl __libc_init_array
-
- /* make sure argc and argv are valid */
- mov r0, #0
- mov r1, #0
-
- /* Let her rip */
- bl main
-
- /* Cleanup global constructors */
- bl __libc_fini_array
-
-#ifdef PROFILING
- /* Cleanup profiling stuff */
- bl _profile_clean
-#endif /* PROFILING */
-
- /* All done */
- bl exit
-
-.Lexit: /* should never get here */
- b .Lexit
-
-.Lstart:
- .size _start,.Lstart-_start
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/701622555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/701622555243001d18b399c1eb9b3628
deleted file mode 100644
index 61da4bc..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/701622555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,7 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/* Stub call for argv veneer */
-void __ARM_argv_veneer(void) {};
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/80cd10545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/80cd10545243001d18b399c1eb9b3628
deleted file mode 100644
index 72c8803..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/80cd10545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# Usage: To re-create this platform project launch xsct with below options.
-# xsct /home/dylan/workspace/phased_array_platform/platform.tcl
-#
-# OR launch xsct and run below command.
-# source /home/dylan/workspace/phased_array_platform/platform.tcl
-#
-# To create the platform in a different location, modify the -out option of "platform create" command.
-# -out option specifies the output directory of the platform project.
-
-platform create -name {phased_array_platform}\
--hw {/home/dylan/Documents/FPGA/phased_array/design_1_wrapper.xsa}\
--proc {ps7_cortexa9_0} -os {standalone} -out {/home/dylan/workspace}
-
-platform write
-platform generate -domains
-platform active {phased_array_platform}
-platform generate
-platform generate
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/82395e595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/82395e595243001d18b399c1eb9b3628
deleted file mode 100644
index c895633..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/82395e595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,69 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2012 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file microblaze_exceptions_i.h
-*
-* This header file contains defines for structures used by the microblaze
-* hardware exception handler.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Date Changes
-* ----- -------- -----------------------------------------------
-* 1.00a 06/24/04 First release
-*
-*
-******************************************************************************/
-
-#ifndef MICROBLAZE_EXCEPTIONS_I_H /* prevent circular inclusions */
-#define MICROBLAZE_EXCEPTIONS_I_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_exception.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *@cond nocomments
- */
-
-typedef struct
-{
- Xil_ExceptionHandler Handler;
- void *CallBackRef;
-} MB_ExceptionVectorTableEntry;
-
-/* Exception IDs */
-#define XEXC_ID_FSL 0U
-#define XEXC_ID_UNALIGNED_ACCESS 1U
-#define XEXC_ID_ILLEGAL_OPCODE 2U
-#define XEXC_ID_M_AXI_I_EXCEPTION 3U
-#define XEXC_ID_IPLB_EXCEPTION 3U
-#define XEXC_ID_M_AXI_D_EXCEPTION 4U
-#define XEXC_ID_DPLB_EXCEPTION 4U
-#define XEXC_ID_DIV_BY_ZERO 5U
-#define XEXC_ID_FPU 6U
-#define XEXC_ID_STACK_VIOLATION 7U
-#define XEXC_ID_MMU 7U
-
-/**
- *@endcond
- */
-
-void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr);
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* end of protection macro */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/90cec9525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/90cec9525243001d18b399c1eb9b3628
deleted file mode 100644
index 1d18bfb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/90cec9525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,203 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_types.h
-*
-* @addtogroup common_types Basic Data types for Xilinx® Software IP
-*
-* The xil_types.h file contains basic types for Xilinx software IP. These data types
-* are applicable for all processors supported by Xilinx.
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 First release
-* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
-* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
-* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
-* Define LONG and ULONG datatypes and mask values
-* 7.00 mus 01/07/19 Add cpp extern macro
-* 7.1 aru 08/19/19 Shift the value in UPPER_32_BITS only if it
-* is 64-bit processor
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-#ifndef XIL_TYPES_H /* prevent circular inclusions */
-#define XIL_TYPES_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include
-#include
-
-/************************** Constant Definitions *****************************/
-
-#ifndef TRUE
-# define TRUE 1U
-#endif
-
-#ifndef FALSE
-# define FALSE 0U
-#endif
-
-#ifndef NULL
-#define NULL 0U
-#endif
-
-#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be
- assigend to "IsReady" member of driver
- instance to indicate that driver
- instance is initialized and ready to use. */
-#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to
- "IsStarted" member of driver instance
- to indicate that driver instance is
- started and it can be enabled. */
-
-/* @name New types
- * New simple types.
- * @{
- */
-#ifndef __KERNEL__
-#ifndef XBASIC_TYPES_H
-/*
- * guarded against xbasic_types.h.
- */
-typedef uint8_t u8;
-typedef uint16_t u16;
-typedef uint32_t u32;
-/** @}*/
-#define __XUINT64__
-typedef struct
-{
- u32 Upper;
- u32 Lower;
-} Xuint64;
-
-
-/*****************************************************************************/
-/**
-* @brief Return the most significant half of the 64 bit data type.
-*
-* @param x is the 64 bit word.
-*
-* @return The upper 32 bits of the 64 bit word.
-*
-******************************************************************************/
-#define XUINT64_MSW(x) ((x).Upper)
-
-/*****************************************************************************/
-/**
-* @brief Return the least significant half of the 64 bit data type.
-*
-* @param x is the 64 bit word.
-*
-* @return The lower 32 bits of the 64 bit word.
-*
-******************************************************************************/
-#define XUINT64_LSW(x) ((x).Lower)
-
-#endif /* XBASIC_TYPES_H */
-
-/*
- * xbasic_types.h does not typedef s* or u64
- */
-/** @{ */
-typedef char char8;
-typedef int8_t s8;
-typedef int16_t s16;
-typedef int32_t s32;
-typedef int64_t s64;
-typedef uint64_t u64;
-typedef int sint32;
-
-typedef intptr_t INTPTR;
-typedef uintptr_t UINTPTR;
-typedef ptrdiff_t PTRDIFF;
-/** @}*/
-#if !defined(LONG) || !defined(ULONG)
-typedef long LONG;
-typedef unsigned long ULONG;
-#endif
-
-#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
-#define ULONG64_LO_MASK ~ULONG64_HI_MASK
-
-#else
-#include
-#endif
-
-/** @{ */
-/**
- * This data type defines an interrupt handler for a device.
- * The argument points to the instance of the component
- */
-typedef void (*XInterruptHandler) (void *InstancePtr);
-
-/**
- * This data type defines an exception handler for a processor.
- * The argument points to the instance of the component
- */
-typedef void (*XExceptionHandler) (void *InstancePtr);
-
-/**
- * @brief Returns 32-63 bits of a number.
- * @param n : Number being accessed.
- * @return Bits 32-63 of number.
- *
- * @note A basic shift-right of a 64- or 32-bit quantity.
- * Use this to suppress the "right shift count >= width of type"
- * warning when that quantity is 32-bits.
- */
-#if defined (__aarch64__) || defined (__arch64__)
-#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
-#else
-#define UPPER_32_BITS(n) 0U
-#endif
-/**
- * @brief Returns 0-31 bits of a number
- * @param n : Number being accessed.
- * @return Bits 0-31 of number
- */
-#define LOWER_32_BITS(n) ((u32)(n))
-
-
-
-
-/************************** Constant Definitions *****************************/
-
-#ifndef TRUE
-#define TRUE 1U
-#endif
-
-#ifndef FALSE
-#define FALSE 0U
-#endif
-
-#ifndef NULL
-#define NULL 0U
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
- *@endcond
- */
-/**
-* @} End of "addtogroup common_types".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/a2217b575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/a2217b575243001d18b399c1eb9b3628
deleted file mode 100644
index 75cd6f6..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/90/a2217b575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,105 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.h
-*
-* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions
-*
-* Cache functions provide access to cache related operations such as flush
-* and invalidate for instruction and data caches. It gives option to perform
-* the cache operations on a single cacheline, a range of memory and an entire
-* cache.
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 01/29/10 First release
-* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
-* APIs.
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-;* MODIFICATION HISTORY:
-;*
-;* Ver Who Date Changes
-;* ----- ---- -------- ---------------------------------------------------
-;* 7.3 dp 06/25/20 Initial version for armclang
-;*
-;*
-;* @note
-;*
-;* None.
-;*
-;******************************************************************************/
-#include "xparameters.h"
-#include "bspconfig.h"
-
- IMPORT |Image$$BSS_SECTION$$Base|
- IMPORT Xil_InitializeExistingMPURegConfig
- EXPORT _startup
- IMPORT __cpu_init
- IMPORT __main
-#ifdef SLEEP_TIMER_BASEADDR
- IMPORT XTime_StartTTCTimer
-#endif
- AREA |.text|, CODE
- REQUIRE8 {TRUE}
- PRESERVE8 {TRUE}
- ENTRY
-
-_startup
- bl __cpu_init ;Initialize the CPU first (BSP provides this)
- ;configure the timer if TTC is present
-#ifdef SLEEP_TIMER_BASEADDR
- bl XTime_StartTTCTimer
-#endif
- bl Xil_InitializeExistingMPURegConfig ;/* Initialize MPU config */
- ;make sure argc and argv are valid
- mov r0, #0
- mov r1, #0
-
-#ifdef XCLOCKING
- bl Xil_ClockInit
-#endif
- bl __main ;Jump to main C code
-
- bl exit
-
-exit ;should never get here
- b exit
-
- END
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/91/116e10565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/91/116e10565243001d18b399c1eb9b3628
deleted file mode 100644
index 9fe1388..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/91/116e10565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,56 +0,0 @@
-;/******************************************************************************
-;* Copyright (c) 2020 - 2021 Xilinx, Inc. All rights reserved.
-;* SPDX-License-Identifier: MIT
-;******************************************************************************/
-;/*****************************************************************************/
-;/**
-;* @file cpu_init.S
-;*
-;* This file contains CPU specific initialization. Invoked from main CRT
-;*
-;*
-;* MODIFICATION HISTORY:
-;*
-;* Ver Who Date Changes
-;* ----- ------- -------- ---------------------------------------------------
-;* 7.3 dp 06/25/20 Initial version for armclang
-;*
-;*
-;*
-;* @note
-;*
-;* None.
-;*
-******************************************************************************/
-
- EXPORT __cpu_init
-
- AREA |.text|, CODE
- REQUIRE8 {TRUE}
- PRESERVE8 {TRUE}
- ENTRY
-
-__cpu_init
-
-;Clear cp15 regs with unknown reset values
- mov r0, #0x0
- mcr p15, 0, r0, c5, c0, 0 ;DFSR
- mcr p15, 0, r0, c5, c0, 1 ;IFSR
- mcr p15, 0, r0, c6, c0, 0 ;DFAR
- mcr p15, 0, r0, c6, c0, 2 ;IFAR
- mcr p15, 0, r0, c9, c13, 2 ;PMXEVCNTR
- mcr p15, 0, r0, c13, c0, 2 ;TPIDRURW
- mcr p15, 0, r0, c13, c0, 3 ;TPIDRURO
-
-
-;Reset and start Cycle Counter
- mov r2, #0x80000000 ;clear overflow
- mcr p15, 0, r2, c9, c12, 3
- mov r2, #0xd ;D, C, E
- mcr p15, 0, r2, c9, c12, 0
- mov r2, #0x80000000 ;enable cycle counter
- mcr p15, 0, r2, c9, c12, 1
-
- bx lr
-
- END
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/91/729a71595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/91/729a71595243001d18b399c1eb9b3628
deleted file mode 100644
index 5b2d4ed..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/91/729a71595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,83 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2006 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-* File : microblaze_update_icache.s
-* Date : 2003, September 24
-* Company: Xilinx
-* Group : Emerging Software Technologies
-*
-* Summary:
-* Update icache on the microblaze.
-* Takes in three parameters
-* r5 : Cache Tag Line
-* r6 : Cache Data
-* r7 : Lock/Valid information
-* Bit 30 is Lock [ 1 indicates locked ]
-* Bit 31 is Valid [ 1 indicates valid ]
-*
-* --------------------------------------------------------------
-* | Lock | Valid | Effect
-* --------------------------------------------------------------
-* | 0 | 0 | Invalidate Cache
-* | 0 | 1 | Valid, but unlocked cacheline
-* | 1 | 0 | Invalidate Cache, No effect of lock
-* | 1 | 1 | Valid cache. Locked to a
-* | | | particular address
-* --------------------------------------------------------------
-*
-*
-**********************************************************************************/
-#include "xparameters.h"
-
-#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
-#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
-#endif
-
- .text
- .globl microblaze_update_icache
- .ent microblaze_update_icache
- .align 2
-microblaze_update_icache:
-#if (XPAR_MICROBLAZE_USE_ICACHE==1) && (XPAR_MICROBLAZE_ALLOW_ICACHE_WR==1)
-
-#if XPAR_MICROBLAZE_ICACHE_LINE_LEN == 1
-
-/* Read the MSR register into a temp register */
- mfs r18, rmsr
-
-/* Clear the icache enable bit to disable the cache
- Register r10,r18 are volatile registers and hence do not need to be saved before use */
- andi r10, r18, ~32
- mts rmsr, r10
-
-/* Update the lock and valid info */
- andi r5, r5, 0xfffffffc
- or r5, r5, r7
-
-/* Update icache */
- wic r5, r6
-
-/* Return */
- rtsd r15, 8
- mts rmsr, r18
-
-#else
-
- /* The only valid usage of this routine for larger cache line lengths is to invalidate an instruction cache line
- So call microblaze_init_icache_range appropriately to do the job */
-
- brid microblaze_init_icache_range
- addik r6, r0, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4)
-
- /* We don't have a return instruction here. This is tail call optimization :) */
-
-#endif /* XPAR_MICROBLAZE_ICACHE_LINE_LEN == 1 */
-
-#else
- rtsd r15, 8
- nop
-#endif
- .end microblaze_update_icache
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/91/803274595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/91/803274595243001d18b399c1eb9b3628
deleted file mode 100644
index a84c6a4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/91/803274595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,68 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2006 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file pvr.c
-*
-* This header file contains defines for structures used by the microblaze
-* PVR routines
-*
-******************************************************************************/
-#include "xparameters.h"
-#include "pvr.h"
-#include
-
-/* Definitions */
-
-/****************************************************************************/
-/**
-* @brief Populate the PVR data structure to which pvr points, with the
-* values of the hardware PVR registers.
-*
-* @param pvr- address of PVR data structure to be populated
-*
-* @return 0 - SUCCESS
-* -1 - FAILURE
-*
-****************************************************************************/
-int microblaze_get_pvr (pvr_t *pvr)
-{
- if (!pvr)
- return -1;
-
- bzero ((void*)pvr, sizeof (pvr_t));
-
-#ifdef MICROBLAZE_PVR_NONE
- return -1;
-#else
- getpvr (0, pvr->pvr[0]);
-#endif /* MICROBLAZE_PVR_NONE */
-
-#ifdef MICROBLAZE_PVR_FULL
- getpvr (1, pvr->pvr[1]);
- getpvr (2, pvr->pvr[2]);
- getpvr (3, pvr->pvr[3]);
-
- getpvr (4, pvr->pvr[4]);
- getpvr (5, pvr->pvr[5]);
- getpvr (6, pvr->pvr[6]);
- getpvr (7, pvr->pvr[7]);
-
- getpvr (8, pvr->pvr[8]);
- getpvr (9, pvr->pvr[9]);
- getpvr (10, pvr->pvr[10]);
- getpvr (11, pvr->pvr[11]);
-
-/* getpvr (12, pvr->pvr[12]); */
-/* getpvr (13, pvr->pvr[13]); */
-/* getpvr (14, pvr->pvr[14]); */
-/* getpvr (15, pvr->pvr[15]); */
-
-#endif /* MICROBLAZE_PVR_FULL */
-
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/91/c0afa6555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/91/c0afa6555243001d18b399c1eb9b3628
deleted file mode 100644
index 0dc034c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/91/c0afa6555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,28 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/*
- * This is the default implementation of the "clock" function of the
- * standard library. It can be replaced with a system-specific
- * implementation.
- *
- * The "clock" function should return the processor time used by the
- * program from some implementation-defined start time. The value
- * should be such that if divided by the macro CLOCKS_PER_SEC the
- * result should yield the time in seconds.
- *
- * The value "0" means that the processor time is not
- * available.
- *
- */
-
-#include
-
-
-clock_t (clock)(void)
-{
- return (0);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/92/12123d585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/92/12123d585243001d18b399c1eb9b3628
deleted file mode 100644
index 517deea..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/92/12123d585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,277 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file boot.S
-*
-* @addtogroup a53_32_boot_code Cortex A53 32bit Processor Boot Code
-* @{
-*
boot.S
-* The boot.S file contains a minimal set of code for transferring control from the
-* processor reset location to the start of the application. The boot code performs
-* minimum configuration which is required for an application to run starting from
-* processor reset state of the processor. Below is a sequence illustrating what all
-* configuration is performed before control reaches to main function.
-*
-* 1. Program vector table base for exception handling
-* 2. Invalidate instruction cache, data cache and TLBs
-* 3. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine,
-* abort, system)
-* 4. Program counter frequency
-* 5. Configure MMU with short descriptor translation table format and program
-* base address of translation table
-* 6. Enable data cache, instruction cache and MMU
-* 7. Transfer control to _start which clears BSS sections and runs global
-* constructor before jumping to main application
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 5.4 pkp 09/11/15 Enable I-Cache and D-Cache in the initialization
-* 6.0 pkp 07/25/16 Program the counter frequency
-* 6.4 mus 07/25/17 Set VFP enable bit in FPEXC register, to support
-* hard floating point in BSP
-*
-*
-*
-******************************************************************************/
-
-#include "xparameters.h"
-
-
-.globl MMUTable
-.global _prestart
-.global _boot
-.global __stack
-.global __irq_stack
-.global __supervisor_stack
-.global __abort_stack
-.global __fiq_stack
-.global __undef_stack
-.global _vector_table
-
-.set PSS_L2CC_BASE_ADDR, 0xF8F02000
-.set PSS_SLCR_BASE_ADDR, 0xF8000000
-
-.set RESERVED, 0x0fffff00
-.set TblBase , MMUTable
-.set LRemap, 0xFE00000F /* set the base address of the peripheral block as not shared */
-
-.set CRValMmuCac, 0b01000000000001 /* Enable IDC, and MMU */
-.set counterfreq, XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ
-
-/* Stack Pointer locations for boot code */
-.set Undef_stack, __undef_stack
-.set FIQ_stack, __fiq_stack
-.set Abort_stack, __abort_stack
-.set SPV_stack, __supervisor_stack
-.set IRQ_stack, __irq_stack
-.set SYS_stack, __stack
-
-.set vector_base, _vector_table
-
-.set FPEXC_EN, 0x40000000 /* FPU enable bit, (1 << 30) */
-
-.section .boot,"ax"
-
-/* this initializes the various processor modes */
-
-_prestart:
-_boot:
-
-OKToRun:
- mrc p15, 0, r0, c0, c0, 0 /* Get the revision */
- and r5, r0, #0x00f00000
- and r6, r0, #0x0000000f
- orr r6, r6, r5, lsr #20-4
-
- /* set VBAR to the _vector_table address in linker script */
- ldr r0, =vector_base
- mcr p15, 0, r0, c12, c0, 0
-
- /* Invalidate caches and TLBs */
- mov r0,#0 /* r0 = 0 */
- mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
- mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
- mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */
- bl invalidate_dcache /* invalidate dcache */
-
- /* Disable MMU, if enabled */
- mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */
- bic r0, r0, #0x1 /* clear bit 0 */
- mcr p15, 0, r0, c1, c0, 0 /* write value back */
-
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the irq stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x12 /* IRQ mode */
- msr cpsr, r2
- ldr r13,=IRQ_stack /* IRQ stack pointer */
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the supervisor stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x13 /* supervisor mode */
- msr cpsr, r2
- ldr r13,=SPV_stack /* Supervisor stack pointer */
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the Abort stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x17 /* Abort mode */
- msr cpsr, r2
- ldr r13,=Abort_stack /* Abort stack pointer */
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the FIQ stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x11 /* FIQ mode */
- msr cpsr, r2
- ldr r13,=FIQ_stack /* FIQ stack pointer */
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the Undefine stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x1b /* Undefine mode */
- msr cpsr, r2
- ldr r13,=Undef_stack /* Undefine stack pointer */
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the system stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x1F /* SYS mode */
- msr cpsr, r2
- ldr r13,=SYS_stack /* SYS stack pointer */
-
- /* program the timer counter frequency */
- ldr r0,=counterfreq
- mcr 15,0,r0,c14,c0,0
-
- mov r0,#0
- mcr 15,0,r0,c2,c0,2 /* N = 0 to use ttbr0 */
-
- /* Write to ACTLR */
- mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR */
- orr r0, r0, #(1 << 0) /* Enable access to CPUECTLR */
- orr r0, r0, #(1 << 1)
- mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR */
-
- /* Write to CPUECTLR */
- mrrc p15, 1, r0, r1, c15 /* Read CPUECTLR */
- orr r0, r0, #(0x01 << 6) /* Set SMPEN bit */
- mcrr p15, 1, r0, r1, c15 /* Write CPUECTLR */
-
- /* enable MMU and cache */
- ldr r0,=TblBase /* Load MMU translation table base */
- orr r0, r0, #0x5B /* Outer-cacheable, WB */
- mcr 15, 0, r0, c2, c0, 0 /* TTB0 */
- mov r0,#0x5B
- mcr p15,0,r0,c2,c0,1
- mvn r0,#0 /* Load MMU domains -- all ones=manager */
- mcr p15,0,r0,c3,c0,0
-
- /* Enable mmu, icahce and dcache */
- mrc p15,0,r0,c1,c0,0
- bic r0, r0, #(0x1 << 13)
- orr r0, r0, #(0x1 << 12) /* enable I-cache */
- orr r0, r0, #(0x1 << 2) /* enable D-Cache */
- orr r0, r0, #0x1 /* enable MMU */
- dsb /* dsb allow the MMU to start up */
- mcr p15,0,r0,c1,c0,0 /* Enable cache and MMU */
- isb /* isb flush prefetch buffer */
-
- mov r0, r0
- mrc p15, 0, r1, c1, c0, 2 /* read cp access control register (CACR) into r1 */
- orr r1, r1, #(0xf << 20) /* enable full access for p10 & p11 */
- mcr p15, 0, r1, c1, c0, 2 /* write back into CACR */
-
- /* enable vfp */
- vmrs r1, FPEXC /* read the exception register */
- orr r1,r1, #FPEXC_EN /* set VFP enable bit, leave the others in orig state */
- vmsr FPEXC, r1 /* write back the exception register */
-
- mrc p15,0,r0,c1,c0,0 /* flow prediction enable */
- orr r0, r0, #(0x01 << 11) /* #0x8000 */
- mcr p15,0,r0,c1,c0,0
-
- mrc p15,0,r0,c1,c0,1 /* read Auxiliary Control Register */
- orr r0, r0, #(0x1 << 2) /* enable Dside prefetch */
- orr r0, r0, #(0x1 << 1) /* enable L2 Prefetch hint */
- mcr p15,0,r0,c1,c0,1 /* write Auxiliary Control Register */
-
- mrs r0, cpsr /* get the current PSR */
- bic r0, r0, #0x100 /* enable asynchronous abort exception */
- msr cpsr_xsf, r0
-
-
- b _startup /* jump to C startup code */
- and r0, r0, r0 /* no op */
-
-.Ldone: b .Ldone /* Paranoia: we should never get here */
-
-
-/*
- *************************************************************************
- *
- * invalidate_dcache - invalidate the entire d-cache by set/way
- *
- * Note: for Cortex-A53, there is no cp instruction for invalidating
- * the whole D-cache. Need to invalidate each line.
- *
- *************************************************************************
- */
-invalidate_dcache:
- mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */
- ands r3, r0, #0x7000000
- mov r3, r3, lsr #23 /* cache level value (naturally aligned) */
- beq finished
- mov r10, #0 /* start with level 0 */
-loop1:
- add r2, r10, r10, lsr #1 /* work out 3xcachelevel */
- mov r1, r0, lsr r2 /* bottom 3 bits are the Cache type for this level */
- and r1, r1, #7 /* get those 3 bits alone */
- cmp r1, #2
- blt skip /* no cache or only instruction cache at this level */
- mcr p15, 2, r10, c0, c0, 0 /* write the Cache Size selection register */
- isb /* isb to sync the change to the CacheSizeID reg */
- mrc p15, 1, r1, c0, c0, 0 /* reads current Cache Size ID register */
- and r2, r1, #7 /* extract the line length field */
- add r2, r2, #4 /* add 4 for the line length offset (log2 16 bytes) */
- ldr r4, =0x3ff
- ands r4, r4, r1, lsr #3 /* r4 is the max number on the way size (right aligned) */
- clz r5, r4 /* r5 is the bit position of the way size increment */
- ldr r7, =0x7fff
- ands r7, r7, r1, lsr #13 /* r7 is the max number of the index size (right aligned) */
-loop2:
- mov r9, r4 /* r9 working copy of the max way size (right aligned) */
-loop3:
- orr r11, r10, r9, lsl r5 /* factor in the way number and cache number into r11 */
- orr r11, r11, r7, lsl r2 /* factor in the index number */
- mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */
- subs r9, r9, #1 /* decrement the way number */
- bge loop3
- subs r7, r7, #1 /* decrement the index */
- bge loop2
-skip:
- add r10, r10, #2 /* increment the cache number */
- cmp r3, r10
- bgt loop1
-
-finished:
- mov r10, #0 /* switch back to cache level 0 */
- mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
- dsb
- isb
-
- bx lr
-
-.end
-/**
-* @} End of "addtogroup a53_32_boot_code".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/92/239490595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/92/239490595243001d18b399c1eb9b3628
deleted file mode 100644
index 1b601db..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/92/239490595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,96 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file smc.h
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 11/03/09 Initial release.
-* 4.2 pkp 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
-* as smc.c is removed
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 02/04/02 First release
-* 2.00a jhl 01/13/04 Addition of dual channels and interrupts.
-* 2.11a mta 03/21/07 Updated to new coding style
-* 3.00a sv 11/21/09 Updated to use HAL Processor APIs.
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xgpio.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-
-/******************************************************************************/
-/**
-* Run a self-test on the driver/device. This function does a minimal test
-* in which the data register is read. It only does a read without any kind
-* of test because the hardware has been parameterized such that it may be only
-* an input such that the state of the inputs won't be known.
-*
-* All other hardware features of the device are not guaranteed to be in the
-* hardware since they are parameterizable.
-*
-*
-* @param InstancePtr is a pointer to the XGpio instance to be worked on.
-* This parameter must have been previously initialized with
-* XGpio_Initialize().
-*
-* @return XST_SUCCESS always. If the GPIO device was not present in the
-* hardware a bus error could be generated. Other indicators of a
-* bus error, such as registers in bridges or buses, may be
-* necessary to determine if this function caused a bus error.
-*
-* @note None.
-*
-******************************************************************************/
-int XGpio_SelfTest(XGpio * InstancePtr)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read from the data register of channel 1 which is always guaranteed
- * to be in the hardware device. Since the data may be configured as
- * all inputs, there is not way to guarantee the value read so don't
- * test it.
- */
- (void) XGpio_DiscreteRead(InstancePtr, 1);
-
- return (XST_SUCCESS);
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/92/f0db3e575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/92/f0db3e575243001d18b399c1eb9b3628
deleted file mode 100644
index 62a5b4d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/92/f0db3e575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1521 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file main.c
-*
-* The main file for the First Stage Boot Loader (FSBL).
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a jz 06/04/11 Initial release
-* 2.00a mb 25/05/12 standalone based FSBL
-* 3.00a np/mb 08/03/12 Added call to FSBL user hook - before handoff.
-* DDR ECC initialization added
-* fsbl print with verbose added
-* Performance measurement added
-* Flushed the UART Tx buffer
-* Added the performance time for ECC DDR init
-* Added clearing of ECC Error Code
-* Added the watchdog timer value
-* 4.00a sgd 02/28/13 Code Cleanup
-* Fix for CR#681014 - ECC init in FSBL should not
-* call fabric_init()
-* Fix for CR#689077 - FSBL hangs at Handoff clearing the
-* TX UART buffer when using UART0
-* instead of UART1
-* Fix for CR#694038 - FSBL debug logs always prints 14.3
-* as the Revision number - this is
-* incorrect
-* Fix for CR#694039 - FSBL prints "unsupported silicon
-* version for v3.0" 3.0 Silicon
-* Fix for CR#699475 - FSBL functionality is broken and
-* its not able to boot in QSPI/NAND
-* bootmode
-* Removed DDR initialization check
-* Removed DDR ECC initialization code
-* Modified hand off address check to 1MB
-* Added RSA authentication support
-* Watchdog disabled for AES E-Fuse encryption
-* 5.00a sgd 05/17/13 Fallback support for E-Fuse encryption
-* Fix for CR#708728 - Issues seen while making HP
-* interconnect 32 bit wide
-* 6.00a kc 07/30/13 Fix for CR#708316 - PS7_init.tcl file should have
-* Error mechanism for all mask_poll
-* Fix for CR#691150 - ps7_init does not check for
-* peripheral initialization failures
-* or timeout on polls
-* Fix for CR#724165 - Partition Header used by FSBL is
-* not authenticated
-* Fix for CR#724166 - FSBL doesn’t use PPK authenticated
-* by Boot ROM for authenticating
-* the Partition images
-* Fix for CR#722979 - Provide customer-friendly
-* changelogs in FSBL
-* Fix for CR#732865 - Backward compatibility for ps7_init
-* function
-* 7.00a kc 10/18/13 Integrated SD/MMC driver
-* 8.00a kc 02/20/14 Fix for CR#775631 - FSBL: FsblGetGlobalTimer()
-* is not proper
-* 9.00a kc 04/16/14 Fix for CR#724166 - SetPpk() will fail on secure
-* fallback unless FSBL* and FSBL
-* are identical in length
-* 10.00a kc 07/24/14 Fix for CR#809336 - Minor code cleanup
-* kc 08/27/14 Fix for CR#820356 - FSBL compilation fails with
-* IAR compiler
-* 11.00a kv 10/08/14 Fix for CR#826030 - LinearBootDeviceFlag should
-* be initialized to 0 in IO mode
-* case
-* 15.00a gan 07/21/16 Fix for CR# 953654 -(2016.3)FSBL -
-* In pcap.c/pcap.h/main.c,
-* Fabric Initialization sequence
-* is modified to check the PL power
-* before sequence starts and checking
-* INIT_B reset status twice in case
-* of failure.
-* 16.00a bsv 03/26/18 Fix for CR# 996973 Add code under JTAG_ENABLE_LEVEL_SHIFTERS macro
-* to enable level shifters in jtag boot mode.
-*
-*
-* @note
-* FSBL runs from OCM, Based on the boot mode selected, FSBL will copy
-* the partitions from the flash device. If the partition is bitstream then
-* the bitstream is programmed in the Fabric and for an partition that is
-* an application , FSBL will copy the application into DDR and does a
-* handoff.The application should not be starting at the OCM address,
-* FSBL does not remap the DDR. Application should use DDR starting from 1MB
-*
-* FSBL can be stitched along with bitstream and application using bootgen
-*
-* Refer to fsbl.h file for details on the compilation flags supported in FSBL
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "fsbl.h"
-#include "qspi.h"
-#include "nand.h"
-#include "nor.h"
-#include "sd.h"
-#include "pcap.h"
-#include "image_mover.h"
-#include "xparameters.h"
-#include "xil_cache.h"
-#include "xil_exception.h"
-#include "xstatus.h"
-#include "fsbl_hooks.h"
-#include "xtime_l.h"
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-#include "xwdtps.h"
-#endif
-
-#ifdef STDOUT_BASEADDRESS
-#ifdef XPAR_XUARTPS_0_BASEADDR
-#include "xuartps_hw.h"
-#endif
-#endif
-
-#ifdef RSA_SUPPORT
-#include "rsa.h"
-#endif
-
-/************************** Constant Definitions *****************************/
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-#define WDT_DEVICE_ID XPAR_XWDTPS_0_DEVICE_ID
-#define WDT_EXPIRE_TIME 100
-#define WDT_CRV_SHIFT 12
-#endif
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-XWdtPs Watchdog; /* Instance of WatchDog Timer */
-#endif
-/************************** Function Prototypes ******************************/
-extern int ps7_init();
-extern char* getPS7MessageInfo(unsigned key);
-#ifdef PS7_POST_CONFIG
-extern int ps7_post_config();
-#endif
-
-static void Update_MultiBootRegister(void);
-/* Exception handlers */
-static void RegisterHandlers(void);
-static void Undef_Handler (void);
-static void SVC_Handler (void);
-static void PreFetch_Abort_Handler (void);
-static void Data_Abort_Handler (void);
-static void IRQ_Handler (void);
-static void FIQ_Handler (void);
-
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-int InitWatchDog(void);
-u32 ConvertTime_WdtCounter(u32 seconds);
-void CheckWDTReset(void);
-#endif
-
-u32 NextValidImageCheck(void);
-
-u32 DDRInitCheck(void);
-
-/************************** Variable Definitions *****************************/
-/*
- * Base Address for the Read Functionality for Image Processing
- */
-u32 FlashReadBaseAddress = 0;
-/*
- * Silicon Version
- */
-u32 Silicon_Version;
-
-/*
- * Boot Device flag
- */
-u8 LinearBootDeviceFlag=0;
-
-u32 PcapCtrlRegVal;
-
-u8 SystemInitFlag;
-
-extern ImageMoverType MoveImage;
-extern XDcfg *DcfgInstPtr;
-extern u8 BitstreamFlag;
-#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
-extern u32 QspiFlashSize;
-#endif
-/*****************************************************************************/
-/**
-*
-* This is the main function for the FSBL ROM code.
-*
-*
-* @param None.
-*
-* @return
-* - XST_SUCCESS to indicate success
-* - XST_FAILURE.to indicate failure
-*
-* @note
-*
-****************************************************************************/
-int main(void)
-{
- u32 BootModeRegister = 0;
- u32 HandoffAddress = 0;
- u32 Status = XST_SUCCESS;
- u32 RegVal;
- /*
- * PCW initialization for MIO,PLL,CLK and DDR
- */
- Status = ps7_init();
- if (Status != FSBL_PS7_INIT_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"PS7_INIT_FAIL : %s\r\n",
- getPS7MessageInfo(Status));
- OutputStatus(PS7_INIT_FAIL);
- /*
- * Calling FsblHookFallback instead of Fallback
- * since, devcfg driver is not yet initialized
- */
- FsblHookFallback();
- }
-
- /*
- * Unlock SLCR for SLCR register write
- */
- SlcrUnlock();
-
- /* If Performance measurement is required
- * then read the Global Timer value , Please note that the
- * time taken for mio, clock and ddr initialisation
- * done in the ps7_init function is not accounted in the FSBL
- *
- */
-#ifdef FSBL_PERF
- XTime tCur = 0;
- FsblGetGlobalTime(&tCur);
-#endif
-
- /*
- * Flush the Caches
- */
- Xil_DCacheFlush();
-
- /*
- * Disable Data Cache
- */
- Xil_DCacheDisable();
-
- /*
- * Register the Exception handlers
- */
- RegisterHandlers();
-
- /*
- * Print the FSBL Banner
- */
- fsbl_printf(DEBUG_GENERAL,"\n\rXilinx First Stage Boot Loader \n\r");
- fsbl_printf(DEBUG_GENERAL,"Release %d.%d %s-%s\r\n",
- SDK_RELEASE_YEAR, SDK_RELEASE_QUARTER,
- __DATE__,__TIME__);
-
-#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR
-
- /*
- * DDR Read/write test
- */
- Status = DDRInitCheck();
- if (Status == XST_FAILURE) {
- fsbl_printf(DEBUG_GENERAL,"DDR_INIT_FAIL \r\n");
- /* Error Handling here */
- OutputStatus(DDR_INIT_FAIL);
- /*
- * Calling FsblHookFallback instead of Fallback
- * since, devcfg driver is not yet initialized
- */
- FsblHookFallback();
- }
-
-
- /*
- * PCAP initialization
- */
- Status = InitPcap();
- if (Status == XST_FAILURE) {
- fsbl_printf(DEBUG_GENERAL,"PCAP_INIT_FAIL \n\r");
- OutputStatus(PCAP_INIT_FAIL);
- /*
- * Calling FsblHookFallback instead of Fallback
- * since, devcfg driver is not yet initialized
- */
- FsblHookFallback();
- }
-
- fsbl_printf(DEBUG_INFO,"Devcfg driver initialized \r\n");
-
- /*
- * Get the Silicon Version
- */
- GetSiliconVersion();
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
- /*
- * Check if WDT Reset has occurred or not
- */
- CheckWDTReset();
-
- /*
- * Initialize the Watchdog Timer so that it is ready to use
- */
- Status = InitWatchDog();
- if (Status == XST_FAILURE) {
- fsbl_printf(DEBUG_GENERAL,"WATCHDOG_INIT_FAIL \n\r");
- OutputStatus(WDT_INIT_FAIL);
- FsblFallback();
- }
- fsbl_printf(DEBUG_INFO,"Watchdog driver initialized \r\n");
-#endif
-
- /*
- * Get PCAP controller settings
- */
- PcapCtrlRegVal = XDcfg_GetControlRegister(DcfgInstPtr);
-
- /*
- * Check for AES source key
- */
- if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
- /*
- * For E-Fuse AES encryption Watch dog Timer disabled and
- * User not allowed to do system reset
- */
-#ifdef XPAR_XWDTPS_0_BASEADDR
- fsbl_printf(DEBUG_INFO,"Watchdog Timer Disabled\r\n");
- XWdtPs_Stop(&Watchdog);
-#endif
- fsbl_printf(DEBUG_INFO,"User not allowed to do "
- "any system resets\r\n");
- }
-
- /*
- * Store FSBL run state in Reboot Status Register
- */
- MarkFSBLIn();
-
- /*
- * Read bootmode register
- */
- BootModeRegister = Xil_In32(BOOT_MODE_REG);
- BootModeRegister &= BOOT_MODES_MASK;
-
- /*
- * QSPI BOOT MODE
- */
-#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
-
-#ifdef MMC_SUPPORT
- /*
- * To support MMC boot
- * QSPI boot mode detection ignored
- */
- if (BootModeRegister == QSPI_MODE) {
- BootModeRegister = MMC_MODE;
- }
-#endif
-
- if (BootModeRegister == QSPI_MODE) {
- fsbl_printf(DEBUG_GENERAL,"Boot mode is QSPI\n\r");
- InitQspi();
- MoveImage = QspiAccess;
- fsbl_printf(DEBUG_INFO,"QSPI Init Done \r\n");
- } else
-#endif
-
- /*
- * NAND BOOT MODE
- */
-#ifdef XPAR_PS7_NAND_0_BASEADDR
- if (BootModeRegister == NAND_FLASH_MODE) {
- /*
- * Boot ROM always initialize the nand at lower speed
- * This is the chance to put it to an optimum speed for your nand
- * device
- */
- fsbl_printf(DEBUG_GENERAL,"Boot mode is NAND\n");
-
- Status = InitNand();
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"NAND_INIT_FAIL \r\n");
- /*
- * Error Handling here
- */
- OutputStatus(NAND_INIT_FAIL);
- FsblFallback();
- }
- MoveImage = NandAccess;
- fsbl_printf(DEBUG_INFO,"NAND Init Done \r\n");
- } else
-#endif
-
- /*
- * NOR BOOT MODE
- */
- if (BootModeRegister == NOR_FLASH_MODE) {
- fsbl_printf(DEBUG_GENERAL,"Boot mode is NOR\n\r");
- /*
- * Boot ROM always initialize the nor at lower speed
- * This is the chance to put it to an optimum speed for your nor
- * device
- */
- InitNor();
- fsbl_printf(DEBUG_INFO,"NOR Init Done \r\n");
- MoveImage = NorAccess;
- } else
-
- /*
- * SD BOOT MODE
- */
-#if defined(XPAR_PS7_SD_0_S_AXI_BASEADDR) || defined(XPAR_XSDPS_0_BASEADDR)
-
- if (BootModeRegister == SD_MODE) {
- fsbl_printf(DEBUG_GENERAL,"Boot mode is SD\r\n");
-
- /*
- * SD initialization returns file open error or success
- */
- Status = InitSD("BOOT.BIN");
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"SD_INIT_FAIL\r\n");
- OutputStatus(SD_INIT_FAIL);
- FsblFallback();
- }
- MoveImage = SDAccess;
- fsbl_printf(DEBUG_INFO,"SD Init Done \r\n");
- } else
-
- if (BootModeRegister == MMC_MODE) {
- fsbl_printf(DEBUG_GENERAL,"Booting Device is MMC\r\n");
-
- /*
- * MMC initialization returns file open error or success
- */
- Status = InitSD("BOOT.BIN");
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"MMC_INIT_FAIL\r\n");
- OutputStatus(SD_INIT_FAIL);
- FsblFallback();
- }
- MoveImage = SDAccess;
- fsbl_printf(DEBUG_INFO,"MMC Init Done \r\n");
- } else
-
-#endif
-
- /*
- * JTAG BOOT MODE
- */
- if (BootModeRegister == JTAG_MODE) {
- fsbl_printf(DEBUG_GENERAL,"Boot mode is JTAG\r\n");
-
- RegVal = Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET);
- /** If bitstream was loaded in jtag boot mode prior to running FSBL */
- if(RegVal & XDCFG_IXR_PCFG_DONE_MASK)
- {
-#ifdef PS7_POST_CONFIG
- ps7_post_config();
- /*
- * Unlock SLCR for SLCR register write
- */
- SlcrUnlock();
-#endif
- }
- /*
- * Stop the Watchdog before JTAG handoff
- */
-#ifdef XPAR_XWDTPS_0_BASEADDR
- XWdtPs_Stop(&Watchdog);
-#endif
- /*
- * Clear our mark in reboot status register
- */
- ClearFSBLIn();
-
- /*
- * SLCR lock
- */
- SlcrLock();
-
- FsblHandoffJtagExit();
- } else {
- fsbl_printf(DEBUG_GENERAL,"ILLEGAL_BOOT_MODE \r\n");
- OutputStatus(ILLEGAL_BOOT_MODE);
- /*
- * fallback starts, no return
- */
- FsblFallback();
- }
-
- fsbl_printf(DEBUG_INFO,"Flash Base Address: 0x%08lx\r\n", FlashReadBaseAddress);
-
- /*
- * Check for valid flash address
- */
- if ((FlashReadBaseAddress != XPS_QSPI_LINEAR_BASEADDR) &&
- (FlashReadBaseAddress != XPS_NAND_BASEADDR) &&
- (FlashReadBaseAddress != XPS_NOR_BASEADDR) &&
- (FlashReadBaseAddress != XPS_SDIO0_BASEADDR)) {
- fsbl_printf(DEBUG_GENERAL,"INVALID_FLASH_ADDRESS \r\n");
- OutputStatus(INVALID_FLASH_ADDRESS);
- FsblFallback();
- }
-
- /*
- * NOR and QSPI (parallel) are linear boot devices
- */
- if ((FlashReadBaseAddress == XPS_NOR_BASEADDR)) {
- fsbl_printf(DEBUG_INFO, "Linear Boot Device\r\n");
- LinearBootDeviceFlag = 1;
- }
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
- /*
- * Prevent WDT reset
- */
- XWdtPs_RestartWdt(&Watchdog);
-#endif
-
- /*
- * This used only in case of E-Fuse encryption
- * For image search
- */
- SystemInitFlag = 1;
-
- /*
- * Load boot image
- */
- HandoffAddress = LoadBootImage();
-
- fsbl_printf(DEBUG_INFO,"Handoff Address: 0x%08lx\r\n",HandoffAddress);
-
- /*
- * For Performance measurement
- */
-#ifdef FSBL_PERF
- XTime tEnd = 0;
- fsbl_printf(DEBUG_GENERAL,"Total Execution time is ");
- FsblMeasurePerfTime(tCur,tEnd);
-#endif
-
- /*
- * FSBL handoff to valid handoff address or
- * exit in JTAG
- */
- FsblHandoff(HandoffAddress);
-
-#else
- OutputStatus(NO_DDR);
- FsblFallback();
-#endif
-
- return Status;
-}
-
-/******************************************************************************/
-/**
-*
-* This function reset the CPU and goes for Boot ROM fallback handling
-*
-* @param None
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-void FsblFallback(void)
-{
- u32 RebootStatusReg;
- u32 Status;
- u32 HandoffAddr;
- u32 BootModeRegister;
-
- /*
- * Read bootmode register
- */
- BootModeRegister = Xil_In32(BOOT_MODE_REG);
- BootModeRegister &= BOOT_MODES_MASK;
-
- /*
- * Fallback support check
- */
- if (!((BootModeRegister == QSPI_MODE) ||
- (BootModeRegister == NAND_FLASH_MODE) ||
- (BootModeRegister == NOR_FLASH_MODE))) {
- fsbl_printf(DEBUG_INFO,"\r\n"
- "This Boot Mode Doesn't Support Fallback\r\n");
- ClearFSBLIn();
- FsblHookFallback();
- }
-
- /*
- * update the Multiboot Register for Golden search hunt
- */
- Update_MultiBootRegister();
-
- /*
- * Notify Boot ROM something is wrong
- */
- RebootStatusReg = Xil_In32(REBOOT_STATUS_REG);
-
- /*
- * Set the FSBL Fail mask
- */
- Xil_Out32(REBOOT_STATUS_REG, RebootStatusReg | FSBL_FAIL_MASK);
-
- /*
- * Barrier for synchronization
- */
- __asm(
- "dsb\n\t"
- "isb"
- );
-
- /*
- * Check for AES source key
- */
- if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
- /*
- * Next valid image search can happen only
- * when system initialization done
- */
- if (SystemInitFlag == 1) {
- /*
- * Clean the Fabric
- */
- Status = FabricInit();
- if(Status != XST_SUCCESS){
- ClearFSBLIn();
- FsblHookFallback();
- }
-
-#ifdef RSA_SUPPORT
-
- /*
- * Making sure PPK is set for efuse error cases
- */
- SetPpk();
-#endif
-
- /*
- * Search for next valid image
- */
- Status = NextValidImageCheck();
- if(Status != XST_SUCCESS){
- fsbl_printf(DEBUG_INFO,"\r\nNo Image Found\r\n");
- ClearFSBLIn();
- FsblHookFallback();
- }
-
- /*
- * Load next valid image
- */
- HandoffAddr = LoadBootImage();
-
- /*
- * Handoff to next image
- */
- FsblHandoff(HandoffAddr);
- } else {
- fsbl_printf(DEBUG_INFO,"System Initialization Failed\r\n");
- fsbl_printf(DEBUG_INFO,"\r\nNo Image Search\r\n");
- ClearFSBLIn();
- FsblHookFallback();
- }
- }
-
- /*
- * Reset PS, so Boot ROM will restart
- */
- Xil_Out32(PS_RST_CTRL_REG, PS_RST_MASK);
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function hands the A9/PS to the loaded user code.
-*
-* @param none
-*
-* @return none
-*
-* @note This function does not return.
-*
-****************************************************************************/
-void FsblHandoff(u32 FsblStartAddr)
-{
- u32 Status;
-
- /*
- * Enable level shifter
- */
- if(BitstreamFlag) {
- /*
- * FSBL will not enable the level shifters for a NON PS instantiated
- * Bitstream
- * CR# 671028
- * This flag can be set during compilation for a NON PS instantiated
- * bitstream
- */
-#ifndef NON_PS_INSTANTIATED_BITSTREAM
-#ifdef PS7_POST_CONFIG
- ps7_post_config();
- /*
- * Unlock SLCR for SLCR register write
- */
- SlcrUnlock();
-#else
- /*
- * Set Level Shifters DT618760
- */
- Xil_Out32(PS_LVL_SHFTR_EN, LVL_PL_PS);
- fsbl_printf(DEBUG_INFO,"Enabling Level Shifters PL to PS "
- "Address = 0x%x Value = 0x%x \n\r",
- PS_LVL_SHFTR_EN, Xil_In32(PS_LVL_SHFTR_EN));
-
- /*
- * Enable AXI interface
- */
- Xil_Out32(FPGA_RESET_REG, 0);
- fsbl_printf(DEBUG_INFO,"AXI Interface enabled \n\r");
- fsbl_printf(DEBUG_INFO, "FPGA Reset Register "
- "Address = 0x%x , Value = 0x%x \r\n",
- FPGA_RESET_REG ,Xil_In32(FPGA_RESET_REG));
-#endif
-#endif
- }
-
- /*
- * FSBL user hook call before handoff to the application
- */
- Status = FsblHookBeforeHandoff();
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_GENERAL,"FSBL_HANDOFF_HOOK_FAIL\r\n");
- OutputStatus(FSBL_HANDOFF_HOOK_FAIL);
- FsblFallback();
- }
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
- XWdtPs_Stop(&Watchdog);
-#endif
-
- /*
- * Clear our mark in reboot status register
- */
- ClearFSBLIn();
-
- if(FsblStartAddr == 0) {
- /*
- * SLCR lock
- */
- SlcrLock();
-
- fsbl_printf(DEBUG_INFO,"No Execution Address JTAG handoff \r\n");
- FsblHandoffJtagExit();
- } else {
- fsbl_printf(DEBUG_GENERAL,"SUCCESSFUL_HANDOFF\r\n");
- OutputStatus(SUCCESSFUL_HANDOFF);
- FsblHandoffExit(FsblStartAddr);
- }
-
- OutputStatus(ILLEGAL_RETURN);
-
- FsblFallback();
-}
-
-/******************************************************************************/
-/**
-*
-* This function outputs the status for the provided State in the boot process.
-*
-* @param State is where in the boot process the output is desired.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void OutputStatus(u32 State)
-{
-#ifdef STDOUT_BASEADDRESS
-#ifdef XPAR_XUARTPS_0_BASEADDR
- u32 UartReg = 0;
-#endif
-
- fsbl_printf(DEBUG_GENERAL,"FSBL Status = 0x%.4lx\r\n", State);
- /*
- * The TX buffer needs to be flushed out
- * If this is not done some of the prints will not appear on the
- * serial output
- */
-#ifdef XPAR_XUARTPS_0_BASEADDR
- UartReg = Xil_In32(STDOUT_BASEADDRESS + XUARTPS_SR_OFFSET);
- while ((UartReg & XUARTPS_SR_TXEMPTY) != XUARTPS_SR_TXEMPTY) {
- UartReg = Xil_In32(STDOUT_BASEADDRESS + XUARTPS_SR_OFFSET);
- }
-#endif
-#endif
-}
-
-/******************************************************************************/
-/**
-*
-* This function handles the error and lockdown processing and outputs the status
-* for the provided State in the boot process.
-*
-* This function is called upon exceptions.
-*
-* @param State - where in the boot process the error occurred.
-*
-* @return None.
-*
-* @note This function does not return, the PS block is reset
-*
-****************************************************************************/
-void ErrorLockdown(u32 State)
-{
- /*
- * Store the error status
- */
- OutputStatus(State);
-
- /*
- * Fall back
- */
- FsblFallback();
-}
-
-/******************************************************************************/
-/**
-*
-* This function copies a memory region to another memory region
-*
-* @param s1 is starting address for destination
-* @param s2 is starting address for the source
-* @param n is the number of bytes to copy
-*
-* @return Starting address for destination
-*
-****************************************************************************/
-void *(memcpy_rom)(void * s1, const void * s2, u32 n)
-{
- char *dst = (char *)s1;
- const char *src = (char *)s2;
-
- /*
- * Loop and copy
- */
- while (n-- != 0)
- *dst++ = *src++;
- return s1;
-}
-/******************************************************************************/
-/**
-*
-* This function copies a string to another, the source string must be null-
-* terminated.
-*
-* @param Dest is starting address for the destination string
-* @param Src is starting address for the source string
-*
-* @return Starting address for the destination string
-*
-****************************************************************************/
-char *strcpy_rom(char *Dest, const char *Src)
-{
- unsigned i;
- for (i=0; Src[i] != '\0'; ++i)
- Dest[i] = Src[i];
- Dest[i] = '\0';
- return Dest;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function sets FSBL is running mask in reboot status register
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void MarkFSBLIn(void)
-{
- Xil_Out32(REBOOT_STATUS_REG,
- Xil_In32(REBOOT_STATUS_REG) | FSBL_IN_MASK);
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function clears FSBL is running mask in reboot status register
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void ClearFSBLIn(void)
-{
- Xil_Out32(REBOOT_STATUS_REG,
- (Xil_In32(REBOOT_STATUS_REG)) & ~(FSBL_FAIL_MASK));
-}
-
-/******************************************************************************/
-/**
-*
-* This function Registers the Exception Handlers
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-static void RegisterHandlers(void)
-{
- Xil_ExceptionInit();
-
- /*
- * Initialize the vector table. Register the stub Handler for each
- * exception.
- */
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_UNDEFINED_INT,
- (Xil_ExceptionHandler)Undef_Handler,
- (void *) 0);
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_SWI_INT,
- (Xil_ExceptionHandler)SVC_Handler,
- (void *) 0);
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_PREFETCH_ABORT_INT,
- (Xil_ExceptionHandler)PreFetch_Abort_Handler,
- (void *) 0);
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_DATA_ABORT_INT,
- (Xil_ExceptionHandler)Data_Abort_Handler,
- (void *) 0);
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
- (Xil_ExceptionHandler)IRQ_Handler,(void *) 0);
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_FIQ_INT,
- (Xil_ExceptionHandler)FIQ_Handler,(void *) 0);
-
- Xil_ExceptionEnable();
-
-}
-
-static void Undef_Handler (void)
-{
- fsbl_printf(DEBUG_GENERAL,"UNDEFINED_HANDLER\r\n");
- ErrorLockdown (EXCEPTION_ID_UNDEFINED_INT);
-}
-
-static void SVC_Handler (void)
-{
- fsbl_printf(DEBUG_GENERAL,"SVC_HANDLER \r\n");
- ErrorLockdown (EXCEPTION_ID_SWI_INT);
-}
-
-static void PreFetch_Abort_Handler (void)
-{
- fsbl_printf(DEBUG_GENERAL,"PREFETCH_ABORT_HANDLER \r\n");
- ErrorLockdown (EXCEPTION_ID_PREFETCH_ABORT_INT);
-}
-
-static void Data_Abort_Handler (void)
-{
- fsbl_printf(DEBUG_GENERAL,"DATA_ABORT_HANDLER \r\n");
- ErrorLockdown (EXCEPTION_ID_DATA_ABORT_INT);
-}
-
-static void IRQ_Handler (void)
-{
- fsbl_printf(DEBUG_GENERAL,"IRQ_HANDLER \r\n");
- ErrorLockdown (EXCEPTION_ID_IRQ_INT);
-}
-
-static void FIQ_Handler (void)
-{
- fsbl_printf(DEBUG_GENERAL,"FIQ_HANDLER \r\n");
- ErrorLockdown (EXCEPTION_ID_FIQ_INT);
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function Updates the Multi boot Register to enable golden image
-* search for boot rom
-*
-* @param None
-*
-* @return
-* return none
-*
-****************************************************************************/
-static void Update_MultiBootRegister(void)
-{
- u32 MultiBootReg = 0;
-
- if (Silicon_Version != SILICON_VERSION_1) {
- /*
- * Read the mulitboot register
- */
- MultiBootReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
- XDCFG_MULTIBOOT_ADDR_OFFSET);
-
- /*
- * Incrementing multiboot register by one
- */
- MultiBootReg++;
-
- XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr,
- XDCFG_MULTIBOOT_ADDR_OFFSET,
- MultiBootReg);
-
- fsbl_printf(DEBUG_INFO,"Updated MultiBootReg = 0x%08lx\r\n",
- MultiBootReg);
- }
-}
-
-
-/******************************************************************************
-*
-* This function reset the CPU and goes for Boot ROM fallback handling
-*
-* @param None
-*
-* @return None
-*
-* @note None
-*
-*******************************************************************************/
-
-u32 GetResetReason(void)
-{
- u32 Regval;
-
- /* We are using REBOOT_STATUS_REG, we have to use bits 23:16 */
- /* for storing the RESET_REASON register value*/
- Regval = ((Xil_In32(REBOOT_STATUS_REG) >> 16) & 0xFF);
-
- return Regval;
-}
-
-
-/******************************************************************************
-*
-* This function Gets the ticks from the Global Timer
-*
-* @param Current time
-*
-* @return
-* None
-*
-* @note None
-*
-*******************************************************************************/
-#ifdef FSBL_PERF
-void FsblGetGlobalTime (XTime *tCur)
-{
- XTime_GetTime(tCur);
-}
-
-
-/******************************************************************************
-*
-* This function Measures the execution time
-*
-* @param Current time , End time
-*
-* @return
-* None
-*
-* @note None
-*
-*******************************************************************************/
-void FsblMeasurePerfTime (XTime tCur, XTime tEnd)
-{
- double tDiff = 0.0;
- double tPerfSeconds;
- XTime_GetTime(&tEnd);
- tDiff = (double)tEnd - (double)tCur;
-
- /*
- * Convert tPerf into Seconds
- */
- tPerfSeconds = tDiff/COUNTS_PER_SECOND;
-
-#if defined(STDOUT_BASEADDRESS)
- printf("%f seconds \r\n",tPerfSeconds);
-#endif
-
-}
-#endif
-
-/******************************************************************************
-*
-* This function initializes the Watchdog driver and starts the timer
-*
-* @param None
-*
-* @return
-* - XST_SUCCESS if the Watchdog driver is initialized
-* - XST_FAILURE if Watchdog driver initialization fails
-*
-* @note None
-*
-*******************************************************************************/
-#ifdef XPAR_XWDTPS_0_BASEADDR
-int InitWatchDog(void)
-{
- u32 Status = XST_SUCCESS;
- XWdtPs_Config *ConfigPtr; /* Config structure of the WatchDog Timer */
- u32 CounterValue = 1;
-
- ConfigPtr = XWdtPs_LookupConfig(WDT_DEVICE_ID);
- Status = XWdtPs_CfgInitialize(&Watchdog,
- ConfigPtr,
- ConfigPtr->BaseAddress);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO,"Watchdog Driver init Failed \n\r");
- return XST_FAILURE;
- }
-
- /*
- * Setting the divider value
- */
- XWdtPs_SetControlValue(&Watchdog,
- XWDTPS_CLK_PRESCALE,
- XWDTPS_CCR_PSCALE_4096);
- /*
- * Convert time to Watchdog counter reset value
- */
- CounterValue = ConvertTime_WdtCounter(WDT_EXPIRE_TIME);
-
- /*
- * Set the Watchdog counter reset value
- */
- XWdtPs_SetControlValue(&Watchdog,
- XWDTPS_COUNTER_RESET,
- CounterValue);
- /*
- * enable reset output, as we are only using this as a basic counter
- */
- XWdtPs_EnableOutput(&Watchdog, XWDTPS_RESET_SIGNAL);
-
- /*
- * Start the Watchdog timer
- */
- XWdtPs_Start(&Watchdog);
-
- XWdtPs_RestartWdt(&Watchdog);
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function checks whether WDT reset has happened during FSBL run
-*
-* If WDT reset happened during FSBL run, then need to fallback
-*
-* @param None.
-*
-* @return
-* None
-*
-* @note None
-*
-****************************************************************************/
-void CheckWDTReset(void)
-{
- u32 ResetReason;
- u32 RebootStatusRegister;
-
- RebootStatusRegister = Xil_In32(REBOOT_STATUS_REG);
-
- /*
- * For 1.0 Silicon the reason for Reset is in the ResetReason Register
- * Hence this register can be read to know the cause for previous reset
- * that happened.
- * Check if that reset is a Software WatchDog reset that happened
- */
- if (Silicon_Version == SILICON_VERSION_1) {
- ResetReason = Xil_In32(RESET_REASON_REG);
- } else {
- ResetReason = GetResetReason();
- }
- /*
- * If the FSBL_IN_MASK Has not been cleared, WDT happened
- * before FSBL exits
- */
- if ((ResetReason & RESET_REASON_SWDT) == RESET_REASON_SWDT ) {
- if ((RebootStatusRegister & FSBL_FAIL_MASK) == FSBL_IN_MASK) {
- /*
- * Clear the SWDT Reset bit
- */
- ResetReason &= ~RESET_REASON_SWDT;
- if (Silicon_Version == SILICON_VERSION_1) {
- /*
- * for 1.0 Silicon we need to write
- * 1 to the RESET REASON Clear register
- */
- Xil_Out32(RESET_REASON_CLR, 1);
- } else {
- Xil_Out32(REBOOT_STATUS_REG, ResetReason);
- }
-
- fsbl_printf(DEBUG_GENERAL,"WDT_RESET_OCCURED \n\r");
- }
- }
-}
-
-
-/******************************************************************************
-*
-* This function converts time into Watchdog counter value
-*
-* @param watchdog expire time in seconds
-*
-* @return
-* Counter value for Watchdog
-*
-* @note None
-*
-*******************************************************************************/
-u32 ConvertTime_WdtCounter(u32 seconds)
-{
- double time = 0.0;
- double CounterValue;
- u32 Crv = 0;
- u32 Prescaler,PrescalerValue;
-
- Prescaler = XWdtPs_GetControlValue(&Watchdog, XWDTPS_CLK_PRESCALE);
-
- if (Prescaler == XWDTPS_CCR_PSCALE_0008)
- PrescalerValue = 8;
- if (Prescaler == XWDTPS_CCR_PSCALE_0064)
- PrescalerValue = 64;
- if (Prescaler == XWDTPS_CCR_PSCALE_4096)
- PrescalerValue = 4096;
-
- time = (double)(PrescalerValue) / (double)XPAR_PS7_WDT_0_WDT_CLK_FREQ_HZ;
-
- CounterValue = seconds / time;
-
- Crv = (u32)CounterValue;
- Crv >>= WDT_CRV_SHIFT;
-
- return Crv;
-}
-
-#endif
-
-
-/******************************************************************************
-*
-* This function Gets the Silicon Version stores in global variable
-*
-* @param None
-*
-* @return None
-*
-* @note None
-*
-*******************************************************************************/
-void GetSiliconVersion(void)
-{
- /*
- * Get the silicon version
- */
- Silicon_Version = XDcfg_GetPsVersion(DcfgInstPtr);
- if(Silicon_Version == SILICON_VERSION_3_1) {
- fsbl_printf(DEBUG_GENERAL,"Silicon Version 3.1\r\n");
- } else {
- fsbl_printf(DEBUG_GENERAL,"Silicon Version %lu.0\r\n",
- Silicon_Version + 1);
- }
-}
-
-
-/******************************************************************************
-*
-* This function HeaderChecksum will calculates the header checksum and
-* compares with checksum read from flash
-*
-* @param FlashOffsetAddress Flash offset address
-*
-* @return
-* - XST_SUCCESS if ID matches
-* - XST_FAILURE if ID mismatches
-*
-* @note None
-*
-*******************************************************************************/
-u32 HeaderChecksum(u32 FlashOffsetAddress){
- u32 Checksum = 0;
- u32 Count;
- u32 TempValue = 0;
-
- for (Count = 0; Count < IMAGE_HEADER_CHECKSUM_COUNT; Count++) {
- /*
- * Read the word from the header
- */
- MoveImage(FlashOffsetAddress + IMAGE_WIDTH_CHECK_OFFSET + (Count*4), (u32)&TempValue, 4);
-
- /*
- * Update checksum
- */
- Checksum += TempValue;
- }
-
- /*
- * Invert checksum, last bit of error checking
- */
- Checksum ^= 0xFFFFFFFF;
- MoveImage(FlashOffsetAddress + IMAGE_CHECKSUM_OFFSET, (u32)&TempValue, 4);
-
- /*
- * Validate the checksum
- */
- if (TempValue != Checksum){
- fsbl_printf(DEBUG_INFO, "Checksum = %8.8lx\r\n", Checksum);
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************
-*
-* This function ImageCheckID will do check for XLNX pattern
-*
-* @param FlashOffsetAddress Flash offset address
-*
-* @return
-* - XST_SUCCESS if ID matches
-* - XST_FAILURE if ID mismatches
-*
-* @note None
-*
-*******************************************************************************/
-u32 ImageCheckID(u32 FlashOffsetAddress){
- u32 ID;
-
- /*
- * Read in the header info
- */
- MoveImage(FlashOffsetAddress + IMAGE_IDENT_OFFSET, (u32)&ID, 4);
-
- /*
- * Check the ID, make sure image is XLNX format
- */
- if (ID != IMAGE_IDENT){
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************
-*
-* This function NextValidImageCheck search for valid boot image
-*
-* @param None
-*
-* @return
-* - XST_SUCCESS if valid image found
-* - XST_FAILURE if no image found
-*
-* @note None
-*
-*******************************************************************************/
-u32 NextValidImageCheck(void)
-{
- u32 ImageBaseAddr;
- u32 MultiBootReg;
- u32 BootDevMaxSize=0;
-
- fsbl_printf(DEBUG_GENERAL, "Searching For Next Valid Image");
-
- /*
- * Setting variable with maximum flash size based on boot mode
- */
-#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
- if (FlashReadBaseAddress == XPS_QSPI_LINEAR_BASEADDR) {
- BootDevMaxSize = QspiFlashSize;
- }
-#endif
-
- if (FlashReadBaseAddress == XPS_NAND_BASEADDR) {
- BootDevMaxSize = NAND_FLASH_SIZE;
- }
-
- if (FlashReadBaseAddress == XPS_NOR_BASEADDR) {
- BootDevMaxSize = NOR_FLASH_SIZE;
- }
-
- /*
- * Read the multiboot register
- */
- MultiBootReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
- XDCFG_MULTIBOOT_ADDR_OFFSET);
-
- /*
- * Compute the image start address
- */
- ImageBaseAddr = (MultiBootReg & PCAP_MBOOT_REG_REBOOT_OFFSET_MASK)
- * GOLDEN_IMAGE_OFFSET;
-
- /*
- * Valid image search continue till end of the flash
- * With increment 32KB in each iteration
- */
- while (ImageBaseAddr < BootDevMaxSize) {
-
- fsbl_printf(DEBUG_INFO,".");
-
- /*
- * Valid image search using XLNX pattern at fixed offset
- * and header checksum
- */
- if ((ImageCheckID(ImageBaseAddr) == XST_SUCCESS) &&
- (HeaderChecksum(ImageBaseAddr) == XST_SUCCESS)) {
-
- fsbl_printf(DEBUG_GENERAL, "\r\nImage found, offset: 0x%.8lx\r\n",
- ImageBaseAddr);
- /*
- * Update multiboot register
- */
- XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr,
- XDCFG_MULTIBOOT_ADDR_OFFSET,
- MultiBootReg);
-
- return XST_SUCCESS;
- }
-
- /*
- * Increment mulitboot count
- */
- MultiBootReg++;
-
- /*
- * Compute the image start address
- */
- ImageBaseAddr = (MultiBootReg & PCAP_MBOOT_REG_REBOOT_OFFSET_MASK)
- * GOLDEN_IMAGE_OFFSET;
- }
-
- return XST_FAILURE;
-}
-
-/******************************************************************************/
-/**
-*
-* This function Checks for the ddr initialization completion
-*
-* @param None.
-*
-* @return
-* - XST_SUCCESS if the initialization is successful
-* - XST_FAILURE if the initialization is NOT successful
-*
-* @note None.
-*
-****************************************************************************/
-u32 DDRInitCheck(void)
-{
- u32 ReadVal;
-
- /*
- * Write and Read from the DDR location for sanity checks
- */
- Xil_Out32(DDR_START_ADDR, DDR_TEST_PATTERN);
- ReadVal = Xil_In32(DDR_START_ADDR);
- if (ReadVal != DDR_TEST_PATTERN) {
- return XST_FAILURE;
- }
-
- /*
- * Write and Read from the DDR location for sanity checks
- */
- Xil_Out32(DDR_START_ADDR + DDR_TEST_OFFSET, DDR_TEST_PATTERN);
- ReadVal = Xil_In32(DDR_START_ADDR + DDR_TEST_OFFSET);
- if (ReadVal != DDR_TEST_PATTERN) {
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/93/014963565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/93/014963565243001d18b399c1eb9b3628
deleted file mode 100644
index 5a1bda3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/93/014963565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,76 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_testio.h
-*
-* @addtogroup common_test_utils Test Utilities for Memory and Caches
-*
I/O test
-* The xil_testio.h file contains utility functions to test endian related memory
-* IO functions.
-*
-* A subset of the memory tests can be selected or all of the tests can be run
-* in order. If there is an error detected by a subtest, the test stops and the
-* failure code is returned. Further tests are not run even if all of the tests
-* are selected.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00 hbm 08/05/09 First release
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ----------------------------------------------
-* 1.00a hbm 08/18/10 First Release
-* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
-* the maximum number of channels.
-* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
-* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
-* 1.02a sg 05/16/12 Made changes for doxygen
-* 1.06a kpc 07/10/13 Added function prototype
-*
-*
-******************************************************************************/
-
-#ifndef XDMAPS_HW_H /* prevent circular inclusions */
-#define XDMAPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets for the DMAC.
- * @{
- */
-
-#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */
-#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */
-#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */
-#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */
-#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register
- */
-#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */
-#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager
- * Register
- */
-#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register
- */
-#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */
-
-#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */
-/*
- * The offset for the rest of the FTC registers is calculated as
- * FTC0 + dev_chan_num * 4
- */
-#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4)
-
-#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */
-/*
- * The offset for the rest of the CS registers is calculated as
- * CS0 + * dev_chan_num * 0x08
- */
-#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8)
-
-#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA
- * Channel 0
- */
-/*
- * The offset for the rest of the CPC registers is calculated as
- * CPC0 + dev_chan_num * 0x08
- */
-#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8)
-
-#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA
- * Channel 0
- */
-/* The offset for the rest of the SA registers is calculated as
- * SA_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for
- * DMA Channel 0
- */
-/* The offset for the rest of the DA registers is calculated as
- * DA_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for
- * DMA Channel 0
- */
-/*
- * The offset for the rest of the CC registers is calculated as
- * CC_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */
-/*
- * The offset for the rest of the LC0 registers is calculated as
- * LC_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20)
-#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */
-/*
- * The offset for the rest of the LC1 registers is calculated as
- * LC_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */
-#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */
-#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */
-#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */
-
-#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */
-#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */
-#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */
-#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */
-#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */
-#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */
-
-#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification
- * Register 0
- */
-#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification
- * Register 1
- */
-#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification
- * Register 2
- */
-#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification
- * Register 3
- */
-#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification
- * Register 0
- */
-#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification
- * Register 1
- */
-#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification
- * Register 2
- */
-#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification
- * Register 3
- */
-
-/*
- * Some useful register masks
- */
-#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */
-#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */
-
-#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */
-
-#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask,
- * llast 3 bits of CS register
- */
-
-#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */
-
-
-/*
- * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register.
- * @b1: Instruction byte 1
- * @b0: Instruction byte 0
- * @ch: Channel number
- * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel
- */
-#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \
- (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1)))
-
-/* @} */
-
-/** @name Control Register
- *
- * The Control register (CR) controls the major functions of the device.
- *
- * Control Register Bit Definition
- */
-
-/* @}*/
-
-
-#define XDMAPS_CHANNELS_PER_DEV 8
-
-
-/** @name Mode Register
- *
- * The mode register (MR) defines the mode of transfer as well as the data
- * format. If this register is modified during transmission or reception,
- * data validity cannot be guaranteed.
- *
- * Mode Register Bit Definition
- * @{
- */
-
-/* @} */
-
-
-/** @name Interrupt Registers
- *
- * Interrupt control logic uses the interrupt enable register (IER) and the
- * interrupt disable register (IDR) to set the value of the bits in the
- * interrupt mask register (IMR). The IMR determines whether to pass an
- * interrupt to the interrupt status register (ISR).
- * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
- * interrupt. IMR and ISR are read only, and IER and IDR are write only.
- * Reading either IER or IDR returns 0x00.
- *
- * All four registers have the same bit definitions.
- *
- * @{
- */
-
-/* @} */
-#define XDMAPS_INTCLR_ALL_MASK 0xFF
-
-#define XDmaPs_ReadReg(BaseAddress, RegOffset) \
- Xil_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write a DMAC register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the base address of the device.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note
-* C-Style signature:
-* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u32 RegisterValue)
-******************************************************************************/
-#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes *****************************/
-/*
- * Perform reset operation to the dmaps interface
- */
-void XDmaPs_ResetHw(u32 BaseAddr);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/93/60b167525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/93/60b167525243001d18b399c1eb9b3628
deleted file mode 100644
index e101fcd..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/93/60b167525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,17 +0,0 @@
-
-
-
-phased_array_platform
-
-
-
-
-
-
-
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/93/708b72b75243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/93/708b72b75243001d18b399c1eb9b3628
deleted file mode 100644
index c63db8f..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/93/708b72b75243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,11 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/93/927ab3585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/93/927ab3585243001d18b399c1eb9b3628
deleted file mode 100644
index bbf3bb8..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/93/927ab3585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,35 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include "xil_types.h"
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) char8 *sbrk (s32 nbytes);
-}
-#endif
-
-extern u8 _heap_start[];
-extern u8 _heap_end[];
-extern char8 HeapBase[];
-extern char8 HeapLimit[];
-
-
-
-__attribute__((weak)) char8 *sbrk (s32 nbytes)
-{
- char8 *base;
- static char8 *heap_ptr = HeapBase;
-
- base = heap_ptr;
- if((heap_ptr != NULL) && (heap_ptr + nbytes <= (char8 *)&HeapLimit + 1)) {
- heap_ptr += nbytes;
- return base;
- } else {
- errno = ENOMEM;
- return ((char8 *)-1);
- }
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/93/c0ab71575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/93/c0ab71575243001d18b399c1eb9b3628
deleted file mode 100644
index e1bcd93..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/93/c0ab71575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,762 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
- *
- * @file xemacps_bd.h
-* @addtogroup emacps_v3_15
-* @{
- *
- * This header provides operations to manage buffer descriptors in support
- * of scatter-gather DMA.
- *
- * The API exported by this header defines abstracted macros that allow the
- * user to read/write specific BD fields.
- *
- * Buffer Descriptors
- *
- * A buffer descriptor (BD) defines a DMA transaction. The macros defined by
- * this header file allow access to most fields within a BD to tailor a DMA
- * transaction according to user and hardware requirements. See the hardware
- * IP DMA spec for more information on BD fields and how they affect transfers.
- *
- * The XEmacPs_Bd structure defines a BD. The organization of this structure
- * is driven mainly by the hardware for use in scatter-gather DMA transfers.
- *
- * Performance
- *
- * Limiting I/O to BDs can improve overall performance of the DMA channel.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -------------------------------------------------------
- * 1.00a wsy 01/10/10 First release
- * 2.1 srt 07/15/14 Add support for Zynq Ultrascale MP GEM specification
- * and 64-bit changes.
- * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
- * 3.0 hk 02/20/15 Added support for jumbo frames.
- * Disable extended mode. Perform all 64 bit changes under
- * check for arch64.
- * 3.2 hk 11/18/15 Change BD typedef and number of words.
- * 3.8 hk 08/18/18 Remove duplicate definition of XEmacPs_BdSetLength
- * 3.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
- *
- *
- *
- * ***************************************************************************
- */
-
-#ifndef XEMACPS_BD_H /* prevent circular inclusions */
-#define XEMACPS_BD_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-#ifdef __aarch64__
-/* Minimum BD alignment */
-#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U
-#define XEMACPS_BD_NUM_WORDS 4U
-#else
-/* Minimum BD alignment */
-#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U
-#define XEMACPS_BD_NUM_WORDS 2U
-#endif
-
-/**
- * The XEmacPs_Bd is the type for buffer descriptors (BDs).
- */
-typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- * Zero out BD fields
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Nothing
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClear(BdPtr) \
- memset((BdPtr), 0, sizeof(XEmacPs_Bd))
-
-/****************************************************************************/
-/**
-*
-* Read the given Buffer Descriptor word.
-*
-* @param BaseAddress is the base address of the BD to read
-* @param Offset is the word offset to be read
-*
-* @return The 32-bit value of the field
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)
-*
-*****************************************************************************/
-#define XEmacPs_BdRead(BaseAddress, Offset) \
- (*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given Buffer Descriptor word.
-*
-* @param BaseAddress is the base address of the BD to write
-* @param Offset is the word offset to be written
-* @param Data is the 32-bit value to write to the field
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)
-*
-*****************************************************************************/
-#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \
- (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
-
-/*****************************************************************************/
-/**
- * Set the BD's Address field (word 0).
- *
- * @param BdPtr is the BD pointer to operate on
- * @param Addr is the value to write to BD's status field.
- *
- * @note :
- *
- * C-style signature:
- * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
- *
- *****************************************************************************/
-#if defined(__aarch64__) || defined(__arch64__)
-#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- (u32)((Addr) & ULONG64_LO_MASK)); \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
- (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
-#else
-#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
-#endif
-
-/*****************************************************************************/
-/**
- * Set the BD's Address field (word 0).
- *
- * @param BdPtr is the BD pointer to operate on
- * @param Addr is the value to write to BD's status field.
- *
- * @note : Due to some bits are mixed within receive BD's address field,
- * read-modify-write is performed.
- *
- * C-style signature:
- * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
- *
- *****************************************************************************/
-#ifdef __aarch64__
-#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- ~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
- (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
-#else
-#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))
-#endif
-
-/*****************************************************************************/
-/**
- * Set the BD's Status field (word 1).
- *
- * @param BdPtr is the BD pointer to operate on
- * @param Data is the value to write to BD's status field.
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetStatus(BdPtr, Data) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))
-
-
-/*****************************************************************************/
-/**
- * Retrieve the BD's Packet DMA transfer status word (word 1).
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Status word
- *
- * @note
- * C-style signature:
- * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)
- *
- * Due to the BD bit layout differences in transmit and receive. User's
- * caution is required.
- *****************************************************************************/
-#define XEmacPs_BdGetStatus(BdPtr) \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
-
-
-/*****************************************************************************/
-/**
- * Get the address (bits 0..31) of the BD's buffer address (word 0)
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#if defined(__aarch64__) || defined(__arch64__)
-#define XEmacPs_BdGetBufAddr(BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
-#else
-#define XEmacPs_BdGetBufAddr(BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
-#endif
-
-/*****************************************************************************/
-/**
- * Set transfer length in bytes for the given BD. The length must be set each
- * time a BD is submitted to hardware.
- *
- * @param BdPtr is the BD pointer to operate on
- * @param LenBytes is the number of bytes to transfer.
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
-
-
-/*****************************************************************************/
-/**
- * Retrieve the BD length field.
- *
- * For Tx channels, the returned value is the same as that written with
- * XEmacPs_BdSetLength().
- *
- * For Rx channels, the returned value is the size of the received packet.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Length field processed by hardware or set by
- * XEmacPs_BdSetLength().
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
- * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
- *
- *****************************************************************************/
-#define XEmacPs_BdGetLength(BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_LEN_MASK)
-
-/*****************************************************************************/
-/**
- * Retrieve the RX frame size.
- *
- * The returned value is the size of the received packet.
- * This API supports jumbo frame sizes if enabled.
- *
- * @param InstancePtr is the pointer to XEmacps instance
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Length field processed by hardware or set by
- * XEmacPs_BdSetLength().
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr)
- * RxBufMask is dependent on whether jumbo is enabled or not.
- *
- *****************************************************************************/
-#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- (InstancePtr)->RxBufMask)
-
-/*****************************************************************************/
-/**
- * Test whether the given BD has been marked as the last BD of a packet.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsLast(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Tell the DMA engine that the given transmit BD marks the end of the current
- * packet to be processed.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetLast(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_LAST_MASK))
-
-
-/*****************************************************************************/
-/**
- * Tell the DMA engine that the current packet does not end with the given
- * BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearLast(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_LAST_MASK))
-
-
-/*****************************************************************************/
-/**
- * Set this bit to mark the last descriptor in the receive buffer descriptor
- * list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-/*#define XEmacPs_BdSetRxWrap(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
- XEMACPS_RXBUF_WRAP_MASK))
-*/
-
-/*****************************************************************************/
-/**
- * Determine the wrap bit of the receive BD which indicates end of the
- * BD list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxWrap(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Sets this bit to mark the last descriptor in the transmit buffer
- * descriptor list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-/*#define XEmacPs_BdSetTxWrap(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_WRAP_MASK))
-*/
-
-/*****************************************************************************/
-/**
- * Determine the wrap bit of the transmit BD which indicates end of the
- * BD list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxWrap(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/*
- * Must clear this bit to enable the MAC to write data to the receive
- * buffer. Hardware sets this bit once it has successfully written a frame to
- * memory. Once set, software has to clear the bit before the buffer can be
- * used again. This macro clear the new bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearRxNew(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- ~XEMACPS_RXBUF_NEW_MASK))
-
-
-/*****************************************************************************/
-/**
- * Determine the new bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxNew(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Software sets this bit to disable the buffer to be read by the hardware.
- * Hardware sets this bit for the first buffer of a frame once it has been
- * successfully transmitted. This macro sets this bit of transmit BD to avoid
- * confusion.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetTxUsed(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_USED_MASK))
-
-
-/*****************************************************************************/
-/**
- * Software clears this bit to enable the buffer to be read by the hardware.
- * Hardware sets this bit for the first buffer of a frame once it has been
- * successfully transmitted. This macro clears this bit of transmit BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearTxUsed(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_USED_MASK))
-
-
-/*****************************************************************************/
-/**
- * Determine the used bit of the transmit BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxUsed(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if a frame fails to be transmitted due to too many retries.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxRetry(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if a frame fails to be transmitted due to data can not be
- * feteched in time or buffers are exhausted.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxUrun(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if a frame fails to be transmitted due to buffer is exhausted
- * mid-frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxExh(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Sets this bit, no CRC will be appended to the current frame. This control
- * bit must be set for the first buffer in a frame and will be ignored for
- * the subsequent buffers of a frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * This bit must be clear when using the transmit checksum generation offload,
- * otherwise checksum generation and substitution will not occur.
- *
- * C-style signature:
- * UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetTxNoCRC(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_NOCRC_MASK))
-
-
-/*****************************************************************************/
-/**
- * Clear this bit, CRC will be appended to the current frame. This control
- * bit must be set for the first buffer in a frame and will be ignored for
- * the subsequent buffers of a frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * This bit must be clear when using the transmit checksum generation offload,
- * otherwise checksum generation and substitution will not occur.
- *
- * C-style signature:
- * UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearTxNoCRC(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_NOCRC_MASK))
-
-
-/*****************************************************************************/
-/**
- * Determine the broadcast bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxBcast(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the multicast hash bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxMultiHash(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the unicast hash bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxUniHash(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if the received frame is a VLAN Tagged frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxVlan(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if the received frame has Type ID of 8100h and null VLAN
- * identifier(Priority tag).
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxPri(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if the received frame's Concatenation Format Indicator (CFI) of
- * the frames VLANTCI field was set.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxCFI(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the End Of Frame (EOF) bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxEOF(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the Start Of Frame (SOF) bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxSOF(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
-
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/93/d0a4c0595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/93/d0a4c0595243001d18b399c1eb9b3628
deleted file mode 100644
index 6d07851..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/93/d0a4c0595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,60 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm.h
-*
-* @addtogroup a9_specific Cortex A9 Processor Specific Include Files
-*
-* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h.
-*
-* The xreg_cortexa9.h file contains definitions for inline assembler code.
-* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers,
-* co-processor registers and Debug registers.
-*
-* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
-* assembler instructions, available as macros. These can be very useful for
-* tasks such as setting or getting special purpose registers, synchronization,
-* or cache manipulation etc. These inline assembler instructions can be used
-* from drivers and user applications written in C.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 10/18/09 First release
-* 3.04a sdm 01/02/12 Remove redundant dsb in mcr instruction.
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-*
-******************************************************************************/
-#ifndef XPSEUDO_ASM_H
-#define XPSEUDO_ASM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xreg_cortexa9.h"
-#ifdef __GNUC__
- #include "xpseudo_asm_gcc.h"
-#elif defined (__ICCARM__)
- #include "xpseudo_asm_iccarm.h"
-#else
- #include "xpseudo_asm_rvct.h"
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XPSEUDO_ASM_H */
-/**
-* @} End of "addtogroup a9_specific".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/93/f0c7e2585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/93/f0c7e2585243001d18b399c1eb9b3628
deleted file mode 100644
index 48dcec3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/93/f0c7e2585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,53 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file cpu_init.S
-*
-* This file contains CPU specific initialization. Invoked from main CRT
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 1.00a ecm/sdm 10/20/09 Initial version
-* 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
-* 5.0 pkp 12/16/14 removed incorrect initialization of TLB lockdown
-* register to fix CR#830580
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
- .text
- .global __cpu_init
- .align 2
-__cpu_init:
-
-/* Clear cp15 regs with unknown reset values */
- mov r0, #0x0
- mcr p15, 0, r0, c5, c0, 0 /* DFSR */
- mcr p15, 0, r0, c5, c0, 1 /* IFSR */
- mcr p15, 0, r0, c6, c0, 0 /* DFAR */
- mcr p15, 0, r0, c6, c0, 2 /* IFAR */
- mcr p15, 0, r0, c9, c13, 2 /* PMXEVCNTR */
- mcr p15, 0, r0, c13, c0, 2 /* TPIDRURW */
- mcr p15, 0, r0, c13, c0, 3 /* TPIDRURO */
-
-/* Reset and start Cycle Counter */
- mov r2, #0x80000000 /* clear overflow */
- mcr p15, 0, r2, c9, c12, 3
- mov r2, #0xd /* D, C, E */
- mcr p15, 0, r2, c9, c12, 0
- mov r2, #0x80000000 /* enable cycle counter */
- mcr p15, 0, r2, c9, c12, 1
-
- bx lr
-
-.end
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/94/00880e585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/94/00880e585243001d18b399c1eb9b3628
deleted file mode 100644
index d6b7040..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/94/00880e585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,949 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xscugic_hw.c
-* @addtogroup scugic_v4_6
-* @{
-*
-* This file contains low-level driver functions that can be used to access the
-* device. The user should refer to the hardware device specification for more
-* details of the device operation.
-* These routines are used when the user does not want to create an instance of
-* XScuGic structure but still wants to use the ScuGic device. Hence the
-* routines provided here take device id or scugic base address as arguments.
-* Separate static versions of DistInit and CPUInit are provided to implement
-* the low level driver routines.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.01a sdm 07/18/11 First release
-* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
-* 702687).
-* Added support to direct interrupts to the appropriate
-* CPU. Earlier interrupts were directed to CPU1
-* (hard coded). Now depending upon the CPU selected by
-* the user (xparameters.h), interrupts will be directed
-* to the relevant CPU.This fixes CR 699688.
-* 1.04a hk 05/04/13 Fix for CR#705621. Moved functions
-* XScuGic_SetPriTrigTypeByDistAddr and
-* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.c
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.6 kvn 02/17/17 Add support for changing GIC CPU master at run time.
-* kvn 02/28/17 Make the CpuId as static variable and Added new
-* XScugiC_GetCpuId to access CpuId.
-* 3.9 mus 02/21/18 Added new API's
-* XScuGic_InterruptUnmapFromCpuByDistAddr and
-* XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
-* API's can be used by applications to unmap
-* specific/all interrupts from target CPU. It fixes
-* CR#992490.
-* 3.10 mus 07/17/18 Updated XScuGic_DeviceInterruptHandler to fix array
-* overrun reported by coverity tool. It fixes
-* CR#1006344.
-* 3.10 mus 07/17/18 Updated file to fix the various coding style issues
-* reported by checkpatch. It fixes CR#1006344.
-* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
-* It fixes CR#1007753
-* 3.10 mus 09/19/18 Update documentation for XScuGic_RegisterHandler to
-* fix doxygen warnings.
-* 4.1 asa 03/30/19 Made changes not to direct each interrupt to all
-* available CPUs by default. This was breaking AMP
-* behavior. Instead every time an interrupt enable
-* request is received, the interrupt was mapped to
-* the respective CPU. There were several other changes
-* made to implement this including adding APIs:
-* XScuGic_InterruptMapFromCpuByDistAddr,
-* XScuGic_EnableIntr, and XScuGic_DisableIntr.
-* This set of changes was to fix CR-1024716.
-* 4.1 mus 06/12/19 Updated existing low level API's to support GIC500. It
-* fixes CR#1033401.
-* 4.3 mus 05/11/20 Added assert checks in XScuGic_EnableIntr and
-* XScuGic_DisableIntr API. It fixes CR#1063034.
-* 4.5 asa 03/07/21 Added spinlock protection for critical sections in the
-* code. The sections are critical when applications
-* running on separate CPUs (R5s or A9s) try to update
-* the same register. The spinlock mechanism used here
-* used exclusive load and store instructions. To ensure
-* that legacy behavior is not broken, unless someone
-* enables spinlocks explicitely in their applications
-* the existing flow will remain unchanged. On how to
-* enable spinlocks, please refer to the documentations
-* at: lib/bsp/standalone/src/arm/common/gcc/xil_spinlock.c
-* 4.6 sk 08/05/21 Fix Scugic Misrac violations.
-* 4.7 sk 09/14/21 Fix gcc compiler warnings for A72 processor.
-*
-*
-******************************************************************************/
-
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xscugic.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-static void DistInit(const XScuGic_Config *Config);
-#if !defined (GICv3)
-static void CPUInit(const XScuGic_Config *Config);
-#endif
-static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress);
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* DistInit initializes the distributor of the GIC. The
-* initialization entails:
-*
-* - Write the trigger mode, priority and target CPU
-* - All interrupt sources are disabled
-* - Enable the distributor
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-* @param CpuID is the Cpu ID to be initialized.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-static void DistInit(const XScuGic_Config *Config)
-{
- u32 Int_Id;
-
-#if (defined (USE_AMP) && (USE_AMP==1))
- #warning "Building GIC for AMP"
-
- /*
- * The distributor should not be initialized by FreeRTOS in the case of
- * AMP -- it is assumed that Linux is the master of this device in that
- * case.
- */
- return;
-#endif
-
-#if defined (GICv3)
- u32 Temp;
- u32 Waker_State;
-
- Waker_State = XScuGic_ReadReg((Config->DistBaseAddress) +
- XSCUGIC_RDIST_OFFSET,XSCUGIC_RDIST_WAKER_OFFSET);
- XScuGic_WriteReg((Config->DistBaseAddress) +
- XSCUGIC_RDIST_OFFSET,XSCUGIC_RDIST_WAKER_OFFSET,
- Waker_State & (~ XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK));
- /* Enable system reg interface through ICC_SRE_EL1 */
-#if EL3
- XScuGic_Enable_SystemReg_CPU_Interface_EL3();
-#endif
- XScuGic_Enable_SystemReg_CPU_Interface_EL1();
- isb();
-
- Temp = XScuGic_ReadReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET);
- Temp |= (XSCUGIC500_DCTLR_ARE_NS_ENABLE | XSCUGIC500_DCTLR_ARE_S_ENABLE);
- Temp &= ~(XSCUGIC_EN_INT_MASK);
- XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, Temp);
-#else
- XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, 0U);
-#endif
-
- /*
- * Set the security domains in the int_security registers for non-secure
- * interrupts. All are secure, so leave at the default. Set to 1 for
- * non-secure interrupts.
- */
-
-
- /*
- * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
- */
-
- /*
- * 1. The trigger mode in the int_config register
- * Only write to the SPI interrupts, so start at 32
- */
- for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
- Int_Id = Int_Id+16U) {
- /*
- * Each INT_ID uses two bits, or 16 INT_ID per register
- * Set them all to be level sensitive, active HIGH.
- */
- XScuGic_WriteReg(Config->DistBaseAddress,
- XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), 0U);
- }
-
-
-#define DEFAULT_PRIORITY 0xa0a0a0a0U
- for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
- Int_Id = Int_Id+4U) {
- /*
- * 2. The priority using int the priority_level register
- * The priority_level and spi_target registers use one byte per
- * INT_ID.
- * Write a default value that can be changed elsewhere.
- */
- XScuGic_WriteReg(Config->DistBaseAddress,
- XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
- DEFAULT_PRIORITY);
- }
-
-#if defined (GICv3)
- for (Int_Id = 0U; Int_IdDistBaseAddress,
- XSCUGIC_SECURITY_TARGET_OFFSET_CALC(Int_Id),
- XSCUGIC_DEFAULT_SECURITY);
- }
- /*
- * Set security for SGI/PPI
- *
- */
- XScuGic_WriteReg( Config->DistBaseAddress + XSCUGIC_RDIST_SGI_PPI_OFFSET,
- XSCUGIC_RDIST_IGROUPR_OFFSET, XSCUGIC_DEFAULT_SECURITY);
-#endif
-
- for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
- Int_Id = Int_Id+32U) {
- /*
- * 4. Enable the SPI using the enable_set register.
- * Leave all disabled for now.
- */
- XScuGic_WriteReg(Config->DistBaseAddress,
- XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET,
- Int_Id),
- 0xFFFFFFFFU);
-
- }
-
-#if defined (GICv3)
- Temp = XScuGic_ReadReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET);
- Temp |= XSCUGIC_EN_INT_MASK;
- XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, Temp);
- XScuGic_Enable_Group1_Interrupts();
- XScuGic_Enable_Group0_Interrupts();
- XScuGic_set_priority_filter(0xff);
-#else
-
- XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET,
- XSCUGIC_EN_INT_MASK);
-#endif
-
-}
-
-#if !defined (GICv3)
-/*****************************************************************************/
-/**
-*
-* CPUInit initializes the CPU Interface of the GIC. The initialization entails:
-*
-* - Set the priority of the CPU.
-* - Enable the CPU interface
-*
-* @param ConfigPtr is a pointer to a config table for the particular
-* device this driver is associated with.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-static void CPUInit(const XScuGic_Config *Config)
-{
- /*
- * Program the priority mask of the CPU using the Priority mask
- * register
- */
- XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CPU_PRIOR_OFFSET,
- 0xF0U);
-
- /*
- * If the CPU operates in both security domains, set parameters in the
- * control_s register.
- * 1. Set FIQen=1 to use FIQ for secure interrupts,
- * 2. Program the AckCtl bit
- * 3. Program the SBPR bit to select the binary pointer behavior
- * 4. Set EnableS = 1 to enable secure interrupts
- * 5. Set EnbleNS = 1 to enable non secure interrupts
- */
-
- /*
- * If the CPU operates only in the secure domain, setup the
- * control_s register.
- * 1. Set FIQen=1,
- * 2. Set EnableS=1, to enable the CPU interface to signal secure .
- * interrupts Only enable the IRQ output unless secure interrupts
- * are needed.
- */
- XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CONTROL_OFFSET, 0x07U);
-
-}
-#endif
-
-/*****************************************************************************/
-/**
-*
-* Initialize the GIC based on the device id. The
-* initialization entails:
-*
-* - Initialize distributor interface
-* - Initialize cpu interface
-*
-* @param DeviceId is device id to be worked on.
-*
-* @return
-*
-* - XST_SUCCESS if initialization was successful
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-s32 XScuGic_DeviceInitialize(u32 DeviceId)
-{
- XScuGic_Config *Config;
-
- Config = &XScuGic_ConfigTable[(u32)DeviceId];
- DistInit(Config);
-#if !defined (GICv3)
- CPUInit(Config);
-#endif
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-* This function is the primary interrupt handler for the driver. It must be
-* connected to the interrupt source such that it is called when an interrupt of
-* the interrupt controller is active. It will resolve which interrupts are
-* active and enabled and call the appropriate interrupt handler. It uses
-* the Interrupt Type information to determine when to acknowledge the
-* interrupt.Highest priority interrupts are serviced first.
-*
-* This function assumes that an interrupt vector table has been previously
-* initialized. It does not verify that entries in the table are valid before
-* calling an interrupt handler.
-*
-* @param DeviceId is the unique identifier for the ScuGic device.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XScuGic_DeviceInterruptHandler(void *DeviceId)
-{
-
- u32 InterruptID;
-#if !defined (GICv3)
- u32 IntIDFull;
-#endif
- XScuGic_VectorTableEntry *TablePtr;
- XScuGic_Config *CfgPtr;
-
- CfgPtr = &XScuGic_ConfigTable[(INTPTR)DeviceId];
-
-#if defined (GICv3)
- InterruptID = XScuGic_get_IntID();
-#else
- /*
- * Read the int_ack register to identify the highest priority
- * interrupt ID and make sure it is valid. Reading Int_Ack will
- * clear the interrupt in the GIC.
- */
- IntIDFull = XScuGic_ReadReg(CfgPtr->CpuBaseAddress,
- XSCUGIC_INT_ACK_OFFSET);
- InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
-
-#endif
- if (XSCUGIC_MAX_NUM_INTR_INPUTS <= InterruptID) {
- goto IntrExit;
- }
-
- /*
- * If the interrupt is shared, do some locking here if there are
- * multiple processors.
- */
- /*
- * If preemption is required:
- * Re-enable preemption by setting the CPSR I bit for non-secure ,
- * interrupts or the F bit for secure interrupts
- */
-
- /*
- * If we need to change security domains, issue a SMC instruction here.
- */
-
- /*
- * Execute the ISR. Jump into the Interrupt service routine based on
- * the IRQSource. A software trigger is cleared by the ACK.
- */
- TablePtr = &(CfgPtr->HandlerTable[InterruptID]);
- if (TablePtr != NULL) {
- TablePtr->Handler(TablePtr->CallBackRef);
- }
-
-IntrExit:
- /*
- * Write to the EOI register, we are all done here.
- * Let this function return, the boot code will restore the stack.
- */
-#if defined (GICv3)
- XScuGic_ack_Int(InterruptID);
-#else
- XScuGic_WriteReg(CfgPtr->CpuBaseAddress, XSCUGIC_EOI_OFFSET, IntIDFull);
-#endif
-
- /*
- * Return from the interrupt. Change security domains could happen
- * here.
- */
-}
-
-/*****************************************************************************/
-/**
-*
-* Register a handler function for a specific interrupt ID. The vector table
-* of the interrupt controller is updated, overwriting any previous handler.
-* The handler function will be called when an interrupt occurs for the given
-* interrupt ID.
-*
-* @param BaseAddress is the CPU Interface Register base address of the
-* interrupt controller whose vector table will be modified.
-* @param InterruptID is the interrupt ID to be associated with the input
-* handler.
-* @param IntrHandler is the function pointer that will be added to
-* the vector table for the given interrupt ID.
-* @param CallBackRef is the argument that will be passed to the new
-* handler function when it is called. This is user-specific.
-*
-* @return None.
-*
-* @note
-*
-* Note that this function has no effect if the input base address is invalid.
-*
-******************************************************************************/
-void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
- Xil_InterruptHandler IntrHandler, void *CallBackRef)
-{
- XScuGic_Config *CfgPtr;
- CfgPtr = LookupConfigByBaseAddress(BaseAddress);
-
- if (CfgPtr != NULL) {
- if (IntrHandler != NULL) {
- CfgPtr->HandlerTable[InterruptID].Handler =
- (Xil_InterruptHandler)IntrHandler;
- }
- if (CallBackRef != NULL) {
- CfgPtr->HandlerTable[InterruptID].CallBackRef =
- CallBackRef;
- }
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Looks up the device configuration based on the CPU interface base address of
-* the device. A table contains the configuration info for each device in the
-* system.
-*
-* @param CpuBaseAddress is the CPU Interface Register base address.
-*
-* @return A pointer to the configuration structure for the specified
-* device, or NULL if the device was not found.
-*
-* @note None.
-*
-******************************************************************************/
-static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress)
-{
- XScuGic_Config *CfgPtr = NULL;
- u32 Index;
-
- for (Index = 0U; Index < XPAR_SCUGIC_NUM_INSTANCES; Index++) {
- if (XScuGic_ConfigTable[Index].CpuBaseAddress ==
- CpuBaseAddress) {
- CfgPtr = &XScuGic_ConfigTable[Index];
- break;
- }
- }
-
- return (XScuGic_Config *)CfgPtr;
-}
-
-/****************************************************************************/
-/**
-* Sets the interrupt priority and trigger type for the specificd IRQ source.
-*
-* @param DistBaseAddress is the distributor base address
-* @param Int_Id is the IRQ source number to modify
-* @param Priority is the new priority for the IRQ source. 0 is highest
-* priority, 0xF8(248) is lowest. There are 32 priority
-* levels supported with a step of 8. Hence the supported
-* priorities are 0, 8, 16, 32, 40 ..., 248.
-* @param Trigger is the new trigger type for the IRQ source.
-* Each bit pair describes the configuration for an INT_ID.
-* SFI Read Only b10 always
-* PPI Read Only depending on how the PPIs are configured.
-* b01 Active HIGH level sensitive
-* b11 Rising edge sensitive
-* SPI LSB is read only.
-* b01 Active HIGH level sensitive
-* b11 Rising edge sensitive/
-*
-* @return None.
-*
-* @note This API has the similar functionality of XScuGic_SetPriority
-* TriggerType() and should be used when there is no InstancePtr.
-*
-*****************************************************************************/
-void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
- u8 Priority, u8 Trigger)
-{
- u32 RegValue;
-#if defined (GICv3)
- u32 Temp;
- u32 Index;
-#endif
- u8 LocalPriority = Priority;
-
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(Trigger <= XSCUGIC_INT_CFG_MASK);
- Xil_AssertVoid(LocalPriority <= XSCUGIC_MAX_INTR_PRIO_VAL);
-#if defined (GICv3)
- if (Int_Id < XSCUGIC_SPI_INT_ID_START )
- {
- XScuGic_WriteReg(DistBaseAddress + XSCUGIC_RDIST_SGI_PPI_OFFSET,
- XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(Int_Id),Priority);
- Temp = XScuGic_ReadReg(DistBaseAddress + XSCUGIC_RDIST_SGI_PPI_OFFSET,
- XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(Int_Id));
- Index = XScuGic_Get_Rdist_Int_Trigger_Index(Int_Id);
- Temp |= (Trigger << Index);
- XScuGic_WriteReg(DistBaseAddress + XSCUGIC_RDIST_SGI_PPI_OFFSET,
- XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(Int_Id),Temp);
- return;
- }
-#endif
-
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
-
- /*
- * Determine the register to write to using the Int_Id.
- */
- RegValue = XScuGic_ReadReg(DistBaseAddress,
- XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
-
- /*
- * The priority bits are Bits 7 to 3 in GIC Priority Register. This
- * means the number of priority levels supported are 32 and they are
- * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
- * The lower order 3 bits are masked before putting it in the register.
- */
- LocalPriority = LocalPriority & XSCUGIC_INTR_PRIO_MASK;
- /*
- * Shift and Mask the correct bits for the priority and trigger in the
- * register
- */
- RegValue &= ~((u32)XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
- RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
-
- /*
- * Write the value back to the register.
- */
- XScuGic_WriteReg(DistBaseAddress, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
- RegValue);
- /*
- * Determine the register to write to using the Int_Id.
- */
- RegValue = XScuGic_ReadReg(DistBaseAddress,
- XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id));
-
- /*
- * Shift and Mask the correct bits for the priority and trigger in the
- * register
- */
- RegValue &= ~((u32)XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
- RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
-
- /*
- * Write the value back to the register.
- */
- XScuGic_WriteReg(DistBaseAddress, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
- RegValue);
-
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-}
-
-/****************************************************************************/
-/**
-* Gets the interrupt priority and trigger type for the specificd IRQ source.
-*
-* @param DistBaseAddress is the distributor base address
-* @param Int_Id is the IRQ source number to modify
-* @param Priority is a pointer to the value of the priority of the IRQ
-* source. This is a return value.
-* @param Trigger is pointer to the value of the trigger of the IRQ
-* source. This is a return value.
-*
-* @return None.
-*
-* @note This API has the similar functionality of XScuGic_GetPriority
-* TriggerType() and should be used when there is no InstancePtr.
-*
-*****************************************************************************/
-void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
- u8 *Priority, u8 *Trigger)
-{
- u32 RegValue;
-
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
- Xil_AssertVoid(Priority != NULL);
- Xil_AssertVoid(Trigger != NULL);
-
- /*
- * Determine the register to read to using the Int_Id.
- */
- RegValue = XScuGic_ReadReg(DistBaseAddress,
- XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
-
- /*
- * Shift and Mask the correct bits for the priority and trigger in the
- * register
- */
- RegValue = RegValue >> ((Int_Id%4U)*8U);
- *Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
-
- /*
- * Determine the register to read to using the Int_Id.
- */
- RegValue = XScuGic_ReadReg(DistBaseAddress,
- XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id));
-
- /*
- * Shift and Mask the correct bits for the priority and trigger in the
- * register
- */
- RegValue = RegValue >> ((Int_Id%16U)*2U);
-
- *Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
-}
-
-/****************************************************************************/
-/**
-* Sets the target CPU for the interrupt of a peripheral
-*
-* @param DistBaseAddress is the device base address
-* @param Cpu_Id is a CPU number from which the interrupt has to be
-* unmapped
-* @param Int_Id is the IRQ source number to modify
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_InterruptMapFromCpuByDistAddr(u32 DistBaseAddress,
- u8 Cpu_Id, u32 Int_Id)
-{
- u32 RegValue;
-#if !defined (GICv3)
- u32 Offset;
- u8 Cpu_CoreId;
-#endif
-
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
-#if defined (GICv3)
- u32 Temp;
- if (Int_Id >= 32) {
- Temp = Int_Id - 32;
- RegValue = XScuGic_ReadReg(DistBaseAddress,
- XSCUGIC_IROUTER_OFFSET_CALC(Temp));
- RegValue |= (Cpu_Id);
- XScuGic_WriteReg(DistBaseAddress, XSCUGIC_IROUTER_OFFSET_CALC(Temp),
- RegValue);
- }
-#else
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
- RegValue = XScuGic_ReadReg(DistBaseAddress,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
-
- Offset = (Int_Id & 0x3U);
- Cpu_CoreId = (0x1U << Cpu_Id);
-
- RegValue |= (u32)(Cpu_CoreId) << (Offset*8U);
-
- XScuGic_WriteReg(DistBaseAddress,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
- RegValue);
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-#endif
-}
-
-/****************************************************************************/
-/**
-* Unmaps specific SPI interrupt from the target CPU
-*
-* @param DistBaseAddress is the device base address
-* @param Cpu_Id is a CPU number from which the interrupt has to be
-* unmapped
-* @param Int_Id is the IRQ source number to modify
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
- u8 Cpu_Id, u32 Int_Id)
-{
- u32 RegValue;
-#if !defined (GICv3)
- u32 Offset;
- u32 Cpu_CoreId;
-#endif
-
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
-#if defined (GICv3)
- u32 Temp;
- if (Int_Id >= 32 && Cpu_Id != 0) {
- Temp = Int_Id - 32;
- RegValue = XScuGic_ReadReg(DistBaseAddress,
- XSCUGIC_IROUTER_OFFSET_CALC(Temp));
- RegValue &= ~(Cpu_Id);
- XScuGic_WriteReg(DistBaseAddress, XSCUGIC_IROUTER_OFFSET_CALC(Temp),
- RegValue);
- } else if (Cpu_Id == 0) {
- xil_printf("Error: Unable to unmap interrupt id %d from core %d",Int_Id,Cpu_Id);
- }
-#else
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
-
- RegValue = XScuGic_ReadReg(DistBaseAddress,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
-
- Offset = (Int_Id & 0x3U);
- Cpu_CoreId = ((u32)0x1U << Cpu_Id);
-
- RegValue &= ~(Cpu_CoreId << (Offset*8U));
- XScuGic_WriteReg(DistBaseAddress,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), RegValue);
-
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-#endif
-}
-
-/****************************************************************************/
-/**
-* Unmaps all SPI interrupts from the target CPU
-*
-* @param DistBaseAddress is the device base address
-* @param Cpu_Id is a CPU number from which the interrupts has to be
-* unmapped
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
- u8 Cpu_Id)
-{
- u32 Int_Id;
- u32 Target_Cpu;
- u32 LocalCpuID = ((u32)1U << Cpu_Id);
-
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
-
- LocalCpuID |= LocalCpuID << 8U;
- LocalCpuID |= LocalCpuID << 16U;
-
- for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS;
- Int_Id = Int_Id+4U) {
-
- Target_Cpu = XScuGic_ReadReg(DistBaseAddress,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
- /* Remove LocalCpuID from interrupt target register */
- Target_Cpu &= (~LocalCpuID);
- XScuGic_WriteReg(DistBaseAddress,
- XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), Target_Cpu);
-
- }
-
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-}
-
-/*****************************************************************************/
-/**
-*
-* Enables the interrupt source provided as the argument Int_Id. Any pending
-* interrupt condition for the specified Int_Id will occur after this function is
-* called.
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-* @param Int_Id contains the ID of the interrupt source and should be
-* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XScuGic_EnableIntr (u32 DistBaseAddress, u32 Int_Id)
-{
- u8 Cpu_Id = (u8)XScuGic_GetCpuID();
-#if defined (GICv3)
- u32 Temp;
-#endif
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
-
-#if defined (GICv3)
- if (Int_Id < XSCUGIC_SPI_INT_ID_START) {
- XScuGic_InterruptMapFromCpuByDistAddr(DistBaseAddress, Cpu_Id,
- Int_Id);
-
- Int_Id &= 0x1f;
- Int_Id = 1 << Int_Id;
-
- Temp = XScuGic_ReadReg(DistBaseAddress +
- XSCUGIC_RDIST_SGI_PPI_OFFSET, XSCUGIC_RDIST_ISENABLE_OFFSET);
- Temp |= Int_Id;
- XScuGic_WriteReg(DistBaseAddress + XSCUGIC_RDIST_SGI_PPI_OFFSET,
- XSCUGIC_RDIST_ISENABLE_OFFSET,Temp);
- }
-#endif
-
- XScuGic_InterruptMapFromCpuByDistAddr(DistBaseAddress, Cpu_Id, Int_Id);
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
- XScuGic_WriteReg((DistBaseAddress), XSCUGIC_ENABLE_SET_OFFSET +
- (((Int_Id) / 32U) * 4U), ((u32)0x00000001U << ((Int_Id) % 32U)));
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-}
-
-/*****************************************************************************/
-/**
-*
-* Disables the interrupt source provided as the argument Int_Id such that the
-* interrupt controller will not cause interrupts for the specified Int_Id. The
-* interrupt controller will continue to hold an interrupt condition for the
-* Int_Id, but will not cause an interrupt.
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-* @param Int_Id contains the ID of the interrupt source and should be
-* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XScuGic_DisableIntr (u32 DistBaseAddress, u32 Int_Id)
-{
- u8 Cpu_Id = (u8)XScuGic_GetCpuID();
- Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
-
-#if defined (GICv3)
- u32 Temp;
-
- if (Int_Id < XSCUGIC_SPI_INT_ID_START) {
-
- XScuGic_InterruptUnmapFromCpuByDistAddr(DistBaseAddress +
- XSCUGIC_RDIST_SGI_PPI_OFFSET, Cpu_Id, Int_Id);
-
- Int_Id &= 0x1f;
- Int_Id = 1 << Int_Id;
-
- Temp = XScuGic_ReadReg(DistBaseAddress + XSCUGIC_RDIST_SGI_PPI_OFFSET,
- XSCUGIC_RDIST_ISENABLE_OFFSET);
- Temp &= ~Int_Id;
- XScuGic_WriteReg(DistBaseAddress + XSCUGIC_RDIST_SGI_PPI_OFFSET,
- XSCUGIC_RDIST_ISENABLE_OFFSET,Temp);
- }
-#endif
- XScuGic_InterruptUnmapFromCpuByDistAddr(DistBaseAddress, Cpu_Id, Int_Id);
- /*
- * Call spinlock to protect multiple applications running at separate
- * CPUs to write to the same register. This macro also ensures that
- * the spinlock mechanism is used only if spinlock is enabled by
- * user.
- */
- XIL_SPINLOCK();
- XScuGic_WriteReg((DistBaseAddress), XSCUGIC_DISABLE_OFFSET +
- (((Int_Id) / 32U) * 4U), ((u32)0x00000001U << ((Int_Id) % 32U)));
- /*
- * Release the lock previously taken. This macro ensures that the lock
- * is given only if spinlock mechanism is enabled by the user.
- */
- XIL_SPINUNLOCK();
-}
-
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/94/500145585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/94/500145585243001d18b399c1eb9b3628
deleted file mode 100644
index 012ecfb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/94/500145585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,155 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file translation_table.s
-*
-* @addtogroup a53_32_boot_code
-* @{
-*
translation_table.S
-* The translation_table.S contains a static page table required by MMU for
-* cortex-A53. This translation table is flat mapped (input address = output
-* address) with default memory attributes defined for zynq ultrascale+
-* architecture. It utilizes short descriptor translation table format with each
-* section defining 1MB of memory.
-*
-* For DDR in region 0x00000000 - 0x7FFFFFFF, a system where DDR is less than
-* 2GB, region after DDR and before PL is marked as undefined/reserved in
-* translation table. In region 0xFFC00000 - 0xFFDFFFFF, it contains CSU
-* and PMU memory which are marked as Device since it is less than 1MB and
-* falls in a region with device memory.
-*
-* The overview of translation table memory attributes is described below.
-*
-*| | Memory Range | Definition in Translation Table |
-*|-----------------|-------------------------|---------------------------------|
-*| DDR | 0x00000000 - 0x7FFFFFFF | Normal write-back Cacheable |
-*| PL | 0x80000000 - 0xBFFFFFFF | Strongly Ordered |
-*| QSPI, lower PCIe| 0xC0000000 - 0xEFFFFFFF | Device Memory |
-*| Reserved | 0xF0000000 - 0xF7FFFFFF | Unassigned |
-*| STM Coresight | 0xF8000000 - 0xF8FFFFFF | Device Memory |
-*| GIC | 0xF9000000 - 0xF90FFFFF | Device memory |
-*| Reserved | 0xF9100000 - 0xFCFFFFFF | Unassigned |
-*| FPS, LPS slaves | 0xFD000000 - 0xFFBFFFFF | Device memory |
-*| CSU, PMU | 0xFFC00000 - 0xFFDFFFFF | Device Memory |
-*| TCM, OCM | 0xFFE00000 - 0xFFFFFFFF | Normal write-back cacheable |
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 5.4 pkp 18/12/15 Updated the address map according to proper address map
-* 6.0 mus 20/07/16 Added warning for ddrless HW design CR-954977
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 08/25/09 First release
-* 7.5 mus 03/10/21 Added new set of Xil_TestMem32, Xil_TestMem16 and
-* Xil_TestMem8 APIs to support memory test for memory
-* regions mapped at extended addresses
-* (addresses > 4 GB). These new set of APIs would be
-* compiled only for 32 bit Microblaze processor, if
-* XPAR_MICROBLAZE_ADDR_SIZE is greater than 32.
-* It fixes CR#1089129.
-* 7.6 mus 07/29/21 Updated Xil_TestMem8 to fix issues reported by static
-* analysis tool. It fixes CR#1105956.
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xil_testmem.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions ****************************/
-/************************** Function Prototypes *****************************/
-
-static u32 RotateLeft(u32 Input, u8 Width);
-
-/* define ROTATE_RIGHT to give access to this functionality */
-/* #define ROTATE_RIGHT */
-#ifdef ROTATE_RIGHT
-static u32 RotateRight(u32 Input, u8 Width);
-#endif /* ROTATE_RIGHT */
-
-#if defined(__MICROBLAZE__) && !defined(__arch64__) && (XPAR_MICROBLAZE_ADDR_SIZE > 32)
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 8-bit wide memory test.
-*
-* @param Addrlow: lower 32 bit address of memory to be tested.
-* @param Addrhigh: upper 32 bit address of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: type of test selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u8 Val;
- u8 WordMem8;
- s32 Status = 0;
- u64 Addr = (Addrlow + ((u64)Addrhigh << 32));
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * select the proper Subtest(s)
- */
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from XIL_TESTMEM_INIT_VALUE
- */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- sbea(Addr+I, Val);
- Val++;
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = XIL_TESTMEM_INIT_VALUE;
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference
- * Val
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = lbuea(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val++;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking ones test
- */
-
- for (j = 0U; j < NUM_OF_BITS_IN_BYTE; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
- Val = (u8)((u32)1 << j);
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
- for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) {
- /* write memory location */
- sbea(Addr+I, Val);
- Val = (u8)RotateLeft(Val, 8U);
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u8)((u32)1 << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) {
- /* read memory location */
- WordMem8 = lbuea(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = (u8)RotateLeft(Val, NUM_OF_BITS_IN_BYTE);
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible initial test
- * Patterns for walking zeros test
- */
-
- for (j = 0U; j < NUM_OF_BITS_IN_BYTE; j++) {
- /*
- * Generate an initial value for walking ones test to test
- * for bad data bits
- */
- Val = (u8) (~(1U << j));
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
- for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) {
- /* write memory location */
- sbea(Addr+I, Val);
- Val = ~((u8)RotateLeft(~Val, NUM_OF_BITS_IN_BYTE));
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u8) (~(1U << j));
- /* Read the values from each location that was written */
- for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) {
- /* read memory location */
- WordMem8 = lbuea(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val = ~((u8)RotateLeft(~Val, NUM_OF_BITS_IN_BYTE));
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- Val = (u8) (~((INTPTR) (Addr + I)));
- sbea(Addr+I, Val);
- }
-
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = lbuea(Addr+I);
- Val = (u8) (~((INTPTR) (Addr+I)));
- if ((WordMem8 ^ Val) != 0x00U) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
-
- if (Pattern == (u8)0) {
- Val = 0xA5U;
- }
- else {
- Val = Pattern;
- }
- /*
- * Fill the memory with fixed Pattern
- */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- sbea(Addr+I, Val);
- }
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed Pattern
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = lbuea(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
-End_Label:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 16-bit wide memory test.
-*
-* @param Addrlow: lower 32 bit address of memory to be tested.
-* @param Addrhigh: upper 32 bit address of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant Pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: type of test selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u16 Val;
- u16 WordMem16;
- s32 Status = 0;
- u64 Addr = (Addrlow + ((u64)Addrhigh << 32));
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * selectthe proper Subtest(s)
- */
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from 'XIL_TESTMEM_INIT_VALUE'
- */
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) {
- /* write memory location */
- shea(Addr+I, Val);
- Val++;
- I = I + NUM_OF_BYTES_IN_HW;
- }
-
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference val
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) {
- /* read memory location */
- WordMem16 = lhuea(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val++;
- I = I + NUM_OF_BYTES_IN_HW;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial test
- * Patterns for walking ones test
- */
-
- for (j = 0U; j < NUM_OF_BITS_IN_HW; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = (u16)((u32)1 << j);
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) {
- /* write memory location */
- shea(Addr+I,Val);
- Val = (u16)RotateLeft(Val, 16U);
- I = I + NUM_OF_BYTES_IN_HW;
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u16)((u32)1 << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) {
- /* read memory location */
- WordMem16 = lhuea(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = (u16)RotateLeft(Val, NUM_OF_BITS_IN_HW);
- I = I + NUM_OF_BYTES_IN_HW;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking zeros test
- */
-
- for (j = 0U; j < NUM_OF_BITS_IN_HW; j++) {
- /*
- * Generate an initial value for walking ones
- * test to test for bad
- * data bits
- */
-
- Val = ~(1U << j);
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW);) {
- shea(Addr+I, Val);
- Val = ~((u16)RotateLeft(~Val, 16U));
- I = I + NUM_OF_BYTES_IN_HW;
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = ~(1U << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) {
- WordMem16= lhuea(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = ~((u16)RotateLeft(~Val, NUM_OF_BITS_IN_HW));
- I = I + NUM_OF_BYTES_IN_HW;
- }
-
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) {
- /* write memory location */
- Val = (u16) (~((INTPTR)((Addr+I))));
- shea(Addr+I, Val);
- I = I + NUM_OF_BYTES_IN_HW;
- }
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW*Words); ) {
- /* read memory location */
- //WordMem16 = *(Addr+I);
- WordMem16 = lhuea(Addr+I);
- Val = (u16) (~((INTPTR) ((Addr+I))));
- if ((WordMem16 ^ Val) != 0x0000U) {
- Status = -1;
- goto End_Label;
- }
- I = I + NUM_OF_BYTES_IN_HW;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
- if (Pattern == (u16)0) {
- Val = 0xDEADU;
- }
- else {
- Val = Pattern;
- }
-
- /*
- * Fill the memory with fixed pattern
- */
-
- for (I = 0U; I < (2*Words);) {
- /* write memory location */
- shea(Addr+I, Val);
- I = I + NUM_OF_BYTES_IN_HW;
- }
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed pattern
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) {
- /* read memory location */
- WordMem16=lhuea(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- I = I + NUM_OF_BYTES_IN_HW;
- }
- }
-End_Label:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 32-bit wide memory test.
-*
-* @param Addrlow: lower 32 bit address of memory to be tested.
-* @param Addrhigh: upper 32 bit address of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: test type selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-* - 0 is returned for a pass
-* - 1 is returned for a failure
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u32 Val;
- u32 WordMem32;
- s32 Status = 0;
- u64 Addr = (Addrlow + ((u64)Addrhigh << 32));
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
-
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from 'XIL_TESTMEM_INIT_VALUE'
- */
- for (I = 0U; I <(NUM_OF_BYTES_IN_WORD * Words);) {
- swea(Addr+I, Val);
- Val++;
- I = I + NUM_OF_BYTES_IN_WORD;
- }
-
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference
- * Val
- */
-
- for (I = 0U; I < ( NUM_OF_BYTES_IN_WORD * Words);) {
- WordMem32 = lwea(Addr+I);
-
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val++;
- I = I + NUM_OF_BYTES_IN_WORD;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking ones test
- */
-
- for (j = 0U; j < NUM_OF_BITS_IN_WORD; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = (1U << j);
-
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * NUM_OF_BITS_IN_WORD);) {
- /* write memory location */
- swea(Addr+I, Val);
- Val = (u32) RotateLeft(Val, NUM_OF_BITS_IN_WORD);
- I = I + NUM_OF_BYTES_IN_WORD;
- }
-
- /*
- * Restore the reference 'val' to the
- * initial value
- */
- Val = 1U << j;
-
- /* Read the values from each location that was
- * written */
- for (I = 0U; I < ((u32)32 * NUM_OF_BYTES_IN_WORD);) {
- /* read memory location */
-
- WordMem32 = lwea(Addr+I);
-
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val = (u32)RotateLeft(Val, NUM_OF_BITS_IN_WORD);
- I = I + NUM_OF_BYTES_IN_WORD;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible
- * initial test Patterns for walking zeros test
- */
-
- for (j = 0U; j < NUM_OF_BITS_IN_WORD; j++) {
-
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = ~(1U << j);
-
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (NUM_OF_BITS_IN_WORD * NUM_OF_BYTES_IN_WORD);) {
- /* write memory location */
- swea(Addr+I, Val);
- Val = ~((u32)RotateLeft(~Val, NUM_OF_BITS_IN_WORD));
- I = I + NUM_OF_BYTES_IN_WORD;
- }
-
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
-
- Val = ~(1U << j);
-
- /* Read the values from each location that was
- * written */
- for (I = 0U; I < (NUM_OF_BITS_IN_WORD * NUM_OF_BYTES_IN_WORD);) {
- /* read memory location */
- WordMem32 = lwea(Addr+I);
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = ~((u32)RotateLeft(~Val, NUM_OF_BITS_IN_WORD));
- I = I + NUM_OF_BYTES_IN_WORD;
- }
-
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) {
- /* write memory location */
- Val = (u32) (~((INTPTR) (Addr+I)));
- swea(Addr+I, Val);
- I = I + NUM_OF_BYTES_IN_WORD;
- }
-
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) {
- /* Read the location */
- WordMem32 = lwea(Addr+I);
- Val = (u32) (~((INTPTR) (Addr+I)));
-
- if ((WordMem32 ^ Val) != 0x00000000U) {
- Status = -1;
- goto End_Label;
- }
- I = I + NUM_OF_BYTES_IN_WORD;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
-
- if (Pattern == (u32)0) {
- Val = 0xDEADBEEFU;
- }
- else {
- Val = Pattern;
- }
-
- /*
- * Fill the memory with fixed Pattern
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) {
- /* write memory location */
- swea(Addr+I, Val);
- I = I + NUM_OF_BYTES_IN_WORD;
- }
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed Pattern
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) {
-
- /* read memory location */
-
- WordMem32 = lwea(Addr+I);
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
- I = I + NUM_OF_BYTES_IN_WORD;
- }
- }
-
-End_Label:
- return Status;
-}
-
-#else
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 32-bit wide memory test.
-*
-* @param Addr: pointer to the region of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: test type selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-* - 0 is returned for a pass
-* - 1 is returned for a failure
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u32 Val;
- u32 FirtVal;
- u32 WordMem32;
- s32 Status = 0;
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
- FirtVal = XIL_TESTMEM_INIT_VALUE;
-
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from 'FirtVal'
- */
- for (I = 0U; I < Words; I++) {
- *(Addr+I) = Val;
- Val++;
- }
-
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = FirtVal;
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference
- * Val
- */
-
- for (I = 0U; I < Words; I++) {
- WordMem32 = *(Addr+I);
-
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val++;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking ones test
- */
-
- for (j = 0U; j < (u32)32; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = (1U << j);
-
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (u32)32; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = (u32) RotateLeft(Val, 32U);
- }
-
- /*
- * Restore the reference 'val' to the
- * initial value
- */
- Val = 1U << j;
-
- /* Read the values from each location that was
- * written */
- for (I = 0U; I < (u32)32; I++) {
- /* read memory location */
-
- WordMem32 = *(Addr+I);
-
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val = (u32)RotateLeft(Val, 32U);
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible
- * initial test Patterns for walking zeros test
- */
-
- for (j = 0U; j < (u32)32; j++) {
-
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = ~(1U << j);
-
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (u32)32; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = ~((u32)RotateLeft(~Val, 32U));
- }
-
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
-
- Val = ~(1U << j);
-
- /* Read the values from each location that was
- * written */
- for (I = 0U; I < (u32)32; I++) {
- /* read memory location */
- WordMem32 = *(Addr+I);
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = ~((u32)RotateLeft(~Val, 32U));
- }
-
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- Val = (u32) (~((INTPTR) (&Addr[I])));
- *(Addr+I) = Val;
- }
-
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < Words; I++) {
- /* Read the location */
- WordMem32 = *(Addr+I);
- Val = (u32) (~((INTPTR) (&Addr[I])));
-
- if ((WordMem32 ^ Val) != 0x00000000U) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
-
- if (Pattern == (u32)0) {
- Val = 0xDEADBEEFU;
- }
- else {
- Val = Pattern;
- }
-
- /*
- * Fill the memory with fixed Pattern
- */
-
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- }
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed Pattern
- */
-
- for (I = 0U; I < Words; I++) {
-
- /* read memory location */
-
- WordMem32 = *(Addr+I);
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
-End_Label:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 16-bit wide memory test.
-*
-* @param Addr: pointer to the region of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant Pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: type of test selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-* @note Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u16 Val;
- u16 FirtVal;
- u16 WordMem16;
- s32 Status = 0;
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
- FirtVal = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * selectthe proper Subtest(s)
- */
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from 'FirtVal'
- */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val++;
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = FirtVal;
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference val
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val++;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial test
- * Patterns for walking ones test
- */
-
- for (j = 0U; j < (u32)16; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = (u16)((u32)1 << j);
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (u32)16; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = (u16)RotateLeft(Val, 16U);
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u16)((u32)1 << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < (u32)16; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = (u16)RotateLeft(Val, 16U);
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking zeros test
- */
-
- for (j = 0U; j < (u32)16; j++) {
- /*
- * Generate an initial value for walking ones
- * test to test for bad
- * data bits
- */
-
- Val = ~(1U << j);
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (u32)16; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = ~((u16)RotateLeft(~Val, 16U));
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = ~(1U << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < (u32)16; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = ~((u16)RotateLeft(~Val, 16U));
- }
-
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- Val = (u16) (~((INTPTR)(&Addr[I])));
- *(Addr+I) = Val;
- }
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- Val = (u16) (~((INTPTR) (&Addr[I])));
- if ((WordMem16 ^ Val) != 0x0000U) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
- if (Pattern == (u16)0) {
- Val = 0xDEADU;
- }
- else {
- Val = Pattern;
- }
-
- /*
- * Fill the memory with fixed pattern
- */
-
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- }
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed pattern
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
-End_Label:
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 8-bit wide memory test.
-*
-* @param Addr: pointer to the region of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: type of test selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u8 Val;
- u8 FirtVal;
- u8 WordMem8;
- s32 Status = 0;
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
- FirtVal = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * select the proper Subtest(s)
- */
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from 'FirtVal'
- */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val++;
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = FirtVal;
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference
- * Val
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val++;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking ones test
- */
-
- for (j = 0U; j < (u32)8; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
- Val = (u8)((u32)1 << j);
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
- for (I = 0U; I < (u32)8; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = (u8)RotateLeft(Val, 8U);
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u8)((u32)1 << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < (u32)8; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = (u8)RotateLeft(Val, 8U);
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible initial test
- * Patterns for walking zeros test
- */
-
- for (j = 0U; j < (u32)8; j++) {
- /*
- * Generate an initial value for walking ones test to test
- * for bad data bits
- */
- Val = (u8) (~(1U << j));
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
- for (I = 0U; I < (u32)8; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = ~((u8)RotateLeft(~Val, 8U));
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u8) (~(1U << j));
- /* Read the values from each location that was written */
- for (I = 0U; I < (u32)8; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val = ~((u8)RotateLeft(~Val, 8U));
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- Val = (u8) (~((INTPTR) (&Addr[I])));
- *(Addr+I) = Val;
- }
-
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- Val = (u8) (~((INTPTR) (&Addr[I])));
- if ((WordMem8 ^ Val) != 0x00U) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
-
- if (Pattern == (u8)0) {
- Val = 0xA5U;
- }
- else {
- Val = Pattern;
- }
- /*
- * Fill the memory with fixed Pattern
- */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- }
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed Pattern
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
-End_Label:
- return Status;
-}
-#endif
-
-/*****************************************************************************/
-/**
-*
-* @brief Rotates the provided value to the left one bit position
-*
-* @param Input is value to be rotated to the left
-* @param Width is the number of bits in the input data
-*
-* @return The resulting unsigned long value of the rotate left
-*
-*
-*****************************************************************************/
-static u32 RotateLeft(u32 Input, u8 Width)
-{
- u32 Msb;
- u32 ReturnVal;
- u32 WidthMask;
- u32 MsbMask;
- u32 LocalInput = Input;
-
- /*
- * set up the WidthMask and the MsbMask
- */
-
- MsbMask = 1U << (Width - 1U);
-
- WidthMask = (MsbMask << (u32)1) - (u32)1;
-
- /*
- * set the Width of the Input to the correct width
- */
-
- LocalInput = LocalInput & WidthMask;
-
- Msb = LocalInput & MsbMask;
-
- ReturnVal = LocalInput << 1U;
-
- if (Msb != 0x00000000U) {
- ReturnVal = ReturnVal | (u32)0x00000001;
- }
-
- ReturnVal = ReturnVal & WidthMask;
-
- return ReturnVal;
-
-}
-
-#ifdef ROTATE_RIGHT
-/*****************************************************************************/
-/**
-*
-* @brief Rotates the provided value to the right one bit position
-*
-* @param Input: value to be rotated to the right
-* @param Width: number of bits in the input data
-*
-* @return
-* The resulting u32 value of the rotate right
-*
-*****************************************************************************/
-static u32 RotateRight(u32 Input, u8 Width)
-{
- u32 Lsb;
- u32 ReturnVal;
- u32 WidthMask;
- u32 MsbMask;
- u32 LocalInput = Input;
- /*
- * set up the WidthMask and the MsbMask
- */
-
- MsbMask = 1U << (Width - 1U);
-
- WidthMask = (MsbMask << 1U) - 1U;
-
- /*
- * set the width of the input to the correct width
- */
-
- LocalInput = LocalInput & WidthMask;
-
- ReturnVal = LocalInput >> 1U;
-
- Lsb = LocalInput & 0x00000001U;
-
- if (Lsb != 0x00000000U) {
- ReturnVal = ReturnVal | MsbMask;
- }
-
- ReturnVal = ReturnVal & WidthMask;
-
- return ReturnVal;
-
-}
-#endif /* ROTATE_RIGHT */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/94/a0db56585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/94/a0db56585243001d18b399c1eb9b3628
deleted file mode 100644
index 2c4d446..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/94/a0db56585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,92 +0,0 @@
-###############################################################################
-# Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
-# SPDX-License-Identifier: MIT
-###############################################################################
-DRIVER_LIB_VERSION = v1.0
-
-include config.make
-
-AS=$(ASSEMBLER)
-COMPILER=$(COMPILER)
-ARCHIVER=$(ARCHIVER)
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-INCLUDEFILES=*.h
-
-SRCFILES:=$(wildcard *.c)
-ASSEMBLY_SRCFILES:=$(wildcard *.S)
-
-COBJS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(wildcard *.c))))
-AOBJS1 = $(RELEASEDIR)/asm_vectors.o
-AOBJS2 = $(RELEASEDIR)/translation_table.o
-AOBJS3 = $(RELEASEDIR)/boot.o
-OBJS = $(COBJS) $(AOBJS1) $(AOBJS2) $(AOBJS3)
-
-ASOURCES1 = asm_vectors.S
-ASOURCES2 = translation_table.S
-ASOURCES3 = boot.S
-
-OBJECTS = $(OBJS)
-
-libs: standalone_libs
-standalone_libs: ${OBJECTS}
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-ASSEMBLY_DEPFILES := $(ASSEMBLY_SRCFILES:%.S=$(RELEASEDIR)%.d)
-
-include $(wildcard $(ASSEMBLY_DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(AOBJS1): $(ASOURCES1)
-ifeq ($(findstring asm_vectors.S,$(wildcard *.S)),asm_vectors.S)
- ${COMPILER} $(INCLUDES) --target=aarch64-arm-none-eabi -E -o asm_vectors_post.s asm_vectors.S
-endif
- ${AS} --cpu=8-A.64 --fpu=fp-armv8 -o $*.o asm_vectors_post.s --depend=$*.d
-
-$(AOBJS2): $(ASOURCES2)
-ifeq ($(findstring translation_table.S,$(wildcard *.S)),translation_table.S)
- ${COMPILER} $(INCLUDES) --target=aarch64-arm-none-eabi -E -o translation_table_post.s translation_table.S
-endif
- ${AS} --cpu=8-A.64 --fpu=fp-armv8 -o $*.o translation_table_post.s --depend=$*.d
-
-$(AOBJS3): $(ASOURCES3)
-ifeq ($(findstring boot.S,$(wildcard *.S)),boot.S)
- ${COMPILER} $(INCLUDES) --target=aarch64-arm-none-eabi -E -o boot_post.s boot.S
-endif
- ${AS} --cpu=8-A.64 --fpu=fp-armv8 -o $*.o boot_post.s --depend=$*.d
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} -c $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $<
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h)) $(addprefix $(INCLUDEDIR), $(subst includes_ps/,,$(wildcard includes_ps/*.h)))
-
-
-
-$(INCLUDEDIR)%.h: includes_ps/%.h
- $(CP) $< $@
-
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf $(DEPFILES)
- rm -rf $(ASSEMBLY_DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/95/00a354565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/95/00a354565243001d18b399c1eb9b3628
deleted file mode 100644
index e8b87b5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/95/00a354565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,176 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_assert.h
-*
-* @addtogroup common_assert_apis Assert APIs and Macros
-*
-* The xil_assert.h file contains assert related functions and macros.
-* Assert APIs/Macros specifies that a application program satisfies certain
-* conditions at particular points in its execution. These function can be
-* used by application programs to ensure that, application code is satisfying
-* certain conditions.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 First release
-* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_ASSERT_H /* prevent circular inclusions */
-#define XIL_ASSERT_H /* by using protection macros */
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-
-
-/************************** Constant Definitions *****************************/
-
-#define XIL_ASSERT_NONE 0U
-#define XIL_ASSERT_OCCURRED 1U
-#define XNULL NULL
-
-extern u32 Xil_AssertStatus;
-extern s32 Xil_AssertWait;
-extern void Xil_Assert(const char8 *File, s32 Line);
-/**
- *@endcond
- */
-void XNullHandler(void *NullParameter);
-
-/**
- * This data type defines a callback to be invoked when an
- * assert occurs. The callback is invoked only when asserts are enabled
- */
-typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#ifndef NDEBUG
-
-/*****************************************************************************/
-/**
-* @brief This assert macro is to be used for void functions. This in
-* conjunction with the Xil_AssertWait boolean can be used to
-* accommodate tests so that asserts which fail allow execution to
-* continue.
-*
-* @param Expression: expression to be evaluated. If it evaluates to
-* false, the assert occurs.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertVoid(Expression) \
-{ \
- if (Expression) { \
- Xil_AssertStatus = XIL_ASSERT_NONE; \
- } else { \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* @brief This assert macro is to be used for functions that do return a
-* value. This in conjunction with the Xil_AssertWait boolean can be
-* used to accommodate tests so that asserts which fail allow execution
-* to continue.
-*
-* @param Expression: expression to be evaluated. If it evaluates to false,
-* the assert occurs.
-*
-* @return Returns 0 unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertNonvoid(Expression) \
-{ \
- if (Expression) { \
- Xil_AssertStatus = XIL_ASSERT_NONE; \
- } else { \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return 0; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* @brief Always assert. This assert macro is to be used for void functions.
-* Use for instances where an assert should always occur.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertVoidAlways() \
-{ \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return; \
-}
-
-/*****************************************************************************/
-/**
-* @brief Always assert. This assert macro is to be used for functions that
-* do return a value. Use for instances where an assert should always
-* occur.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertNonvoidAlways() \
-{ \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return 0; \
-}
-
-
-#else
-
-#define Xil_AssertVoid(Expression)
-#define Xil_AssertVoidAlways()
-#define Xil_AssertNonvoid(Expression)
-#define Xil_AssertNonvoidAlways()
-
-#endif
-
-/************************** Function Prototypes ******************************/
-
-void Xil_AssertSetCallback(Xil_AssertCallback Routine);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_assert_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/95/1089c7565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/95/1089c7565243001d18b399c1eb9b3628
deleted file mode 100644
index 20f0886..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/95/1089c7565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,42 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
- .globl _mcount
- .text
- .align 2
- .ent _mcount
-
- #ifndef PROFILE_NO_GRAPH
-
-_mcount:
- addi r1, r1, -48
- swi r11, r1, 44
- swi r12, r1, 40
- swi r5, r1, 36
- swi r6, r1, 32
- swi r7, r1, 28
- swi r8, r1, 24
- swi r9, r1, 20
- swi r10, r1, 16
- swi r15, r1, 12
- add r5, r0, r15
- brlid r15, mcount
- add r6, r0, r16
-
- lwi r11, r1, 44
- lwi r12, r1, 40
- lwi r5, r1, 36
- lwi r6, r1, 32
- lwi r7, r1, 28
- lwi r8, r1, 24
- lwi r9, r1, 20
- lwi r10, r1, 16
- lwi r15, r1, 12
- rtsd r15, 4
- addi r1, r1, 48
-
- #endif /* PROFILE_NO_GRAPH */
-
- .end _mcount
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/95/605594545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/95/605594545243001d18b399c1eb9b3628
deleted file mode 100644
index cb45d29..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/95/605594545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,90 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xdmaps_hw.c
-* @addtogroup dmaps_v2_8
-* @{
-*
-* This file contains the implementation of the interface reset functionality
-* for XDmaPs driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.06a kpc 10/07/13 First release
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xdmaps_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-#ifndef XDMAPS_MAX_WAIT
-#define XDMAPS_MAX_WAIT 4000
-#endif
-/************************** Function Prototypes *****************************/
-
-/************************** Variable Definitions ****************************/
-
-/*****************************************************************************/
-/**
-* This function perform the reset sequence to the given dmaps interface by
-* configuring the appropriate control bits in the dmaps specifc registers
-* the dmaps reset squence involves the following steps
-* Disable all the interuupts
-* Clear the pending interrupts
-* Kill all the active channel threads
-* Kill the manager thread
-*
-* @param BaseAddress of the interface
-*
-* @return N/A
-*
-* @note
-* This function will not modify the slcr registers that are relavant for
-* dmaps controller
-******************************************************************************/
-void XDmaPs_ResetHw(u32 BaseAddress)
-{
- u32 DbgInst;
- u32 WaitCount = 0;
- u32 ChanIndex;
-
- /* Disable all the interrupts */
- XDmaPs_WriteReg(BaseAddress, XDMAPS_INTEN_OFFSET, 0x00);
- /* Clear the interrupts */
- XDmaPs_WriteReg(BaseAddress, XDMAPS_INTCLR_OFFSET, XDMAPS_INTCLR_ALL_MASK);
- /* Kill the dma channel threads */
- for (ChanIndex=0; ChanIndex < XDMAPS_CHANNELS_PER_DEV; ChanIndex++) {
- while ((XDmaPs_ReadReg(BaseAddress, XDMAPS_DBGSTATUS_OFFSET)
- & XDMAPS_DBGSTATUS_BUSY)
- && (WaitCount < XDMAPS_MAX_WAIT))
- WaitCount++;
-
- DbgInst = XDmaPs_DBGINST0(0, 0x01, ChanIndex, 1);
- XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
- XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);
- XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
- }
- /* Kill the manager thread */
- DbgInst = XDmaPs_DBGINST0(0, 0x01, 0, 0);
- XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
- XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);
- XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
-}
-
-
-
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/95/613528595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/95/613528595243001d18b399c1eb9b3628
deleted file mode 100644
index 6f009c6..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/95/613528595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,24 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 2021.2
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2022 Xilinx, Inc. All Rights Reserved.
-* SPDX-License-Identifier: MIT
-
-*
-* Description: Configurations for Standalone BSP
-*
-*******************************************************************/
-
-#ifndef BSPCONFIG_H /* prevent circular inclusions */
-#define BSPCONFIG_H /* by using protection macros */
-
-#define MICROBLAZE_PVR_NONE
-
-/* Definition for hard-float ABI */
-#define FPU_HARD_FLOAT_ABI_ENABLED 1
-
-#endif /*end of __BSPCONFIG_H_*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/95/71050a565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/95/71050a565243001d18b399c1eb9b3628
deleted file mode 100644
index 9d17f5c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/95/71050a565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,86 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xtime_l.h
-* @addtogroup a9_time_apis Cortex A9 Time Functions
-*
-* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This
-* counter increases by one at every two processor cycles. These functions can
-* be used to get/set time in the global timer.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 1.00a rp/sdm 11/03/09 Initial release.
-* 3.06a sgd 05/15/12 Updated get/set time functions to make use Global Timer
-* 3.06a asa 06/17/12 Reverted back the changes to make use Global Timer.
-* 3.07a sgd 07/05/12 Updated get/set time functions to make use Global Timer
-* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep
-* implementation
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
-* displaying same warnings multiple times. It fixes CR#1090562.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/28/09 Initial release
-* 4.1 asa 05/09/14 Ensured that the address uses for cache test is aligned
-* cache line.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
-* 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors.
-*
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xadcps.h"
-
-/************************** Constant Definitions ****************************/
-
-/*
- * The following constant defines the test value to be written
- * to the Alarm Threshold Register
- */
-#define XADCPS_ATR_TEST_VALUE 0x55U
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-/*****************************************************************************/
-/**
-*
-* Run a self-test on the driver/device. The test
-* - Resets the device,
-* - Writes a value into the Alarm Threshold register and reads it back
-* for comparison.
-* - Resets the device again.
-*
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return
-* - XST_SUCCESS if the value read from the Alarm Threshold
-* register is the same as the value written.
-* - XST_FAILURE Otherwise
-*
-* @note This is a destructive test in that resets of the device are
-* performed. Refer to the device specification for the
-* device status after the reset operation.
-*
-******************************************************************************/
-int XAdcPs_SelfTest(XAdcPs *InstancePtr)
-{
- int Status;
- u32 RegValue;
-
- /*
- * Assert the argument
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- /*
- * Reset the device to get it back to its default state
- */
- XAdcPs_Reset(InstancePtr);
-
- /*
- * Write a value into the Alarm Threshold registers, read it back, and
- * do the comparison
- */
- XAdcPs_SetAlarmThreshold(InstancePtr, XADCPS_ATR_VCCINT_UPPER,
- XADCPS_ATR_TEST_VALUE);
- RegValue = XAdcPs_GetAlarmThreshold(InstancePtr, XADCPS_ATR_VCCINT_UPPER);
-
- if (RegValue == XADCPS_ATR_TEST_VALUE) {
- Status = XST_SUCCESS;
- } else {
- Status = XST_FAILURE;
- }
-
- /*
- * Reset the device again to its default state.
- */
- XAdcPs_Reset(InstancePtr);
- /*
- * Return the test result.
- */
- return Status;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/96/c077e5535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/96/c077e5535243001d18b399c1eb9b3628
deleted file mode 100644
index d61e2b5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/96/c077e5535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,118 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xsdps_core.h
-* @addtogroup sdps_v3_13
-* @{
-*
-* This header file contains the identifiers and basic HW access driver
-* functions (or macros) that can be used to access the device. Other driver
-* functions are defined in xsdps.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 3.9 mn 03/03/20 Restructured the code for more readability and modularity
-* mn 03/16/20 Move XSdPs_Select_Card API to User APIs
-* 3.12 sk 01/28/21 Added support for non-blocking write.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 4.00a sgd 02/28/13 Initial release
-* 6.00a kc 07/30/13 Added FSBL_DEBUG_RSA to print more RSA buffers
-* Fix for CR#724165 - Partition Header used by FSBL is
-* not authenticated
-* Fix for CR#724166 - FSBL doesn’t use PPK authenticated
-* by Boot ROM for authenticating
-* the Partition images
-* Fix for CR#722979 - Provide customer-friendly
-* changelogs in FSBL
-* 9.00a kc 04/16/14 Fix for CR#724166 - SetPpk() will fail on secure
-* fallback unless FSBL* and FSBL are
-* identical in length
-* Fix for CR#791245 - Use of xilrsa in FSBL
-*
-*
-* @note
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#ifdef RSA_SUPPORT
-#include "fsbl.h"
-#include "rsa.h"
-#include "xilrsa.h"
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-#include "xwdtps.h"
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-#ifdef XPAR_XWDTPS_0_BASEADDR
-extern XWdtPs Watchdog; /* Instance of WatchDog Timer */
-#endif
-
-
-/************************** Variable Definitions *****************************/
-
-static u8 *PpkModular;
-static u8 *PpkModularEx;
-static u32 PpkExp;
-static u32 PpkAlreadySet=0;
-
-extern u32 FsblLength;
-
-void FsblPrintArray (u8 *Buf, u32 Len, char *Str)
-{
-#ifdef FSBL_DEBUG_RSA
- int Index;
- fsbl_printf(DEBUG_INFO, "%s START\r\n", Str);
- for (Index=0;Index
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 01/12/12 Initial version
-* 4.2 pkp 07/21/14 Included xil_types.h file which contains definition for
-* u32 which resolves issue of CR#805869
-* 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-*
-*
-******************************************************************************/
-
-/**
-*@cond nocomments
-*/
-
-#ifndef XIL_MMU_H
-#define XIL_MMU_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/* Memory type */
-#define NORM_NONCACHE 0x11DE2 /* Normal Non-cacheable */
-#define STRONG_ORDERED 0xC02 /* Strongly ordered */
-#define DEVICE_MEMORY 0xC06 /* Device memory */
-#define RESERVED 0x0 /* reserved memory */
-
-/* Normal write-through cacheable shareable */
-#define NORM_WT_CACHE 0x16DEA
-
-/* Normal write back cacheable shareable */
-#define NORM_WB_CACHE 0x15DE6
-
-/* shareability attribute */
-#define SHAREABLE (0x1 << 16)
-#define NON_SHAREABLE (~(0x1 << 16))
-
-/* Execution type */
-#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0))
-
-/**
-*@endcond
-*/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
-void Xil_EnableMMU(void);
-void Xil_DisableMMU(void);
-void* Xil_MemMap(UINTPTR PhysAddr, size_t size, u32 flags);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_MMU_H */
-/**
-* @} End of "addtogroup a9_mmu_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/97/d1f7c7595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/97/d1f7c7595243001d18b399c1eb9b3628
deleted file mode 100644
index 1f5f962..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/97/d1f7c7595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,33 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 2021.2
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2022 Xilinx, Inc. All Rights Reserved.
-* SPDX-License-Identifier: MIT
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xuartps.h"
-
-/*
-* The configuration table for devices
-*/
-
-XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES] =
-{
- {
- XPAR_PS7_UART_1_DEVICE_ID,
- XPAR_PS7_UART_1_BASEADDR,
- XPAR_PS7_UART_1_UART_CLK_FREQ_HZ,
- XPAR_PS7_UART_1_HAS_MODEM
- }
-};
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/97/f0e9a1545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/97/f0e9a1545243001d18b399c1eb9b3628
deleted file mode 100644
index 9698ed3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/97/f0e9a1545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1133 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
- *
- * @file xemacps_control.c
-* @addtogroup emacps_v3_15
-* @{
- *
- * Functions in this file implement general purpose command and control related
- * functionality. See xemacps.h for a detailed description of the driver.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -------------------------------------------------------
- * 1.00a wsy 01/10/10 First release
- * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
- * register. Added a new API for setting the BURST length
- * in DMACR register.
- * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
- * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
- * 3.0 hk 02/20/15 Added support for jumbo frames.
- * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
- *
- *****************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xemacps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
- * Set the MAC address for this driver/device. The address is a 48-bit value.
- * The device must be stopped before calling this function.
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param AddressPtr is a pointer to a 6-byte MAC address.
- * @param Index is a index to which MAC (1-4) address.
- *
- * @return
- * - XST_SUCCESS if the MAC address was set successfully
- * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
- *
- *****************************************************************************/
-LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
-{
- u32 MacAddr;
- u8 *Aptr = (u8 *)(void *)AddressPtr;
- u8 IndexLoc = Index;
- LONG Status;
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(Aptr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
-
- /* Be sure device has been stopped */
- if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
- Status = (LONG)(XST_DEVICE_IS_STARTED);
- }
- else{
- /* Index ranges 1 to 4, for offset calculation is 0 to 3. */
- IndexLoc--;
-
- /* Set the MAC bits [31:0] in BOT */
- MacAddr = *(Aptr);
- MacAddr |= ((u32)(*(Aptr+1)) << 8U);
- MacAddr |= ((u32)(*(Aptr+2)) << 16U);
- MacAddr |= ((u32)(*(Aptr+3)) << 24U);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- ((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
-
- /* There are reserved bits in TOP so don't affect them */
- MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
-
- MacAddr &= (u32)(~XEMACPS_LADDR_MACH_MASK);
-
- /* Set MAC bits [47:32] in TOP */
- MacAddr |= (u32)(*(Aptr+4));
- MacAddr |= (u32)(*(Aptr+5)) << 8U;
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
-
- Status = (LONG)(XST_SUCCESS);
- }
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Get the MAC address for this driver/device.
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param AddressPtr is an output parameter, and is a pointer to a buffer into
- * which the current MAC address will be copied.
- * @param Index is a index to which MAC (1-4) address.
- *
- *****************************************************************************/
-void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
-{
- u32 MacAddr;
- u8 *Aptr = (u8 *)(void *)AddressPtr;
- u8 IndexLoc = Index;
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(Aptr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
-
- /* Index ranges 1 to 4, for offset calculation is 0 to 3. */
- IndexLoc--;
-
- MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- ((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)));
- *Aptr = (u8) MacAddr;
- *(Aptr+1) = (u8) (MacAddr >> 8U);
- *(Aptr+2) = (u8) (MacAddr >> 16U);
- *(Aptr+3) = (u8) (MacAddr >> 24U);
-
- /* Read MAC bits [47:32] in TOP */
- MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
- *(Aptr+4) = (u8) MacAddr;
- *(Aptr+5) = (u8) (MacAddr >> 8U);
-}
-
-
-/*****************************************************************************/
-/**
- * Set 48-bit MAC addresses in hash table.
- * The device must be stopped before calling this function.
- *
- * The hash address register is 64 bits long and takes up two locations in
- * the memory map. The least significant bits are stored in hash register
- * bottom and the most significant bits in hash register top.
- *
- * The unicast hash enable and the multicast hash enable bits in the network
- * configuration register enable the reception of hash matched frames. The
- * destination address is reduced to a 6 bit index into the 64 bit hash
- * register using the following hash function. The hash function is an XOR
- * of every sixth bit of the destination address.
- *
- *
- *
- * where f[HOSTCLK] is the bus clock frequency in MHz, and f[MDC] is the
- * MDIO clock frequency in MHz to the PHY. Typically, f[MDC] should not
- * exceed 2.5 MHz. Some PHYs can tolerate faster speeds which means faster
- * access. Here is the table to show values to generate MDC,
- *
- *
- * 000 : divide pclk by 8 (pclk up to 20 MHz)
- * 001 : divide pclk by 16 (pclk up to 40 MHz)
- * 010 : divide pclk by 32 (pclk up to 80 MHz)
- * 011 : divide pclk by 48 (pclk up to 120 MHz)
- * 100 : divide pclk by 64 (pclk up to 160 MHz)
- * 101 : divide pclk by 96 (pclk up to 240 MHz)
- * 110 : divide pclk by 128 (pclk up to 320 MHz)
- * 111 : divide pclk by 224 (pclk up to 540 MHz)
- *
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param Divisor is the divisor to set. Range is 0b000 to 0b111.
- *
- *****************************************************************************/
-void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor)
-{
- u32 Reg;
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Divisor <= (XEmacPs_MdcDiv)0x7); /* only last three bits are valid */
-
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCFG_OFFSET);
- /* clear these three bits, could be done with mask */
- Reg &= (u32)(~XEMACPS_NWCFG_MDCCLKDIV_MASK);
-
- Reg |= ((u32)Divisor << XEMACPS_NWCFG_MDC_SHIFT_MASK);
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCFG_OFFSET, Reg);
-}
-
-
-/*****************************************************************************/
-/**
-* Read the current value of the PHY register indicated by the PhyAddress and
-* the RegisterNum parameters. The MAC provides the driver with the ability to
-* talk to a PHY that adheres to the Media Independent Interface (MII) as
-* defined in the IEEE 802.3 standard.
-*
-* Prior to PHY access with this function, the user should have setup the MDIO
-* clock with XEmacPs_SetMdioDivisor().
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-* @param PhyAddress is the address of the PHY to be read (supports multiple
-* PHYs)
-* @param RegisterNum is the register number, 0-31, of the specific PHY register
-* to read
-* @param PhyDataPtr is an output parameter, and points to a 16-bit buffer into
-* which the current value of the register will be copied.
-*
-* @return
-*
-* - XST_SUCCESS if the PHY was read from successfully
-* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
-*
-* @note
-*
-* This function is not thread-safe. The user must provide mutually exclusive
-* access to this function if there are to be multiple threads that can call it.
-*
-* There is the possibility that this function will not return if the hardware
-* is broken (i.e., it never sets the status bit indicating that the read is
-* done). If this is of concern to the user, the user should provide a mechanism
-* suitable to their needs for recovery.
-*
-* For the duration of this function, all host interface reads and writes are
-* blocked to the current XEmacPs instance.
-*
-******************************************************************************/
-LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
- u32 RegisterNum, u16 *PhyDataPtr)
-{
- u32 Mgtcr;
- volatile u32 Ipisr;
- u32 IpReadTemp;
- LONG Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /* Make sure no other PHY operation is currently in progress */
- if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWSR_OFFSET) &
- XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
- Status = (LONG)(XST_EMAC_MII_BUSY);
- } else {
-
- /* Construct Mgtcr mask for the operation */
- Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_R_MASK |
- (PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
- (RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK);
-
- /* Write Mgtcr and wait for completion */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
-
- do {
- Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWSR_OFFSET);
- IpReadTemp = Ipisr;
- } while ((IpReadTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
-
- /* Read data */
- *PhyDataPtr = (u16)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_PHYMNTNC_OFFSET);
- Status = (LONG)(XST_SUCCESS);
- }
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
-* Write data to the specified PHY register. The Ethernet driver does not
-* require the device to be stopped before writing to the PHY. Although it is
-* probably a good idea to stop the device, it is the responsibility of the
-* application to deem this necessary. The MAC provides the driver with the
-* ability to talk to a PHY that adheres to the Media Independent Interface
-* (MII) as defined in the IEEE 802.3 standard.
-*
-* Prior to PHY access with this function, the user should have setup the MDIO
-* clock with XEmacPs_SetMdioDivisor().
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-* @param PhyAddress is the address of the PHY to be written (supports multiple
-* PHYs)
-* @param RegisterNum is the register number, 0-31, of the specific PHY register
-* to write
-* @param PhyData is the 16-bit value that will be written to the register
-*
-* @return
-*
-* - XST_SUCCESS if the PHY was written to successfully. Since there is no error
-* status from the MAC on a write, the user should read the PHY to verify the
-* write was successful.
-* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
-*
-* @note
-*
-* This function is not thread-safe. The user must provide mutually exclusive
-* access to this function if there are to be multiple threads that can call it.
-*
-* There is the possibility that this function will not return if the hardware
-* is broken (i.e., it never sets the status bit indicating that the write is
-* done). If this is of concern to the user, the user should provide a mechanism
-* suitable to their needs for recovery.
-*
-* For the duration of this function, all host interface reads and writes are
-* blocked to the current XEmacPs instance.
-*
-******************************************************************************/
-LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
- u32 RegisterNum, u16 PhyData)
-{
- u32 Mgtcr;
- volatile u32 Ipisr;
- u32 IpWriteTemp;
- LONG Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /* Make sure no other PHY operation is currently in progress */
- if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWSR_OFFSET) &
- XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
- Status = (LONG)(XST_EMAC_MII_BUSY);
- } else {
- /* Construct Mgtcr mask for the operation */
- Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_W_MASK |
- (PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
- (RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK) | (u32)PhyData;
-
- /* Write Mgtcr and wait for completion */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
-
- do {
- Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWSR_OFFSET);
- IpWriteTemp = Ipisr;
- } while ((IpWriteTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
-
- Status = (LONG)(XST_SUCCESS);
- }
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* API to update the Burst length in the DMACR register.
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-* @param BLength is the length in bytes for the dma burst.
-*
-* @return None
-*
-******************************************************************************/
-void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength)
-{
- u32 Reg;
- u32 RegUpdateVal = 0;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid((BLength == XEMACPS_SINGLE_BURST) ||
- (BLength == XEMACPS_4BYTE_BURST) ||
- (BLength == XEMACPS_8BYTE_BURST) ||
- (BLength == XEMACPS_16BYTE_BURST));
-
- switch (BLength) {
- case XEMACPS_SINGLE_BURST:
- RegUpdateVal = XEMACPS_DMACR_SINGLE_AHB_BURST;
- break;
-
- case XEMACPS_4BYTE_BURST:
- RegUpdateVal = XEMACPS_DMACR_INCR4_AHB_BURST;
- break;
-
- case XEMACPS_8BYTE_BURST:
- RegUpdateVal = XEMACPS_DMACR_INCR8_AHB_BURST;
- break;
-
- case XEMACPS_16BYTE_BURST:
- RegUpdateVal = XEMACPS_DMACR_INCR16_AHB_BURST;
- break;
- }
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_DMACR_OFFSET);
-
- Reg &= (u32)(~XEMACPS_DMACR_BLENGTH_MASK);
- Reg |= RegUpdateVal;
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
- Reg);
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/98/7024d8595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/98/7024d8595243001d18b399c1eb9b3628
deleted file mode 100644
index 0e49078..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/98/7024d8595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,31 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 2021.2
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2022 Xilinx, Inc. All Rights Reserved.
-* SPDX-License-Identifier: MIT
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xusbps.h"
-
-/*
-* The configuration table for devices
-*/
-
-XUsbPs_Config XUsbPs_ConfigTable[XPAR_XUSBPS_NUM_INSTANCES] =
-{
- {
- XPAR_PS7_USB_0_DEVICE_ID,
- XPAR_PS7_USB_0_BASEADDR
- }
-};
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/98/91b6c7535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/98/91b6c7535243001d18b399c1eb9b3628
deleted file mode 100644
index 4951140..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/98/91b6c7535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,648 +0,0 @@
-#ifndef XPARAMETERS_H /* prevent circular inclusions */
-#define XPARAMETERS_H /* by using protection macros */
-
-/* Definition for CPU ID */
-#define XPAR_CPU_ID 0U
-
-/* Definitions for peripheral PS7_CORTEXA9_0 */
-#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_CORTEXA9_0 */
-#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
-
-
-/******************************************************************/
-
-#include "xparameters_ps.h"
-
-#define STDIN_BASEADDRESS 0xE0001000
-#define STDOUT_BASEADDRESS 0xE0001000
-
-/******************************************************************/
-
-/* Platform specific definitions */
-#define PLATFORM_ZYNQ
-
-/* Definitions for sleep timer configuration */
-#define XSLEEP_TIMER_IS_DEFAULT_TIMER
-
-
-/******************************************************************/
-
-/* Definitions for peripheral PS7_DDR_0 */
-#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
-#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
-
-
-/******************************************************************/
-
-/* Definitions for driver DEVCFG */
-#define XPAR_XDCFG_NUM_INSTANCES 1U
-
-/* Definitions for peripheral PS7_DEV_CFG_0 */
-#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0U
-#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000U
-#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FFU
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_DEV_CFG_0 */
-#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
-#define XPAR_XDCFG_0_BASEADDR 0xF8007000U
-#define XPAR_XDCFG_0_HIGHADDR 0xF80070FFU
-
-
-/******************************************************************/
-
-/* Definitions for driver DMAPS */
-#define XPAR_XDMAPS_NUM_INSTANCES 2
-
-/* Definitions for peripheral PS7_DMA_NS */
-#define XPAR_PS7_DMA_NS_DEVICE_ID 0
-#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
-#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
-
-
-/* Definitions for peripheral PS7_DMA_S */
-#define XPAR_PS7_DMA_S_DEVICE_ID 1
-#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
-#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_DMA_NS */
-#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
-#define XPAR_XDMAPS_0_BASEADDR 0xF8004000
-#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
-
-/* Canonical definitions for peripheral PS7_DMA_S */
-#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
-#define XPAR_XDMAPS_1_BASEADDR 0xF8003000
-#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
-
-
-/******************************************************************/
-
-/* Definitions for driver EMACPS */
-#define XPAR_XEMACPS_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_ETHERNET_0 */
-#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0
-#define XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000
-#define XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF
-#define XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 125000000
-#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8
-#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1
-#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8
-#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5
-#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8
-#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50
-#define XPAR_PS7_ETHERNET_0_ENET_TSU_CLK_FREQ_HZ 0
-
-
-/******************************************************************/
-
-#define XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT 0
-#define XPAR_XEMACPS_0_IS_CACHE_COHERENT 0
-/* Canonical definitions for peripheral PS7_ETHERNET_0 */
-#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID
-#define XPAR_XEMACPS_0_BASEADDR 0xE000B000
-#define XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF
-#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 125000000
-#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8
-#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
-#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 8
-#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5
-#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8
-#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50
-#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 0
-
-
-/******************************************************************/
-
-
-/* Peripheral Definitions for peripheral PS7_AFI_0 */
-#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
-#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
-
-
-/* Peripheral Definitions for peripheral PS7_AFI_1 */
-#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
-#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
-
-
-/* Peripheral Definitions for peripheral PS7_AFI_2 */
-#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
-#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
-
-
-/* Peripheral Definitions for peripheral PS7_AFI_3 */
-#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
-#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
-
-
-/* Peripheral Definitions for peripheral PS7_DDRC_0 */
-#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
-#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
-
-
-/* Peripheral Definitions for peripheral PS7_GLOBALTIMER_0 */
-#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
-#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
-
-
-/* Peripheral Definitions for peripheral PS7_GPV_0 */
-#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
-#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
-
-
-/* Peripheral Definitions for peripheral PS7_INTC_DIST_0 */
-#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
-#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
-
-
-/* Peripheral Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
-#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
-#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
-
-
-/* Peripheral Definitions for peripheral PS7_L2CACHEC_0 */
-#define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000
-#define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF
-
-
-/* Peripheral Definitions for peripheral PS7_OCMC_0 */
-#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
-#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
-
-
-/* Peripheral Definitions for peripheral PS7_PL310_0 */
-#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
-#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
-
-
-/* Peripheral Definitions for peripheral PS7_PMU_0 */
-#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
-#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
-#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
-#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
-
-
-/* Peripheral Definitions for peripheral PS7_QSPI_LINEAR_0 */
-#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
-#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF
-
-
-/* Peripheral Definitions for peripheral PS7_RAM_0 */
-#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
-#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
-
-
-/* Peripheral Definitions for peripheral PS7_RAM_1 */
-#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
-#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
-
-
-/* Peripheral Definitions for peripheral PS7_SCUC_0 */
-#define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000
-#define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC
-
-
-/* Peripheral Definitions for peripheral PS7_SLCR_0 */
-#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
-#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
-
-
-/******************************************************************/
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-/******************************************************************/
-
-/* Definitions for driver GPIO */
-#define XPAR_XGPIO_NUM_INSTANCES 12
-
-/* Definitions for peripheral AXI_GPIO_0 */
-#define XPAR_AXI_GPIO_0_BASEADDR 0x41250000
-#define XPAR_AXI_GPIO_0_HIGHADDR 0x4125FFFF
-#define XPAR_AXI_GPIO_0_DEVICE_ID 0
-#define XPAR_AXI_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_AXI_GPIO_0_IS_DUAL 1
-
-
-/* Definitions for peripheral AXI_GPIO_1 */
-#define XPAR_AXI_GPIO_1_BASEADDR 0x41260000
-#define XPAR_AXI_GPIO_1_HIGHADDR 0x4126FFFF
-#define XPAR_AXI_GPIO_1_DEVICE_ID 1
-#define XPAR_AXI_GPIO_1_INTERRUPT_PRESENT 0
-#define XPAR_AXI_GPIO_1_IS_DUAL 1
-
-
-/* Definitions for peripheral HIER_0_AXI_GPIO_0 */
-#define XPAR_HIER_0_AXI_GPIO_0_BASEADDR 0x41200000
-#define XPAR_HIER_0_AXI_GPIO_0_HIGHADDR 0x4120FFFF
-#define XPAR_HIER_0_AXI_GPIO_0_DEVICE_ID 2
-#define XPAR_HIER_0_AXI_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_HIER_0_AXI_GPIO_0_IS_DUAL 1
-
-
-/* Definitions for peripheral HIER_1_AXI_GPIO_0 */
-#define XPAR_HIER_1_AXI_GPIO_0_BASEADDR 0x41210000
-#define XPAR_HIER_1_AXI_GPIO_0_HIGHADDR 0x4121FFFF
-#define XPAR_HIER_1_AXI_GPIO_0_DEVICE_ID 3
-#define XPAR_HIER_1_AXI_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_HIER_1_AXI_GPIO_0_IS_DUAL 1
-
-
-/* Definitions for peripheral HIER_2_AXI_GPIO_0 */
-#define XPAR_HIER_2_AXI_GPIO_0_BASEADDR 0x41220000
-#define XPAR_HIER_2_AXI_GPIO_0_HIGHADDR 0x4122FFFF
-#define XPAR_HIER_2_AXI_GPIO_0_DEVICE_ID 4
-#define XPAR_HIER_2_AXI_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_HIER_2_AXI_GPIO_0_IS_DUAL 1
-
-
-/* Definitions for peripheral HIER_3_AXI_GPIO_0 */
-#define XPAR_HIER_3_AXI_GPIO_0_BASEADDR 0x41230000
-#define XPAR_HIER_3_AXI_GPIO_0_HIGHADDR 0x4123FFFF
-#define XPAR_HIER_3_AXI_GPIO_0_DEVICE_ID 5
-#define XPAR_HIER_3_AXI_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_HIER_3_AXI_GPIO_0_IS_DUAL 1
-
-
-/* Definitions for peripheral HIER_4_AXI_GPIO_0 */
-#define XPAR_HIER_4_AXI_GPIO_0_BASEADDR 0x41240000
-#define XPAR_HIER_4_AXI_GPIO_0_HIGHADDR 0x4124FFFF
-#define XPAR_HIER_4_AXI_GPIO_0_DEVICE_ID 6
-#define XPAR_HIER_4_AXI_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_HIER_4_AXI_GPIO_0_IS_DUAL 1
-
-
-/* Definitions for peripheral HIER_5_AXI_GPIO_0 */
-#define XPAR_HIER_5_AXI_GPIO_0_BASEADDR 0x41270000
-#define XPAR_HIER_5_AXI_GPIO_0_HIGHADDR 0x4127FFFF
-#define XPAR_HIER_5_AXI_GPIO_0_DEVICE_ID 7
-#define XPAR_HIER_5_AXI_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_HIER_5_AXI_GPIO_0_IS_DUAL 1
-
-
-/* Definitions for peripheral HIER_6_AXI_GPIO_0 */
-#define XPAR_HIER_6_AXI_GPIO_0_BASEADDR 0x41280000
-#define XPAR_HIER_6_AXI_GPIO_0_HIGHADDR 0x4128FFFF
-#define XPAR_HIER_6_AXI_GPIO_0_DEVICE_ID 8
-#define XPAR_HIER_6_AXI_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_HIER_6_AXI_GPIO_0_IS_DUAL 1
-
-
-/* Definitions for peripheral HIER_7_AXI_GPIO_0 */
-#define XPAR_HIER_7_AXI_GPIO_0_BASEADDR 0x41290000
-#define XPAR_HIER_7_AXI_GPIO_0_HIGHADDR 0x4129FFFF
-#define XPAR_HIER_7_AXI_GPIO_0_DEVICE_ID 9
-#define XPAR_HIER_7_AXI_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_HIER_7_AXI_GPIO_0_IS_DUAL 1
-
-
-/* Definitions for peripheral HIER_8_AXI_GPIO_0 */
-#define XPAR_HIER_8_AXI_GPIO_0_BASEADDR 0x412A0000
-#define XPAR_HIER_8_AXI_GPIO_0_HIGHADDR 0x412AFFFF
-#define XPAR_HIER_8_AXI_GPIO_0_DEVICE_ID 10
-#define XPAR_HIER_8_AXI_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_HIER_8_AXI_GPIO_0_IS_DUAL 1
-
-
-/* Definitions for peripheral HIER_9_AXI_GPIO_0 */
-#define XPAR_HIER_9_AXI_GPIO_0_BASEADDR 0x412B0000
-#define XPAR_HIER_9_AXI_GPIO_0_HIGHADDR 0x412BFFFF
-#define XPAR_HIER_9_AXI_GPIO_0_DEVICE_ID 11
-#define XPAR_HIER_9_AXI_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_HIER_9_AXI_GPIO_0_IS_DUAL 1
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral AXI_GPIO_0 */
-#define XPAR_GPIO_0_BASEADDR 0x41250000
-#define XPAR_GPIO_0_HIGHADDR 0x4125FFFF
-#define XPAR_GPIO_0_DEVICE_ID XPAR_AXI_GPIO_0_DEVICE_ID
-#define XPAR_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_0_IS_DUAL 1
-
-/* Canonical definitions for peripheral AXI_GPIO_1 */
-#define XPAR_GPIO_1_BASEADDR 0x41260000
-#define XPAR_GPIO_1_HIGHADDR 0x4126FFFF
-#define XPAR_GPIO_1_DEVICE_ID XPAR_AXI_GPIO_1_DEVICE_ID
-#define XPAR_GPIO_1_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_1_IS_DUAL 1
-
-/* Canonical definitions for peripheral HIER_0_AXI_GPIO_0 */
-#define XPAR_GPIO_2_BASEADDR 0x41200000
-#define XPAR_GPIO_2_HIGHADDR 0x4120FFFF
-#define XPAR_GPIO_2_DEVICE_ID XPAR_HIER_0_AXI_GPIO_0_DEVICE_ID
-#define XPAR_GPIO_2_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_2_IS_DUAL 1
-
-/* Canonical definitions for peripheral HIER_1_AXI_GPIO_0 */
-#define XPAR_GPIO_3_BASEADDR 0x41210000
-#define XPAR_GPIO_3_HIGHADDR 0x4121FFFF
-#define XPAR_GPIO_3_DEVICE_ID XPAR_HIER_1_AXI_GPIO_0_DEVICE_ID
-#define XPAR_GPIO_3_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_3_IS_DUAL 1
-
-/* Canonical definitions for peripheral HIER_2_AXI_GPIO_0 */
-#define XPAR_GPIO_4_BASEADDR 0x41220000
-#define XPAR_GPIO_4_HIGHADDR 0x4122FFFF
-#define XPAR_GPIO_4_DEVICE_ID XPAR_HIER_2_AXI_GPIO_0_DEVICE_ID
-#define XPAR_GPIO_4_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_4_IS_DUAL 1
-
-/* Canonical definitions for peripheral HIER_3_AXI_GPIO_0 */
-#define XPAR_GPIO_5_BASEADDR 0x41230000
-#define XPAR_GPIO_5_HIGHADDR 0x4123FFFF
-#define XPAR_GPIO_5_DEVICE_ID XPAR_HIER_3_AXI_GPIO_0_DEVICE_ID
-#define XPAR_GPIO_5_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_5_IS_DUAL 1
-
-/* Canonical definitions for peripheral HIER_4_AXI_GPIO_0 */
-#define XPAR_GPIO_6_BASEADDR 0x41240000
-#define XPAR_GPIO_6_HIGHADDR 0x4124FFFF
-#define XPAR_GPIO_6_DEVICE_ID XPAR_HIER_4_AXI_GPIO_0_DEVICE_ID
-#define XPAR_GPIO_6_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_6_IS_DUAL 1
-
-/* Canonical definitions for peripheral HIER_5_AXI_GPIO_0 */
-#define XPAR_GPIO_7_BASEADDR 0x41270000
-#define XPAR_GPIO_7_HIGHADDR 0x4127FFFF
-#define XPAR_GPIO_7_DEVICE_ID XPAR_HIER_5_AXI_GPIO_0_DEVICE_ID
-#define XPAR_GPIO_7_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_7_IS_DUAL 1
-
-/* Canonical definitions for peripheral HIER_6_AXI_GPIO_0 */
-#define XPAR_GPIO_8_BASEADDR 0x41280000
-#define XPAR_GPIO_8_HIGHADDR 0x4128FFFF
-#define XPAR_GPIO_8_DEVICE_ID XPAR_HIER_6_AXI_GPIO_0_DEVICE_ID
-#define XPAR_GPIO_8_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_8_IS_DUAL 1
-
-/* Canonical definitions for peripheral HIER_7_AXI_GPIO_0 */
-#define XPAR_GPIO_9_BASEADDR 0x41290000
-#define XPAR_GPIO_9_HIGHADDR 0x4129FFFF
-#define XPAR_GPIO_9_DEVICE_ID XPAR_HIER_7_AXI_GPIO_0_DEVICE_ID
-#define XPAR_GPIO_9_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_9_IS_DUAL 1
-
-/* Canonical definitions for peripheral HIER_8_AXI_GPIO_0 */
-#define XPAR_GPIO_10_BASEADDR 0x412A0000
-#define XPAR_GPIO_10_HIGHADDR 0x412AFFFF
-#define XPAR_GPIO_10_DEVICE_ID XPAR_HIER_8_AXI_GPIO_0_DEVICE_ID
-#define XPAR_GPIO_10_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_10_IS_DUAL 1
-
-/* Canonical definitions for peripheral HIER_9_AXI_GPIO_0 */
-#define XPAR_GPIO_11_BASEADDR 0x412B0000
-#define XPAR_GPIO_11_HIGHADDR 0x412BFFFF
-#define XPAR_GPIO_11_DEVICE_ID XPAR_HIER_9_AXI_GPIO_0_DEVICE_ID
-#define XPAR_GPIO_11_INTERRUPT_PRESENT 0
-#define XPAR_GPIO_11_IS_DUAL 1
-
-
-/******************************************************************/
-
-/* Definitions for driver GPIOPS */
-#define XPAR_XGPIOPS_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_GPIO_0 */
-#define XPAR_PS7_GPIO_0_DEVICE_ID 0
-#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
-#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_GPIO_0 */
-#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
-#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
-#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
-
-
-/******************************************************************/
-
-/* Definitions for driver QSPIPS */
-#define XPAR_XQSPIPS_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_QSPI_0 */
-#define XPAR_PS7_QSPI_0_DEVICE_ID 0
-#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000
-#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
-#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000
-#define XPAR_PS7_QSPI_0_QSPI_MODE 0
-#define XPAR_PS7_QSPI_0_QSPI_BUS_WIDTH 2
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_QSPI_0 */
-#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID
-#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000
-#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
-#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000
-#define XPAR_XQSPIPS_0_QSPI_MODE 0
-#define XPAR_XQSPIPS_0_QSPI_BUS_WIDTH 2
-
-
-/******************************************************************/
-
-/* Definitions for driver SCUGIC */
-#define XPAR_XSCUGIC_NUM_INSTANCES 1U
-
-/* Definitions for peripheral PS7_SCUGIC_0 */
-#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0U
-#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100U
-#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FFU
-#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_SCUGIC_0 */
-#define XPAR_SCUGIC_0_DEVICE_ID 0U
-#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100U
-#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FFU
-#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
-
-
-/******************************************************************/
-
-/* Definitions for driver SCUTIMER */
-#define XPAR_XSCUTIMER_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_SCUTIMER_0 */
-#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
-#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
-#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_SCUTIMER_0 */
-#define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID
-#define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600
-#define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F
-
-
-/******************************************************************/
-
-/* Definitions for driver SCUWDT */
-#define XPAR_XSCUWDT_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_SCUWDT_0 */
-#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
-#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
-#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_SCUWDT_0 */
-#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
-#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
-#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
-
-
-/******************************************************************/
-
-/* Definitions for driver SDPS */
-#define XPAR_XSDPS_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_SD_0 */
-#define XPAR_PS7_SD_0_DEVICE_ID 0
-#define XPAR_PS7_SD_0_BASEADDR 0xE0100000
-#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
-#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
-#define XPAR_PS7_SD_0_HAS_CD 1
-#define XPAR_PS7_SD_0_HAS_WP 0
-#define XPAR_PS7_SD_0_BUS_WIDTH 0
-#define XPAR_PS7_SD_0_MIO_BANK 0
-#define XPAR_PS7_SD_0_HAS_EMIO 0
-
-
-/******************************************************************/
-
-#define XPAR_PS7_SD_0_IS_CACHE_COHERENT 0
-/* Canonical definitions for peripheral PS7_SD_0 */
-#define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID
-#define XPAR_XSDPS_0_BASEADDR 0xE0100000
-#define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF
-#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000
-#define XPAR_XSDPS_0_HAS_CD 1
-#define XPAR_XSDPS_0_HAS_WP 0
-#define XPAR_XSDPS_0_BUS_WIDTH 0
-#define XPAR_XSDPS_0_MIO_BANK 0
-#define XPAR_XSDPS_0_HAS_EMIO 0
-#define XPAR_XSDPS_0_IS_CACHE_COHERENT 0
-
-
-/******************************************************************/
-
-/* Definitions for driver UARTPS */
-#define XPAR_XUARTPS_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_UART_1 */
-#define XPAR_PS7_UART_1_DEVICE_ID 0
-#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
-#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
-#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 100000000
-#define XPAR_PS7_UART_1_HAS_MODEM 0
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_UART_1 */
-#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
-#define XPAR_XUARTPS_0_BASEADDR 0xE0001000
-#define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF
-#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 100000000
-#define XPAR_XUARTPS_0_HAS_MODEM 0
-
-
-/******************************************************************/
-
-/* Definition for input Clock */
-/* Definitions for driver USBPS */
-#define XPAR_XUSBPS_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_USB_0 */
-#define XPAR_PS7_USB_0_DEVICE_ID 0
-#define XPAR_PS7_USB_0_BASEADDR 0xE0002000
-#define XPAR_PS7_USB_0_HIGHADDR 0xE0002FFF
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_USB_0 */
-#define XPAR_XUSBPS_0_DEVICE_ID XPAR_PS7_USB_0_DEVICE_ID
-#define XPAR_XUSBPS_0_BASEADDR 0xE0002000
-#define XPAR_XUSBPS_0_HIGHADDR 0xE0002FFF
-
-
-/******************************************************************/
-
-/* Definitions for driver XADCPS */
-#define XPAR_XADCPS_NUM_INSTANCES 1
-
-/* Definitions for peripheral PS7_XADC_0 */
-#define XPAR_PS7_XADC_0_DEVICE_ID 0
-#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100
-#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120
-
-
-/******************************************************************/
-
-/* Canonical definitions for peripheral PS7_XADC_0 */
-#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
-#define XPAR_XADCPS_0_BASEADDR 0xF8007100
-#define XPAR_XADCPS_0_HIGHADDR 0xF8007120
-
-
-/******************************************************************/
-
-#endif /* end of protection macro */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/98/a113a7575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/98/a113a7575243001d18b399c1eb9b3628
deleted file mode 100644
index 1e9e6fb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/98/a113a7575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,522 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xstatus.h
-*
-* @addtogroup common_status_codes Xilinx software status codes
-*
-* The xstatus.h file contains the Xilinx software status codes.These codes are
-* used throughout the Xilinx device drivers.
-*
-* @{
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XSTATUS_H /* prevent circular inclusions */
-#define XSTATUS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/*********************** Common statuses 0 - 500 *****************************/
-/**
-@name Common Status Codes for All Device Drivers
-@{
-*/
-#define XST_SUCCESS 0L
-#define XST_FAILURE 1L
-#define XST_DEVICE_NOT_FOUND 2L
-#define XST_DEVICE_BLOCK_NOT_FOUND 3L
-#define XST_INVALID_VERSION 4L
-#define XST_DEVICE_IS_STARTED 5L
-#define XST_DEVICE_IS_STOPPED 6L
-#define XST_FIFO_ERROR 7L /*!< An error occurred during an
- operation with a FIFO such as
- an underrun or overrun, this
- error requires the device to
- be reset */
-#define XST_RESET_ERROR 8L /*!< An error occurred which requires
- the device to be reset */
-#define XST_DMA_ERROR 9L /*!< A DMA error occurred, this error
- typically requires the device
- using the DMA to be reset */
-#define XST_NOT_POLLED 10L /*!< The device is not configured for
- polled mode operation */
-#define XST_FIFO_NO_ROOM 11L /*!< A FIFO did not have room to put
- the specified data into */
-#define XST_BUFFER_TOO_SMALL 12L /*!< The buffer is not large enough
- to hold the expected data */
-#define XST_NO_DATA 13L /*!< There was no data available */
-#define XST_REGISTER_ERROR 14L /*!< A register did not contain the
- expected value */
-#define XST_INVALID_PARAM 15L /*!< An invalid parameter was passed
- into the function */
-#define XST_NOT_SGDMA 16L /*!< The device is not configured for
- scatter-gather DMA operation */
-#define XST_LOOPBACK_ERROR 17L /*!< A loopback test failed */
-#define XST_NO_CALLBACK 18L /*!< A callback has not yet been
- registered */
-#define XST_NO_FEATURE 19L /*!< Device is not configured with
- the requested feature */
-#define XST_NOT_INTERRUPT 20L /*!< Device is not configured for
- interrupt mode operation */
-#define XST_DEVICE_BUSY 21L /*!< Device is busy */
-#define XST_ERROR_COUNT_MAX 22L /*!< The error counters of a device
- have maxed out */
-#define XST_IS_STARTED 23L /*!< Used when part of device is
- already started i.e.
- sub channel */
-#define XST_IS_STOPPED 24L /*!< Used when part of device is
- already stopped i.e.
- sub channel */
-#define XST_DATA_LOST 26L /*!< Driver defined error */
-#define XST_RECV_ERROR 27L /*!< Generic receive error */
-#define XST_SEND_ERROR 28L /*!< Generic transmit error */
-#define XST_NOT_ENABLED 29L /*!< A requested service is not
- available because it has not
- been enabled */
-#define XST_NO_ACCESS 30L /* Generic access error */
-#define XST_TIMEOUT 31L /*!< Event timeout occurred */
-
-/** @} */
-/***************** Utility Component statuses 401 - 500 *********************/
-/**
-@name Utility Component Status Codes 401 - 500
-@{
-*/
-#define XST_MEMTEST_FAILED 401L /*!< Memory test failed */
-
-/** @} */
-/***************** Common Components statuses 501 - 1000 *********************/
-/**
-@name Packet Fifo Status Codes 501 - 510
-@{
-*/
-/********************* Packet Fifo statuses 501 - 510 ************************/
-
-#define XST_PFIFO_LACK_OF_DATA 501L /*!< Not enough data in FIFO */
-#define XST_PFIFO_NO_ROOM 502L /*!< Not enough room in FIFO */
-#define XST_PFIFO_BAD_REG_VALUE 503L /*!< Self test, a register value
- was invalid after reset */
-#define XST_PFIFO_ERROR 504L /*!< Generic packet FIFO error */
-#define XST_PFIFO_DEADLOCK 505L /*!< Packet FIFO is reporting
- * empty and full simultaneously
- */
-/** @} */
-/**
-@name DMA Status Codes 511 - 530
-@{
-*/
-/************************** DMA statuses 511 - 530 ***************************/
-
-#define XST_DMA_TRANSFER_ERROR 511L /*!< Self test, DMA transfer
- failed */
-#define XST_DMA_RESET_REGISTER_ERROR 512L /*!< Self test, a register value
- was invalid after reset */
-#define XST_DMA_SG_LIST_EMPTY 513L /*!< Scatter gather list contains
- no buffer descriptors ready
- to be processed */
-#define XST_DMA_SG_IS_STARTED 514L /*!< Scatter gather not stopped */
-#define XST_DMA_SG_IS_STOPPED 515L /*!< Scatter gather not running */
-#define XST_DMA_SG_LIST_FULL 517L /*!< All the buffer descriptors of
- the scatter gather list are
- being used */
-#define XST_DMA_SG_BD_LOCKED 518L /*!< The scatter gather buffer
- descriptor which is to be
- copied over in the scatter
- list is locked */
-#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /*!< No buffer descriptors have been
- put into the scatter gather
- list to be committed */
-#define XST_DMA_SG_COUNT_EXCEEDED 521L /*!< The packet count threshold
- specified was larger than the
- total # of buffer descriptors
- in the scatter gather list */
-#define XST_DMA_SG_LIST_EXISTS 522L /*!< The scatter gather list has
- already been created */
-#define XST_DMA_SG_NO_LIST 523L /*!< No scatter gather list has
- been created */
-#define XST_DMA_SG_BD_NOT_COMMITTED 524L /*!< The buffer descriptor which was
- being started was not committed
- to the list */
-#define XST_DMA_SG_NO_DATA 525L /*!< The buffer descriptor to start
- has already been used by the
- hardware so it can't be reused
- */
-#define XST_DMA_SG_LIST_ERROR 526L /*!< General purpose list access
- error */
-#define XST_DMA_BD_ERROR 527L /*!< General buffer descriptor
- error */
-/** @} */
-/**
-@name IPIF Status Codes Codes 531 - 550
-@{
-*/
-/************************** IPIF statuses 531 - 550 ***************************/
-
-#define XST_IPIF_REG_WIDTH_ERROR 531L /*!< An invalid register width
- was passed into the function */
-#define XST_IPIF_RESET_REGISTER_ERROR 532L /*!< The value of a register at
- reset was not valid */
-#define XST_IPIF_DEVICE_STATUS_ERROR 533L /*!< A write to the device interrupt
- status register did not read
- back correctly */
-#define XST_IPIF_DEVICE_ACK_ERROR 534L /*!< The device interrupt status
- register did not reset when
- acked */
-#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /*!< The device interrupt enable
- register was not updated when
- other registers changed */
-#define XST_IPIF_IP_STATUS_ERROR 536L /*!< A write to the IP interrupt
- status register did not read
- back correctly */
-#define XST_IPIF_IP_ACK_ERROR 537L /*!< The IP interrupt status register
- did not reset when acked */
-#define XST_IPIF_IP_ENABLE_ERROR 538L /*!< IP interrupt enable register was
- not updated correctly when other
- registers changed */
-#define XST_IPIF_DEVICE_PENDING_ERROR 539L /*!< The device interrupt pending
- register did not indicate the
- expected value */
-#define XST_IPIF_DEVICE_ID_ERROR 540L /*!< The device interrupt ID register
- did not indicate the expected
- value */
-#define XST_IPIF_ERROR 541L /*!< Generic ipif error */
-/** @} */
-
-/****************** Device specific statuses 1001 - 4095 *********************/
-/**
-@name Ethernet Status Codes 1001 - 1050
-@{
-*/
-/********************* Ethernet statuses 1001 - 1050 *************************/
-
-#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /*!< Memory space is not big enough
- * to hold the minimum number of
- * buffers or descriptors */
-#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /*!< Memory allocation failed */
-#define XST_EMAC_MII_READ_ERROR 1003L /*!< MII read error */
-#define XST_EMAC_MII_BUSY 1004L /*!< An MII operation is in progress */
-#define XST_EMAC_OUT_OF_BUFFERS 1005L /*!< Driver is out of buffers */
-#define XST_EMAC_PARSE_ERROR 1006L /*!< Invalid driver init string */
-#define XST_EMAC_COLLISION_ERROR 1007L /*!< Excess deferral or late
- * collision on polled send */
-/** @} */
-/**
-@name UART Status Codes 1051 - 1075
-@{
-*/
-/*********************** UART statuses 1051 - 1075 ***************************/
-#define XST_UART
-
-#define XST_UART_INIT_ERROR 1051L
-#define XST_UART_START_ERROR 1052L
-#define XST_UART_CONFIG_ERROR 1053L
-#define XST_UART_TEST_FAIL 1054L
-#define XST_UART_BAUD_ERROR 1055L
-#define XST_UART_BAUD_RANGE 1056L
-
-/** @} */
-/**
-@name IIC Status Codes 1076 - 1100
-@{
-*/
-/************************ IIC statuses 1076 - 1100 ***************************/
-
-#define XST_IIC_SELFTEST_FAILED 1076 /*!< self test failed */
-#define XST_IIC_BUS_BUSY 1077 /*!< bus found busy */
-#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /*!< mastersend attempted with */
- /* general call address */
-#define XST_IIC_STAND_REG_RESET_ERROR 1079 /*!< A non parameterizable reg */
- /* value after reset not valid */
-#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /*!< Tx fifo included in design */
- /* value after reset not valid */
-#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /*!< Rx fifo included in design */
- /* value after reset not valid */
-#define XST_IIC_TBA_REG_RESET_ERROR 1082 /*!< 10 bit addr incl in design */
- /* value after reset not valid */
-#define XST_IIC_CR_READBACK_ERROR 1083 /*!< Read of the control register */
- /* didn't return value written */
-#define XST_IIC_DTR_READBACK_ERROR 1084 /*!< Read of the data Tx reg */
- /* didn't return value written */
-#define XST_IIC_DRR_READBACK_ERROR 1085 /*!< Read of the data Receive reg */
- /* didn't return value written */
-#define XST_IIC_ADR_READBACK_ERROR 1086 /*!< Read of the data Tx reg */
- /* didn't return value written */
-#define XST_IIC_TBA_READBACK_ERROR 1087 /*!< Read of the 10 bit addr reg */
- /* didn't return written value */
-#define XST_IIC_NOT_SLAVE 1088 /*!< The device isn't a slave */
-#define XST_IIC_ARB_LOST 1089 /*!< Arbitration lost for master */
-/** @} */
-/**
-@name ATMC Status Codes 1101 - 1125
-@{
-*/
-/*********************** ATMC statuses 1101 - 1125 ***************************/
-
-#define XST_ATMC_ERROR_COUNT_MAX 1101L /*!< the error counters in the ATM
- controller hit the max value
- which requires the statistics
- to be cleared */
-/** @} */
-/**
-@name Flash Status Codes 1126 - 1150
-@{
-*/
-/*********************** Flash statuses 1126 - 1150 **************************/
-
-#define XST_FLASH_BUSY 1126L /*!< Flash is erasing or programming
- */
-#define XST_FLASH_READY 1127L /*!< Flash is ready for commands */
-#define XST_FLASH_ERROR 1128L /*!< Flash had detected an internal
- error. Use XFlash_DeviceControl
- to retrieve device specific codes
- */
-#define XST_FLASH_ERASE_SUSPENDED 1129L /*!< Flash is in suspended erase state
- */
-#define XST_FLASH_WRITE_SUSPENDED 1130L /*!< Flash is in suspended write state
- */
-#define XST_FLASH_PART_NOT_SUPPORTED 1131L /*!< Flash type not supported by
- driver */
-#define XST_FLASH_NOT_SUPPORTED 1132L /*!< Operation not supported */
-#define XST_FLASH_TOO_MANY_REGIONS 1133L /*!< Too many erase regions */
-#define XST_FLASH_TIMEOUT_ERROR 1134L /*!< Programming or erase operation
- aborted due to a timeout */
-#define XST_FLASH_ADDRESS_ERROR 1135L /*!< Accessed flash outside its
- addressible range */
-#define XST_FLASH_ALIGNMENT_ERROR 1136L /*!< Write alignment error */
-#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /*!< Couldn't return immediately from
- write/erase function with
- XFL_NON_BLOCKING_WRITE/ERASE
- option cleared */
-#define XST_FLASH_CFI_QUERY_ERROR 1138L /*!< Failed to query the device */
-/** @} */
-/**
-@name SPI Status Codes 1151 - 1175
-@{
-*/
-/*********************** SPI statuses 1151 - 1175 ****************************/
-
-#define XST_SPI_MODE_FAULT 1151 /*!< master was selected as slave */
-#define XST_SPI_TRANSFER_DONE 1152 /*!< data transfer is complete */
-#define XST_SPI_TRANSMIT_UNDERRUN 1153 /*!< slave underruns transmit register */
-#define XST_SPI_RECEIVE_OVERRUN 1154 /*!< device overruns receive register */
-#define XST_SPI_NO_SLAVE 1155 /*!< no slave has been selected yet */
-#define XST_SPI_TOO_MANY_SLAVES 1156 /*!< more than one slave is being
- * selected */
-#define XST_SPI_NOT_MASTER 1157 /*!< operation is valid only as master */
-#define XST_SPI_SLAVE_ONLY 1158 /*!< device is configured as slave-only
- */
-#define XST_SPI_SLAVE_MODE_FAULT 1159 /*!< slave was selected while disabled */
-#define XST_SPI_SLAVE_MODE 1160 /*!< device has been addressed as slave */
-#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /*!< device received data in slave mode */
-
-#define XST_SPI_COMMAND_ERROR 1162 /*!< unrecognised command - qspi only */
-#define XST_SPI_POLL_DONE 1163 /*!< controller completed polling the
- device for status */
-/** @} */
-/**
-@name OPB Arbiter Status Codes 1176 - 1200
-@{
-*/
-/********************** OPB Arbiter statuses 1176 - 1200 *********************/
-
-#define XST_OPBARB_INVALID_PRIORITY 1176 /*!< the priority registers have either
- * one master assigned to two or more
- * priorities, or one master not
- * assigned to any priority
- */
-#define XST_OPBARB_NOT_SUSPENDED 1177 /*!< an attempt was made to modify the
- * priority levels without first
- * suspending the use of priority
- * levels
- */
-#define XST_OPBARB_PARK_NOT_ENABLED 1178 /*!< bus parking by id was enabled but
- * bus parking was not enabled
- */
-#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /*!< the arbiter must be in fixed
- * priority mode to allow the
- * priorities to be changed
- */
-/** @} */
-/**
-@name INTC Status Codes 1201 - 1225
-@{
-*/
-/************************ Intc statuses 1201 - 1225 **************************/
-
-#define XST_INTC_FAIL_SELFTEST 1201 /*!< self test failed */
-#define XST_INTC_CONNECT_ERROR 1202 /*!< interrupt already in use */
-/** @} */
-/**
-@name TmrCtr Status Codes 1226 - 1250
-@{
-*/
-/********************** TmrCtr statuses 1226 - 1250 **************************/
-
-#define XST_TMRCTR_TIMER_FAILED 1226 /*!< self test failed */
-/** @} */
-/**
-@name WdtTb Status Codes 1251 - 1275
-@{
-*/
-/********************** WdtTb statuses 1251 - 1275 ***************************/
-
-#define XST_WDTTB_TIMER_FAILED 1251L
-/** @} */
-/**
-@name PlbArb status Codes 1276 - 1300
-@{
-*/
-/********************** PlbArb statuses 1276 - 1300 **************************/
-
-#define XST_PLBARB_FAIL_SELFTEST 1276L
-/** @} */
-/**
-@name Plb2Opb Status Codes 1301 - 1325
-@{
-*/
-/********************** Plb2Opb statuses 1301 - 1325 *************************/
-
-#define XST_PLB2OPB_FAIL_SELFTEST 1301L
-/** @} */
-/**
-@name Opb2Plb Status 1326 - 1350
-@{
-*/
-/********************** Opb2Plb statuses 1326 - 1350 *************************/
-
-#define XST_OPB2PLB_FAIL_SELFTEST 1326L
-/** @} */
-/**
-@name SysAce Status Codes 1351 - 1360
-@{
-*/
-/********************** SysAce statuses 1351 - 1360 **************************/
-
-#define XST_SYSACE_NO_LOCK 1351L /*!< No MPU lock has been granted */
-/** @} */
-/**
-@name PCI Bridge Status Codes 1361 - 1375
-@{
-*/
-/********************** PCI Bridge statuses 1361 - 1375 **********************/
-
-#define XST_PCI_INVALID_ADDRESS 1361L
-/** @} */
-/**
-@name FlexRay Constants 1400 - 1409
-@{
-*/
-/********************** FlexRay constants 1400 - 1409 *************************/
-
-#define XST_FR_TX_ERROR 1400
-#define XST_FR_TX_BUSY 1401
-#define XST_FR_BUF_LOCKED 1402
-#define XST_FR_NO_BUF 1403
-/** @} */
-/**
-@name USB constants 1410 - 1420
-@{
-*/
-/****************** USB constants 1410 - 1420 *******************************/
-
-#define XST_USB_ALREADY_CONFIGURED 1410
-#define XST_USB_BUF_ALIGN_ERROR 1411
-#define XST_USB_NO_DESC_AVAILABLE 1412
-#define XST_USB_BUF_TOO_BIG 1413
-#define XST_USB_NO_BUF 1414
-/** @} */
-/**
-@name HWICAP constants 1421 - 1429
-@{
-*/
-/****************** HWICAP constants 1421 - 1429 *****************************/
-
-#define XST_HWICAP_WRITE_DONE 1421
-
-/** @} */
-/**
-@name AXI VDMA constants 1430 - 1440
-@{
-*/
-/****************** AXI VDMA constants 1430 - 1440 *****************************/
-
-#define XST_VDMA_MISMATCH_ERROR 1430
-/** @} */
-/**
-@name NAND Flash Status Codes 1441 - 1459
-@{
-*/
-/*********************** NAND Flash statuses 1441 - 1459 *********************/
-
-#define XST_NAND_BUSY 1441L /*!< Flash is erasing or
- * programming
- */
-#define XST_NAND_READY 1442L /*!< Flash is ready for commands
- */
-#define XST_NAND_ERROR 1443L /*!< Flash had detected an
- * internal error.
- */
-#define XST_NAND_PART_NOT_SUPPORTED 1444L /*!< Flash type not supported by
- * driver
- */
-#define XST_NAND_OPT_NOT_SUPPORTED 1445L /*!< Operation not supported
- */
-#define XST_NAND_TIMEOUT_ERROR 1446L /*!< Programming or erase
- * operation aborted due to a
- * timeout
- */
-#define XST_NAND_ADDRESS_ERROR 1447L /*!< Accessed flash outside its
- * addressible range
- */
-#define XST_NAND_ALIGNMENT_ERROR 1448L /*!< Write alignment error
- */
-#define XST_NAND_PARAM_PAGE_ERROR 1449L /*!< Failed to read parameter
- * page of the device
- */
-#define XST_NAND_CACHE_ERROR 1450L /*!< Flash page buffer error
- */
-
-#define XST_NAND_WRITE_PROTECTED 1451L /*!< Flash is write protected
- */
-/** @} */
-
-/**************************** Type Definitions *******************************/
-
-typedef s32 XStatus;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
-
-/**
-* @} End of "addtogroup common_status_codes".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/98/b1992f575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/98/b1992f575243001d18b399c1eb9b3628
deleted file mode 100644
index 69d5327..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/98/b1992f575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,46 +0,0 @@
-# Auto Generated by Xilinx generate_app. Modify at your own risk
-
-CC := arm-none-eabi-gcc
-CC_FLAGS := -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
-CFLAGS :=
-BSP_FLAGS := -O2 -c
-LN_FLAGS := -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec -lrsa -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilffs,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lrsa,-lxil,-lgcc,-lc,--end-group -Wl,--gc-sections
-
-c_SOURCES := $(wildcard *.c)
-S_SOURCES := $(wildcard *.S)
-s_SOURCES := $(wildcard *.s)
-INCLUDES := $(wildcard *.h)
-OBJS := $(patsubst %.c, %.o, $(c_SOURCES))
-OBJS += $(patsubst %.S, %.o, $(S_SOURCES))
-OBJS += $(patsubst %.s, %.o, $(s_SOURCES))
-LSCRIPT := -Tlscript.ld
-
-CURRENT_DIR = $(shell pwd)
-DEPFILES := $(patsubst %.o, %.d, $(OBJS))
-LIBS := zynq_fsbl_bsp/ps7_cortexa9_0/lib/libxil.a
-EXEC := fsbl.elf
-
-INCLUDEPATH := -Izynq_fsbl_bsp/ps7_cortexa9_0/include -I.
-LIBPATH := -Lzynq_fsbl_bsp/ps7_cortexa9_0/lib -L./
-
-all: $(EXEC)
-
-$(EXEC): $(LIBS) $(OBJS) $(INCLUDES)
- $(CC) -o $@ $(sort $(OBJS)) $(CC_FLAGS) $(CFLAGS) $(LN_FLAGS) $(LIBPATH) $(LSCRIPT)
-
-$(LIBS):
- $(MAKE) -C zynq_fsbl_bsp
-
-%.o:%.c
- $(CC) $(CFLAGS) $(BSP_FLAGS) $(CC_FLAGS) -c $< -o $@ $(INCLUDEPATH)
-
-%.o:%.S
- $(CC) $(CFLAGS) $(BSP_FLAGS) $(CC_FLAGS) -c $< -o $@ $(INCLUDEPATH)
-
-%.o:%.s
- $(CC) $(CFLAGS) $(BSP_FLAGS) $(CC_FLAGS) -c $< -o $@ $(INCLUDEPATH)
-
-clean:
- rm -rf $(OBJS) $(LIBS) $(EXEC) *.o
-
--include $(DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/98/c18b23575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/98/c18b23575243001d18b399c1eb9b3628
deleted file mode 100644
index e8eb9ee..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/98/c18b23575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1813 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xadcps.c
-* @addtogroup xadcps_v2_6
-* @{
-*
-* This file contains the driver API functions that can be used to access
-* the XADC device.
-*
-* Refer to the xadcps.h header file for more information about this driver.
-*
-* @note None.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
-* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
-* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
-* to fix CR #693371
-* 2.1 bss 08/05/14 Modified Assert for XAdcPs_SetSingleChParams to fix
-* CR #807563.
-* 2.2 bss 04/27/14 Modified to use correct Device Config base address
-* (CR#854437).
-* 2.3 mn 07/09/18 Fix Doxygen warning
-* 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors.
-*
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xadcps.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Function Prototypes *****************************/
-
-void XAdcPs_WriteInternalReg(XAdcPs *InstancePtr, u32 RegOffset, u32 Data);
-u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset);
-
-
-/************************** Variable Definitions ****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* This function initializes a specific XAdcPs device/instance. This function
-* must be called prior to using the XADC device.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param ConfigPtr points to the XAdcPs device configuration structure.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. If the address translation is not used then the
-* physical address is passed.
-* Unexpected errors may occur if the address mapping is changed
-* after this function is invoked.
-*
-* @return
-* - XST_SUCCESS if successful.
-*
-* @note The user needs to first call the XAdcPs_LookupConfig() API
-* which returns the Configuration structure pointer which is
-* passed as a parameter to the XAdcPs_CfgInitialize() API.
-*
-******************************************************************************/
-int XAdcPs_CfgInitialize(XAdcPs *InstancePtr, XAdcPs_Config *ConfigPtr,
- u32 EffectiveAddr)
-{
-
- u32 RegValue;
- /*
- * Assert the input arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
-
-
- /*
- * Set the values read from the device config and the base address.
- */
- InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
- InstancePtr->Config.BaseAddress = EffectiveAddr;
-
- /* Write Unlock value to Device Config Unlock register */
- XAdcPs_WriteReg(XPAR_XDCFG_0_BASEADDR,
- XADCPS_UNLK_OFFSET, XADCPS_UNLK_VALUE);
-
- /* Enable the PS access of xadc and set FIFO thresholds */
-
- RegValue = XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
- XADCPS_CFG_OFFSET);
-
- RegValue = RegValue | XADCPS_CFG_ENABLE_MASK |
- XADCPS_CFG_CFIFOTH_MASK | XADCPS_CFG_DFIFOTH_MASK;
-
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
- XADCPS_CFG_OFFSET, RegValue);
-
- /* Release xadc from reset */
-
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
- XADCPS_MCTL_OFFSET, 0x00);
-
- /*
- * Indicate the instance is now ready to use and
- * initialized without error.
- */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- return XST_SUCCESS;
-}
-
-
-/****************************************************************************/
-/**
-*
-* The functions sets the contents of the Config Register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Data is the 32 bit data to be written to the Register.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_SetConfigRegister(XAdcPs *InstancePtr, u32 Data)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
- XADCPS_CFG_OFFSET, Data);
-
-}
-
-
-/****************************************************************************/
-/**
-*
-* The functions reads the contents of the Config Register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return A 32-bit value representing the contents of the Config Register.
-* Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to
-* interpret the returned value.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XAdcPs_GetConfigRegister(XAdcPs *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Config Register and return the value.
- */
- return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
- XADCPS_CFG_OFFSET);
-}
-
-
-/****************************************************************************/
-/**
-*
-* The functions reads the contents of the Miscellaneous Status Register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return A 32-bit value representing the contents of the Miscellaneous
-* Status Register. Use the XADCPS_MSTS_*_MASK constants defined
-* in xadcps_hw.h to interpret the returned value.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XAdcPs_GetMiscStatus(XAdcPs *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Miscellaneous Status Register and return the value.
- */
- return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
- XADCPS_MSTS_OFFSET);
-}
-
-
-/****************************************************************************/
-/**
-*
-* The functions sets the contents of the Miscellaneous Control register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Data is the 32 bit data to be written to the Register.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_SetMiscCtrlRegister(XAdcPs *InstancePtr, u32 Data)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Write to the Miscellaneous control register Register.
- */
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
- XADCPS_MCTL_OFFSET, Data);
-}
-
-
-/****************************************************************************/
-/**
-*
-* The functions reads the contents of the Miscellaneous control register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return A 32-bit value representing the contents of the Config Register.
-* Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to
-* interpret the returned value.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XAdcPs_GetMiscCtrlRegister(XAdcPs *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Miscellaneous control register and return the value.
- */
- return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
- XADCPS_MCTL_OFFSET);
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This function resets the XADC Hard Macro in the device.
-*
-* @param InstancePtr is a pointer to the Xxadc instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XAdcPs_Reset(XAdcPs *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Generate the reset by Control
- * register and release from reset
- */
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
- XADCPS_MCTL_OFFSET, 0x10);
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
- XADCPS_MCTL_OFFSET, 0x00);
-}
-
-
-/****************************************************************************/
-/**
-*
-* Get the ADC converted data for the specified channel.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Channel is the channel number. Use the XADCPS_CH_* defined in
-* the file xadcps.h.
-* The valid channels are
-* - 0 to 6
-* - 13 to 31
-*
-* @return A 16-bit value representing the ADC converted data for the
-* specified channel. The XADC Monitor/ADC device guarantees
-* a 10 bit resolution for the ADC converted data and data is the
-* 10 MSB bits of the 16 data read from the device.
-*
-* @note The channels 7,8,9 are used for calibration of the device and
-* hence there is no associated data with this channel.
-*
-*****************************************************************************/
-u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel)
-{
-
- u32 RegData;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((Channel <= XADCPS_CH_VBRAM) ||
- ((Channel >= XADCPS_CH_VCCPINT) &&
- (Channel <= XADCPS_CH_AUX_MAX)));
-
- RegData = XAdcPs_ReadInternalReg(InstancePtr,
- (XADCPS_TEMP_OFFSET + (u32)Channel));
- return (u16) RegData;
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the calibration coefficient data for the specified
-* parameter.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param CoeffType specifies the calibration coefficient
-* to be read. Use XADCPS_CALIB_* constants defined in xadcps.h to
-* specify the calibration coefficient to be read.
-*
-* @return A 16-bit value representing the calibration coefficient.
-* The XADC device guarantees a 10 bit resolution for
-* the ADC converted data and data is the 10 MSB bits of the 16
-* data read from the device.
-*
-* @note None.
-*
-*****************************************************************************/
-u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType)
-{
- u32 RegData;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(CoeffType <= XADCPS_CALIB_GAIN_ERROR_COEFF);
-
- /*
- * Read the selected calibration coefficient.
- */
- RegData = XAdcPs_ReadInternalReg(InstancePtr,
- (XADCPS_ADC_A_SUPPLY_CALIB_OFFSET +
- (u32)CoeffType));
- return (u16) RegData;
-}
-
-/****************************************************************************/
-/**
-*
-* This function reads the Minimum/Maximum measurement for one of the
-* specified parameters. Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in
-* xadcps.h to specify the parameters (Temperature, VccInt, VccAux, VBram,
-* VccPInt, VccPAux and VccPDro).
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param MeasurementType specifies the parameter for which the
-* Minimum/Maximum measurement has to be read.
-* Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in xadcps.h to
-* specify the data to be read.
-*
-* @return A 16-bit value representing the maximum/minimum measurement for
-* specified parameter.
-* The XADC device guarantees a 10 bit resolution for
-* the ADC converted data and data is the 10 MSB bits of the 16
-* data read from the device.
-*
-* @note None.
-*
-*****************************************************************************/
-u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType)
-{
- u32 RegData;
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((MeasurementType <= XADCPS_MAX_VCCPDRO) ||
- ((MeasurementType >= XADCPS_MIN_VCCPINT) &&
- (MeasurementType <= XADCPS_MIN_VCCPDRO)))
-
- /*
- * Read and return the specified Minimum/Maximum measurement.
- */
- RegData = XAdcPs_ReadInternalReg(InstancePtr,
- (XADCPS_MAX_TEMP_OFFSET +
- (u32)MeasurementType));
- return (u16) RegData;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the number of samples of averaging that is to be done for
-* all the channels in both the single channel mode and sequence mode of
-* operations.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Average is the number of samples of averaging programmed to the
-* Configuration Register 0. Use the XADCPS_AVG_* definitions defined
-* in xadcps.h file :
-* - XADCPS_AVG_0_SAMPLES for no averaging
-* - XADCPS_AVG_16_SAMPLES for 16 samples of averaging
-* - XADCPS_AVG_64_SAMPLES for 64 samples of averaging
-* - XADCPS_AVG_256_SAMPLES for 256 samples of averaging
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average)
-{
- u32 RegData;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Average <= XADCPS_AVG_256_SAMPLES);
-
- /*
- * Write the averaging value into the Configuration Register 0.
- */
- RegData = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR0_OFFSET) &
- (~XADCPS_CFR0_AVG_VALID_MASK);
-
- RegData |= (((u32) Average << XADCPS_CFR0_AVG_SHIFT));
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
- RegData);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the number of samples of averaging configured for all
-* the channels in the Configuration Register 0.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return The averaging read from the Configuration Register 0 is
-* returned. Use the XADCPS_AVG_* bit definitions defined in
-* xadcps.h file to interpret the returned value :
-* - XADCPS_AVG_0_SAMPLES means no averaging
-* - XADCPS_AVG_16_SAMPLES means 16 samples of averaging
-* - XADCPS_AVG_64_SAMPLES means 64 samples of averaging
-* - XADCPS_AVG_256_SAMPLES means 256 samples of averaging
-*
-* @note None.
-*
-*****************************************************************************/
-u8 XAdcPs_GetAvg(XAdcPs *InstancePtr)
-{
- u32 Average;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the averaging value from the Configuration Register 0.
- */
- Average = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR0_OFFSET) & XADCPS_CFR0_AVG_VALID_MASK;
-
-
- return ((u8) (Average >> XADCPS_CFR0_AVG_SHIFT));
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the given parameters in the Configuration Register 0 in
-* the single channel mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Channel is the channel number for the singel channel mode.
-* The valid channels are 0 to 6, 8, and 13 to 31.
-* If the external Mux is used then this specifies the channel
-* oonnected to the external Mux. Please read the Device Spec
-* to know which channels are valid.
-* @param IncreaseAcqCycles is a boolean parameter which specifies whether
-* the Acquisition time for the external channels has to be
-* increased to 10 ADCCLK cycles (specify TRUE) or remain at the
-* default 4 ADCCLK cycles (specify FALSE). This parameter is
-* only valid for the external channels.
-* @param IsEventMode specifies whether the operation of the ADC is Event
-* driven or Continuous mode.
-* @param IsDifferentialMode is a boolean parameter which specifies
-* unipolar(specify FALSE) or differential mode (specify TRUE) for
-* the analog inputs. The input mode is only valid for the
-* external channels.
-*
-* @return
-* - XST_SUCCESS if the given values were written successfully to
-* the Configuration Register 0.
-* - XST_FAILURE if the channel sequencer is enabled or the input
-* parameters are not valid for the selected channel.
-*
-* @note
-* - The number of samples for the averaging for all the channels
-* is set by using the function XAdcPs_SetAvg.
-* - The calibration of the device is done by doing a ADC
-* conversion on the calibration channel(channel 8). The input
-* parameters IncreaseAcqCycles, IsDifferentialMode and
-* IsEventMode are not valid for this channel
-*
-*
-*****************************************************************************/
-int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
- u8 Channel,
- int IncreaseAcqCycles,
- int IsEventMode,
- int IsDifferentialMode)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((Channel <= XADCPS_CH_VBRAM) ||
- (Channel == XADCPS_CH_ADC_CALIB) ||
- ((Channel >= XADCPS_CH_VCCPINT) &&
- (Channel <= XADCPS_CH_AUX_MAX)));
- Xil_AssertNonvoid((IncreaseAcqCycles == 0x1) ||
- (IncreaseAcqCycles == 0x0));
- Xil_AssertNonvoid((IsEventMode == 0x1) || (IsEventMode == 0x0));
- Xil_AssertNonvoid((IsDifferentialMode == 0x1) ||
- (IsDifferentialMode == 0x0));
-
- /*
- * Check if the device is in single channel mode else return failure
- */
- if ((XAdcPs_GetSequencerMode(InstancePtr) !=
- XADCPS_SEQ_MODE_SINGCHAN)) {
- return XST_FAILURE;
- }
-
- /*
- * Read the Configuration Register 0.
- */
- RegValue = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR0_OFFSET) &
- XADCPS_CFR0_AVG_VALID_MASK;
-
- /*
- * Select the number of acquisition cycles. The acquisition cycles is
- * only valid for the external channels.
- */
- if (IncreaseAcqCycles == 0x1) {
- if (((Channel >= XADCPS_CH_AUX_MIN) &&
- (Channel <= XADCPS_CH_AUX_MAX)) ||
- (Channel == XADCPS_CH_VPVN)){
- RegValue |= XADCPS_CFR0_ACQ_MASK;
- } else {
- return XST_FAILURE;
- }
-
- }
-
- /*
- * Select the input mode. The input mode is only valid for the
- * external channels.
- */
- if (IsDifferentialMode == 0x1) {
-
- if ((Channel >= XADCPS_CH_AUX_MIN) ||
- (Channel == XADCPS_CH_VPVN)){
- RegValue |= XADCPS_CFR0_DU_MASK;
- } else {
- return XST_FAILURE;
- }
- }
-
- /*
- * Select the ADC mode.
- */
- if (IsEventMode == 0x1) {
- RegValue |= XADCPS_CFR0_EC_MASK;
- }
-
- /*
- * Write the given values into the Configuration Register 0.
- */
- RegValue |= ((u32)Channel & XADCPS_CFR0_CHANNEL_MASK);
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
- RegValue);
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* This function enables the alarm outputs for the specified alarms in the
-* Configuration Register 1.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param AlmEnableMask is the bit-mask of the alarm outputs to be enabled
-* in the Configuration Register 1.
-* Bit positions of 1 will be enabled. Bit positions of 0 will be
-* disabled. This mask is formed by OR'ing XADCPS_CFR1_ALM_*_MASK and
-* XADCPS_CFR1_OT_MASK masks defined in xadcps_hw.h.
-*
-* @return None.
-*
-* @note The implementation of the alarm enables in the Configuration
-* register 1 is such that the alarms for bit positions of 1 will
-* be disabled and alarms for bit positions of 0 will be enabled.
-* The alarm outputs specified by the AlmEnableMask are negated
-* before writing to the Configuration Register 1.
-*
-*
-*****************************************************************************/
-void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- RegValue = XAdcPs_ReadInternalReg(InstancePtr, XADCPS_CFR1_OFFSET);
-
- RegValue &= ~XADCPS_CFR1_ALM_ALL_MASK;
- RegValue |= (~(u32)AlmEnableMask & XADCPS_CFR1_ALM_ALL_MASK);
-
- /*
- * Enable/disables the alarm enables for the specified alarm bits in the
- * Configuration Register 1.
- */
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
- RegValue);
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the status of the alarm output enables in the
-* Configuration Register 1.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return This is the bit-mask of the enabled alarm outputs in the
-* Configuration Register 1. Use the masks XADCPS_CFR1_ALM*_* and
-* XADCPS_CFR1_OT_MASK defined in xadcps_hw.h to interpret the
-* returned value.
-* Bit positions of 1 indicate that the alarm output is enabled.
-* Bit positions of 0 indicate that the alarm output is disabled.
-*
-*
-* @note The implementation of the alarm enables in the Configuration
-* register 1 is such that alarms for the bit positions of 1 will
-* be disabled and alarms for bit positions of 0 will be enabled.
-* The enabled alarm outputs returned by this function is the
-* negated value of the the data read from the Configuration
-* Register 1.
-*
-*****************************************************************************/
-u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the status of alarm output enables from the Configuration
- * Register 1.
- */
- RegValue = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR1_OFFSET) & XADCPS_CFR1_ALM_ALL_MASK;
- return (u16) (~RegValue & XADCPS_CFR1_ALM_ALL_MASK);
-}
-
-/****************************************************************************/
-/**
-*
-* This function enables the specified calibration in the Configuration
-* Register 1 :
-*
-* - XADCPS_CFR1_CAL_ADC_OFFSET_MASK : Calibration 0 -ADC offset correction
-* - XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : Calibration 1 -ADC gain and offset
-* correction
-* - XADCPS_CFR1_CAL_PS_OFFSET_MASK : Calibration 2 -Power Supply sensor
-* offset correction
-* - XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Calibration 3 -Power Supply sensor
-* gain and offset correction
-* - XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Calibration is the Calibration to be applied.
-* Use XADCPS_CFR1_CAL*_* bits defined in xadcps_hw.h.
-* Multiple calibrations can be enabled at a time by oring the
-* XADCPS_CFR1_CAL_ADC_* and XADCPS_CFR1_CAL_PS_* bits.
-* Calibration can be disabled by specifying
- XADCPS_CFR1_CAL_DISABLE_MASK;
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(((Calibration >= XADCPS_CFR1_CAL_ADC_OFFSET_MASK) &&
- (Calibration <= XADCPS_CFR1_CAL_VALID_MASK)) ||
- (Calibration == XADCPS_CFR1_CAL_DISABLE_MASK));
-
- /*
- * Set the specified calibration in the Configuration Register 1.
- */
- RegValue = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR1_OFFSET);
-
- RegValue &= ~XADCPS_CFR1_CAL_VALID_MASK;
- RegValue |= ((u32)Calibration & XADCPS_CFR1_CAL_VALID_MASK);
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
- RegValue);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function reads the value of the calibration enables from the
-* Configuration Register 1.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return The value of the calibration enables in the Configuration
-* Register 1 :
-* - XADCPS_CFR1_CAL_ADC_OFFSET_MASK : ADC offset correction
-* - XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : ADC gain and offset
-* correction
-* - XADCPS_CFR1_CAL_PS_OFFSET_MASK : Power Supply sensor offset
-* correction
-* - XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Power Supply sensor
-* gain and offset correction
-* - XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration
-*
-* @note None.
-*
-*****************************************************************************/
-u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the calibration enables from the Configuration Register 1.
- */
- return (u16) XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR1_OFFSET) & XADCPS_CFR1_CAL_VALID_MASK;
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the specified Channel Sequencer Mode in the Configuration
-* Register 1 :
-* - Default safe mode (XADCPS_SEQ_MODE_SAFE)
-* - One pass through sequence (XADCPS_SEQ_MODE_ONEPASS)
-* - Continuous channel sequencing (XADCPS_SEQ_MODE_CONTINPASS)
-* - Single Channel/Sequencer off (XADCPS_SEQ_MODE_SINGCHAN)
-* - Simulataneous sampling mode (XADCPS_SEQ_MODE_SIMUL_SAMPLING)
-* - Independent mode (XADCPS_SEQ_MODE_INDEPENDENT)
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param SequencerMode is the sequencer mode to be set.
-* Use XADCPS_SEQ_MODE_* bits defined in xadcps.h.
-* @return None.
-*
-* @note Only one of the modes can be enabled at a time. Please
-* read the Spec of the XADC for further information about the
-* sequencer modes.
-*
-*
-*****************************************************************************/
-void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((SequencerMode <= XADCPS_SEQ_MODE_SIMUL_SAMPLING) ||
- (SequencerMode == XADCPS_SEQ_MODE_INDEPENDENT));
-
- /*
- * Set the specified sequencer mode in the Configuration Register 1.
- */
- RegValue = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR1_OFFSET);
- RegValue &= (~ XADCPS_CFR1_SEQ_VALID_MASK);
- RegValue |= (((u32)SequencerMode << XADCPS_CFR1_SEQ_SHIFT) &
- XADCPS_CFR1_SEQ_VALID_MASK);
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
- RegValue);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the channel sequencer mode from the Configuration
-* Register 1.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return The channel sequencer mode :
-* - XADCPS_SEQ_MODE_SAFE : Default safe mode
-* - XADCPS_SEQ_MODE_ONEPASS : One pass through sequence
-* - XADCPS_SEQ_MODE_CONTINPASS : Continuous channel sequencing
-* - XADCPS_SEQ_MODE_SINGCHAN : Single channel/Sequencer off
-* - XADCPS_SEQ_MODE_SIMUL_SAMPLING : Simulataneous sampling mode
-* - XADCPS_SEQ_MODE_INDEPENDENT : Independent mode
-*
-*
-* @note None.
-*
-*****************************************************************************/
-u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the channel sequencer mode from the Configuration Register 1.
- */
- return ((u8) ((XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR1_OFFSET) & XADCPS_CFR1_SEQ_VALID_MASK) >>
- XADCPS_CFR1_SEQ_SHIFT));
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the frequency of the ADCCLK by configuring the DCLK to
-* ADCCLK ratio in the Configuration Register #2
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Divisor is clock divisor used to derive ADCCLK from DCLK.
-* Valid values of the divisor are
-* - 0 to 255. Values 0, 1, 2 are all mapped to 2.
-* Refer to the device specification for more details
-*
-* @return None.
-*
-* @note - The ADCCLK is an internal clock used by the ADC and is
-* synchronized to the DCLK clock. The ADCCLK is equal to DCLK
-* divided by the user selection in the Configuration Register 2.
-* - There is no Assert on the minimum value of the Divisor.
-*
-*****************************************************************************/
-void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Write the divisor value into the Configuration Register #2.
- */
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET,
- ((u32)Divisor << XADCPS_CFR2_CD_SHIFT));
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function gets the ADCCLK divisor from the Configuration Register 2.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return The divisor read from the Configuration Register 2.
-*
-* @note The ADCCLK is an internal clock used by the ADC and is
-* synchronized to the DCLK clock. The ADCCLK is equal to DCLK
-* divided by the user selection in the Configuration Register 2.
-*
-*****************************************************************************/
-u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr)
-{
- u16 Divisor;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the divisor value from the Configuration Register 2.
- */
- Divisor = (u16) XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR2_OFFSET);
-
- return (u8) (Divisor >> XADCPS_CFR2_CD_SHIFT);
-}
-
-/****************************************************************************/
-/**
-*
-* This function enables the specified channels in the ADC Channel Selection
-* Sequencer Registers. The sequencer must be disabled before writing to these
-* regsiters.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param ChEnableMask is the bit mask of all the channels to be enabled.
-* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel
-* numbers. Bit masks of 1 will be enabled and bit mask of 0 will
-* be disabled.
-* The ChEnableMask is a 32 bit mask that is written to the two
-* 16 bit ADC Channel Selection Sequencer Registers.
-*
-* @return
-* - XST_SUCCESS if the given values were written successfully to
-* the ADC Channel Selection Sequencer Registers.
-* - XST_FAILURE if the channel sequencer is enabled.
-*
-* @note None
-*
-*****************************************************************************/
-int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * The sequencer must be disabled for writing any of these registers
- * Return XST_FAILURE if the channel sequencer is enabled.
- */
- if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
- return XST_FAILURE;
- }
-
- /*
- * Enable the specified channels in the ADC Channel Selection Sequencer
- * Registers.
- */
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_SEQ00_OFFSET,
- (ChEnableMask & XADCPS_SEQ00_CH_VALID_MASK));
-
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_SEQ01_OFFSET,
- (ChEnableMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
- XADCPS_SEQ01_CH_VALID_MASK);
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the channel enable bits status from the ADC Channel
-* Selection Sequencer Registers.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return Gets the channel enable bits. Use XADCPS_SEQ_CH__* defined in
-* xadcps_hw.h to interpret the Channel numbers. Bit masks of 1
-* are the channels that are enabled and bit mask of 0 are
-* the channels that are disabled.
-*
-* @return None
-*
-* @note None
-*
-*****************************************************************************/
-u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr)
-{
- u32 RegValEnable;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the channel enable bits for all the channels from the ADC
- * Channel Selection Register.
- */
- RegValEnable = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_SEQ00_OFFSET) &
- XADCPS_SEQ00_CH_VALID_MASK;
- RegValEnable |= (XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_SEQ01_OFFSET) &
- XADCPS_SEQ01_CH_VALID_MASK) <<
- XADCPS_SEQ_CH_AUX_SHIFT;
-
-
- return RegValEnable;
-}
-
-/****************************************************************************/
-/**
-*
-* This function enables the averaging for the specified channels in the ADC
-* Channel Averaging Enable Sequencer Registers. The sequencer must be disabled
-* before writing to these regsiters.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param AvgEnableChMask is the bit mask of all the channels for which
-* averaging is to be enabled. Use XADCPS_SEQ_CH__* defined in
-* xadcps_hw.h to specify the Channel numbers. Averaging will be
-* enabled for bit masks of 1 and disabled for bit mask of 0.
-* The AvgEnableChMask is a 32 bit mask that is written to the two
-* 16 bit ADC Channel Averaging Enable Sequencer Registers.
-*
-* @return
-* - XST_SUCCESS if the given values were written successfully to
-* the ADC Channel Averaging Enables Sequencer Registers.
-* - XST_FAILURE if the channel sequencer is enabled.
-*
-* @note None
-*
-*****************************************************************************/
-int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * The sequencer must be disabled for writing any of these registers
- * Return XST_FAILURE if the channel sequencer is enabled.
- */
- if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
- return XST_FAILURE;
- }
-
- /*
- * Enable/disable the averaging for the specified channels in the
- * ADC Channel Averaging Enables Sequencer Registers.
- */
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_SEQ02_OFFSET,
- (AvgEnableChMask & XADCPS_SEQ02_CH_VALID_MASK));
-
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_SEQ03_OFFSET,
- (AvgEnableChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
- XADCPS_SEQ03_CH_VALID_MASK);
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the channels for which the averaging has been enabled
-* in the ADC Channel Averaging Enables Sequencer Registers.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @returns The status of averaging (enabled/disabled) for all the channels.
-* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the
-* Channel numbers. Bit masks of 1 are the channels for which
-* averaging is enabled and bit mask of 0 are the channels for
-* averaging is disabled
-*
-* @note None
-*
-*****************************************************************************/
-u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr)
-{
- u32 RegValAvg;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the averaging enable status for all the channels from the
- * ADC Channel Averaging Enables Sequencer Registers.
- */
- RegValAvg = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_SEQ02_OFFSET) & XADCPS_SEQ02_CH_VALID_MASK;
- RegValAvg |= (XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_SEQ03_OFFSET) & XADCPS_SEQ03_CH_VALID_MASK) <<
- XADCPS_SEQ_CH_AUX_SHIFT;
-
- return RegValAvg;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the Analog input mode for the specified channels in the ADC
-* Channel Analog-Input Mode Sequencer Registers. The sequencer must be disabled
-* before writing to these regsiters.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param InputModeChMask is the bit mask of all the channels for which
-* the input mode is differential mode. Use XADCPS_SEQ_CH__* defined
-* in xadcps_hw.h to specify the channel numbers. Differential
-* input mode will be set for bit masks of 1 and unipolar input
-* mode for bit masks of 0.
-* The InputModeChMask is a 32 bit mask that is written to the two
-* 16 bit ADC Channel Analog-Input Mode Sequencer Registers.
-*
-* @return
-* - XST_SUCCESS if the given values were written successfully to
-* the ADC Channel Analog-Input Mode Sequencer Registers.
-* - XST_FAILURE if the channel sequencer is enabled.
-*
-* @note None
-*
-*****************************************************************************/
-int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * The sequencer must be disabled for writing any of these registers
- * Return XST_FAILURE if the channel sequencer is enabled.
- */
- if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
- return XST_FAILURE;
- }
-
- /*
- * Set the input mode for the specified channels in the ADC Channel
- * Analog-Input Mode Sequencer Registers.
- */
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_SEQ04_OFFSET,
- (InputModeChMask & XADCPS_SEQ04_CH_VALID_MASK));
-
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_SEQ05_OFFSET,
- (InputModeChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
- XADCPS_SEQ05_CH_VALID_MASK);
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the Analog input mode for all the channels from
-* the ADC Channel Analog-Input Mode Sequencer Registers.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @returns The input mode for all the channels.
-* Use XADCPS_SEQ_CH_* defined in xadcps_hw.h to interpret the
-* Channel numbers. Bit masks of 1 are the channels for which
-* input mode is differential and bit mask of 0 are the channels
-* for which input mode is unipolar.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr)
-{
- u32 InputMode;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Get the input mode for all the channels from the ADC Channel
- * Analog-Input Mode Sequencer Registers.
- */
- InputMode = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_SEQ04_OFFSET) &
- XADCPS_SEQ04_CH_VALID_MASK;
- InputMode |= (XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_SEQ05_OFFSET) &
- XADCPS_SEQ05_CH_VALID_MASK) <<
- XADCPS_SEQ_CH_AUX_SHIFT;
-
- return InputMode;
-}
-
-/****************************************************************************/
-/**
-*
-* This function sets the number of Acquisition cycles in the ADC Channel
-* Acquisition Time Sequencer Registers. The sequencer must be disabled
-* before writing to these regsiters.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param AcqCyclesChMask is the bit mask of all the channels for which
-* the number of acquisition cycles is to be extended.
-* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel
-* numbers. Acquisition cycles will be extended to 10 ADCCLK cycles
-* for bit masks of 1 and will be the default 4 ADCCLK cycles for
-* bit masks of 0.
-* The AcqCyclesChMask is a 32 bit mask that is written to the two
-* 16 bit ADC Channel Acquisition Time Sequencer Registers.
-*
-* @return
-* - XST_SUCCESS if the given values were written successfully to
-* the Channel Sequencer Registers.
-* - XST_FAILURE if the channel sequencer is enabled.
-*
-* @note None.
-*
-*****************************************************************************/
-int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * The sequencer must be disabled for writing any of these registers
- * Return XST_FAILURE if the channel sequencer is enabled.
- */
- if ((XAdcPs_GetSequencerMode(InstancePtr) !=
- XADCPS_SEQ_MODE_SAFE)) {
- return XST_FAILURE;
- }
-
- /*
- * Set the Acquisition time for the specified channels in the
- * ADC Channel Acquisition Time Sequencer Registers.
- */
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_SEQ06_OFFSET,
- (AcqCyclesChMask & XADCPS_SEQ06_CH_VALID_MASK));
-
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_SEQ07_OFFSET,
- (AcqCyclesChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
- XADCPS_SEQ07_CH_VALID_MASK);
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the status of acquisition from the ADC Channel Acquisition
-* Time Sequencer Registers.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @returns The acquisition time for all the channels.
-* Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the
-* Channel numbers. Bit masks of 1 are the channels for which
-* acquisition cycles are extended and bit mask of 0 are the
-* channels for which acquisition cycles are not extended.
-*
-* @note None
-*
-*****************************************************************************/
-u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr)
-{
- u32 RegValAcq;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Get the Acquisition cycles for the specified channels from the ADC
- * Channel Acquisition Time Sequencer Registers.
- */
- RegValAcq = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_SEQ06_OFFSET) &
- XADCPS_SEQ06_CH_VALID_MASK;
- RegValAcq |= (XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_SEQ07_OFFSET) &
- XADCPS_SEQ07_CH_VALID_MASK) <<
- XADCPS_SEQ_CH_AUX_SHIFT;
-
- return RegValAcq;
-}
-
-/****************************************************************************/
-/**
-*
-* This functions sets the contents of the given Alarm Threshold Register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param AlarmThrReg is the index of an Alarm Threshold Register to
-* be set. Use XADCPS_ATR_* constants defined in xadcps.h to
-* specify the index.
-* @param Value is the 16-bit threshold value to write into the register.
-*
-* @return None.
-*
-* @note Use XAdcPs_SetOverTemp() to set the Over Temperature upper
-* threshold value.
-*
-*****************************************************************************/
-void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value)
-{
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(AlarmThrReg <= XADCPS_ATR_VCCPDRO_LOWER);
-
- /*
- * Write the value into the specified Alarm Threshold Register.
- */
- XAdcPs_WriteInternalReg(InstancePtr, (XADCPS_ATR_TEMP_UPPER_OFFSET +
- (u32)AlarmThrReg), Value);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the contents of the specified Alarm Threshold Register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param AlarmThrReg is the index of an Alarm Threshold Register
-* to be read. Use XADCPS_ATR_* constants defined in xadcps_hw.h
-* to specify the index.
-*
-* @return A 16-bit value representing the contents of the selected Alarm
-* Threshold Register.
-*
-* @note None.
-*
-*****************************************************************************/
-u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg)
-{
- u32 RegData;
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(AlarmThrReg <= XADCPS_ATR_VCCPDRO_LOWER);
-
- /*
- * Read the specified Alarm Threshold Register and return
- * the value
- */
- RegData = XAdcPs_ReadInternalReg(InstancePtr,
- (XADCPS_ATR_TEMP_UPPER_OFFSET +
- (u32)AlarmThrReg));
-
- return (u16) RegData;
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function enables programming of the powerdown temperature for the
-* OverTemp signal in the OT Powerdown register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr)
-{
- u16 OtUpper;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the OT upper Alarm Threshold Register.
- */
- OtUpper = (u16)(XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_ATR_OT_UPPER_OFFSET));
- OtUpper &= ~((u16)XADCPS_ATR_OT_UPPER_ENB_MASK);
-
- /*
- * Preserve the powerdown value and write OT enable value the into the
- * OT Upper Alarm Threshold Register.
- */
- OtUpper |= XADCPS_ATR_OT_UPPER_ENB_VAL;
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_ATR_OT_UPPER_OFFSET, (u32)OtUpper);
-}
-
-/****************************************************************************/
-/**
-*
-* This function disables programming of the powerdown temperature for the
-* OverTemp signal in the OT Powerdown register.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return None.
-*
-* @note None.
-*
-*
-*****************************************************************************/
-void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr)
-{
- u16 OtUpper;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the OT Upper Alarm Threshold Register.
- */
- OtUpper = (u16)(XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_ATR_OT_UPPER_OFFSET));
- OtUpper &= ~((u16)XADCPS_ATR_OT_UPPER_ENB_MASK);
-
- XAdcPs_WriteInternalReg(InstancePtr,
- XADCPS_ATR_OT_UPPER_OFFSET, (u32)OtUpper);
-}
-
-
-/****************************************************************************/
-/**
-*
-* The function enables the Event mode or Continuous mode in the sequencer mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param IsEventMode is a boolean parameter that specifies continuous
-* sampling (specify FALSE) or event driven sampling mode (specify
-* TRUE) for the given channel.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((IsEventMode == 0x1) || (IsEventMode == 0x0));
-
- /*
- * Read the Configuration Register 0.
- */
- RegValue = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR0_OFFSET) &
- (~XADCPS_CFR0_EC_MASK);
-
- /*
- * Set the ADC mode.
- */
- if (IsEventMode == 0x1) {
- RegValue |= XADCPS_CFR0_EC_MASK;
- } else {
- RegValue &= ~XADCPS_CFR0_EC_MASK;
- }
-
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
- RegValue);
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function returns the sampling mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return The sampling mode
-* - 0 specifies continuous sampling
-* - 1 specifies event driven sampling mode
-*
-* @note None.
-*
-*****************************************************************************/
-int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr)
-{
- u32 Mode;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the sampling mode from the Configuration Register 0.
- */
- Mode = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR0_OFFSET) &
- XADCPS_CFR0_EC_MASK;
- if (Mode > 0U) {
-
- return 1;
- }
-
- return (0);
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function sets the External Mux mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param MuxMode specifies whether External Mux is used
-* - FALSE specifies NO external MUX
-* - TRUE specifies External Mux is used
-* @param Channel specifies the channel to be used for the
-* external Mux. Please read the Device Spec for which
-* channels are valid for which mode.
-*
-* @return None.
-*
-* @note There is no Assert in this function for checking the channel
-* number if the external Mux is used. The user should provide a
-* valid channel number.
-*
-*****************************************************************************/
-void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((MuxMode == 0x1) || (MuxMode == 0x0));
-
- /*
- * Read the Configuration Register 0.
- */
- RegValue = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR0_OFFSET) &
- (~XADCPS_CFR0_MUX_MASK);
- /*
- * Select the Mux mode and the channel to be used.
- */
- if (MuxMode == 0x1) {
- RegValue |= XADCPS_CFR0_MUX_MASK;
- RegValue |= ((u32)Channel & XADCPS_CFR0_CHANNEL_MASK);
-
- }
-
- /*
- * Write the mux mode into the Configuration Register 0.
- */
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
- RegValue);
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function sets the Power Down mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Mode specifies the Power Down Mode
-* - XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and
-* ADC B are enabled)
-* - XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B
-* - XADCPS_PD_MODE_XADC specifies the Power Down of
-* both ADC A and ADC B.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Mode < XADCPS_PD_MODE_XADC);
-
-
- /*
- * Read the Configuration Register 2.
- */
- RegValue = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR2_OFFSET) &
- (~XADCPS_CFR2_PD_MASK);
- /*
- * Select the Power Down mode.
- */
- RegValue |= (Mode << XADCPS_CFR2_PD_SHIFT);
-
- XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET,
- RegValue);
-}
-
-/****************************************************************************/
-/**
-*
-* This function gets the Power Down mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return Mode specifies the Power Down Mode
-* - XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and
-* ADC B are enabled)
-* - XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B
-* - XADCPS_PD_MODE_XADC specifies the Power Down of
-* both ADC A and ADC B.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Power Down Mode.
- */
- RegValue = XAdcPs_ReadInternalReg(InstancePtr,
- XADCPS_CFR2_OFFSET) &
- (~XADCPS_CFR2_PD_MASK);
- /*
- * Return the Power Down mode.
- */
- return (RegValue >> XADCPS_CFR2_PD_SHIFT);
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function is used for writing to XADC Registers using the command FIFO.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param RegOffset is the offset of the XADC register to be written.
-* @param Data is the data to be written.
-*
-* @return None.
-*
-* @note None.
-*
-*
-*****************************************************************************/
-void XAdcPs_WriteInternalReg(XAdcPs *InstancePtr, u32 RegOffset, u32 Data)
-{
- u32 RegData;
-
- /**
- * Write the Data into the FIFO Register.
- */
- RegData = (XADCPS_JTAG_CMD_WRITE_MASK) |
- ((RegOffset << XADCPS_JTAG_ADDR_SHIFT) & XADCPS_JTAG_ADDR_MASK) |
- (Data & XADCPS_JTAG_DATA_MASK);
-
- XAdcPs_WriteFifo(InstancePtr, RegData);
-
- /**
- * Read the Read FIFO after any write since for each write
- * one location of Read FIFO gets updated
- */
- XAdcPs_ReadFifo(InstancePtr);
-
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function is used for reading from the XADC Registers using the Data FIFO.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param RegOffset is the offset of the XADC register to be read.
-*
-* @return Data read from the FIFO
-*
-* @note None.
-*
-*
-*****************************************************************************/
-u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset)
-{
-
- u32 RegData;
-
- RegData = (XADCPS_JTAG_CMD_READ_MASK) |
- ((RegOffset << XADCPS_JTAG_ADDR_SHIFT) & XADCPS_JTAG_ADDR_MASK);
-
- /* Read cmd to FIFO*/
- XAdcPs_WriteFifo(InstancePtr, RegData);
-
- /* Do a Dummy read */
- RegData = XAdcPs_ReadFifo(InstancePtr);
-
- /* Do a Dummy write to get the actual read */
- XAdcPs_WriteFifo(InstancePtr, RegData);
-
- /* Do the Actual read */
- RegData = XAdcPs_ReadFifo(InstancePtr);
-
- return RegData;
-
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/98/c1d993575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/98/c1d993575243001d18b399c1eb9b3628
deleted file mode 100644
index e79ba0d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/98/c1d993575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,788 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xqspips.h
-* @addtogroup qspips_v3_9
-* @{
-* @details
-*
-* This file contains the implementation of the XQspiPs driver. It supports only
-* master mode. User documentation for the driver functions is contained in this
-* file in the form of comment blocks at the front of each function.
-*
-* A QSPI device connects to an QSPI bus through a 4-wire serial interface.
-* The QSPI bus is a full-duplex, synchronous bus that facilitates communication
-* between one master and one slave. The device is always full-duplex,
-* which means that for every byte sent, one is received, and vice-versa.
-* The master controls the clock, so it can regulate when it wants to
-* send or receive data. The slave is under control of the master, it must
-* respond quickly since it has no control of the clock and must send/receive
-* data as fast or as slow as the master does.
-*
-* Linear Mode
-* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller�s
-* functionality by adding a linear addressing scheme that allows the SPI flash
-* memory subsystem to behave like a typical ROM device. The new feature hides
-* the normal SPI protocol from a master reading from the SPI flash memory. The
-* feature improves both the user friendliness and the overall read memory
-* throughput over that of the current Quad-SPI Controller by lessening the
-* amount of software overheads required and by the use of the faster AXI
-* interface.
-*
-* Initialization & Configuration
-*
-* The XQspiPs_Config structure is used by the driver to configure itself. This
-* configuration structure is typically created by the tool-chain based on HW
-* build properties.
-*
-* To support multiple runtime loading and initialization strategies employed by
-* various operating systems, the driver instance can be initialized in the
-* following way:
-* - XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find
-* static configuration structure defined in xqspips_g.c. This is setup
-* by the tools. For some operating systems the config structure will be
-* initialized by the software and this call is not needed.
-* - XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-* configuration structure provided by the caller. If running in a system
-* with address translation, the provided virtual memory base address
-* replaces the physical address present in the configuration structure.
-*
-* Multiple Masters
-*
-* More than one master can exist, but arbitration is the responsibility of
-* the higher layer software. The device driver does not perform any type of
-* arbitration.
-*
-* Modes of Operation
-*
-* There are four modes to perform a data transfer and the selection of a mode
-* is based on Chip Select(CS) and Start. These two options individually, can
-* be controlled either by software(Manual) or hardware(Auto).
-* - Auto CS: Chip select is automatically asserted as soon as the first word
-* is written into the TXFIFO and de asserted when the TXFIFO becomes
-* empty
-* - Manual CS: Software must assert and de assert CS.
-* - Auto Start: Data transmission starts as soon as there is data in the
-* TXFIFO and stalls when the TXFIFO is empty
-* - Manual Start: Software must start data transmission at the beginning of
-* the transaction or whenever the TXFIFO has become empty
-*
-* The preferred combination is Manual CS and Auto Start.
-* In this combination, the software asserts CS before loading any data into
-* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
-* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
-* data is available. If no further data, software disables CS.
-*
-* Risks/challenges of other combinations:
-* - Manual CS and Manual Start: Manual Start bit should be set after each
-* TXFIFO write otherwise there could be a race condition where the TXFIFO
-* becomes empty before the new word is written. In that case the
-* transmission stops.
-* - Auto CS with Manual or Auto Start: It is very difficult for software to
-* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted.
-* This results in a single transaction to be split into multiple pieces each
-* with its own chip select. This will result in garbage data to be sent.
-*
-* Interrupts
-*
-* The user must connect the interrupt handler of the driver,
-* XQspiPs_InterruptHandler, to an interrupt system such that it will be
-* called when an interrupt occurs. This function does not save and restore
-* the processor context such that the user must provide this processing.
-*
-* The driver handles the following interrupts:
-* - Data Transmit Register/FIFO Underflow
-* - Data Receive Register/FIFO Not Empty
-* - Data Transmit Register/FIFO Overwater
-* - Data Receive Register/FIFO Overrun
-*
-* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
-* QSPI device has transmitted the data available to transmit, and now its data
-* register and FIFO is ready to accept more data. The driver uses this
-* interrupt to indicate progress while sending data. The driver may have
-* more data to send, in which case the data transmit register and FIFO is
-* filled for subsequent transmission. When this interrupt arrives and all
-* the data has been sent, the driver invokes the status callback with a
-* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
-* all data has been sent.
-*
-* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
-* as slave, the QSPI device was required to transmit but there was no data
-* available to transmit in the transmit register (or FIFO). This may not
-* be an error if the master is not expecting data. But in the case where
-* the master is expecting data, this serves as a notification of such a
-* condition. The driver reports this condition to the upper layer
-* software through the status handler.
-*
-* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI
-* device received data and subsequently dropped the data because the data
-* receive register and FIFO was full. The driver reports this condition to the
-* upper layer software through the status handler. This likely indicates a
-* problem with the higher layer protocol, or a problem with the slave
-* performance.
-*
-*
-* Polled Operation
-*
-* Transfer in polled mode is supported through a separate interface function
-* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
-* this function blocks until all data has been sent/received.
-*
-* Device Busy
-*
-* Some operations are disallowed when the device is busy. The driver tracks
-* whether a device is busy. The device is considered busy when a data transfer
-* request is outstanding, and is considered not busy only when that transfer
-* completes (or is aborted with a mode fault error).
-*
-* Device Configuration
-*
-* The device can be configured in various ways during the FPGA implementation
-* process. Configuration parameters are stored in the xqspips_g.c file or
-* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry
-* contains configuration information for an QSPI device, including the base
-* address for the device.
-*
-* RTOS Independence
-*
-* This driver is intended to be RTOS and processor independent. It works with
-* physical addresses only. Any needs for dynamic memory management, threads or
-* thread mutual exclusion, virtual memory, or cache control must be satisfied
-* by the layer above this driver.
-*
-* NOTE: This driver was always tested with endianness set to little-endian.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
-* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
-* in xparameters.h
-* 2.00a kka 07/25/12 Added a few register defines for CR 670297
-* Removed code related to mode fault for CR 671468
-* The XQspiPs_SetSlaveSelect has been modified to remove
-* the argument of the slave select as the QSPI controller
-* only supports one slave.
-* XQspiPs_GetSlaveSelect API has been removed
-* Added a flag ShiftReadData to the instance structure
-*. and is used in the XQspiPs_GetReadData API.
-* The ShiftReadData Flag indicates whether the data
-* read from the Rx FIFO needs to be shifted
-* in cases where the data is less than 4 bytes
-* Removed the selection for the following options:
-* Master mode (XQSPIPS_MASTER_OPTION) and
-* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
-* as the QSPI driver supports the Master mode
-* and Flash Interface mode and doesnot support
-* Slave mode or the legacy mode.
-* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
-* APIs so that the last argument (IsInst) specifying whether
-* it is instruction or data has been removed. The first byte
-* in the SendBufPtr argument of these APIs specify the
-* instruction to be sent to the Flash Device.
-* This version of the driver fixes CRs 670197/663787/
-* 670297/671468.
-* Added the option for setting the Holdb_dr bit in the
-* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
-* is the option to be used for setting this bit in the
-* configuration register.
-* The XQspiPs_PolledTransfer function has been updated
-* to fill the data to fifo depth.
-* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
-* Added macros for Set/Get Rx Watermark. Changed QSPI
-* Enable/Disable macro argument from BaseAddress to
-* Instance Pointer. Added DelayNss argument to SetDelays
-* and GetDelays API's.
-* Created macros XQspiPs_IsManualStart and
-* XQspiPs_IsManualChipSelect.
-* Changed QSPI transfer logic for polled and interrupt
-* modes to be based on filled tx fifo count and receive
-* based on it. RXNEMPTY interrupt is not used.
-* Added assertions to XQspiPs_LqspiRead function.
-* SetDelays and GetDelays API's include DelayNss parameter.
-* Added defines for DelayNss,Rx Watermark,Interrupts
-* which need write to clear. Removed Read zeros mask from
-* LQSPI Config register. Renamed Fixed burst error to
-* data FSM error in LQSPI Status register.
-*
-* 2.02a hk 05/07/13 Added ConnectionMode to config structure.
-* Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
-* Added enable and disable to the XQspiPs_LqspiRead() function
-* Removed XQspi_Reset() in Set_Options() function when
-* LQSPI_MODE_OPTION is set.
-* Added instructions for bank selection, die erase and
-* flag status register to the flash instruction table
-* Handling for instructions not in flash instruction
-* table added. Checking for Tx FIFO empty when switching from
-* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
-* byte count 3 (spansion), instruction size and TXD register
-* changed accordingly. CR# 712502 and 703869.
-* Added prefix to constant definitions for ConnectionMode
-* Added (\#ifdef linear base address) in the Linear read function.
-* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to
-* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
-* XQspiPs_LqspiRead function. Fix for CR#718141.
-*
-* 2.03a hk 09/17/13 Modified polled and interrupt transfers to make use of
-* thresholds. This is to improve performance.
-* Added API's for QSPI reset and
-* linear mode initialization for boot.
-* Added RX and TX threshold reset to one in XQspiPs_Abort.
-* Added RX threshold reset(1) after transfer in polled and
-* interrupt transfers. Made changes to make sure threshold
-* change is done only when no transfer is in progress.
-* Updated linear init API for parallel and stacked modes.
-* CR#737760.
-* 3.1 hk 08/13/14 When writing to the configuration register, set/reset
-* required bits leaving reserved bits untouched. CR# 796813.
-* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
-* controller does not update FIFO status flags as expected
-* when thresholds are used.
-* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
-* to remove compilation warnings. CR# 868893.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/05/17 Modified Comment lines in functions of qspips
-* examples to recognize it as documentation block
-* and modified filename tag in
-* xqspips_dual_flash_stack_lqspi_example.c to include it in
-* doxygen examples.
-* 3.4 nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file
-* 3.5 tjs 08/21/18 Fixed compilation warnings for the ARMCC.
-* 3.5 tjs 07/16/18 Added support for low density ISSI flash parts.
-* 3.6 akm 03/28/19 Fixed memory leak issue while reading from qspi.(CR#1016357)
-* 3.6 akm 04/15/19 Modified FlashQuadEnable, FlashWrie and FlashErase APIs,
-* to wait for the on going operation to complete before
-* performing the next operation.
-* 3.6 akm 04/15/19 Modified the mask in XQspiPs_GetReadData() API to retrieve
-* configuration register values of both the Flashes in dual
-* parellel connection.
-* 3.7 akm 11/19/19 Fixed Coverity unused value warning in XQspiPs_PolledTransfer()
-* and XQspiPs_Transfer() APIs.
-* 3.7 akm 03/19/20 Modified XQspiPs_PolledTransfer(), XQspiPs_Transfer() and
-* XQspiPs_InterruptHandler() APIs to fill TX FIFO with valid
-* data when RX buffer is not NULL.
-* 3.8 akm 09/02/20 Updated the Makefile to support parallel make execution.
-*
-*
-*
-******************************************************************************/
-#ifndef XQSPIPS_H /* prevent circular inclusions */
-#define XQSPIPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xqspips_hw.h"
-#include
-
-/************************** Constant Definitions *****************************/
-
-/** @name Configuration options
- *
- * The following options are supported to enable/disable certain features of
- * an QSPI device. Each of the options is a bit mask, so more than one may be
- * specified.
- *
- *
- * The Active Low Clock option configures the device's clock polarity.
- * Setting this option means the clock is active low and the SCK signal idles
- * high. By default, the clock is active high and SCK idles low.
- *
- * The Clock Phase option configures the QSPI device for one of two
- * transfer formats. A clock phase of 0, the default, means data is valid on
- * the first SCK edge (rising or falling) after the slave select (SS) signal
- * has been asserted. A clock phase of 1 means data is valid on the second SCK
- * edge (rising or falling) after SS has been asserted.
- *
- *
- * The QSPI Force Slave Select option is used to enable manual control of
- * the slave select signal.
- * 0: The SPI_SS signal is controlled by the QSPI controller during
- * transfers. (Default)
- * 1: The SPI_SS signal is forced active (driven low) regardless of any
- * transfers in progress.
- *
- * NOTE: The driver will handle setting and clearing the Slave Select when
- * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
- * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the
- * processor cannot empty and refill the FIFOs before the TX FIFO is empty
- * When the QSPI hardware is controlling the Slave Select signals, this
- * will cause slave to be de-selected and terminate the transfer.
- *
- * The Manual Start option is used to enable manual control of
- * the Start command to perform data transfer.
- * 0: The Start command is controlled by the QSPI controller during
- * transfers(Default). Data transmission starts as soon as there is data in
- * the TXFIFO and stalls when the TXFIFO is empty
- * 1: The Start command must be issued by software to perform data transfer.
- * Bit 15 of Configuration register is used to issue Start command. This bit
- * must be set whenever TXFIFO is filled with new data.
- *
- * NOTE: The driver will set the Manual Start Enable bit in Configuration
- * Register, if Manual Start option is selected. Software will issue
- * Manual Start command whenever TXFIFO is filled with data. When there is
- * no further data, driver will clear the Manual Start Enable bit.
- *
- * @{
- */
-#define XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2 /**< Active Low Clock option */
-#define XQSPIPS_CLK_PHASE_1_OPTION 0x4 /**< Clock Phase one option */
-#define XQSPIPS_FORCE_SSELECT_OPTION 0x10 /**< Force Slave Select */
-#define XQSPIPS_MANUAL_START_OPTION 0x20 /**< Manual Start enable */
-#define XQSPIPS_LQSPI_MODE_OPTION 0x80 /**< Linear QPSI mode */
-#define XQSPIPS_HOLD_B_DRIVE_OPTION 0x100 /**< Drive HOLD_B Pin */
-/*@}*/
-
-
-/** @name QSPI Clock Prescaler options
- * The QSPI Clock Prescaler Configuration bits are used to program master mode
- * bit rate. The bit rate can be programmed in divide-by-two decrements from
- * pclk/2 to pclk/256.
- *
- * @{
- */
-#define XQSPIPS_CLK_PRESCALE_2 0x00 /**< PCLK/2 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_4 0x01 /**< PCLK/4 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_8 0x02 /**< PCLK/8 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_16 0x03 /**< PCLK/16 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_32 0x04 /**< PCLK/32 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_64 0x05 /**< PCLK/64 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_128 0x06 /**< PCLK/128 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_256 0x07 /**< PCLK/256 Prescaler */
-
-/*@}*/
-
-
-/** @name Callback events
- *
- * These constants specify the handler events that are passed to
- * a handler from the driver. These constants are not bit masks such that
- * only one will be passed at a time to the handler.
- *
- * @{
- */
-#define XQSPIPS_EVENT_TRANSFER_DONE 2 /**< Transfer done */
-#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
-#define XQSPIPS_EVENT_RECEIVE_OVERRUN 4 /**< Receive data loss because
- * RX FIFO full
- */
-/*@}*/
-
-/** @name Flash commands
- *
- * The following constants define most of the commands supported by flash
- * devices. Users can add more commands supported by the flash devices
- *
- * @{
- */
-#define XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */
-#define XQSPIPS_FLASH_OPCODE_PP 0x02 /* Page program */
-#define XQSPIPS_FLASH_OPCODE_NORM_READ 0x03 /* Normal read data bytes */
-#define XQSPIPS_FLASH_OPCODE_WRDS 0x04 /* Write disable */
-#define XQSPIPS_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */
-#define XQSPIPS_FLASH_OPCODE_WREN 0x06 /* Write enable */
-#define XQSPIPS_FLASH_OPCODE_FAST_READ 0x0B /* Fast read data bytes */
-#define XQSPIPS_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */
-#define XQSPIPS_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */
-#define XQSPIPS_FLASH_OPCODE_DUAL_READ 0x3B /* Dual read data bytes */
-#define XQSPIPS_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */
-#define XQSPIPS_FLASH_OPCODE_QUAD_READ 0x6B /* Quad read data bytes */
-#define XQSPIPS_FLASH_OPCODE_ERASE_SUS 0x75 /* Erase suspend */
-#define XQSPIPS_FLASH_OPCODE_ERASE_RES 0x7A /* Erase resume */
-#define XQSPIPS_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */
-#define XQSPIPS_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */
-#define XQSPIPS_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/
-#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */
-#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */
-#define XQSPIPS_FLASH_OPCODE_BRWR 0x17 /* Bank Register Write */
-#define XQSPIPS_FLASH_OPCODE_BRRD 0x16 /* Bank Register Read */
-/* Extende Address Register Write - Micron's equivalent of Bank Register */
-#define XQSPIPS_FLASH_OPCODE_EARWR 0xC5
-/* Extende Address Register Read - Micron's equivalent of Bank Register */
-#define XQSPIPS_FLASH_OPCODE_EARRD 0xC8
-#define XQSPIPS_FLASH_OPCODE_DIE_ERASE 0xC4
-#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR 0x70
-#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR 0x50
-#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG 0xE8 /* Lock Reg Read */
-#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG 0xE5 /* Lock Reg Write */
-
-/*@}*/
-
-/** @name Instruction size
- *
- * The following constants define numbers 1 to 4.
- * Used to identify whether TXD0,1,2 or 3 is to be used.
- *
- * @{
- */
-#define XQSPIPS_SIZE_ONE 1
-#define XQSPIPS_SIZE_TWO 2
-#define XQSPIPS_SIZE_THREE 3
-#define XQSPIPS_SIZE_FOUR 4
-
-/*@}*/
-
-/** @name ConnectionMode
- *
- * The following constants are the possible values of ConnectionMode in
- * Config structure.
- *
- * @{
- */
-#define XQSPIPS_CONNECTION_MODE_SINGLE 0
-#define XQSPIPS_CONNECTION_MODE_STACKED 1
-#define XQSPIPS_CONNECTION_MODE_PARALLEL 2
-
-/*@}*/
-
-/** @name FIFO threshold value
- *
- * This is the Rx FIFO threshold (in words) that was found to be most
- * optimal in terms of performance
- *
- * @{
- */
-#define XQSPIPS_RXFIFO_THRESHOLD_OPT 32
-
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-/**
- * The handler data type allows the user to define a callback function to
- * handle the asynchronous processing for the QSPI device. The application
- * using this driver is expected to define a handler of this type to support
- * interrupt driven mode. The handler executes in an interrupt context, so
- * only minimal processing should be performed.
- *
- * @param CallBackRef is the callback reference passed in by the upper
- * layer when setting the callback functions, and passed back to
- * the upper layer when the callback is invoked. Its type is
- * not important to the driver, so it is a void pointer.
- * @param StatusEvent holds one or more status events that have occurred.
- * See the XQspiPs_SetStatusHandler() for details on the status
- * events that can be passed in the callback.
- * @param ByteCount indicates how many bytes of data were successfully
- * transferred. This may be less than the number of bytes
- * requested if the status event indicates an error.
- */
-typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
- unsigned ByteCount);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of the device */
- u32 InputClockHz; /**< Input clock frequency */
- u8 ConnectionMode; /**< Single, Stacked and Parallel mode */
-} XQspiPs_Config;
-
-/**
- * The XQspiPs driver instance data. The user is required to allocate a
- * variable of this type for every QSPI device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XQspiPs_Config Config; /**< Configuration structure */
- u32 IsReady; /**< Device is initialized and ready */
-
- u8 *SendBufferPtr; /**< Buffer to send (state) */
- u8 *RecvBufferPtr; /**< Buffer to receive (state) */
- int RequestedBytes; /**< Number of bytes to transfer (state) */
- int RemainingBytes; /**< Number of bytes left to transfer(state) */
- u32 IsBusy; /**< A transfer is in progress (state) */
- XQspiPs_StatusHandler StatusHandler;
- void *StatusRef; /**< Callback reference for status handler */
- u32 ShiftReadData; /**< Flag to indicate whether the data
- * read from the Rx FIFO needs to be shifted
- * in cases where the data is less than 4
- * bytes
- */
-} XQspiPs;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/*
-*
-* Check in OptionsTable if Manual Start Option is enabled or disabled.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return
-* - TRUE if option is set
-* - FALSE if option is not set
-*
-* @note C-Style signature:
-* u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr);
-*
-*****************************************************************************/
-#define XQspiPs_IsManualStart(InstancePtr) \
- ((XQspiPs_GetOptions(InstancePtr) & \
- XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
-
-/****************************************************************************/
-/*
-*
-* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
-*
-* @param InstancePtr is a pointer to the XSpiPs instance.
-*
-* @return
-* - TRUE if option is set
-* - FALSE if option is not set
-*
-* @note C-Style signature:
-* u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr);
-*
-*****************************************************************************/
-#define XQspiPs_IsManualChipSelect(InstancePtr) \
- ((XQspiPs_GetOptions(InstancePtr) & \
- XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the slave idle count register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written, valid values are
-* 0-255.
-*
-* @return None
-*
-* @note C-Style signature:
-* void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr,
-* u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_SICR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_*
-* constants defined in xqspips_hw.h to interpret the bit-mask returned.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return An 8-bit value representing Slave Idle Count.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetSlaveIdle(InstancePtr) \
- XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_SICR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the transmit FIFO watermark register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written, valid values are 1-63.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr,
-* u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_TXWR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the transmit FIFO watermark register.
-* Valid values are in the range 1-63.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return A 6-bit value representing Tx Watermark level.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetTXWatermark(InstancePtr) \
- XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the receive FIFO watermark register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written, valid values are 1-63.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr,
-* u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_RXWR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the receive FIFO watermark register.
-* Valid values are in the range 1-63.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return A 6-bit value representing Rx Watermark level.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetRXWatermark(InstancePtr) \
- XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Enable the device and uninhibit master transactions.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_Enable(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_Enable(InstancePtr) \
- XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
- XQSPIPS_ER_ENABLE_MASK)
-
-/****************************************************************************/
-/**
-*
-* Disable the device.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_Disable(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_Disable(InstancePtr) \
- XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the Linear QSPI Configuration register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written to the Linear QSPI
-* configuration register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr,
-* u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the Linear QSPI Configuration register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return A 32-bit value representing the contents of the LQSPI Config
-* register.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetLqspiConfigReg(InstancePtr) \
- XQspiPs_In32((InstancePtr->Config.BaseAddress) + \
- XQSPIPS_LQSPI_CR_OFFSET)
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Initialization function, implemented in xqspips_sinit.c
- */
-XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
-
-/*
- * Functions implemented in xqspips.c
- */
-int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *Config,
- u32 EffectiveAddr);
-void XQspiPs_Reset(XQspiPs *InstancePtr);
-void XQspiPs_Abort(XQspiPs *InstancePtr);
-
-s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
- u32 ByteCount);
-s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
- u8 *RecvBufPtr, u32 ByteCount);
-int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
- u32 Address, unsigned ByteCount);
-
-int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
-
-void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
- XQspiPs_StatusHandler FuncPtr);
-void XQspiPs_InterruptHandler(void *InstancePtr);
-
-/*
- * Functions for selftest, in xqspips_selftest.c
- */
-int XQspiPs_SelfTest(XQspiPs *InstancePtr);
-
-/*
- * Functions for options, in xqspips_options.c
- */
-s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options);
-u32 XQspiPs_GetOptions(XQspiPs *InstancePtr);
-
-s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
-u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
-
-int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
- u8 DelayAfter, u8 DelayInit);
-void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
- u8 *DelayAfter, u8 *DelayInit);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/98/f01aea585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/98/f01aea585243001d18b399c1eb9b3628
deleted file mode 100644
index 8dae55e..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/98/f01aea585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,451 +0,0 @@
-;******************************************************************************
-; Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-; SPDX-License-Identifier: MIT
-;*****************************************************************************
-;****************************************************************************
-;**
-; @file boot.s
-;
-; This file contains the initial vector table for the Cortex A9 processor
-;
-;
-; MODIFICATION HISTORY:
-;
-; Ver Who Date Changes
-; ----- ------- -------- ---------------------------------------------------
-; 1.00a Initial version
-; 4.2 pkp 08/04/14 Removed PEEP board related code which contained
-; initialization of uart smc nor and sram
-; 5.0 pkp 16/12/14 Modified initialization code to enable scu after
-; MMU is enabled and removed incorrect initialization
-; of TLB lockdown register to fix CR#830580
-; 5.1 pkp 05/13/15 Changed the initialization order so to first invalidate
-; caches and TLB, enable MMU and caches, then enable SMP
-; bit in ACTLR. L2Cache invalidation and enabling of L2Cache
-; is done later.
-; 6.0 mus 08/04/16 Added code to detect zynq-7000 base silicon configuration and
-; attempt to enable dual core behavior on single cpu zynq-7000s devices
-; is prevented from corrupting system behavior.
-; 6.6 srm 10/25/17 Added timer configuration using XTime_StartTTCTimer API.
-; Now the TTC instance as specified by the user will be
-; started.
-;
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 4.1 hk 04/18/14 Add sleep function.
-* 6.0 asa 08/15/16 Updated the sleep/usleep signature. Fix for CR#956899.
-* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
-* implementation. Now sleep routines will use Axi Timer
-* or machine cycles as specified by the user.
-* 6.8 mus 10/04/18 FreeRTOS BSP always use default method for sleep
-* implementation, It does not have user configurable sleep
-* implementation support, that is why FreeRTOS tcl does not
-* export XSLEEP_TIMER_IS_DEFAULT_TIMER macro to
-* xparameters.h. Modified code to always use default timer
-* path for FreeRTOS BSP, based on the "FREERTOS_BSP" macro.
-* It fixes CR#1012363.
-* 7.5 dp 01/05/21 Updated COUNTS_PER_U/MSECOND, ITERS_PER_M/USEC macros to
-* round it off to nearest possible value so that delta error
-* in time calculations can be minimized.
-* 7.5 mus 04/21/21 Microblaze frequency can be changed run time. Sleep routines
-* needs to use updated frequency for delay calculation, else
-* sleep calls would result into incorrect behavior. Added
-* Xil_SetMBFrequency API to write updated frequency value to
-* MBFreq variable, and updated ITERS_PER_SEC macro to read
-* frequency value from MBFreq variable, instead of using XPARS.
-* Xil_SetMBFrequency must be called immediately after change
-* in Microblaze frequency run time, it would keep sleep
-* routines in sync with Microblaze frequency.
-* Added Xil_GetMBFrequency to read current Microbalze frequency.
-* It fixes CR#1094568.
-* 7.6 mus 08/23/21 Updated prototypes for functions which are not taking any
-* arguments with void keyword. This has been done to fix
-* compilation warnings with "-Wstrict-prototypes" flag.
-* It fixes CR#1108601
-*
-*
-*
-* @note
-*
-* This file may contain architecture-dependent code.
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "microblaze_sleep.h"
-#include "bspconfig.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#if defined (XSLEEP_TIMER_IS_AXI_TIMER)
-#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY)
-#define COUNTS_PER_MSECOND ((COUNTS_PER_SECOND + 500) / 1000)
-#define COUNTS_PER_USECOND ((COUNTS_PER_SECOND + 500000)/ 1000000)
-#warning "May wait for more than the specified delay"
-#elif defined (XSLEEP_TIMER_IS_DEFAULT_TIMER) || defined (FREERTOS_BSP)
-#define ITERS_PER_SEC (Xil_GetMBFrequency() / 4)
-#define ITERS_PER_MSEC ((ITERS_PER_SEC + 500) / 1000)
-#define ITERS_PER_USEC ((ITERS_PER_MSEC + 500) / 1000)
-#pragma message ("For the sleep routines, assembly instructions are used")
-#endif
-/***************** Variable Definitions *********************/
-#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER) || defined (FREERTOS_BSP)
-/**
- * This variable stores current value of Microblaze frequency.
- * It would be used by sleep routines to generate delay.
- */
-static u32 MBFreq = XPAR_CPU_CORE_CLOCK_FREQ_HZ;
-#endif
-
-/*****************************************************************************/
-
-#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER) || defined (FREERTOS_BSP)
-/*****************************************************************************/
-/**
-* @brief Sets variable which stores Microblaze frequency value
-* @param Val - Frequency value to be set
-* @return XST_SUCCESS - If frequency updated successfully
-* XST_INVALID_PARAM - If specified frequency value is not valid
-*
-* @note It must be called after runtime change in Microblaze frequency,
-* failing to do so would result in to incorrect behavior of sleep
-* routines
-*
-******************************************************************************/
-u32 Xil_SetMBFrequency(u32 Val)
-{
- if ( Val != 0) {
- MBFreq = Val;
- return XST_SUCCESS;
- }
- return XST_INVALID_PARAM;
-}
-
-/*****************************************************************************/
-/**
-* @brief Returns current Microblaze frequency value
-* @return MBFreq - Current Microblaze frequency value
-*
-******************************************************************************/
-u32 Xil_GetMBFrequency(void)
-{
- return MBFreq;
-}
-
-static void sleep_common(u32 n, u32 iters)
-{
- asm volatile (
- "1: \n\t"
- "addik %1, %1, -1 \n\t"
- "add r7, r0, %0 \n\t"
- "2: \n\t"
- "addik r7, r7, -1 \n\t"
- "bneid r7, 2b \n\t"
- "or r0, r0, r0 \n\t"
- "bneid %1, 1b \n\t"
- "or r0, r0, r0 \n\t"
- :
- : "r"(iters), "r"(n)
- );
-}
-#endif
-
-/*****************************************************************************/
-/**
-* @brief Provides delay for requested duration.
-* @param useconds- time in useconds.
-* @return 0
-*
-* @note Instruction cache should be enabled for this to work.
-*
-******************************************************************************/
-int usleep_MB(unsigned long useconds)
-{
-#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER) || defined (FREERTOS_BSP)
- sleep_common((u32)useconds, ITERS_PER_USEC);
-#elif defined (XSLEEP_TIMER_IS_AXI_TIMER)
- /* Start Axi timer */
- XTime_StartAxiTimer();
- Xil_SleepAxiTimer(useconds, COUNTS_PER_USECOND);
-#endif
-
- return 0;
-}
-
-/*****************************************************************************/
-/**
-* @brief Provides delay for requested duration.
-* @param seconds- time in useconds.
-* @return 0
-*
-* @note Instruction cache should be enabled for this to work.
-*
-******************************************************************************/
-unsigned sleep_MB(unsigned int seconds)
-{
-#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER) || defined (FREERTOS_BSP)
- sleep_common(seconds, ITERS_PER_SEC);
-#elif defined (XSLEEP_TIMER_IS_AXI_TIMER)
- /* Start Axi timer */
- XTime_StartAxiTimer();
- Xil_SleepAxiTimer(seconds, COUNTS_PER_SECOND);
-#endif
-
- return 0;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Provides delay for requested duration..
-*
-* @param MilliSeconds- Delay time in milliseconds.
-*
-* @return None.
-*
-* @note Instruction cache should be enabled for this to work.
-*
-******************************************************************************/
-void MB_Sleep(u32 MilliSeconds)
-{
-#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER) || defined (FREERTOS_BSP)
- sleep_common(MilliSeconds, ITERS_PER_MSEC);
-
-#elif defined (XSLEEP_TIMER_IS_AXI_TIMER)
- /* Start Axi timer */
- XTime_StartAxiTimer();
- Xil_SleepAxiTimer(MilliSeconds, COUNTS_PER_MSECOND);
-#endif
-}
-
-/*****************************************************************************/
-/**
- *
- * @brief Provides delay for requested duration by using Axi Timer.
- *
- * @param delay - delay time in seconds/milli seconds/micro seconds.
- * frequency - Number of counts per
- * second/milli second/micro second.
- *
- * @return None.
- *
- *
- ******************************************************************************/
-#if defined (XSLEEP_TIMER_IS_AXI_TIMER)
-static void Xil_SleepAxiTimer(u32 delay, u64 frequency)
-{
- u64 tEnd = 0U;
- u64 tCur = 0U;
- u32 TimeHighVal = 0U;
- u32 TimeLowVal1 = 0U;
- u32 TimeLowVal2 = 0U;
-
- TimeLowVal1 = Xil_In32((SLEEP_TIMER_BASEADDR) +
- (XSLEEP_TIMER_AXITIMER_TCR_OFFSET));
- tEnd = (u64)TimeLowVal1 + ((u64)(delay) * frequency);
- do
- {
- TimeLowVal2 = Xil_In32((SLEEP_TIMER_BASEADDR) +
- (XSLEEP_TIMER_AXITIMER_TCR_OFFSET));
- if (TimeLowVal2 < TimeLowVal1) {
- TimeHighVal++;
- }
- TimeLowVal1 = TimeLowVal2;
- tCur = (((u64) TimeHighVal) << 32U) | (u64)TimeLowVal2;
- }while (tCur < tEnd);
-}
-
-/*****************************************************************************/
-/**
- *
- * @brief This API starts the Axi Timer only when the timer is not enabled.
- *
- * @param None.
- *
- * @return None.
- *
- * @note Instruction cache should be enabled for this to work.
- *
- ******************************************************************************/
- static void XTime_StartAxiTimer(void)
- {
- u32 ControlStatusReg;
-
- /* Checking if the timer is enabled */
- if(Xil_In32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_AXITIMER_TCSR0_OFFSET) &&
- XSLEEP_TIMER_AXITIMER_CSR_ENABLE_TMR_MASK)
- {
- return;
- }
- /*
- * Read the current register contents such that only the necessary bits
- * of the register are modified in the following operations
- */
- ControlStatusReg = Xil_In32(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_AXITIMER_TCSR0_OFFSET);
- /*
- * Remove the reset condition such that the timer counter starts running
- * with the value loaded from the compare register
- */
- Xil_Out32((SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_AXITIMER_TCSR0_OFFSET),
- (ControlStatusReg | XSLEEP_TIMER_AXITIMER_CSR_ENABLE_TMR_MASK |
- XSLEEP_TIMER_AXITIMER_CSR_AUTO_RELOAD_MASK));
- }
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/99/80fb14595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/99/80fb14595243001d18b399c1eb9b3628
deleted file mode 100644
index a5e2aa4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/99/80fb14595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,334 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xparameters_ps.h
-*
-* @addtogroup r5_peripheral_definitions Cortex R5 peripheral definitions
-*
-* The xparameters_ps.h file contains the canonical definitions and constant
-* declarations for peripherals within hardblock, attached to the ARM Cortex R5
-* core. These definitions can be used by drivers or applications to access the
-* peripherals.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 5.00 pkp 02/29/14 Initial version
-* 6.0 mus 08/18/16 Defined ARMR5 flag
-* 7.2 pm 03/25/20 Add wakeup Interrupt Id for usbpsu controller
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00b kpc 03/07/13 First release
-* 5.4 pkp 09/11/15 Change the description for XOcm_Remap function
-*
-*
-******************************************************************************/
-
-
-/***************************** Include Files *********************************/
-#include "xil_misc_psreset_api.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for ddr reset.
-*
-*
-* @return N/A.
-*
-******************************************************************************/
-void XDdr_ResetHw(void)
-{
- u32 RegVal;
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert and deassert the ddr softreset bit */
- RegVal = Xil_In32(XDDRC_CTRL_BASEADDR);
- RegVal &= (u32)(~XDDRPS_CTRL_RESET_MASK);
- Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
- RegVal |= ((u32)XDDRPS_CTRL_RESET_MASK);
- Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
-
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for remapping the ocm memory region
-* to postbootrom state.
-*
-* @return N/A.
-*
-******************************************************************************/
-void XOcm_Remap(void)
-{
- u32 RegVal;
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Map the ocm region to postbootrom state */
- RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR);
- RegVal = (RegVal & (u32)(~XSLCR_OCM_CFG_HIADDR_MASK)) | (u32)XSLCR_OCM_CFG_RESETVAL;
- Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for SMC reset sequence
-*
-* @param BaseAddress of the interface
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSmc_ResetHw(u32 BaseAddress)
-{
- u32 RegVal;
-
- /* Clear the interuupts */
- RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET);
- RegVal = RegVal | (u32)XSMC_MEMC_CLR_CONFIG_MASK;
- Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal);
- /* Clear the idle counter registers */
- Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0U);
- Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0U);
- /* Update the ecc registers with reset values */
- Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET,
- XSMC_ECC_MEMCFG1_RESET_VAL);
- Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD1_OFFSET,
- XSMC_ECC_MEMCMD1_RESET_VAL);
- Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD2_OFFSET,
- XSMC_ECC_MEMCMD2_RESET_VAL);
-
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for updating the slcr mio registers
-* with reset values
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_MioWriteResetValues(void)
-{
- u32 i;
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Update all the MIO registers with reset values */
- for (i=0U; i<=1U;i++)
- {
- Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
- XSLCR_MIO_PIN_00_RESET_VAL);
- }
- for (; i<=8U;i++)
- {
- Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
- XSLCR_MIO_PIN_02_RESET_VAL);
- }
- for (; i<=53U ;i++)
- {
- Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
- XSLCR_MIO_PIN_00_RESET_VAL);
- }
-
-
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for updating the slcr pll registers
-* with reset values
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_PllWriteResetValues(void)
-{
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
-
- /* update the pll control registers with reset values */
- Xil_Out32(XSLCR_IO_PLL_CTRL_ADDR, XSLCR_IO_PLL_CTRL_RESET_VAL);
- Xil_Out32(XSLCR_ARM_PLL_CTRL_ADDR, XSLCR_ARM_PLL_CTRL_RESET_VAL);
- Xil_Out32(XSLCR_DDR_PLL_CTRL_ADDR, XSLCR_DDR_PLL_CTRL_RESET_VAL);
- /* update the pll config registers with reset values */
- Xil_Out32(XSLCR_IO_PLL_CFG_ADDR, XSLCR_IO_PLL_CFG_RESET_VAL);
- Xil_Out32(XSLCR_ARM_PLL_CFG_ADDR, XSLCR_ARM_PLL_CFG_RESET_VAL);
- Xil_Out32(XSLCR_DDR_PLL_CFG_ADDR, XSLCR_DDR_PLL_CFG_RESET_VAL);
- /* update the clock control registers with reset values */
- Xil_Out32(XSLCR_ARM_CLK_CTRL_ADDR, XSLCR_ARM_CLK_CTRL_RESET_VAL);
- Xil_Out32(XSLCR_DDR_CLK_CTRL_ADDR, XSLCR_DDR_CLK_CTRL_RESET_VAL);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for disabling the level shifters
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_DisableLevelShifters(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Disable the level shifters */
- RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_LVL_SHFTR_EN_MASK);
- Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal);
-
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for OCM software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_OcmReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_OCM_RST_CTRL_VAL);
- Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_OCM_RST_CTRL_VAL);
- Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for Ethernet software reset from
-* the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_EmacPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_GEM_RST_CTRL_VAL);
- Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_GEM_RST_CTRL_VAL);
- Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for USB software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_UsbPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_USB_RST_CTRL_VAL);
- Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_USB_RST_CTRL_VAL);
- Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for QSPI software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_QspiPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_QSPI_RST_CTRL_VAL);
- Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_QSPI_RST_CTRL_VAL);
- Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for SPI software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_SpiPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_SPI_RST_CTRL_VAL);
- Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_SPI_RST_CTRL_VAL);
- Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for i2c software reset from the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_I2cPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_I2C_RST_CTRL_VAL);
- Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_I2C_RST_CTRL_VAL);
- Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for UART software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_UartPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_UART_RST_CTRL_VAL);
- Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_UART_RST_CTRL_VAL);
- Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for CAN software reset from slcr
-* registers
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_CanPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_CAN_RST_CTRL_VAL);
- Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_CAN_RST_CTRL_VAL);
- Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for SMC software reset from the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_SmcPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_SMC_RST_CTRL_VAL);
- Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_SMC_RST_CTRL_VAL);
- Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for DMA controller software reset
-* from the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_DmaPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_DMAC_RST_CTRL_VAL);
- Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_DMAC_RST_CTRL_VAL);
- Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for Gpio AMBA software reset from
-* the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_GpioPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_GPIO_RST_CTRL_VAL);
- Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_GPIO_RST_CTRL_VAL);
- Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/99/b0cbf7575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/99/b0cbf7575243001d18b399c1eb9b3628
deleted file mode 100644
index 01d4fc3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/99/b0cbf7575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,112 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xgpiops_selftest.c
-* @addtogroup gpiops_v3_9
-* @{
-*
-* This file contains a diagnostic self-test function for the XGpioPs driver.
-*
-* Read xgpiops.h file for more information.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sv 01/18/10 First Release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
-* in safety mode and modified the code such as
-* Use of mixed mode arithmetic,Declared the pointer param
-* as Pointer to const,Casting operation to a pointer,
-* Literal value requires a U suffix.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
-* 7.0 aru 01/21/19 Modified the typedef of u32,u16,u8
-* 7.0 aru 02/06/19 Included stdint.h and stddef.h
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
-#define XBASIC_TYPES_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include
-#include
-
-/** @name Legacy types
- * Deprecated legacy types.
- * @{
- */
-typedef uint8_t Xuint8; /**< unsigned 8-bit */
-typedef char Xint8; /**< signed 8-bit */
-typedef uint16_t Xuint16; /**< unsigned 16-bit */
-typedef short Xint16; /**< signed 16-bit */
-typedef uint32_t Xuint32; /**< unsigned 32-bit */
-typedef long Xint32; /**< signed 32-bit */
-typedef float Xfloat32; /**< 32-bit floating point */
-typedef double Xfloat64; /**< 64-bit double precision FP */
-typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
-
-#if !defined __XUINT64__
-typedef struct
-{
- Xuint32 Upper;
- Xuint32 Lower;
-} Xuint64;
-#endif
-
-/** @name New types
- * New simple types.
- * @{
- */
-#ifndef __KERNEL__
-#ifndef XIL_TYPES_H
-typedef Xuint32 u32;
-typedef Xuint16 u16;
-typedef Xuint8 u8;
-#endif
-#else
-#include
-#endif
-
-#ifndef TRUE
-# define TRUE 1U
-#endif
-
-#ifndef FALSE
-# define FALSE 0U
-#endif
-
-#ifndef NULL
-#define NULL 0U
-#endif
-
-/*
- * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
- * Please use NULL, TRUE and FALSE
- */
-#define XNULL NULL
-#define XTRUE TRUE
-#define XFALSE FALSE
-
-/*
- * This file is deprecated and users
- * should use xil_types.h and xil_assert.h\n\r
- */
-#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
-#warning Please refer the Standalone BSP UG647 for further details
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9a/81192e545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9a/81192e545243001d18b399c1eb9b3628
deleted file mode 100644
index 9794da0..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9a/81192e545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,350 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xenv_standalone.h
-*
-* Defines common services specified by xenv.h.
-*
-* @note
-* This file is not intended to be included directly by driver code.
-* Instead, the generic xenv.h file is intended to be included by driver
-* code.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a wgr 02/28/07 Added cache handling macros.
-* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
-* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
-* used under Xilinx standalone BSP.
-* 1.00a xd 11/03/04 Improved support for doxygen.
-* 1.00a rmm 03/21/02 First release
-* 1.00a wgr 03/22/07 Converted to new coding style.
-* 1.00a rpm 06/29/07 Added udelay macro for standalone
-* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
-* to in MICROBLAZE section
-* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
-*
-*
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XENV_STANDALONE_H
-#define XENV_STANDALONE_H
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-/******************************************************************************
- *
- * Get the processor dependent includes
- *
- ******************************************************************************/
-
-#include
-
-#if defined __MICROBLAZE__
-# include "mb_interface.h"
-# include "xparameters.h" /* XPAR constants used below in MB section */
-
-#elif defined __PPC__
-# include "sleep.h"
-# include "xcache_l.h" /* also include xcache_l.h for caching macros */
-#endif
-
-/******************************************************************************
- *
- * MEMCPY / MEMSET related macros.
- *
- * The following are straight forward implementations of memset and memcpy.
- *
- * NOTE: memcpy may not work if source and target memory area are overlapping.
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
- *
- * Copies a non-overlapping block of memory.
- *
- * @param DestPtr
- * Destination address to copy data to.
- *
- * @param SrcPtr
- * Source address to copy data from.
- *
- * @param Bytes
- * Number of bytes to copy.
- *
- * @return None.
- *
- * @note
- * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
- *
- * @note
- * This implementation MAY BREAK work if source and target memory
- * area are overlapping.
- *
- *****************************************************************************/
-
-#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
- memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
-
-
-
-/*****************************************************************************/
-/**
- *
- * Fills an area of memory with constant data.
- *
- * @param DestPtr
- * Destination address to copy data to.
- *
- * @param Data
- * Value to set.
- *
- * @param Bytes
- * Number of bytes to copy.
- *
- * @return None.
- *
- * @note
- * The use of XENV_MEM_FILL is deprecated. Use memset() instead.
- *
- *****************************************************************************/
-
-#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
- memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
-
-
-
-/******************************************************************************
- *
- * TIME related macros
- *
- ******************************************************************************/
-
-/**
- * A structure that contains a time stamp used by other time stamp macros
- * defined below. This structure is processor dependent.
- */
-typedef s32 XENV_TIME_STAMP;
-
-/*****************************************************************************/
-/**
- *
- * Time is derived from the 64 bit PPC timebase register
- *
- * @param StampPtr is the storage for the retrieved time stamp.
- *
- * @return None.
- *
- * @note
- *
- * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_GET(StampPtr)
-
-/*****************************************************************************/
-/**
- *
- * This macro is not yet implemented and always returns 0.
- *
- * @param Stamp1Ptr is the first sampled time stamp.
- * @param Stamp2Ptr is the second sampled time stamp.
- *
- * @return 0
- *
- * @note
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
-
-/*****************************************************************************/
-/**
- *
- * This macro is not yet implemented and always returns 0.
- *
- * @param Stamp1Ptr is the first sampled time stamp.
- * @param Stamp2Ptr is the second sampled time stamp.
- *
- * @return 0
- *
- * @note
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
-
-/*****************************************************************************/
-/**
- * XENV_USLEEP(unsigned delay)
- *
- * Delay the specified number of microseconds. Not implemented without OS
- * support.
- *
- * @param delay
- * Number of microseconds to delay.
- *
- * @return None.
- *
- *****************************************************************************/
-
-#ifdef __PPC__
-#define XENV_USLEEP(delay) usleep(delay)
-#define udelay(delay) usleep(delay)
-#else
-#define XENV_USLEEP(delay)
-#define udelay(delay)
-#endif
-
-
-/******************************************************************************
- *
- * CACHE handling macros / mappings
- *
- ******************************************************************************/
-/******************************************************************************
- *
- * Processor independent macros
- *
- ******************************************************************************/
-
-#define XCACHE_ENABLE_CACHE() \
- { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
-
-#define XCACHE_DISABLE_CACHE() \
- { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
-
-
-/******************************************************************************
- *
- * MicroBlaze case
- *
- * NOTE: Currently the following macros will only work on systems that contain
- * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
- * system is built using a xparameters.h file.
- *
- ******************************************************************************/
-
-#if defined __MICROBLAZE__
-
-/* Check if MicroBlaze data cache was built into the core.
- */
-#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
-# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
-# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
-# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
-
-# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
- microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
-
-#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
-# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
-#else
-# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
-#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
-
-#else
-# define XCACHE_ENABLE_DCACHE()
-# define XCACHE_DISABLE_DCACHE()
-# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
-#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
-
-
-/* Check if MicroBlaze instruction cache was built into the core.
- */
-#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
-# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
-# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
-
-# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
-
-# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
- microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
-
-#else
-# define XCACHE_ENABLE_ICACHE()
-# define XCACHE_DISABLE_ICACHE()
-#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
-
-
-/******************************************************************************
- *
- * PowerPC case
- *
- * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
- * specific memory region (0x80000001). Each bit (0-30) in the regions
- * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
- * range.
- *
- * regions --> cached address range
- * ------------|--------------------------------------------------
- * 0x80000000 | [0, 0x7FFFFFF]
- * 0x00000001 | [0xF8000000, 0xFFFFFFFF]
- * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
- *
- ******************************************************************************/
-
-#elif defined __PPC__
-
-#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
-#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
-#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
-#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
-
-#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
- XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
-
-#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
-
-#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
-
-
-/******************************************************************************
- *
- * Unknown processor / architecture
- *
- ******************************************************************************/
-
-#else
-/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* #ifndef XENV_STANDALONE_H */
-
- /**
- *@endcond
- */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9a/91c40c565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9a/91c40c565243001d18b399c1eb9b3628
deleted file mode 100644
index d2cc146..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9a/91c40c565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,104 +0,0 @@
-##############################################################################
-# Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-#
-# SPDX-License-Identifier: MIT
-#
-##############################################################################
-DRIVER_LIB_VERSION = v1.0
-
-include config.make
-
-AS=$(ASSEMBLER)
-COMPILER=$(COMPILER)
-ARCHIVER=$(ARCHIVER)
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-INCLUDEFILES=*.h
-
-SRCFILES:=$(wildcard *.c)
-
-ASSEMBLY_SRCFILES:=$(wildcard *.S)
-
-COBJS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(wildcard *.c))))
-AOBJS1 = $(RELEASEDIR)/asm_vectors.o
-AOBJS2 = $(RELEASEDIR)/boot.o
-AOBJS3 = $(RELEASEDIR)/xil-crt0.o
-AOBJS4 = $(RELEASEDIR)/cpu_init.o
-OBJS = $(COBJS) $(AOBJS1) $(AOBJS2) $(AOBJS3) $(AOBJS4)
-
-ASOURCES1 = asm_vectors.S
-ASOURCES2 = boot.S
-ASOURCES3 = xil-crt0.S
-ASOURCES4 = cpu_init.S
-
-OBJECTS = $(OBJS)
-
-libs: standalone_libs
-
-standalone_libs: ${OBJECTS}
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-ASSEMBLY_DEPFILES := $(ASSEMBLY_SRCFILES:%.S=$(RELEASEDIR)%.d)
-
-include $(wildcard $(ASSEMBLY_DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(AOBJS1): $(ASOURCES1)
-ifeq ($(findstring asm_vectors.S,$(wildcard *.S)),asm_vectors.S)
- ${COMPILER} $(INCLUDES) --target=arm-arm-none-eabi -E -o asm_vectors_post.s asm_vectors.S
-endif
- ${AS} --cpu=Cortex-R5 -o $*.o asm_vectors_post.s --depend=$*.d
-
-$(AOBJS2): $(ASOURCES2)
-ifeq ($(findstring boot.S,$(wildcard *.S)),boot.S)
- ${COMPILER} $(INCLUDES) --target=arm-arm-none-eabi -E -o boot_post.s boot.S
-endif
- ${AS} --cpu=Cortex-R5 -o $*.o boot_post.s --depend=$*.d
-
-$(AOBJS3): $(ASOURCES3)
-ifeq ($(findstring xil-crt0.S,$(wildcard *.S)),xil-crt0.S)
- ${COMPILER} $(INCLUDES) --target=arm-arm-none-eabi -E -o xil-crt0_post.s xil-crt0.S
-endif
- ${AS} --cpu=Cortex-R5 -o $*.o xil-crt0_post.s --depend=$*.d
-
-$(AOBJS4): $(ASOURCES4)
-ifeq ($(findstring cpu_init.S,$(wildcard *.S)),cpu_init.S)
- ${COMPILER} $(INCLUDES) --target=arm-arm-none-eabi -E -o cpu_init_post.s cpu_init.S
-endif
- ${AS} --cpu=Cortex-R5 -o $*.o cpu_init_post.s --depend=$*.d
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $<
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h)) $(addprefix $(INCLUDEDIR), $(subst includes_ps/,,$(wildcard includes_ps/*.h)))
-
-
-
-$(INCLUDEDIR)%.h: includes_ps/%.h
- $(CP) $< $@
-
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf $(DEPFILES)
- rm -rf $(ASSEMBLY_DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9c/00dc95545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9c/00dc95545243001d18b399c1eb9b3628
deleted file mode 100644
index d039278..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9c/00dc95545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,267 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xdmaps_hw.h
-* @addtogroup dmaps_v2_8
-* @{
-*
-* This header file contains the hardware interface of an XDmaPs device.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ----------------------------------------------
-* 1.00a hbm 08/18/10 First Release
-* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
-* the maximum number of channels.
-* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
-* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
-* 1.02a sg 05/16/12 Made changes for doxygen
-* 1.06a kpc 07/10/13 Added function prototype
-*
-*
-******************************************************************************/
-
-#ifndef XDMAPS_HW_H /* prevent circular inclusions */
-#define XDMAPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets for the DMAC.
- * @{
- */
-
-#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */
-#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */
-#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */
-#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */
-#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register
- */
-#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */
-#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager
- * Register
- */
-#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register
- */
-#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */
-
-#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */
-/*
- * The offset for the rest of the FTC registers is calculated as
- * FTC0 + dev_chan_num * 4
- */
-#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4)
-
-#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */
-/*
- * The offset for the rest of the CS registers is calculated as
- * CS0 + * dev_chan_num * 0x08
- */
-#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8)
-
-#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA
- * Channel 0
- */
-/*
- * The offset for the rest of the CPC registers is calculated as
- * CPC0 + dev_chan_num * 0x08
- */
-#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8)
-
-#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA
- * Channel 0
- */
-/* The offset for the rest of the SA registers is calculated as
- * SA_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for
- * DMA Channel 0
- */
-/* The offset for the rest of the DA registers is calculated as
- * DA_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for
- * DMA Channel 0
- */
-/*
- * The offset for the rest of the CC registers is calculated as
- * CC_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */
-/*
- * The offset for the rest of the LC0 registers is calculated as
- * LC_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20)
-#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */
-/*
- * The offset for the rest of the LC1 registers is calculated as
- * LC_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */
-#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */
-#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */
-#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */
-
-#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */
-#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */
-#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */
-#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */
-#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */
-#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */
-
-#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification
- * Register 0
- */
-#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification
- * Register 1
- */
-#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification
- * Register 2
- */
-#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification
- * Register 3
- */
-#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification
- * Register 0
- */
-#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification
- * Register 1
- */
-#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification
- * Register 2
- */
-#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification
- * Register 3
- */
-
-/*
- * Some useful register masks
- */
-#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */
-#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */
-
-#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */
-
-#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask,
- * llast 3 bits of CS register
- */
-
-#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */
-
-
-/*
- * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register.
- * @b1: Instruction byte 1
- * @b0: Instruction byte 0
- * @ch: Channel number
- * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel
- */
-#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \
- (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1)))
-
-/* @} */
-
-/** @name Control Register
- *
- * The Control register (CR) controls the major functions of the device.
- *
- * Control Register Bit Definition
- */
-
-/* @}*/
-
-
-#define XDMAPS_CHANNELS_PER_DEV 8
-
-
-/** @name Mode Register
- *
- * The mode register (MR) defines the mode of transfer as well as the data
- * format. If this register is modified during transmission or reception,
- * data validity cannot be guaranteed.
- *
- * Mode Register Bit Definition
- * @{
- */
-
-/* @} */
-
-
-/** @name Interrupt Registers
- *
- * Interrupt control logic uses the interrupt enable register (IER) and the
- * interrupt disable register (IDR) to set the value of the bits in the
- * interrupt mask register (IMR). The IMR determines whether to pass an
- * interrupt to the interrupt status register (ISR).
- * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
- * interrupt. IMR and ISR are read only, and IER and IDR are write only.
- * Reading either IER or IDR returns 0x00.
- *
- * All four registers have the same bit definitions.
- *
- * @{
- */
-
-/* @} */
-#define XDMAPS_INTCLR_ALL_MASK 0xFF
-
-#define XDmaPs_ReadReg(BaseAddress, RegOffset) \
- Xil_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write a DMAC register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the base address of the device.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note
-* C-Style signature:
-* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u32 RegisterValue)
-******************************************************************************/
-#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes *****************************/
-/*
- * Perform reset operation to the dmaps interface
- */
-void XDmaPs_ResetHw(u32 BaseAddr);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9c/22d268575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9c/22d268575243001d18b399c1eb9b3628
deleted file mode 100644
index e567699..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9c/22d268575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,377 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xdevcfg.h
-* @addtogroup devcfg_v3_7
-* @{
-* @details
-*
-* The is the main header file for the Device Configuration Interface of the Zynq
-* device. The device configuration interface has three main functionality.
-* 1. AXI-PCAP
-* 2. Security Policy
-* 3. XADC
-* This current version of the driver supports only the AXI-PCAP and Security
-* Policy blocks. There is a separate driver for XADC.
-*
-* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream.
-* DMA embedded in the AXI PCAP provides the master interface to
-* the Device configuration block for any DMA transfers. The data transfer can
-* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip
-* RAM/DDR/peripheral memory).
-*
-* The current driver only supports the downloading the FPGA bitstream and
-* readback of the decrypted image (sort of loopback).
-* The driver does not know what information needs to be written to the FPGA to
-* readback FPGA configuration register or memory data. The application above the
-* driver should take care of creating the data that needs to be downloaded to
-* the FPGA so that the bitstream can be readback.
-* This driver also does not support the reading of the internal registers of the
-* PCAP. The driver has no knowledge of the PCAP internals.
-*
-* Initialization and Configuration
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate with the Device Configuration device.
-*
-* XDcfg_CfgInitialize() API is used to initialize the Device Configuration
-* Interface. The user needs to first call the XDcfg_LookupConfig() API which
-* returns the Configuration structure pointer which is passed as a parameter to
-* the XDcfg_CfgInitialize() API.
-*
-* Interrupts
-* The Driver implements an interrupt handler to support the interrupts provided
-* by this interface.
-*
-* Threads
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* Asserts
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* Building the driver
-*
-* The XDcfg driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
-* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
-* APIs is words (32 bit) and not bytes.
-* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
-* to add information that 2 LSBs of the Source/Destination
-* address when equal to 2�b01 indicate the last DMA command
-* of an overall transfer.
-* Destination Address passed to this API for secure transfers
-* instead of using 0xFFFFFFFF for CR 662197. This issue was
-* resulting in the failure of secure transfers of
-* non-bitstream images.
-* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
-* set the mask instead of oring it with the
-* value read from the interrupt status register
-* Added defines for the PS Version bits,
-* removed the FIFO Flush bits from the
-* Miscellaneous Control Reg.
-* Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
-* and XDcfg_SelectPcapInterface APIs for CR 643295
-* The user has to call the XDcfg_SelectIcapInterface API
-* for the PL reconfiguration using AXI HwIcap.
-* Updated the XDcfg_Transfer API to clear the
-* QUARTER_PCAP_RATE_EN bit in the control register for
-* non secure writes for CR 675543.
-* 2.02a nm 01/31/13 Fixed CR# 679335.
-* Added Setting and Clearing the internal PCAP loopback.
-* Removed code for enabling/disabling AES engine as BootROM
-* locks down this setting.
-* Fixed CR# 681976.
-* Skip Checking the PCFG_INIT in case of non-secure DMA
-* loopback.
-* Fixed CR# 699558.
-* XDcfg_Transfer fails to transfer data in loopback mode.
-* Fixed CR# 701348.
-* Peripheral test fails with Running
-* DcfgSelfTestExample() in SECURE bootmode.
-* 2.03a nm 04/19/13 Fixed CR# 703728.
-* Updated the register definitions as per the latest TRM
-* version UG585 (v1.4) November 16, 2012.
-* 3.0 adk 10/12/13 Updated as per the New Tcl API's
-* 3.0 kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
-* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
-* updated driver code with != instead of ==,
-* while checking for Interrupt Status with DMA and
-* PCAP Done Mask
-* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
-* XDCFG_INT_STS_OFFSET) &
-* XDCFG_IXR_D_P_DONE_MASK) !=
-* XDCFG_IXR_D_P_DONE_MASK);
-* A new example has been added to read back the
-* configuration registers from the PL region.
-* xdevcfg_reg_readback_example.c
-* 3.3 sk 04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/10/17 Modified filename tag in interrupt and polled examples
-* to include them in doxygen examples.
-* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros
-* definitions of devcfg in xparameters.h
-* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
-*
-*
-******************************************************************************/
-#ifndef XDCFG_H /* prevent circular inclusions */
-#define XDCFG_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xdevcfg_hw.h"
-#include "xstatus.h"
-#include "xil_assert.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/* Types of PCAP transfers */
-
-#define XDCFG_NON_SECURE_PCAP_WRITE 1
-#define XDCFG_SECURE_PCAP_WRITE 2
-#define XDCFG_PCAP_READBACK 3
-#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4
-#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5
-
-
-/**************************** Type Definitions *******************************/
-/**
-* The handler data type allows the user to define a callback function to
-* respond to interrupt events in the system. This function is executed
-* in interrupt context, so amount of processing should be minimized.
-*
-* @param CallBackRef is the callback reference passed in by the upper
-* layer when setting the callback functions, and passed back to
-* the upper layer when the callback is invoked. Its type is
-* unimportant to the driver component, so it is a void pointer.
-* @param Status is the Interrupt status of the XDcfg device.
-*/
-typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddr; /**< Base address of the device */
-} XDcfg_Config;
-
-/**
- * The XDcfg driver instance data.
- */
-typedef struct {
- XDcfg_Config Config; /**< Hardware Configuration */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStarted; /**< Device Configuration Interface
- * is running
- */
- XDcfg_IntrHandler StatusHandler; /* Event handler function */
- void *CallBackRef; /* Callback reference for event handler */
-} XDcfg;
-
-/****************************************************************************/
-/**
-*
-* Unlock the Device Config Interface block.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_Unlock(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_Unlock(InstancePtr) \
- XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \
- XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
-
-
-
-/****************************************************************************/
-/**
-*
-* Get the version number of the PS from the Miscellaneous Control Register.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return Version of the PS.
-*
-* @note C-style signature:
-* void XDcfg_GetPsVersion(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_GetPsVersion(InstancePtr) \
- ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
- XDCFG_MCTRL_OFFSET)) & \
- XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \
- XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
-
-
-
-/****************************************************************************/
-/**
-*
-* Read the multiboot config register value.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_ReadMultiBootConfig(InstancePtr) \
- XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
- XDCFG_MULTIBOOT_ADDR_OFFSET)
-
-
-/****************************************************************************/
-/**
-*
-* Selects ICAP interface for reconfiguration after the initial configuration
-* of the PL.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_SelectIcapInterface(InstancePtr) \
- XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
- ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
- & ( ~XDCFG_CTRL_PCAP_PR_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Selects PCAP interface for reconfiguration after the initial configuration
-* of the PL.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_SelectPcapInterface(InstancePtr) \
- XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
- ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
- | XDCFG_CTRL_PCAP_PR_MASK))
-
-
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Lookup configuration in xdevcfg_sinit.c.
- */
-XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId);
-
-/*
- * Selftest function in xdevcfg_selftest.c
- */
-int XDcfg_SelfTest(XDcfg *InstancePtr);
-
-/*
- * Interface functions in xdevcfg.c
- */
-int XDcfg_CfgInitialize(XDcfg *InstancePtr,
- XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
-
-void XDcfg_EnablePCAP(XDcfg *InstancePtr);
-
-void XDcfg_DisablePCAP(XDcfg *InstancePtr);
-
-void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask);
-
-void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask);
-
-u32 XDcfg_GetControlRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetLockRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask);
-
-u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr);
-
-u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr);
-
-void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
- u32 SrcWordLength, u32 DestWordLength);
-
-u32 XDcfg_Transfer(XDcfg *InstancePtr,
- void *SourcePtr, u32 SrcWordLength,
- void *DestPtr, u32 DestWordLength,
- u32 TransferType);
-
-/*
- * Interrupt related function prototypes implemented in xdevcfg_intr.c
- */
-void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask);
-
-void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask);
-
-u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr);
-
-u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr);
-
-void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask);
-
-void XDcfg_InterruptHandler(XDcfg *InstancePtr);
-
-void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
- void *CallBackRef);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9c/6051d0585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9c/6051d0585243001d18b399c1eb9b3628
deleted file mode 100644
index 42baaee..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9c/6051d0585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,13 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#include "xil_types.h"
-/* Stuv for exit() sys-call */
-__weak void _sys_exit(s32 rc)
-{
- while(1) {
- ;
- }
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9d/002b68565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9d/002b68565243001d18b399c1eb9b3628
deleted file mode 100644
index 7e29233..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9d/002b68565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,165 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_testmem.h
-* @addtogroup common_test_utils Test Utilities for Memory and Caches
-*
-* - Cache test: xil_testcache.h contains utility functions to test cache.
-*
-* - I/O test: The Xil_testio.h file contains endian related memory IO functions. A
-* subset of the memory tests can be selected or all of the tests can be run in order.
-* If there is an error detected by a subtest, the test stops and the failure code is
-* returned. Further tests are not run even if all of the tests are selected.
-*
-* - Memory test: The xil_testmem.h file contains utility functions to test memory.
-* A subset of the memory tests can be selected or all of the tests can be run
-* in order. If there is an error detected by a subtest, the test stops and the
-* failure code is returned. Further tests are not run even if all of the tests are selected.
-*
-*
-* Following list describes the supported memory tests:
-*
-* - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
-*
-* - XIL_TESTMEM_INCREMENT: This test
-* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
-* test value for memory.
-*
-* - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
-* uses a walking '1' as the test value for memory.
-* @code
-* location 1 = 0x00000001
-* location 2 = 0x00000002
-* ...
-* @endcode
-*
-* - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
-* This test uses the inverse value of the walking ones test
-* as the test value for memory.
-* @code
-* location 1 = 0xFFFFFFFE
-* location 2 = 0xFFFFFFFD
-* ...
-*@endcode
-*
-* - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
-* This test uses the inverse of the address of the location under test
-* as the test value for memory.
-*
-* - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
-* This test uses the provided patters as the test value for memory.
-* If zero is provided as the pattern the test uses '0xDEADBEEF".
-*
-* @warning
-* The tests are DESTRUCTIVE. Run before any initialized memory spaces
-* have been set up.
-* The address provided to the memory tests is not checked for
-* validity except for the NULL case. It is possible to provide a code-space
-* pointer for this test to start with and ultimately destroy executable code
-* causing random failures.
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 08/25/09 First release
-* 7.5 mus 03/10/21 Added new set of Xil_TestMem32, Xil_TestMem16 and
-* Xil_TestMem8 APIs to support memory test for memory
-* regions mapped at extended addresses
-* (addresses > 4 GB). These new set of APIs would be
-* compiled only for 32 bit Microblaze processor, if
-* XPAR_MICROBLAZE_ADDR_SIZE is greater than 32.
-* It fixes CR#1089129.
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_TESTMEM_H /* prevent circular inclusions */
-#define XIL_TESTMEM_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-/* xutil_memtest defines */
-
-#define XIL_TESTMEM_INIT_VALUE 1U
-
-/** @name Memory subtests
- * @{
- */
-/**
- * See the detailed description of the subtests in the file description.
- */
-#define XIL_TESTMEM_ALLMEMTESTS 0x00U
-#define XIL_TESTMEM_INCREMENT 0x01U
-#define XIL_TESTMEM_WALKONES 0x02U
-#define XIL_TESTMEM_WALKZEROS 0x03U
-#define XIL_TESTMEM_INVERSEADDR 0x04U
-#define XIL_TESTMEM_FIXEDPATTERN 0x05U
-#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN
-/* @} */
-
-#if !defined(__aarch64__) && !defined(__arch64__)
-#define NUM_OF_BITS_IN_BYTE 8U
-#define NUM_OF_BYTES_IN_HW 2U
-#define NUM_OF_BITS_IN_HW 16U
-#define NUM_OF_BYTES_IN_WORD 4U
-#define NUM_OF_BITS_IN_WORD 32U
-#endif
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**
- *@endcond
- */
-
-/************************** Function Prototypes ******************************/
-
-/* xutil_testmem prototypes */
-#if defined(__MICROBLAZE__) && !defined(__arch64__) && (XPAR_MICROBLAZE_ADDR_SIZE > 32)
-extern s32 Xil_TestMem32(u32 AddrLow, u32 AddrHigh, u32 Words, u32 Pattern, u8 Subtest);
-extern s32 Xil_TestMem16(u32 AddrLow, u32 AddrHigh, u32 Words, u16 Pattern, u8 Subtest);
-extern s32 Xil_TestMem8(u32 AddrLow, u32 AddrHigh, u32 Words, u8 Pattern, u8 Subtest);
-#else
-extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
-extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
-extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_test_utils".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9d/31c45c575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9d/31c45c575243001d18b399c1eb9b3628
deleted file mode 100644
index 266fd7f..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9d/31c45c575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,395 +0,0 @@
-/*----------------------------------------------------------------------------/
-/ FatFs - Generic FAT Filesystem module R0.13b /
-/-----------------------------------------------------------------------------/
-/
-/ Copyright (C) 2018, ChaN, all right reserved.
-/
-/ FatFs module is an open source software. Redistribution and use of FatFs in
-/ source and binary forms, with or without modification, are permitted provided
-/ that the following condition is met:
-
-/ 1. Redistributions of source code must retain the above copyright notice,
-/ this condition and the following disclaimer.
-/
-/ This software is provided by the copyright holder and contributors "AS IS"
-/ and any warranties related to this software are DISCLAIMED.
-/ The copyright owner or contributors be NOT LIABLE for any damages caused
-/ by use of this software.
-/
-/----------------------------------------------------------------------------*/
-
-
-#ifndef FF_DEFINED
-#define FF_DEFINED 63463 /* Revision ID */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xil_types.h"
-#include "integer.h" /* Basic integer types */
-#include "ffconf.h" /* FatFs configuration options */
-
-#if FF_DEFINED != FFCONF_DEF
-#error Wrong configuration file (ffconf.h).
-#endif
-
-
-
-/* Definitions of volume management */
-
-#if FF_MULTI_PARTITION /* Multiple partition configuration */
-typedef struct {
- BYTE pd; /* Physical drive number */
- BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */
-} PARTITION;
-extern PARTITION VolToPart[]; /* Volume - Partition resolution table */
-#endif
-
-#if FF_STR_VOLUME_ID
-#ifndef FF_VOLUME_STRS
-extern const char* VolumeStr[FF_VOLUMES]; /* User defied volume ID */
-#endif
-#endif
-
-
-
-/* Type of path name strings on FatFs API */
-
-#ifndef _INC_TCHAR
-#define _INC_TCHAR
-
-#if FF_USE_LFN && FF_LFN_UNICODE == 1 /* Unicode in UTF-16 encoding */
-typedef WCHAR TCHAR;
-#define _T(x) L ## x
-#define _TEXT(x) L ## x
-#elif FF_USE_LFN && FF_LFN_UNICODE == 2 /* Unicode in UTF-8 encoding */
-typedef char TCHAR;
-#define _T(x) u8 ## x
-#define _TEXT(x) u8 ## x
-#elif FF_USE_LFN && FF_LFN_UNICODE == 3 /* Unicode in UTF-32 encoding */
-typedef DWORD TCHAR;
-#define _T(x) U ## x
-#define _TEXT(x) U ## x
-#elif FF_USE_LFN && (FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3)
-#error Wrong FF_LFN_UNICODE setting
-#else /* ANSI/OEM code in SBCS/DBCS */
-typedef char TCHAR;
-#define _T(x) x
-#define _TEXT(x) x
-#endif
-
-#endif
-
-
-
-/* Type of file size variables */
-
-#if FF_FS_EXFAT
-typedef QWORD FSIZE_t;
-#else
-typedef DWORD FSIZE_t;
-#endif
-
-
-
-/* Filesystem object structure (FATFS) */
-
-typedef struct {
- BYTE fs_type; /* Filesystem type (0:N/A) */
- BYTE pdrv; /* Physical drive number */
- BYTE n_fats; /* Number of FATs (1 or 2) */
- BYTE wflag; /* win[] flag (b0:dirty) */
- BYTE fsi_flag; /* FSINFO flags (b7:disabled, b0:dirty) */
- WORD id; /* Volume mount ID */
- WORD n_rootdir; /* Number of root directory entries (FAT12/16) */
- WORD csize; /* Cluster size [sectors] */
-#if FF_MAX_SS != FF_MIN_SS
- WORD ssize; /* Sector size (512, 1024, 2048 or 4096) */
-#endif
-#if FF_USE_LFN
- WCHAR* lfnbuf; /* LFN working buffer */
-#endif
-#if FF_FS_EXFAT
- BYTE* dirbuf; /* Directory entry block scratchpad buffer for exFAT */
-#endif
-#if FF_FS_REENTRANT
- FF_SYNC_t sobj; /* Identifier of sync object */
-#endif
-#if !FF_FS_READONLY
- DWORD last_clst; /* Last allocated cluster */
- DWORD free_clst; /* Number of free clusters */
-#endif
-#if FF_FS_RPATH
- DWORD cdir; /* Current directory start cluster (0:root) */
-#if FF_FS_EXFAT
- DWORD cdc_scl; /* Containing directory start cluster (invalid when cdir is 0) */
- DWORD cdc_size; /* b31-b8:Size of containing directory, b7-b0: Chain status */
- DWORD cdc_ofs; /* Offset in the containing directory (invalid when cdir is 0) */
-#endif
-#endif
- DWORD n_fatent; /* Number of FAT entries (number of clusters + 2) */
- DWORD fsize; /* Size of an FAT [sectors] */
- DWORD volbase; /* Volume base sector */
- DWORD fatbase; /* FAT base sector */
- DWORD dirbase; /* Root directory base sector/cluster */
- DWORD database; /* Data base sector */
- DWORD winsect; /* Current sector appearing in the win[] */
-#ifdef __ICCARM__
-#pragma data_alignment = 32
- BYTE win[FF_MAX_SS];
-#else
-#ifdef __aarch64__
- BYTE win[FF_MAX_SS] __attribute__ ((aligned(64))); /* Disk access window for Directory, FAT (and file data at tiny cfg) */
-#else
- BYTE win[FF_MAX_SS] __attribute__ ((aligned(32))); /* Disk access window for Directory, FAT (and file data at tiny cfg) */
-#endif
-#endif
-} FATFS;
-
-
-
-/* Object ID and allocation information (FFOBJID) */
-
-typedef struct {
- FATFS* fs; /* Pointer to the hosting volume of this object */
- WORD id; /* Hosting volume mount ID */
- BYTE attr; /* Object attribute */
- BYTE stat; /* Object chain status (b1-0: =0:not contiguous, =2:contiguous, =3:flagmented in this session, b2:sub-directory stretched) */
- DWORD sclust; /* Object data start cluster (0:no cluster or root directory) */
- FSIZE_t objsize; /* Object size (valid when sclust != 0) */
-#if FF_FS_EXFAT
- DWORD n_cont; /* Size of first fragment - 1 (valid when stat == 3) */
- DWORD n_frag; /* Size of last fragment needs to be written to FAT (valid when not zero) */
- DWORD c_scl; /* Containing directory start cluster (valid when sclust != 0) */
- DWORD c_size; /* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */
- DWORD c_ofs; /* Offset in the containing directory (valid when file object and sclust != 0) */
-#endif
-#if FF_FS_LOCK
- UINT lockid; /* File lock ID origin from 1 (index of file semaphore table Files[]) */
-#endif
-} FFOBJID;
-
-
-
-/* File object structure (FIL) */
-
-typedef struct {
- FFOBJID obj; /* Object identifier (must be the 1st member to detect invalid object pointer) */
- BYTE flag; /* File status flags */
- BYTE err; /* Abort flag (error code) */
- FSIZE_t fptr; /* File read/write pointer (Zeroed on file open) */
- DWORD clust; /* Current cluster of fpter (invalid when fptr is 0) */
- DWORD sect; /* Sector number appearing in buf[] (0:invalid) */
-#if !FF_FS_READONLY
- DWORD dir_sect; /* Sector number containing the directory entry (not used at exFAT) */
- BYTE* dir_ptr; /* Pointer to the directory entry in the win[] (not used at exFAT) */
-#endif
-#if FF_USE_FASTSEEK
- DWORD* cltbl; /* Pointer to the cluster link map table (nulled on open, set by application) */
-#endif
-#if !FF_FS_TINY
-#ifdef __ICCARM__
-#pragma data_alignment = 32
- BYTE buf[FF_MAX_SS]; /* File private data read/write window */
-#else
-#ifdef __aarch64__
- BYTE buf[FF_MAX_SS] __attribute__ ((aligned(64))); /* File private data read/write window */
-#else
- BYTE buf[FF_MAX_SS] __attribute__ ((aligned(32))); /* File private data read/write window */
-#endif
-#endif
-#endif
-} FIL;
-
-
-
-/* Directory object structure (DIR) */
-
-typedef struct {
- FFOBJID obj; /* Object identifier */
- DWORD dptr; /* Current read/write offset */
- DWORD clust; /* Current cluster */
- DWORD sect; /* Current sector (0:Read operation has terminated) */
- BYTE* dir; /* Pointer to the directory item in the win[] */
- BYTE fn[12]; /* SFN (in/out) {body[8],ext[3],status[1]} */
-#if FF_USE_LFN
- DWORD blk_ofs; /* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */
-#endif
-#if FF_USE_FIND
- const TCHAR* pat; /* Pointer to the name matching pattern */
-#endif
-} DIR;
-
-
-
-/* File information structure (FILINFO) */
-
-typedef struct {
- FSIZE_t fsize; /* File size */
- WORD fdate; /* Modified date */
- WORD ftime; /* Modified time */
- BYTE fattrib; /* File attribute */
-#if FF_USE_LFN
- TCHAR altname[FF_SFN_BUF + 1];/* Altenative file name */
- TCHAR fname[FF_LFN_BUF + 1]; /* Primary file name */
-#else
- TCHAR fname[12 + 1]; /* File name */
-#endif
-} FILINFO;
-
-
-
-/* File function return code (FRESULT) */
-
-typedef enum {
- FR_OK = 0, /* (0) Succeeded */
- FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */
- FR_INT_ERR, /* (2) Assertion failed */
- FR_NOT_READY, /* (3) The physical drive cannot work */
- FR_NO_FILE, /* (4) Could not find the file */
- FR_NO_PATH, /* (5) Could not find the path */
- FR_INVALID_NAME, /* (6) The path name format is invalid */
- FR_DENIED, /* (7) Access denied due to prohibited access or directory full */
- FR_EXIST, /* (8) Access denied due to prohibited access */
- FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
- FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
- FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
- FR_NOT_ENABLED, /* (12) The volume has no work area */
- FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */
- FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any problem */
- FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
- FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */
- FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
- FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > FF_FS_LOCK */
- FR_INVALID_PARAMETER /* (19) Given parameter is invalid */
-} FRESULT;
-
-
-
-/*--------------------------------------------------------------*/
-/* FatFs module application interface */
-
-FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */
-FRESULT f_close (FIL* fp); /* Close an open file object */
-FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from the file */
-FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to the file */
-FRESULT f_lseek (FIL* fp, FSIZE_t ofs); /* Move file pointer of the file object */
-FRESULT f_truncate (FIL* fp); /* Truncate the file */
-FRESULT f_sync (FIL* fp); /* Flush cached data of the writing file */
-FRESULT f_opendir (DIR* dp, const TCHAR* path); /* Open a directory */
-FRESULT f_closedir (DIR* dp); /* Close an open directory */
-FRESULT f_readdir (DIR* dp, FILINFO* fno); /* Read a directory item */
-FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern); /* Find first file */
-FRESULT f_findnext (DIR* dp, FILINFO* fno); /* Find next file */
-FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */
-FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */
-FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */
-FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */
-FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask); /* Change attribute of a file/dir */
-FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change timestamp of a file/dir */
-FRESULT f_chdir (const TCHAR* path); /* Change current directory */
-FRESULT f_chdrive (const TCHAR* path); /* Change current drive */
-FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */
-FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */
-FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn); /* Get volume label */
-FRESULT f_setlabel (const TCHAR* label); /* Set volume label */
-FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */
-FRESULT f_expand (FIL* fp, FSIZE_t szf, BYTE opt); /* Allocate a contiguous block to the file */
-FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */
-FRESULT f_mkfs (const TCHAR* path, BYTE opt, DWORD au, void* work, UINT len); /* Create a FAT volume */
-FRESULT f_fdisk (BYTE pdrv, const DWORD* szt, void* work); /* Divide a physical drive into some partitions */
-FRESULT f_setcp (WORD cp); /* Set current code page */
-int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */
-int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */
-int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */
-TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */
-
-#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize))
-#define f_error(fp) ((fp)->err)
-#define f_tell(fp) ((fp)->fptr)
-#define f_size(fp) ((fp)->obj.objsize)
-#define f_rewind(fp) f_lseek((fp), 0)
-#define f_rewinddir(dp) f_readdir((dp), 0)
-#define f_rmdir(path) f_unlink(path)
-#define f_unmount(path) f_mount(NULL, path, 0)
-
-#ifndef EOF
-#define EOF (-1)
-#endif
-
-
-
-
-/*--------------------------------------------------------------*/
-/* Additional user defined functions */
-
-/* RTC function */
-#if !FF_FS_READONLY && !FF_FS_NORTC
-DWORD get_fattime (void);
-#endif
-
-/* LFN support functions */
-#if FF_USE_LFN >= 1 /* Code conversion (defined in unicode.c) */
-WCHAR ff_oem2uni (WCHAR oem, WORD cp); /* OEM code to Unicode conversion */
-WCHAR ff_uni2oem (DWORD uni, WORD cp); /* Unicode to OEM code conversion */
-DWORD ff_wtoupper (DWORD uni); /* Unicode upper-case conversion */
-#endif
-#if FF_USE_LFN == 3 /* Dynamic memory allocation */
-void* ff_memalloc (UINT msize); /* Allocate memory block */
-void ff_memfree (void* mblock); /* Free memory block */
-#endif
-
-/* Sync functions */
-#if FF_FS_REENTRANT
-int ff_cre_syncobj (BYTE vol, FF_SYNC_t* sobj); /* Create a sync object */
-int ff_req_grant (FF_SYNC_t sobj); /* Lock sync object */
-void ff_rel_grant (FF_SYNC_t sobj); /* Unlock sync object */
-int ff_del_syncobj (FF_SYNC_t sobj); /* Delete a sync object */
-#endif
-
-
-
-
-/*--------------------------------------------------------------*/
-/* Flags and offset address */
-
-
-/* File access mode and open method flags (3rd argument of f_open) */
-#define FA_READ 0x01
-#define FA_WRITE 0x02
-#define FA_OPEN_EXISTING 0x00
-#define FA_CREATE_NEW 0x04
-#define FA_CREATE_ALWAYS 0x08
-#define FA_OPEN_ALWAYS 0x10
-#define FA_OPEN_APPEND 0x30
-
-/* Fast seek controls (2nd argument of f_lseek) */
-#define CREATE_LINKMAP ((FSIZE_t)0 - 1)
-
-/* Format options (2nd argument of f_mkfs) */
-#define FM_FAT 0x01
-#define FM_FAT32 0x02
-#define FM_EXFAT 0x04
-#define FM_ANY 0x07
-#define FM_SFD 0x08
-
-/* Filesystem type (FATFS.fs_type) */
-#define FS_FAT12 1
-#define FS_FAT16 2
-#define FS_FAT32 3
-#define FS_EXFAT 4
-
-/* File attribute bits for directory entry (FILINFO.fattrib) */
-#define AM_RDO 0x01 /* Read only */
-#define AM_HID 0x02 /* Hidden */
-#define AM_SYS 0x04 /* System */
-#define AM_DIR 0x10 /* Directory */
-#define AM_ARC 0x20 /* Archive */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* FF_DEFINED */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9d/609c1a555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9d/609c1a555243001d18b399c1eb9b3628
deleted file mode 100644
index a22ecf5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9d/609c1a555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,324 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xparameters_ps.h
-*
-* This file contains the address definitions for the hard peripherals
-* attached to the ARM Cortex A53 core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 6.0 mus 18/08/16 Defined ARMA53_32 flag
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.01a nm 08/01/12 Added defines for the PS Version bits,
-* removed the FIFO Flush bits from the
-* Miscellaneous Control Reg
-* 2.03a nm 04/19/13 Fixed CR# 703728.
-* Updated the register definitions as per the latest TRM
-* version UG585 (v1.4) November 16, 2012.
-* 2.04a kpc 10/07/13 Added function prototype.
-* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
-*
-*
-******************************************************************************/
-#ifndef XDCFG_HW_H /* prevent circular inclusions */
-#define XDCFG_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- * Offsets of registers from the start of the device
- * @{
- */
-
-#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */
-#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */
-#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */
-#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */
-#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */
-#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */
-#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */
-#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */
-#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */
-#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */
-#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */
-#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */
-#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */
-#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */
-#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */
-
-/* @} */
-
-/** @name Control Register Bit definitions
- * @{
- */
-
-#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into
- * Secure Reset
- */
-#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to
- * Reset FPGA
- */
-#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */
-#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */
-#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */
-#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data
- * to FPGA every 4 PCAP
- * cycles
- */
-#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */
-#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */
-#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */
-#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */
-#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */
-#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */
-#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure
- * Status mask
- */
-#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive
- * Debug Enable
- */
-#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive
- * Debug Enable
- */
-#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug
- * Enable
- */
-#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug
- * Enable
- */
-#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */
-
-/* @} */
-
-/** @name Lock register bit definitions
- * @{
- */
-
-#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */
-#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */
-#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */
-#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and
- * USER_MODE
- */
-#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks
- * security config
- * including: DAP_En,
- * DBGEN,,
- * NIDEN, SPNIEN
- */
-/*@}*/
-
-
-
-/** @name Config Register Bit definitions
- * @{
- */
-#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO
- * Threshold Mask
- */
-#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold
- * Mask
- */
-#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active
- * clock edge
- */
-#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active
- * clock edge
- */
-#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address
- * increment mask
- */
-#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination
- * address increment
- * mask
- */
-/* @} */
-
-
-/** @name Interrupt Status/Mask Register Bit definitions
- * @{
- */
-#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during
- * HIZ
- */
-#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration
- * done
- */
-#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */
-#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during
- * configuration
- */
-#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration
- * reset
- */
-#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address
- * or Data or response
- * timeout
- */
-#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response
- * error
- */
-#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or
- * response timeout
- */
-#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response
- * error
- */
-#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */
-#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than
- * threshold */
-#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than
- * threshold */
-#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */
-#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue
- * overflow
- */
-#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */
-#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP
- * transfers Done
- */
-#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer
- * length error
- */
-#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */
-#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */
-#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */
-#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */
-#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */
-#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge
- * of Init Signal
- */
-#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge
- * of Init Signal
- */
-#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \
- XDCFG_IXR_AXI_WERR_MASK | \
- XDCFG_IXR_AXI_RTO_MASK | \
- XDCFG_IXR_AXI_RERR_MASK | \
- XDCFG_IXR_RX_FIFO_OV_MASK | \
- XDCFG_IXR_DMA_CMD_ERR_MASK |\
- XDCFG_IXR_DMA_Q_OV_MASK | \
- XDCFG_IXR_P2D_LEN_ERR_MASK |\
- XDCFG_IXR_PCFG_HMAC_ERR_MASK)
-
-
-#define XDCFG_IXR_ALL_MASK 0x00F7F8EF
-
-
-
-/* @} */
-
-
-/** @name Status Register Bit definitions
- * @{
- */
-#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command
- * Queue full
- */
-#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command
- * Queue empty
- */
-#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of
- * completed DMA
- * transfers
- */
-#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */
-#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */
-
-#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO
- * during HIZ
- */
-#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config
- * done
- */
-#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */
-#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during
- * config
- */
-#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset
- * POR Status
- */
-#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB
- * access
- */
-#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config
- * reset status
- */
-#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init
- * Status
- */
-#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008
- /**< BBRAM key
- * disable
- */
-#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security
- * Enable Status
- */
-#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG
- * Disable
- * status
- */
-/* @} */
-
-
-/** @name DMA Source/Destination Transfer Length Register Bit definitions
- * @{
- */
-#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */
-/*@}*/
-
-
-
-
-/** @name Miscellaneous Control Register Bit definitions
- * @{
- */
-#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */
-#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */
-#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */
-/* @} */
-
-/** @name FIFO Threshold Bit definitions
- * @{
- */
-
-#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */
-#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */
-#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */
-#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */
-/* @}*/
-
-
-/* Miscellaneous constant values */
-#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */
-#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/
-#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base
- * address
- */
-#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note C-style signature:
-* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XDcfg_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + (RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write to the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + (RegOffset), (Data))
-
-/************************** Function Prototypes ******************************/
-/*
- * Perform reset operation to the devcfg interface
- */
-void XDcfg_ResetHw(u32 BaseAddr);
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9e/40d269595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9e/40d269595243001d18b399c1eb9b3628
deleted file mode 100644
index 559ae46..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9e/40d269595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,101 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2008 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-*
-* microblaze_invalidate_dcache_range (unsigned int cacheaddr, unsigned int len)
-*
-* Invalidate a Dcache range
-*
-* Parameters:
-* 'cacheaddr' - address in the Dcache where invalidation begins
-* 'len ' - length (in bytes) worth of Dcache to be invalidated
-*
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-#include "microblaze_instructions.h"
-
-#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
-#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
-
-#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
-#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
-#endif
-
-#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
-#define MB_VERSION_LT_v720
-#define MB_HAS_WRITEBACK_SET 0
-#else
-#define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
-#endif
-
- .text
- .globl microblaze_invalidate_dcache_range
- .ent microblaze_invalidate_dcache_range
- .align 2
-
-microblaze_invalidate_dcache_range:
-#if (XPAR_MICROBLAZE_USE_DCACHE==1) && (XPAR_MICROBLAZE_ALLOW_DCACHE_WR==1)
-
-#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
- mfs r9, rmsr
- andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
- mts rmsr, r10
-#endif
-
- BEQI r6, L_done /* Skip loop if size is zero */
-
- ADD r6, r5, r6 /* Compute end address */
- ADDIK r6, r6, -1
-
- ANDI r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */
- ANDI r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align start down to cache line */
-
-#if MB_HAS_WRITEBACK_SET == 0 /* Use a different scheme for MB version < v7.20 or when caches are write-through */
-
-L_start:
- CMPU r18, r5, r6 /* Are we at the end? */
- BLTI r18, L_done
-
- wdc r5, r0
-
-#if defined (__arch64__ )
- addlik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the address by 4 */
- breai L_start /* Branch to the beginning of the loop */
-#else
- brid L_start /* Branch to the beginning of the loop */
- addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the address by 4 (delay slot) */
-#endif
-#else
-
- RSUBK r6, r5, r6
- /* r6 will now contain (count of bytes - (4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) */
-L_start:
- wdc.clear r5, r6 /* Invalidate the cache line only if the address matches */
-#if defined (__arch64__ )
- addlik r6, r6, -(XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
- beagei r6, L_start
-#else
- bneid r6, L_start
- addik r6, r6, -(XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
-#endif
-
-#endif
-
-L_done:
- rtsd r15, 8
-#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
- mts rmsr, r9
-#else
- nop
-#endif
-
-#else
- rtsd r15, 8
- nop
-#endif
- .end microblaze_invalidate_dcache_range
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9e/6394b0585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9e/6394b0585243001d18b399c1eb9b3628
deleted file mode 100644
index f0c63a3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9e/6394b0585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,30 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#include
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) sint32 _isatty(sint32 fd);
-}
-#endif
-
-/*
- * isatty -- returns 1 if connected to a terminal device,
- * returns 0 if not. Since we're hooked up to a
- * serial port, we'll say yes _AND return a 1.
- */
-__attribute__((weak)) sint32 isatty(sint32 fd)
-{
- (void)fd;
- return (1);
-}
-
-__attribute__((weak)) sint32 _isatty(sint32 fd)
-{
- (void)fd;
- return (1);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9e/829a39595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9e/829a39595243001d18b399c1eb9b3628
deleted file mode 100644
index c52d476..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9e/829a39595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,447 +0,0 @@
-/******************************************************************************
-* Copyright (c) 1995 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-*******************************************************************************/
-/*---------------------------------------------------*/
-/* Modified from : */
-/* Public Domain version of printf */
-/* Rud Merriam, Compsult, Inc. Houston, Tx. */
-/* For Embedded Systems Programming, 1991 */
-/* */
-/*---------------------------------------------------*/
-#include "xil_printf.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include
-#include
-#include
-
-static void padding( const s32 l_flag,const struct params_s *par);
-static void outs(const charptr lp, struct params_s *par);
-static s32 getnum( charptr* linep);
-
-typedef struct params_s {
- s32 len;
- s32 num1;
- s32 num2;
- char8 pad_character;
- s32 do_padding;
- s32 left_flag;
- s32 unsigned_flag;
-} params_t;
-
-
-/*---------------------------------------------------*/
-/* The purpose of this routine is to output data the */
-/* same as the standard printf function without the */
-/* overhead most run-time libraries involve. Usually */
-/* the printf brings in many kilobytes of code and */
-/* that is unacceptable in most embedded systems. */
-/*---------------------------------------------------*/
-
-
-/*---------------------------------------------------*/
-/* */
-/* This routine puts pad characters into the output */
-/* buffer. */
-/* */
-static void padding( const s32 l_flag, const struct params_s *par)
-{
- s32 i;
-
- if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) {
- i=(par->len);
- for (; i<(par->num1); i++) {
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( par->pad_character);
-#endif
- }
- }
-}
-
-/*---------------------------------------------------*/
-/* */
-/* This routine moves a string to the output buffer */
-/* as directed by the padding and positioning flags. */
-/* */
-static void outs(const charptr lp, struct params_s *par)
-{
- charptr LocalPtr;
- LocalPtr = lp;
- /* pad on left if needed */
- if(LocalPtr != NULL) {
- par->len = (s32)strlen( LocalPtr);
- padding( !(par->left_flag), par);
- /* Move string to the buffer */
- while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) {
- (par->num2)--;
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte(*LocalPtr);
-#endif
- LocalPtr += 1;
- }
-}
-
- /* Pad on right if needed */
- /* CR 439175 - elided next stmt. Seemed bogus. */
- /* par->len = strlen( lp) */
- padding( par->left_flag, par);
-}
-
-/*---------------------------------------------------*/
-/* */
-/* This routine moves a number to the output buffer */
-/* as directed by the padding and positioning flags. */
-/* */
-
-static void outnum( const s32 n, const s32 base, struct params_s *par)
-{
- s32 negative;
- s32 i;
- char8 outbuf[32];
- const char8 digits[] = "0123456789ABCDEF";
- u32 num;
- for(i = 0; i<32; i++) {
- outbuf[i] = '0';
- }
-
- /* Check if number is negative */
- if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
- negative = 1;
- num =(-(n));
- }
- else{
- num = n;
- negative = 0;
- }
-
- /* Build number (backwards) in outbuf */
- i = 0;
- do {
- outbuf[i] = digits[(num % base)];
- i++;
- num /= base;
- } while (num > 0);
-
- if (negative != 0) {
- outbuf[i] = '-';
- i++;
- }
-
- outbuf[i] = '\0';
- i--;
-
- /* Move the converted number to the buffer and */
- /* add in the padding where needed. */
- par->len = (s32)strlen(outbuf);
- padding( !(par->left_flag), par);
- while (&outbuf[i] >= outbuf) {
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( outbuf[i] );
-#endif
- i--;
-}
- padding( par->left_flag, par);
-}
-/*---------------------------------------------------*/
-/* */
-/* This routine moves a 64-bit number to the output */
-/* buffer as directed by the padding and positioning */
-/* flags. */
-/* */
-#if defined (__aarch64__) || defined (__arch64__)
-static void outnum1( const s64 n, const s32 base, params_t *par)
-{
- s32 negative;
- s32 i;
- char8 outbuf[64];
- const char8 digits[] = "0123456789ABCDEF";
- u64 num;
- for(i = 0; i<64; i++) {
- outbuf[i] = '0';
- }
-
- /* Check if number is negative */
- if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
- negative = 1;
- num =(-(n));
- }
- else{
- num = (n);
- negative = 0;
- }
-
- /* Build number (backwards) in outbuf */
- i = 0;
- do {
- outbuf[i] = digits[(num % base)];
- i++;
- num /= base;
- } while (num > 0);
-
- if (negative != 0) {
- outbuf[i] = '-';
- i++;
- }
-
- outbuf[i] = '\0';
- i--;
-
- /* Move the converted number to the buffer and */
- /* add in the padding where needed. */
- par->len = (s32)strlen(outbuf);
- padding( !(par->left_flag), par);
- while (&outbuf[i] >= outbuf) {
- outbyte( outbuf[i] );
- i--;
-}
- padding( par->left_flag, par);
-}
-#endif
-/*---------------------------------------------------*/
-/* */
-/* This routine gets a number from the format */
-/* string. */
-/* */
-static s32 getnum(charptr* linep)
-{
- s32 n = 0;
- s32 ResultIsDigit = 0;
- charptr cptr = *linep;
-
- while (cptr != NULL) {
- ResultIsDigit = isdigit(((s32)*cptr));
- if (ResultIsDigit == 0)
- break;
- n = ((n*10) + (((s32)*cptr) - (s32)'0'));
- cptr += 1;
- }
-
- *linep = ((charptr)(cptr));
- return(n);
-}
-
-/*---------------------------------------------------*/
-/* */
-/* This routine operates just like a printf/sprintf */
-/* routine. It outputs a set of data under the */
-/* control of a formatting string. Not all of the */
-/* standard C format control are supported. The ones */
-/* provided are primarily those needed for embedded */
-/* systems work. Primarily the floating point */
-/* routines are omitted. Other formats could be */
-/* added easily by following the examples shown for */
-/* the supported formats. */
-/* */
-
-/* void esp_printf( const func_ptr f_ptr,
- const charptr ctrl1, ...) */
-#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
-void xil_printf( const char8 *ctrl1, ...){
- XPVXenConsole_Printf(ctrl1);
-}
-#else
-void xil_printf( const char8 *ctrl1, ...)
-{
- va_list argp;
-
- va_start(argp, ctrl1);
-
- xil_vprintf(ctrl1, argp);
-
- va_end(argp);
-}
-#endif
-
-/* This routine is equivalent to vprintf routine */
-void xil_vprintf(const char8 *ctrl1, va_list argp)
-{
- s32 Check;
-#if defined (__aarch64__) || defined (__arch64__)
- s32 long_flag;
-#endif
- s32 dot_flag;
-
- params_t par;
-
- char8 ch;
- char8 *ctrl = (char8 *)ctrl1;
-
- while ((ctrl != NULL) && (*ctrl != (char8)0)) {
-
- /* move format string chars to buffer until a */
- /* format control is found. */
- if (*ctrl != '%') {
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte(*ctrl);
-#endif
- ctrl += 1;
- continue;
- }
-
- /* initialize all the flags for this format. */
- dot_flag = 0;
-#if defined (__aarch64__) || defined (__arch64__)
- long_flag = 0;
-#endif
- par.unsigned_flag = 0;
- par.left_flag = 0;
- par.do_padding = 0;
- par.pad_character = ' ';
- par.num2=32767;
- par.num1=0;
- par.len=0;
-
- try_next:
- if(ctrl != NULL) {
- ctrl += 1;
- }
- if(ctrl != NULL) {
- ch = *ctrl;
- } else {
- break;
- }
-
- if (isdigit((s32)ch) != 0) {
- if (dot_flag != 0) {
- par.num2 = getnum(&ctrl);
- }
- else {
- if (ch == '0') {
- par.pad_character = '0';
- }
- if(ctrl != NULL) {
- par.num1 = getnum(&ctrl);
- }
- par.do_padding = 1;
- }
- if(ctrl != NULL) {
- ctrl -= 1;
- }
- goto try_next;
- }
-
- switch (tolower((s32)ch)) {
- case '%':
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( '%');
-#endif
- Check = 1;
- break;
-
- case '-':
- par.left_flag = 1;
- Check = 0;
- break;
-
- case '.':
- dot_flag = 1;
- Check = 0;
- break;
-
- case 'l':
- #if defined (__aarch64__) || defined (__arch64__)
- long_flag = 1;
- #endif
- Check = 0;
- break;
-
- case 'u':
- par.unsigned_flag = 1;
- /* fall through */
- case 'i':
- case 'd':
- #if defined (__aarch64__) || defined (__arch64__)
- if (long_flag != 0){
- outnum1((s64)va_arg(argp, s64), 10L, &par);
- }
- else {
- outnum( va_arg(argp, s32), 10L, &par);
- }
- #else
- outnum( va_arg(argp, s32), 10L, &par);
- #endif
- Check = 1;
- break;
- case 'p':
- #if defined (__aarch64__) || defined (__arch64__)
- par.unsigned_flag = 1;
- outnum1((s64)va_arg(argp, s64), 16L, &par);
- Check = 1;
- break;
- #endif
- case 'X':
- case 'x':
- par.unsigned_flag = 1;
- #if defined (__aarch64__) || defined (__arch64__)
- if (long_flag != 0) {
- outnum1((s64)va_arg(argp, s64), 16L, &par);
- }
- else {
- outnum((s32)va_arg(argp, s32), 16L, &par);
- }
- #else
- outnum((s32)va_arg(argp, s32), 16L, &par);
- #endif
- Check = 1;
- break;
-
- case 's':
- outs( va_arg( argp, char *), &par);
- Check = 1;
- break;
-
- case 'c':
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( va_arg( argp, s32));
-#endif
- Check = 1;
- break;
-
- case '\\':
- switch (*ctrl) {
- case 'a':
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( ((char8)0x07));
-#endif
- break;
- case 'h':
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( ((char8)0x08));
-#endif
- break;
- case 'r':
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( ((char8)0x0D));
-#endif
- break;
- case 'n':
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( ((char8)0x0D));
- outbyte( ((char8)0x0A));
-#endif
- break;
- default:
-#if defined(STDOUT_BASEADDRESS) || defined(VERSAL_PLM)
- outbyte( *ctrl);
-#endif
- break;
- }
- ctrl += 1;
- Check = 0;
- break;
-
- default:
- Check = 1;
- break;
- }
- if(Check == 1) {
- if(ctrl != NULL) {
- ctrl += 1;
- }
- continue;
- }
- goto try_next;
- }
-}
-/*---------------------------------------------------*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9e/a13457595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9e/a13457595243001d18b399c1eb9b3628
deleted file mode 100644
index c38e742..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9e/a13457595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,29 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-* Disable exceptions on microblaze.
-*
-*
-******************************************************************************/
-
-#include "xparameters.h"
-
- .text
- .globl microblaze_disable_exceptions
- .ent microblaze_disable_exceptions
- .align 2
-microblaze_disable_exceptions:
-#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
- rtsd r15, 8
- msrclr r0, 0x100
-#else
- mfs r4, rmsr;
- andi r4, r4, ~(0x100); /* Turn OFF the EE bit */
- mts rmsr, r4;
- rtsd r15, 8;
- nop;
-#endif
-.end microblaze_disable_exceptions
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9e/a14d4a575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9e/a14d4a575243001d18b399c1eb9b3628
deleted file mode 100644
index 5050be5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9e/a14d4a575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,117 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 666666687
-#define DDR_FREQ 533333374
-#define DCI_FREQ 10158730
-#define QSPI_FREQ 200000000
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 125000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 50000000
-#define UART_FREQ 100000000
-#define SPI_FREQ 10000000
-#define I2C_FREQ 111111115
-#define WDT_FREQ 111111115
-#define TTC_FREQ 50000000
-#define CAN_FREQ 10000000
-#define PCAP_FREQ 200000000
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 50000000
-#define FPGA1_FREQ 10000000
-#define FPGA2_FREQ 10000000
-#define FPGA3_FREQ 10000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9e/a2d0c6575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9e/a2d0c6575243001d18b399c1eb9b3628
deleted file mode 100644
index b42d32b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9e/a2d0c6575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,68 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xdevcfg_sinit.c
-* @addtogroup devcfg_v3_7
-* @{
-*
-* This file contains method for static initialization (compile-time) of the
-* driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 3.5 ms 08/07/17 Fixed compilation warnings.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xdevcfg.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-* Lookup the device configuration based on the unique device ID. The table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId is the unique device ID of the device being looked up.
-*
-* @return A pointer to the configuration table entry corresponding to the
-* given device ID, or NULL if no match is found.
-*
-* @note None.
-*
-******************************************************************************/
-XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId)
-{
- extern XDcfg_Config XDcfg_ConfigTable[];
- XDcfg_Config *CfgPtr = NULL;
- u32 Index;
-
- for (Index = 0U; Index < XPAR_XDCFG_NUM_INSTANCES; Index++) {
- if (XDcfg_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XDcfg_ConfigTable[Index];
- break;
- }
- }
-
- return (CfgPtr);
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9e/b186c4575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9e/b186c4575243001d18b399c1eb9b3628
deleted file mode 100644
index 1feacd9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9e/b186c4575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,87 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xdevcfg_hw.c
-* @addtogroup devcfg_v3_7
-* @{
-*
-* This file contains the implementation of the interface reset functionality
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 2.04a kpc 10/07/13 First release
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xdevcfg_hw.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-* This function perform the reset sequence to the given devcfg interface by
-* configuring the appropriate control bits in the devcfg specifc registers
-* the devcfg reset squence involves the following steps
-* Disable all the interuupts
-* Clear the status
-* Update relevant config registers with reset values
-* Disbale the looopback mode and pcap rate enable
-*
-* @param BaseAddress of the interface
-*
-* @return N/A
-*
-* @note
-* This function will not modify the slcr registers that are relavant for
-* devcfg controller
-******************************************************************************/
-void XDcfg_ResetHw(u32 BaseAddr)
-{
- u32 Regval = 0;
-
- /* Mask the interrupts */
- XDcfg_WriteReg(BaseAddr, XDCFG_INT_MASK_OFFSET,
- XDCFG_IXR_ALL_MASK);
- /* Clear the interuupt status */
- Regval = XDcfg_ReadReg(BaseAddr, XDCFG_INT_STS_OFFSET);
- XDcfg_WriteReg(BaseAddr, XDCFG_INT_STS_OFFSET, Regval);
- /* Clear the source address register */
- XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_ADDR_OFFSET, 0x0);
- /* Clear the destination address register */
- XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_ADDR_OFFSET, 0x0);
- /* Clear the source length register */
- XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_LEN_OFFSET, 0x0);
- /* Clear the destination length register */
- XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_LEN_OFFSET, 0x0);
- /* Clear the loopback enable bit */
- Regval = XDcfg_ReadReg(BaseAddr, XDCFG_MCTRL_OFFSET);
- Regval = Regval & ~XDCFG_MCTRL_PCAP_LPBK_MASK;
- XDcfg_WriteReg(BaseAddr, XDCFG_MCTRL_OFFSET, Regval);
- /*Reset the configuration register to reset value */
- XDcfg_WriteReg(BaseAddr, XDCFG_CFG_OFFSET,
- XDCFG_CONFIG_RESET_VALUE);
- /*Disable the PCAP rate enable bit */
- Regval = XDcfg_ReadReg(BaseAddr, XDCFG_CTRL_OFFSET);
- Regval = Regval & ~XDCFG_CTRL_PCAP_RATE_EN_MASK;
- XDcfg_WriteReg(BaseAddr, XDCFG_CTRL_OFFSET, Regval);
-
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9f/1184a1595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9f/1184a1595243001d18b399c1eb9b3628
deleted file mode 100644
index 853ef6b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9f/1184a1595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,412 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_io.h
-*
-* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
-*
-* The xil_io.h file contains the interface for the general I/O component, which
-* encapsulates the Input/Output functions for the processors that do not
-* require any special I/O handling.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/29/14 First release
-* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
-* ARM processors
-* 7.20 har 01/03/20 Added Xil_SecureOut32 for avoiding blindwrite for
-* CR-1049218
-* 7.30 kpt 09/21/20 Moved Xil_EndianSwap16 and Xil_EndianSwap32 to
-* xil_io.h and made them as static inline
-* am 10/13/20 Changed the return type of Xil_SecureOut32 function
-* from u32 to int
-* 7.50 dp 02/12/21 Fix compilation error in Xil_EndianSwap32() that occur
-* when -Werror=conversion compiler flag is enabled
-* 7.5 mus 05/17/21 Update the functions with comments. It fixes CR#1067739.
-*
-*
-******************************************************************************/
-
-#ifndef XIL_IO_H /* prevent circular inclusions */
-#define XIL_IO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_printf.h"
-#include "xstatus.h"
-
-#if defined (__MICROBLAZE__)
-#include "mb_interface.h"
-#else
-#include "xpseudo_asm.h"
-#endif
-
-/************************** Function Prototypes ******************************/
-#ifdef ENABLE_SAFETY
-extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
-#endif
-
-/***************** Macros (Inline Functions) Definitions *********************/
-#if defined __GNUC__
-#if defined (__MICROBLAZE__)
-# define INST_SYNC mbar(0)
-# define DATA_SYNC mbar(1)
-# else
-# define SYNCHRONIZE_IO dmb()
-# define INST_SYNC isb()
-# define DATA_SYNC dsb()
-# endif
-#else
-# define SYNCHRONIZE_IO
-# define INST_SYNC
-# define DATA_SYNC
-# define INST_SYNC
-# define DATA_SYNC
-#endif
-
-#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
-#define INLINE inline
-#else
-#define INLINE __inline
-#endif
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading
-* from the specified address and returning the 8 bit Value read from
-* that address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 8 bit Value read from the specified input address.
-
-*
-******************************************************************************/
-static INLINE u8 Xil_In8(UINTPTR Addr)
-{
- return *(volatile u8 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading from
-* the specified address and returning the 16 bit Value read from that
-* address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 16 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u16 Xil_In16(UINTPTR Addr)
-{
- return *(volatile u16 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by
-* reading from the specified address and returning the 32 bit Value
-* read from that address.
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 32 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u32 Xil_In32(UINTPTR Addr)
-{
- return *(volatile u32 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an input operation for a memory location by reading the
-* 64 bit Value read from that address.
-*
-*
-* @param Addr: contains the address to perform the input operation
-*
-* @return The 64 bit Value read from the specified input address.
-*
-******************************************************************************/
-static INLINE u64 Xil_In64(UINTPTR Addr)
-{
- return *(volatile u64 *) Addr;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for an memory location by
-* writing the 8 bit Value to the the specified address.
-*
-* @param Addr: contains the address to perform the output operation
-* @param Value: contains the 8 bit Value to be written at the specified
-* address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
-{
- /* write 8 bit value to specified address */
- volatile u8 *LocalAddr = (volatile u8 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 16 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains the Value to be written at the specified address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
-{
- /* write 16 bit value to specified address */
- volatile u16 *LocalAddr = (volatile u16 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 32 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains the 32 bit Value to be written at the specified
-* address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
-{
- /* write 32 bit value to specified address */
-#ifndef ENABLE_SAFETY
- volatile u32 *LocalAddr = (volatile u32 *)Addr;
- *LocalAddr = Value;
-#else
- XStl_RegUpdate(Addr, Value);
-#endif
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Performs an output operation for a memory location by writing the
-* 64 bit Value to the the specified address.
-*
-* @param Addr contains the address to perform the output operation
-* @param Value contains 64 bit Value to be written at the specified address.
-*
-* @return None.
-*
-******************************************************************************/
-static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
-{
- /* write 64 bit value to specified address */
- volatile u64 *LocalAddr = (volatile u64 *)Addr;
- *LocalAddr = Value;
-}
-
-/*****************************************************************************/
-/**
- *
- * @brief Performs an output operation for a memory location by writing the
- * 32 bit Value to the the specified address and then reading it
- * back to verify the value written in the register.
- *
- * @param Addr contains the address to perform the output operation
- * @param Value contains 32 bit Value to be written at the specified address
- *
- * @return Returns Status
- * - XST_SUCCESS on success
- * - XST_FAILURE on failure
- *
- *****************************************************************************/
-static INLINE int Xil_SecureOut32(UINTPTR Addr, u32 Value)
-{
- int Status = XST_FAILURE;
- u32 ReadReg;
- u32 ReadRegTemp;
-
- /* writing 32 bit value to specified address */
- Xil_Out32(Addr, Value);
-
- /* verify value written to specified address with multiple reads */
- ReadReg = Xil_In32(Addr);
- ReadRegTemp = Xil_In32(Addr);
-
- if( (ReadReg == Value) && (ReadRegTemp == Value) ) {
- Status = XST_SUCCESS;
- }
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a 16-bit endian conversion.
-*
-* @param Data: 16 bit value to be converted
-*
-* @return 16 bit Data with converted endianness
-*
-******************************************************************************/
-static INLINE __attribute__((always_inline)) u16 Xil_EndianSwap16(u16 Data)
-{
- return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a 32-bit endian conversion.
-*
-* @param Data: 32 bit value to be converted
-*
-* @return 32 bit data with converted endianness
-*
-******************************************************************************/
-static INLINE __attribute__((always_inline)) u32 Xil_EndianSwap32(u32 Data)
-{
- u16 LoWord;
- u16 HiWord;
-
- /* get each of the half words from the 32 bit word */
-
- LoWord = (u16) (Data & 0x0000FFFFU);
- HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
-
- /* byte swap each of the 16 bit half words */
-
- LoWord = (u16)(((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
- HiWord = (u16)(((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
-
- /* swap the half words before returning the value */
-
- return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-# define Xil_In16LE Xil_In16
-# define Xil_In32LE Xil_In32
-# define Xil_Out16LE Xil_Out16
-# define Xil_Out32LE Xil_Out32
-# define Xil_Htons Xil_EndianSwap16
-# define Xil_Htonl Xil_EndianSwap32
-# define Xil_Ntohs Xil_EndianSwap16
-# define Xil_Ntohl Xil_EndianSwap32
-# else
-# define Xil_In16BE Xil_In16
-# define Xil_In32BE Xil_In32
-# define Xil_Out16BE Xil_Out16
-# define Xil_Out32BE Xil_Out32
-# define Xil_Htons(Data) (Data)
-# define Xil_Htonl(Data) (Data)
-# define Xil_Ntohs(Data) (Data)
-# define Xil_Ntohl(Data) (Data)
-#endif
-#else
-# define Xil_In16LE Xil_In16
-# define Xil_In32LE Xil_In32
-# define Xil_Out16LE Xil_Out16
-# define Xil_Out32LE Xil_Out32
-# define Xil_Htons Xil_EndianSwap16
-# define Xil_Htonl Xil_EndianSwap32
-# define Xil_Ntohs Xil_EndianSwap16
-# define Xil_Ntohl Xil_EndianSwap32
-#endif
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE u16 Xil_In16BE(UINTPTR Addr)
-#else
-static INLINE u16 Xil_In16LE(UINTPTR Addr)
-#endif
-#else
-static INLINE u16 Xil_In16BE(UINTPTR Addr)
-#endif
-{
- u16 value = Xil_In16(Addr);
- return Xil_EndianSwap16(value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE u32 Xil_In32BE(UINTPTR Addr)
-#else
-static INLINE u32 Xil_In32LE(UINTPTR Addr)
-#endif
-#else
-static INLINE u32 Xil_In32BE(UINTPTR Addr)
-#endif
-{
- u32 value = Xil_In32(Addr);
- return Xil_EndianSwap32(value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
-#else
-static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
-#endif
-#else
-static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
-#endif
-{
- Value = Xil_EndianSwap16(Value);
- Xil_Out16(Addr, Value);
-}
-
-#if defined (__MICROBLAZE__)
-#ifdef __LITTLE_ENDIAN__
-static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
-#else
-static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
-#endif
-#else
-static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
-#endif
-{
- Value = Xil_EndianSwap32(Value);
- Xil_Out32(Addr, Value);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_io_interfacing_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9f/800b3c595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9f/800b3c595243001d18b399c1eb9b3628
deleted file mode 100644
index e469934..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9f/800b3c595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,80 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2017 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-*@file xil_sleepcommon.c
-*
-* This file contains the sleep API's
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.6 srm 11/02/17 First release
-*
-******************************************************************************/
-
-
-/***************************** Include Files *********************************/
-#include "xil_io.h"
-#include "sleep.h"
-
-/**************************** Constant Definitions *************************/
-
-
-/*****************************************************************************/
-/**
-*
-* This API gives delay in sec
-*
-* @param seconds - delay time in seconds
-*
-* @return none
-*
-* @note none
-*
-*****************************************************************************/
- void sleep(unsigned int seconds)
- {
-#if defined (ARMR5)
- sleep_R5(seconds);
-#elif defined (__aarch64__) || defined (ARMA53_32)
- sleep_A53(seconds);
-#elif defined (__MICROBLAZE__)
- sleep_MB(seconds);
-#else
- sleep_A9(seconds);
-#endif
-
- }
-
-/****************************************************************************/
-/**
-*
-* This API gives delay in usec
-*
-* @param useconds - delay time in useconds
-*
-* @return none
-*
-* @note none
-*
-*****************************************************************************/
- void usleep(unsigned long useconds)
- {
-#if defined (ARMR5)
- usleep_R5(useconds);
-#elif defined (__aarch64__) || defined (ARMA53_32)
- usleep_A53(useconds);
-#elif defined (__MICROBLAZE__)
- usleep_MB(useconds);
-#else
- usleep_A9(useconds);
-#endif
-
- }
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9f/907ab3585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9f/907ab3585243001d18b399c1eb9b3628
deleted file mode 100644
index b248e6a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9f/907ab3585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,27 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#ifndef UNDEFINE_FILE_OPS
-#include
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode);
-}
-#endif
-/*
- * open -- open a file descriptor. We don't have a filesystem, so
- * we return an error.
- */
-__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode)
-{
- (void)buf;
- (void)flags;
- (void)mode;
- errno = EIO;
- return (-1);
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9f/a0ac43595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9f/a0ac43595243001d18b399c1eb9b3628
deleted file mode 100644
index 1d18bfb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9f/a0ac43595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,203 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_types.h
-*
-* @addtogroup common_types Basic Data types for Xilinx® Software IP
-*
-* The xil_types.h file contains basic types for Xilinx software IP. These data types
-* are applicable for all processors supported by Xilinx.
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 First release
-* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
-* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
-* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
-* Define LONG and ULONG datatypes and mask values
-* 7.00 mus 01/07/19 Add cpp extern macro
-* 7.1 aru 08/19/19 Shift the value in UPPER_32_BITS only if it
-* is 64-bit processor
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-#ifndef XIL_TYPES_H /* prevent circular inclusions */
-#define XIL_TYPES_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include
-#include
-
-/************************** Constant Definitions *****************************/
-
-#ifndef TRUE
-# define TRUE 1U
-#endif
-
-#ifndef FALSE
-# define FALSE 0U
-#endif
-
-#ifndef NULL
-#define NULL 0U
-#endif
-
-#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be
- assigend to "IsReady" member of driver
- instance to indicate that driver
- instance is initialized and ready to use. */
-#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to
- "IsStarted" member of driver instance
- to indicate that driver instance is
- started and it can be enabled. */
-
-/* @name New types
- * New simple types.
- * @{
- */
-#ifndef __KERNEL__
-#ifndef XBASIC_TYPES_H
-/*
- * guarded against xbasic_types.h.
- */
-typedef uint8_t u8;
-typedef uint16_t u16;
-typedef uint32_t u32;
-/** @}*/
-#define __XUINT64__
-typedef struct
-{
- u32 Upper;
- u32 Lower;
-} Xuint64;
-
-
-/*****************************************************************************/
-/**
-* @brief Return the most significant half of the 64 bit data type.
-*
-* @param x is the 64 bit word.
-*
-* @return The upper 32 bits of the 64 bit word.
-*
-******************************************************************************/
-#define XUINT64_MSW(x) ((x).Upper)
-
-/*****************************************************************************/
-/**
-* @brief Return the least significant half of the 64 bit data type.
-*
-* @param x is the 64 bit word.
-*
-* @return The lower 32 bits of the 64 bit word.
-*
-******************************************************************************/
-#define XUINT64_LSW(x) ((x).Lower)
-
-#endif /* XBASIC_TYPES_H */
-
-/*
- * xbasic_types.h does not typedef s* or u64
- */
-/** @{ */
-typedef char char8;
-typedef int8_t s8;
-typedef int16_t s16;
-typedef int32_t s32;
-typedef int64_t s64;
-typedef uint64_t u64;
-typedef int sint32;
-
-typedef intptr_t INTPTR;
-typedef uintptr_t UINTPTR;
-typedef ptrdiff_t PTRDIFF;
-/** @}*/
-#if !defined(LONG) || !defined(ULONG)
-typedef long LONG;
-typedef unsigned long ULONG;
-#endif
-
-#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
-#define ULONG64_LO_MASK ~ULONG64_HI_MASK
-
-#else
-#include
-#endif
-
-/** @{ */
-/**
- * This data type defines an interrupt handler for a device.
- * The argument points to the instance of the component
- */
-typedef void (*XInterruptHandler) (void *InstancePtr);
-
-/**
- * This data type defines an exception handler for a processor.
- * The argument points to the instance of the component
- */
-typedef void (*XExceptionHandler) (void *InstancePtr);
-
-/**
- * @brief Returns 32-63 bits of a number.
- * @param n : Number being accessed.
- * @return Bits 32-63 of number.
- *
- * @note A basic shift-right of a 64- or 32-bit quantity.
- * Use this to suppress the "right shift count >= width of type"
- * warning when that quantity is 32-bits.
- */
-#if defined (__aarch64__) || defined (__arch64__)
-#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
-#else
-#define UPPER_32_BITS(n) 0U
-#endif
-/**
- * @brief Returns 0-31 bits of a number
- * @param n : Number being accessed.
- * @return Bits 0-31 of number
- */
-#define LOWER_32_BITS(n) ((u32)(n))
-
-
-
-
-/************************** Constant Definitions *****************************/
-
-#ifndef TRUE
-#define TRUE 1U
-#endif
-
-#ifndef FALSE
-#define FALSE 0U
-#endif
-
-#ifndef NULL
-#define NULL 0U
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
- *@endcond
- */
-/**
-* @} End of "addtogroup common_types".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9f/d0a793565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9f/d0a793565243001d18b399c1eb9b3628
deleted file mode 100644
index b8b4805..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9f/d0a793565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,51 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2008 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-*
-* microblaze_flush_dcache()
-*
-* Flush the L1 DCache
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-#include "microblaze_instructions.h"
-
-#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
-#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
-
-#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
-#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
-#endif
-
- .text
- .globl microblaze_flush_dcache
- .ent microblaze_flush_dcache
- .align 2
-
-microblaze_flush_dcache:
-#if (XPAR_MICROBLAZE_USE_DCACHE==1) && (XPAR_MICROBLAZE_ALLOW_DCACHE_WR==1)
- ADDIK r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Align to cache line */
- ADDIK r6, r5, XPAR_MICROBLAZE_DCACHE_BYTE_SIZE & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) /* Compute end */
-
-L_start:
- wdc.flush r5, r0 /* Flush the Cache */
-
- CMPU r18, r5, r6 /* Are we at the end? */
- BLEI r18, L_done
-
-#if defined (__arch64__ )
- addlik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the address by 4 */
- BRI L_start
-#else
- brid L_start /* Branch to the beginning of the loop */
- addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the address by 4 (delay slot) */
-#endif
-L_done:
-#endif
- rtsd r15, 8 /* Return */
- nop
- .end microblaze_flush_dcache
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9f/d1a704595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9f/d1a704595243001d18b399c1eb9b3628
deleted file mode 100644
index 5db2e71..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/9f/d1a704595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,83 +0,0 @@
-###############################################################################
-# Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
-# SPDX-License-Identifier: MIT
-###############################################################################
-DRIVER_LIB_VERSION = v1.0
-
-include config.make
-CC=$(COMPILER)
-AR=$(ARCHIVER)
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS))
-ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS))
-
-ifeq ($(notdir $(CC)), armr5-none-eabi-gcc)
-ECC_FLAGS += -nostartfiles
-endif
-ECC_FLAGS_NO_FLTO1 = $(subst -flto,,$(ECC_FLAGS))
-ECC_FLAGS_NO_FLTO = $(subst -ffat-lto-objects,,$(ECC_FLAGS_NO_FLTO1))
-
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-SRCFILES:=$(wildcard *.c)
-
-ASSEMBLY_SRCFILES:=$(wildcard *.S)
-
-OBJECTS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(filter-out _exit.c, $(wildcard *.c)))))
-ASSEMBLY_OBJECTS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(wildcard *.S))))
-
-NON_LTO_OBJECTS = $(addprefix $(RELEASEDIR),$(addsuffix .o,$(basename _exit.c)))
-
-INCLUDEFILES=*.h
-INCLUDEFILES+=includes_ps/*.h
-
-libs: $(LIBS)
-
-standalone_libs: $(OBJECTS) $(ASSEMBLY_OBJECTS) $(NON_LTO_OBJECTS)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-ASSEMBLY_DEPFILES := $(ASSEMBLY_SRCFILES:%.S=$(RELEASEDIR)%.d)
-
-include $(wildcard $(ASSEMBLY_DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)_exit.o: _exit.c
- $(CC) $(CC_FLAGS) $(ECC_FLAGS_NO_FLTO) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $<
-
-$(RELEASEDIR)%.o: %.S
- $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $<
-
-$(RELEASEDIR)%.o: %.c
- $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $<
-
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h)) $(addprefix $(INCLUDEDIR), $(subst includes_ps/,,$(wildcard includes_ps/*.h)))
-
-
-
-$(INCLUDEDIR)%.h: includes_ps/%.h
- $(CP) $< $@
-
-
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf ${ASSEMBLY_OBJECTS}
- rm -rf $(DEPFILES)
- rm -rf $(ASSEMBLY_DEPFILES)
- rm -rf $(NON_LTO_OBJECTS)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a/71e88e525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a/71e88e525243001d18b399c1eb9b3628
deleted file mode 100644
index a8544b3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a/71e88e525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,40 +0,0 @@
-/*******************************************************************************
-* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-*******************************************************************************/
-
-/******************************************************************************/
-/**
- *
- * @file xddrps.h
- * @addtogroup ddrps_v1_2
- * @{
- * @details
- *
- * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps
- * IP core.
- *
- * @note None.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.0 nsk 08/06/15 First Release
- * 1.0 nsk 08/20/15 Updated define_addr_params in ddrps.tcl
- * to support PBD Designs (CR #876857)
- *
- *
- *
-*******************************************************************************/
-
-#ifndef XDDRPS_H_
-/* Prevent circular inclusions by using protection macros. */
-#define XDDRPS_H_
-
-/******************************* Include Files ********************************/
-
-
-#endif /* XDDRPS_H_ */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a/904263595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a/904263595243001d18b399c1eb9b3628
deleted file mode 100644
index 869dc92..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a/904263595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,59 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2006 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-* microblaze_init_dcache_range (unsigned int cache_start, unsigned int cache_len)
-*
-* Invalidate dcache on the microblaze
-*
-* Parameters:
-* 'cache_start' - address in the Dcache where invalidation begins
-* 'cache_len' - length (in bytes) worth of Dcache to be invalidated
-*
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-
-#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
-#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
-
-#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
-#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
-#endif
-
- .text
- .globl microblaze_init_dcache_range
- .ent microblaze_init_dcache_range
- .align 2
-
-microblaze_init_dcache_range:
-#if (XPAR_MICROBLAZE_USE_DCACHE==1) && (XPAR_MICROBLAZE_ALLOW_DCACHE_WR==1)
- mfs r9, rmsr /* Disable Dcache and interrupts before invalidating */
- andi r10, r9, (~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE))
- mts rmsr, r10
-
- andi r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align to cache line */
-
- add r6, r5, r6 /* Compute end */
- andi r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align to cache line */
-
-L_start:
- wdc r5, r0 /* Invalidate the Cache (delay slot) */
-
- cmpu r18, r5, r6 /* Are we at the end ? */
- blei r18, L_done
-
- brid L_start /* Branch to the beginning of the loop */
- addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the address by 4 (delay slot) */
-
-L_done:
- rtsd r15, 8 /* Return */
- mts rmsr, r9
-#else
- rtsd r15, 8 /* Return */
- nop
-#endif
- .end microblaze_init_dcache_range
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a/a3217b575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a/a3217b575243001d18b399c1eb9b3628
deleted file mode 100644
index 21c8ced..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a/a3217b575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,75 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache_l.h
-*
-* Contains L1 and L2 specific functions for the ARM cache functionality
-* used by xcache.c. This functionality is being made available here for
-* more sophisticated users.
-*
-* @addtogroup a9_cache_apis
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 01/24/10 First release
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 First release
-* 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx is modified.
-* Earlier it used to search in "BdLimit" number of BDs to
-* know which BDs are processed. Now one more check is
-* added. It looks for BDs till the current BD pointer
-* reaches HwTail. By doing this processing time is saved.
-* 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
-* xemacps_bdring.c is modified. Now start of packet is
-* searched for returning the number of BDs processed.
-* 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
-* removed. It is expected that all BDs are allocated in
-* from uncached area. Fix for CR #663885.
-* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
-* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.6 rb 09/08/17 Add XEmacPs_BdRingPtrReset() API to reset BD ring
-* pointers
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xil_cache.h"
-#include "xemacps_hw.h"
-#include "xemacps_bd.h"
-#include "xemacps_bdring.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************
- * Compute the virtual address of a descriptor from its physical address
- *
- * @param BdPtr is the physical address of the BD
- *
- * @returns Virtual address of BdPtr
- *
- * @note Assume BdPtr is always a valid BD in the ring
- ****************************************************************************/
-#define XEMACPS_PHYS_TO_VIRT(BdPtr) \
- ((UINTPTR)(BdPtr) + (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr))
-
-/****************************************************************************
- * Compute the physical address of a descriptor from its virtual address
- *
- * @param BdPtr is the physical address of the BD
- *
- * @returns Physical address of BdPtr
- *
- * @note Assume BdPtr is always a valid BD in the ring
- ****************************************************************************/
-#define XEMACPS_VIRT_TO_PHYS(BdPtr) \
- ((UINTPTR)(BdPtr) - (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr))
-
-/****************************************************************************
- * Move the BdPtr argument ahead an arbitrary number of BDs wrapping around
- * to the beginning of the ring if needed.
- *
- * We know if a wrapaound should occur if the new BdPtr is greater than
- * the high address in the ring OR if the new BdPtr crosses over the
- * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not
- * allow a BD space to span this boundary.
- *
- * @param RingPtr is the ring BdPtr appears in
- * @param BdPtr on input is the starting BD position and on output is the
- * final BD position
- * @param NumBd is the number of BD spaces to increment
- *
- ****************************************************************************/
-#define XEMACPS_RING_SEEKAHEAD(RingPtr, BdPtr, NumBd) \
- { \
- UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \
- \
- Addr += ((RingPtr)->Separation * (NumBd)); \
- if ((Addr > (RingPtr)->HighBdAddr) || ((UINTPTR)(void *)(BdPtr) > Addr)) \
- { \
- Addr -= (RingPtr)->Length; \
- } \
- \
- (BdPtr) = (XEmacPs_Bd*)(void *)Addr; \
- }
-
-/****************************************************************************
- * Move the BdPtr argument backwards an arbitrary number of BDs wrapping
- * around to the end of the ring if needed.
- *
- * We know if a wrapaound should occur if the new BdPtr is less than
- * the base address in the ring OR if the new BdPtr crosses over the
- * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not
- * allow a BD space to span this boundary.
- *
- * @param RingPtr is the ring BdPtr appears in
- * @param BdPtr on input is the starting BD position and on output is the
- * final BD position
- * @param NumBd is the number of BD spaces to increment
- *
- ****************************************************************************/
-#define XEMACPS_RING_SEEKBACK(RingPtr, BdPtr, NumBd) \
- { \
- UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \
- \
- Addr -= ((RingPtr)->Separation * (NumBd)); \
- if ((Addr < (RingPtr)->BaseBdAddr) || ((UINTPTR)(void*)(BdPtr) < Addr)) \
- { \
- Addr += (RingPtr)->Length; \
- } \
- \
- (BdPtr) = (XEmacPs_Bd*)(void*)Addr; \
- }
-
-
-/************************** Function Prototypes ******************************/
-
-static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr);
-static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr);
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
- * Using a memory segment allocated by the caller, create and setup the BD list
- * for the given DMA channel.
- *
- * @param RingPtr is the instance to be worked on.
- * @param PhysAddr is the physical base address of user memory region.
- * @param VirtAddr is the virtual base address of the user memory region. If
- * address translation is not being utilized, then VirtAddr should be
- * equivalent to PhysAddr.
- * @param Alignment governs the byte alignment of individual BDs. This function
- * will enforce a minimum alignment of 4 bytes with no maximum as long
- * as it is specified as a power of 2.
- * @param BdCount is the number of BDs to setup in the user memory region. It
- * is assumed the region is large enough to contain the BDs.
- *
- * @return
- *
- * - XST_SUCCESS if initialization was successful
- * - XST_NO_FEATURE if the provided instance is a non DMA type
- * channel.
- * - XST_INVALID_PARAM under any of the following conditions:
- * 1) PhysAddr and/or VirtAddr are not aligned to the given Alignment
- * parameter.
- * 2) Alignment parameter does not meet minimum requirements or is not a
- * power of 2 value.
- * 3) BdCount is 0.
- * - XST_DMA_SG_LIST_ERROR if the memory segment containing the list spans
- * over address 0x00000000 in virtual address space.
- *
- * @note
- * Make sure to pass in the right alignment value.
- *****************************************************************************/
-LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
- UINTPTR VirtAddr, u32 Alignment, u32 BdCount)
-{
- u32 i;
- UINTPTR BdVirtAddr;
- UINTPTR BdPhyAddr;
- UINTPTR VirtAddrLoc = VirtAddr;
-
- /* In case there is a failure prior to creating list, make sure the
- * following attributes are 0 to prevent calls to other functions
- * from doing anything.
- */
- RingPtr->AllCnt = 0U;
- RingPtr->FreeCnt = 0U;
- RingPtr->HwCnt = 0U;
- RingPtr->PreCnt = 0U;
- RingPtr->PostCnt = 0U;
-
- /* Make sure Alignment parameter meets minimum requirements */
- if (Alignment < (u32)XEMACPS_DMABD_MINIMUM_ALIGNMENT) {
- return (LONG)(XST_INVALID_PARAM);
- }
-
- /* Make sure Alignment is a power of 2 */
- if (((Alignment - 0x00000001U) & Alignment)!=0x00000000U) {
- return (LONG)(XST_INVALID_PARAM);
- }
-
- /* Make sure PhysAddr and VirtAddr are on same Alignment */
- if (((PhysAddr % Alignment)!=(u32)0) || ((VirtAddrLoc % Alignment)!=(u32)0)) {
- return (LONG)(XST_INVALID_PARAM);
- }
-
- /* Is BdCount reasonable? */
- if (BdCount == 0x00000000U) {
- return (LONG)(XST_INVALID_PARAM);
- }
-
- /* Figure out how many bytes will be between the start of adjacent BDs */
- RingPtr->Separation = ((u32)sizeof(XEmacPs_Bd));
-
- /* Must make sure the ring doesn't span address 0x00000000. If it does,
- * then the next/prev BD traversal macros will fail.
- */
- if (VirtAddrLoc > ((VirtAddrLoc + (RingPtr->Separation * BdCount)) - (u32)1)) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- /* Initial ring setup:
- * - Clear the entire space
- * - Setup each BD's BDA field with the physical address of the next BD
- */
- (void)memset((void *) VirtAddrLoc, 0, (RingPtr->Separation * BdCount));
-
- BdVirtAddr = VirtAddrLoc;
- BdPhyAddr = PhysAddr + RingPtr->Separation;
- for (i = 1U; i < BdCount; i++) {
- BdVirtAddr += RingPtr->Separation;
- BdPhyAddr += RingPtr->Separation;
- }
-
- /* Setup and initialize pointers and counters */
- RingPtr->RunState = (u32)(XST_DMA_SG_IS_STOPPED);
- RingPtr->BaseBdAddr = VirtAddrLoc;
- RingPtr->PhysBaseAddr = PhysAddr;
- RingPtr->HighBdAddr = BdVirtAddr;
- RingPtr->Length =
- ((RingPtr->HighBdAddr - RingPtr->BaseBdAddr) + RingPtr->Separation);
- RingPtr->AllCnt = (u32)BdCount;
- RingPtr->FreeCnt = (u32)BdCount;
- RingPtr->FreeHead = (XEmacPs_Bd *)(void *)VirtAddrLoc;
- RingPtr->PreHead = (XEmacPs_Bd *)VirtAddrLoc;
- RingPtr->HwHead = (XEmacPs_Bd *)VirtAddrLoc;
- RingPtr->HwTail = (XEmacPs_Bd *)VirtAddrLoc;
- RingPtr->PostHead = (XEmacPs_Bd *)VirtAddrLoc;
- RingPtr->BdaRestart = (XEmacPs_Bd *)(void *)PhysAddr;
-
- return (LONG)(XST_SUCCESS);
-}
-
-
-/*****************************************************************************/
-/**
- * Clone the given BD into every BD in the list.
- * every field of the source BD is replicated in every BD of the list.
- *
- * This function can be called only when all BDs are in the free group such as
- * they are immediately after initialization with XEmacPs_BdRingCreate().
- * This prevents modification of BDs while they are in use by hardware or the
- * user.
- *
- * @param RingPtr is the pointer of BD ring instance to be worked on.
- * @param SrcBdPtr is the source BD template to be cloned into the list. This
- * BD will be modified.
- * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
- * which direction.
- *
- * @return
- * - XST_SUCCESS if the list was modified.
- * - XST_DMA_SG_NO_LIST if a list has not been created.
- * - XST_DMA_SG_LIST_ERROR if some of the BDs in this channel are under
- * hardware or user control.
- * - XST_DEVICE_IS_STARTED if the DMA channel has not been stopped.
- *
- *****************************************************************************/
-LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
- u8 Direction)
-{
- u32 i;
- UINTPTR CurBd;
-
- /* Can't do this function if there isn't a ring */
- if (RingPtr->AllCnt == 0x00000000U) {
- return (LONG)(XST_DMA_SG_NO_LIST);
- }
-
- /* Can't do this function with the channel running */
- if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
- return (LONG)(XST_DEVICE_IS_STARTED);
- }
-
- /* Can't do this function with some of the BDs in use */
- if (RingPtr->FreeCnt != RingPtr->AllCnt) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
- return (LONG)(XST_INVALID_PARAM);
- }
-
- /* Starting from the top of the ring, save BD.Next, overwrite the entire
- * BD with the template, then restore BD.Next
- */
- CurBd = RingPtr->BaseBdAddr;
- for (i = 0U; i < RingPtr->AllCnt; i++) {
- memcpy((void *)CurBd, SrcBdPtr, sizeof(XEmacPs_Bd));
- CurBd += RingPtr->Separation;
- }
-
- CurBd -= RingPtr->Separation;
-
- if (Direction == XEMACPS_RECV) {
- XEmacPs_BdSetRxWrap(CurBd);
- }
- else {
- XEmacPs_BdSetTxWrap(CurBd);
- }
-
- return (LONG)(XST_SUCCESS);
-}
-
-
-/*****************************************************************************/
-/**
- * Reserve locations in the BD list. The set of returned BDs may be modified
- * in preparation for future DMA transaction(s). Once the BDs are ready to be
- * submitted to hardware, the user must call XEmacPs_BdRingToHw() in the same
- * order which they were allocated here. Example:
- *
- *
- * NumBd = 2,
- * Status = XEmacPs_BdRingAlloc(MyRingPtr, NumBd, &MyBdSet),
- *
- * if (Status != XST_SUCCESS)
- * {
- * *Not enough BDs available for the request*
- * }
- *
- * CurBd = MyBdSet,
- * for (i=0; i
- *
- * A more advanced use of this function may allocate multiple sets of BDs.
- * They must be allocated and given to hardware in the correct sequence:
- *
- *
- * Use the API defined in xemacps_bd.h to modify individual BDs. Traversal
- * of the BD set can be done using XEmacPs_BdRingNext() and
- * XEmacPs_BdRingPrev().
- *
- * @param RingPtr is a pointer to the BD ring instance to be worked on.
- * @param NumBd is the number of BDs to allocate
- * @param BdSetPtr is an output parameter, it points to the first BD available
- * for modification.
- *
- * @return
- * - XST_SUCCESS if the requested number of BDs was returned in the BdSetPtr
- * parameter.
- * - XST_FAILURE if there were not enough free BDs to satisfy the request.
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- * call that modifies the BD space. It is the caller's responsibility to
- * provide a mutual exclusion mechanism.
- *
- * @note Do not modify more BDs than the number requested with the NumBd
- * parameter. Doing so will lead to data corruption and system
- * instability.
- *
- *****************************************************************************/
-LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd ** BdSetPtr)
-{
- LONG Status;
- /* Enough free BDs available for the request? */
- if (RingPtr->FreeCnt < NumBd) {
- Status = (LONG)(XST_FAILURE);
- } else {
- /* Set the return argument and move FreeHead forward */
- *BdSetPtr = RingPtr->FreeHead;
- XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->FreeHead, NumBd);
- RingPtr->FreeCnt -= NumBd;
- RingPtr->PreCnt += NumBd;
- Status = (LONG)(XST_SUCCESS);
- }
- return Status;
-}
-
-/*****************************************************************************/
-/**
- * Fully or partially undo an XEmacPs_BdRingAlloc() operation. Use this
- * function if all the BDs allocated by XEmacPs_BdRingAlloc() could not be
- * transferred to hardware with XEmacPs_BdRingToHw().
- *
- * This function helps out in situations when an unrelated error occurs after
- * BDs have been allocated but before they have been given to hardware.
- * An example of this type of error would be an OS running out of resources.
- *
- * This function is not the same as XEmacPs_BdRingFree(). The Free function
- * returns BDs to the free list after they have been processed by hardware,
- * while UnAlloc returns them before being processed by hardware.
- *
- * There are two scenarios where this function can be used. Full UnAlloc or
- * Partial UnAlloc. A Full UnAlloc means all the BDs Alloc'd will be returned:
- *
- *
- * Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
- * ...
- * if (Error)
- * {
- * Status = XEmacPs_BdRingUnAlloc(MyRingPtr, 10, &BdPtr),
- * }
- *
- *
- * A partial UnAlloc means some of the BDs Alloc'd will be returned:
- *
- *
- *
- * A partial UnAlloc must include the last BD in the list that was Alloc'd.
- *
- * @param RingPtr is a pointer to the instance to be worked on.
- * @param NumBd is the number of BDs to allocate
- * @param BdSetPtr is an output parameter, it points to the first BD available
- * for modification.
- *
- * @return
- * - XST_SUCCESS if the BDs were unallocated.
- * - XST_FAILURE if NumBd parameter was greater that the number of BDs in
- * the preprocessing state.
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- * call that modifies the BD space. It is the caller's responsibility to
- * provide a mutual exclusion mechanism.
- *
- *****************************************************************************/
-LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr)
-{
- LONG Status;
- (void) BdSetPtr;
- Xil_AssertNonvoid(RingPtr != NULL);
- Xil_AssertNonvoid(BdSetPtr != NULL);
-
- /* Enough BDs in the free state for the request? */
- if (RingPtr->PreCnt < NumBd) {
- Status = (LONG)(XST_FAILURE);
- } else {
- /* Set the return argument and move FreeHead backward */
- XEMACPS_RING_SEEKBACK(RingPtr, (RingPtr->FreeHead), NumBd);
- RingPtr->FreeCnt += NumBd;
- RingPtr->PreCnt -= NumBd;
- Status = (LONG)(XST_SUCCESS);
- }
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Enqueue a set of BDs to hardware that were previously allocated by
- * XEmacPs_BdRingAlloc(). Once this function returns, the argument BD set goes
- * under hardware control. Any changes made to these BDs after this point will
- * corrupt the BD list leading to data corruption and system instability.
- *
- * The set will be rejected if the last BD of the set does not mark the end of
- * a packet (see XEmacPs_BdSetLast()).
- *
- * @param RingPtr is a pointer to the instance to be worked on.
- * @param NumBd is the number of BDs in the set.
- * @param BdSetPtr is the first BD of the set to commit to hardware.
- *
- * @return
- * - XST_SUCCESS if the set of BDs was accepted and enqueued to hardware.
- * - XST_FAILURE if the set of BDs was rejected because the last BD of the set
- * did not have its "last" bit set.
- * - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
- * XEmacPs_BdRingAlloc().
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- * call that modifies the BD space. It is the caller's responsibility to
- * provide a mutual exclusion mechanism.
- *
- *****************************************************************************/
-LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr)
-{
- XEmacPs_Bd *CurBdPtr;
- u32 i;
- LONG Status;
- /* if no bds to process, simply return. */
- if (0U == NumBd){
- Status = (LONG)(XST_SUCCESS);
- } else {
- /* Make sure we are in sync with XEmacPs_BdRingAlloc() */
- if ((RingPtr->PreCnt < NumBd) || (RingPtr->PreHead != BdSetPtr)) {
- Status = (LONG)(XST_DMA_SG_LIST_ERROR);
- } else {
- CurBdPtr = BdSetPtr;
- for (i = 0U; i < NumBd; i++) {
- CurBdPtr = (XEmacPs_Bd *)((void *)XEmacPs_BdRingNext(RingPtr, CurBdPtr));
- }
- /* Adjust ring pointers & counters */
- XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PreHead, NumBd);
- RingPtr->PreCnt -= NumBd;
- RingPtr->HwTail = CurBdPtr;
- RingPtr->HwCnt += NumBd;
-
- Status = (LONG)(XST_SUCCESS);
- }
- }
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Returns a set of BD(s) that have been processed by hardware. The returned
- * BDs may be examined to determine the outcome of the DMA transaction(s).
- * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
- * in the same order which they were retrieved here. Example:
- *
- *
- * NumBd = XEmacPs_BdRingFromHwTx(MyRingPtr, MaxBd, &MyBdSet),
- * if (NumBd == 0)
- * {
- * * hardware has nothing ready for us yet*
- * }
- *
- * CurBd = MyBdSet,
- * for (i=0; i
- *
- * A more advanced use of this function may allocate multiple sets of BDs.
- * They must be retrieved from hardware and freed in the correct sequence:
- *
- *
- * If hardware has only partially completed a packet spanning multiple BDs,
- * then none of the BDs for that packet will be included in the results.
- *
- * @param RingPtr is a pointer to the instance to be worked on.
- * @param BdLimit is the maximum number of BDs to return in the set.
- * @param BdSetPtr is an output parameter, it points to the first BD available
- * for examination.
- *
- * @return
- * The number of BDs processed by hardware. A value of 0 indicates that no
- * data is available. No more than BdLimit BDs will be returned.
- *
- * @note Treat BDs returned by this function as read-only.
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- * call that modifies the BD space. It is the caller's responsibility to
- * provide a mutual exclusion mechanism.
- *
- *****************************************************************************/
-u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
- XEmacPs_Bd ** BdSetPtr)
-{
- XEmacPs_Bd *CurBdPtr;
- u32 BdStr = 0U;
- u32 BdCount;
- u32 BdPartialCount;
- u32 Sop = 0U;
- u32 Status;
- u32 BdLimitLoc = BdLimit;
- CurBdPtr = RingPtr->HwHead;
- BdCount = 0U;
- BdPartialCount = 0U;
-
- /* If no BDs in work group, then there's nothing to search */
- if (RingPtr->HwCnt == 0x00000000U) {
- *BdSetPtr = NULL;
- Status = 0U;
- } else {
-
- if (BdLimitLoc > RingPtr->HwCnt){
- BdLimitLoc = RingPtr->HwCnt;
- }
- /* Starting at HwHead, keep moving forward in the list until:
- * - A BD is encountered with its new/used bit set which means
- * hardware has not completed processing of that BD.
- * - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
- * - The number of requested BDs has been processed
- */
- while (BdCount < BdLimitLoc) {
- /* Read the status */
- if(CurBdPtr != NULL){
- BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
- }
-
- if ((Sop == 0x00000000U) && ((BdStr & XEMACPS_TXBUF_USED_MASK)!=0x00000000U)){
- Sop = 1U;
- }
- if (Sop == 0x00000001U) {
- BdCount++;
- BdPartialCount++;
- }
-
- /* hardware has processed this BD so check the "last" bit.
- * If it is clear, then there are more BDs for the current
- * packet. Keep a count of these partial packet BDs.
- */
- if ((Sop == 0x00000001U) && ((BdStr & XEMACPS_TXBUF_LAST_MASK)!=0x00000000U)) {
- Sop = 0U;
- BdPartialCount = 0U;
- }
-
- /* Move on to next BD in work group */
- CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
- }
-
- /* Subtract off any partial packet BDs found */
- BdCount -= BdPartialCount;
-
- /* If BdCount is non-zero then BDs were found to return. Set return
- * parameters, update pointers and counters, return success
- */
- if (BdCount > 0x00000000U) {
- *BdSetPtr = RingPtr->HwHead;
- RingPtr->HwCnt -= BdCount;
- RingPtr->PostCnt += BdCount;
- XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
- Status = (BdCount);
- } else {
- *BdSetPtr = NULL;
- Status = 0U;
- }
- }
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Returns a set of BD(s) that have been processed by hardware. The returned
- * BDs may be examined to determine the outcome of the DMA transaction(s).
- * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
- * in the same order which they were retrieved here. Example:
- *
- *
- * NumBd = XEmacPs_BdRingFromHwRx(MyRingPtr, MaxBd, &MyBdSet),
- *
- * if (NumBd == 0)
- * {
- * *hardware has nothing ready for us yet*
- * }
- *
- * CurBd = MyBdSet,
- * for (i=0; i
- *
- * A more advanced use of this function may allocate multiple sets of BDs.
- * They must be retrieved from hardware and freed in the correct sequence:
- *
- *
- * If hardware has only partially completed a packet spanning multiple BDs,
- * then none of the BDs for that packet will be included in the results.
- *
- * @param RingPtr is a pointer to the instance to be worked on.
- * @param BdLimit is the maximum number of BDs to return in the set.
- * @param BdSetPtr is an output parameter, it points to the first BD available
- * for examination.
- *
- * @return
- * The number of BDs processed by hardware. A value of 0 indicates that no
- * data is available. No more than BdLimit BDs will be returned.
- *
- * @note Treat BDs returned by this function as read-only.
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- * call that modifies the BD space. It is the caller's responsibility to
- * provide a mutual exclusion mechanism.
- *
- *****************************************************************************/
-u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
- XEmacPs_Bd ** BdSetPtr)
-{
- XEmacPs_Bd *CurBdPtr;
- u32 BdStr = 0U;
- u32 BdCount;
- u32 BdPartialCount;
- u32 Status;
-
- CurBdPtr = RingPtr->HwHead;
- BdCount = 0U;
- BdPartialCount = 0U;
-
- /* If no BDs in work group, then there's nothing to search */
- if (RingPtr->HwCnt == 0x00000000U) {
- *BdSetPtr = NULL;
- Status = 0U;
- } else {
-
- /* Starting at HwHead, keep moving forward in the list until:
- * - A BD is encountered with its new/used bit set which means
- * hardware has completed processing of that BD.
- * - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
- * - The number of requested BDs has been processed
- */
- while (BdCount < BdLimit) {
-
- /* Read the status */
- if(CurBdPtr!=NULL){
- BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
- }
- if ((!(XEmacPs_BdIsRxNew(CurBdPtr)))==TRUE) {
- break;
- }
-
- BdCount++;
-
- /* hardware has processed this BD so check the "last" bit. If
- * it is clear, then there are more BDs for the current packet.
- * Keep a count of these partial packet BDs.
- */
- if ((BdStr & XEMACPS_RXBUF_EOF_MASK)!=0x00000000U) {
- BdPartialCount = 0U;
- } else {
- BdPartialCount++;
- }
-
- /* Move on to next BD in work group */
- CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
- }
-
- /* Subtract off any partial packet BDs found */
- BdCount -= BdPartialCount;
-
- /* If BdCount is non-zero then BDs were found to return. Set return
- * parameters, update pointers and counters, return success
- */
- if (BdCount > 0x00000000U) {
- *BdSetPtr = RingPtr->HwHead;
- RingPtr->HwCnt -= BdCount;
- RingPtr->PostCnt += BdCount;
- XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
- Status = (BdCount);
- }
- else {
- *BdSetPtr = NULL;
- Status = 0U;
- }
-}
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Frees a set of BDs that had been previously retrieved with
- * XEmacPs_BdRingFromHw().
- *
- * @param RingPtr is a pointer to the instance to be worked on.
- * @param NumBd is the number of BDs to free.
- * @param BdSetPtr is the head of a list of BDs returned by
- * XEmacPs_BdRingFromHw().
- *
- * @return
- * - XST_SUCCESS if the set of BDs was freed.
- * - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
- * XEmacPs_BdRingFromHw().
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- * call that modifies the BD space. It is the caller's responsibility to
- * provide a mutual exclusion mechanism.
- *
- *****************************************************************************/
-LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr)
-{
- LONG Status;
- /* if no bds to process, simply return. */
- if (0x00000000U == NumBd){
- Status = (LONG)(XST_SUCCESS);
- } else {
- /* Make sure we are in sync with XEmacPs_BdRingFromHw() */
- if ((RingPtr->PostCnt < NumBd) || (RingPtr->PostHead != BdSetPtr)) {
- Status = (LONG)(XST_DMA_SG_LIST_ERROR);
- } else {
- /* Update pointers and counters */
- RingPtr->FreeCnt += NumBd;
- RingPtr->PostCnt -= NumBd;
- XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PostHead, NumBd);
- Status = (LONG)(XST_SUCCESS);
- }
- }
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Check the internal data structures of the BD ring for the provided channel.
- * The following checks are made:
- *
- * - Is the BD ring linked correctly in physical address space.
- * - Do the internal pointers point to BDs in the ring.
- * - Do the internal counters add up.
- *
- * The channel should be stopped prior to calling this function.
- *
- * @param RingPtr is a pointer to the instance to be worked on.
- * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
- * which direction.
- *
- * @return
- * - XST_SUCCESS if the set of BDs was freed.
- * - XST_DMA_SG_NO_LIST if the list has not been created.
- * - XST_IS_STARTED if the channel is not stopped.
- * - XST_DMA_SG_LIST_ERROR if a problem is found with the internal data
- * structures. If this value is returned, the channel should be reset to
- * avoid data corruption or system instability.
- *
- * @note This function should not be preempted by another XEmacPs_Bd function
- * call that modifies the BD space. It is the caller's responsibility to
- * provide a mutual exclusion mechanism.
- *
- *****************************************************************************/
-LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction)
-{
- UINTPTR AddrV, AddrP;
- u32 i;
-
- if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
- return (LONG)(XST_INVALID_PARAM);
- }
-
- /* Is the list created */
- if (RingPtr->AllCnt == 0x00000000U) {
- return (LONG)(XST_DMA_SG_NO_LIST);
- }
-
- /* Can't check if channel is running */
- if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
- return (LONG)(XST_IS_STARTED);
- }
-
- /* RunState doesn't make sense */
- if (RingPtr->RunState != (u32)XST_DMA_SG_IS_STOPPED) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- /* Verify internal pointers point to correct memory space */
- AddrV = (UINTPTR) RingPtr->FreeHead;
- if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- AddrV = (UINTPTR) RingPtr->PreHead;
- if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- AddrV = (UINTPTR) RingPtr->HwHead;
- if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- AddrV = (UINTPTR) RingPtr->HwTail;
- if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- AddrV = (UINTPTR) RingPtr->PostHead;
- if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- /* Verify internal counters add up */
- if ((RingPtr->HwCnt + RingPtr->PreCnt + RingPtr->FreeCnt +
- RingPtr->PostCnt) != RingPtr->AllCnt) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- /* Verify BDs are linked correctly */
- AddrV = RingPtr->BaseBdAddr;
- AddrP = RingPtr->PhysBaseAddr + RingPtr->Separation;
-
- for (i = 1U; i < RingPtr->AllCnt; i++) {
- /* Check BDA for this BD. It should point to next physical addr */
- if (XEmacPs_BdRead(AddrV, XEMACPS_BD_ADDR_OFFSET) != AddrP) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
-
- /* Move on to next BD */
- AddrV += RingPtr->Separation;
- AddrP += RingPtr->Separation;
- }
-
- /* Last BD should have wrap bit set */
- if (XEMACPS_SEND == Direction) {
- if ((!XEmacPs_BdIsTxWrap(AddrV))==TRUE) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
- }
- else { /* XEMACPS_RECV */
- if ((!XEmacPs_BdIsRxWrap(AddrV))==TRUE) {
- return (LONG)(XST_DMA_SG_LIST_ERROR);
- }
- }
-
- /* No problems found */
- return (LONG)(XST_SUCCESS);
-}
-
-/*****************************************************************************/
-/**
- * Set this bit to mark the last descriptor in the receive buffer descriptor
- * list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr)
-{
- u32 DataValueRx;
- u32 *TempPtr;
-
- BdPtr += (u32)(XEMACPS_BD_ADDR_OFFSET);
- TempPtr = (u32 *)BdPtr;
- if(TempPtr != NULL) {
- DataValueRx = *TempPtr;
- DataValueRx |= XEMACPS_RXBUF_WRAP_MASK;
- *TempPtr = DataValueRx;
- }
-}
-
-/*****************************************************************************/
-/**
- * Sets this bit to mark the last descriptor in the transmit buffer
- * descriptor list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr)
-{
- u32 DataValueTx;
- u32 *TempPtr;
-
- BdPtr += (u32)(XEMACPS_BD_STAT_OFFSET);
- TempPtr = (u32 *)BdPtr;
- if(TempPtr != NULL) {
- DataValueTx = *TempPtr;
- DataValueTx |= XEMACPS_TXBUF_WRAP_MASK;
- *TempPtr = DataValueTx;
- }
-}
-
-/*****************************************************************************/
-/**
- * Reset BD ring head and tail pointers.
- *
- * @param RingPtr is the instance to be worked on.
- * @param virtaddrloc is the virtual base address of the user memory region.
- *
- * @note
- * Should be called after XEmacPs_Stop()
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc)
- *
- *****************************************************************************/
-void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc)
-{
- RingPtr->FreeHead = virtaddrloc;
- RingPtr->PreHead = virtaddrloc;
- RingPtr->HwHead = virtaddrloc;
- RingPtr->HwTail = virtaddrloc;
- RingPtr->PostHead = virtaddrloc;
-}
-
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a0/503cf7515243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a0/503cf7515243001d18b399c1eb9b3628
deleted file mode 100644
index 261e808..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a0/503cf7515243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,342 +0,0 @@
-
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diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a0/809e8c525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a0/809e8c525243001d18b399c1eb9b3628
deleted file mode 100644
index 99b1375..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a0/809e8c525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,113 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xbasic_types.h
-*
-*
-* @note Dummy File for backwards compatibility
-*
-
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
-* 7.0 aru 01/21/19 Modified the typedef of u32,u16,u8
-* 7.0 aru 02/06/19 Included stdint.h and stddef.h
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
-#define XBASIC_TYPES_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include
-#include
-
-/** @name Legacy types
- * Deprecated legacy types.
- * @{
- */
-typedef uint8_t Xuint8; /**< unsigned 8-bit */
-typedef char Xint8; /**< signed 8-bit */
-typedef uint16_t Xuint16; /**< unsigned 16-bit */
-typedef short Xint16; /**< signed 16-bit */
-typedef uint32_t Xuint32; /**< unsigned 32-bit */
-typedef long Xint32; /**< signed 32-bit */
-typedef float Xfloat32; /**< 32-bit floating point */
-typedef double Xfloat64; /**< 64-bit double precision FP */
-typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
-
-#if !defined __XUINT64__
-typedef struct
-{
- Xuint32 Upper;
- Xuint32 Lower;
-} Xuint64;
-#endif
-
-/** @name New types
- * New simple types.
- * @{
- */
-#ifndef __KERNEL__
-#ifndef XIL_TYPES_H
-typedef Xuint32 u32;
-typedef Xuint16 u16;
-typedef Xuint8 u8;
-#endif
-#else
-#include
-#endif
-
-#ifndef TRUE
-# define TRUE 1U
-#endif
-
-#ifndef FALSE
-# define FALSE 0U
-#endif
-
-#ifndef NULL
-#define NULL 0U
-#endif
-
-/*
- * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
- * Please use NULL, TRUE and FALSE
- */
-#define XNULL NULL
-#define XTRUE TRUE
-#define XFALSE FALSE
-
-/*
- * This file is deprecated and users
- * should use xil_types.h and xil_assert.h\n\r
- */
-#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
-#warning Please refer the Standalone BSP UG647 for further details
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a0/a041c9575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a0/a041c9575243001d18b399c1eb9b3628
deleted file mode 100644
index be5fccb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a0/a041c9575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,41 +0,0 @@
-DRIVER_LIB_VERSION = 1.0
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I$(INCLUDEDIR)
-
-INCLUDEFILES:=*.h
-
-SRCFILES:=$(wildcard *.c)
-
-OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
-
-libs: $(OBJECTS)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf $(DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a0/b032ea535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a0/b032ea535243001d18b399c1eb9b3628
deleted file mode 100644
index 9d17f5c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a0/b032ea535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,86 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xtime_l.h
-* @addtogroup a9_time_apis Cortex A9 Time Functions
-*
-* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This
-* counter increases by one at every two processor cycles. These functions can
-* be used to get/set time in the global timer.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 1.00a rp/sdm 11/03/09 Initial release.
-* 3.06a sgd 05/15/12 Updated get/set time functions to make use Global Timer
-* 3.06a asa 06/17/12 Reverted back the changes to make use Global Timer.
-* 3.07a sgd 07/05/12 Updated get/set time functions to make use Global Timer
-* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep
-* implementation
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
-* displaying same warnings multiple times. It fixes CR#1090562.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------
-* 1.00 kvn 02/14/15 First release
-* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
-* kvn 08/18/15 Modified Makefile according to compiler changes.
-* 1.2 kvn 10/09/15 Add support for IAR Compiler.
-* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
-* for MB BSPs. Instead it throws up a warning. This
-* fixes the CR#953056.
-* 1.5 sne 01/19/19 Fixed MISRA-C Violations CR#1025101.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#ifdef __MICROBLAZE__
-#warning "The driver is supported only for ARM architecture"
-#else
-
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#include "xcoresightpsdcc.h"
-
-#ifdef __ICCARM__
-#define INLINE
-#else
-#define INLINE __inline
-#endif
-
-/* DCC Status Bits */
-#define XCORESIGHTPS_DCC_STATUS_RX (1 << 30)
-#define XCORESIGHTPS_DCC_STATUS_TX (1 << 29)
-
-static INLINE u32 XCoresightPs_DccGetStatus(void);
-
-/****************************************************************************/
-/**
-*
-* This functions sends a single byte using the DCC. It is blocking in that it
-* waits for the transmitter to become non-full before it writes the byte to
-* the transmit register.
-*
-* @param BaseAddress is a dummy parameter to match the function proto
-* of functions for other stdio devices.
-* @param Data is the byte of data to send
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data)
-{
- (void) BaseAddress;
- while (XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_TX)
- {dsb();}
-#ifdef __aarch64__
- asm volatile ("msr dbgdtrtx_el0, %0" : : "r" (Data));
-#elif defined (__GNUC__) || defined (__ICCARM__)
- asm volatile("mcr p14, 0, %0, c0, c5, 0"
- : : "r" (Data));
-#else
- {
- volatile register u32 Reg __asm("cp14:0:c0:c5:0");
- Reg = Data;
- }
-#endif
- isb();
-
-}
-
-/****************************************************************************/
-/**
-*
-* This functions receives a single byte using the DCC. It is blocking in that
-* it waits for the receiver to become non-empty before it reads from the
-* receive register.
-*
-* @param BaseAddress is a dummy parameter to match the function proto
-* of functions for other stdio devices.
-*
-* @return The byte of data received.
-*
-* @note None.
-*
-******************************************************************************/
-u8 XCoresightPs_DccRecvByte(u32 BaseAddress)
-{
- u8 Data = 0U;
- (void) BaseAddress;
-
- while (!(XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_RX))
- {dsb();}
-
-#ifdef __aarch64__
- asm volatile ("mrs %0, dbgdtrrx_el0" : "=r" (Data));
-#elif defined (__GNUC__) || defined (__ICCARM__)
- asm volatile("mrc p14, 0, %0, c0, c5, 0"
- : "=r" (Data));
-#else
- {
- volatile register u32 Reg __asm("cp14:0:c0:c5:0");
- Data = Reg;
- }
-#endif
- isb();
-
- return Data;
-}
-
-
-/****************************************************************************/
-/**INLINE
-*
-* This functions read the status register of the DCC.
-*
-* @param BaseAddress is the base address of the device
-*
-* @return The contents of the Status Register.
-*
-* @note None.
-*
-******************************************************************************/
-static INLINE u32 XCoresightPs_DccGetStatus(void)
-{
- u32 Status = 0U;
-
-#ifdef __aarch64__
- asm volatile ("mrs %0, mdccsr_el0" : "=r" (Status));
-#elif defined (__GNUC__) || defined (__ICCARM__)
- asm volatile("mrc p14, 0, %0, c0, c1, 0"
- : "=r" (Status) : : "cc");
-#else
- {
- volatile register u32 Reg __asm("cp14:0:c0:c1:0");
- Status = Reg;
- }
-#endif
- return Status;
-}
-#endif
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a1/b286c4575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a1/b286c4575243001d18b399c1eb9b3628
deleted file mode 100644
index 1b7d881..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a1/b286c4575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,369 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xdevcfg_hw.h
-* @addtogroup devcfg_v3_7
-* @{
-*
-* This file contains the hardware interface to the Device Config Interface.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.01a nm 08/01/12 Added defines for the PS Version bits,
-* removed the FIFO Flush bits from the
-* Miscellaneous Control Reg
-* 2.03a nm 04/19/13 Fixed CR# 703728.
-* Updated the register definitions as per the latest TRM
-* version UG585 (v1.4) November 16, 2012.
-* 2.04a kpc 10/07/13 Added function prototype.
-* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
-*
-*
-******************************************************************************/
-#ifndef XDCFG_HW_H /* prevent circular inclusions */
-#define XDCFG_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- * Offsets of registers from the start of the device
- * @{
- */
-
-#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */
-#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */
-#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */
-#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */
-#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */
-#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */
-#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */
-#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */
-#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */
-#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */
-#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */
-#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */
-#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */
-#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */
-#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */
-
-/* @} */
-
-/** @name Control Register Bit definitions
- * @{
- */
-
-#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into
- * Secure Reset
- */
-#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to
- * Reset FPGA
- */
-#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */
-#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */
-#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */
-#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data
- * to FPGA every 4 PCAP
- * cycles
- */
-#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */
-#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */
-#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */
-#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */
-#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */
-#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */
-#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure
- * Status mask
- */
-#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive
- * Debug Enable
- */
-#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive
- * Debug Enable
- */
-#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug
- * Enable
- */
-#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug
- * Enable
- */
-#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */
-
-/* @} */
-
-/** @name Lock register bit definitions
- * @{
- */
-
-#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */
-#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */
-#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */
-#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and
- * USER_MODE
- */
-#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks
- * security config
- * including: DAP_En,
- * DBGEN,,
- * NIDEN, SPNIEN
- */
-/*@}*/
-
-
-
-/** @name Config Register Bit definitions
- * @{
- */
-#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO
- * Threshold Mask
- */
-#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold
- * Mask
- */
-#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active
- * clock edge
- */
-#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active
- * clock edge
- */
-#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address
- * increment mask
- */
-#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination
- * address increment
- * mask
- */
-/* @} */
-
-
-/** @name Interrupt Status/Mask Register Bit definitions
- * @{
- */
-#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during
- * HIZ
- */
-#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration
- * done
- */
-#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */
-#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during
- * configuration
- */
-#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration
- * reset
- */
-#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address
- * or Data or response
- * timeout
- */
-#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response
- * error
- */
-#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or
- * response timeout
- */
-#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response
- * error
- */
-#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */
-#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than
- * threshold */
-#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than
- * threshold */
-#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */
-#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue
- * overflow
- */
-#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */
-#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP
- * transfers Done
- */
-#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer
- * length error
- */
-#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */
-#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */
-#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */
-#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */
-#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */
-#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge
- * of Init Signal
- */
-#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge
- * of Init Signal
- */
-#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \
- XDCFG_IXR_AXI_WERR_MASK | \
- XDCFG_IXR_AXI_RTO_MASK | \
- XDCFG_IXR_AXI_RERR_MASK | \
- XDCFG_IXR_RX_FIFO_OV_MASK | \
- XDCFG_IXR_DMA_CMD_ERR_MASK |\
- XDCFG_IXR_DMA_Q_OV_MASK | \
- XDCFG_IXR_P2D_LEN_ERR_MASK |\
- XDCFG_IXR_PCFG_HMAC_ERR_MASK)
-
-
-#define XDCFG_IXR_ALL_MASK 0x00F7F8EF
-
-
-
-/* @} */
-
-
-/** @name Status Register Bit definitions
- * @{
- */
-#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command
- * Queue full
- */
-#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command
- * Queue empty
- */
-#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of
- * completed DMA
- * transfers
- */
-#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */
-#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */
-
-#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO
- * during HIZ
- */
-#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config
- * done
- */
-#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */
-#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during
- * config
- */
-#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset
- * POR Status
- */
-#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB
- * access
- */
-#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config
- * reset status
- */
-#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init
- * Status
- */
-#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008
- /**< BBRAM key
- * disable
- */
-#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security
- * Enable Status
- */
-#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG
- * Disable
- * status
- */
-/* @} */
-
-
-/** @name DMA Source/Destination Transfer Length Register Bit definitions
- * @{
- */
-#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */
-/*@}*/
-
-
-
-
-/** @name Miscellaneous Control Register Bit definitions
- * @{
- */
-#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */
-#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */
-#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */
-/* @} */
-
-/** @name FIFO Threshold Bit definitions
- * @{
- */
-
-#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */
-#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */
-#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */
-#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */
-/* @}*/
-
-
-/* Miscellaneous constant values */
-#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */
-#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/
-#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base
- * address
- */
-#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note C-style signature:
-* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XDcfg_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + (RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write to the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + (RegOffset), (Data))
-
-/************************** Function Prototypes ******************************/
-/*
- * Perform reset operation to the devcfg interface
- */
-void XDcfg_ResetHw(u32 BaseAddr);
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a1/e1e3c2585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a1/e1e3c2585243001d18b399c1eb9b3628
deleted file mode 100644
index f0102aa..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a1/e1e3c2585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,54 +0,0 @@
-/* putnum.c -- put a hex number on the output device.
- *
- * Copyright (c) 1995 Cygnus Support
- *
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
- * putnum -- print a 32 bit number in hex
- */
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-
-/************************** Function Prototypes ******************************/
-extern void print (const char8 *ptr);
-void putnum(u32 num);
-
-void putnum(u32 num)
-{
- char8 buf[9];
- s32 cnt;
- s32 i;
- char8 *ptr;
- u32 digit;
- for(i = 0; i<9; i++) {
- buf[i] = '0';
- }
-
- ptr = buf;
- for (cnt = 7 ; cnt >= 0 ; cnt--) {
- digit = (num >> (cnt * 4U)) & 0x0000000fU;
-
- if (digit <= 9U) {
- digit += (u32)'0';
- *ptr = ((char8) digit);
- ptr += 1;
- } else {
- digit += ((u32)'a' - (u32)10);
- *ptr = ((char8)digit);
- ptr += 1;
- }
- }
-
- print (buf);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a1/f0a8f6595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a1/f0a8f6595243001d18b399c1eb9b3628
deleted file mode 100644
index edd697a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a1/f0a8f6595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,79 +0,0 @@
-/*-----------------------------------------------------------------------/
-/ Low level disk interface module include file (C)ChaN, 2014 /
-/-----------------------------------------------------------------------*/
-
-#ifndef DISKIO_DEFINED
-#define DISKIO_DEFINED
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define USE_WRITE 1 /* 1: Enable disk_write function */
-#define USE_IOCTL 1 /* 1: Enable disk_ioctl function */
-
-#include "integer.h"
-#include "xil_types.h"
-
-/* Status of Disk Functions */
-typedef BYTE DSTATUS;
-
-/* Results of Disk Functions */
-typedef enum {
- RES_OK = 0, /* 0: Successful */
- RES_ERROR, /* 1: R/W Error */
- RES_WRPRT, /* 2: Write Protected */
- RES_NOTRDY, /* 3: Not Ready */
- RES_PARERR /* 4: Invalid Parameter */
-} DRESULT;
-
-
-/*---------------------------------------*/
-/* Prototypes for disk control functions */
-
-DSTATUS disk_initialize (BYTE pdrv);
-DSTATUS disk_status (BYTE pdrv);
-DRESULT disk_read (BYTE pdrv, BYTE* buff, DWORD sector, UINT count);
-DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count);
-DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
-
-
-/* Disk Status Bits (DSTATUS) */
-
-#define STA_NOINIT 0x01U /* Drive not initialized */
-#define STA_NODISK 0x02U /* No medium in the drive */
-#define STA_PROTECT 0x04U /* Write protected */
-
-
-/* Command code for disk_ioctrl function */
-
-/* Generic command (used by FatFs) */
-#define CTRL_SYNC 0U /* Flush disk cache (for write functions) */
-#define GET_SECTOR_COUNT 1U /* Get media size (for only f_mkfs()) */
-#define GET_SECTOR_SIZE 2U /* Get sector size (for multiple sector size (_MAX_SS >= 1024)) */
-#define GET_BLOCK_SIZE 3U /* Get erase block size (for only f_mkfs()) */
-#define CTRL_ERASE_SECTOR 4U /* Force erased a block of sectors (for only _USE_ERASE) */
-
-/* Generic command (not used by FatFs) */
-#define CTRL_POWER 5U /* Get/Set power status */
-#define CTRL_LOCK 6U /* Lock/Unlock media removal */
-#define CTRL_EJECT 7U /* Eject media */
-#define CTRL_FORMAT 8U /* Create physical format on the media */
-
-/* MMC/SDC specific ioctl command */
-#define MMC_GET_TYPE 10U /* Get card type */
-#define MMC_GET_CSD 11U /* Get CSD */
-#define MMC_GET_CID 12U /* Get CID */
-#define MMC_GET_OCR 13U /* Get OCR */
-#define MMC_GET_SDSTAT 14U /* Get SD status */
-
-/* ATA/CF specific ioctl command */
-#define ATA_GET_REV 20U /* Get F/W revision */
-#define ATA_GET_MODEL 21U /* Get model name */
-#define ATA_GET_SN 22U /* Get serial number */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a2/1077dc535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a2/1077dc535243001d18b399c1eb9b3628
deleted file mode 100644
index de98c61..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a2/1077dc535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,345 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xscutimer.h
-* @addtogroup scutimer_v2_3
-* @{
-* @details
-*
-* The timer driver supports the Cortex A9 private timer.
-*
-* The timer driver supports the following features:
-* - Normal mode and Auto reload mode
-* - Interrupts (Interrupt handler is not provided in this driver. Application
-* has to register it's own handler)
-*
-* Initialization and Configuration
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate with the Timer.
-*
-* XScuTimer_CfgInitialize() API is used to initialize the Timer. The
-* user needs to first call the XScuTimer_LookupConfig() API which returns
-* the Configuration structure pointer which is passed as a parameter to
-* the XScuTimer_CfgInitialize() API.
-*
-* Interrupts
-*
-* The Timer hardware supports interrupts.
-*
-* This driver does not provide a Interrupt Service Routine (ISR) for the device.
-* It is the responsibility of the application to provide one if needed. Refer to
-* the interrupt example provided with this driver for details on using the
-* Timer in interrupt mode.
-*
-* Virtual Memory
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-* Threads
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* Asserts
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* Building the driver
-*
-* The XScuTimer driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-*
-*
-* NOTE:
-* The timer is not a part of the snoop control unit as indicated by the
-* prefix "scu" in the name of the driver.
-* It is an independent module in APU.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm 03/10/10 First release
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 2.3 mus 08/31/20 Updated makefile to support parallel make and
-* incremental builds, it would help to reduce compilation
-* time.
-*
-*
-******************************************************************************/
-#ifndef XSCUTIMER_H /* prevent circular inclusions */
-#define XSCUTIMER_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xscutimer_hw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddr; /**< Base address of the device */
-} XScuTimer_Config;
-
-/**
- * The XScuTimer driver instance data. The user is required to allocate a
- * variable of this type for every timer device in the system.
- * A pointer to a variable of this type is then passed to the driver API
- * functions.
- */
-typedef struct {
- XScuTimer_Config Config; /**< Hardware Configuration */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStarted; /**< Device timer is running */
-} XScuTimer;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Check if the timer has expired.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return
-* - TRUE if the timer has expired.
-* - FALSE if the timer has not expired.
-*
-* @note C-style signature:
-* int XScuTimer_IsExpired(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_IsExpired(InstancePtr) \
- ((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_ISR_OFFSET) & \
- XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
- XSCUTIMER_ISR_EVENT_FLAG_MASK)
-
-/****************************************************************************/
-/**
-*
-* Re-start the timer. This macro will read the timer load register
-* and writes the same value to load register to update the counter register.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_RestartTimer(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_RestartTimer(InstancePtr) \
- XScuTimer_LoadTimer((InstancePtr), \
- XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_LOAD_OFFSET))
-
-/****************************************************************************/
-/**
-*
-* Write to the timer load register. This will also update the
-* timer counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-* @param Value is the count to be loaded in to the load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_LoadTimer(InstancePtr, Value) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_LOAD_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer counter register value. It can be called at any
-* time.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return Contents of the timer counter register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_GetCounterValue(InstancePtr) \
- XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_COUNTER_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Enable auto-reload mode.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_EnableAutoReload(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) | \
- XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
-
-/****************************************************************************/
-/**
-*
-* Disable auto-reload mode.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_DisableAutoReload(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) & \
- ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Enable the Timer interrupt.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_EnableInterrupt(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) | \
- XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
-
-/****************************************************************************/
-/**
-*
-* Disable the Timer interrupt.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_DisableInterrupt(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) & \
- ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
-
-/*****************************************************************************/
-/**
-*
-* This function reads the interrupt status.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_GetInterruptStatus(InstancePtr) \
- XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_ISR_OFFSET)
-
-/*****************************************************************************/
-/**
-*
-* This function clears the interrupt status.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_ClearInterruptStatus(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Lookup configuration in xscutimer_sinit.c
- */
-XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId);
-
-/*
- * Selftest function in xscutimer_selftest.c
- */
-s32 XScuTimer_SelfTest(XScuTimer *InstancePtr);
-
-/*
- * Interface functions in xscutimer.c
- */
-s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
- XScuTimer_Config *ConfigPtr, u32 EffectiveAddress);
-void XScuTimer_Start(XScuTimer *InstancePtr);
-void XScuTimer_Stop(XScuTimer *InstancePtr);
-void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue);
-u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a2/209490595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a2/209490595243001d18b399c1eb9b3628
deleted file mode 100644
index bbf3bb8..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a2/209490595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,35 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include "xil_types.h"
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) char8 *sbrk (s32 nbytes);
-}
-#endif
-
-extern u8 _heap_start[];
-extern u8 _heap_end[];
-extern char8 HeapBase[];
-extern char8 HeapLimit[];
-
-
-
-__attribute__((weak)) char8 *sbrk (s32 nbytes)
-{
- char8 *base;
- static char8 *heap_ptr = HeapBase;
-
- base = heap_ptr;
- if((heap_ptr != NULL) && (heap_ptr + nbytes <= (char8 *)&HeapLimit + 1)) {
- heap_ptr += nbytes;
- return base;
- } else {
- errno = ENOMEM;
- return ((char8 *)-1);
- }
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a2/20ddf8575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a2/20ddf8575243001d18b399c1eb9b3628
deleted file mode 100644
index abc67b7..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a2/20ddf8575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,73 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xgpiops_sinit.c
-* @addtogroup gpiops_v3_9
-* @{
-*
-* This file contains the implementation of the XGpioPs driver's static
-* initialization functionality.
-*
-* @note None.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sv 01/15/10 First Release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xgpiops.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-
-/*****************************************************************************/
-/**
-*
-* This function looks for the device configuration based on the unique device
-* ID. The table XGpioPs_ConfigTable[] contains the configuration information
-* for each device in the system.
-*
-* @param DeviceId is the unique device ID of the device being looked up.
-*
-* @return A pointer to the configuration table entry corresponding to the
-* given device ID, or NULL if no match is found.
-*
-* @note None.
-*
-******************************************************************************/
-XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
-{
- XGpioPs_Config *CfgPtr = NULL;
- u32 Index;
-
- for (Index = 0U; Index < (u32)XPAR_XGPIOPS_NUM_INSTANCES; Index++) {
- if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XGpioPs_ConfigTable[Index];
- break;
- }
- }
-
- return (XGpioPs_Config *)CfgPtr;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a2/513cd9565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a2/513cd9565243001d18b399c1eb9b3628
deleted file mode 100644
index e48c5f3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a2/513cd9565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,111 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_errata.h
-*
-* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
-* @{
-* Various ARM errata are handled in the standalone BSP. The implementation for
-* errata handling follows ARM guidelines and is based on the open source Linux
-* support for these errata.
-*
-* @note The errata handling is enabled by default. To disable handling of all the
-* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
-* disable errata on a per-erratum basis, un-define relevant macros in
-* xil_errata.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a srt 04/18/13 First release
-* 6.6 mus 12/07/17 Removed errata 753970, It fixes CR#989132.
-*
-*
-******************************************************************************/
-#ifndef XIL_ERRATA_H
-#define XIL_ERRATA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *@cond nocomments
- */
-/**
- * @name errata_definitions
- *
- * The errata conditions handled in the standalone BSP are listed below
- * @{
- */
-
-#define ENABLE_ARM_ERRATA 1
-
-/**
- *@endcond
- */
-
-#ifdef ENABLE_ARM_ERRATA
-
-/**
- * Errata No: 742230
- * Description: DMB operation may be faulty
- */
-#define CONFIG_ARM_ERRATA_742230 1
-
-/**
- * Errata No: 743622
- * Description: Faulty hazard checking in the Store Buffer may lead
- * to data corruption.
- */
-#define CONFIG_ARM_ERRATA_743622 1
-
-/**
- * Errata No: 775420
- * Description: A data cache maintenance operation which aborts,
- * might lead to deadlock
- */
-#define CONFIG_ARM_ERRATA_775420 1
-
-/**
- * Errata No: 794073
- * Description: Speculative instruction fetches with MMU disabled
- * might not comply with architectural requirements
- */
-#define CONFIG_ARM_ERRATA_794073 1
-
-
-/** PL310 L2 Cache Errata */
-
-/**
- * Errata No: 588369
- * Description: Clean & Invalidate maintenance operations do not
- * invalidate clean lines
- */
-#define CONFIG_PL310_ERRATA_588369 1
-
-/**
- * Errata No: 727915
- * Description: Background Clean and Invalidate by Way operation
- * can cause data corruption
- */
-#define CONFIG_PL310_ERRATA_727915 1
-
-/*@}*/
-#endif /* ENABLE_ARM_ERRATA */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_ERRATA_H */
-/**
-* @} End of "addtogroup a9_errata".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a2/60882f595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a2/60882f595243001d18b399c1eb9b3628
deleted file mode 100644
index da7e768..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a2/60882f595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,36 +0,0 @@
-/* print.c -- print a string on the output device.
- *
- * Copyright (c) 1995 Cygnus Support
- *
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- *
- */
-
-/*
- * print -- do a raw print of a string
- */
-#include "xil_printf.h"
-
-void print(const char8 *ptr)
-{
-#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
- XPVXenConsole_Write(ptr);
-#else
-#ifdef STDOUT_BASEADDRESS
- while (*ptr != (char8)0) {
- outbyte (*ptr);
- ptr++;
- }
-#else
-(void)ptr;
-#endif
-#endif
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a2/60e5f3555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a2/60e5f3555243001d18b399c1eb9b3628
deleted file mode 100644
index 1b601db..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a2/60e5f3555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,96 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file smc.h
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 11/03/09 Initial release.
-* 4.2 pkp 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
-* as smc.c is removed
-*
-*
-* @note None.
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef SMC_H /* prevent circular inclusions */
-#define SMC_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xparameters.h"
-#include "xil_io.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/* Memory controller configuration register offset */
-#define XSMCPSS_MC_STATUS 0x000U /* Controller status reg, RO */
-#define XSMCPSS_MC_INTERFACE_CONFIG 0x004U /* Interface config reg, RO */
-#define XSMCPSS_MC_SET_CONFIG 0x008U /* Set configuration reg, WO */
-#define XSMCPSS_MC_CLR_CONFIG 0x00CU /* Clear config reg, WO */
-#define XSMCPSS_MC_DIRECT_CMD 0x010U /* Direct command reg, WO */
-#define XSMCPSS_MC_SET_CYCLES 0x014U /* Set cycles register, WO */
-#define XSMCPSS_MC_SET_OPMODE 0x018U /* Set opmode register, WO */
-#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020U /* Refresh period_0 reg, RW */
-#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024U /* Refresh period_1 reg, RW */
-
-/* Chip select configuration register offset */
-#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100U /* Interface 0 chip 0 config */
-#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120U /* Interface 0 chip 1 config */
-#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140U /* Interface 0 chip 2 config */
-#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160U /* Interface 0 chip 3 config */
-#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180U /* Interface 1 chip 0 config */
-#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0U /* Interface 1 chip 1 config */
-#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0U /* Interface 1 chip 2 config */
-#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0U /* Interface 1 chip 3 config */
-
-/* User configuration register offset */
-#define XSMCPSS_UC_STATUS_OFFSET 0x200U /* User status reg, RO */
-#define XSMCPSS_UC_CONFIG_OFFSET 0x204U /* User config reg, WO */
-
-/* Integration test register offset */
-#define XSMCPSS_IT_OFFSET 0xE00U
-
-/* ID configuration register offset */
-#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0U
-#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4U
-#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8U
-#define XSMCPSS_ID_PERIP_3_OFFSET 0xFECU
-#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0U
-#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4U
-#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8U
-#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFCU
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* SMC_H */
-
-/**
- *@endcond
- */
\ No newline at end of file
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a2/d04f13525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a2/d04f13525243001d18b399c1eb9b3628
deleted file mode 100644
index e273e37..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a2/d04f13525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,41 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#ifndef __PLATFORM_H_
-#define __PLATFORM_H_
-
-#include "platform_config.h"
-
-void init_platform();
-void cleanup_platform();
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a2/f1ffc1555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a2/f1ffc1555243001d18b399c1eb9b3628
deleted file mode 100644
index ba7531d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a2/f1ffc1555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,143 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2017 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/*****************************************************************************/
-/**
-*
-* @file xil_sleeptimer.c
-*
-* This file provides the common helper routines for the sleep API's
-*
-*
-* MODIFICATION HISTORY :
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 6.6 srm 10/18/17 First Release.
-* 6.6 srm 04/20/18 Fixed compilation warning in Xil_SleepTTCCommon API
-* 7.0 mus 03/27/19 Updated XTime_StartTTCTimer to skip IOU slcr address
-* space access, if processor is nonsecure and IOU slcr
-* address space is secure. CR#1015725.
-*
-*
-*****************************************************************************/
-
-/**************************** Include Files ********************************/
-
-#include "xil_io.h"
-#include "xil_sleeptimer.h"
-#include "xtime_l.h"
-
-/**************************** Constant Definitions *************************/
-
-
-/* Function definitions are applicable only when TTC3 is present*/
-#if defined (SLEEP_TIMER_BASEADDR)
-/****************************************************************************/
-/**
-*
-* This is a helper function used by sleep/usleep APIs to
-* have delay in sec/usec
-*
-* @param delay - delay time in seconds/micro seconds
-*
-* @param frequency - Number of counts per second/micro second
-*
-* @return none
-*
-* @note none
-*
-*****************************************************************************/
-void Xil_SleepTTCCommon(u32 delay, u64 frequency)
-{
- u64 tEnd = 0U;
- u64 tCur = 0U;
- XCntrVal TimeHighVal = 0U;
- XCntrVal TimeLowVal1 = 0U;
- XCntrVal TimeLowVal2 = 0U;
-
- TimeLowVal1 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET);
- tEnd = (u64)TimeLowVal1 + ((u64)(delay) * frequency);
- do
- {
- TimeLowVal2 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET);
- if (TimeLowVal2 < TimeLowVal1) {
- TimeHighVal++;
- }
- TimeLowVal1 = TimeLowVal2;
- tCur = (((u64) TimeHighVal) << XSLEEP_TIMER_REG_SHIFT) |
- (u64)TimeLowVal2;
- }while (tCur < tEnd);
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This API starts the Triple Timer Counter
-*
-* @param none
-*
-* @return none
-*
-* @note none
-*
-*****************************************************************************/
-void XTime_StartTTCTimer()
-{
- u32 TimerPrescalar;
- u32 TimerCntrl;
-
-#if (defined (__aarch64__) && EL3==1) || (defined (ARMR5) && (PROCESSOR_ACCESS_VALUE & IOU_SLCR_TZ_MASK)) || defined (ARMA53_32)
- u32 LpdRst;
-
-#if defined (versal)
- u32 RstAddr = CRL_TTC_RST;
- u32 RstMask = CRL_TTC_BASE_RST_MASK << XSLEEP_TTC_INSTANCE;
-#else
- u32 RstAddr = RST_LPD_IOU2;
- u32 RstMask = RST_LPD_IOU2_TTC_BASE_RESET_MASK << XSLEEP_TTC_INSTANCE;
-#endif
- /* check if the timer is reset */
- LpdRst = XSleep_ReadCounterVal(RstAddr);
- if ((LpdRst & RstMask) != 0 ) {
- LpdRst = LpdRst & (~RstMask);
- Xil_Out32(RstAddr, LpdRst);
- } else {
-#endif
- TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET);
- /* check if Timer is disabled */
- if ((TimerCntrl & XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK) == 0) {
- TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET);
- /* check if Timer is configured with proper functionalty for sleep */
- if ((TimerPrescalar & XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK) == 0)
- return;
- }
-#if (defined (__aarch64__) && EL3==1) || (defined (ARMR5) && (PROCESSOR_ACCESS_VALUE & IOU_SLCR_TZ_MASK)) || defined (ARMA53_32)
- }
-#endif
- /* Disable the timer to configure */
- TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET);
- TimerCntrl = TimerCntrl | XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK;
- Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET,
- TimerCntrl);
- /* Disable the prescalar */
- TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET);
- TimerPrescalar = TimerPrescalar & (~XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK);
- Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET,
- TimerPrescalar);
- /* Enable the Timer */
- TimerCntrl = TimerCntrl & (~XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK);
- Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET,
- TimerCntrl);
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a3/106bcc565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a3/106bcc565243001d18b399c1eb9b3628
deleted file mode 100644
index 1b601db..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a3/106bcc565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,96 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file smc.h
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 11/03/09 Initial release.
-* 4.2 pkp 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
-* as smc.c is removed
-*
-*
-* @note None.
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef SMC_H /* prevent circular inclusions */
-#define SMC_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xparameters.h"
-#include "xil_io.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/* Memory controller configuration register offset */
-#define XSMCPSS_MC_STATUS 0x000U /* Controller status reg, RO */
-#define XSMCPSS_MC_INTERFACE_CONFIG 0x004U /* Interface config reg, RO */
-#define XSMCPSS_MC_SET_CONFIG 0x008U /* Set configuration reg, WO */
-#define XSMCPSS_MC_CLR_CONFIG 0x00CU /* Clear config reg, WO */
-#define XSMCPSS_MC_DIRECT_CMD 0x010U /* Direct command reg, WO */
-#define XSMCPSS_MC_SET_CYCLES 0x014U /* Set cycles register, WO */
-#define XSMCPSS_MC_SET_OPMODE 0x018U /* Set opmode register, WO */
-#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020U /* Refresh period_0 reg, RW */
-#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024U /* Refresh period_1 reg, RW */
-
-/* Chip select configuration register offset */
-#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100U /* Interface 0 chip 0 config */
-#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120U /* Interface 0 chip 1 config */
-#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140U /* Interface 0 chip 2 config */
-#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160U /* Interface 0 chip 3 config */
-#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180U /* Interface 1 chip 0 config */
-#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0U /* Interface 1 chip 1 config */
-#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0U /* Interface 1 chip 2 config */
-#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0U /* Interface 1 chip 3 config */
-
-/* User configuration register offset */
-#define XSMCPSS_UC_STATUS_OFFSET 0x200U /* User status reg, RO */
-#define XSMCPSS_UC_CONFIG_OFFSET 0x204U /* User config reg, WO */
-
-/* Integration test register offset */
-#define XSMCPSS_IT_OFFSET 0xE00U
-
-/* ID configuration register offset */
-#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0U
-#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4U
-#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8U
-#define XSMCPSS_ID_PERIP_3_OFFSET 0xFECU
-#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0U
-#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4U
-#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8U
-#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFCU
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* SMC_H */
-
-/**
- *@endcond
- */
\ No newline at end of file
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a3/210a48545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a3/210a48545243001d18b399c1eb9b3628
deleted file mode 100644
index fa58233..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a3/210a48545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,78 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_spinlock.h
-*
-* This header file contains function prototypes to be used while using Xilinx
-* spinlocking mechanism.
-* Please refer to file header contents of xil_spinlock.c to understand in
-* detail the spinlocking mechanism.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 7.5 asa 02/16/21 First release
-* 7.6 sk 08/05/21 Add Boolean check and braces for Xil_IsSpinLockEnabled
-* if condition to fix misrac violations.
-*
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- --------------------------------------------------------
- * 1.00a wgr 10/10/10 First release
- * 2.5 pm 02/20/20 Added multiplier bit for ISO frame handling.
- *
- *
- ******************************************************************************/
-#ifndef XUSBPS_ENDPOINT_H
-#define XUSBPS_ENDPOINT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xusbps.h"
-#include "xil_types.h"
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-
-/**
- * Endpoint Device Transfer Descriptor
- *
- * The dTD describes to the device controller the location and quantity of data
- * to be sent/received for given transfer. The driver does not attempt to
- * modify any field in an active dTD except the Next Link Pointer.
- */
-#define XUSBPS_dTDNLP 0x00 /**< Pointer to the next descriptor */
-#define XUSBPS_dTDTOKEN 0x04 /**< Descriptor Token */
-#define XUSBPS_dTDBPTR0 0x08 /**< Buffer Pointer 0 */
-#define XUSBPS_dTDBPTR1 0x0C /**< Buffer Pointer 1 */
-#define XUSBPS_dTDBPTR2 0x10 /**< Buffer Pointer 2 */
-#define XUSBPS_dTDBPTR3 0x14 /**< Buffer Pointer 3 */
-#define XUSBPS_dTDBPTR4 0x18 /**< Buffer Pointer 4 */
-#define XUSBPS_dTDBPTR(n) (XUSBPS_dTDBPTR0 + (n) * 0x04)
-#define XUSBPS_dTDRSRVD 0x1C /**< Reserved field */
-
-/* We use the reserved field in the dTD to store user data. */
-#define XUSBPS_dTDUSERDATA XUSBPS_dTDRSRVD /**< Reserved field */
-
-
-/** @name dTD Next Link Pointer (dTDNLP) bit positions.
- * @{
- */
-#define XUSBPS_dTDNLP_T_MASK 0x00000001
- /**< USB dTD Next Link Pointer Terminate Bit */
-#define XUSBPS_dTDNLP_ADDR_MASK 0xFFFFFFE0
- /**< USB dTD Next Link Pointer Address [31:5] */
-/* @} */
-
-
-/** @name dTD Token (dTDTOKEN) bit positions.
- * @{
- */
-#define XUSBPS_dTDTOKEN_XERR_MASK 0x00000008 /**< dTD Transaction Error */
-#define XUSBPS_dTDTOKEN_BUFERR_MASK 0x00000020 /**< dTD Data Buffer Error */
-#define XUSBPS_dTDTOKEN_HALT_MASK 0x00000040 /**< dTD Halted Flag */
-#define XUSBPS_dTDTOKEN_ACTIVE_MASK 0x00000080 /**< dTD Active Bit */
-#define XUSBPS_dTDTOKEN_MULTO_MASK 0x00000C00 /**< Multiplier Override Field [1:0] */
-#define XUSBPS_dTDTOKEN_IOC_MASK 0x00008000 /**< Interrupt on Complete Bit */
-#define XUSBPS_dTDTOKEN_LEN_MASK 0x7FFF0000 /**< Transfer Length Field */
-/* @} */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- *
- * IMPORTANT NOTE:
- * ===============
- *
- * Many of the following macros modify Device Queue Head (dQH) data structures
- * and Device Transfer Descriptor (dTD) data structures. Those structures can
- * potentially reside in CACHED memory. Therefore, it's the callers
- * responsibility to ensure cache coherency by using provided
- *
- * XUsbPs_dQHInvalidateCache()
- * XUsbPs_dQHFlushCache()
- * XUsbPs_dTDInvalidateCache()
- * XUsbPs_dTDFlushCache()
- *
- * function calls.
- *
- ******************************************************************************/
-#define XUsbPs_dTDInvalidateCache(dTDPtr) \
- Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
-
-#define XUsbPs_dTDFlushCache(dTDPtr) \
- Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
-
-#define XUsbPs_dQHInvalidateCache(dQHPtr) \
- Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
-
-#define XUsbPs_dQHFlushCache(dQHPtr) \
- Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Transfer Length for the given Transfer Descriptor.
- *
- * @param dTDPtr is pointer to the dTD element.
- * @param Len is the length to be set. Range: 0..16384
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetTransferLen(dTDPtr, Len) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
- ~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16))
-
-
-/*****************************************************************************/
-/**
- *
- * This macro gets the Next Link pointer of the given Transfer Descriptor.
- *
- * @param dTDPtr is pointer to the dTD element.
- *
- * @return TransferLength field of the descriptor.
- *
- * @note C-style signature:
- * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDGetNLP(dTDPtr) \
- (XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\
- & XUSBPS_dTDNLP_ADDR_MASK))
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Next Link pointer of the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- * @param NLP is the Next Link Pointer
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetNLP(dTDPtr, NLP) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
- (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
- ~XUSBPS_dTDNLP_ADDR_MASK) | \
- ((NLP) & XUSBPS_dTDNLP_ADDR_MASK))
-
-
-/*****************************************************************************/
-/**
- *
- * This macro gets the Transfer Length for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @return TransferLength field of the descriptor.
- *
- * @note C-style signature:
- * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDGetTransferLen(dTDPtr) \
- (u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) \
- & XUSBPS_dTDTOKEN_LEN_MASK) >> 16)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Interrupt On Complete (IOC) bit for the given Transfer
- * Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetIOC(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetIOC(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
- XUSBPS_dTDTOKEN_IOC_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Terminate bit for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetTerminate(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetTerminate(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) | \
- XUSBPS_dTDNLP_T_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro clears the Terminate bit for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDClrTerminate(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDClrTerminate(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
- ~XUSBPS_dTDNLP_T_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro checks if the given descriptor is active.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @return
- * - TRUE: The buffer is active.
- * - FALSE: The buffer is not active.
- *
- * @note C-style signature:
- * int XUsbPs_dTDIsActive(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDIsActive(dTDPtr) \
- ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
- XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Active bit for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetActive(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetActive(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
- XUSBPS_dTDTOKEN_ACTIVE_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the multiplier bit for the Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- * @param val is the multiplier value.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetMultO(u32 dTDPtr, u32 val)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetMultO(dTDPtr, val) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
- (~XUSBPS_dTDTOKEN_MULTO_MASK)) | val)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro reads the content of a field in a Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- * @param Id is the field ID inside the dTD element to read.
- *
- * @note C-style signature:
- * u32 XUsbPs_ReaddTD(u32 dTDPtr, u32 Id)
- *
- ******************************************************************************/
-#define XUsbPs_ReaddTD(dTDPtr, Id) (*(u32 *)((u32)(dTDPtr) + (u32)(Id)))
-
-/*****************************************************************************/
-/**
- *
- * This macro writes a value to a field in a Transfer Descriptor.
- *
- * @param dTDPtr is pointer to the dTD element.
- * @param Id is the field ID inside the dTD element to read.
- * @param Val is the value to write to the field.
- *
- * @note C-style signature:
- * u32 XUsbPs_WritedTD(u32 dTDPtr, u32 Id, u32 Val)
- *
- ******************************************************************************/
-#define XUsbPs_WritedTD(dTDPtr, Id, Val) \
- (*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val))
-
-
-/******************************************************************************/
-/**
- * Endpoint Device Queue Head
- *
- * Device queue heads are arranged in an array in a continuous area of memory
- * pointed to by the ENDPOINTLISTADDR pointer. The device controller will index
- * into this array based upon the endpoint number received from the USB bus.
- * All information necessary to respond to transactions for all primed
- * transfers is contained in this list so the Device Controller can readily
- * respond to incoming requests without having to traverse a linked list.
- *
- * The device Endpoint Queue Head (dQH) is where all transfers are managed. The
- * dQH is a 48-byte data structure, but must be aligned on a 64-byte boundary.
- * During priming of an endpoint, the dTD (device transfer descriptor) is
- * copied into the overlay area of the dQH, which starts at the nextTD pointer
- * DWord and continues through the end of the buffer pointers DWords. After a
- * transfer is complete, the dTD status DWord is updated in the dTD pointed to
- * by the currentTD pointer. While a packet is in progress, the overlay area of
- * the dQH is used as a staging area for the dTD so that the Device Controller
- * can access needed information with little minimal latency.
- *
- * @note
- * Software must ensure that no interface data structure reachable by the
- * Device Controller spans a 4K-page boundary. The first element of the
- * Endpoint Queue Head List must be aligned on a 4K boundary.
- */
-#define XUSBPS_dQHCFG 0x00 /**< dQH Configuration */
-#define XUSBPS_dQHCPTR 0x04 /**< dQH Current dTD Pointer */
-#define XUSBPS_dQHdTDNLP 0x08 /**< dTD Next Link Ptr in dQH
- overlay */
-#define XUSBPS_dQHdTDTOKEN 0x0C /**< dTD Token in dQH overlay */
-#define XUSBPS_dQHSUB0 0x28 /**< USB dQH Setup Buffer 0 */
-#define XUSBPS_dQHSUB1 0x2C /**< USB dQH Setup Buffer 1 */
-
-
-/** @name dQH Configuration (dQHCFG) bit positions.
- * @{
- */
-#define XUSBPS_dQHCFG_IOS_MASK 0x00008000
- /**< USB dQH Interrupt on Setup Bit */
-#define XUSBPS_dQHCFG_MPL_MASK 0x07FF0000
- /**< USB dQH Maximum Packet Length
- * Field [10:0] */
-#define XUSBPS_dQHCFG_MPL_SHIFT 16
-#define XUSBPS_dQHCFG_ZLT_MASK 0x20000000
- /**< USB dQH Zero Length Termination
- * Select Bit */
-#define XUSBPS_dQHCFG_MULT_MASK 0xC0000000
- /* USB dQH Number of Transactions Field
- * [1:0] */
-#define XUSBPS_dQHCFG_MULT_SHIFT 30
-/* @} */
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Maximum Packet Length field of the give Queue Head.
- *
- * @param dQHPtr is a pointer to the dQH element.
- * @param Len is the length to be set.
- *
- * @note C-style signature:
- * void XUsbPs_dQHSetMaxPacketLen(u32 dQHPtr, u32 Len)
- *
- ******************************************************************************/
-#define XUsbPs_dQHSetMaxPacketLen(dQHPtr, Len) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
- ~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16))
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Interrupt On Setup (IOS) bit for an endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHSetIOS(u32 dQHPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dQHSetIOS(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
- XUSBPS_dQHCFG_IOS_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro clears the Interrupt On Setup (IOS) bit for an endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHClrIOS(u32 dQHPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dQHClrIOS(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
- ~XUSBPS_dQHCFG_IOS_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro enables Zero Length Termination for the endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHEnableZLT(u32 dQHPtr)
- *
- *
- ******************************************************************************/
-#define XUsbPs_dQHEnableZLT(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
- ~XUSBPS_dQHCFG_ZLT_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro disables Zero Length Termination for the endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHDisableZLT(u32 dQHPtr)
- *
- *
- ******************************************************************************/
-#define XUsbPs_dQHDisableZLT(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
- XUSBPS_dQHCFG_ZLT_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro reads the content of a field in a Queue Head.
- *
- * @param dQHPtr is a pointer to the dQH element.
- * @param Id is the Field ID inside the dQH element to read.
- *
- * @note C-style signature:
- * u32 XUsbPs_ReaddQH(u32 dQHPtr, u32 Id)
- *
- ******************************************************************************/
-#define XUsbPs_ReaddQH(dQHPtr, Id) (*(u32 *)((u32)(dQHPtr) + (u32) (Id)))
-
-/*****************************************************************************/
-/**
- *
- * This macro writes a value to a field in a Queue Head.
- *
- * @param dQHPtr is a pointer to the dQH element.
- * @param Id is the Field ID inside the dQH element to read.
- * @param Val is the Value to write to the field.
- *
- * @note C-style signature:
- * u32 XUsbPs_WritedQH(u32 dQHPtr, u32 Id, u32 Val)
- *
- ******************************************************************************/
-#define XUsbPs_WritedQH(dQHPtr, Id, Val) \
- (*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val))
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XUSBPS_ENDPOINT_H */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a3/50f4f0545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a3/50f4f0545243001d18b399c1eb9b3628
deleted file mode 100644
index ab2b506..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a3/50f4f0545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,454 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xsdps.c
-* @addtogroup sdps_v3_13
-* @{
-*
-* Contains the interface functions of the XSdPs driver.
-* See xsdps.h for a detailed description of the device and driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a hk/sg 10/17/13 Initial release
-* 2.0 hk 12/13/13 Added check for arm to use sleep.h and its API's
-* 2.1 hk 04/18/14 Add sleep for microblaze designs. CR# 781117.
-* 2.2 hk 07/28/14 Make changes to enable use of data cache.
-* 2.3 sk 09/23/14 Send command for relative card address
-* when re-initialization is done.CR# 819614.
-* Use XSdPs_Change_ClkFreq API whenever changing
-* clock.CR# 816586.
-* 2.4 sk 12/04/14 Added support for micro SD without
-* WP/CD. CR# 810655.
-* Checked for DAT Inhibit mask instead of CMD
-* Inhibit mask in Cmd Transfer API.
-* Added Support for SD Card v1.0
-* 2.5 sg 07/09/15 Added SD 3.0 features
-* kvn 07/15/15 Modified the code according to MISRAC-2012.
-* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
-* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
-* sk 12/10/15 Added support for MMC cards.
-* sk 02/16/16 Corrected the Tuning logic.
-* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
-* 2.8 sk 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
-* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
-* sk 07/16/16 Added support for UHS modes.
-* sk 07/07/16 Used usleep API for both arm and microblaze.
-* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
-* operating modes.
-* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
-* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
-* sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
-* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
-* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
-* sk 02/01/17 Added HSD and DDR mode support for eMMC.
-* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
-* sk 03/20/17 Add support for EL1 non-secure mode.
-* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
-* mn 07/17/17 Add support for running SD at 200MHz
-* mn 07/26/17 Fixed compilation warnings
-* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
-* mn 08/17/17 Added CCI support for A53 and disabled data cache
-* operations when it is enabled.
-* mn 08/22/17 Updated for Word Access System support
-* mn 09/06/17 Resolved compilation errors with IAR toolchain
-* mn 09/26/17 Added UHS_MODE_ENABLE macro to enable UHS mode
-* 3.4 mn 10/17/17 Use different commands for single and multi block
-* transfers
-* mn 03/02/18 Move UHS macro check to SD card initialization routine
-* 3.5 mn 04/18/18 Resolve compilation warnings for sdps driver
-* 3.6 mn 07/06/18 Fix Cppcheck and Doxygen warnings for sdps driver
-* mn 08/01/18 Add support for using 64Bit DMA with 32-Bit Processor
-* mn 08/01/18 Add cache invalidation call before returning from
-* ReadPolled API
-* mn 08/14/18 Resolve compilation warnings for ARMCC toolchain
-* mn 10/01/18 Change Expected Response for CMD3 to R1 for MMC
-* mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
-* 3.7 mn 02/01/19 Add support for idling of SDIO
-* aru 03/12/19 Modified the code according to MISRAC-2012.
-* 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
-* mn 09/17/19 Modified ADMA handling API for 32bit and 64bit addresses
-* 3.9 sd 02/07/20 Added clock support
-* mn 03/03/20 Restructured the code for more readability and modularity
-* mn 03/30/20 Return XST_DEVICE_IS_STARTED when host is already started
-* mn 03/30/20 Move Clock enabling before checking for Host already started
-* 3.10 mn 06/05/20 Check Transfer completion separately from XSdPs_Read and
-* XSdPs_Write APIs
-* mn 06/05/20 Modified code for SD Non-Blocking Read support
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xsdps_core.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-/*****************************************************************************/
-/**
-*
-* @brief
-* Initializes a specific XSdPs instance such that the driver is ready to use.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param ConfigPtr is a reference to a structure containing information
-* about a specific SD device. This function initializes an
-* InstancePtr object for a specific device specified by the
-* contents of Config.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. The caller is responsible for keeping the address
-* mapping from EffectiveAddr to the device physical base address
-* unchanged once this function is invoked. Unexpected errors may
-* occur if the address mapping changes after this function is
-* called. If address translation is not used, use
-* ConfigPtr->Config.BaseAddress for this device.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_DEVICE_IS_STARTED if the device is already started.
-* It must be stopped to re-initialize.
-*
-* @note This function initializes the host controller.
-* Initial clock of 400KHz is set.
-* Voltage of 3.3V is selected as that is supported by host.
-* Interrupts status is enabled and signal disabled by default.
-* Default data direction is card to host and
-* 32 bit ADMA2 is selected. Default Block size is 512 bytes.
-*
-******************************************************************************/
-s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
- u32 EffectiveAddr)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
-
-#if defined (XCLOCKING)
- InstancePtr->Config.RefClk = ConfigPtr->RefClk;
- Xil_ClockEnable(InstancePtr->Config.RefClk);
-#endif
- /* If this API is getting called twice, return value accordingly */
- if (InstancePtr->IsReady == XIL_COMPONENT_IS_READY) {
- Status = (s32)XST_DEVICE_IS_STARTED;
- goto RETURN_PATH ;
- }
-
- /* Set some default values. */
- InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
- InstancePtr->Config.BaseAddress = EffectiveAddr;
- InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
- InstancePtr->Config.CardDetect = ConfigPtr->CardDetect;
- InstancePtr->Config.WriteProtect = ConfigPtr->WriteProtect;
- InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
- InstancePtr->Config.BankNumber = ConfigPtr->BankNumber;
- InstancePtr->Config.HasEMIO = ConfigPtr->HasEMIO;
- InstancePtr->Config.IsCacheCoherent = ConfigPtr->IsCacheCoherent;
- InstancePtr->SectorCount = 0U;
- InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
- InstancePtr->OTapDelay = 0U;
- InstancePtr->ITapDelay = 0U;
- InstancePtr->Dma64BitAddr = 0U;
- InstancePtr->SlcrBaseAddr = XPS_SYS_CTRL_BASEADDR;
- InstancePtr->IsBusy = FALSE;
- InstancePtr->BlkSize = 0U;
-
- /* Host Controller version is read. */
- InstancePtr->HC_Version =
- (u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK);
-
- /*
- * Read capabilities register and update it in Instance pointer.
- * It is sufficient to read this once on power on.
- */
- InstancePtr->Host_Caps = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_CAPS_OFFSET);
-
- /* Reset the SD bus lines */
- Status = XSdPs_ResetConfig(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- /* Configure the SD Host Controller */
- XSdPs_HostConfig(InstancePtr);
-
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
-RETURN_PATH:
-#if defined (XCLOCKING)
- Xil_ClockDisable(InstancePtr->Config.RefClk);
-#endif
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* Initialize Card with Identification mode sequence
-*
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because
-* a) SD is already initialized
-* b) There is no card inserted
-* c) One of the steps (commands) in the
-* initialization cycle failed
-*
-*
-******************************************************************************/
-s32 XSdPs_CardInitialize(XSdPs *InstancePtr)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Default settings */
- InstancePtr->BusWidth = XSDPS_1_BIT_WIDTH;
- InstancePtr->CardType = XSDPS_CARD_SD;
- InstancePtr->Switch1v8 = 0U;
- InstancePtr->BusSpeed = XSDPS_CLK_400_KHZ;
-
-#if defined (XCLOCKING)
- Xil_ClockEnable(InstancePtr->Config.RefClk);
-#endif
-
- /* Change the clock frequency to 400 KHz */
- Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- /* Identify the Card whether it is SD, MMC or eMMC */
- Status = XSdPs_IdentifyCard(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Initialize the identified card */
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
- Status = XSdPs_SdCardInitialize(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } else {
- Status = XSdPs_MmcCardInitialize(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
-RETURN_PATH:
-#if defined (XCLOCKING)
- Xil_ClockDisable(InstancePtr->Config.RefClk);
-#endif
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function performs SD read in polled mode.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Arg is the address passed by the user that is to be sent as
-* argument along with the command.
-* @param BlkCnt - Block count passed by the user.
-* @param Buff - Pointer to the data buffer for a DMA transfer.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because another transfer
-* is in progress or command or data inhibit is set
-*
-******************************************************************************/
-s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- if (InstancePtr->IsBusy == TRUE) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
-#if defined (XCLOCKING)
- Xil_ClockEnable(InstancePtr->Config.RefClk);
-#endif
-
- /* Setup the Read Transfer */
- Status = XSdPs_SetupTransfer(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Read from the card */
- Status = XSdPs_Read(InstancePtr, Arg, BlkCnt, Buff);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Check for transfer done */
- Status = XSdps_CheckTransferDone(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if (InstancePtr->Config.IsCacheCoherent == 0U) {
- Xil_DCacheInvalidateRange((INTPTR)Buff,
- (INTPTR)BlkCnt * InstancePtr->BlkSize);
- }
-
-RETURN_PATH:
-#if defined (XCLOCKING)
- Xil_ClockDisable(InstancePtr->Config.RefClk);
-#endif
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function performs SD write in polled mode.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Arg is the address passed by the user that is to be sent as
-* argument along with the command.
-* @param BlkCnt - Block count passed by the user.
-* @param Buff - Pointer to the data buffer for a DMA transfer.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because another transfer
-* is in progress or command or data inhibit is set
-*
-******************************************************************************/
-s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- if (InstancePtr->IsBusy == TRUE) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
-#if defined (XCLOCKING)
- Xil_ClockEnable(InstancePtr->Config.RefClk);
-#endif
-
- /* Setup the Write Transfer */
- Status = XSdPs_SetupTransfer(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Write to the card */
- Status = XSdPs_Write(InstancePtr, Arg, BlkCnt, Buff);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Check for transfer done */
- Status = XSdps_CheckTransferDone(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
-RETURN_PATH:
-#if defined (XCLOCKING)
- Xil_ClockDisable(InstancePtr->Config.RefClk);
-#endif
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to idle the SDIO Interface
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Idle(XSdPs *InstancePtr)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-#if defined (XCLOCKING)
- Xil_ClockEnable(InstancePtr->Config.RefClk);
-#endif
-
- /* Check if the bus is idle */
- Status = XSdPs_CheckBusIdle(InstancePtr, XSDPS_PSR_INHIBIT_CMD_MASK
- | XSDPS_PSR_INHIBIT_DAT_MASK
- | XSDPS_PSR_DAT_ACTIVE_MASK);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- /* Disable the Bus Power */
- XSdPs_DisableBusPower(InstancePtr);
-
- /* Reset Command and Data Lines */
- Status = XSdPs_Reset(InstancePtr, XSDPS_SWRST_ALL_MASK);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
-#if defined (XCLOCKING)
- Xil_ClockDisable(InstancePtr->Config.RefClk);
-#endif
- return Status;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a3/5136e0555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a3/5136e0555243001d18b399c1eb9b3628
deleted file mode 100644
index e5a1efd..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a3/5136e0555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,122 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm_rvct.c
-*
-* This header file contains functions for using assembler code. It is
-* written specifically for RVCT.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 11/18/09 First Release
-* 7.2 asa 04/04/20 Renamed the str macro to strw.
-*
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.00a wgr 10/10/10 First release
- * 1.04a nm 10/23/12 Fixed CR# 679106.
- * 1.05a kpc 07/03/13 Added XUsbPs_ResetHw function prototype
- * 2.00a kpc 04/03/14 Fixed CR#777764. Corrected max endpoint vale and masks
- * 2.5 pm 02/20/20 Added Endpoint Control Register bit positions for Rx & Tx
- *
- *
- ******************************************************************************/
-#ifndef XUSBPS_HW_H
-#define XUSBPS_HW_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-
-#define XUSBPS_REG_SPACING 4
-
-/** @name Timer 0 Register offsets
- *
- * @{
- */
-#define XUSBPS_TIMER0_LD_OFFSET 0x00000080
-#define XUSBPS_TIMER0_CTL_OFFSET 0x00000084
-/* @} */
-
-/** @name Timer Control Register bit mask
- *
- * @{
- */
-#define XUSBPS_TIMER_RUN_MASK 0x80000000
-#define XUSBPS_TIMER_STOP_MASK 0x80000000
-#define XUSBPS_TIMER_RESET_MASK 0x40000000
-#define XUSBPS_TIMER_REPEAT_MASK 0x01000000
-/* @} */
-
-/** @name Timer Control Register bit mask
- *
- * @{
- */
-#define XUSBPS_TIMER_COUNTER_MASK 0x00FFFFFF
-/* @} */
-
-/** @name Device Hardware Parameters
- *
- * @{
- */
-#define XUSBPS_HWDEVICE_OFFSET 0x0000000C
-
-#define XUSBPS_EP_NUM_MASK 0x3E
-#define XUSBPS_EP_NUM_SHIFT 1
-/* @} */
-
-/** @name Capability Register offsets
- */
-#define XUSBPS_HCSPARAMS_OFFSET 0x00000104
-
-/** @name Operational Register offsets.
- * Register comments are tagged with "H:" and "D:" for Host and Device modes,
- * respectively.
- * Tags are only present for registers that have a different meaning DEVICE and
- * HOST modes. Most registers are only valid for either DEVICE or HOST mode.
- * Those registers don't have tags.
- * @{
- */
-#define XUSBPS_CMD_OFFSET 0x00000140 /**< Configuration */
-#define XUSBPS_ISR_OFFSET 0x00000144 /**< Interrupt Status */
-#define XUSBPS_IER_OFFSET 0x00000148 /**< Interrupt Enable */
-#define XUSBPS_FRAME_OFFSET 0x0000014C /**< USB Frame Index */
-#define XUSBPS_LISTBASE_OFFSET 0x00000154 /**< H: Periodic List Base Address */
-#define XUSBPS_DEVICEADDR_OFFSET 0x00000154 /**< D: Device Address */
-#define XUSBPS_ASYNCLISTADDR_OFFSET 0x00000158 /**< H: Async List Address */
-#define XUSBPS_EPLISTADDR_OFFSET 0x00000158 /**< D: Endpoint List Addr */
-#define XUSBPS_TTCTRL_OFFSET 0x0000015C /**< TT Control */
-#define XUSBPS_BURSTSIZE_OFFSET 0x00000160 /**< Burst Size */
-#define XUSBPS_TXFILL_OFFSET 0x00000164 /**< Tx Fill Tuning */
-#define XUSBPS_ULPIVIEW_OFFSET 0x00000170 /**< ULPI Viewport */
-#define XUSBPS_EPNAKISR_OFFSET 0x00000178 /**< Endpoint NAK IRQ Status */
-#define XUSBPS_EPNAKIER_OFFSET 0x0000017C /**< Endpoint NAK IRQ Enable */
-#define XUSBPS_PORTSCR1_OFFSET 0x00000184 /**< Port Control/Status 1 */
-
-/* NOTE: The Port Control / Status Register index is 1-based. */
-#define XUSBPS_PORTSCRn_OFFSET(n) \
- (XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING))
-
-
-#define XUSBPS_OTGCSR_OFFSET 0x000001A4 /**< OTG Status and Control */
-#define XUSBPS_MODE_OFFSET 0x000001A8 /**< USB Mode */
-#define XUSBPS_EPSTAT_OFFSET 0x000001AC /**< Endpoint Setup Status */
-#define XUSBPS_EPPRIME_OFFSET 0x000001B0 /**< Endpoint Prime */
-#define XUSBPS_EPFLUSH_OFFSET 0x000001B4 /**< Endpoint Flush */
-#define XUSBPS_EPRDY_OFFSET 0x000001B8 /**< Endpoint Ready */
-#define XUSBPS_EPCOMPL_OFFSET 0x000001BC /**< Endpoint Complete */
-#define XUSBPS_EPCR0_OFFSET 0x000001C0 /**< Endpoint Control 0 */
-#define XUSBPS_EPCR1_OFFSET 0x000001C4 /**< Endpoint Control 1 */
-#define XUSBPS_EPCR2_OFFSET 0x000001C8 /**< Endpoint Control 2 */
-#define XUSBPS_EPCR3_OFFSET 0x000001CC /**< Endpoint Control 3 */
-#define XUSBPS_EPCR4_OFFSET 0x000001D0 /**< Endpoint Control 4 */
-
-#define XUSBPS_MAX_ENDPOINTS 12 /**< Number of supported Endpoints in
- * this core. */
-#define XUSBPS_EP_OUT_MASK 0x00000FFF /**< OUR (RX) endpoint mask */
-#define XUSBPS_EP_IN_MASK 0x0FFF0000 /**< IN (TX) endpoint mask */
-#define XUSBPS_EP_ALL_MASK 0x0FFF0FFF /**< Mask used for endpoint control
- * registers */
-#define XUSBPS_EPCRn_OFFSET(n) \
- (XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING))
-
-#define XUSBPS_EPFLUSH_RX_SHIFT 0
-#define XUSBPS_EPFLUSH_TX_SHIFT 16
-
-/* @} */
-
-
-
-/** @name Endpoint Control Register (EPCR) bit positions.
- * @{
- */
-
-/* Definitions for TX Endpoint bits */
-#define XUSBPS_EPCR_TXT_TYPE_SHIFT 18 /* < Endpoint Type - TX bit shift*/
-#define XUSBPS_EPCR_TXT_TYPE_MASK 0x000C0000 /* < Endpoint Type - TX read only*/
-#define XUSBPS_EPCR_TXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - TX */
-#define XUSBPS_EPCR_TXT_ISO_MASK 0x00040000 /**< Isochronous. Endpoint */
-#define XUSBPS_EPCR_TXT_BULK_MASK 0x00080000 /**< Bulk Endpoint - TX */
-#define XUSBPS_EPCR_TXT_INTR_MASK 0x000C0000 /**< Interrupt Endpoint */
-#define XUSBPS_EPCR_TXS_MASK 0x00010000 /**< Stall TX endpoint */
-#define XUSBPS_EPCR_TXE_MASK 0x00800000 /**< Transmit enable - TX */
-#define XUSBPS_EPCR_TXR_MASK 0x00400000 /**< Data Toggle Reset Bit */
-
-
-/* Definitions for RX Endpoint bits */
-#define XUSBPS_EPCR_RXT_TYPE_SHIFT 2 /* < Endpoint Type - RX bit shift*/
-#define XUSBPS_EPCR_RXT_TYPE_MASK 0x0000000C /**< Endpoint Type - RX read only*/
-#define XUSBPS_EPCR_RXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - RX */
-#define XUSBPS_EPCR_RXT_ISO_MASK 0x00000004 /**< Isochronous Endpoint */
-#define XUSBPS_EPCR_RXT_BULK_MASK 0x00000008 /**< Bulk Endpoint - RX */
-#define XUSBPS_EPCR_RXT_INTR_MASK 0x0000000C /**< Interrupt Endpoint */
-#define XUSBPS_EPCR_RXS_MASK 0x00000001 /**< Stall RX endpoint. */
-#define XUSBPS_EPCR_RXE_MASK 0x00000080 /**< Transmit enable. - RX */
-#define XUSBPS_EPCR_RXR_MASK 0x00000040 /**< Data Toggle Reset Bit */
-/* @} */
-
-
-/** @name USB Command Register (CR) bit positions.
- * @{
- */
-#define XUSBPS_CMD_RS_MASK 0x00000001 /**< Run/Stop */
-#define XUSBPS_CMD_RST_MASK 0x00000002 /**< Controller RESET */
-#define XUSBPS_CMD_FS01_MASK 0x0000000C /**< Frame List Size bit 0,1 */
-#define XUSBPS_CMD_PSE_MASK 0x00000010 /**< Periodic Sched Enable */
-#define XUSBPS_CMD_ASE_MASK 0x00000020 /**< Async Sched Enable */
-#define XUSBPS_CMD_IAA_MASK 0x00000040 /**< IRQ Async Advance Doorbell */
-#define XUSBPS_CMD_ASP_MASK 0x00000300 /**< Async Sched Park Mode Cnt */
-#define XUSBPS_CMD_ASPE_MASK 0x00000800 /**< Async Sched Park Mode Enbl */
-#define XUSBPS_CMD_SUTW_MASK 0x00002000 /**< Setup TripWire */
-#define XUSBPS_CMD_ATDTW_MASK 0x00004000 /**< Add dTD TripWire */
-#define XUSBPS_CMD_FS2_MASK 0x00008000 /**< Frame List Size bit 2 */
-#define XUSBPS_CMD_ITC_MASK 0x00FF0000 /**< IRQ Threshold Control */
-/* @} */
-
-
-/**
- * @name Interrupt Threshold
- * These definitions are used by software to set the maximum rate at which the
- * USB controller will generate interrupt requests. The interrupt interval is
- * given in number of micro-frames.
- *
- * USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF)
- * packet each and every 1ms. USB also defines a high-speed micro-frame with a
- * 125us frame time. For each micro-frame a SOF (Start Of Frame) packet is
- * generated. Data is sent in between the SOF packets. The interrupt threshold
- * defines how many micro-frames the controller waits before issuing an
- * interrupt after data has been received.
- *
- * For a threshold of 0 the controller will issue an interrupt immediately
- * after the last byte of the data has been received. For a threshold n>0 the
- * controller will wait for n micro-frames before issuing an interrupt.
- *
- * Therefore, a setting of 8 micro-frames (default) means that the controller
- * will issue at most 1 interrupt per millisecond.
- *
- * @{
- */
-#define XUSBPS_CMD_ITHRESHOLD_0 0x00 /**< Immediate interrupt. */
-#define XUSBPS_CMD_ITHRESHOLD_1 0x01 /**< 1 micro-frame */
-#define XUSBPS_CMD_ITHRESHOLD_2 0x02 /**< 2 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_4 0x04 /**< 4 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_8 0x08 /**< 8 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_16 0x10 /**< 16 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_32 0x20 /**< 32 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_64 0x40 /**< 64 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_MAX XUSBPS_CMD_ITHRESHOLD_64
-#define XUSBPS_CMD_ITHRESHOLD_DEFAULT XUSBPS_CMD_ITHRESHOLD_8
-/* @} */
-
-
-
-/** @name USB Interrupt Status Register (ISR) / Interrupt Enable Register (IER)
- * bit positions.
- * @{
- */
-#define XUSBPS_IXR_UI_MASK 0x00000001 /**< USB Transaction Complete */
-#define XUSBPS_IXR_UE_MASK 0x00000002 /**< Transaction Error */
-#define XUSBPS_IXR_PC_MASK 0x00000004 /**< Port Change Detect */
-#define XUSBPS_IXR_FRE_MASK 0x00000008 /**< Frame List Rollover */
-#define XUSBPS_IXR_AA_MASK 0x00000020 /**< Async Advance */
-#define XUSBPS_IXR_UR_MASK 0x00000040 /**< RESET Received */
-#define XUSBPS_IXR_SR_MASK 0x00000080 /**< Start of Frame */
-#define XUSBPS_IXR_SLE_MASK 0x00000100 /**< Device Controller Suspend */
-#define XUSBPS_IXR_ULPI_MASK 0x00000400 /**< ULPI IRQ */
-#define XUSBPS_IXR_HCH_MASK 0x00001000 /**< Host Controller Halted
- * Read Only */
-#define XUSBPS_IXR_RCL_MASK 0x00002000 /**< USB Reclamation Read Only */
-#define XUSBPS_IXR_PS_MASK 0x00004000 /**< Periodic Sched Status
- * Read Only */
-#define XUSBPS_IXR_AS_MASK 0x00008000 /**< Async Sched Status Read only */
-#define XUSBPS_IXR_NAK_MASK 0x00010000 /**< NAK IRQ */
-#define XUSBPS_IXR_UA_MASK 0x00040000 /**< USB Host Async IRQ */
-#define XUSBPS_IXR_UP_MASK 0x00080000 /**< USB Host Periodic IRQ */
-#define XUSBPS_IXR_TI0_MASK 0x01000000 /**< Timer 0 Interrupt */
-#define XUSBPS_IXR_TI1_MASK 0x02000000 /**< Timer 1 Interrupt */
-
-#define XUSBPS_IXR_ALL (XUSBPS_IXR_UI_MASK | \
- XUSBPS_IXR_UE_MASK | \
- XUSBPS_IXR_PC_MASK | \
- XUSBPS_IXR_FRE_MASK | \
- XUSBPS_IXR_AA_MASK | \
- XUSBPS_IXR_UR_MASK | \
- XUSBPS_IXR_SR_MASK | \
- XUSBPS_IXR_SLE_MASK | \
- XUSBPS_IXR_ULPI_MASK | \
- XUSBPS_IXR_HCH_MASK | \
- XUSBPS_IXR_RCL_MASK | \
- XUSBPS_IXR_PS_MASK | \
- XUSBPS_IXR_AS_MASK | \
- XUSBPS_IXR_NAK_MASK | \
- XUSBPS_IXR_UA_MASK | \
- XUSBPS_IXR_UP_MASK | \
- XUSBPS_IXR_TI0_MASK | \
- XUSBPS_IXR_TI1_MASK)
- /**< Mask for ALL IRQ types */
-/* @} */
-
-
-/** @name USB Mode Register (MODE) bit positions.
- * @{
- */
-#define XUSBPS_MODE_CM_MASK 0x00000003 /**< Controller Mode Select */
-#define XUSBPS_MODE_CM_IDLE_MASK 0x00000000
-#define XUSBPS_MODE_CM_DEVICE_MASK 0x00000002
-#define XUSBPS_MODE_CM_HOST_MASK 0x00000003
-#define XUSBPS_MODE_ES_MASK 0x00000004 /**< USB Endian Select */
-#define XUSBPS_MODE_SLOM_MASK 0x00000008 /**< USB Setup Lockout Mode Disable */
-#define XUSBPS_MODE_SDIS_MASK 0x00000010
-#define XUSBPS_MODE_VALID_MASK 0x0000001F
-
-/* @} */
-
-
-/** @name USB Device Address Register (DEVICEADDR) bit positions.
- * @{
- */
-#define XUSBPS_DEVICEADDR_DEVICEAADV_MASK 0x01000000
- /**< Device Addr Auto Advance */
-#define XUSBPS_DEVICEADDR_ADDR_MASK 0xFE000000
- /**< Device Address */
-#define XUSBPS_DEVICEADDR_ADDR_SHIFT 25
- /**< Address shift */
-#define XUSBPS_DEVICEADDR_MAX 127
- /**< Biggest allowed address */
-/* @} */
-
-/** @name USB TT Control Register (TTCTRL) bit positions.
- * @{
- */
-#define XUSBPS_TTCTRL_HUBADDR_MASK 0x7F000000 /**< TT Hub Address */
-/* @} */
-
-
-/** @name USB Burst Size Register (BURSTSIZE) bit posisions.
- * @{
- */
-#define XUSBPS_BURSTSIZE_RX_MASK 0x000000FF /**< RX Burst Length */
-#define XUSBPS_BURSTSIZE_TX_MASK 0x0000FF00 /**< TX Burst Length */
-/* @} */
-
-
-/** @name USB Tx Fill Tuning Register (TXFILL) bit positions.
- * @{
- */
-#define XUSBPS_TXFILL_OVERHEAD_MASK 0x000000FF
- /**< Scheduler Overhead */
-#define XUSBPS_TXFILL_HEALTH_MASK 0x00001F00
- /**< Scheduler Health Cntr */
-#define XUSBPS_TXFILL_BURST_MASK 0x003F0000
- /**< FIFO Burst Threshold */
-/* @} */
-
-
-/** @name USB ULPI Viewport Register (ULPIVIEW) bit positions.
- * @{
- */
-#define XUSBPS_ULPIVIEW_DATWR_MASK 0x000000FF /**< ULPI Data Write */
-#define XUSBPS_ULPIVIEW_DATRD_MASK 0x0000FF00 /**< ULPI Data Read */
-#define XUSBPS_ULPIVIEW_ADDR_MASK 0x00FF0000 /**< ULPI Data Address */
-#define XUSBPS_ULPIVIEW_PORT_MASK 0x07000000 /**< ULPI Port Number */
-#define XUSBPS_ULPIVIEW_SS_MASK 0x08000000 /**< ULPI Synchronous State */
-#define XUSBPS_ULPIVIEW_RW_MASK 0x20000000 /**< ULPI Read/Write Control */
-#define XUSBPS_ULPIVIEW_RUN_MASK 0x40000000 /**< ULPI Run */
-#define XUSBPS_ULPIVIEW_WU_MASK 0x80000000 /**< ULPI Wakeup */
-/* @} */
-
-
-/** @name Port Status Control Register bit positions.
- * @{
- */
-#define XUSBPS_PORTSCR_CCS_MASK 0x00000001 /**< Current Connect Status */
-#define XUSBPS_PORTSCR_CSC_MASK 0x00000002 /**< Connect Status Change */
-#define XUSBPS_PORTSCR_PE_MASK 0x00000004 /**< Port Enable/Disable */
-#define XUSBPS_PORTSCR_PEC_MASK 0x00000008 /**< Port Enable/Disable Change */
-#define XUSBPS_PORTSCR_OCA_MASK 0x00000010 /**< Over-current Active */
-#define XUSBPS_PORTSCR_OCC_MASK 0x00000020 /**< Over-current Change */
-#define XUSBPS_PORTSCR_FPR_MASK 0x00000040 /**< Force Port Resume */
-#define XUSBPS_PORTSCR_SUSP_MASK 0x00000080 /**< Suspend */
-#define XUSBPS_PORTSCR_PR_MASK 0x00000100 /**< Port Reset */
-#define XUSBPS_PORTSCR_HSP_MASK 0x00000200 /**< High Speed Port */
-#define XUSBPS_PORTSCR_LS_MASK 0x00000C00 /**< Line Status */
-#define XUSBPS_PORTSCR_PP_MASK 0x00001000 /**< Port Power */
-#define XUSBPS_PORTSCR_PO_MASK 0x00002000 /**< Port Owner */
-#define XUSBPS_PORTSCR_PIC_MASK 0x0000C000 /**< Port Indicator Control */
-#define XUSBPS_PORTSCR_PTC_MASK 0x000F0000 /**< Port Test Control */
-#define XUSBPS_PORTSCR_WKCN_MASK 0x00100000 /**< Wake on Connect Enable */
-#define XUSBPS_PORTSCR_WKDS_MASK 0x00200000 /**< Wake on Disconnect Enable */
-#define XUSBPS_PORTSCR_WKOC_MASK 0x00400000 /**< Wake on Over-current Enable */
-#define XUSBPS_PORTSCR_PHCD_MASK 0x00800000 /**< PHY Low Power Suspend -
- * Clock Disable */
-#define XUSBPS_PORTSCR_PFSC_MASK 0x01000000 /**< Port Force Full Speed
- * Connect */
-#define XUSBPS_PORTSCR_PSPD_MASK 0x0C000000 /**< Port Speed */
-/* @} */
-
-
-/** @name On-The-Go Status Control Register (OTGCSR) bit positions.
- * @{
- */
-#define XUSBPS_OTGSC_VD_MASK 0x00000001 /**< VBus Discharge Bit */
-#define XUSBPS_OTGSC_VC_MASK 0x00000002 /**< VBus Charge Bit */
-#define XUSBPS_OTGSC_HAAR_MASK 0x00000004 /**< HW Assist Auto Reset
- * Enable Bit */
-#define XUSBPS_OTGSC_OT_MASK 0x00000008 /**< OTG Termination Bit */
-#define XUSBPS_OTGSC_DP_MASK 0x00000010 /**< Data Pulsing Pull-up
- * Enable Bit */
-#define XUSBPS_OTGSC_IDPU_MASK 0x00000020 /**< ID Pull-up Enable Bit */
-#define XUSBPS_OTGSC_HADP_MASK 0x00000040 /**< HW Assist Data Pulse
- * Enable Bit */
-#define XUSBPS_OTGSC_HABA_MASK 0x00000080 /**< USB Hardware Assist
- * B Disconnect to A
- * Connect Enable Bit */
-#define XUSBPS_OTGSC_ID_MASK 0x00000100 /**< ID Status Flag */
-#define XUSBPS_OTGSC_AVV_MASK 0x00000200 /**< USB A VBus Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_ASV_MASK 0x00000400 /**< USB A Session Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_BSV_MASK 0x00000800 /**< USB B Session Valid Status Flag */
-#define XUSBPS_OTGSC_BSE_MASK 0x00001000 /**< USB B Session End Status Flag */
-#define XUSBPS_OTGSC_1MST_MASK 0x00002000 /**< USB 1 Millisecond Timer Status Flag */
-#define XUSBPS_OTGSC_DPS_MASK 0x00004000 /**< Data Pulse Status Flag */
-#define XUSBPS_OTGSC_IDIS_MASK 0x00010000 /**< USB ID Interrupt Status Flag */
-#define XUSBPS_OTGSC_AVVIS_MASK 0x00020000 /**< USB A VBus Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_ASVIS_MASK 0x00040000 /**< USB A Session Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_BSVIS_MASK 0x00080000 /**< USB B Session Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_BSEIS_MASK 0x00100000 /**< USB B Session End Interrupt Status Flag */
-#define XUSBPS_OTGSC_1MSS_MASK 0x00200000 /**< 1 Millisecond Timer Interrupt Status Flag */
-#define XUSBPS_OTGSC_DPIS_MASK 0x00400000 /**< Data Pulse Interrupt Status Flag */
-#define XUSBPS_OTGSC_IDIE_MASK 0x01000000 /**< ID Interrupt Enable Bit */
-#define XUSBPS_OTGSC_AVVIE_MASK 0x02000000 /**< USB A VBus Valid Interrupt Enable Bit */
-#define XUSBPS_OTGSC_ASVIE_MASK 0x04000000 /**< USB A Session Valid Interrupt Enable Bit */
-#define XUSBPS_OTGSC_BSVIE_MASK 0x08000000 /**< USB B Session Valid Interrupt Enable Bit */
-#define XUSBPS_OTGSC_BSEE_MASK 0x10000000 /**< USB B Session End Interrupt Enable Bit */
-#define XUSBPS_OTGSC_1MSE_MASK 0x20000000 /**< 1 Millisecond Timer
- * Interrupt Enable Bit */
-#define XUSBPS_OTGSC_DPIE_MASK 0x40000000 /**< Data Pulse Interrupt
- * Enable Bit */
-
-#define XUSBPS_OTG_ISB_ALL (XUSBPS_OTGSC_IDIS_MASK |\
- XUSBPS_OTGSC_AVVIS_MASK | \
- XUSBPS_OTGSC_ASVIS_MASK | \
- XUSBPS_OTGSC_BSVIS_MASK | \
- XUSBPS_OTGSC_BSEIS_MASK | \
- XUSBPS_OTGSC_1MSS_MASK | \
- XUSBPS_OTGSC_DPIS_MASK)
- /** Mask for All IRQ status masks */
-
-#define XUSBPS_OTG_IEB_ALL (XUSBPS_OTGSC_IDIE_MASK |\
- XUSBPS_OTGSC_AVVIE_MASK | \
- XUSBPS_OTGSC_ASVIE_MASK | \
- XUSBPS_OTGSC_BSVIE_MASK | \
- XUSBPS_OTGSC_BSEE_IEB_MASK | \
- XUSBPS_OTGSC_1MSE_MASK | \
- XUSBPS_OTGSC_DPIE_MASK)
- /** Mask for All IRQ Enable masks */
-/* @} */
-
-
-/**< Alignment of the Device Queue Head List BASE. */
-#define XUSBPS_dQH_BASE_ALIGN 2048
-
-/**< Alignment of a Device Queue Head structure. */
-#define XUSBPS_dQH_ALIGN 64
-
-/**< Alignment of a Device Transfer Descriptor structure. */
-#define XUSBPS_dTD_ALIGN 32
-
-/**< Size of one RX buffer for a OUT Transfer Descriptor. */
-#define XUSBPS_dTD_BUF_SIZE 4096
-
-/**< Maximum size of one RX/TX buffer. */
-#define XUSBPS_dTD_BUF_MAX_SIZE 16*1024
-
-/**< Alignment requirement for Transfer Descriptor buffers. */
-#define XUSBPS_dTD_BUF_ALIGN 4096
-
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* This macro reads the given register.
-*
-* @param BaseAddress is the base address for the USB registers.
-* @param RegOffset is the register offset to be read.
-*
-* @return The 32-bit value of the register.
-*
-* @note C-style signature:
-* u32 XUsbPs_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XUsbPs_ReadReg(BaseAddress, RegOffset) \
- Xil_In32(BaseAddress + (RegOffset))
-
-
-/****************************************************************************/
-/**
-*
-* This macro writes the given register.
-*
-* @param BaseAddress is the the base address for the USB registers.
-* @param RegOffset is the register offset to be written.
-* @param Data is the the 32-bit value to write to the register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XUsbPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
- *****************************************************************************/
-#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data) \
- Xil_Out32(BaseAddress + (RegOffset), (Data))
-
-
-/************************** Function Prototypes ******************************/
-/*
- * Perform reset operation to the USB PS interface
- */
-void XUsbPs_ResetHw(u32 BaseAddress);
-/************************** Variable Definitions ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XUSBPS_L_H */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a4/a0e584575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a4/a0e584575243001d18b399c1eb9b3628
deleted file mode 100644
index 60f4ba3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a4/a0e584575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,53 +0,0 @@
-/******************************************************************************
-* Copyright (c) 1995 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-*******************************************************************************/
- #ifndef XIL_PRINTF_H
- #define XIL_PRINTF_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include
-#include
-#include
-#include "xil_types.h"
-#include "xparameters.h"
-#include "bspconfig.h"
-#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
-#include "xen_console.h"
-#endif
-
-/*----------------------------------------------------*/
-/* Use the following parameter passing structure to */
-/* make xil_printf re-entrant. */
-/*----------------------------------------------------*/
-
-struct params_s;
-
-
-/*---------------------------------------------------*/
-/* The purpose of this routine is to output data the */
-/* same as the standard printf function without the */
-/* overhead most run-time libraries involve. Usually */
-/* the printf brings in many kilobytes of code and */
-/* that is unacceptable in most embedded systems. */
-/*---------------------------------------------------*/
-
-typedef char8* charptr;
-typedef s32 (*func_ptr)(int c);
-
-/* */
-
-void xil_printf( const char8 *ctrl1, ...);
-void xil_vprintf(const char8 *ctrl1, va_list argp);
-void print( const char8 *ptr);
-extern void outbyte (char8 c);
-extern char8 inbyte(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a4/a1449c545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a4/a1449c545243001d18b399c1eb9b3628
deleted file mode 100644
index 33822bf..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a4/a1449c545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,843 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
- *
- * @file xemacps.h
-* @addtogroup emacps_v3_15
-* @{
-* @details
- *
- * The Xilinx Embedded Processor Block Ethernet driver.
- *
- * For a full description of XEMACPS features, please see the hardware spec.
- * This driver supports the following features:
- * - Memory mapped access to host interface registers
- * - Statistics counter registers for RMON/MIB
- * - API for interrupt driven frame transfers for hardware configured DMA
- * - Virtual memory support
- * - Unicast, broadcast, and multicast receive address filtering
- * - Full and half duplex operation
- * - Automatic PAD & FCS insertion and stripping
- * - Flow control
- * - Support up to four 48bit addresses
- * - Address checking for four specific 48bit addresses
- * - VLAN frame support
- * - Pause frame support
- * - Large frame support up to 1536 bytes
- * - Checksum offload
- *
- * Driver Description
- *
- * The device driver enables higher layer software (e.g., an application) to
- * communicate to the XEmacPs. The driver handles transmission and reception
- * of Ethernet frames, as well as configuration and control. No pre or post
- * processing of frame data is performed. The driver does not validate the
- * contents of an incoming frame in addition to what has already occurred in
- * hardware.
- * A single device driver can support multiple devices even when those devices
- * have significantly different configurations.
- *
- * Initialization & Configuration
- *
- * The XEmacPs_Config structure is used by the driver to configure itself.
- * This configuration structure is typically created by the tool-chain based
- * on hardware build properties.
- *
- * The driver instance can be initialized in
- *
- * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a
- * configuration structure provided by the caller. If running in a system
- * with address translation, the provided virtual memory base address
- * replaces the physical address present in the configuration structure.
- *
- * The device supports DMA only as current development plan. No FIFO mode is
- * supported. The driver expects to start the DMA channels and expects that
- * the user has set up the buffer descriptor lists.
- *
- * Interrupts and Asynchronous Callbacks
- *
- * The driver has no dependencies on the interrupt controller. When an
- * interrupt occurs, the handler will perform a small amount of
- * housekeeping work, determine the source of the interrupt, and call the
- * appropriate callback function. All callbacks are registered by the user
- * level application.
- *
- * Virtual Memory
- *
- * All virtual to physical memory mappings must occur prior to accessing the
- * driver API.
- *
- * For DMA transactions, user buffers supplied to the driver must be in terms
- * of their physical address.
- *
- * DMA
- *
- * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
- * These BDs are typically chained together into a list the hardware follows
- * when transferring data in and out of the packet buffers. Each BD describes
- * a memory region containing either a full or partial Ethernet packet.
- *
- * Interrupt coalescing is not supported from this built-in DMA engine.
- *
- * This API requires the user to understand how the DMA operates. The
- * following paragraphs provide some explanation, but the user is encouraged
- * to read documentation in xemacps_bdring.h as well as study example code
- * that accompanies this driver.
- *
- * The API is designed to get BDs to and from the DMA engine in the most
- * efficient means possible. The first step is to establish a memory region
- * to contain all BDs for a specific channel. This is done with
- * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
- * follow as BDs are processed. The ring will consist of a user defined number
- * of BDs which will all be partially initialized. For example on the transmit
- * channel, the driver will initialize all BDs' so that they are configured
- * for transmit. The more fields that can be permanently setup at
- * initialization, then the fewer accesses will be needed to each BD while
- * the DMA engine is in operation resulting in better throughput and CPU
- * utilization. The best case initialization would require the user to set
- * only a frame buffer address and length prior to submitting the BD to the
- * engine.
- *
- * BDs move through the engine with the help of functions
- * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
- * and XEmacPs_BdRingFree().
- * All these functions handle BDs that are in place. That is, there are no
- * copies of BDs kept anywhere and any BD the user interacts with is an actual
- * BD from the same ring hardware accesses.
- *
- * BDs in the ring go through a series of states as follows:
- * 1. Idle. The driver controls BDs in this state.
- * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
- * reserve BD(s). Once allocated, the user may setup the BD(s) with
- * frame buffer address, length, and other attributes. The user controls
- * BDs in this state.
- * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
- * in this state are either waiting to be processed by hardware, are in
- * process, or have been processed. The DMA engine controls BDs in this
- * state.
- * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
- * user. Once retrieved, the user can examine each BD for the outcome of
- * the DMA transfer. The user controls BDs in this state. After examining
- * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
- * into state 1.
- *
- * Each of the four BD accessor functions operate on a set of BDs. A set is
- * defined as a segment of the BD ring consisting of one or more BDs. The user
- * views the set as a pointer to the first BD along with the number of BDs for
- * that set. The set can be navigated by using macros XEmacPs_BdNext(). The
- * user must exercise extreme caution when changing BDs in a set as there is
- * nothing to prevent doing a mBdNext past the end of the set and modifying a
- * BD out of bounds.
- *
- * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
- * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
- * tandem. The same BD set retrieved with BdRingAlloc should be the same one
- * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
- * BdRIngFree.
- *
- * Alignment & Data Cache Restrictions
- *
- * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
- * aligned. Please reference xemacps_bd.h for cache related macros.
- *
- * DMA Tx:
- *
- * - If frame buffers exist in cached memory, then they must be flushed
- * prior to committing them to hardware.
- *
- * DMA Rx:
- *
- * - If frame buffers exist in cached memory, then the cache must be
- * invalidated for the memory region containing the frame prior to data
- * access
- *
- * Both cache invalidate/flush are taken care of in driver code.
- *
- * Buffer Copying
- *
- * The driver is designed for a zero-copy buffer scheme. That is, the driver
- * will not copy buffers. This avoids potential throughput bottlenecks within
- * the driver. If byte copying is required, then the transfer will take longer
- * to complete.
- *
- * Checksum Offloading
- *
- * The Embedded Processor Block Ethernet can be configured to perform IP, TCP
- * and UDP checksum offloading in both receive and transmit directions.
- *
- * IP packets contain a 16-bit checksum field, which is the 16-bit 1s
- * complement of the 1s complement sum of all 16-bit words in the header.
- * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
- * 1s complement of the 1s complement sum of all 16-bit words in the header,
- * the data and a conceptual pseudo header.
- *
- * To calculate these checksums in software requires each byte of the packet
- * to be read. For TCP and UDP this can use a large amount of processing power.
- * Offloading the checksum calculation to hardware can result in significant
- * performance improvements.
- *
- * The transmit checksum offload is only available to use DMA in packet buffer
- * mode. This is because the complete frame to be transmitted must be read
- * into the packet buffer memory before the checksum can be calculated and
- * written to the header at the beginning of the frame.
- *
- * For IP, TCP or UDP receive checksum offload to be useful, the operating
- * system containing the protocol stack must be aware that this offload is
- * available so that it can make use of the fact that the hardware has verified
- * the checksum.
- *
- * When receive checksum offloading is enabled in the hardware, the IP header
- * checksum is checked, where the packet meets the following criteria:
- *
- * 1. If present, the VLAN header must be four octets long and the CFI bit
- * must not be set.
- * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
- * encoding.
- * 3. IP v4 packet.
- * 4. IP header is of a valid length.
- * 5. Good IP header checksum.
- * 6. No IP fragmentation.
- * 7. TCP or UDP packet.
- *
- * When an IP, TCP or UDP frame is received, the receive buffer descriptor
- * gives an indication if the hardware was able to verify the checksums.
- * There is also an indication if the frame had SNAP encapsulation. These
- * indication bits will replace the type ID match indication bits when the
- * receive checksum offload is enabled.
- *
- * If any of the checksums are verified incorrect by the hardware, the packet
- * is discarded and the appropriate statistics counter incremented.
- *
- * PHY Interfaces
- *
- * RGMII 1.3 is the only interface supported.
- *
- * Asserts
- *
- * Asserts are used within all Xilinx drivers to enforce constraints on
- * parameters. Asserts can be turned off on a system-wide basis by defining,
- * at compile time, the NDEBUG identifier. By default, asserts are turned on
- * and it is recommended that users leave asserts on during development. For
- * deployment use -DNDEBUG compiler switch to remove assert code.
- *
- * @note
- *
- * Xilinx drivers are typically composed of two parts, one is the driver
- * and the other is the adapter. The driver is independent of OS and processor
- * and is intended to be highly portable. The adapter is OS-specific and
- * facilitates communication between the driver and an OS.
- * This driver is intended to be RTOS and processor independent. Any needs for
- * dynamic memory management, threads or thread mutual exclusion, or cache
- * control must be satisfied bythe layer above this driver.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -------------------------------------------------------
- * 1.00a wsy 01/10/10 First release
- * 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file
- * xemacps_bdring.c is modified. Earlier it was checking for
- * "BdLimit"(passed argument) number of BDs for finding out
- * which BDs are successfully processed. Now one more check
- * is added. It looks for BDs till the current BD pointer
- * reaches HwTail. By doing this processing time is saved.
- * 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
- * xemacps_bdring.c is modified. Now start of packet is
- * searched for returning the number of BDs processed.
- * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
- * registers. Added a new API to set the bust length.
- * Added some new hash-defines.
- * 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for
- * Rx errors. Under heavy Rx traffic, there will be a large
- * number of errors related to receive buffer not available.
- * Because of a HW bug (SI #692601), under such heavy errors,
- * the Rx data path can become unresponsive. To reduce the
- * probabilities for hitting this HW bug, the SW writes to
- * bit 18 to flush a packet from Rx DPRAM immediately. The
- * changes for it are done in the function
- * XEmacPs_IntrHandler.
- * 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
- * removed. It is expected that all BDs are allocated in
- * from uncached area.
- * 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
- * to 0x1fff. This fixes the CR#744902.
- * Made changes in example file xemacps_example.h to fix compilation
- * issues with iarcc compiler.
- * 2.0 adk 10/12/13 Updated as per the New Tcl API's
- * 2.1 adk 11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
- * 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy
- * address in xparameters.h when GMII to RGMII converter
- * is present in hw.
- * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
- * changes.
- * 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
- * 1000BASE-X mode export proper values to the xparameters.h
- * file. Changes are made in the driver tcl file.
- * 3.0 adk 08/1/15 Don't include gem in peripheral test when gem is
- * configured with PCS/PMA Core. Changes are made in the
- * test app tcl(CR:827686).
- * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
- * 3.0 hk 03/18/15 Added support for jumbo frames. Increase AHB burst.
- * Disable extended mode. Perform all 64 bit changes under
- * check for arch64.
- * Remove "used bit set" from TX error interrupt masks.
- * 3.1 hk 07/27/15 Do not call error handler with '0' error code when
- * there is no error. CR# 869403
- * 08/10/15 Update upper 32 bit tx and rx queue ptr registers.
- * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
- * 3.4 ms 01/23/17 Modified xil_printf statement in main function for all
- * examples to ensure that "Successfully ran" and "Failed"
- * strings are available in all examples. This is a fix
- * for CR-965028.
- * ms 03/17/17 Modified text file in examples folder for doxygen
- * generation.
- * ms 04/05/17 Added tabspace for return statements in functions of
- * xemacps_ieee1588_example.c for proper documentation
- * while generating doxygen.
- * 3.5 hk 08/14/17 Update cache coherency information of the interface in
- * its config structure.
- * 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
- * changed to volatile.
- * Add API XEmacPs_BdRingPtrReset() to reset pointers
- * 3.8 hk 07/19/18 Fixed CPP, GCC and doxygen warnings - CR-1006327
- * hk 09/17/18 Fix PTP interrupt masks and cleanup comments.
- * 3.9 hk 01/23/19 Add RX watermark support
- * 3.11 sd 02/14/20 Add clock support
- * 3.13 nsk 12/14/20 Updated the tcl to not to use the instance names.
- *
- *
- *
- ****************************************************************************/
-
-#ifndef XEMACPS_H /* prevent circular inclusions */
-#define XEMACPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xemacps_hw.h"
-#include "xemacps_bd.h"
-#include "xemacps_bdring.h"
-#if defined (XCLOCKING)
-#include "xil_clocking.h"
-#endif
-
-/************************** Constant Definitions ****************************/
-
-/*
- * Device information
- */
-#define XEMACPS_DEVICE_NAME "xemacps"
-#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC"
-
-
-/** @name Configuration options
- *
- * Device configuration options. See the XEmacPs_SetOptions(),
- * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
- * use options.
- *
- * The default state of the options are noted and are what the device and
- * driver will be set to after calling XEmacPs_Reset() or
- * XEmacPs_Initialize().
- *
- * @{
- */
-
-#define XEMACPS_PROMISC_OPTION 0x00000001U
-/**< Accept all incoming packets.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_FRAME1536_OPTION 0x00000002U
-/**< Frame larger than 1516 support for Tx & Rx.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_VLAN_OPTION 0x00000004U
-/**< VLAN Rx & Tx frame support.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U
-/**< Enable recognition of flow control frames on Rx
- * This option defaults to enabled (set) */
-
-#define XEMACPS_FCS_STRIP_OPTION 0x00000020U
-/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
- * stripped.
- * This option defaults to enabled (set) */
-
-#define XEMACPS_FCS_INSERT_OPTION 0x00000040U
-/**< Generate FCS field and add PAD automatically for outgoing frames.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U
-/**< Enable Length/Type error checking for incoming frames. When this option is
- * set, the MAC will filter frames that have a mismatched type/length field
- * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
- * types of frames are encountered. When this option is cleared, the MAC will
- * allow these types of frames to be received.
- *
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U
-/**< Enable the transmitter.
- * This option defaults to enabled (set) */
-
-#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U
-/**< Enable the receiver
- * This option defaults to enabled (set) */
-
-#define XEMACPS_BROADCAST_OPTION 0x00000400U
-/**< Allow reception of the broadcast address
- * This option defaults to enabled (set) */
-
-#define XEMACPS_MULTICAST_OPTION 0x00000800U
-/**< Allows reception of multicast addresses programmed into hash
- * This option defaults to disabled (clear) */
-
-#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U
-/**< Enable the RX checksum offload
- * This option defaults to enabled (set) */
-
-#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U
-/**< Enable the TX checksum offload
- * This option defaults to enabled (set) */
-
-#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U
-#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U
-
-#define XEMACPS_DEFAULT_OPTIONS \
- ((u32)XEMACPS_FLOW_CONTROL_OPTION | \
- (u32)XEMACPS_FCS_INSERT_OPTION | \
- (u32)XEMACPS_FCS_STRIP_OPTION | \
- (u32)XEMACPS_BROADCAST_OPTION | \
- (u32)XEMACPS_LENTYPE_ERR_OPTION | \
- (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
- (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
- (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
- (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
-
-/**< Default options set when device is initialized or reset */
-/*@}*/
-
-/** @name Callback identifiers
- *
- * These constants are used as parameters to XEmacPs_SetHandler()
- * @{
- */
-#define XEMACPS_HANDLER_DMASEND 1U
-#define XEMACPS_HANDLER_DMARECV 2U
-#define XEMACPS_HANDLER_ERROR 3U
-/*@}*/
-
-/* Constants to determine the configuration of the hardware device. They are
- * used to allow the driver to verify it can operate with the hardware.
- */
-#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */
-
-/* The next few constants help upper layers determine the size of memory
- * pools used for Ethernet buffers and descriptor lists.
- */
-#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */
-
-#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */
-#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */
-#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */
-#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
-#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
-#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
- XEMACPS_TRL_SIZE)
-#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
- XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
-#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
- XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
-
-/* DMACR Bust length hash defines */
-
-#define XEMACPS_SINGLE_BURST 0x00000001
-#define XEMACPS_4BYTE_BURST 0x00000004
-#define XEMACPS_8BYTE_BURST 0x00000008
-#define XEMACPS_16BYTE_BURST 0x00000010
-
-
-/**************************** Type Definitions ******************************/
-/** @name Typedefs for callback functions
- *
- * These callbacks are invoked in interrupt context.
- * @{
- */
-/**
- * Callback invoked when frame(s) have been sent or received in interrupt
- * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
- *
- * @param CallBackRef is user data assigned when the callback was set.
- *
- * @note
- * See xemacps_hw.h for bitmasks definitions and the device hardware spec for
- * further information on their meaning.
- *
- */
-typedef void (*XEmacPs_Handler) (void *CallBackRef);
-
-/**
- * Callback when an asynchronous error occurs. To set this callback, invoke
- * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
- * parameter.
- *
- * @param CallBackRef is user data assigned when the callback was set.
- * @param Direction defines either receive or transmit error(s) has occurred.
- * @param ErrorWord definition varies with Direction
- *
- */
-typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
- u32 ErrorWord);
-
-/*@}*/
-
-/**
- * This typedef contains configuration information for a device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
- u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
- * describes whether Cache Coherent or not */
-#if defined (XCLOCKING)
- u32 RefClk; /**< Input clock */
-#endif
- u16 S1GDiv0; /**< 1Gbps Clock Divider 0 */
- u8 S1GDiv1; /**< 1Gbps Clock Divider 1 */
- u16 S100MDiv0; /**< 100Mbps Clock Divider 0 */
- u8 S100MDiv1; /**< 100Mbps Clock Divider 1 */
- u16 S10MDiv0; /**< 10Mbps Clock Divider 0 */
- u8 S10MDiv1; /**< 10Mbps Clock Divider 1 */
-} XEmacPs_Config;
-
-
-/**
- * The XEmacPs driver instance data. The user is required to allocate a
- * structure of this type for every XEmacPs device in the system. A pointer
- * to a structure of this type is then passed to the driver API functions.
- */
-typedef struct XEmacPs_Instance {
- XEmacPs_Config Config; /* Hardware configuration */
- u32 IsStarted; /* Device is currently started */
- u32 IsReady; /* Device is initialized and ready */
- u32 Options; /* Current options word */
-
- XEmacPs_BdRing TxBdRing; /* Transmit BD ring */
- XEmacPs_BdRing RxBdRing; /* Receive BD ring */
-
- XEmacPs_Handler SendHandler;
- XEmacPs_Handler RecvHandler;
- void *SendRef;
- void *RecvRef;
-
- XEmacPs_ErrHandler ErrorHandler;
- void *ErrorRef;
- u32 Version;
- u32 RxBufMask;
- u32 MaxMtuSize;
- u32 MaxFrameSize;
- u32 MaxVlanFrameSize;
-
-} XEmacPs;
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* Retrieve the Tx ring object. This object can be used in the various Ring
-* API functions.
-*
-* @param InstancePtr is the DMA channel to operate on.
-*
-* @return TxBdRing attribute
-*
-* @note
-* C-style signature:
-* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
-
-/****************************************************************************/
-/**
-* Retrieve the Rx ring object. This object can be used in the various Ring
-* API functions.
-*
-* @param InstancePtr is the DMA channel to operate on.
-*
-* @return RxBdRing attribute
-*
-* @note
-* C-style signature:
-* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
-
-/****************************************************************************/
-/**
-*
-* Enable interrupts specified in Mask. The corresponding interrupt for
-* each bit set to 1 in Mask, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to enable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntEnable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_IER_OFFSET, \
- ((Mask) & XEMACPS_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Disable interrupts specified in Mask. The corresponding interrupt for
-* each bit set to 1 in Mask, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to disable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntDisable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_IDR_OFFSET, \
- ((Mask) & XEMACPS_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Enable interrupts specified in Mask. The corresponding interrupt for
-* each bit set to 1 in Mask, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to enable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_INTQ1_IER_OFFSET, \
- ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Disable interrupts specified in Mask. The corresponding interrupt for
-* each bit set to 1 in Mask, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to disable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_INTQ1_IDR_OFFSET, \
- ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* This macro triggers trasmit circuit to send data currently in TX buffer(s).
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return
-*
-* @note
-*
-* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_Transmit(InstancePtr) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_NWCTRL_OFFSET, \
- (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
-
-/****************************************************************************/
-/**
-*
-* This macro determines if the device is configured with checksum offloading
-* on the receive channel
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return
-*
-* Boolean TRUE if the device is configured with checksum offloading, or
-* FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_IsRxCsum(InstancePtr) \
- ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
- ? TRUE : FALSE)
-
-/****************************************************************************/
-/**
-*
-* This macro determines if the device is configured with checksum offloading
-* on the transmit channel
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return
-*
-* Boolean TRUE if the device is configured with checksum offloading, or
-* FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_IsTxCsum(InstancePtr) \
- ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
- ? TRUE : FALSE)
-
-/************************** Function Prototypes *****************************/
-
-/****************************************************************************/
-/**
-*
-* This macro sets RX watermark register.
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-* @param High is the non-zero RX high watermark value. When SRAM fill level
-* is above this, a pause frame will be sent.
-* @param Low is the non-zero RX low watermark value. When SRAM fill level
-* is below this, a zero length pause frame will be sent IF the last
-* pause frame sent was non-zero.
-*
-* @return None
-*
-* @note
-*
-* Signature: void XEmacPs_SetRXWatermark(XEmacPs *InstancePtr, u16 High,
-* u16 Low)
-*
-*****************************************************************************/
-#define XEmacPs_SetRXWatermark(InstancePtr, High, Low) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_RXWATERMARK_OFFSET, \
- (High & XEMACPS_RXWM_HIGH_MASK) | \
- ((Low << XEMACPS_RXWM_LOW_SHFT_MSK) & XEMACPS_RXWM_LOW_MASK) |)
-
-/****************************************************************************/
-/**
-*
-* This macro gets RX watermark register.
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return RX watermark register value
-*
-* @note
-*
-* Signature: void XEmacPs_GetRXWatermark(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_GetRXWatermark(InstancePtr) \
- XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_RXWATERMARK_OFFSET)
-/*
- * Initialization functions in xemacps.c
- */
-LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
- UINTPTR EffectiveAddress);
-void XEmacPs_Start(XEmacPs *InstancePtr);
-void XEmacPs_Stop(XEmacPs *InstancePtr);
-void XEmacPs_Reset(XEmacPs *InstancePtr);
-void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
- u16 Direction);
-
-/*
- * Lookup configuration in xemacps_sinit.c
- */
-XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
-
-/*
- * Interrupt-related functions in xemacps_intr.c
- * DMA only and FIFO is not supported. This DMA does not support coalescing.
- */
-LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
- void *FuncPointer, void *CallBackRef);
-void XEmacPs_IntrHandler(void *XEmacPsPtr);
-
-/*
- * MAC configuration/control functions in XEmacPs_control.c
- */
-LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
-LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
-u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
-
-LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
-LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
-void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
-
-LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
-void XEmacPs_ClearHash(XEmacPs *InstancePtr);
-void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
-
-void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
- XEmacPs_MdcDiv Divisor);
-void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
-u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
-LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
- u32 RegisterNum, u16 *PhyDataPtr);
-LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
- u32 RegisterNum, u16 PhyData);
-LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
-
-LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
-void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a4/e13224585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a4/e13224585243001d18b399c1eb9b3628
deleted file mode 100644
index 8d11ff8..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a4/e13224585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,365 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xscuwdt.h
-* @addtogroup scuwdt_v2_4
-* @{
-* @details
-*
-* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private
-* watchdog timer hardware.
-*
-* The XScuWdt driver supports the following features:
-* - Watchdog mode
-* - Timer mode
-* - Auto reload (timer mode only)
-*
-* The watchdog counter register is a down counter and starts decrementing when
-* the watchdog is started.
-* In watchdog mode, when the counter reaches 0, the Reset flag is set in the
-* Reset status register and the WDRESETREQ pin is asserted, causing a system
-* reset. The Reset flag is not reset by normal processor reset and is cleared
-* when written with a value of 1. This enables the user to differentiate a
-* normal reset and a reset caused by watchdog time-out. The user needs to call
-* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out.
-*
-* The IsWdtExpired function can be used to check if the watchdog was the cause
-* of the last reset. In this situation, call Initialize then call IsWdtExpired.
-* If the result is true, watchdog timeout caused the last system reset. The
-* application then needs to clear the Reset flag.
-*
-* In timer mode, when the counter reaches 0, the Event flag is set in the
-* Interrupt status register and if interrupts are enabled, interrupt ID 30 is
-* set as pending in the interrupt distributor. The IsTimerExpired function
-* is used to check if the watchdog counter has decremented to 0 in timer mode.
-* If auto-reload mode is enabled, the Counter register is automatically reloaded
-* from the Load register.
-*
-* Initialization and Configuration
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate with the Watchdog Timer.
-*
-* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The
-* user needs to first call the XScuWdt_LookupConfig() API which returns
-* the Configuration structure pointer which is passed as a parameter to
-* the XScuWdt_CfgInitialize() API.
-*
-* Interrupts
-*
-* The SCU Watchdog Timer supports interrupts in Timer mode.
-*
-* This driver does not provide a Interrupt Service Routine (ISR) for the device.
-* It is the responsibility of the application to provide one if needed. Refer to
-* the interrupt example provided with this driver for details on using the
-* Timer in interrupt mode.
-*
-* Virtual Memory
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-* Threads
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* Asserts
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* Building the driver
-*
-* The XScuWdt driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-*
-*
-* NOTE:
-* The watchdog timer is not a part of the snoop control unit as indicated
-* by the prefix "scu" in the name of the driver.
-* It is an independent module in APU.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 2.3 mus 08/31/20 Updated makefile to support parallel make and
-* incremental builds. It would help to reduce compilaton
-* time.
-* 2.3 sne 09/16/20 Fixed MISRA-C violations.
-* 2.4 sne 02/04/21 Fixed Doxygen warnings.
-*
-*
-******************************************************************************/
-#ifndef XSCUWDT_H /**< prevent circular inclusions */
-#define XSCUWDT_H /**< by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xscuwdt_hw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddr; /**< Base address of the device */
-} XScuWdt_Config;
-
-/**
- * The XScuWdt driver instance data. The user is required to allocate a
- * variable of this type for every watchdog/timer device in the system.
- * A pointer to a variable of this type is then passed to the driver API
- * functions.
- */
-typedef struct {
- XScuWdt_Config Config;/**< Hardware Configuration */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStarted; /**< Device watchdog timer is running */
-} XScuWdt;
-
-/************************** Variable Definitions *****************************/
-extern XScuWdt_Config XScuWdt_ConfigTable[];
-
-/***************** Macros (Inline Functions) Definitions *********************/
-/****************************************************************************/
-/**
-*
-* This function is used to check if the watchdog has timed-out and the last
-* reset was caused by the watchdog reset.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return
-* - TRUE if the watchdog has expired.
-* - FALSE if the watchdog has not expired.
-*
-* @note C-style signature:
-* int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_IsWdtExpired(InstancePtr) \
- ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_RST_STS_OFFSET) & \
- XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
-
-/****************************************************************************/
-/**
-*
-* This function is used to check if the watchdog counter has reached 0 in timer
-* mode.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return
-* - TRUE if the watchdog has expired.
-* - FALSE if the watchdog has not expired.
-*
-* @note C-style signature:
-* int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_IsTimerExpired(InstancePtr) \
- ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_ISR_OFFSET) & \
- XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
-
-/****************************************************************************/
-/**
-*
-* Re-start the watchdog timer. This macro will read the watchdog load register
-* and write the same value to load register to update the counter register.
-* An application needs to call this function periodically to keep the watchdog
-* from asserting the WDRESETREQ reset request output pin.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_RestartWdt(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_RestartWdt(InstancePtr) \
- XScuWdt_LoadWdt((InstancePtr), \
- (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_LOAD_OFFSET)))
-
-/****************************************************************************/
-/**
-*
-* Write to the watchdog timer load register. This will also update the
-* watchdog counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-* @param Value is the value to be written to the Watchdog Load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value)
-*
-******************************************************************************/
-#define XScuWdt_LoadWdt(InstancePtr, Value) \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_LOAD_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the
-* Watchdog control register.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_SetWdMode(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_SetWdMode(InstancePtr) \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET, \
- (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET) | \
- (XSCUWDT_CONTROL_WD_MODE_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321
-* successively to the Watchdog Disable Register.
-* The software must write 0x12345678 and 0x87654321 successively to the
-* Watchdog Disable Register so that the watchdog mode bit in the Watchdog
-* Control Register is set to zero.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_SetTimerMode(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_SetTimerMode(InstancePtr) \
-{ \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_DISABLE_OFFSET, \
- XSCUWDT_DISABLE_VALUE1); \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_DISABLE_OFFSET, \
- XSCUWDT_DISABLE_VALUE2); \
-}
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the watchdog control register.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return Contents of the watchdog control register.
-*
-* @note C-style signature:
- u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_GetControlReg(InstancePtr) \
- XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the watchdog control register.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-* @param ControlReg is the value to be written to the watchdog control
-* register.
-*
-* @return None.
-*
-* @note C-style signature:
- void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg)
-*
-******************************************************************************/
-#define XScuWdt_SetControlReg(InstancePtr, ControlReg) \
- XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUWDT_CONTROL_OFFSET, (ControlReg))
-
-/****************************************************************************/
-/**
-*
-* Enable auto-reload mode.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr)
-*
-******************************************************************************/
-#define XScuWdt_EnableAutoReload(InstancePtr) \
- XScuWdt_SetControlReg((InstancePtr), \
- (XScuWdt_GetControlReg(InstancePtr) | \
- XSCUWDT_CONTROL_AUTO_RELOAD_MASK))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Lookup configuration in xscuwdt_sinit.c.
- */
-XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId);
-
-/*
- * Selftest function in xscuwdt_selftest.c
- */
-s32 XScuWdt_SelfTest(XScuWdt *InstancePtr);
-
-/*
- * Interface functions in xscuwdt.c
- */
-s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
- XScuWdt_Config *ConfigPtr, u32 EffectiveAddress);
-
-void XScuWdt_Start(XScuWdt *InstancePtr);
-
-void XScuWdt_Stop(XScuWdt *InstancePtr);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a5/c042d9535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a5/c042d9535243001d18b399c1eb9b3628
deleted file mode 100644
index a270af6..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a5/c042d9535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,691 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xscugic_hw.h
-* @addtogroup scugic_v4_6
-* @{
-*
-* This header file contains identifiers and HW access functions (or
-* macros) that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-* The driver functions/APIs are defined in xscugic.h.
-*
-* This GIC device has two parts, a distributor and CPU interface(s). Each part
-* has separate register definition sections.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------------
-* 1.00a drg 01/19/10 First release
-* 1.01a sdm 11/09/11 "xil_exception.h" added as include.
-* Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
-* added to enable or disable interrupts based on
-* Distributor Register base address. Normally users use
-* XScuGic instance and call XScuGic_Enable or
-* XScuGic_Disable to enable/disable interrupts. These
-* new macros are provided when user does not want to
-* use an instance pointer but still wants to enable or
-* disable interrupts.
-* Function prototypes for functions (present in newly
-* added file xscugic_hw.c) are added.
-* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
-* 702687).
-* 1.04a hk 05/04/13 Fix for CR#705621. Moved function prototypes
-* XScuGic_SetPriTrigTypeByDistAddr and
-* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
-* 3.0 pkp 12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
-* Zynq Ultrascale Mp
-* 3.0 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
-* 3.2 pkp 11/09/15 Corrected the interrupt processsor target mask value
-* for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
-* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
-* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
-* API's can be used by applications to unmap specific/all
-* interrupts from target CPU. It fixes CR#992490.
-* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
-* 4.1 asa 03/30/19 Removed macros for XScuGic_EnableIntr, and
-* XScuGic_DisableIntr. These are now C functions. This
-* change was to fix CR-1024716.
-* 4.1 mus 06/12/19 Updated XSCUGIC_MAX_NUM_INTR_INPUTS for Versal.
-* 4.6 sk 06/07/21 Delete the commented macro code to fix the MISRA-C warning.
-* 4.6 sk 08/05/21 Fix Scugic Misrac violations.
-*
-*
-*
-******************************************************************************/
-
-#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
-#define XSCUGIC_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xil_exception.h"
-#include "bspconfig.h"
-
-/************************** Constant Definitions *****************************/
-#if defined (versal) && !defined(ARMR5)
-#define GICv3
-#endif
-
-/*
- * The maximum number of interrupts supported by the hardware.
- */
-#ifdef PLATFORM_ZYNQ
-#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */
-#elif defined (versal)
-#define XSCUGIC_MAX_NUM_INTR_INPUTS 192U
-#else
-#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
-#endif
-
-/*
- * First Interrupt Id for SPI interrupts.
- */
-#define XSCUGIC_SPI_INT_ID_START 0x20
-/*
- * The maximum priority value that can be used in the GIC.
- */
-#define XSCUGIC_MAX_INTR_PRIO_VAL 248U
-#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U
-
-/** @name Distributor Interface Register Map
- *
- * Define the offsets from the base address for all Distributor registers of
- * the interrupt controller, some registers may be reserved in the hardware
- * device.
- * @{
- */
-#define XSCUGIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable
- Register */
-#define XSCUGIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller
- Type Register */
-#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID
- Register */
-#define XSCUGIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security
- Register */
-#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set
- Register */
-#define XSCUGIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */
-#define XSCUGIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set
- Register */
-#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear
- Register */
-#define XSCUGIC_ACTIVE_OFFSET 0x00000300U /**< Active Status Register */
-#define XSCUGIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */
-#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target
- Register 0x800-0x8FB */
-#define XSCUGIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration
- Register 0xC00-0xCFC */
-#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */
-#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register
- 0xd04-0xd7C */
-#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration
- Register */
-#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered
- Interrupt Register */
-#define XSCUGIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */
-#if defined (GICv3)
-#define XSCUGIC_PCELLID_OFFSET 0x0000FFF0U /**< Pcell ID Register */
-#else
-#define XSCUGIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */
-#endif
-/* @} */
-
-/** @name Distributor Enable Register
- * Controls if the distributor response to external interrupt inputs.
- * @{
- */
-#if defined (GICv3)
-#define XSCUGIC_EN_INT_MASK 0x00000003U /**< Interrupt In Enable */
-#else
-#define XSCUGIC_EN_INT_MASK 0x00000001U /**< Interrupt In Enable */
-#endif
-/* @} */
-
-/** @name Interrupt Controller Type Register
- * @{
- */
-#define XSCUGIC_LSPI_MASK 0x0000F800U /**< Number of Lockable
- Shared Peripheral
- Interrupts*/
-#define XSCUGIC_DOMAIN_MASK 0x00000400U /**< Number os Security domains*/
-#define XSCUGIC_CPU_NUM_MASK 0x000000E0U /**< Number of CPU Interfaces */
-#define XSCUGIC_NUM_INT_MASK 0x0000001FU /**< Number of Interrupt IDs */
-/* @} */
-
-/** @name Implementor ID Register
- * Implementor and revision information.
- * @{
- */
-#define XSCUGIC_REV_MASK 0x00FFF000U /**< Revision Number */
-#define XSCUGIC_IMPL_MASK 0x00000FFFU /**< Implementor */
-/* @} */
-
-/** @name Interrupt Security Registers
- * Each bit controls the security level of an interrupt, either secure or non
- * secure. These registers can only be accessed using secure read and write.
- * There are registers for each of the CPU interfaces at offset 0x080. A
- * register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x084.
- * @{
- */
-#define XSCUGIC_INT_NS_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Enable Set Register
- * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
- * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
- * bit to 0.
- * There are registers for each of the CPU interfaces at offset 0x100. With up
- * to 8 registers aliased to the same address. A register set for the SPI
- * interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x104.
- * @{
- */
-#define XSCUGIC_INT_EN_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Enable Clear Register
- * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
- * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
- * sets the corresponding bit to 0.
- * There are registers for each of the CPU interfaces at offset 0x180. With up
- * to 8 registers aliased to the same address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x184.
- * @{
- */
-#define XSCUGIC_INT_CLR_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Pending Set Register
- * Each bit controls the Pending or Active and Pending state of an interrupt, a
- * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
- * an interrupt to the pending state.
- * There are registers for each of the CPU interfaces at offset 0x200. With up
- * to 8 registers aliased to the same address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x204.
- * @{
- */
-#define XSCUGIC_PEND_SET_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Pending Clear Register
- * Each bit can clear the Pending or Active and Pending state of an interrupt, a
- * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
- * clears the pending state of an interrupt.
- * There are registers for each of the CPU interfaces at offset 0x280. With up
- * to 8 registers aliased to the same address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x284.
- * @{
- */
-#define XSCUGIC_PEND_CLR_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Active Status Register
- * Each bit provides the Active status of an interrupt, a
- * 0 is not Active, a 1 is Active. This is a read only register.
- * There are registers for each of the CPU interfaces at offset 0x300. With up
- * to 8 registers aliased to each address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x380.
- * @{
- */
-#define XSCUGIC_ACTIVE_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Priority Level Register
- * Each byte in a Priority Level Register sets the priority level of an
- * interrupt. Reading the register provides the priority level of an interrupt.
- * There are registers for each of the CPU interfaces at offset 0x400 through
- * 0x41C. With up to 8 registers aliased to each address.
- * 0 is highest priority, 0xFF is lowest.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 255 of these registers staring at location 0x420.
- * @{
- */
-#define XSCUGIC_PRIORITY_MASK 0x000000FFU /**< Each Byte corresponds to an
- INT_ID */
-#define XSCUGIC_PRIORITY_MAX 0x000000FFU /**< Highest value of a priority
- actually the lowest priority*/
-/* @} */
-
-/** @name SPI Target Register 0x800-0x8FB
- * Each byte references a separate SPI and programs which of the up to 8 CPU
- * interfaces are sent a Pending interrupt.
- * There are registers for each of the CPU interfaces at offset 0x800 through
- * 0x81C. With up to 8 registers aliased to each address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 255 of these registers staring at location 0x820.
- *
- * This driver does not support multiple CPU interfaces. These are included
- * for complete documentation.
- * @{
- */
-#define XSCUGIC_SPI_CPU7_MASK 0x00000080U /**< CPU 7 Mask*/
-#define XSCUGIC_SPI_CPU6_MASK 0x00000040U /**< CPU 6 Mask*/
-#define XSCUGIC_SPI_CPU5_MASK 0x00000020U /**< CPU 5 Mask*/
-#define XSCUGIC_SPI_CPU4_MASK 0x00000010U /**< CPU 4 Mask*/
-#define XSCUGIC_SPI_CPU3_MASK 0x00000008U /**< CPU 3 Mask*/
-#define XSCUGIC_SPI_CPU2_MASK 0x00000004U /**< CPU 2 Mask*/
-#define XSCUGIC_SPI_CPU1_MASK 0x00000002U /**< CPU 1 Mask*/
-#define XSCUGIC_SPI_CPU0_MASK 0x00000001U /**< CPU 0 Mask*/
-/* @} */
-
-/** @name Interrupt Configuration Register 0xC00-0xCFC
- * The interrupt configuration registers program an SFI to be active HIGH level
- * sensitive or rising edge sensitive.
- * Each bit pair describes the configuration for an INT_ID.
- * SFI Read Only b10 always
- * PPI Read Only depending on how the PPIs are configured.
- * b01 Active HIGH level sensitive
- * b11 Rising edge sensitive
- * SPI LSB is read only.
- * b01 Active HIGH level sensitive
- * b11 Rising edge sensitive/
- * There are registers for each of the CPU interfaces at offset 0xC00 through
- * 0xC04. With up to 8 registers aliased to each address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 255 of these registers staring at location 0xC08.
- * @{
- */
-#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */
-/* @} */
-
-/** @name PPI Status Register
- * Enables an external AMBA master to access the status of the PPI inputs.
- * A CPU can only read the status of its local PPI signals and cannot read the
- * status for other CPUs.
- * This register is aliased for each CPU interface.
- * @{
- */
-#define XSCUGIC_PPI_C15_MASK 0x00008000U /**< PPI Status */
-#define XSCUGIC_PPI_C14_MASK 0x00004000U /**< PPI Status */
-#define XSCUGIC_PPI_C13_MASK 0x00002000U /**< PPI Status */
-#define XSCUGIC_PPI_C12_MASK 0x00001000U /**< PPI Status */
-#define XSCUGIC_PPI_C11_MASK 0x00000800U /**< PPI Status */
-#define XSCUGIC_PPI_C10_MASK 0x00000400U /**< PPI Status */
-#define XSCUGIC_PPI_C09_MASK 0x00000200U /**< PPI Status */
-#define XSCUGIC_PPI_C08_MASK 0x00000100U /**< PPI Status */
-#define XSCUGIC_PPI_C07_MASK 0x00000080U /**< PPI Status */
-#define XSCUGIC_PPI_C06_MASK 0x00000040U /**< PPI Status */
-#define XSCUGIC_PPI_C05_MASK 0x00000020U /**< PPI Status */
-#define XSCUGIC_PPI_C04_MASK 0x00000010U /**< PPI Status */
-#define XSCUGIC_PPI_C03_MASK 0x00000008U /**< PPI Status */
-#define XSCUGIC_PPI_C02_MASK 0x00000004U /**< PPI Status */
-#define XSCUGIC_PPI_C01_MASK 0x00000002U /**< PPI Status */
-#define XSCUGIC_PPI_C00_MASK 0x00000001U /**< PPI Status */
-/* @} */
-
-/** @name SPI Status Register 0xd04-0xd7C
- * Enables an external AMBA master to access the status of the SPI inputs.
- * There are up to 63 registers if the maximum number of SPI inputs are
- * configured.
- * @{
- */
-#define XSCUGIC_SPI_N_MASK 0x00000001U /**< Each bit corresponds to an SPI
- input */
-/* @} */
-
-/** @name AHB Configuration Register
- * Provides the status of the CFGBIGEND input signal and allows the endianness
- * of the GIC to be set.
- * @{
- */
-#define XSCUGIC_AHB_END_MASK 0x00000004U /**< 0-GIC uses little Endian,
- 1-GIC uses Big Endian */
-#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002U /**< 0-Uses CFGBIGEND control,
- 1-use the AHB_END bit */
-#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U /**< State of CFGBIGEND */
-
-/* @} */
-
-/** @name Software Triggered Interrupt Register
- * Controls issuing of software interrupts.
- * @{
- */
-#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000U
-#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U /**< Target List filter
- b00-Use the target List
- b01-All CPUs except requester
- b10-To Requester
- b11-reserved */
-#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U /**< CPU Target list */
-#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U /**< 0= Use a secure interrupt */
-#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU /**< Set to the INTID
- signaled to the CPU*/
-/* @} */
-
-/** @name CPU Interface Register Map
- *
- * Define the offsets from the base address for all CPU registers of the
- * interrupt controller, some registers may be reserved in the hardware device.
- * @{
- */
-#define XSCUGIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control
- Register */
-#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */
-#define XSCUGIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */
-#define XSCUGIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */
-#define XSCUGIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */
-#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */
-#define XSCUGIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt
- Register */
-#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure
- Binary Point Register */
-
-/**< 0x00000020 to 0x00000FBC are reserved and should not be read or written
- * to. */
-/* @} */
-
-
-/** @name Control Register
- * CPU Interface Control register definitions
- * All bits are defined here although some are not available in the non-secure
- * mode.
- * @{
- */
-#define XSCUGIC_CNTR_SBPR_MASK 0x00000010U /**< Secure Binary Pointer,
- 0=separate registers,
- 1=both use bin_pt_s */
-#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008U /**< Use nFIQ_C for secure
- interrupts,
- 0= use IRQ for both,
- 1=Use FIQ for secure, IRQ for non*/
-#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U /**< Ack control for secure or non secure */
-#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002U /**< Non Secure enable */
-#define XSCUGIC_CNTR_EN_S_MASK 0x00000001U /**< Secure enable, 0=Disabled, 1=Enabled */
-/* @} */
-
-
-/** @name Binary Point Register
- * Binary Point register definitions
- * @{
- */
-
-#define XSCUGIC_BIN_PT_MASK 0x00000007U /**< Binary point mask value
- Value Secure Non-secure
- b000 0xFE 0xFF
- b001 0xFC 0xFE
- b010 0xF8 0xFC
- b011 0xF0 0xF8
- b100 0xE0 0xF0
- b101 0xC0 0xE0
- b110 0x80 0xC0
- b111 0x00 0x80
- */
-/*@}*/
-
-/** @name Interrupt Acknowledge Register
- * Interrupt Acknowledge register definitions
- * Identifies the current Pending interrupt, and the CPU ID for software
- * interrupts.
- */
-#define XSCUGIC_ACK_INTID_MASK 0x000003FFU /**< Interrupt ID */
-#define XSCUGIC_CPUID_MASK 0x00000C00U /**< CPU ID */
-/* @} */
-
-/** @name End of Interrupt Register
- * End of Interrupt register definitions
- * Allows the CPU to signal the GIC when it completes an interrupt service
- * routine.
- */
-#define XSCUGIC_EOI_INTID_MASK 0x000003FFU /**< Interrupt ID */
-
-/* @} */
-
-/** @name Running Priority Register
- * Running Priority register definitions
- * Identifies the interrupt priority level of the highest priority active
- * interrupt.
- */
-#define XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU /**< Interrupt Priority */
-/* @} */
-
-#if defined (GICv3)
-#define XSCUGIC_IROUTER_BASE_OFFSET 0x6000U
-#endif
-/*
- * Highest Pending Interrupt register definitions
- * Identifies the interrupt priority of the highest priority pending interrupt
- */
-#define XSCUGIC_PEND_INTID_MASK 0x000003FFU /**< Pending Interrupt ID */
-/* @} */
-#if defined (GICv3)
-/** @name ReDistributor Interface Register Map
- *
- * @{
- */
-#define XSCUGIC_RDIST_OFFSET 0x80000U
-#define XSCUGIC_RDIST_BASE_ADDRESS (XPAR_SCUGIC_0_DIST_BASEADDR + XSCUGIC_RDIST_OFFSET)
-#define XSCUGIC_RDIST_SGI_PPI_OFFSET 0x90000U
-#define XSCUGIC_RDIST_SGI_PPI_BASE_ADDRESS (XPAR_SCUGIC_0_DIST_BASEADDR + XSCUGIC_RDIST_SGI_PPI_OFFSET)
-#define XSCUGIC_RDIST_ISENABLE_OFFSET 0x100U
-#define XSCUGIC_RDIST_IPRIORITYR_OFFSET 0x400U
-#define XSCUGIC_RDIST_IGROUPR_OFFSET 0x80U
-#define XSCUGIC_RDIST_GRPMODR_OFFSET 0xD00U
-#define XSCUGIC_RDIST_INT_CONFIG_OFFSET 0xC00U
-#define XSCUGIC_RDIST_WAKER_OFFSET 0x14U
-#define XSCUGIC_SGIR_EL1_INITID_SHIFT 24U
-
-/*
- * GICR_IGROUPR register definitions
- */
-#if EL3
-#define XSCUGIC_DEFAULT_SECURITY 0x0U
-#else
-#define XSCUGIC_DEFAULT_SECURITY 0xFFFFFFFFU
-#endif
-/*
- * GICR_WAKER register definitions
- */
-#define XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK 0x7
-#endif
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Configuration Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Priority Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Routing Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_IROUTER_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_IROUTER_BASE_OFFSET + (InterruptID * 8))
-
-/****************************************************************************/
-/**
-*
-* Read the SPI Target Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
-/****************************************************************************/
-/**
-*
-* Read the SPI Target Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_SECURITY_TARGET_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_SECURITY_OFFSET + (((InterruptID)/32U)*4U))
-
-/****************************************************************************/
-/**
-*
-* Read the Re-distributor Interrupt configuration register offset
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_RDIST_INT_CONFIG_OFFSET + ((InterruptID /16)*4))
-
-/****************************************************************************/
-/**
-*
-* Read the Re-distributor Interrupt Priority register offset
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_RDIST_IPRIORITYR_OFFSET + (InterruptID * 4))
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Clear-Enable Register offset for an interrupt ID
-*
-* @param Register is the register offset for the clear/enable bank.
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
- ((Register) + (((InterruptID)/32U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the given Intc register.
-*
-* @param BaseAddress is the base address of the device.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_ReadReg(BaseAddress, RegOffset) \
- (Xil_In32((BaseAddress) + (RegOffset)))
-
-
-/****************************************************************************/
-/**
-*
-* Write the given Intc register.
-*
-* @param BaseAddress is the base address of the device.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
- (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
-
-
-/************************** Function Prototypes ******************************/
-
-void XScuGic_DeviceInterruptHandler(void *DeviceId);
-s32 XScuGic_DeviceInitialize(u32 DeviceId);
-void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
- Xil_InterruptHandler IntrHandler, void *CallBackRef);
-void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
- u8 Priority, u8 Trigger);
-void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
- u8 *Priority, u8 *Trigger);
-void XScuGic_InterruptMapFromCpuByDistAddr(u32 DistBaseAddress,
- u8 Cpu_Id, u32 Int_Id);
-void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
- u8 Cpu_Id, u32 Int_Id);
-void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
- u8 Cpu_Id);
-void XScuGic_EnableIntr (u32 DistBaseAddress, u32 Int_Id);
-void XScuGic_DisableIntr (u32 DistBaseAddress, u32 Int_Id);
-/************************** Variable Definitions *****************************/
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/200a48545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/200a48545243001d18b399c1eb9b3628
deleted file mode 100644
index 5007212..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/200a48545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,111 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2017 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_sleeptimer.h
-*
-* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs.
-* For sleep related functions that can be used across all Xilinx supported
-* processors, please use xil_sleeptimer.h.
-*
-*
-*
-* MODIFICATION HISTORY :
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 6.6 srm 10/18/17 First Release.
-* 7.0 mus 01/07/19 Add cpp extern macro
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00 hbm 08/19/10 First Release
-* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
-* the maximum number of channels.
-* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
-* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
-* Added the tcl file to automatically generate the
-* xparameters.h
-* 1.02a sg 05/16/12 Made changes for doxygen and moved some function
-* header from the xdmaps.h file to xdmaps.c file
-* Other cleanup for coding guidelines and CR 657109
-* and CR 657898
-* The xdmaps_example_no_intr.c example is removed
-* as it is using interrupts and is similar to
-* the interrupt example - CR 652477
-* 1.03a sg 07/16/2012 changed inline to __inline for CR665681
-* 1.04a nm 10/22/2012 Fixed CR# 681671.
-* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled
-* with -Wall and -Wextra option in bsp.
-* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
-* function description.
-* Fixed CR# 704396. Removed unused variables
-* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
-* function.
-* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc.
-* Removed the PDBG prints. By default they were always
-* defined out and never used. The PDBG is non-standard for
-* Xilinx drivers and no other driver does something similar.
-* Since there is no easy way to fix compilation issues with
-* the IARCC compiler around PDBG, it is better to remove it.
-* Users can always use xil_printfs if they want to debug.
-* 2.0 adk 10/12/13 Updated as per the New Tcl API's
-* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
-* 2.2 mus 08/12/16 Declared all inline functions in xdmaps.c as extern, to avoid
-* linker error for IAR compiler
-* 2.3 ms 01/23/17 Modified xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 2.4 adk 13/08/18 Fixed armcc compiler warnings in the driver CR-1008310.
-* 2.8 sk 05/18/21 Modify all inline functions declarations from extern inline
-* to static inline to avoid the linkage conflict for IAR compiler.
-*
-*
-*****************************************************************************/
-
-#ifndef XDMAPS_H /* prevent circular inclusions */
-#define XDMAPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xparameters.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-
-#include "xdmaps_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of device (IPIF) */
-} XDmaPs_Config;
-
-
-/** DMA channle control structure. It's for AXI bus transaction.
- * This struct will be translated into a 32-bit channel control register value.
- */
-typedef struct {
- unsigned int EndianSwapSize; /**< Endian swap size. */
- unsigned int DstCacheCtrl; /**< Destination cache control */
- unsigned int DstProtCtrl; /**< Destination protection control */
- unsigned int DstBurstLen; /**< Destination burst length */
- unsigned int DstBurstSize; /**< Destination burst size */
- unsigned int DstInc; /**< Destination incrementing or fixed
- * address */
- unsigned int SrcCacheCtrl; /**< Source cache control */
- unsigned int SrcProtCtrl; /**< Source protection control */
- unsigned int SrcBurstLen; /**< Source burst length */
- unsigned int SrcBurstSize; /**< Source burst size */
- unsigned int SrcInc; /**< Source incrementing or fixed
- * address */
-} XDmaPs_ChanCtrl;
-
-/** DMA block descriptor stucture.
- */
-typedef struct {
- u32 SrcAddr; /**< Source starting address */
- u32 DstAddr; /**< Destination starting address */
- unsigned int Length; /**< Number of bytes for the block */
-} XDmaPs_BD;
-
-/**
- * A DMA command consisits of a channel control struct, a block descriptor,
- * a user defined program, a pointer pointing to generated DMA program, and
- * execution result.
- *
- */
-typedef struct {
- XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */
- XDmaPs_BD BD; /**< Together with SgLength field,
- * it's a scatter-gather list.
- */
- void *UserDmaProg; /**< If user wants the driver to
- * execute their own DMA program,
- * this field points to the DMA
- * program.
- */
- int UserDmaProgLength; /**< The length of user defined
- * DMA program.
- */
-
- void *GeneratedDmaProg; /**< The DMA program genreated
- * by the driver. This field will be
- * set if a user invokes the DMA
- * program generation function. Or
- * the DMA command is finished and
- * a user informs the driver not to
- * release the program buffer.
- * This field has two purposes, one
- * is to ask the driver to generate
- * a DMA program while the DMAC is
- * performaning DMA transactions. The
- * other purpose is to debug the
- * driver.
- */
- int GeneratedDmaProgLength; /**< The length of the DMA program
- * generated by the driver
- */
- int DmaStatus; /**< 0 on success, otherwise error code
- */
- u32 ChanFaultType; /**< Channel fault type in case of fault
- */
- u32 ChanFaultPCAddr; /**< Channel fault PC address
- */
-} XDmaPs_Cmd;
-
-/**
- * It's the done handler a user can set for a channel
- */
-typedef void (*XDmaPsDoneHandler) (unsigned int Channel,
- XDmaPs_Cmd *DmaCmd,
- void *CallbackRef);
-
-/**
- * It's the fault handler a user can set for a channel
- */
-typedef void (*XDmaPsFaultHandler) (unsigned int Channel,
- XDmaPs_Cmd *DmaCmd,
- void *CallbackRef);
-
-#define XDMAPS_MAX_CHAN_BUFS 2
-#define XDMAPS_CHAN_BUF_LEN 128
-
-/**
- * The XDmaPs_ProgBuf is the struct for a DMA program buffer.
- */
-typedef struct {
- char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the
- * content */
- unsigned Len; /**< The actual length of the DMA
- * program in bytes. */
- int Allocated; /**< A tag indicating whether the
- * buffer is allocated or not */
-} XDmaPs_ProgBuf;
-
-/**
- * The XDmaPs_ChannelData is a struct to book keep individual channel of
- * the DMAC.
- */
-typedef struct {
- unsigned DevId; /**< Device id indicating which DMAC */
- unsigned ChanId; /**< Channel number of the DMAC */
- XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of
- program buffers*/
- XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */
- void *DoneRef; /**< Done interrupt callback data */
- XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */
- XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished.
- * This field is for debugging purpose
- */
- int HoldDmaProg; /**< A tag indicating whether to hold the
- * DMA program after the DMA is done.
- */
-
-} XDmaPs_ChannelData;
-
-/**
- * The XDmaPs driver instance data structure. A pointer to an instance data
- * structure is passed around by functions to refer to a specific driver
- * instance.
- */
-typedef struct {
- XDmaPs_Config Config; /**< Configuration data structure */
- int IsReady; /**< Device is Ready */
- int CacheLength; /**< icache length */
- XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */
- void *FaultRef; /**< fault call back data */
- XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV];
- /**<
- * channel data
- */
-} XDmaPs;
-
-/*
- * Functions implemented in xdmaps.c
- */
-int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
- XDmaPs_Config *Config,
- u32 EffectiveAddr);
-
-int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
- XDmaPs_Cmd *Cmd,
- int HoldDmaProg);
-
-int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel);
-int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel,
- XDmaPs_Cmd *Cmd);
-int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel,
- XDmaPs_Cmd *Cmd);
-void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
-
-
-int XDmaPs_ResetManager(XDmaPs *InstPtr);
-int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel);
-
-
-int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
- unsigned Channel,
- XDmaPsDoneHandler DoneHandler,
- void *CallbackRef);
-
-int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
- XDmaPsFaultHandler FaultHandler,
- void *CallbackRef);
-
-void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
-int XDmaPs_Instr_DMARMB(char *DmaProg);
-int XDmaPs_Instr_DMAWMB(char *DmaProg);
-
-/**
- * To avoid linkage error,modify all inline functions from extern
- * inline to static inline for IAR compiler
- */
-#ifdef __ICCARM__
-static INLINE int XDmaPs_Instr_DMAEND(char *DmaProg);
-static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src);
-static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
- u32 Imm, unsigned int Ns);
-static INLINE int XDmaPs_Instr_DMALD(char *DmaProg);
-static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
- unsigned LoopIterations);
-static INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc);
-static INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm);
-static INLINE int XDmaPs_Instr_DMANOP(char *DmaProg);
-static INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber);
-static INLINE int XDmaPs_Instr_DMAST(char *DmaProg);
-static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize);
-static INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize);
-#endif
-
-/**
- * Driver done interrupt service routines for the channels.
- * We need this done ISR mainly because the driver needs to release the
- * DMA program buffer. This is the one that connects the GIC
- */
-void XDmaPs_DoneISR_0(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_1(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_2(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_3(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_4(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_5(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_6(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_7(XDmaPs *InstPtr);
-
-/**
- * Driver fault interrupt service routine
- */
-void XDmaPs_FaultISR(XDmaPs *InstPtr);
-
-
-/*
- * Static loopup function implemented in xdmaps_sinit.c
- */
-XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId);
-
-
-/*
- * self-test functions in xdmaps_selftest.c
- */
-int XDmaPs_SelfTest(XDmaPs *InstPtr);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/301d5d585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/301d5d585243001d18b399c1eb9b3628
deleted file mode 100644
index 9df2cc9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/301d5d585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,122 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2014 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file xil-crt0.S
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00 pkp 05/21/14 Initial version
-* 5.04 pkp 12/18/15 Initialized global constructor for C++ applications
-* 5.04 pkp 01/05/16 Set the reset vector register RVBAR equivalent to
-* vector table base address
-* 6.02 pkp 01/22/17 Added support for EL1 non-secure
-* 6.6 srm 10/18/17 Added timer configuration using XTime_StartTTCTimer API.
-* Now the TTC instance as specified by the user will be
-* started.
-* 6.6 mus 01/29/18 Initialized the xen PV console for Cortexa53 64 bit
-* EL1 NS BSP.
-* 7.2 sd 02/23/20 Clock Init is called
-* 7.2 sd 02/23/20 Clock code added under XCLOCKING flag
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#include "xparameters.h"
-#include "bspconfig.h"
- .file "xil-crt0.S"
- .section ".got2","aw"
- .align 2
-
- .text
-.Lsbss_start:
- .quad __sbss_start
-
-.Lsbss_end:
- .quad __sbss_end
-
-.Lbss_start:
- .quad __bss_start__
-
-.Lbss_end:
- .quad __bss_end__
-
-
-.set APU_PWRCTL, 0xFD5C0090
-
- .globl _startup
-_startup:
-
- mov x0, #0
-.if (EL3 == 1)
- /* Check whether the clearing of bss sections shall be skipped */
- ldr x10, =APU_PWRCTL /* Load PWRCTRL address */
- ldr w11, [x10] /* Read PWRCTRL register */
- mrs x2, MPIDR_EL1 /* Read MPIDR_EL1 */
- ubfx x2, x2, #0, #8 /* Extract CPU ID (affinity level 0) */
- mov w1, #1
- lsl w2, w1, w2 /* Shift CPU ID to get one-hot ID */
- ands w11, w11, w2 /* Get PWRCTRL bit for this core */
- bne .Lenclbss /* Skip BSS and SBSS clearing */
-.endif
- /* clear sbss */
- ldr x1,.Lsbss_start /* calculate beginning of the SBSS */
- ldr x2,.Lsbss_end /* calculate end of the SBSS */
-
-.Lloop_sbss:
- cmp x1,x2
- bge .Lenclsbss /* If no SBSS, no clearing required */
- str x0, [x1], #8
- b .Lloop_sbss
-
-.Lenclsbss:
- /* clear bss */
- ldr x1,.Lbss_start /* calculate beginning of the BSS */
- ldr x2,.Lbss_end /* calculate end of the BSS */
-
-.Lloop_bss:
- cmp x1,x2
- bge .Lenclbss /* If no BSS, no clearing required */
- str x0, [x1], #8
- b .Lloop_bss
-
-.Lenclbss:
- /* run global constructors */
- bl __libc_init_array
-
- /* Reset and start Triple Timer Counter */
- #if defined (SLEEP_TIMER_BASEADDR)
- bl XTime_StartTTCTimer
- #endif
-
- .if (EL1_NONSECURE == 1 && HYP_GUEST == 1 && \
- XEN_USE_PV_CONSOLE == 1)
- bl XPVXenConsole_Init
- .endif
- /* make sure argc and argv are valid */
- mov x0, #0
- mov x1, #0
-
-#ifdef XCLOCKING
- bl Xil_ClockInit
-#endif
- bl main /* Jump to main C code */
-
- /* Cleanup global constructors */
- bl __libc_fini_array
-
- bl exit
-
-.Lexit: /* should never get here */
- b .Lexit
-
-.Lstart:
- .size _startup,.Lstart-_startup
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/30f29c525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/30f29c525243001d18b399c1eb9b3628
deleted file mode 100644
index e1bcd93..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/30f29c525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,762 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
- *
- * @file xemacps_bd.h
-* @addtogroup emacps_v3_15
-* @{
- *
- * This header provides operations to manage buffer descriptors in support
- * of scatter-gather DMA.
- *
- * The API exported by this header defines abstracted macros that allow the
- * user to read/write specific BD fields.
- *
- * Buffer Descriptors
- *
- * A buffer descriptor (BD) defines a DMA transaction. The macros defined by
- * this header file allow access to most fields within a BD to tailor a DMA
- * transaction according to user and hardware requirements. See the hardware
- * IP DMA spec for more information on BD fields and how they affect transfers.
- *
- * The XEmacPs_Bd structure defines a BD. The organization of this structure
- * is driven mainly by the hardware for use in scatter-gather DMA transfers.
- *
- * Performance
- *
- * Limiting I/O to BDs can improve overall performance of the DMA channel.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -------------------------------------------------------
- * 1.00a wsy 01/10/10 First release
- * 2.1 srt 07/15/14 Add support for Zynq Ultrascale MP GEM specification
- * and 64-bit changes.
- * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
- * 3.0 hk 02/20/15 Added support for jumbo frames.
- * Disable extended mode. Perform all 64 bit changes under
- * check for arch64.
- * 3.2 hk 11/18/15 Change BD typedef and number of words.
- * 3.8 hk 08/18/18 Remove duplicate definition of XEmacPs_BdSetLength
- * 3.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
- *
- *
- *
- * ***************************************************************************
- */
-
-#ifndef XEMACPS_BD_H /* prevent circular inclusions */
-#define XEMACPS_BD_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-#ifdef __aarch64__
-/* Minimum BD alignment */
-#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U
-#define XEMACPS_BD_NUM_WORDS 4U
-#else
-/* Minimum BD alignment */
-#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U
-#define XEMACPS_BD_NUM_WORDS 2U
-#endif
-
-/**
- * The XEmacPs_Bd is the type for buffer descriptors (BDs).
- */
-typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- * Zero out BD fields
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Nothing
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClear(BdPtr) \
- memset((BdPtr), 0, sizeof(XEmacPs_Bd))
-
-/****************************************************************************/
-/**
-*
-* Read the given Buffer Descriptor word.
-*
-* @param BaseAddress is the base address of the BD to read
-* @param Offset is the word offset to be read
-*
-* @return The 32-bit value of the field
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)
-*
-*****************************************************************************/
-#define XEmacPs_BdRead(BaseAddress, Offset) \
- (*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given Buffer Descriptor word.
-*
-* @param BaseAddress is the base address of the BD to write
-* @param Offset is the word offset to be written
-* @param Data is the 32-bit value to write to the field
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)
-*
-*****************************************************************************/
-#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \
- (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
-
-/*****************************************************************************/
-/**
- * Set the BD's Address field (word 0).
- *
- * @param BdPtr is the BD pointer to operate on
- * @param Addr is the value to write to BD's status field.
- *
- * @note :
- *
- * C-style signature:
- * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
- *
- *****************************************************************************/
-#if defined(__aarch64__) || defined(__arch64__)
-#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- (u32)((Addr) & ULONG64_LO_MASK)); \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
- (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
-#else
-#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
-#endif
-
-/*****************************************************************************/
-/**
- * Set the BD's Address field (word 0).
- *
- * @param BdPtr is the BD pointer to operate on
- * @param Addr is the value to write to BD's status field.
- *
- * @note : Due to some bits are mixed within receive BD's address field,
- * read-modify-write is performed.
- *
- * C-style signature:
- * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
- *
- *****************************************************************************/
-#ifdef __aarch64__
-#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- ~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
- (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
-#else
-#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))
-#endif
-
-/*****************************************************************************/
-/**
- * Set the BD's Status field (word 1).
- *
- * @param BdPtr is the BD pointer to operate on
- * @param Data is the value to write to BD's status field.
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetStatus(BdPtr, Data) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))
-
-
-/*****************************************************************************/
-/**
- * Retrieve the BD's Packet DMA transfer status word (word 1).
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Status word
- *
- * @note
- * C-style signature:
- * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)
- *
- * Due to the BD bit layout differences in transmit and receive. User's
- * caution is required.
- *****************************************************************************/
-#define XEmacPs_BdGetStatus(BdPtr) \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
-
-
-/*****************************************************************************/
-/**
- * Get the address (bits 0..31) of the BD's buffer address (word 0)
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#if defined(__aarch64__) || defined(__arch64__)
-#define XEmacPs_BdGetBufAddr(BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
-#else
-#define XEmacPs_BdGetBufAddr(BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
-#endif
-
-/*****************************************************************************/
-/**
- * Set transfer length in bytes for the given BD. The length must be set each
- * time a BD is submitted to hardware.
- *
- * @param BdPtr is the BD pointer to operate on
- * @param LenBytes is the number of bytes to transfer.
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
-
-
-/*****************************************************************************/
-/**
- * Retrieve the BD length field.
- *
- * For Tx channels, the returned value is the same as that written with
- * XEmacPs_BdSetLength().
- *
- * For Rx channels, the returned value is the size of the received packet.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Length field processed by hardware or set by
- * XEmacPs_BdSetLength().
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
- * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
- *
- *****************************************************************************/
-#define XEmacPs_BdGetLength(BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_LEN_MASK)
-
-/*****************************************************************************/
-/**
- * Retrieve the RX frame size.
- *
- * The returned value is the size of the received packet.
- * This API supports jumbo frame sizes if enabled.
- *
- * @param InstancePtr is the pointer to XEmacps instance
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Length field processed by hardware or set by
- * XEmacPs_BdSetLength().
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr)
- * RxBufMask is dependent on whether jumbo is enabled or not.
- *
- *****************************************************************************/
-#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- (InstancePtr)->RxBufMask)
-
-/*****************************************************************************/
-/**
- * Test whether the given BD has been marked as the last BD of a packet.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsLast(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Tell the DMA engine that the given transmit BD marks the end of the current
- * packet to be processed.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetLast(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_LAST_MASK))
-
-
-/*****************************************************************************/
-/**
- * Tell the DMA engine that the current packet does not end with the given
- * BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearLast(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_LAST_MASK))
-
-
-/*****************************************************************************/
-/**
- * Set this bit to mark the last descriptor in the receive buffer descriptor
- * list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-/*#define XEmacPs_BdSetRxWrap(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
- XEMACPS_RXBUF_WRAP_MASK))
-*/
-
-/*****************************************************************************/
-/**
- * Determine the wrap bit of the receive BD which indicates end of the
- * BD list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxWrap(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Sets this bit to mark the last descriptor in the transmit buffer
- * descriptor list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-/*#define XEmacPs_BdSetTxWrap(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_WRAP_MASK))
-*/
-
-/*****************************************************************************/
-/**
- * Determine the wrap bit of the transmit BD which indicates end of the
- * BD list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxWrap(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/*
- * Must clear this bit to enable the MAC to write data to the receive
- * buffer. Hardware sets this bit once it has successfully written a frame to
- * memory. Once set, software has to clear the bit before the buffer can be
- * used again. This macro clear the new bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearRxNew(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- ~XEMACPS_RXBUF_NEW_MASK))
-
-
-/*****************************************************************************/
-/**
- * Determine the new bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxNew(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Software sets this bit to disable the buffer to be read by the hardware.
- * Hardware sets this bit for the first buffer of a frame once it has been
- * successfully transmitted. This macro sets this bit of transmit BD to avoid
- * confusion.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetTxUsed(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_USED_MASK))
-
-
-/*****************************************************************************/
-/**
- * Software clears this bit to enable the buffer to be read by the hardware.
- * Hardware sets this bit for the first buffer of a frame once it has been
- * successfully transmitted. This macro clears this bit of transmit BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearTxUsed(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_USED_MASK))
-
-
-/*****************************************************************************/
-/**
- * Determine the used bit of the transmit BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxUsed(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if a frame fails to be transmitted due to too many retries.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxRetry(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if a frame fails to be transmitted due to data can not be
- * feteched in time or buffers are exhausted.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxUrun(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if a frame fails to be transmitted due to buffer is exhausted
- * mid-frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxExh(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Sets this bit, no CRC will be appended to the current frame. This control
- * bit must be set for the first buffer in a frame and will be ignored for
- * the subsequent buffers of a frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * This bit must be clear when using the transmit checksum generation offload,
- * otherwise checksum generation and substitution will not occur.
- *
- * C-style signature:
- * UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetTxNoCRC(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_NOCRC_MASK))
-
-
-/*****************************************************************************/
-/**
- * Clear this bit, CRC will be appended to the current frame. This control
- * bit must be set for the first buffer in a frame and will be ignored for
- * the subsequent buffers of a frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * This bit must be clear when using the transmit checksum generation offload,
- * otherwise checksum generation and substitution will not occur.
- *
- * C-style signature:
- * UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearTxNoCRC(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_NOCRC_MASK))
-
-
-/*****************************************************************************/
-/**
- * Determine the broadcast bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxBcast(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the multicast hash bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxMultiHash(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the unicast hash bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxUniHash(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if the received frame is a VLAN Tagged frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxVlan(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if the received frame has Type ID of 8100h and null VLAN
- * identifier(Priority tag).
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxPri(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if the received frame's Concatenation Format Indicator (CFI) of
- * the frames VLANTCI field was set.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxCFI(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the End Of Frame (EOF) bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxEOF(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the Start Of Frame (SOF) bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxSOF(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
-
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/515ad4565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/515ad4565243001d18b399c1eb9b3628
deleted file mode 100644
index e8b87b5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/515ad4565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,176 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_assert.h
-*
-* @addtogroup common_assert_apis Assert APIs and Macros
-*
-* The xil_assert.h file contains assert related functions and macros.
-* Assert APIs/Macros specifies that a application program satisfies certain
-* conditions at particular points in its execution. These function can be
-* used by application programs to ensure that, application code is satisfying
-* certain conditions.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 First release
-* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_ASSERT_H /* prevent circular inclusions */
-#define XIL_ASSERT_H /* by using protection macros */
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-
-
-/************************** Constant Definitions *****************************/
-
-#define XIL_ASSERT_NONE 0U
-#define XIL_ASSERT_OCCURRED 1U
-#define XNULL NULL
-
-extern u32 Xil_AssertStatus;
-extern s32 Xil_AssertWait;
-extern void Xil_Assert(const char8 *File, s32 Line);
-/**
- *@endcond
- */
-void XNullHandler(void *NullParameter);
-
-/**
- * This data type defines a callback to be invoked when an
- * assert occurs. The callback is invoked only when asserts are enabled
- */
-typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#ifndef NDEBUG
-
-/*****************************************************************************/
-/**
-* @brief This assert macro is to be used for void functions. This in
-* conjunction with the Xil_AssertWait boolean can be used to
-* accommodate tests so that asserts which fail allow execution to
-* continue.
-*
-* @param Expression: expression to be evaluated. If it evaluates to
-* false, the assert occurs.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertVoid(Expression) \
-{ \
- if (Expression) { \
- Xil_AssertStatus = XIL_ASSERT_NONE; \
- } else { \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* @brief This assert macro is to be used for functions that do return a
-* value. This in conjunction with the Xil_AssertWait boolean can be
-* used to accommodate tests so that asserts which fail allow execution
-* to continue.
-*
-* @param Expression: expression to be evaluated. If it evaluates to false,
-* the assert occurs.
-*
-* @return Returns 0 unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertNonvoid(Expression) \
-{ \
- if (Expression) { \
- Xil_AssertStatus = XIL_ASSERT_NONE; \
- } else { \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return 0; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* @brief Always assert. This assert macro is to be used for void functions.
-* Use for instances where an assert should always occur.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertVoidAlways() \
-{ \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return; \
-}
-
-/*****************************************************************************/
-/**
-* @brief Always assert. This assert macro is to be used for functions that
-* do return a value. Use for instances where an assert should always
-* occur.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertNonvoidAlways() \
-{ \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return 0; \
-}
-
-
-#else
-
-#define Xil_AssertVoid(Expression)
-#define Xil_AssertVoidAlways()
-#define Xil_AssertNonvoid(Expression)
-#define Xil_AssertNonvoidAlways()
-
-#endif
-
-/************************** Function Prototypes ******************************/
-
-void Xil_AssertSetCallback(Xil_AssertCallback Routine);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_assert_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/80fb32545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/80fb32545243001d18b399c1eb9b3628
deleted file mode 100644
index 2e5cbd5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/80fb32545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,146 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xgpiops_hw.h
-* @addtogroup gpiops_v3_9
-* @{
-*
-* This header file contains the identifiers and basic driver functions (or
-* macros) that can be used to access the device. Other driver functions
-* are defined in xgpiops.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------
-* 1.00a sv 01/15/10 First Release
-* 1.02a hk 08/22/13 Added low level reset API function prototype and
-* related constant definitions
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/13/15 Corrected reset values of banks.
-* 3.5 sne 03/14/19 Added versal support.
-*
-*
-******************************************************************************/
-#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
-#define XGPIOPS_HW_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register offsets for the GPIO. Each register is 32 bits.
- * @{
- */
-#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /**< Mask and Data Register LSW, WO */
-#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /**< Mask and Data Register MSW, WO */
-#define XGPIOPS_DATA_OFFSET 0x00000040U /**< Data Register, RW */
-#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /**< Data Register - Input, RO */
-#define XGPIOPS_DIRM_OFFSET 0x00000204U /**< Direction Mode Register, RW */
-#define XGPIOPS_OUTEN_OFFSET 0x00000208U /**< Output Enable Register, RW */
-#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /**< Interrupt Mask Register, RO */
-#define XGPIOPS_INTEN_OFFSET 0x00000210U /**< Interrupt Enable Register, WO */
-#define XGPIOPS_INTDIS_OFFSET 0x00000214U /**< Interrupt Disable Register, WO*/
-#define XGPIOPS_INTSTS_OFFSET 0x00000218U /**< Interrupt Status Register, RO */
-#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /**< Interrupt Type Register, RW */
-#define XGPIOPS_INTPOL_OFFSET 0x00000220U /**< Interrupt Polarity Register, RW */
-#define XGPIOPS_INTANY_OFFSET 0x00000224U /**< Interrupt On Any Register, RW */
-/** @} */
-
-/** @name Register offsets for each Bank.
- * @{
- */
-#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /**< Data/Mask Registers offset */
-#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /**< Data Registers offset */
-#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /**< Registers offset */
-/** @} */
-
-/* For backwards compatibility */
-#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40 /**< Mask for backward support */
-
-/** @name Interrupt type reset values for each bank
- * @{
- */
-#ifdef XPAR_PSU_GPIO_0_BASEADDR
-#define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-#define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-#define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-#else
-#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /**< Resets specific to Zynq */
-#define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU /**< Resets specific to Zynq */
-#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU /**< Resets specific to Zynq */
-#endif
-
-#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /**< Reset common to both platforms */
-#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-/** @} */
-#define XGPIOPS_PS_GPIO_BASEADDR 0xFF0B0000U /**< Flag for Base Address for PS_GPIO in Versal */
-#define XGPIOPS_ZERO 0U /**< Flag for 0 Value */
-#define XGPIOPS_ONE 1U /**< Flag for 1 Value */
-#define XGPIOPS_TWO 2U /**< Flag for 2 Value */
-#define XGPIOPS_THREE 3U /**< Flag for 3 Value */
-#define XGPIOPS_FOUR 4U /**< Flag for 4 Value */
-#define XGPIOPS_SIX 6U /**< Flag for 6 Value */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* This macro reads the given register.
-*
-* @param BaseAddr is the base address of the device.
-* @param RegOffset is the register offset to be read.
-*
-* @return The 32-bit value of the register
-*
-* @note None.
-*
-*****************************************************************************/
-#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + (u32)(RegOffset))
-
-/****************************************************************************/
-/**
-*
-* This macro writes to the given register.
-*
-* @param BaseAddr is the base address of the device.
-* @param RegOffset is the offset of the register to be written.
-* @param Data is the 32-bit value to write to the register.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
-
-/************************** Function Prototypes ******************************/
-
-void XGpioPs_ResetHw(UINTPTR BaseAddress);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XGPIOPS_HW_H */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/a14a95555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/a14a95555243001d18b399c1eb9b3628
deleted file mode 100644
index 00b233a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/a14a95555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,20 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include "xil_types.h"
-
-/*
- * fcntl -- Manipulate a file descriptor.
- * We don't have a filesystem, so we do nothing.
- */
-__attribute__((weak)) sint32 fcntl (sint32 fd, sint32 cmd, long arg)
-{
- (void)fd;
- (void)cmd;
- (void)arg;
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/b37d87575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/b37d87575243001d18b399c1eb9b3628
deleted file mode 100644
index 5a1bda3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/b37d87575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,76 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_testio.h
-*
-* @addtogroup common_test_utils Test Utilities for Memory and Caches
-*
I/O test
-* The xil_testio.h file contains utility functions to test endian related memory
-* IO functions.
-*
-* A subset of the memory tests can be selected or all of the tests can be run
-* in order. If there is an error detected by a subtest, the test stops and the
-* failure code is returned. Further tests are not run even if all of the tests
-* are selected.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00 hbm 08/05/09 First release
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_TESTIO_H /* prevent circular inclusions */
-#define XIL_TESTIO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-
-#define XIL_TESTIO_DEFAULT 0
-#define XIL_TESTIO_LE 1
-#define XIL_TESTIO_BE 2
-
-/**
- *@endcond
- */
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
-extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
-extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_test_utils".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/c006e3535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/c006e3535243001d18b399c1eb9b3628
deleted file mode 100644
index 2782826..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/c006e3535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,342 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xsdps.h
-* @addtogroup sdps_v3_13
-* @{
-* @details
-*
-* This file contains the implementation of XSdPs driver.
-* This driver is used initialize read from and write to the SD card.
-* Features such as switching bus width to 4-bit and switching to high speed,
-* changing clock frequency, block size etc. are supported.
-* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
-* is done using 1-bit bus width and 400KHz clock frequency.
-* SD commands are classified as broadcast and addressed. Commands can be
-* those with response only (using only command line) or
-* response + data (using command and data lines).
-* Only one command can be sent at a time. During a data transfer however,
-* when dsta lines are in use, certain commands (which use only the command
-* line) can be sent, most often to obtain status.
-* This driver does not support multi card slots at present.
-*
-* Initialization:
-* This includes initialization on the host controller side to select
-* clock frequency, bus power and default transfer related parameters.
-* The default voltage is 3.3V.
-* On the SD card side, the initialization and identification state diagram is
-* implemented. This resets the card, gives it a unique address/ID and
-* identifies key card related specifications.
-*
-* Data transfer:
-* The SD card is put in transfer state to read from or write to it.
-* The default block size is 512 bytes and if supported,
-* default bus width is 4-bit and bus speed is High speed.
-* The read and write functions are implemented in polled mode using ADMA2.
-*
-* At any point, when key parameters such as block size or
-* clock/speed or bus width are modified, this driver takes care of
-* maintaining the same selection on host and card.
-* All error bits in host controller are monitored by the driver and in the
-* event one of them is set, driver will clear the interrupt status and
-* communicate failure to the upper layer.
-*
-* File system use:
-* This driver can be used with xilffs library to read and write files to SD.
-* (Please refer to procedure in diskio.c). The file system read/write example
-* in polled mode can used for reference.
-*
-* There is no example for using SD driver without file system at present.
-* However, the driver can be used without the file system. The glue layer
-* in filesystem can be used as reference for the same. The block count
-* passed to the read/write function in one call is limited by the ADMA2
-* descriptor table and hence care will have to be taken to call read/write
-* API's in a loop for large file sizes.
-*
-* Interrupt mode is not supported because it offers no improvement when used
-* with file system.
-*
-* eMMC support:
-* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
-* The features of eMMC supported by the driver will depend on those supported
-* by the host controller. The current driver supports read/write on eMMC card
-* using 4-bit and high speed mode currently.
-*
-* Features not supported include - card write protect, password setting,
-* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
-* 64-bit addressed ADMA2, erase/pre-erase commands.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a hk/sg 10/17/13 Initial release
-* 2.0 hk 03/07/14 Version number revised.
-* 2.1 hk 04/18/14 Increase sleep for eMMC switch command.
-* Add sleep for microblaze designs. CR# 781117.
-* 2.2 hk 07/28/14 Make changes to enable use of data cache.
-* 2.3 sk 09/23/14 Send command for relative card address
-* when re-initialization is done.CR# 819614.
-* Use XSdPs_Change_ClkFreq API whenever changing
-* clock.CR# 816586.
-* 2.4 sk 12/04/14 Added support for micro SD without
-* WP/CD. CR# 810655.
-* Checked for DAT Inhibit mask instead of CMD
-* Inhibit mask in Cmd Transfer API.
-* Added Support for SD Card v1.0
-* 2.5 sg 07/09/15 Added SD 3.0 features
-* kvn 07/15/15 Modified the code according to MISRAC-2012.
-* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
-* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
-* sk 12/10/15 Added support for MMC cards.
-* 01/08/16 Added workaround for issue in auto tuning mode
-* of SDR50, SDR104 and HS200.
-* sk 02/16/16 Corrected the Tuning logic.
-* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
-* 2.8 sk 04/20/16 Added new workaround for auto tuning.
-* 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
-* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
-* sk 07/16/16 Added support for UHS modes.
-* sk 07/07/16 Used usleep API for both arm and microblaze.
-* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
-* operating modes.
-* sk 08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
-* CR#956899.
-* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
-* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
-* sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
-* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
-* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value.
-* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
-* sk 02/01/17 Added HSD and DDR mode support for eMMC.
-* sk 02/01/17 Consider bus width parameter from design for switching
-* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
-* sk 03/20/17 Add support for EL1 non-secure mode.
-* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
-* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
-* mn 08/17/17 Enabled CCI support for A53 by adding cache coherency
-* information.
-* mn 09/06/17 Resolved compilation errors with IAR toolchain
-* 3.6 mn 08/01/18 Add support for using 64Bit DMA with 32-Bit Processor
-* 3.7 mn 02/01/19 Add support for idling of SDIO
-* 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
-* mn 09/17/19 Modified ADMA handling API for 32bit and 64bit addresses
-* 3.9 mn 03/03/20 Restructured the code for more readability and modularity
-* mn 03/16/20 Move XSdPs_Select_Card API to User APIs
-* 3.10 mn 06/05/20 Check Transfer completion separately from XSdPs_Read and
-* XSdPs_Write APIs
-* mn 06/05/20 Modified code for SD Non-Blocking Read support
-* 3.11 sk 12/01/20 Tap programming sequence updates like disable OTAPEN
-* always, write zero to tap register for zero tap value.
-* sk 12/07/20 Fix eMMC DDR52 mode write/read issue.
-* sk 12/17/20 Removed checking platform specific SD macros and used
-* Baseaddress instead.
-* 3.12 sk 01/28/21 Added support for non-blocking write.
-* sk 02/12/21 Fix the issue in reading CID and CSD.
-* sk 04/08/21 Fixed doxygen warnings in all source files.
-* sk 05/25/21 Fix the compilation issue in Cortex-A72 + EL1_NS by
-* removing the DLL reset logic (Dead code for Versal).
-* 3.13 sk 08/10/21 Limit the SD operating frequency to 19MHz for Versal.
-*
-*
-*
-******************************************************************************/
-
-
-#ifndef SDPS_H_
-#define SDPS_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xil_printf.h"
-#include "xil_cache.h"
-#include "xstatus.h"
-#include "xsdps_hw.h"
-#include "xplatform_info.h"
-#include "sleep.h"
-#include
-#if defined (XCLOCKING)
-#include "xil_clocking.h"
-#endif
-
-/************************** Constant Definitions *****************************/
-
-#define XSDPS_CT_ERROR 0x2L /**< Command timeout flag */
-#define MAX_TUNING_COUNT 40U /**< Maximum Tuning count */
-#define MAX_TIMEOUT 0x1FFFFFFFU /**< Maximum Timeout */
-#define XSDPS_CMD8_VOL_PATTERN 0x1AAU /**< CMD8 voltage pattern */
-#define XSDPS_RESPOCR_READY 0x80000000U /**< Ready response */
-#define XSDPS_ACMD41_HCS 0x40000000U /**< High Capacity Support */
-#define XSDPS_ACMD41_3V3 0x00300000U /**< 3.3 voltage support */
-#define XSDPS_CMD1_HIGH_VOL 0x00FF8000U /**< CMD1 for High voltage */
-#define XSDPS_CMD1_DUAL_VOL 0x00FF8010U /**< CMD1 for Dual voltage */
-#define HIGH_SPEED_SUPPORT 0x2U /**< High Speed support */
-#define UHS_SDR12_SUPPORT 0x1U /**< SDR12 support */
-#define UHS_SDR25_SUPPORT 0x2U /**< SDR25 support */
-#define UHS_SDR50_SUPPORT 0x4U /**< SDR50 support */
-#define UHS_SDR104_SUPPORT 0x8U /**< SDR104 support */
-#define UHS_DDR50_SUPPORT 0x10U /**< DDR50 support */
-#define WIDTH_4_BIT_SUPPORT 0x4U /**< 4-bit width support */
-#define SD_CLK_25_MHZ 25000000U /**< 25MHz clock */
-#define SD_CLK_19_MHZ 19000000U /**< 19MHz clock */
-#define SD_CLK_26_MHZ 26000000U /**< 26MHz clock */
-#define EXT_CSD_DEVICE_TYPE_BYTE 196U /**< CSD Device Type byte number */
-#define EXT_CSD_SEC_COUNT_BYTE1 212U /**< CSD Sector count byte 1 */
-#define EXT_CSD_SEC_COUNT_BYTE2 213U /**< CSD Sector count byte 2 */
-#define EXT_CSD_SEC_COUNT_BYTE3 214U /**< CSD Sector count byte 3 */
-#define EXT_CSD_SEC_COUNT_BYTE4 215U /**< CSD Sector count byte 4 */
-#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED 0x2U /**< CSD Device type HS */
-#define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED 0x4U /**< CSD Dev type DDR 1.8v speed */
-#define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED 0x8U /**< CSD Dev type DDR 1.2v speed */
-#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 0x10U /**< CSD SDR 1.8v HS200 */
-#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200 0x20U /**< CSD SDR 1.2v HS200 */
-#define CSD_SPEC_VER_3 0x3U /**< CSD card spec ver 3 */
-#define SCR_SPEC_VER_3 0x80U /**< SCR spec ver 3 */
-#define ADDRESS_BEYOND_32BIT 0x100000000U /**< Macro used for beyond 32-bit addr */
-
-#define XSDPS_ZYNQMP_SD0_BASE 0xFF160000U /**< ZynqMP SD0 Baseaddress */
-#define XSDPS_ZYNQMP_SD1_BASE 0xFF170000U /**< ZynqMP SD1 Baseaddress */
-#define XSDPS_VERSAL_SD0_BASE 0xF1040000U /**< Versal SD0 Baseaddress */
-#define XSDPS_VERSAL_SD1_BASE 0xF1050000U /**< Versal SD1 Baseaddress */
-
-/**************************** Type Definitions *******************************/
-
-/**
- * Function pointer for configuring the Tap delays.
- */
-typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of the device */
- u32 InputClockHz; /**< Input clock frequency */
- u32 CardDetect; /**< Card Detect */
- u32 WriteProtect; /**< Write Protect */
- u32 BusWidth; /**< Bus Width */
- u32 BankNumber; /**< MIO Bank selection for SD */
- u32 HasEMIO; /**< If SD is connected to EMIO */
- u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */
-#if defined (XCLOCKING)
- u32 RefClk; /**< Input clocks */
-#endif
-} XSdPs_Config;
-
-/**
- * ADMA2 32-Bit descriptor table
- */
-typedef struct {
- u16 Attribute; /**< Attributes of descriptor */
- u16 Length; /**< Length of current dma transfer */
- u32 Address; /**< Address of current dma transfer */
-#ifdef __ICCARM__
-#pragma data_alignment = 32
-} XSdPs_Adma2Descriptor32;
-#else
-} __attribute__((__packed__))XSdPs_Adma2Descriptor32;
-#endif
-
-/**
- * ADMA2 64-Bit descriptor table
- */
-typedef struct {
- u16 Attribute; /**< Attributes of descriptor */
- u16 Length; /**< Length of current dma transfer */
- u64 Address; /**< Address of current dma transfer */
-#ifdef __ICCARM__
-#pragma data_alignment = 32
-} XSdPs_Adma2Descriptor64;
-#else
-} __attribute__((__packed__))XSdPs_Adma2Descriptor64;
-#endif
-
-/**
- * The XSdPs driver instance data. The user is required to allocate a
- * variable of this type for every SD device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XSdPs_Config Config; /**< Configuration structure */
- u32 IsReady; /**< Device is initialized and ready */
- u32 Host_Caps; /**< Capabilities of host controller */
- u32 Host_CapsExt; /**< Extended Capabilities */
- u32 HCS; /**< High capacity support in card */
- u8 CardType; /**< Type of card - SD/MMC/eMMC */
- u8 Card_Version; /**< Card version */
- u8 HC_Version; /**< Host controller version */
- u8 BusWidth; /**< Current operating bus width */
- u32 BusSpeed; /**< Current operating bus speed */
- u8 Switch1v8; /**< 1.8V Switch support */
- u32 CardID[4]; /**< Card ID Register */
- u32 RelCardAddr; /**< Relative Card Address */
- u32 CardSpecData[4]; /**< Card Specific Data Register */
- u32 SectorCount; /**< Sector Count */
- u32 SdCardConfig; /**< Sd Card Configuration Register */
- u32 Mode; /**< Bus Speed Mode */
- u32 OTapDelay; /**< Output Tap Delay */
- u32 ITapDelay; /**< Input Tap Delay */
- u64 Dma64BitAddr; /**< 64 Bit DMA Address */
- u16 TransferMode; /**< Transfer Mode */
- u32 SlcrBaseAddr; /**< SLCR base address*/
- u8 IsBusy; /**< Busy Flag*/
- u32 BlkSize; /**< Block Size*/
-} XSdPs;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-/**
- * @name SD High Speed mode configuration options
- * @{
- */
-/**
- * User configuration option to enable or disable SD HS mode.
- * By default SD HS mode is disabled for Versal and enabled for
- * other platforms.
- */
-#ifdef versal
-#define SD_HS_MODE_ENABLE 0
-#else
-#define SD_HS_MODE_ENABLE 1
-#endif
-/** @} */
-
-/************************** Function Prototypes ******************************/
-XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
-s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
- u32 EffectiveAddr);
-s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
-s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
-s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
-s32 XSdPs_Idle(XSdPs *InstancePtr);
-
-s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr);
-s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq);
-s32 XSdPs_Pullup(XSdPs *InstancePtr);
-s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *ReadBuff);
-s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr);
-s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff);
-s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
-s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg);
-s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize);
-s32 XSdPs_Get_Status(XSdPs *InstancePtr, u8 *SdStatReg);
-s32 XSdPs_Select_Card(XSdPs *InstancePtr);
-s32 XSdPs_StartReadTransfer(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
-s32 XSdPs_CheckReadTransfer(XSdPs *InstancePtr);
-s32 XSdPs_StartWriteTransfer(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
-s32 XSdPs_CheckWriteTransfer(XSdPs *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SD_H_ */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/d0839f555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/d0839f555243001d18b399c1eb9b3628
deleted file mode 100644
index 90efcf4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a6/d0839f555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,23 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#include
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) clock_t clock(void);
-}
-#endif
-/*
- * clock -- It supposed to return processor time. We are not implementing
- * this function, as timekeeping is tightly coupled with system, hence
- * always returning 0. Users can override this with their system
- * specific implementation.
- *
- */
-__attribute__((weak)) clock_t clock(void)
-{
- return (0);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a7/00ec9e595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a7/00ec9e595243001d18b399c1eb9b3628
deleted file mode 100644
index e48c5f3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a7/00ec9e595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,111 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_errata.h
-*
-* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
-* @{
-* Various ARM errata are handled in the standalone BSP. The implementation for
-* errata handling follows ARM guidelines and is based on the open source Linux
-* support for these errata.
-*
-* @note The errata handling is enabled by default. To disable handling of all the
-* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
-* disable errata on a per-erratum basis, un-define relevant macros in
-* xil_errata.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a srt 04/18/13 First release
-* 6.6 mus 12/07/17 Removed errata 753970, It fixes CR#989132.
-*
-*
-******************************************************************************/
-#ifndef XIL_ERRATA_H
-#define XIL_ERRATA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *@cond nocomments
- */
-/**
- * @name errata_definitions
- *
- * The errata conditions handled in the standalone BSP are listed below
- * @{
- */
-
-#define ENABLE_ARM_ERRATA 1
-
-/**
- *@endcond
- */
-
-#ifdef ENABLE_ARM_ERRATA
-
-/**
- * Errata No: 742230
- * Description: DMB operation may be faulty
- */
-#define CONFIG_ARM_ERRATA_742230 1
-
-/**
- * Errata No: 743622
- * Description: Faulty hazard checking in the Store Buffer may lead
- * to data corruption.
- */
-#define CONFIG_ARM_ERRATA_743622 1
-
-/**
- * Errata No: 775420
- * Description: A data cache maintenance operation which aborts,
- * might lead to deadlock
- */
-#define CONFIG_ARM_ERRATA_775420 1
-
-/**
- * Errata No: 794073
- * Description: Speculative instruction fetches with MMU disabled
- * might not comply with architectural requirements
- */
-#define CONFIG_ARM_ERRATA_794073 1
-
-
-/** PL310 L2 Cache Errata */
-
-/**
- * Errata No: 588369
- * Description: Clean & Invalidate maintenance operations do not
- * invalidate clean lines
- */
-#define CONFIG_PL310_ERRATA_588369 1
-
-/**
- * Errata No: 727915
- * Description: Background Clean and Invalidate by Way operation
- * can cause data corruption
- */
-#define CONFIG_PL310_ERRATA_727915 1
-
-/*@}*/
-#endif /* ENABLE_ARM_ERRATA */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_ERRATA_H */
-/**
-* @} End of "addtogroup a9_errata".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a7/12e940555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a7/12e940555243001d18b399c1eb9b3628
deleted file mode 100644
index 4366107..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a7/12e940555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,118 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2017 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_smc.h
-*
-* @addtogroup a53_64_smc_api Cortex A53 64bit EL1 Non-secure SMC Call
-*
-* Cortex A53 64bit EL1 Non-secure SMC Call provides a C wrapper for calling
-* SMC from EL1 Non-secure application to request Secure monitor for secure
-* services. SMC calling conventions should be followed.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.2 pkp 02/16/17 First release
-* 6.4 mus 08/17/17 Added constant define for SMC ID , which is
-* intended to read the version/idcode of the
-* platform
-* 7.1 mus 07/31/19 Added support for Versal
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm 11/11/09 First release
-* 3.07a sgd 07/05/12 Updated sleep function to make use Global
-* 6.0 asa 08/15/16 Updated the sleep signature. Fix for CR#956899.
-* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
-* implementation. Now sleep routines will use Timer
-* specified by the user (i.e. Global timer/TTC timer)
-*
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "sleep.h"
-#include "xtime_l.h"
-#include "xparameters.h"
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#include "xil_sleeptimer.h"
-#endif
-
-/*****************************************************************************/
-/*
-*
-* This API is used to provide delays in seconds
-*
-* @param seconds requested
-*
-* @return 0 always
-*
-* @note None.
-*
-****************************************************************************/
-unsigned sleep_A9(unsigned int seconds)
-{
-#if defined (SLEEP_TIMER_BASEADDR)
- Xil_SleepTTCCommon(seconds, COUNTS_PER_SECOND);
-#else
- XTime tEnd, tCur;
-
- XTime_GetTime(&tCur);
- tEnd = tCur + (((XTime) seconds) * COUNTS_PER_SECOND);
- do
- {
- XTime_GetTime(&tCur);
- } while (tCur < tEnd);
-#endif
-
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a7/601ea6565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a7/601ea6565243001d18b399c1eb9b3628
deleted file mode 100644
index ec5f8b1..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a7/601ea6565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,184 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-* microblaze_scrub ()
-*
-* Scrub LMB memory and all internal BRAMs (data cache, instruction cache,
-* MMU UTLB and branch target cache) in MicroBlaze to reduce the possibility
-* of an uncorrectable error when fault tolerance support is enabled.
-*
-* This routine assumes that the processor is in privileged mode when it is
-* called, if the MMU is enabled.
-*
-* Call this routine regularly from a timer interrupt.
-*
-* Parameters:
-* None
-*
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-
-/* Define if fault tolerance is used */
-#ifdef XPAR_MICROBLAZE_FAULT_TOLERANT
- #if XPAR_MICROBLAZE_FAULT_TOLERANT > 0
- #define FAULT_TOLERANT
- #endif
-#endif
-
-/* Define if LMB is used and can be scrubbed */
-#if defined(XPAR_MICROBLAZE_D_LMB) && \
- defined(XPAR_DLMB_CNTLR_BASEADDR) && \
- defined(XPAR_DLMB_CNTLR_HIGHADDR)
- #if XPAR_MICROBLAZE_D_LMB == 1
- #define HAS_SCRUBBABLE_LMB
- #define DLMB_MASK (XPAR_DLMB_CNTLR_HIGHADDR - XPAR_DLMB_CNTLR_BASEADDR)
- #endif
-#endif
-
-/* Set default cache line lengths */
-#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
- #define XPAR_MICROBLAZE_DCACHE_LINE_LEN 4
-#endif
-
-#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
- #define XPAR_MICROBLAZE_ICACHE_LINE_LEN 4
-#endif
-
-/* Define if internal Data Cache BRAMs are used */
-#if defined(XPAR_MICROBLAZE_USE_DCACHE) && defined(XPAR_MICROBLAZE_DCACHE_BYTE_SIZE)
- #if XPAR_MICROBLAZE_USE_DCACHE == 1 && XPAR_MICROBLAZE_DCACHE_BYTE_SIZE > 1024
- #define HAS_BRAM_DCACHE
- #define DCACHE_INCREMENT (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
- #define DCACHE_MASK (XPAR_MICROBLAZE_DCACHE_BYTE_SIZE - 1)
- #endif
-#endif
-
-/* Define if internal Instruction Cache BRAMs are used */
-#if defined(XPAR_MICROBLAZE_USE_ICACHE) && defined(XPAR_MICROBLAZE_CACHE_BYTE_SIZE)
- #if XPAR_MICROBLAZE_USE_ICACHE == 1 && XPAR_MICROBLAZE_CACHE_BYTE_SIZE > 1024
- #define HAS_BRAM_ICACHE
- #define ICACHE_INCREMENT (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4)
- #define ICACHE_MASK (XPAR_MICROBLAZE_CACHE_BYTE_SIZE - 1)
- #endif
-#endif
-
-/* Define if internal MMU UTLB BRAM is used */
-#ifdef XPAR_MICROBLAZE_USE_MMU
- #if XPAR_MICROBLAZE_USE_MMU > 1
- #define HAS_BRAM_MMU_UTLB
- #endif
-#endif
-
-/* Define if internal BTC BRAM is used, and match BTC clear to a complete cache scrub */
-#if defined(XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE) && \
- defined(XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE)
- #if XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE == 1
- #if XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE == 0 || \
- XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE > 4
- #define HAS_BRAM_BRANCH_TARGET_CACHE
- #ifdef HAS_BRAM_DCACHE
- #define BTC_MASK_D (XPAR_MICROBLAZE_DCACHE_BYTE_SIZE/DCACHE_INCREMENT-1)
- #else
- #define BTC_MASK_D 256
- #endif
- #ifdef HAS_BRAM_ICACHE
- #define BTC_MASK_I (XPAR_MICROBLAZE_CACHE_BYTE_SIZE/ICACHE_INCREMENT-1)
- #else
- #define BTC_MASK_I 256
- #endif
- #if BTC_MASK_D > BTC_MASK_I
- #define BTC_MASK BTC_MASK_D
- #else
- #define BTC_MASK BTC_MASK_I
- #endif
- #endif
- #endif
-#endif
-
-/* Define index offsets to persistent data used by this routine */
-#define DLMB_INDEX_OFFSET 0
-#define DCACHE_INDEX_OFFSET 4
-#define ICACHE_INDEX_OFFSET 8
-#define MMU_INDEX_OFFSET 12
-#define BTC_CALL_COUNT_OFFSET 16
-
- .text
- .globl microblaze_scrub
- .ent microblaze_scrub
- .align 2
-
-microblaze_scrub:
-#ifdef FAULT_TOLERANT
- la r6, r0, L_persistent_data /* Get pointer to data */
-
-#ifdef HAS_SCRUBBABLE_LMB
-L_dlmb:
- lwi r5, r6, DLMB_INDEX_OFFSET /* Get dlmb index */
- lw r7, r5, r0 /* Load and store */
- sw r7, r5, r0
- addik r5, r5, 4 /* Increment and save dlmb index */
- andi r5, r5, DLMB_MASK
- swi r5, r6, DLMB_INDEX_OFFSET
-#endif /* HAS_SCRUBBABLE_LMB */
-
-#ifdef HAS_BRAM_DCACHE
-L_dcache:
- lwi r5, r6, DCACHE_INDEX_OFFSET /* Get dcache line index */
- wdc r5, r0 /* Invalidate data cache line */
- addik r5, r5, DCACHE_INCREMENT /* Increment and save entry index */
- andi r5, r5, DCACHE_MASK
- swi r5, r6, DCACHE_INDEX_OFFSET
-#endif /* HAS_BRAM_DCACHE */
-
-#ifdef HAS_BRAM_ICACHE
-L_icache:
- lwi r5, r6, ICACHE_INDEX_OFFSET /* Get icache line index */
- wic r5, r0 /* Invalidate data cache line */
- addik r5, r5, ICACHE_INCREMENT /* Increment and save entry index */
- andi r5, r5, ICACHE_MASK
- swi r5, r6, ICACHE_INDEX_OFFSET
-#endif /* HAS_BRAM_ICACHE */
-
-#ifdef HAS_BRAM_MMU_UTLB
-L_mmu:
- lwi r5, r6, MMU_INDEX_OFFSET /* Get UTLB entry index */
- mts rtlbx, r5 /* Access next entry in UTLB */
- mts rtlbhi, r0 /* Clear the UTLB entry */
-
- addik r5, r5, 1 /* Increment and save entry index */
- andi r5, r5, 0x3F
- swi r5, r6, MMU_INDEX_OFFSET
-#endif /* HAS_BRAM_MMU_UTLB */
-
-#ifdef HAS_BRAM_BRANCH_TARGET_CACHE
-L_btc:
- lwi r5, r6, BTC_CALL_COUNT_OFFSET /* Get BTC call count offset */
- addik r5, r5, 1 /* Increment and save call count */
- andi r5, r5, BTC_MASK
- swi r5, r6, BTC_CALL_COUNT_OFFSET
-
- bnei r5, L_skip_btc_scrub /* Skip scrub unless count wrap */
- bri 4 /* Clear branch target cache */
-L_skip_btc_scrub:
-#endif /* HAS_BRAM_BRANCH_TARGET_CACHE */
-
-#endif /* FAULT_TOLERANT */
-L_done:
- rtsd r15, 8 /* Return */
- nop
- .end microblaze_scrub
-
- /* Persistent data used by this routine */
- .data
- .align 2
-L_persistent_data:
- .long 0 /* dlmb index */
- .long 0 /* dcache index */
- .long 0 /* icache index */
- .long 0 /* mmu entry index */
- .long 0 /* btc call count */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a7/80e603525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a7/80e603525243001d18b399c1eb9b3628
deleted file mode 100644
index ab7a047..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a7/80e603525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1 +0,0 @@
-2182947523
\ No newline at end of file
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a7/b2992f575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a7/b2992f575243001d18b399c1eb9b3628
deleted file mode 100644
index 8eea377..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a7/b2992f575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,2 +0,0 @@
-*startfile:
-crti%O%s crtbegin%O%s
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a7/d15eba555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a7/d15eba555243001d18b399c1eb9b3628
deleted file mode 100644
index f0102aa..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a7/d15eba555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,54 +0,0 @@
-/* putnum.c -- put a hex number on the output device.
- *
- * Copyright (c) 1995 Cygnus Support
- *
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
- * putnum -- print a 32 bit number in hex
- */
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-
-/************************** Function Prototypes ******************************/
-extern void print (const char8 *ptr);
-void putnum(u32 num);
-
-void putnum(u32 num)
-{
- char8 buf[9];
- s32 cnt;
- s32 i;
- char8 *ptr;
- u32 digit;
- for(i = 0; i<9; i++) {
- buf[i] = '0';
- }
-
- ptr = buf;
- for (cnt = 7 ; cnt >= 0 ; cnt--) {
- digit = (num >> (cnt * 4U)) & 0x0000000fU;
-
- if (digit <= 9U) {
- digit += (u32)'0';
- *ptr = ((char8) digit);
- ptr += 1;
- } else {
- digit += ((u32)'a' - (u32)10);
- *ptr = ((char8)digit);
- ptr += 1;
- }
- }
-
- print (buf);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a8/8000ca535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a8/8000ca535243001d18b399c1eb9b3628
deleted file mode 100644
index d1bd537..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a8/8000ca535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,320 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xparameters_ps.h
-*
-* This file contains the address definitions for the hard peripherals
-* attached to the ARM Cortex A9 core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 1.00a ecm/sdm 02/01/10 Initial version
-* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
-* driver tcl
-* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
-* 6.6 srm 10/18/17 Added ARMA9 macro to identify CortexA9
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b ch 10/24/02 Added XENV_LINUX
-* 1.00a rmm 04/17/02 First release
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XENV_H /* prevent circular inclusions */
-#define XENV_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * Select which target environment we are operating under
- */
-
-/* VxWorks target environment */
-#if defined XENV_VXWORKS
-#include "xenv_vxworks.h"
-
-/* Linux target environment */
-#elif defined XENV_LINUX
-#include "xenv_linux.h"
-
-/* Unit test environment */
-#elif defined XENV_UNITTEST
-#include "ut_xenv.h"
-
-/* Integration test environment */
-#elif defined XENV_INTTEST
-#include "int_xenv.h"
-
-/* Standalone environment selected */
-#else
-#include "xenv_standalone.h"
-#endif
-
-
-/*
- * The following comments specify the types and macro wrappers that are
- * expected to be defined by the target specific header files
- */
-
-/**************************** Type Definitions *******************************/
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP
- *
- * A structure that contains a time stamp used by other time stamp macros
- * defined below. This structure is processor dependent.
- */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- *
- * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
- *
- * Copies a non-overlapping block of memory.
- *
- * @param DestPtr is the destination address to copy data to.
- * @param SrcPtr is the source address to copy data from.
- * @param Bytes is the number of bytes to copy.
- *
- * @return None
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
- *
- * Fills an area of memory with constant data.
- *
- * @param DestPtr is the destination address to set.
- * @param Data contains the value to set.
- * @param Bytes is the number of bytes to set.
- *
- * @return None
- */
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
- *
- * Samples the processor's or external timer's time base counter.
- *
- * @param StampPtr is the storage for the retrieved time stamp.
- *
- * @return None
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
- *
- * Computes the delta between the two time stamps.
- *
- * @param Stamp1Ptr - First sampled time stamp.
- * @param Stamp1Ptr - Sedond sampled time stamp.
- *
- * @return An unsigned int value with units of microseconds.
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
- *
- * Computes the delta between the two time stamps.
- *
- * @param Stamp1Ptr - First sampled time stamp.
- * @param Stamp1Ptr - Sedond sampled time stamp.
- *
- * @return An unsigned int value with units of milliseconds.
- */
-
-/*****************************************************************************//**
- *
- * XENV_USLEEP(unsigned delay)
- *
- * Delay the specified number of microseconds.
- *
- * @param delay is the number of microseconds to delay.
- *
- * @return None
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a8/82c4b5585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a8/82c4b5585243001d18b399c1eb9b3628
deleted file mode 100644
index d986349..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a8/82c4b5585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,240 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm_gcc.h
-*
-* This header file contains macros for using inline assembler code. It is
-* written specifically for the GNU compiler.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/21/14 First release
-* 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors
-* 7.2 asa 04/03/20 Renamed the str macro to strw.
-* 7.2 dp 04/30/20 Added clobber "cc" to mtcpsr for aarch32 processors
-*
-; MODIFICATION HISTORY:
-;
-; Ver Who Date Changes
-; ----- ------- -------- ---------------------------------------------------
-; 6.2 mus 01/27/17 Initial version
-;
-;
-; @note
-;
-; None.
-;
-;*****************************************************************************/
-
- MODULE ?asm_vectors
-
- ;; Forward declaration of sections.
- SECTION IRQ_STACK:DATA:NOROOT(3)
- SECTION FIQ_STACK:DATA:NOROOT(3)
- SECTION SVC_STACK:DATA:NOROOT(3)
- SECTION ABT_STACK:DATA:NOROOT(3)
- SECTION UND_STACK:DATA:NOROOT(3)
- SECTION CSTACK:DATA:NOROOT(3)
-
-#define UART_BAUDRATE 115200
-
- IMPORT _prestart
- IMPORT __iar_program_start
-
- SECTION .intvec:CODE:NOROOT(2)
-
-
-
- PUBLIC _vector_table
-
- IMPORT FIQInterrupt
- IMPORT IRQInterrupt
- IMPORT SWInterrupt
- IMPORT DataAbortInterrupt
- IMPORT PrefetchAbortInterrupt
- IMPORT UndefinedException
- IMPORT UndefinedExceptionAddr
- IMPORT PrefetchAbortAddr
- IMPORT DataAbortAddr
-
- IMPORT prof_pc
-
-
-_vector_table
- ARM
- ldr pc,=__iar_program_start
- ldr pc,=Undefined
- ldr pc,=SVCHandler
- ldr pc,=PrefetchAbortHandler
- ldr pc,=DataAbortHandler
- NOP ; Placeholder for address exception vector
- ldr pc,=IRQHandler
- ldr pc,=FIQHandler
-
- SECTION .text:CODE:NOROOT(2)
- REQUIRE _vector_table
-
- ARM
-IRQHandler ; IRQ vector handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
-#ifndef __SOFTFP__
- vpush {d0-d7} /* Store floating point registers */
- vmrs r1, FPSCR
- push {r1}
- vmrs r1, FPEXC
- push {r1}
-#endif
- bl IRQInterrupt ; IRQ vector
-#ifndef __SOFTFP__
- pop {r1} /* Restore floating point registers */
- vmsr FPEXC, r1
- pop {r1}
- vmsr FPSCR, r1
- vpop {d0-d7}
-#endif
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- subs pc, lr, #4 ; adjust return
-
-FIQHandler ; FIQ vector handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
-FIQLoop
- bl FIQInterrupt ; FIQ vector
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- subs pc, lr, #4 ; adjust return
-
-Undefined ; Undefined handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- ldr r0, =UndefinedExceptionAddr
- sub r1, lr, #4
- str r1, [r0] ; Store address of instruction causing undefined exception
-
- bl UndefinedException ; UndefinedException: call C function here
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- movs pc, lr
-
-SVCHandler ; SWI handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- tst r0, #0x20 ; check the T bit
- ldrneh r0, [lr,#-2] ; Thumb mode
- bicne r0, r0, #0xff00 ; Thumb mode
- ldreq r0, [lr,#-4] ; ARM mode
- biceq r0, r0, #0xff000000 ; ARM mode
- bl SWInterrupt ; SWInterrupt: call C function here
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- movs pc, lr ; adjust return
-
-DataAbortHandler ; Data Abort handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- ldr r0, =DataAbortAddr
- sub r1, lr, #8
- str r1, [r0] ; Stores instruction causing data abort
- bl DataAbortInterrupt ;DataAbortInterrupt :call C function here
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- subs pc, lr, #8 ; adjust return
-
-PrefetchAbortHandler ; Prefetch Abort handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- ldr r0, =PrefetchAbortAddr
- sub r1, lr, #4
- str r1, [r0] ; Stores instruction causing prefetch abort */
- bl PrefetchAbortInterrupt ; PrefetchAbortInterrupt: call C function here */
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code */
- subs pc, lr, #4 ; adjust return */
-
-
- END
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a9/801479595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a9/801479595243001d18b399c1eb9b3628
deleted file mode 100644
index d279665..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a9/801479595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,392 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.h
-*
-* @addtogroup microblaze_cache_apis Microblaze Cache APIs
-* @{
-*
-*
-* The xil_cache.h file contains cache related driver functions (or macros)
-* that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-* The functions in this header file can be used across all Xilinx supported
-* processors.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00 hbm 07/28/09 Initial release
-* 3.02a sdm 10/24/11 Updated the file to include xparameters.h so that
-* the correct cache flush routines are used based on
-* whether the write-back or write-through caches are
-* used (cr #630532).
-* 3.10a asa 05/04/13 This version of MicroBlaze BSP adds support for system
-* cache/L2 cache. The existing/old APIs/macros in this
-* file are renamed to imply that they deal with L1 cache.
-* New macros/APIs are added to address similar features for
-* L2 cache. Users can include this file in their application
-* to use the various cache related APIs. These changes are
-* done for implementing PR #697214.
-*
-*
-*
-*
-******************************************************************************/
-
-#ifndef XIL_CACHE_H
-#define XIL_CACHE_H
-
-#if defined XENV_VXWORKS
-/* VxWorks environment */
-#error "Unknown processor / architecture. Must be PPC for VxWorks."
-#else
-/* standalone environment */
-
-#include "mb_interface.h"
-#include "xil_types.h"
-#include "xparameters.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/****************************************************************************/
-/**
-*
-* @brief Invalidate the entire L1 data cache. If the cacheline is modified
-* (dirty), the modified contents are lost.
-*
-*
-* @return None.
-*
-* @note Processor must be in real mode.
-****************************************************************************/
-#define Xil_L1DCacheInvalidate() microblaze_invalidate_dcache()
-
-/****************************************************************************/
-/**
-*
-* @brief Invalidate the entire L2 data cache. If the cacheline is modified
-* (dirty),the modified contents are lost.
-*
-* @return None.
-*
-* @note Processor must be in real mode.
-****************************************************************************/
-#define Xil_L2CacheInvalidate() microblaze_invalidate_cache_ext()
-
-/****************************************************************************/
-/**
-*
-* @brief Invalidate the L1 data cache for the given address range.
-* If the bytes specified by the address (Addr) are cached by the L1
-* data cache, the cacheline containing that byte is invalidated.If
-* the cacheline is modified (dirty), the modified contents are lost.
-*
-* @param Addr is address of range to be invalidated.
-* @param Len is the length in bytes to be invalidated.
-*
-* @return None.
-*
-* @note Processor must be in real mode.
-****************************************************************************/
-#define Xil_L1DCacheInvalidateRange(Addr, Len) \
- microblaze_invalidate_dcache_range((Addr), (Len))
-
-/****************************************************************************/
-/**
-*
-* @brief Invalidate the L1 data cache for the given address range.
-* If the bytes specified by the address (Addr) are cached by the
-* L1 data cache, the cacheline containing that byte is invalidated.
-* If the cacheline is modified (dirty), the modified contents are lost.
-*
-* @param Addr: address of range to be invalidated.
-* @param Len: length in bytes to be invalidated.
-*
-* @return None.
-*
-* @note Processor must be in real mode.
-****************************************************************************/
-#define Xil_L2CacheInvalidateRange(Addr, Len) \
- microblaze_invalidate_cache_ext_range((Addr), (Len))
-
-/****************************************************************************/
-/**
-* @brief Flush the L1 data cache for the given address range.
-* If the bytes specified by the address (Addr) are cached by the
-* data cache, and is modified (dirty), the cacheline will be written
-* to system memory.The cacheline will also be invalidated.
-*
-* @param Addr: the starting address of the range to be flushed.
-* @param Len: length in byte to be flushed.
-*
-* @return None.
-*
-****************************************************************************/
-#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
-# define Xil_L1DCacheFlushRange(Addr, Len) \
- microblaze_flush_dcache_range((Addr), (Len))
-#else
-# define Xil_L1DCacheFlushRange(Addr, Len) \
- microblaze_invalidate_dcache_range((Addr), (Len))
-#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */
-
-/****************************************************************************/
-/**
-* @brief Flush the L2 data cache for the given address range.
-* If the bytes specified by the address (Addr) are cached by the
-* data cache, and is modified (dirty), the cacheline will be
-* written to system memory. The cacheline will also be invalidated.
-*
-* @param Addr: the starting address of the range to be flushed.
-* @param Len: length in byte to be flushed.
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_L2CacheFlushRange(Addr, Len) \
- microblaze_flush_cache_ext_range((Addr), (Len))
-
-/****************************************************************************/
-/**
-* @brief Flush the entire L1 data cache. If any cacheline is dirty, the
-* cacheline will be written to system memory. The entire data cache
-* will be invalidated.
-*
-* @return None.
-*
-****************************************************************************/
-#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
-# define Xil_L1DCacheFlush() microblaze_flush_dcache()
-#else
-# define Xil_L1DCacheFlush() microblaze_invalidate_dcache()
-#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */
-
-/****************************************************************************/
-/**
-* @brief Flush the entire L2 data cache. If any cacheline is dirty, the
-* cacheline will be written to system memory. The entire data cache
-* will be invalidated.
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_L2CacheFlush() microblaze_flush_cache_ext()
-
-/****************************************************************************/
-/**
-*
-* @brief Invalidate the instruction cache for the given address range.
-*
-* @param Addr is address of ragne to be invalidated.
-* @param Len is the length in bytes to be invalidated.
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_L1ICacheInvalidateRange(Addr, Len) \
- microblaze_invalidate_icache_range((Addr), (Len))
-
-/****************************************************************************/
-/**
-*
-* @brief Invalidate the entire instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_L1ICacheInvalidate() \
- microblaze_invalidate_icache()
-
-
-/****************************************************************************/
-/**
-*
-* @brief Enable the L1 data cache.
-*
-* @return None.
-*
-* @note This is processor specific.
-*
-****************************************************************************/
-#define Xil_L1DCacheEnable() \
- microblaze_enable_dcache()
-
-/****************************************************************************/
-/**
-*
-* @brief Disable the L1 data cache.
-*
-* @return None.
-*
-* @note This is processor specific.
-*
-****************************************************************************/
-#define Xil_L1DCacheDisable() \
- microblaze_disable_dcache()
-
-/****************************************************************************/
-/**
-*
-* @brief Enable the instruction cache.
-*
-* @return None.
-*
-* @note This is processor specific.
-*
-****************************************************************************/
-#define Xil_L1ICacheEnable() \
- microblaze_enable_icache()
-
-/****************************************************************************/
-/**
-*
-* @brief Disable the L1 Instruction cache.
-*
-* @return None.
-*
-* @note This is processor specific.
-*
-****************************************************************************/
-#define Xil_L1ICacheDisable() \
- microblaze_disable_icache()
-
-/****************************************************************************/
-/**
-*
-* @brief Enable the data cache.
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_DCacheEnable() Xil_L1DCacheEnable()
-
-/****************************************************************************/
-/**
-*
-* @brief Enable the instruction cache.
-*
-* @return None.
-*
-*
-****************************************************************************/
-#define Xil_ICacheEnable() Xil_L1ICacheEnable()
-
-/****************************************************************************/
-/**
-*
-* @brief Invalidate the entire Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_DCacheInvalidate() \
- Xil_L2CacheInvalidate(); \
- Xil_L1DCacheInvalidate();
-
-
-/****************************************************************************/
-/**
-*
-* @brief Invalidate the Data cache for the given address range.
-* If the bytes specified by the address (adr) are cached by the
-* Data cache, the cacheline containing that byte is invalidated.
-* If the cacheline is modified (dirty), the modified contents are
-* lost and are NOT written to system memory before the line is
-* invalidated.
-*
-* @param Addr: Start address of range to be invalidated.
-* @param Len: Length of range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_DCacheInvalidateRange(Addr, Len) \
- Xil_L2CacheInvalidateRange((Addr), (Len)); \
- Xil_L1DCacheInvalidateRange((Addr), (Len));
-
-
-/****************************************************************************/
-/**
-*
-* @brief Flush the entire Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_DCacheFlush() \
- Xil_L2CacheFlush(); \
- Xil_L1DCacheFlush();
-
-/****************************************************************************/
-/**
-* @brief Flush the Data cache for the given address range.
-* If the bytes specified by the address (adr) are cached by the
-* Data cache, the cacheline containing that byte is invalidated.
-* If the cacheline is modified (dirty), the written to system
-* memory first before the before the line is invalidated.
-*
-* @param Addr: Start address of range to be flushed.
-* @param Len: Length of range to be flushed in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_DCacheFlushRange(Addr, Len) \
- Xil_L2CacheFlushRange((Addr), (Len)); \
- Xil_L1DCacheFlushRange((Addr), (Len));
-
-
-/****************************************************************************/
-/**
-* @brief Invalidate the entire instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_ICacheInvalidate() \
- Xil_L2CacheInvalidate(); \
- Xil_L1ICacheInvalidate();
-
-
-/****************************************************************************/
-/**
-* @brief Invalidate the instruction cache for the given address range.
-* If the bytes specified by the address (adr) are cached by the
-* Data cache, the cacheline containing that byte is invalidated.
-* If the cacheline is modified (dirty), the modified contents are
-* lost and are NOT written to system memory before the line is
-* invalidated.
-*
-* @param Addr: Start address of ragne to be invalidated.
-* @param Len: Length of range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_ICacheInvalidateRange(Addr, Len) \
- Xil_L2CacheInvalidateRange((Addr), (Len)); \
- Xil_L1ICacheInvalidateRange((Addr), (Len));
-
-void Xil_DCacheDisable(void);
-void Xil_ICacheDisable(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
-/**
-* @} End of "addtogroup microblaze_cache_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a9/910003565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a9/910003565243001d18b399c1eb9b3628
deleted file mode 100644
index d1bd537..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/a9/910003565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,320 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xparameters_ps.h
-*
-* This file contains the address definitions for the hard peripherals
-* attached to the ARM Cortex A9 core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 1.00a ecm/sdm 02/01/10 Initial version
-* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
-* driver tcl
-* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
-* 6.6 srm 10/18/17 Added ARMA9 macro to identify CortexA9
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 3.9 mn 03/03/20 Restructured the code for more readability and modularity
-* mn 03/16/20 Move XSdPs_Select_Card API to User APIs
-* 3.12 sk 01/28/21 Added support for non-blocking write.
-*
-*
-*
-******************************************************************************/
-
-#ifndef SDPS_INCLUDE_H_
-#define SDPS_INCLUDE_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xsdps.h"
-#if defined (__aarch64__)
-#include "xil_smc.h"
-#endif
-
-/** @cond INTERNAL */
-s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr);
-s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr);
-s32 XSdPs_IdentifyCard(XSdPs *InstancePtr);
-s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
-s32 XSdPs_SetupTransfer(XSdPs *InstancePtr);
-s32 XSdPs_Read(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
-s32 XSdPs_Write(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
-s32 XSdPs_CheckTransferComplete(XSdPs *InstancePtr);
-void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff);
-s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
-s32 XSdPs_DllReset(XSdPs *InstancePtr);
-s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr);
-void XSdPs_SetupADMA2DescTbl64Bit(XSdPs *InstancePtr, u32 BlkCnt);
-void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
-void XSdPs_DllRstCtrl(XSdPs *InstancePtr, u8 EnRst);
-void XSdPs_ConfigTapDelay(XSdPs *InstancePtr);
-s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr);
-void XSdPs_Setup32ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
-void XSdPs_Setup64ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
-u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd);
-void XSdPs_SetTapDelay(XSdPs *InstancePtr);
-s32 XSdPs_CheckResetDone(XSdPs *InstancePtr, u8 Value);
-s32 XSdPs_CheckVoltage18(XSdPs *InstancePtr);
-s32 XSdPs_SetupCmd(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt);
-void XSdPs_SetExecTuning(XSdPs *InstancePtr);
-s32 XSdPs_CheckCardDetect(XSdPs *InstancePtr);
-s32 XSdPs_CardReset(XSdPs *InstancePtr);
-s32 XSdPs_CardIfCond(XSdPs *InstancePtr);
-s32 XSdPs_CardOpCond(XSdPs *InstancePtr);
-s32 XSdPs_GetCardId(XSdPs *InstancePtr);
-s32 XSdPs_GetCsd(XSdPs *InstancePtr);
-s32 XSdPs_CardSetVoltage18(XSdPs *InstancePtr);
-s32 XSdPs_SdModeInit(XSdPs *InstancePtr);
-s32 XSdPs_SdCardEnum(XSdPs *InstancePtr);
-s32 XSdPs_MmcCardEnum(XSdPs *InstancePtr);
-s32 XSdPs_MmcModeInit(XSdPs *InstancePtr);
-s32 XSdPs_EmmcModeInit(XSdPs *InstancePtr);
-s32 XSdPs_ResetConfig(XSdPs *InstancePtr);
-void XSdPs_HostConfig(XSdPs *InstancePtr);
-s32 XSdPs_Reset(XSdPs *InstancePtr, u8 Value);
-void XSdPs_DisableBusPower(XSdPs *InstancePtr);
-void XSdPs_EnableBusPower(XSdPs *InstancePtr);
-s32 XSdPs_CheckBusIdle(XSdPs *InstancePtr, u32 Value);
-s32 XSdPs_CheckBusHigh(XSdPs *InstancePtr);
-s32 XSdPs_SetupVoltageSwitch(XSdPs *InstancePtr);
-s32 XSdPs_AutoTuning(XSdPs *InstancePtr);
-s32 XSdPs_SetClock(XSdPs *InstancePtr, u32 SelFreq);
-u32 XSdPs_CalcClock(XSdPs *InstancePtr, u32 SelFreq);
-s32 XSdPs_EnableClock(XSdPs *InstancePtr, u16 ClockReg);
-s32 XSdps_CheckTransferDone(XSdPs *InstancePtr);
-s32 XSdPs_Change_SdBusSpeed(XSdPs *InstancePtr);
-s32 XSdPs_Change_MmcBusSpeed(XSdPs *InstancePtr);
-s32 XSdPs_CalcBusSpeed(XSdPs *InstancePtr, u32 *Arg);
-void XSdPs_SetupReadDma(XSdPs *InstancePtr, u16 BlkCnt, u16 BlkSize, u8 *Buff);
-void XSdPs_SetupWriteDma(XSdPs *InstancePtr, u16 BlkCnt, u16 BlkSize, const u8 *Buff);
-s32 XSdPs_DoDmaTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
-s32 XSdPs_DoCmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
-s32 XSdPs_SetVoltage18(XSdPs *InstancePtr);
-s32 XSdPs_SendCmd(XSdPs *InstancePtr, u32 Cmd);
-void XSdPs_IdentifyEmmcMode(XSdPs *InstancePtr, const u8 *ExtCsd);
-s32 XSdPs_CheckEmmcTiming(XSdPs *InstancePtr, u8 *ExtCsd);
-void XSdPs_ConfigPower(XSdPs *InstancePtr);
-void XSdPs_ConfigDma(XSdPs *InstancePtr);
-void XSdPs_ConfigInterrupt(XSdPs *InstancePtr);
-
-#if EL1_NONSECURE && defined (__aarch64__)
-void XSdps_Smc(XSdPs *InstancePtr, u32 RegOffset, u32 Mask, u32 Val);
-#endif
-/** @endcond */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ab/1098fd575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ab/1098fd575243001d18b399c1eb9b3628
deleted file mode 100644
index e79ba0d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ab/1098fd575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,788 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xqspips.h
-* @addtogroup qspips_v3_9
-* @{
-* @details
-*
-* This file contains the implementation of the XQspiPs driver. It supports only
-* master mode. User documentation for the driver functions is contained in this
-* file in the form of comment blocks at the front of each function.
-*
-* A QSPI device connects to an QSPI bus through a 4-wire serial interface.
-* The QSPI bus is a full-duplex, synchronous bus that facilitates communication
-* between one master and one slave. The device is always full-duplex,
-* which means that for every byte sent, one is received, and vice-versa.
-* The master controls the clock, so it can regulate when it wants to
-* send or receive data. The slave is under control of the master, it must
-* respond quickly since it has no control of the clock and must send/receive
-* data as fast or as slow as the master does.
-*
-* Linear Mode
-* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller�s
-* functionality by adding a linear addressing scheme that allows the SPI flash
-* memory subsystem to behave like a typical ROM device. The new feature hides
-* the normal SPI protocol from a master reading from the SPI flash memory. The
-* feature improves both the user friendliness and the overall read memory
-* throughput over that of the current Quad-SPI Controller by lessening the
-* amount of software overheads required and by the use of the faster AXI
-* interface.
-*
-* Initialization & Configuration
-*
-* The XQspiPs_Config structure is used by the driver to configure itself. This
-* configuration structure is typically created by the tool-chain based on HW
-* build properties.
-*
-* To support multiple runtime loading and initialization strategies employed by
-* various operating systems, the driver instance can be initialized in the
-* following way:
-* - XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find
-* static configuration structure defined in xqspips_g.c. This is setup
-* by the tools. For some operating systems the config structure will be
-* initialized by the software and this call is not needed.
-* - XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-* configuration structure provided by the caller. If running in a system
-* with address translation, the provided virtual memory base address
-* replaces the physical address present in the configuration structure.
-*
-* Multiple Masters
-*
-* More than one master can exist, but arbitration is the responsibility of
-* the higher layer software. The device driver does not perform any type of
-* arbitration.
-*
-* Modes of Operation
-*
-* There are four modes to perform a data transfer and the selection of a mode
-* is based on Chip Select(CS) and Start. These two options individually, can
-* be controlled either by software(Manual) or hardware(Auto).
-* - Auto CS: Chip select is automatically asserted as soon as the first word
-* is written into the TXFIFO and de asserted when the TXFIFO becomes
-* empty
-* - Manual CS: Software must assert and de assert CS.
-* - Auto Start: Data transmission starts as soon as there is data in the
-* TXFIFO and stalls when the TXFIFO is empty
-* - Manual Start: Software must start data transmission at the beginning of
-* the transaction or whenever the TXFIFO has become empty
-*
-* The preferred combination is Manual CS and Auto Start.
-* In this combination, the software asserts CS before loading any data into
-* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
-* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
-* data is available. If no further data, software disables CS.
-*
-* Risks/challenges of other combinations:
-* - Manual CS and Manual Start: Manual Start bit should be set after each
-* TXFIFO write otherwise there could be a race condition where the TXFIFO
-* becomes empty before the new word is written. In that case the
-* transmission stops.
-* - Auto CS with Manual or Auto Start: It is very difficult for software to
-* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted.
-* This results in a single transaction to be split into multiple pieces each
-* with its own chip select. This will result in garbage data to be sent.
-*
-* Interrupts
-*
-* The user must connect the interrupt handler of the driver,
-* XQspiPs_InterruptHandler, to an interrupt system such that it will be
-* called when an interrupt occurs. This function does not save and restore
-* the processor context such that the user must provide this processing.
-*
-* The driver handles the following interrupts:
-* - Data Transmit Register/FIFO Underflow
-* - Data Receive Register/FIFO Not Empty
-* - Data Transmit Register/FIFO Overwater
-* - Data Receive Register/FIFO Overrun
-*
-* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
-* QSPI device has transmitted the data available to transmit, and now its data
-* register and FIFO is ready to accept more data. The driver uses this
-* interrupt to indicate progress while sending data. The driver may have
-* more data to send, in which case the data transmit register and FIFO is
-* filled for subsequent transmission. When this interrupt arrives and all
-* the data has been sent, the driver invokes the status callback with a
-* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
-* all data has been sent.
-*
-* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
-* as slave, the QSPI device was required to transmit but there was no data
-* available to transmit in the transmit register (or FIFO). This may not
-* be an error if the master is not expecting data. But in the case where
-* the master is expecting data, this serves as a notification of such a
-* condition. The driver reports this condition to the upper layer
-* software through the status handler.
-*
-* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI
-* device received data and subsequently dropped the data because the data
-* receive register and FIFO was full. The driver reports this condition to the
-* upper layer software through the status handler. This likely indicates a
-* problem with the higher layer protocol, or a problem with the slave
-* performance.
-*
-*
-* Polled Operation
-*
-* Transfer in polled mode is supported through a separate interface function
-* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
-* this function blocks until all data has been sent/received.
-*
-* Device Busy
-*
-* Some operations are disallowed when the device is busy. The driver tracks
-* whether a device is busy. The device is considered busy when a data transfer
-* request is outstanding, and is considered not busy only when that transfer
-* completes (or is aborted with a mode fault error).
-*
-* Device Configuration
-*
-* The device can be configured in various ways during the FPGA implementation
-* process. Configuration parameters are stored in the xqspips_g.c file or
-* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry
-* contains configuration information for an QSPI device, including the base
-* address for the device.
-*
-* RTOS Independence
-*
-* This driver is intended to be RTOS and processor independent. It works with
-* physical addresses only. Any needs for dynamic memory management, threads or
-* thread mutual exclusion, virtual memory, or cache control must be satisfied
-* by the layer above this driver.
-*
-* NOTE: This driver was always tested with endianness set to little-endian.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
-* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
-* in xparameters.h
-* 2.00a kka 07/25/12 Added a few register defines for CR 670297
-* Removed code related to mode fault for CR 671468
-* The XQspiPs_SetSlaveSelect has been modified to remove
-* the argument of the slave select as the QSPI controller
-* only supports one slave.
-* XQspiPs_GetSlaveSelect API has been removed
-* Added a flag ShiftReadData to the instance structure
-*. and is used in the XQspiPs_GetReadData API.
-* The ShiftReadData Flag indicates whether the data
-* read from the Rx FIFO needs to be shifted
-* in cases where the data is less than 4 bytes
-* Removed the selection for the following options:
-* Master mode (XQSPIPS_MASTER_OPTION) and
-* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
-* as the QSPI driver supports the Master mode
-* and Flash Interface mode and doesnot support
-* Slave mode or the legacy mode.
-* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
-* APIs so that the last argument (IsInst) specifying whether
-* it is instruction or data has been removed. The first byte
-* in the SendBufPtr argument of these APIs specify the
-* instruction to be sent to the Flash Device.
-* This version of the driver fixes CRs 670197/663787/
-* 670297/671468.
-* Added the option for setting the Holdb_dr bit in the
-* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
-* is the option to be used for setting this bit in the
-* configuration register.
-* The XQspiPs_PolledTransfer function has been updated
-* to fill the data to fifo depth.
-* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
-* Added macros for Set/Get Rx Watermark. Changed QSPI
-* Enable/Disable macro argument from BaseAddress to
-* Instance Pointer. Added DelayNss argument to SetDelays
-* and GetDelays API's.
-* Created macros XQspiPs_IsManualStart and
-* XQspiPs_IsManualChipSelect.
-* Changed QSPI transfer logic for polled and interrupt
-* modes to be based on filled tx fifo count and receive
-* based on it. RXNEMPTY interrupt is not used.
-* Added assertions to XQspiPs_LqspiRead function.
-* SetDelays and GetDelays API's include DelayNss parameter.
-* Added defines for DelayNss,Rx Watermark,Interrupts
-* which need write to clear. Removed Read zeros mask from
-* LQSPI Config register. Renamed Fixed burst error to
-* data FSM error in LQSPI Status register.
-*
-* 2.02a hk 05/07/13 Added ConnectionMode to config structure.
-* Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
-* Added enable and disable to the XQspiPs_LqspiRead() function
-* Removed XQspi_Reset() in Set_Options() function when
-* LQSPI_MODE_OPTION is set.
-* Added instructions for bank selection, die erase and
-* flag status register to the flash instruction table
-* Handling for instructions not in flash instruction
-* table added. Checking for Tx FIFO empty when switching from
-* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
-* byte count 3 (spansion), instruction size and TXD register
-* changed accordingly. CR# 712502 and 703869.
-* Added prefix to constant definitions for ConnectionMode
-* Added (\#ifdef linear base address) in the Linear read function.
-* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to
-* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
-* XQspiPs_LqspiRead function. Fix for CR#718141.
-*
-* 2.03a hk 09/17/13 Modified polled and interrupt transfers to make use of
-* thresholds. This is to improve performance.
-* Added API's for QSPI reset and
-* linear mode initialization for boot.
-* Added RX and TX threshold reset to one in XQspiPs_Abort.
-* Added RX threshold reset(1) after transfer in polled and
-* interrupt transfers. Made changes to make sure threshold
-* change is done only when no transfer is in progress.
-* Updated linear init API for parallel and stacked modes.
-* CR#737760.
-* 3.1 hk 08/13/14 When writing to the configuration register, set/reset
-* required bits leaving reserved bits untouched. CR# 796813.
-* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
-* controller does not update FIFO status flags as expected
-* when thresholds are used.
-* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
-* to remove compilation warnings. CR# 868893.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/05/17 Modified Comment lines in functions of qspips
-* examples to recognize it as documentation block
-* and modified filename tag in
-* xqspips_dual_flash_stack_lqspi_example.c to include it in
-* doxygen examples.
-* 3.4 nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file
-* 3.5 tjs 08/21/18 Fixed compilation warnings for the ARMCC.
-* 3.5 tjs 07/16/18 Added support for low density ISSI flash parts.
-* 3.6 akm 03/28/19 Fixed memory leak issue while reading from qspi.(CR#1016357)
-* 3.6 akm 04/15/19 Modified FlashQuadEnable, FlashWrie and FlashErase APIs,
-* to wait for the on going operation to complete before
-* performing the next operation.
-* 3.6 akm 04/15/19 Modified the mask in XQspiPs_GetReadData() API to retrieve
-* configuration register values of both the Flashes in dual
-* parellel connection.
-* 3.7 akm 11/19/19 Fixed Coverity unused value warning in XQspiPs_PolledTransfer()
-* and XQspiPs_Transfer() APIs.
-* 3.7 akm 03/19/20 Modified XQspiPs_PolledTransfer(), XQspiPs_Transfer() and
-* XQspiPs_InterruptHandler() APIs to fill TX FIFO with valid
-* data when RX buffer is not NULL.
-* 3.8 akm 09/02/20 Updated the Makefile to support parallel make execution.
-*
-*
-*
-******************************************************************************/
-#ifndef XQSPIPS_H /* prevent circular inclusions */
-#define XQSPIPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xqspips_hw.h"
-#include
-
-/************************** Constant Definitions *****************************/
-
-/** @name Configuration options
- *
- * The following options are supported to enable/disable certain features of
- * an QSPI device. Each of the options is a bit mask, so more than one may be
- * specified.
- *
- *
- * The Active Low Clock option configures the device's clock polarity.
- * Setting this option means the clock is active low and the SCK signal idles
- * high. By default, the clock is active high and SCK idles low.
- *
- * The Clock Phase option configures the QSPI device for one of two
- * transfer formats. A clock phase of 0, the default, means data is valid on
- * the first SCK edge (rising or falling) after the slave select (SS) signal
- * has been asserted. A clock phase of 1 means data is valid on the second SCK
- * edge (rising or falling) after SS has been asserted.
- *
- *
- * The QSPI Force Slave Select option is used to enable manual control of
- * the slave select signal.
- * 0: The SPI_SS signal is controlled by the QSPI controller during
- * transfers. (Default)
- * 1: The SPI_SS signal is forced active (driven low) regardless of any
- * transfers in progress.
- *
- * NOTE: The driver will handle setting and clearing the Slave Select when
- * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
- * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the
- * processor cannot empty and refill the FIFOs before the TX FIFO is empty
- * When the QSPI hardware is controlling the Slave Select signals, this
- * will cause slave to be de-selected and terminate the transfer.
- *
- * The Manual Start option is used to enable manual control of
- * the Start command to perform data transfer.
- * 0: The Start command is controlled by the QSPI controller during
- * transfers(Default). Data transmission starts as soon as there is data in
- * the TXFIFO and stalls when the TXFIFO is empty
- * 1: The Start command must be issued by software to perform data transfer.
- * Bit 15 of Configuration register is used to issue Start command. This bit
- * must be set whenever TXFIFO is filled with new data.
- *
- * NOTE: The driver will set the Manual Start Enable bit in Configuration
- * Register, if Manual Start option is selected. Software will issue
- * Manual Start command whenever TXFIFO is filled with data. When there is
- * no further data, driver will clear the Manual Start Enable bit.
- *
- * @{
- */
-#define XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2 /**< Active Low Clock option */
-#define XQSPIPS_CLK_PHASE_1_OPTION 0x4 /**< Clock Phase one option */
-#define XQSPIPS_FORCE_SSELECT_OPTION 0x10 /**< Force Slave Select */
-#define XQSPIPS_MANUAL_START_OPTION 0x20 /**< Manual Start enable */
-#define XQSPIPS_LQSPI_MODE_OPTION 0x80 /**< Linear QPSI mode */
-#define XQSPIPS_HOLD_B_DRIVE_OPTION 0x100 /**< Drive HOLD_B Pin */
-/*@}*/
-
-
-/** @name QSPI Clock Prescaler options
- * The QSPI Clock Prescaler Configuration bits are used to program master mode
- * bit rate. The bit rate can be programmed in divide-by-two decrements from
- * pclk/2 to pclk/256.
- *
- * @{
- */
-#define XQSPIPS_CLK_PRESCALE_2 0x00 /**< PCLK/2 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_4 0x01 /**< PCLK/4 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_8 0x02 /**< PCLK/8 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_16 0x03 /**< PCLK/16 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_32 0x04 /**< PCLK/32 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_64 0x05 /**< PCLK/64 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_128 0x06 /**< PCLK/128 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_256 0x07 /**< PCLK/256 Prescaler */
-
-/*@}*/
-
-
-/** @name Callback events
- *
- * These constants specify the handler events that are passed to
- * a handler from the driver. These constants are not bit masks such that
- * only one will be passed at a time to the handler.
- *
- * @{
- */
-#define XQSPIPS_EVENT_TRANSFER_DONE 2 /**< Transfer done */
-#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
-#define XQSPIPS_EVENT_RECEIVE_OVERRUN 4 /**< Receive data loss because
- * RX FIFO full
- */
-/*@}*/
-
-/** @name Flash commands
- *
- * The following constants define most of the commands supported by flash
- * devices. Users can add more commands supported by the flash devices
- *
- * @{
- */
-#define XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */
-#define XQSPIPS_FLASH_OPCODE_PP 0x02 /* Page program */
-#define XQSPIPS_FLASH_OPCODE_NORM_READ 0x03 /* Normal read data bytes */
-#define XQSPIPS_FLASH_OPCODE_WRDS 0x04 /* Write disable */
-#define XQSPIPS_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */
-#define XQSPIPS_FLASH_OPCODE_WREN 0x06 /* Write enable */
-#define XQSPIPS_FLASH_OPCODE_FAST_READ 0x0B /* Fast read data bytes */
-#define XQSPIPS_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */
-#define XQSPIPS_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */
-#define XQSPIPS_FLASH_OPCODE_DUAL_READ 0x3B /* Dual read data bytes */
-#define XQSPIPS_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */
-#define XQSPIPS_FLASH_OPCODE_QUAD_READ 0x6B /* Quad read data bytes */
-#define XQSPIPS_FLASH_OPCODE_ERASE_SUS 0x75 /* Erase suspend */
-#define XQSPIPS_FLASH_OPCODE_ERASE_RES 0x7A /* Erase resume */
-#define XQSPIPS_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */
-#define XQSPIPS_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */
-#define XQSPIPS_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/
-#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */
-#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */
-#define XQSPIPS_FLASH_OPCODE_BRWR 0x17 /* Bank Register Write */
-#define XQSPIPS_FLASH_OPCODE_BRRD 0x16 /* Bank Register Read */
-/* Extende Address Register Write - Micron's equivalent of Bank Register */
-#define XQSPIPS_FLASH_OPCODE_EARWR 0xC5
-/* Extende Address Register Read - Micron's equivalent of Bank Register */
-#define XQSPIPS_FLASH_OPCODE_EARRD 0xC8
-#define XQSPIPS_FLASH_OPCODE_DIE_ERASE 0xC4
-#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR 0x70
-#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR 0x50
-#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG 0xE8 /* Lock Reg Read */
-#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG 0xE5 /* Lock Reg Write */
-
-/*@}*/
-
-/** @name Instruction size
- *
- * The following constants define numbers 1 to 4.
- * Used to identify whether TXD0,1,2 or 3 is to be used.
- *
- * @{
- */
-#define XQSPIPS_SIZE_ONE 1
-#define XQSPIPS_SIZE_TWO 2
-#define XQSPIPS_SIZE_THREE 3
-#define XQSPIPS_SIZE_FOUR 4
-
-/*@}*/
-
-/** @name ConnectionMode
- *
- * The following constants are the possible values of ConnectionMode in
- * Config structure.
- *
- * @{
- */
-#define XQSPIPS_CONNECTION_MODE_SINGLE 0
-#define XQSPIPS_CONNECTION_MODE_STACKED 1
-#define XQSPIPS_CONNECTION_MODE_PARALLEL 2
-
-/*@}*/
-
-/** @name FIFO threshold value
- *
- * This is the Rx FIFO threshold (in words) that was found to be most
- * optimal in terms of performance
- *
- * @{
- */
-#define XQSPIPS_RXFIFO_THRESHOLD_OPT 32
-
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-/**
- * The handler data type allows the user to define a callback function to
- * handle the asynchronous processing for the QSPI device. The application
- * using this driver is expected to define a handler of this type to support
- * interrupt driven mode. The handler executes in an interrupt context, so
- * only minimal processing should be performed.
- *
- * @param CallBackRef is the callback reference passed in by the upper
- * layer when setting the callback functions, and passed back to
- * the upper layer when the callback is invoked. Its type is
- * not important to the driver, so it is a void pointer.
- * @param StatusEvent holds one or more status events that have occurred.
- * See the XQspiPs_SetStatusHandler() for details on the status
- * events that can be passed in the callback.
- * @param ByteCount indicates how many bytes of data were successfully
- * transferred. This may be less than the number of bytes
- * requested if the status event indicates an error.
- */
-typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
- unsigned ByteCount);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of the device */
- u32 InputClockHz; /**< Input clock frequency */
- u8 ConnectionMode; /**< Single, Stacked and Parallel mode */
-} XQspiPs_Config;
-
-/**
- * The XQspiPs driver instance data. The user is required to allocate a
- * variable of this type for every QSPI device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XQspiPs_Config Config; /**< Configuration structure */
- u32 IsReady; /**< Device is initialized and ready */
-
- u8 *SendBufferPtr; /**< Buffer to send (state) */
- u8 *RecvBufferPtr; /**< Buffer to receive (state) */
- int RequestedBytes; /**< Number of bytes to transfer (state) */
- int RemainingBytes; /**< Number of bytes left to transfer(state) */
- u32 IsBusy; /**< A transfer is in progress (state) */
- XQspiPs_StatusHandler StatusHandler;
- void *StatusRef; /**< Callback reference for status handler */
- u32 ShiftReadData; /**< Flag to indicate whether the data
- * read from the Rx FIFO needs to be shifted
- * in cases where the data is less than 4
- * bytes
- */
-} XQspiPs;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/*
-*
-* Check in OptionsTable if Manual Start Option is enabled or disabled.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return
-* - TRUE if option is set
-* - FALSE if option is not set
-*
-* @note C-Style signature:
-* u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr);
-*
-*****************************************************************************/
-#define XQspiPs_IsManualStart(InstancePtr) \
- ((XQspiPs_GetOptions(InstancePtr) & \
- XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
-
-/****************************************************************************/
-/*
-*
-* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
-*
-* @param InstancePtr is a pointer to the XSpiPs instance.
-*
-* @return
-* - TRUE if option is set
-* - FALSE if option is not set
-*
-* @note C-Style signature:
-* u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr);
-*
-*****************************************************************************/
-#define XQspiPs_IsManualChipSelect(InstancePtr) \
- ((XQspiPs_GetOptions(InstancePtr) & \
- XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the slave idle count register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written, valid values are
-* 0-255.
-*
-* @return None
-*
-* @note C-Style signature:
-* void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr,
-* u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_SICR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_*
-* constants defined in xqspips_hw.h to interpret the bit-mask returned.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return An 8-bit value representing Slave Idle Count.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetSlaveIdle(InstancePtr) \
- XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_SICR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the transmit FIFO watermark register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written, valid values are 1-63.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr,
-* u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_TXWR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the transmit FIFO watermark register.
-* Valid values are in the range 1-63.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return A 6-bit value representing Tx Watermark level.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetTXWatermark(InstancePtr) \
- XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the receive FIFO watermark register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written, valid values are 1-63.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr,
-* u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_RXWR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the receive FIFO watermark register.
-* Valid values are in the range 1-63.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return A 6-bit value representing Rx Watermark level.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetRXWatermark(InstancePtr) \
- XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Enable the device and uninhibit master transactions.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_Enable(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_Enable(InstancePtr) \
- XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
- XQSPIPS_ER_ENABLE_MASK)
-
-/****************************************************************************/
-/**
-*
-* Disable the device.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_Disable(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_Disable(InstancePtr) \
- XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the Linear QSPI Configuration register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written to the Linear QSPI
-* configuration register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr,
-* u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the Linear QSPI Configuration register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return A 32-bit value representing the contents of the LQSPI Config
-* register.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetLqspiConfigReg(InstancePtr) \
- XQspiPs_In32((InstancePtr->Config.BaseAddress) + \
- XQSPIPS_LQSPI_CR_OFFSET)
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Initialization function, implemented in xqspips_sinit.c
- */
-XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
-
-/*
- * Functions implemented in xqspips.c
- */
-int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *Config,
- u32 EffectiveAddr);
-void XQspiPs_Reset(XQspiPs *InstancePtr);
-void XQspiPs_Abort(XQspiPs *InstancePtr);
-
-s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
- u32 ByteCount);
-s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
- u8 *RecvBufPtr, u32 ByteCount);
-int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
- u32 Address, unsigned ByteCount);
-
-int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
-
-void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
- XQspiPs_StatusHandler FuncPtr);
-void XQspiPs_InterruptHandler(void *InstancePtr);
-
-/*
- * Functions for selftest, in xqspips_selftest.c
- */
-int XQspiPs_SelfTest(XQspiPs *InstancePtr);
-
-/*
- * Functions for options, in xqspips_options.c
- */
-s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options);
-u32 XQspiPs_GetOptions(XQspiPs *InstancePtr);
-
-s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
-u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
-
-int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
- u8 DelayAfter, u8 DelayInit);
-void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
- u8 *DelayAfter, u8 *DelayInit);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ab/30a7e1535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ab/30a7e1535243001d18b399c1eb9b3628
deleted file mode 100644
index 0cdfc1e..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ab/30a7e1535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,156 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xscuwdt_hw.h
-* @addtogroup scuwdt_v2_4
-* @{
-*
-* This file contains the hardware interface to the Xilinx SCU private Watch Dog
-* Timer (XSCUWDT).
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
-* of 0x20 as the base address obtained from the tools
-* starts at 0x20.
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-#ifndef XSCUWDT_HW_H /**< prevent circular inclusions */
-#define XSCUWDT_HW_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- * Offsets of registers from the start of the device. The WDT registers start at
- * an offset 0x20
- * @{
- */
-
-#define XSCUWDT_LOAD_OFFSET 0x00U /**< Watchdog Load Register */
-#define XSCUWDT_COUNTER_OFFSET 0x04U /**< Watchdog Counter Register */
-#define XSCUWDT_CONTROL_OFFSET 0x08U /**< Watchdog Control Register */
-#define XSCUWDT_ISR_OFFSET 0x0CU /**< Watchdog Interrupt Status Register */
-#define XSCUWDT_RST_STS_OFFSET 0x10U /**< Watchdog Reset Status Register */
-#define XSCUWDT_DISABLE_OFFSET 0x14U /**< Watchdog Disable Register */
-/* @} */
-
-/** @name Watchdog Control register
- * This register bits control the prescaler, WD/Timer mode, Intr enable,
- * auto-reload, watchdog enable.
- * @{
- */
-
-#define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
-#define XSCUWDT_CONTROL_PRESCALER_SHIFT 8U
-#define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008U /**< Watchdog/Timer mode */
-#define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004U /**< Intr enable (in
- timer mode) */
-#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload (in
- timer mode) */
-#define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001U /**< Watchdog enable */
-/* @} */
-
-/** @name Interrupt Status register
- * This register indicates the Counter register has reached zero in Counter
- * mode.
- * @{
- */
-
-#define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
-/*@}*/
-
-/** @name Reset Status register
- * This register indicates the Counter register has reached zero in Watchdog
- * mode and a reset request is sent.
- * @{
- */
-
-#define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001U /**< Time out occurred */
-/*@}*/
-
-/** @name Disable register
- * This register is used to switch from watchdog mode to timer mode.
- * The software must write 0x12345678 and 0x87654321 successively to the
- * Watchdog Disable Register so that the watchdog mode bit in the Watchdog
- * Control Register is set to zero.
- * @{
- */
-#define XSCUWDT_DISABLE_VALUE1 0x12345678U /**< Watchdog mode disable
- value 1 */
-#define XSCUWDT_DISABLE_VALUE2 0x87654321U /**< Watchdog mode disable
- value 2 */
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note C-style signature:
-* u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuWdt_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + ((u32)RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ab/50b889525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ab/50b889525243001d18b399c1eb9b3628
deleted file mode 100644
index 51cc7c5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ab/50b889525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,477 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xadcps_hw.h
-* @addtogroup xadcps_v2_6
-* @{
-*
-* This header file contains identifiers and basic driver functions (or
-* macros) that can be used to access the XADC device through the Device
-* Config Interface of the Zynq.
-*
-*
-* Refer to the device specification for more information about this driver.
-*
-* @note None.
-*
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a bss 12/22/11 First release based on the XPS/AXI xadc driver
-* 1.03a bss 11/01/13 Modified macros to use correct Register offsets
-* CR#749687
-* 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors.
-*
-*
-*
-*****************************************************************************/
-#ifndef XADCPS_HW_H /* Prevent circular inclusions */
-#define XADCPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**@name Register offsets of XADC in the Device Config
- *
- * The following constants provide access to each of the registers of the
- * XADC device.
- * @{
- */
-
-#define XADCPS_CFG_OFFSET 0x00U /**< Configuration Register */
-#define XADCPS_INT_STS_OFFSET 0x04U /**< Interrupt Status Register */
-#define XADCPS_INT_MASK_OFFSET 0x08U /**< Interrupt Mask Register */
-#define XADCPS_MSTS_OFFSET 0x0CU /**< Misc status register */
-#define XADCPS_CMDFIFO_OFFSET 0x10U /**< Command FIFO Register */
-#define XADCPS_RDFIFO_OFFSET 0x14U /**< Read FIFO Register */
-#define XADCPS_MCTL_OFFSET 0x18U /**< Misc control register */
-
-/* @} */
-
-
-
-
-
-/** @name XADC Config Register Bit definitions
- * @{
- */
-#define XADCPS_CFG_ENABLE_MASK 0x80000000U /**< Enable access from PS mask */
-#define XADCPS_CFG_CFIFOTH_MASK 0x00F00000U /**< Command FIFO Threshold mask */
-#define XADCPS_CFG_DFIFOTH_MASK 0x000F0000U /**< Data FIFO Threshold mask */
-#define XADCPS_CFG_WEDGE_MASK 0x00002000U /**< Write Edge Mask */
-#define XADCPS_CFG_REDGE_MASK 0x00001000U /**< Read Edge Mask */
-#define XADCPS_CFG_TCKRATE_MASK 0x00000300U /**< Clock freq control */
-#define XADCPS_CFG_IGAP_MASK 0x0000001FU /**< Idle Gap between
- * successive commands */
-/* @} */
-
-
-/** @name XADC Interrupt Status/Mask Register Bit definitions
- *
- * The definitions are same for the Interrupt Status Register and
- * Interrupt Mask Register. They are defined only once.
- * @{
- */
-#define XADCPS_INTX_ALL_MASK 0x000003FFU /**< Alarm Signals Mask */
-#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200U /**< CMD FIFO less than threshold */
-#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100U /**< Data FIFO greater than threshold */
-#define XADCPS_INTX_OT_MASK 0x00000080U /**< Over temperature Alarm Status */
-#define XADCPS_INTX_ALM_ALL_MASK 0x0000007FU /**< Alarm Signals Mask */
-#define XADCPS_INTX_ALM6_MASK 0x00000040U /**< Alarm 6 Mask */
-#define XADCPS_INTX_ALM5_MASK 0x00000020U /**< Alarm 5 Mask */
-#define XADCPS_INTX_ALM4_MASK 0x00000010U /**< Alarm 4 Mask */
-#define XADCPS_INTX_ALM3_MASK 0x00000008U /**< Alarm 3 Mask */
-#define XADCPS_INTX_ALM2_MASK 0x00000004U /**< Alarm 2 Mask */
-#define XADCPS_INTX_ALM1_MASK 0x00000002U /**< Alarm 1 Mask */
-#define XADCPS_INTX_ALM0_MASK 0x00000001U /**< Alarm 0 Mask */
-
-/* @} */
-
-
-/** @name XADC Miscellaneous Register Bit definitions
- * @{
- */
-#define XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000U /**< Command FIFO Level mask */
-#define XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000U /**< Data FIFO Level Mask */
-#define XADCPS_MSTS_CFIFOF_MASK 0x00000800U /**< Command FIFO Full Mask */
-#define XADCPS_MSTS_CFIFOE_MASK 0x00000400U /**< Command FIFO Empty Mask */
-#define XADCPS_MSTS_DFIFOF_MASK 0x00000200U /**< Data FIFO Full Mask */
-#define XADCPS_MSTS_DFIFOE_MASK 0x00000100U /**< Data FIFO Empty Mask */
-#define XADCPS_MSTS_OT_MASK 0x00000080U /**< Over Temperature Mask */
-#define XADCPS_MSTS_ALM_MASK 0x0000007FU /**< Alarms Mask */
-/* @} */
-
-
-/** @name XADC Miscellaneous Control Register Bit definitions
- * @{
- */
-#define XADCPS_MCTL_RESET_MASK 0x00000010U /**< Reset XADC */
-#define XADCPS_MCTL_FLUSH_MASK 0x00000001U /**< Flush the FIFOs */
-/* @} */
-
-
-/**@name Internal Register offsets of the XADC
- *
- * The following constants provide access to each of the internal registers of
- * the XADC device.
- * @{
- */
-
-/*
- * XADC Internal Channel Registers
- */
-#define XADCPS_TEMP_OFFSET 0x00U /**< On-chip Temperature Reg */
-#define XADCPS_VCCINT_OFFSET 0x01U /**< On-chip VCCINT Data Reg */
-#define XADCPS_VCCAUX_OFFSET 0x02U /**< On-chip VCCAUX Data Reg */
-#define XADCPS_VPVN_OFFSET 0x03U /**< ADC out of VP/VN */
-#define XADCPS_VREFP_OFFSET 0x04U /**< On-chip VREFP Data Reg */
-#define XADCPS_VREFN_OFFSET 0x05U /**< On-chip VREFN Data Reg */
-#define XADCPS_VBRAM_OFFSET 0x06U /**< On-chip VBRAM , 7 Series */
-#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08U /**< ADC A Supply Offset Reg */
-#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09U /**< ADC A Offset Data Reg */
-#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0AU /**< ADC A Gain Error Reg */
-#define XADCPS_VCCPINT_OFFSET 0x0DU /**< On-chip VCCPINT Reg, Zynq */
-#define XADCPS_VCCPAUX_OFFSET 0x0EU /**< On-chip VCCPAUX Reg, Zynq */
-#define XADCPS_VCCPDRO_OFFSET 0x0FU /**< On-chip VCCPDRO Reg, Zynq */
-
-/*
- * XADC External Channel Registers
- */
-#define XADCPS_AUX00_OFFSET 0x10U /**< ADC out of VAUXP0/VAUXN0 */
-#define XADCPS_AUX01_OFFSET 0x11U /**< ADC out of VAUXP1/VAUXN1 */
-#define XADCPS_AUX02_OFFSET 0x12U /**< ADC out of VAUXP2/VAUXN2 */
-#define XADCPS_AUX03_OFFSET 0x13U /**< ADC out of VAUXP3/VAUXN3 */
-#define XADCPS_AUX04_OFFSET 0x14U /**< ADC out of VAUXP4/VAUXN4 */
-#define XADCPS_AUX05_OFFSET 0x15U /**< ADC out of VAUXP5/VAUXN5 */
-#define XADCPS_AUX06_OFFSET 0x16U /**< ADC out of VAUXP6/VAUXN6 */
-#define XADCPS_AUX07_OFFSET 0x17U /**< ADC out of VAUXP7/VAUXN7 */
-#define XADCPS_AUX08_OFFSET 0x18U /**< ADC out of VAUXP8/VAUXN8 */
-#define XADCPS_AUX09_OFFSET 0x19U /**< ADC out of VAUXP9/VAUXN9 */
-#define XADCPS_AUX10_OFFSET 0x1AU /**< ADC out of VAUXP10/VAUXN10 */
-#define XADCPS_AUX11_OFFSET 0x1BU /**< ADC out of VAUXP11/VAUXN11 */
-#define XADCPS_AUX12_OFFSET 0x1CU /**< ADC out of VAUXP12/VAUXN12 */
-#define XADCPS_AUX13_OFFSET 0x1DU /**< ADC out of VAUXP13/VAUXN13 */
-#define XADCPS_AUX14_OFFSET 0x1EU /**< ADC out of VAUXP14/VAUXN14 */
-#define XADCPS_AUX15_OFFSET 0x1FU /**< ADC out of VAUXP15/VAUXN15 */
-
-/*
- * XADC Registers for Maximum/Minimum data captured for the
- * on chip Temperature/VCCINT/VCCAUX data.
- */
-#define XADCPS_MAX_TEMP_OFFSET 0x20U /**< Max Temperature Reg */
-#define XADCPS_MAX_VCCINT_OFFSET 0x21U /**< Max VCCINT Register */
-#define XADCPS_MAX_VCCAUX_OFFSET 0x22U /**< Max VCCAUX Register */
-#define XADCPS_MAX_VCCBRAM_OFFSET 0x23U /**< Max BRAM Register, 7 series */
-#define XADCPS_MIN_TEMP_OFFSET 0x24U /**< Min Temperature Reg */
-#define XADCPS_MIN_VCCINT_OFFSET 0x25U /**< Min VCCINT Register */
-#define XADCPS_MIN_VCCAUX_OFFSET 0x26U /**< Min VCCAUX Register */
-#define XADCPS_MIN_VCCBRAM_OFFSET 0x27U /**< Min BRAM Register, 7 series */
-#define XADCPS_MAX_VCCPINT_OFFSET 0x28U /**< Max VCCPINT Register, Zynq */
-#define XADCPS_MAX_VCCPAUX_OFFSET 0x29U /**< Max VCCPAUX Register, Zynq */
-#define XADCPS_MAX_VCCPDRO_OFFSET 0x2AU /**< Max VCCPDRO Register, Zynq */
-#define XADCPS_MIN_VCCPINT_OFFSET 0x2CU /**< Min VCCPINT Register, Zynq */
-#define XADCPS_MIN_VCCPAUX_OFFSET 0x2DU /**< Min VCCPAUX Register, Zynq */
-#define XADCPS_MIN_VCCPDRO_OFFSET 0x2EU /**< Min VCCPDRO Register,Zynq */
- /* Undefined 0x2F to 0x3E */
-#define XADCPS_FLAG_OFFSET 0x3FU /**< Flag Register */
-
-/*
- * XADC Configuration Registers
- */
-#define XADCPS_CFR0_OFFSET 0x40U /**< Configuration Register 0 */
-#define XADCPS_CFR1_OFFSET 0x41U /**< Configuration Register 1 */
-#define XADCPS_CFR2_OFFSET 0x42U /**< Configuration Register 2 */
-
-/* Test Registers 0x43 to 0x47 */
-
-/*
- * XADC Sequence Registers
- */
-#define XADCPS_SEQ00_OFFSET 0x48U /**< Seq Reg 00 Adc Channel Selection */
-#define XADCPS_SEQ01_OFFSET 0x49U /**< Seq Reg 01 Adc Channel Selection */
-#define XADCPS_SEQ02_OFFSET 0x4AU /**< Seq Reg 02 Adc Average Enable */
-#define XADCPS_SEQ03_OFFSET 0x4BU /**< Seq Reg 03 Adc Average Enable */
-#define XADCPS_SEQ04_OFFSET 0x4CU /**< Seq Reg 04 Adc Input Mode Select */
-#define XADCPS_SEQ05_OFFSET 0x4DU /**< Seq Reg 05 Adc Input Mode Select */
-#define XADCPS_SEQ06_OFFSET 0x4EU /**< Seq Reg 06 Adc Acquisition Select */
-#define XADCPS_SEQ07_OFFSET 0x4FU /**< Seq Reg 07 Adc Acquisition Select */
-
-/*
- * XADC Alarm Threshold/Limit Registers (ATR)
- */
-#define XADCPS_ATR_TEMP_UPPER_OFFSET 0x50U /**< Temp Upper Alarm Register */
-#define XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51U /**< VCCINT Upper Alarm Reg */
-#define XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52U /**< VCCAUX Upper Alarm Reg */
-#define XADCPS_ATR_OT_UPPER_OFFSET 0x53U /**< Over Temp Upper Alarm Reg */
-#define XADCPS_ATR_TEMP_LOWER_OFFSET 0x54U /**< Temp Lower Alarm Register */
-#define XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55U /**< VCCINT Lower Alarm Reg */
-#define XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56U /**< VCCAUX Lower Alarm Reg */
-#define XADCPS_ATR_OT_LOWER_OFFSET 0x57U /**< Over Temp Lower Alarm Reg */
-#define XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58U /**< VBRAM Upper Alarm, 7 series */
-#define XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59U /**< VCCPINT Upper Alarm, Zynq */
-#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5AU /**< VCCPAUX Upper Alarm, Zynq */
-#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5BU /**< VCCPDRO Upper Alarm, Zynq */
-#define XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5CU /**< VRBAM Lower Alarm, 7 Series */
-#define XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5DU /**< VCCPINT Lower Alarm, Zynq */
-#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5EU /**< VCCPAUX Lower Alarm, Zynq */
-#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5FU /**< VCCPDRO Lower Alarm, Zynq */
-
-/* Undefined 0x60 to 0x7F */
-
-/*@}*/
-
-
-
-/**
- * @name Configuration Register 0 (CFR0) mask(s)
- * @{
- */
-#define XADCPS_CFR0_CAL_AVG_MASK 0x00008000U /**< Averaging enable Mask */
-#define XADCPS_CFR0_AVG_VALID_MASK 0x00003000U /**< Averaging bit Mask */
-#define XADCPS_CFR0_AVG1_MASK 0x00000000U /**< No Averaging */
-#define XADCPS_CFR0_AVG16_MASK 0x00001000U /**< Average 16 samples */
-#define XADCPS_CFR0_AVG64_MASK 0x00002000U /**< Average 64 samples */
-#define XADCPS_CFR0_AVG256_MASK 0x00003000U /**< Average 256 samples */
-#define XADCPS_CFR0_AVG_SHIFT 12U /**< Averaging bits shift */
-#define XADCPS_CFR0_MUX_MASK 0x00000800U /**< External Mask Enable */
-#define XADCPS_CFR0_DU_MASK 0x00000400U /**< Bipolar/Unipolar mode */
-#define XADCPS_CFR0_EC_MASK 0x00000200U /**< Event driven/
- * Continuous mode selection
- */
-#define XADCPS_CFR0_ACQ_MASK 0x00000100U /**< Add acquisition by 6 ADCCLK */
-#define XADCPS_CFR0_CHANNEL_MASK 0x0000001FU /**< Channel number bit Mask */
-
-/*@}*/
-
-/**
- * @name Configuration Register 1 (CFR1) mask(s)
- * @{
- */
-#define XADCPS_CFR1_SEQ_VALID_MASK 0x0000F000U /**< Sequence bit Mask */
-#define XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x00000000U /**< Default Safe Mode */
-#define XADCPS_CFR1_SEQ_ONEPASS_MASK 0x00001000U /**< Onepass through Seq */
-#define XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x00002000U /**< Continuous Cycling Seq */
-#define XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x00003000U /**< Single channel - No Seq */
-#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x00004000U /**< Simulataneous Sampling Mask */
-#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x00008000U /**< Independent Mode */
-#define XADCPS_CFR1_SEQ_SHIFT 12U /**< Sequence bit shift */
-#define XADCPS_CFR1_ALM_VCCPDRO_MASK 0x00000800U /**< Alm 6 - VCCPDRO, Zynq */
-#define XADCPS_CFR1_ALM_VCCPAUX_MASK 0x00000400U /**< Alm 5 - VCCPAUX, Zynq */
-#define XADCPS_CFR1_ALM_VCCPINT_MASK 0x00000200U /**< Alm 4 - VCCPINT, Zynq */
-#define XADCPS_CFR1_ALM_VBRAM_MASK 0x00000100U /**< Alm 3 - VBRAM, 7 series */
-#define XADCPS_CFR1_CAL_VALID_MASK 0x000000F0U /**< Valid Calibration Mask */
-#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x00000080U /**< Calibration 3 -Power
- Supply Gain/Offset
- Enable */
-#define XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x00000040U /**< Calibration 2 -Power
- Supply Offset Enable */
-#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x00000020U /**< Calibration 1 -ADC Gain
- Offset Enable */
-#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x00000010U /**< Calibration 0 -ADC Offset
- Enable */
-#define XADCPS_CFR1_CAL_DISABLE_MASK 0x00000000U /**< No Calibration */
-#define XADCPS_CFR1_ALM_ALL_MASK 0x00000F0FU /**< Mask for all alarms */
-#define XADCPS_CFR1_ALM_VCCAUX_MASK 0x00000008U /**< Alarm 2 - VCCAUX Enable */
-#define XADCPS_CFR1_ALM_VCCINT_MASK 0x00000004U /**< Alarm 1 - VCCINT Enable */
-#define XADCPS_CFR1_ALM_TEMP_MASK 0x00000002U /**< Alarm 0 - Temperature */
-#define XADCPS_CFR1_OT_MASK 0x00000001U /**< Over Temperature Enable */
-
-/*@}*/
-
-/**
- * @name Configuration Register 2 (CFR2) mask(s)
- * @{
- */
-#define XADCPS_CFR2_CD_VALID_MASK 0xFF00U /**
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 4.2 pkp 07/21/14 Corrected reset value of event counter in function
-* Xpm_ResetEventCounters to fix CR#796275
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xpm_counter.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-typedef const u32 PmcrEventCfg32[XPM_CTRCOUNT];
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void Xpm_DisableEventCounters(void);
-void Xpm_EnableEventCounters (void);
-void Xpm_ResetEventCounters (void);
-
-/******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @brief This function disables the Cortex A9 event counters.
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_DisableEventCounters(void)
-{
- /* Disable the event counters */
- mtcp(XREG_CP15_COUNT_ENABLE_CLR, 0x3f);
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function enables the Cortex A9 event counters.
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_EnableEventCounters(void)
-{
- /* Enable the event counters */
- mtcp(XREG_CP15_COUNT_ENABLE_SET, 0x3f);
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function resets the Cortex A9 event counters.
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_ResetEventCounters(void)
-{
- u32 Reg;
-#ifdef __GNUC__
- Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
-#else
- { register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL);
- Reg = C15Reg; }
-#endif
- Reg |= (1U << 1U); /* reset event counters */
- mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
-
-}
-
-/****************************************************************************/
-/**
-* @brief This function configures the Cortex A9 event counters controller,
-* with the event codes, in a configuration selected by the user and
-* enables the counters.
-*
-* @param PmcrCfg: Configuration value based on which the event counters
-* are configured. XPM_CNTRCFG* values defined in xpm_counter.h can
-* be utilized for setting configuration.
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_SetEvents(s32 PmcrCfg)
-{
- u32 Counter;
- static PmcrEventCfg32 PmcrEvents[] = {
- {
- XPM_EVENT_SOFTINCR,
- XPM_EVENT_INSRFETCH_CACHEREFILL,
- XPM_EVENT_INSTRFECT_TLBREFILL,
- XPM_EVENT_DATA_CACHEREFILL,
- XPM_EVENT_DATA_CACHEACCESS,
- XPM_EVENT_DATA_TLBREFILL
- },
- {
- XPM_EVENT_DATA_READS,
- XPM_EVENT_DATA_WRITE,
- XPM_EVENT_EXCEPTION,
- XPM_EVENT_EXCEPRETURN,
- XPM_EVENT_CHANGECONTEXT,
- XPM_EVENT_SW_CHANGEPC
- },
- {
- XPM_EVENT_IMMEDBRANCH,
- XPM_EVENT_UNALIGNEDACCESS,
- XPM_EVENT_BRANCHMISS,
- XPM_EVENT_CLOCKCYCLES,
- XPM_EVENT_BRANCHPREDICT,
- XPM_EVENT_JAVABYTECODE
- },
- {
- XPM_EVENT_SWJAVABYTECODE,
- XPM_EVENT_JAVABACKBRANCH,
- XPM_EVENT_COHERLINEMISS,
- XPM_EVENT_COHERLINEHIT,
- XPM_EVENT_INSTRSTALL,
- XPM_EVENT_DATASTALL
- },
- {
- XPM_EVENT_MAINTLBSTALL,
- XPM_EVENT_STREXPASS,
- XPM_EVENT_STREXFAIL,
- XPM_EVENT_DATAEVICT,
- XPM_EVENT_NODISPATCH,
- XPM_EVENT_ISSUEEMPTY
- },
- {
- XPM_EVENT_INSTRRENAME,
- XPM_EVENT_PREDICTFUNCRET,
- XPM_EVENT_MAINEXEC,
- XPM_EVENT_SECEXEC,
- XPM_EVENT_LDRSTR,
- XPM_EVENT_FLOATRENAME
- },
- {
- XPM_EVENT_NEONRENAME,
- XPM_EVENT_PLDSTALL,
- XPM_EVENT_WRITESTALL,
- XPM_EVENT_INSTRTLBSTALL,
- XPM_EVENT_DATATLBSTALL,
- XPM_EVENT_INSTR_uTLBSTALL
- },
- {
- XPM_EVENT_DATA_uTLBSTALL,
- XPM_EVENT_DMB_STALL,
- XPM_EVENT_INT_CLKEN,
- XPM_EVENT_DE_CLKEN,
- XPM_EVENT_INSTRISB,
- XPM_EVENT_INSTRDSB
- },
- {
- XPM_EVENT_INSTRDMB,
- XPM_EVENT_EXTINT,
- XPM_EVENT_PLE_LRC,
- XPM_EVENT_PLE_LRS,
- XPM_EVENT_PLE_FLUSH,
- XPM_EVENT_PLE_CMPL
- },
- {
- XPM_EVENT_PLE_OVFL,
- XPM_EVENT_PLE_PROG,
- XPM_EVENT_PLE_LRC,
- XPM_EVENT_PLE_LRS,
- XPM_EVENT_PLE_FLUSH,
- XPM_EVENT_PLE_CMPL
- },
- {
- XPM_EVENT_DATASTALL,
- XPM_EVENT_INSRFETCH_CACHEREFILL,
- XPM_EVENT_INSTRFECT_TLBREFILL,
- XPM_EVENT_DATA_CACHEREFILL,
- XPM_EVENT_DATA_CACHEACCESS,
- XPM_EVENT_DATA_TLBREFILL
- },
- };
- const u32 *ptr = PmcrEvents[PmcrCfg];
-
- Xpm_DisableEventCounters();
-
- for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
-
- /* Selecet event counter */
- mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
-
- /* Set the event */
- mtcp(XREG_CP15_EVENT_TYPE_SEL, ptr[Counter]);
- }
-
- Xpm_ResetEventCounters();
- Xpm_EnableEventCounters();
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function disables the event counters and returns the counter
-* values.
-*
-* @param PmCtrValue: Pointer to an array of type u32 PmCtrValue[6].
-* It is an output parameter which is used to return the PM
-* counter values.
-*
-* @return None.
-*
-*****************************************************************************/
-void Xpm_GetEventCounters(u32 *PmCtrValue)
-{
- u32 Counter;
-
- Xpm_DisableEventCounters();
-
- for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
-
- mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
-#ifdef __GNUC__
- PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_PERF_MONITOR_COUNT, PmCtrValue[Counter]);
-#else
- { register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT);
- PmCtrValue[Counter] = Cp15Reg; }
-#endif
- }
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ac/202f2d545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ac/202f2d545243001d18b399c1eb9b3628
deleted file mode 100644
index ee6ac60..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ac/202f2d545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,646 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xemacps_hw.h
-* @addtogroup emacps_v3_15
-* @{
-*
-* This header file contains identifiers and low-level driver functions (or
-* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
-* High-level driver functions are defined in xemacps.h.
-*
-* @note
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 First release.
-* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration.
-* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype
-* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
-* to 0x1fff. This fixes the CR#744902.
-* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
-* 3.0 kvn 12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
-* XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
-* 3.0 kpc 1/23/15 Corrected the extended descriptor macro values.
-* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.0 hk 03/18/15 Added support for jumbo frames.
-* Remove "used bit set" from TX error interrupt masks.
-* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
-* 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
-* 3.8 hk 09/17/18 Fix PTP interrupt masks.
-* 3.9 hk 01/23/19 Add RX watermark support
-* 3.10 hk 05/16/19 Clear status registers properly in reset
-*
-*
-******************************************************************************/
-
-#ifndef XEMACPS_HW_H /* prevent circular inclusions */
-#define XEMACPS_HW_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address
- supported */
-#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */
-
-#ifdef __aarch64__
-#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment
- on the local bus */
-#else
-
-#define XEMACPS_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment
- on the local bus */
-#endif
-#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using
- options that impose alignment
- restrictions on the buffer data on
- the local bus */
-
-/** @name Direction identifiers
- *
- * These are used by several functions and callbacks that need
- * to specify whether an operation specifies a send or receive channel.
- * @{
- */
-#define XEMACPS_SEND 1U /**< send direction */
-#define XEMACPS_RECV 2U /**< receive direction */
-/*@}*/
-
-/** @name MDC clock division
- * currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
- * @{
- */
-typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
- MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
-} XEmacPs_MdcDiv;
-
-/*@}*/
-
-#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
- bytes, 64, 128, ... 10240 */
-#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
-
-#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a
- unit, this is HW setup */
-
-#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */
-#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */
-
-#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
-
-/* Register offset definitions. Unless otherwise noted, register access is
- * 32 bit. Names are self explained here.
- */
-
-#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */
-#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */
-#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */
-
-#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */
-#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */
-#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */
-#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */
-#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */
-
-#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */
-#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */
-#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */
-#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */
-
-#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */
-#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */
-#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */
-
-#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */
-
-#define XEMACPS_RXWATERMARK_OFFSET 0x0000007CU /**< RX watermark reg */
-
-#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */
-#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */
-
-#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */
-#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */
-#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */
-#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */
-#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */
-#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */
-#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */
-#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */
-
-#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */
-#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */
-#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */
-#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */
-
-#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */
-
-#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low
- reg */
-#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High
- reg */
-
-#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes
- transmitted counter */
-#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast
- Frames counter*/
-#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast
- Frame counter */
-#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted
- Counter */
-#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames
- Transmitted counter */
-#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte
- Frames Transmitted
- counter */
-#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte
- Frames Transmitted
- counter*/
-#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte
- Frames transmitted
- counter */
-#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte
- Frames transmitted
- counter */
-#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte
- Frames transmitted
- counter */
-#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than
- 1519 byte Frames
- transmitted counter */
-#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error
- counter */
-
-#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame
- Counter */
-#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame
- Counter */
-#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
- Counter */
-#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame
- Counter */
-#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission
- Frame Counter */
-#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense
- Error Counter */
-
-#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register
- Low */
-#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register
- High */
-
-#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames
- Received Counter */
-#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast
- Frames Received Counter */
-#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast
- Frames Received Counter */
-#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames
- Received Counter */
-#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames
- Received Counter */
-#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte
- Frames Received Counter */
-#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte
- Frames Received Counter */
-#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte
- Frames Received Counter */
-#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte
- Frames Received Counter */
-#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte
- Frames Received Counter */
-#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte
- Frames Received Counter */
-#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received
- Counter */
-#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received
- Counter */
-#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received
- Counter */
-#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence
- Error Counter */
-#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error
- Counter */
-#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */
-#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */
-#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error
- Counter */
-#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */
-#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error
- Counter */
-#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error
- Counter */
-#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error
- Counter */
-#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter
- offset, for clearing */
-
-#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */
-#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */
-#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond
- adjustment counter */
-#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond
- increment counter */
-#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second
- counter */
-#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
- nanosecond counter */
-#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second
- counter */
-#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
- nanosecond counter */
-#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit
- second counter */
-#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
- nanosecond counter */
-#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive
- second counter */
-#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
- nanosecond counter */
-
-#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status
- reg */
-#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address
- reg */
-#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address
- reg */
-#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base
- reg */
-#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base
- reg */
-#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable
- reg */
-#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable
- reg */
-#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask
- reg */
-
-/* Define some bit positions for registers. */
-
-/** @name network control register bit definitions
- * @{
- */
-#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from
- Rx SRAM */
-#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
- pause frame */
-#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */
-#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission
- after current frame */
-#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */
-
-#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to
- stat counters */
-#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic
- registers */
-#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic
- registers */
-#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */
-#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */
-#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */
-#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */
-/*@}*/
-
-/** @name network configuration register bit definitions
- * @{
- */
-#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
- non-standard preamble */
-#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */
-#define XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U /**< SGMII Enable */
-#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of
- FCS error */
-#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */
-#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum
- offload */
-#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
- Frames to memory */
-#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */
-#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */
-#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */
-#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from
- received frames */
-#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
-/**< RX length error discard */
-#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */
-#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */
-#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
-#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
-/**< External address match enable */
-#define XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U /**< PCS Select */
-#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */
-#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte
- frames reception */
-#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
- frames */
-#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
- frames */
-#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive
- broadcast frames */
-#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */
-#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */
-#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN
- frames */
-#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */
-#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */
-#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */
-/*@}*/
-
-/** @name network status register bit definitaions
- * @{
- */
-#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */
-#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */
-/*@}*/
-
-
-/** @name MAC address register word 1 mask
- * @{
- */
-#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32]
- bit[31:0] are in BOTTOM */
-/*@}*/
-
-
-/** @name DMA control register bit definitions
- * @{
- */
-#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */
-#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */
-#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */
-#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer
- size */
-#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer
- size */
-#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX
- checksum offload */
-#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */
-#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */
-#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */
-#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */
-#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */
-#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */
-#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */
-#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */
-/*@}*/
-
-/** @name transmit status register bit definitions
- * @{
- */
-#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */
-#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */
-#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */
-#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted
- mid frame */
-#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */
-#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */
-#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */
-#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */
-
-#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
- (u32)XEMACPS_TXSR_URUN_MASK | \
- (u32)XEMACPS_TXSR_BUFEXH_MASK | \
- (u32)XEMACPS_TXSR_RXOVR_MASK | \
- (u32)XEMACPS_TXSR_FRAMERX_MASK | \
- (u32)XEMACPS_TXSR_USEDREAD_MASK)
-/*@}*/
-
-/**
- * @name receive status register bit definitions
- * @{
- */
-#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */
-#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */
-#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */
-#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */
-
-#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
- (u32)XEMACPS_RXSR_RXOVR_MASK | \
- (u32)XEMACPS_RXSR_BUFFNA_MASK)
-
-#define XEMACPS_SR_ALL_MASK 0xFFFFFFFFU /**< Mask for full register */
-
-/*@}*/
-
-/**
- * @name Interrupt Q1 status register bit definitions
- * @{
- */
-#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */
-#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */
-
-#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
- (u32)XEMACPS_INTQ1SR_TXERR_MASK)
-
-/*@}*/
-
-/**
- * @name interrupts bit definitions
- * Bits definitions are same in XEMACPS_ISR_OFFSET,
- * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
- * @{
- */
-#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Pdelay_resp TXed */
-#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req TXed */
-#define XEMACPS_IXR_PTPPSRX_MASK 0x00800000U /**< PTP Pdelay_resp RXed */
-#define XEMACPS_IXR_PTPPDRRX_MASK 0x00400000U /**< PTP Pdelay_req RXed */
-
-#define XEMACPS_IXR_PTPSTX_MASK 0x00200000U /**< PTP Sync TXed */
-#define XEMACPS_IXR_PTPDRTX_MASK 0x00100000U /**< PTP Delay_req TXed */
-#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync RXed */
-#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req RXed */
-
-#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */
-#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached
- zero */
-#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
-#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */
-#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */
-#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */
-#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or
- no buffers*/
-#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */
-#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */
-#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */
-#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */
-#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */
-#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */
-#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */
-
-#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \
- (u32)XEMACPS_IXR_RETRY_MASK | \
- (u32)XEMACPS_IXR_URUN_MASK)
-
-
-#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \
- (u32)XEMACPS_IXR_RXUSED_MASK | \
- (u32)XEMACPS_IXR_RXOVR_MASK)
-
-/*@}*/
-
-/** @name PHY Maintenance bit definitions
- * @{
- */
-#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */
-#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */
-#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */
-#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */
-#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */
-#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */
-#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */
-#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */
-/*@}*/
-
-/** @name RX watermark bit definitions
- * @{
- */
-#define XEMACPS_RXWM_HIGH_MASK 0x0000FFFFU /**< RXWM high mask */
-#define XEMACPS_RXWM_LOW_MASK 0xFFFF0000U /**< RXWM low mask */
-#define XEMACPS_RXWM_LOW_SHFT_MSK 16U /**< Shift for RXWM low */
-/*@}*/
-
-/* Transmit buffer descriptor status words offset
- * @{
- */
-#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */
-#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */
-#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */
-
-/*
- * @}
- */
-
-/* Transmit buffer descriptor status words bit positions.
- * Transmit buffer descriptor consists of two 32-bit registers,
- * the first - word0 contains a 32-bit address pointing to the location of
- * the transmit data.
- * The following register - word1, consists of various information to control
- * the XEmacPs transmit process. After transmit, this is updated with status
- * information, whether the frame was transmitted OK or why it had failed.
- * @{
- */
-#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */
-#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */
-#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
-#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */
-#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */
-#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */
-#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
-#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */
-#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */
-/*
- * @}
- */
-
-/* Receive buffer descriptor status words bit positions.
- * Receive buffer descriptor consists of two 32-bit registers,
- * the first - word0 contains a 32-bit word aligned address pointing to the
- * address of the buffer. The lower two bits make up the wrap bit indicating
- * the last descriptor and the ownership bit to indicate it has been used by
- * the XEmacPs.
- * The following register - word1, contains status information regarding why
- * the frame was received (the filter match condition) as well as other
- * useful info.
- * @{
- */
-#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */
-#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
-#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */
-#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */
-#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address
- matched */
-#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */
-#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */
-#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */
-#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */
-#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */
-#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */
-#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */
-#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */
-#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */
-#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
-
-#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */
-#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */
-#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */
-/*
- * @}
- */
-
-/*
- * Define appropriate I/O access method to memory mapped I/O or other
- * interface if necessary.
- */
-
-#define XEmacPs_In32 Xil_In32
-#define XEmacPs_Out32 Xil_Out32
-
-
-/****************************************************************************/
-/**
-*
-* Read the given register.
-*
-* @param BaseAddress is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
- XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
-
-
-/****************************************************************************/
-/**
-*
-* Write the given register.
-*
-* @param BaseAddress is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
-* u32 Data)
-*
-*****************************************************************************/
-#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
- XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
-
-/************************** Function Prototypes *****************************/
-/*
- * Perform reset operation to the emacps interface
- */
-void XEmacPs_ResetHw(u32 BaseAddr);
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ac/80a576525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ac/80a576525243001d18b399c1eb9b3628
deleted file mode 100644
index b80c577..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ac/80a576525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,281 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#ifndef PROFILE_TIMER_HW_H
-#define PROFILE_TIMER_HW_H
-
-#include "profile.h"
-
-#ifdef PROC_PPC
-#if defined __GNUC__
-# define SYNCHRONIZE_IO __asm__ volatile ("eieio")
-#elif defined __DCC__
-# define SYNCHRONIZE_IO __asm volatile(" eieio")
-#else
-# define SYNCHRONIZE_IO
-#endif
-#endif
-
-#ifdef PROC_PPC
-#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
-#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
-#else
-#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
-#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
-#endif
-
-#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
- ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \
- (u32)(RegOffset)), (u32)(ValueToWrite))
-
-#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
- ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
-
-#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
- ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (RegisterValue))
-
-#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \
- ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
-
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef PROC_PPC
-#include "xexception_l.h"
-#include "xtime_l.h"
-#include "xpseudo_asm.h"
-#endif
-
-#ifdef TIMER_CONNECT_INTC
-#include "xintc_l.h"
-#include "xintc.h"
-#endif /* TIMER_CONNECT_INTC */
-
-#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
-#include "xtmrctr_l.h"
-#endif
-
-#ifdef PROC_CORTEXA9
-#include "xscutimer_hw.h"
-#include "xscugic.h"
-#endif
-
-extern u32 timer_clk_ticks ;
-
-/*--------------------------------------------------------------------
- * PowerPC Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_PPC
-
-#ifdef PPC_PIT_INTERRUPT
-u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */
-#endif
-
-#ifdef PROC_PPC440
-#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
-#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
-#define XREG_SPR_PIT XREG_SPR_DEC
-#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
-#endif
-
-/* --------------------------------------------------------------------
- * Disable the Timer - During Profiling
- *
- * For PIT Timer -
- * 1. XTime_PITDisableInterrupt() ;
- * 2. Store the remaining timer clk tick
- * 3. Stop the PIT Timer
- *-------------------------------------------------------------------- */
-
-#ifdef PPC_PIT_INTERRUPT
-#define disable_timer() \
- { \
- u32 val; \
- val=mfspr(XREG_SPR_TCR); \
- mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \
- timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
- mtspr(XREG_SPR_PIT, 0); \
- }
-#else
-#define disable_timer() \
- { \
- u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(addr); \
- tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
- ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
- }
-#endif
-
-
-
-/* --------------------------------------------------------------------
- * Enable the Timer
- *
- * For PIT Timer -
- * 1. Load the remaining timer clk ticks
- * 2. XTime_PITEnableInterrupt() ;
- *-------------------------------------------------------------------- */
-#ifdef PPC_PIT_INTERRUPT
-#define enable_timer() \
- { \
- u32 val; \
- val=mfspr(XREG_SPR_TCR); \
- mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
- mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
- }
-#else
-#define enable_timer() \
- { \
- u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(addr); \
- tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
- ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
- }
-#endif
-
-
-
-/* --------------------------------------------------------------------
- * Send Ack to Timer Interrupt
- *
- * For PIT Timer -
- * 1. Load the timer clk ticks
- * 2. Enable AutoReload and Interrupt
- * 3. Clear PIT Timer Status bits
- *-------------------------------------------------------------------- */
-#ifdef PPC_PIT_INTERRUPT
-#define timer_ack() \
- { \
- u32 val; \
- mtspr(XREG_SPR_PIT, timer_clk_ticks); \
- mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
- val=mfspr(XREG_SPR_TCR); \
- mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
- }
-#else
-#define timer_ack() \
- { \
- u32 csr; \
- csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
- ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
- }
-#endif
-
-/*-------------------------------------------------------------------- */
-#endif /* PROC_PPC */
-/* -------------------------------------------------------------------- */
-
-
-
-
-/* --------------------------------------------------------------------
- * MicroBlaze Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_MICROBLAZE
-
-/* --------------------------------------------------------------------
- * Disable the Timer during Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define disable_timer() \
- { \
- u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
- Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
- Addr += (u32)XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(Addr); \
- tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
- u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
- OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
- OutAddr += (u32)XTC_TCSR_OFFSET; \
- ProfIo_Out32(OutAddr, (u32)tmp_v); \
- }
-
-
-/* --------------------------------------------------------------------
- * Enable the Timer after Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define enable_timer() \
- { \
- u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
- Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
- Addr += (u32)XTC_TCSR_OFFSET; \
- u32 tmp_v = (u32)ProfIo_In32(Addr); \
- tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \
- ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
- }
-
-
-/* --------------------------------------------------------------------
- * Send Ack to Timer Interrupt
- *
- *-------------------------------------------------------------------- */
-#define timer_ack() \
- { \
- u32 csr; \
- csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \
- ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \
- }
-
-/*-------------------------------------------------------------------- */
-#endif /* PROC_MICROBLAZE */
-/*-------------------------------------------------------------------- */
-
-/* --------------------------------------------------------------------
- * Cortex A9 Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_CORTEXA9
-
-/* --------------------------------------------------------------------
- * Disable the Timer during Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define disable_timer() \
-{ \
- u32 Reg; \
- Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
- Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
- Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
-}
-
-
-/* --------------------------------------------------------------------
- * Enable the Timer after Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define enable_timer() \
-{ \
- u32 Reg; \
- Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
- Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
- Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
-}
-
-
-/* --------------------------------------------------------------------
- * Send Ack to Timer Interrupt
- *
- *-------------------------------------------------------------------- */
-#define timer_ack() \
-{ \
- Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
- (u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
-}
-
-/*-------------------------------------------------------------------- */
-#endif /* PROC_CORTEXA9 */
-/*-------------------------------------------------------------------- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ac/80ed40595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ac/80ed40595243001d18b399c1eb9b3628
deleted file mode 100644
index 5a1bda3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ac/80ed40595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,76 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_testio.h
-*
-* @addtogroup common_test_utils Test Utilities for Memory and Caches
-*
I/O test
-* The xil_testio.h file contains utility functions to test endian related memory
-* IO functions.
-*
-* A subset of the memory tests can be selected or all of the tests can be run
-* in order. If there is an error detected by a subtest, the test stops and the
-* failure code is returned. Further tests are not run even if all of the tests
-* are selected.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00 hbm 08/05/09 First release
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_TESTIO_H /* prevent circular inclusions */
-#define XIL_TESTIO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-
-#define XIL_TESTIO_DEFAULT 0
-#define XIL_TESTIO_LE 1
-#define XIL_TESTIO_BE 2
-
-/**
- *@endcond
- */
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
-extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
-extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_test_utils".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ac/a0c354595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ac/a0c354595243001d18b399c1eb9b3628
deleted file mode 100644
index 47ddf9b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ac/a0c354595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,712 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
- * Microblaze HW Exception Handler
- * - Non self-modifying exception handler for the following exception conditions
- * - Unalignment
- * - Instruction bus error
- * - Data bus error
- * - Illegal instruction opcode
- * - Divide-by-zero
- * - Stack protection violation
- *******************************************************************************/
-
-#include "microblaze_exceptions_g.h"
-#include "xparameters.h"
-#include "microblaze_instructions.h"
-
-/* 64-bit definitions */
-#if defined (__arch64__)
-#define INTPTR_DATAITEM .quad
-#define REGSIZE 8
-#define DATAALIGN 4
-#else
-#define INTPTR_DATAITEM .long
-#define REGSIZE 4
-#define DATAALIGN 2
-#endif /* 64-bit definitions */
-
-/* Helpful Macros */
-#define EX_HANDLER_STACK_SIZ (REGSIZE*21)
-#define RMSR_OFFSET (20 * REGSIZE)
-#define R17_OFFSET (0)
-#define REG_OFFSET(regnum) (REGSIZE * (regnum + 1))
-#define NUM_TO_REG(num) r ## num
-
-#define R3_TO_STACK(regnum) SI r3, r1, REG_OFFSET(regnum)
-#define R3_FROM_STACK(regnum) LI r3, r1, REG_OFFSET(regnum)
-
-#define PUSH_REG(regnum) SI NUM_TO_REG(regnum), r1, REG_OFFSET(regnum)
-#define POP_REG(regnum) LI NUM_TO_REG(regnum), r1, REG_OFFSET(regnum)
-
-/* Uses r5 */
-#define PUSH_MSR \
- mfs r5, rmsr; \
- swi r5, r1, RMSR_OFFSET;
-
-#define PUSH_MSR_AND_ENABLE_EXC \
- mfs r5, rmsr; \
- swi r5, r1, RMSR_OFFSET; \
- ori r5, r5, 0x100; /* Turn ON the EE bit*/ \
- mts rmsr, r5;
-
-/* Uses r5 */
-#define POP_MSR \
- lwi r5, r1, RMSR_OFFSET; \
- mts rmsr, r5;
-
-/* Push r17 */
-#define PUSH_R17 SI r17, r1, R17_OFFSET
-/* Pop r17 */
-#define POP_R17 LI r17, r1, R17_OFFSET
-
-#define LWREG_NOP \
- BRI ex_handler_unhandled; \
- nop;
-
-#define SWREG_NOP \
- BRI ex_handler_unhandled; \
- nop;
-
-/* r3 is the source */
-#define R3_TO_LWREG_V(regnum) \
- R3_TO_STACK (regnum); \
- BRI ex_handler_done;
-
-/* r3 is the source */
-#define R3_TO_LWREG(regnum) \
- OR NUM_TO_REG (regnum), r0, r3; \
- BRI ex_handler_done;
-
-/* r3 is the target */
-#define SWREG_TO_R3_V(regnum) \
- R3_FROM_STACK (regnum); \
- BRI ex_sw_tail;
-
-/* r3 is the target */
-#define SWREG_TO_R3(regnum) \
- OR r3, r0, NUM_TO_REG (regnum); \
- BRI ex_sw_tail;
-
-/* regnum is the source */
-#define FP_EX_OPB_SAVE(regnum) \
- SI NUM_TO_REG (regnum), r0, mb_fpex_op_b; \
- nop; \
- BRI handle_fp_ex_opa;
-
-/* regnum is the source */
-#define FP_EX_OPB_SAVE_V(regnum) \
- R3_FROM_STACK (regnum); \
- SI r3, r0, mb_fpex_op_b; \
- BRI handle_fp_ex_opa;
-
-/* regnum is the source */
-#define FP_EX_OPA_SAVE(regnum) \
- SI NUM_TO_REG (regnum), r0, mb_fpex_op_a; \
- nop; \
- BRI handle_fp_ex_done;
-
-/* regnum is the source */
-#define FP_EX_OPA_SAVE_V(regnum) \
- R3_FROM_STACK (regnum); \
- SI r3, r0, mb_fpex_op_a; \
- BRI handle_fp_ex_done;
-
-#define FP_EX_UNHANDLED \
- BRI fp_ex_unhandled; \
- nop; \
- nop;
-
-/* ESR masks */
-#define ESR_EXC_MASK 0x0000001F
-#define ESR_REG_MASK 0x000003E0
-#define ESR_LW_SW_MASK 0x00000400
-#define ESR_WORD_MASK 0x00000800
-#define ESR_DS_MASK 0x00001000
-#define ESR_LONG_MASK 0x00002000
-
-/* Extern declarations */
-.extern XNullHandler
-
-
-#ifdef MICROBLAZE_EXCEPTIONS_ENABLED /* If exceptions are enabled in the processor */
-
-/*
- * hw_exception_handler - Handler for unaligned exceptions
- * Exception handler notes:
- * - Does not handle exceptions other than unaligned exceptions
- * - Does not handle exceptions during load into r17, r1, r0.
- * - Does not handle exceptions during store from r17 (cannot be done) and r1 (slows down common case)
- *
- * Relevant register structures
- *
- * EAR - |----|----|----|----|----|----|----|----|
- * - < ## 32 or 64 bit faulting address ## >
- *
- * ESR - |----|----|----|----|----| - | - |-----|-----|
- * - W S REG EXC
- *
- *
- * STACK FRAME STRUCTURE
- * ---------------------
- *
- * +-------------+ + 0
- * | r17 |
- * +-------------+ + 4 (32-bit) + 8 (64-bit)
- * | Args for |
- * | next func |
- * +-------------+ + 8 (32-bit) + 16 (64-bit)
- * | r1 |
- * | . |
- * | . |
- * | . |
- * | . |
- * | r18 |
- * +-------------+ + 80 (32-bit) + 160 (64-bit)
- * | MSR |
- * +-------------+ + 84 (32-bit) + 168 (64-bit)
- * | . |
- * | . |
- */
-
-
-.global _hw_exception_handler
-.section .text
-.align 2
-.ent _hw_exception_handler
-.type _hw_exception_handler, @function
-_hw_exception_handler:
-
-#if defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1)
- /* Immediately halt for stack protection violation exception without using any stack */
- SI r3, r0, mb_sp_save_r3; /* Save temporary register */
- mfs r3, resr; /* Extract ESR[DS] */
- andi r3, r3, ESR_EXC_MASK;
- xori r3, r3, 0x7; /* Check for stack protection violation */
- BNEI r3, ex_handler_not_sp_violation;
-ex_handler_sp_violation:
- bri 0; /* Halt here if stack protection violation */
-ex_handler_not_sp_violation:
- LI r3, r0, mb_sp_save_r3; /* Restore temporary register */
-#endif /* defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1) */
-
- ADDIK r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */
- PUSH_REG(3);
- PUSH_REG(4);
- PUSH_REG(5);
- PUSH_REG(6);
-#ifdef MICROBLAZE_CAN_HANDLE_EXCEPTIONS_IN_DELAY_SLOTS
- mfs r6, resr;
- andi r6, r6, ESR_DS_MASK;
- BEQI r6, ex_handler_no_ds;
- mfs r17, rbtr;
-ex_handler_no_ds:
-#endif
- PUSH_R17;
- PUSH_MSR_AND_ENABLE_EXC; /* Exceptions enabled here. This will allow nested exceptions */
-
- mfs r3, resr;
- andi r5, r3, ESR_EXC_MASK; /* Extract ESR[EXC] */
-#ifndef NO_UNALIGNED_EXCEPTIONS
- xori r6, r5, 1; /* 00001 = Unaligned Exception */
- BNEI r6, handle_ex_regular;
-
- ADDIK r4, r0, MB_ExceptionVectorTable; /* Check if user has registered an unaligned exception handler */
-#if defined (__arch64__)
- LI r4, r4, 16;
-#else
- LI r4, r4, 8;
-#endif
- ADDIK r6, r0, XNullHandler; /* If exceptionvectortable entry is still XNullHandler, use */
- XOR r6, r4, r6; /* the default exception handler */
- BEQI r6, handle_unaligned_ex ;
-
-handle_ex_regular:
-#endif /* ! NO_UNALIGNED_EXCEPTIONS */
-
-#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE)
- xori r6, r5, 6; /* 00110 = FPU exception */
- BEQI r6, handle_fp_ex; /* Go and decode the FP exception */
-#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
-
-handle_other_ex: /* Handle Other exceptions here */
- ori r6, r0, 20;
- cmp r6, r5, r6; /* >= 20 are exceptions we do not handle. */
- BLEI r6, ex_handler_unhandled;
-
- ori r6, r0, 7;
- cmp r6, r5, r6; /* Convert MMU exception indices into an ordinal of 7 */
- BGTI r6, handle_other_ex_tail;
- ori r5, r0, 0x7;
-
-handle_other_ex_tail:
- PUSH_REG(7); /* Save other volatiles before we make procedure calls below */
- PUSH_REG(8);
- PUSH_REG(9);
- PUSH_REG(10);
- PUSH_REG(11);
- PUSH_REG(12);
- PUSH_REG(15);
- PUSH_REG(18);
-
- ADDIK r4, r0, MB_ExceptionVectorTable; /* Load the Exception vector table base address */
- ADDK r7, r5, r5; /* Calculate exception vector offset = r5 * 8 (32-bit) */
- ADDK r7, r7, r7;
- ADDK r7, r7, r7;
-#if defined (__arch64__)
- ADDK r7, r7, r7; /* or r5 * 16 (64-bit) */
-#endif
- ADDK r7, r7, r4; /* Get pointer to exception vector */
- LI r5, r7, REGSIZE; /* Load argument to exception handler from table */
- LOAD r7, r7, r0; /* Load vector itself here */
-
- brald r15, r7; /* Branch to handler */
- nop;
-
- POP_REG(7); /* Restore other volatiles */
- POP_REG(8);
- POP_REG(9);
- POP_REG(10);
- POP_REG(11);
- POP_REG(12);
- POP_REG(15);
- POP_REG(18);
-
- BRI ex_handler_done; /* Complete exception handling */
-
-#ifndef NO_UNALIGNED_EXCEPTIONS
-handle_unaligned_ex:
- andi r6, r3, ESR_REG_MASK; /* Mask and extract the register operand */
- srl r6, r6; /* r6 >> 5 */
- srl r6, r6;
- srl r6, r6;
- srl r6, r6;
- srl r6, r6;
- sbi r6, r0, ex_reg_op; /* Store the register operand in a temporary location */
- mfs r4, rear;
- andi r6, r3, ESR_LW_SW_MASK; /* Extract ESR[S] */
- BNEI r6, ex_sw;
-#if defined (__arch64__)
-ex_ll:
- andi r6, r3, ESR_LONG_MASK; /* Extract ESR[L] */
- BEQI r6, ex_lw;
- lbui r5, r4, 0; /* Exception address in r4 */
- sbi r5, r0, ex_tmp_data_loc_0; /* Load a long, byte-by-byte from destination address and save it in tmp space */
- lbui r5, r4, 1;
- sbi r5, r0, ex_tmp_data_loc_1;
- lbui r5, r4, 2;
- sbi r5, r0, ex_tmp_data_loc_2;
- lbui r5, r4, 3;
- sbi r5, r0, ex_tmp_data_loc_3;
- lbui r5, r4, 4;
- sbi r5, r0, ex_tmp_data_loc_4;
- lbui r5, r4, 5;
- sbi r5, r0, ex_tmp_data_loc_5;
- lbui r5, r4, 6;
- sbi r5, r0, ex_tmp_data_loc_6;
- lbui r5, r4, 7;
- sbi r5, r0, ex_tmp_data_loc_7;
- lli r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */
- BRI ex_lw_tail;
-#endif
-ex_lw:
- andi r6, r3, ESR_WORD_MASK; /* Extract ESR[W] */
- BEQI r6, ex_lhw;
- lbui r5, r4, 0; /* Exception address in r4 */
- sbi r5, r0, ex_tmp_data_loc_0; /* Load a word, byte-by-byte from destination address and save it in tmp space */
- lbui r5, r4, 1;
- sbi r5, r0, ex_tmp_data_loc_1;
- lbui r5, r4, 2;
- sbi r5, r0, ex_tmp_data_loc_2;
- lbui r5, r4, 3;
- sbi r5, r0, ex_tmp_data_loc_3;
- lwi r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */
- BRI ex_lw_tail;
-ex_lhw:
- lbui r5, r4, 0; /* Exception address in r4 */
- sbi r5, r0, ex_tmp_data_loc_0; /* Load a half-word, byte-by-byte from destination address and save it in tmp space */
- lbui r5, r4, 1;
- sbi r5, r0, ex_tmp_data_loc_1;
- lhui r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */
-ex_lw_tail:
- lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */
- ADDIK r6, r0, lw_table; /* Form load_word jump table offset (lw_table + (8 * regnum)) */
- ADDK r5, r5, r5;
- ADDK r5, r5, r5;
- ADDK r5, r5, r5;
- ADDK r5, r5, r6;
- bra r5;
-ex_lw_end: /* Exception handling of load word, ends */
-ex_sw:
- lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */
- ADDIK r6, r0, sw_table; /* Form store_word jump table offset (sw_table + (8 * regnum)) */
- ADDK r5, r5, r5;
- ADDK r5, r5, r5;
- ADDK r5, r5, r5;
- ADDK r5, r5, r6;
- bra r5;
-ex_sw_tail:
-#if defined (__arch64__)
-ex_sl:
- mfs r6, resr;
- andi r6, r6, ESR_LONG_MASK; /* Extract ESR[L] */
- BEQI r6, ex_not_sl;
- sli r3, r0, ex_tmp_data_loc_0;
- lbui r3, r0, ex_tmp_data_loc_0; /* Store the long, byte-by-byte into destination address */
- sbi r3, r4, 0;
- lbui r3, r0, ex_tmp_data_loc_1;
- sbi r3, r4, 1;
- lbui r3, r0, ex_tmp_data_loc_2;
- sbi r3, r4, 2;
- lbui r3, r0, ex_tmp_data_loc_3;
- sbi r3, r4, 3;
- lbui r3, r0, ex_tmp_data_loc_4;
- sbi r3, r4, 4;
- lbui r3, r0, ex_tmp_data_loc_5;
- sbi r3, r4, 5;
- lbui r3, r0, ex_tmp_data_loc_6;
- sbi r3, r4, 6;
- lbui r3, r0, ex_tmp_data_loc_7;
- sbi r3, r4, 7;
- BRI ex_handler_done;
-ex_not_sl:
-#endif
- mfs r6, resr;
- andi r6, r6, ESR_WORD_MASK; /* Extract ESR[W] */
- BEQI r6, ex_shw;
- swi r3, r0, ex_tmp_data_loc_0;
- lbui r3, r0, ex_tmp_data_loc_0; /* Store the word, byte-by-byte into destination address */
- sbi r3, r4, 0;
- lbui r3, r0, ex_tmp_data_loc_1;
- sbi r3, r4, 1;
- lbui r3, r0, ex_tmp_data_loc_2;
- sbi r3, r4, 2;
- lbui r3, r0, ex_tmp_data_loc_3;
- sbi r3, r4, 3;
- BRI ex_handler_done;
-ex_shw:
- swi r3, r0, ex_tmp_data_loc_0; /* Store the lower half-word, byte-by-byte into destination address */
-
-#ifdef __LITTLE_ENDIAN__
- lbui r3, r0, ex_tmp_data_loc_0;
-#else
- lbui r3, r0, ex_tmp_data_loc_2;
-#endif
- sbi r3, r4, 0;
-#ifdef __LITTLE_ENDIAN__
- lbui r3, r0, ex_tmp_data_loc_1;
-#else
- lbui r3, r0, ex_tmp_data_loc_3;
-#endif
- sbi r3, r4, 1;
-ex_sw_end: /* Exception handling of store word, ends. */
- BRI ex_handler_done;
-#endif /* !NO_UNALIGNED_EXCEPTIONS */
-
-#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE)
-handle_fp_ex:
- ADDIK r3, r17, -4; /* r17 contains (addr of exception causing FP instruction + 4) */
- lw r4, r0, r3; /* We might find ourselves in a spot here. Unguaranteed load */
-
-handle_fp_ex_opb:
- ADDIK r6, r0, fp_table_opb; /* Decode opB and store its value in mb_fpex_op_b */
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- andi r3, r4, 0x1F;
- ADDK r3, r3, r3; /* Calculate (fp_table_opb + (regno * 12)) in r5 */
- ADDK r3, r3, r3;
- ADDK r5, r3, r3;
- ADDK r5, r5, r3;
- ADDK r5, r5, r6;
- bra r5;
-
-handle_fp_ex_opa:
- ADDIK r6, r0, fp_table_opa; /* Decode opA and store its value in mb_fpex_op_a */
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- andi r3, r4, 0x1F;
- ADDK r3, r3, r3; /* Calculate (fp_table_opb + (regno * 12)) in r5 */
- ADDK r3, r3, r3;
- ADDK r5, r3, r3;
- ADDK r5, r5, r3;
- ADDK r5, r5, r6;
- bra r5;
-
-handle_fp_ex_done:
- ori r5, r0, 6; /* Set exception number back to 6 */
- BRI handle_other_ex_tail;
-
-fp_ex_unhandled:
- bri 0;
-#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
-
-ex_handler_done:
- POP_R17;
- POP_MSR;
- POP_REG(3);
- POP_REG(4);
- POP_REG(5);
- POP_REG(6);
-
- ADDIK r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */
- rted r17, 0
- nop
-
-ex_handler_unhandled:
- bri 0 /* UNHANDLED. TRAP HERE */
-.end _hw_exception_handler
-
-#ifndef NO_UNALIGNED_EXCEPTIONS
-
-/*
- * hw_exception_handler Jump Table
- * - Contains code snippets for each register that caused the unaligned exception.
- * - Hence exception handler is NOT self-modifying
- * - Separate table for load exceptions and store exceptions.
- * - Each table is of size: (8 * 32) = 256 bytes
- */
-
-.section .text
-.align 4
-lw_table:
-lw_r0: R3_TO_LWREG (0);
-lw_r1: LWREG_NOP;
-lw_r2: R3_TO_LWREG (2);
-lw_r3: R3_TO_LWREG_V (3);
-lw_r4: R3_TO_LWREG_V (4);
-lw_r5: R3_TO_LWREG_V (5);
-lw_r6: R3_TO_LWREG_V (6);
-lw_r7: R3_TO_LWREG (7);
-lw_r8: R3_TO_LWREG (8);
-lw_r9: R3_TO_LWREG (9);
-lw_r10: R3_TO_LWREG (10);
-lw_r11: R3_TO_LWREG (11);
-lw_r12: R3_TO_LWREG (12);
-lw_r13: R3_TO_LWREG (13);
-lw_r14: R3_TO_LWREG (14);
-lw_r15: R3_TO_LWREG (15);
-lw_r16: R3_TO_LWREG (16);
-lw_r17: LWREG_NOP;
-lw_r18: R3_TO_LWREG (18);
-lw_r19: R3_TO_LWREG (19);
-lw_r20: R3_TO_LWREG (20);
-lw_r21: R3_TO_LWREG (21);
-lw_r22: R3_TO_LWREG (22);
-lw_r23: R3_TO_LWREG (23);
-lw_r24: R3_TO_LWREG (24);
-lw_r25: R3_TO_LWREG (25);
-lw_r26: R3_TO_LWREG (26);
-lw_r27: R3_TO_LWREG (27);
-lw_r28: R3_TO_LWREG (28);
-lw_r29: R3_TO_LWREG (29);
-lw_r30: R3_TO_LWREG (30);
-lw_r31: R3_TO_LWREG (31);
-
-sw_table:
-sw_r0: SWREG_TO_R3 (0);
-sw_r1: SWREG_NOP;
-sw_r2: SWREG_TO_R3 (2);
-sw_r3: SWREG_TO_R3_V (3);
-sw_r4: SWREG_TO_R3_V (4);
-sw_r5: SWREG_TO_R3_V (5);
-sw_r6: SWREG_TO_R3_V (6);
-sw_r7: SWREG_TO_R3 (7);
-sw_r8: SWREG_TO_R3 (8);
-sw_r9: SWREG_TO_R3 (9);
-sw_r10: SWREG_TO_R3 (10);
-sw_r11: SWREG_TO_R3 (11);
-sw_r12: SWREG_TO_R3 (12);
-sw_r13: SWREG_TO_R3 (13);
-sw_r14: SWREG_TO_R3 (14);
-sw_r15: SWREG_TO_R3 (15);
-sw_r16: SWREG_TO_R3 (16);
-sw_r17: SWREG_NOP;
-sw_r18: SWREG_TO_R3 (18);
-sw_r19: SWREG_TO_R3 (19);
-sw_r20: SWREG_TO_R3 (20);
-sw_r21: SWREG_TO_R3 (21);
-sw_r22: SWREG_TO_R3 (22);
-sw_r23: SWREG_TO_R3 (23);
-sw_r24: SWREG_TO_R3 (24);
-sw_r25: SWREG_TO_R3 (25);
-sw_r26: SWREG_TO_R3 (26);
-sw_r27: SWREG_TO_R3 (27);
-sw_r28: SWREG_TO_R3 (28);
-sw_r29: SWREG_TO_R3 (29);
-sw_r30: SWREG_TO_R3 (30);
-sw_r31: SWREG_TO_R3 (31);
-
-/* Temporary data structures used in the handler */
-.section .data
-.align DATAALIGN
-ex_tmp_data_loc_0:
- .byte 0
-ex_tmp_data_loc_1:
- .byte 0
-ex_tmp_data_loc_2:
- .byte 0
-ex_tmp_data_loc_3:
- .byte 0
-#if defined (__arch64__)
-ex_tmp_data_loc_4:
- .byte 0
-ex_tmp_data_loc_5:
- .byte 0
-ex_tmp_data_loc_6:
- .byte 0
-ex_tmp_data_loc_7:
- .byte 0
-#endif
-ex_reg_op:
- .byte 0
-
-#endif /* ! NO_UNALIGNED_EXCEPTIONS */
-
-#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE)
-/*
- * FP exception decode jump table.
- * - Contains code snippets for each register that could have been a source operand for an excepting FP instruction
- * - Hence exception handler is NOT self-modifying
- * - Separate table for opA and opB
- * - Each table is of size: (12 * 32) = 384 bytes
- */
-
-.section .text
-.align 4
-fp_table_opa:
-opa_r0: FP_EX_OPA_SAVE (0);
-opa_r1: FP_EX_UNHANDLED;
-opa_r2: FP_EX_OPA_SAVE (2);
-opa_r3: FP_EX_OPA_SAVE_V (3);
-opa_r4: FP_EX_OPA_SAVE_V (4);
-opa_r5: FP_EX_OPA_SAVE_V (5);
-opa_r6: FP_EX_OPA_SAVE_V (6);
-opa_r7: FP_EX_OPA_SAVE (7);
-opa_r8: FP_EX_OPA_SAVE (8);
-opa_r9: FP_EX_OPA_SAVE (9);
-opa_r10: FP_EX_OPA_SAVE (10);
-opa_r11: FP_EX_OPA_SAVE (11);
-opa_r12: FP_EX_OPA_SAVE (12);
-opa_r13: FP_EX_OPA_SAVE (13);
-opa_r14: FP_EX_UNHANDLED;
-opa_r15: FP_EX_UNHANDLED;
-opa_r16: FP_EX_UNHANDLED;
-opa_r17: FP_EX_UNHANDLED;
-opa_r18: FP_EX_OPA_SAVE (18);
-opa_r19: FP_EX_OPA_SAVE (19);
-opa_r20: FP_EX_OPA_SAVE (20);
-opa_r21: FP_EX_OPA_SAVE (21);
-opa_r22: FP_EX_OPA_SAVE (22);
-opa_r23: FP_EX_OPA_SAVE (23);
-opa_r24: FP_EX_OPA_SAVE (24);
-opa_r25: FP_EX_OPA_SAVE (25);
-opa_r26: FP_EX_OPA_SAVE (26);
-opa_r27: FP_EX_OPA_SAVE (27);
-opa_r28: FP_EX_OPA_SAVE (28);
-opa_r29: FP_EX_OPA_SAVE (29);
-opa_r30: FP_EX_OPA_SAVE (30);
-opa_r31: FP_EX_OPA_SAVE (31);
-
-fp_table_opb:
-opb_r0: FP_EX_OPB_SAVE (0);
-opb_r1: FP_EX_UNHANDLED;
-opb_r2: FP_EX_OPB_SAVE (2);
-opb_r3: FP_EX_OPB_SAVE_V (3);
-opb_r4: FP_EX_OPB_SAVE_V (4);
-opb_r5: FP_EX_OPB_SAVE_V (5);
-opb_r6: FP_EX_OPB_SAVE_V (6);
-opb_r7: FP_EX_OPB_SAVE (7);
-opb_r8: FP_EX_OPB_SAVE (8);
-opb_r9: FP_EX_OPB_SAVE (9);
-opb_r10: FP_EX_OPB_SAVE (10);
-opb_r11: FP_EX_OPB_SAVE (11);
-opb_r12: FP_EX_OPB_SAVE (12);
-opb_r13: FP_EX_OPB_SAVE (13);
-opb_r14: FP_EX_UNHANDLED;
-opb_r15: FP_EX_UNHANDLED;
-opb_r16: FP_EX_UNHANDLED;
-opb_r17: FP_EX_UNHANDLED;
-opb_r18: FP_EX_OPB_SAVE (18);
-opb_r19: FP_EX_OPB_SAVE (19);
-opb_r20: FP_EX_OPB_SAVE (20);
-opb_r21: FP_EX_OPB_SAVE (21);
-opb_r22: FP_EX_OPB_SAVE (22);
-opb_r23: FP_EX_OPB_SAVE (23);
-opb_r24: FP_EX_OPB_SAVE (24);
-opb_r25: FP_EX_OPB_SAVE (25);
-opb_r26: FP_EX_OPB_SAVE (26);
-opb_r27: FP_EX_OPB_SAVE (27);
-opb_r28: FP_EX_OPB_SAVE (28);
-opb_r29: FP_EX_OPB_SAVE (29);
-opb_r30: FP_EX_OPB_SAVE (30);
-opb_r31: FP_EX_OPB_SAVE (31);
-
-#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
-
-#if defined(MICROBLAZE_FP_EXCEPTION_ENABLED) && defined(MICROBLAZE_FP_EXCEPTION_DECODE)
-/* This is where we store the opA and opB of the last excepting FP instruction */
-.section .data
-.align DATAALIGN
-.global mb_fpex_op_a
-.global mb_fpex_op_b
-mb_fpex_op_a:
- INTPTR_DATAITEM 0
-mb_fpex_op_b:
- INTPTR_DATAITEM 0
-#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
-
-#if defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1)
-/* This is where we store the register used to check which exception occurred */
- .section .data
- .align DATAALIGN
-mb_sp_save_r3:
- INTPTR_DATAITEM 0
-#endif /* defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1) */
-
-/* The exception vector table */
-.section .data
-.align DATAALIGN
-.global MB_ExceptionVectorTable
-MB_ExceptionVectorTable:
- INTPTR_DATAITEM XNullHandler
- INTPTR_DATAITEM 0 /* -- FSL Exception -- */
- INTPTR_DATAITEM XNullHandler
- INTPTR_DATAITEM 1 /* -- Unaligned Access Exception -- */
- INTPTR_DATAITEM XNullHandler
- INTPTR_DATAITEM 2 /* -- Illegal Opcode Exception -- */
- INTPTR_DATAITEM XNullHandler
- INTPTR_DATAITEM 3 /* -- Instruction Bus Exception -- */
- INTPTR_DATAITEM XNullHandler
- INTPTR_DATAITEM 4 /* -- Data Bus Exception -- */
- INTPTR_DATAITEM XNullHandler
- INTPTR_DATAITEM 5 /* -- Div-by-0 Exception -- */
- INTPTR_DATAITEM XNullHandler
- INTPTR_DATAITEM 6 /* -- FPU Exception -- */
- INTPTR_DATAITEM XNullHandler
- INTPTR_DATAITEM 7 /* -- MMU Exceptions -- */
-
-#else /* Dummy exception handler, in case exceptions are not present in the processor */
-
-.global _hw_exception_handler
-.section .text
-.align 2
-.ent _hw_exception_handler
-_hw_exception_handler:
- bri 0;
-.end _hw_exception_handler
-
-#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ac/b05f8c575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ac/b05f8c575243001d18b399c1eb9b3628
deleted file mode 100644
index 379023c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ac/b05f8c575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,154 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xl2cc.h
-*
-* This file contains the address definitions for the PL310 Level-2 Cache
-* Controller.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 02/01/10 Initial version
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef _XL2CC_H_
-#define _XL2CC_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-/* L2CC Register Offsets */
-#define XPS_L2CC_ID_OFFSET 0x0000U
-#define XPS_L2CC_TYPE_OFFSET 0x0004U
-#define XPS_L2CC_CNTRL_OFFSET 0x0100U
-#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104U
-#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108U
-#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010CU
-
-#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200U
-#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204U
-#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208U
-#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020CU
-#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210U
-
-#define XPS_L2CC_IER_OFFSET 0x0214U /* Interrupt Mask */
-#define XPS_L2CC_IPR_OFFSET 0x0218U /* Masked interrupt status */
-#define XPS_L2CC_ISR_OFFSET 0x021CU /* Raw Interrupt Status */
-#define XPS_L2CC_IAR_OFFSET 0x0220U /* Interrupt Clear */
-
-#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730U /* Cache Sync */
-#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740U /* Dummy Register for Cache Sync */
-#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770U /* Cache Invalid by PA */
-#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077CU /* Cache Invalid by Way */
-#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0U /* Cache Clean by PA */
-#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8U /* Cache Clean by Index */
-#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BCU /* Cache Clean by Way */
-#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0U /* Cache Invalidate and Clean by PA */
-#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8U /* Cache Invalidate and Clean by Index */
-#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FCU /* Cache Invalidate and Clean by Way */
-
-#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900U /* Cache Data Lockdown 0 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904U /* Cache Instruction Lockdown 0 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908U /* Cache Data Lockdown 1 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090CU /* Cache Instruction Lockdown 1 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910U /* Cache Data Lockdown 2 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914U /* Cache Instruction Lockdown 2 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918U /* Cache Data Lockdown 3 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091CU /* Cache Instruction Lockdown 3 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920U /* Cache Data Lockdown 4 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924U /* Cache Instruction Lockdown 4 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928U /* Cache Data Lockdown 5 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092CU /* Cache Instruction Lockdown 5 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930U /* Cache Data Lockdown 6 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934U /* Cache Instruction Lockdown 6 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938U /* Cache Data Lockdown 7 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093CU /* Cache Instruction Lockdown 7 by Way */
-
-#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U /* Cache Lockdown Line Enable */
-#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954U /* Cache Unlock All Lines by Way */
-
-#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00U /* Start of address filtering */
-#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04U /* Start of address filtering */
-
-#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40U /* Debug Control Register */
-
-/* XPS_L2CC_CNTRL_OFFSET bit masks */
-#define XPS_L2CC_ENABLE_MASK 0x00000001U /* enables the L2CC */
-
-/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */
-#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000U /* Early BRESP Enable */
-#define XPS_L2CC_AUX_IPFE_MASK 0x20000000U /* Instruction Prefetch Enable */
-#define XPS_L2CC_AUX_DPFE_MASK 0x10000000U /* Data Prefetch Enable */
-#define XPS_L2CC_AUX_NSIC_MASK 0x08000000U /* Non-secure interrupt access control */
-#define XPS_L2CC_AUX_NSLE_MASK 0x04000000U /* Non-secure lockdown enable */
-#define XPS_L2CC_AUX_CRP_MASK 0x02000000U /* Cache replacement policy */
-#define XPS_L2CC_AUX_FWE_MASK 0x01800000U /* Force write allocate */
-#define XPS_L2CC_AUX_SAOE_MASK 0x00400000U /* Shared attribute override enable */
-#define XPS_L2CC_AUX_PE_MASK 0x00200000U /* Parity enable */
-#define XPS_L2CC_AUX_EMBE_MASK 0x00100000U /* Event monitor bus enable */
-#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000U /* Way-size */
-#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000U /* Associativity */
-#define XPS_L2CC_AUX_SAIE_MASK 0x00002000U /* Shared attribute invalidate enable */
-#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000U /* Exclusive cache configuration */
-#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800U /* Store buffer device limitation Enable */
-#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400U /* High Priority for SO and Dev Reads Enable */
-#define XPS_L2CC_AUX_FLZE_MASK 0x00000001U /* Full line of zero enable */
-
-#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000U /* Enable all prefetching, */
- /* Cache replacement policy, Parity enable, */
- /* Event monitor bus enable and Way Size (64 KB) */
-#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFFU /* */
-
-#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111U /* latency for TAG RAM */
-#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121U /* latency for DATA RAM */
-
-/* Interrupt bit masks */
-#define XPS_L2CC_IXR_DECERR_MASK 0x00000100U /* DECERR from L3 */
-#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080U /* SLVERR from L3 */
-#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040U /* Error on L2 data RAM (Read) */
-#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020U /* Error on L2 tag RAM (Read) */
-#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010U /* Error on L2 data RAM (Write) */
-#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008U /* Error on L2 tag RAM (Write) */
-#define XPS_L2CC_IXR_PARRD_MASK 0x00000004U /* Parity Error on L2 data RAM (Read) */
-#define XPS_L2CC_IXR_PARRT_MASK 0x00000002U /* Parity Error on L2 tag RAM (Read) */
-#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001U /* Event Counter1/0 Overflow Increment */
-
-/* Address filtering mask and enable bit */
-#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000U /* Address filtering valid bits*/
-#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U /* Address filtering enable bit*/
-
-/* Debug control bits */
-#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004U /* Debug SPIDEN bit */
-#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002U /* Debug DWB bit, forces write through */
-#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002U /* Debug DCL bit, disables cache line fill */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* protection macro */
-
-/**
- *@endcond
- */
\ No newline at end of file
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ac/d03602595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ac/d03602595243001d18b399c1eb9b3628
deleted file mode 100644
index 2d0c539..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ac/d03602595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,292 +0,0 @@
-;/******************************************************************************
-;* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-;* SPDX-License-Identifier: MIT
-;******************************************************************************/
-;/*****************************************************************************/
-;/**
-;* @file boot.S
-;*
-;* @addtogroup r5_boot_code Cortex R5 Processor Boot Code
-;* @{
-;*
boot.S
-;* The boot code performs minimum configuration which is required for an
-;* application to run starting from processor's reset state. Below is a
-;* sequence illustrating what all configuration is performed before control
-;* reaches to main function.
-;*
-;* 1. Program vector table base for exception handling
-;* 2. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine,
-;* abort, system)
-;* 3. Disable instruction cache, data cache and MPU
-;* 4. Invalidate instruction and data cache
-;* 5. Configure MPU with short descriptor translation table format and program
-;* base address of translation table
-;* 6. Enable data cache, instruction cache and MPU
-;* 7. Enable Floating point unit
-;* 8. Transfer control to _start which clears BSS sections and jumping to main
-;* application
-;*
-;*
-;*
-;* MODIFICATION HISTORY:
-;*
-;* Ver Who Date Changes
-;* ----- ---- -------- ---------------------------------------------------
-;* 7.3 dp 06/25/20 Initial version for armclang
-;*
-;*
-;******************************************************************************/
-#include "xparameters.h"
-
- EXPORT _prestart
- EXPORT _boot
- IMPORT |Image$$ARM_LIB_STACK$$Base|
- IMPORT |Image$$ARM_IRQ_STACK$$Base|
- IMPORT |Image$$ARM_SV_STACK$$Base|
- IMPORT |Image$$ARM_ABORT_STACK$$Base|
- IMPORT |Image$$ARM_FIQ_STACK$$Base|
- IMPORT |Image$$ARM_UNDEF_STACK$$Base|
- IMPORT Init_MPU
- IMPORT _startup
-
-RPU_GLBL_CNTL EQU 0xFF9A0000
-RPU_ERR_INJ EQU 0xFF9A0020
-RPU_0_CFG EQU 0xFF9A0100
-RPU_1_CFG EQU 0xFF9A0200
-#if defined(versal)
-RST_LPD_DBG EQU 0xFF5E0338
-BOOT_MODE_USER EQU 0xF1260200
-#else
-RST_LPD_DBG EQU 0xFF5E0240
-BOOT_MODE_USER EQU 0xFF5E0200
-#endif
-fault_log_enable EQU 0x101
-
-;0th bit of PROCESSOR_ACCESS_VALUE macro signifies trustzone
-;setting for RPU address space
-
-#define RPU_TZ_MASK 0x1
-
- AREA |.boot|, CODE
- REQUIRE8 {TRUE}
- PRESERVE8 {TRUE}
- ENTRY
-;this initializes the various processor modes
-
-_prestart
-_boot
-
-OKToRun
-
-;Initialize processor registers to 0
- mov r0,#0
- mov r1,#0
- mov r2,#0
- mov r3,#0
- mov r4,#0
- mov r5,#0
- mov r6,#0
- mov r7,#0
- mov r8,#0
- mov r9,#0
- mov r10,#0
- mov r11,#0
- mov r12,#0
-
-;Initialize stack pointer and banked registers for various mode
- mrs r0, cpsr ;get the current PSR
- mvn r1, #0x1f ;set up the irq stack pointer
- and r2, r1, r0
- orr r2, r2, #0x12 ;IRQ mode
- msr cpsr_cxsf, r2
- ldr r13,=|Image$$ARM_IRQ_STACK$$Base| ;IRQ stack pointer
- mov r14,#0
-
- mrs r0, cpsr ;get the current PSR
- mvn r1, #0x1f ;set up the supervisor stack pointer
- and r2, r1, r0
- orr r2, r2, #0x13 ;supervisor mode
- msr cpsr_cxsf, r2
- ldr r13,=|Image$$ARM_SV_STACK$$Base| ;Supervisor stack pointer
- mov r14,#0
-
- mrs r0, cpsr ;get the current PSR
- mvn r1, #0x1f ;set up the Abort stack pointer
- and r2, r1, r0
- orr r2, r2, #0x17 ;Abort mode
- msr cpsr_cxsf, r2
- ldr r13,=|Image$$ARM_ABORT_STACK$$Base| ;Abort stack pointer
- mov r14,#0
-
- mrs r0, cpsr ;get the current PSR
- mvn r1, #0x1f ;set up the FIQ stack pointer
- and r2, r1, r0
- orr r2, r2, #0x11 ;FIQ mode
- msr cpsr_cxsf, r2
- mov r8, #0
- mov r9, #0
- mov r10, #0
- mov r11, #0
- mov r12, #0
- ldr r13,=|Image$$ARM_FIQ_STACK$$Base| ;FIQ stack pointer
- mov r14,#0
-
- mrs r0, cpsr ;get the current PSR
- mvn r1, #0x1f ;set up the Undefine stack pointer
- and r2, r1, r0
- orr r2, r2, #0x1b ;Undefine mode
- msr cpsr_cxsf, r2
- ldr r13,=|Image$$ARM_UNDEF_STACK$$Base| ;Undefine stack pointer
- mov r14,#0
-
- mrs r0, cpsr ;get the current PSR
- mvn r1, #0x1f ;set up the system stack pointer
- and r2, r1, r0
- orr r2, r2, #0x1F ;SYS mode
- msr cpsr_cxsf, r2
- ldr r13,=|Image$$ARM_LIB_STACK$$Base| ;SYS stack pointer
- mov r14,#0
-
-;Enable access to VFP by enabling access to Coprocessors 10 and 11.
-;Enables Full Access i.e. in both privileged and non privileged modes
- mrc p15, 0, r0, c1, c0, 2 ;Read Coprocessor Access Control Register (CPACR)
- orr r0, r0, #(0xF << 20) ;Enable access to CP 10 & 11
- mcr p15, 0, r0, c1, c0, 2 ;Write Coprocessor Access Control Register (CPACR)
- isb
-
-;enable fpu access
- vmrs r3, FPEXC
- orr r1, r3, #(1<<30)
- vmsr FPEXC, r1
-
-;clear the floating point register
- mov r1,#0
- vmov d0,r1,r1
- vmov d1,r1,r1
- vmov d2,r1,r1
- vmov d3,r1,r1
- vmov d4,r1,r1
- vmov d5,r1,r1
- vmov d6,r1,r1
- vmov d7,r1,r1
- vmov d8,r1,r1
- vmov d9,r1,r1
- vmov d10,r1,r1
- vmov d11,r1,r1
- vmov d12,r1,r1
- vmov d13,r1,r1
- vmov d14,r1,r1
- vmov d15,r1,r1
-
-#ifdef __SOFTFP__
-;Disable the FPU if SOFTFP is defined
- vmsr FPEXC,r3
-#endif
-
-;Disable MPU and caches
- mrc p15, 0, r0, c1, c0, 0 ;Read CP15 Control Register
- bic r0, r0, #0x05 ;Disable MPU (M bit) and data cache (C bit)
- bic r0, r0, #0x1000 ;Disable instruction cache (I bit)
- dsb ;Ensure all previous loads/stores have completed
- mcr p15, 0, r0, c1, c0, 0 ;Write CP15 Control Register
- isb ;Ensure subsequent insts execute wrt new MPU settings
-
-;Disable Branch prediction, TCM ECC checks
- mrc p15, 0, r0, c1, c0, 1 ;Read ACTLR
- orr r0, r0, #(0x1 << 17) ;Enable RSDIS bit 17 to disable the return stack
- orr r0, r0, #(0x1 << 16) ;Clear BP bit 15 and set BP bit 16:
- bic r0, r0, #(0x1 << 15) ;Branch always not taken and history table updates disabled
- orr r0, r0, #(0x1 << 27) ;Enable B1TCM ECC check
- orr r0, r0, #(0x1 << 26) ;Enable B0TCM ECC check
- orr r0, r0, #(0x1 << 25) ;Enable ATCM ECC check
- bic r0, r0, #(0x1 << 5) ;Generate abort on parity errors, with [5:3]=b 000
- bic r0, r0, #(0x1 << 4)
- bic r0, r0, #(0x1 << 3)
- mcr p15, 0, r0, c1, c0, 1 ;Write ACTLR
- dsb ;Complete all outstanding explicit memory operations
-
-;Invalidate caches
- mov r0,#0 ;r0 = 0
- dsb
- mcr p15, 0, r0, c7, c5, 0 ;invalidate icache
- mcr p15, 0, r0, c15, c5, 0 ;Invalidate entire data cache
- isb
-#if LOCKSTEP_MODE_DEBUG == 0 && (PROCESSOR_ACCESS_VALUE & RPU_TZ_MASK)
-;enable fault log for lock step
- ldr r0,=RPU_GLBL_CNTL
- ldr r1, [r0]
- ands r1, r1, #0x8
-;branch to initialization if split mode
- bne init
-;check for boot mode if in lock step, branch to init if JTAG boot mode
- ldr r0,=BOOT_MODE_USER
- ldr r1, [r0]
- ands r1, r1, #0xF
- beq init
-;reset the debug logic
- ldr r0,=RST_LPD_DBG
- ldr r1, [r0]
- orr r1, r1, #(0x1 << 4)
- orr r1, r1, #(0x1 << 5)
- str r1, [r0]
-;enable fault log
- ldr r0,=RPU_ERR_INJ
- ldr r1,=fault_log_enable
- ldr r2, [r0]
- orr r2, r2, r1
- str r2, [r0]
- nop
- nop
-#endif
-
-init
- bl Init_MPU;Initialize MPU
-
-;Enable Branch prediction
- mrc p15, 0, r0, c1, c0, 1 ;Read ACTLR
- bic r0, r0, #(0x1 << 17) ;Clear RSDIS bit 17 to enable return stack
- bic r0, r0, #(0x1 << 16) ;Clear BP bit 15 and BP bit 16:
- bic r0, r0, #(0x1 << 15) ;Normal operation, BP is taken from the global history table.
- orr r0, r0, #(0x1 << 14) ;Disable DBWR for errata 780125
- mcr p15, 0, r0, c1, c0, 1 ;Write ACTLR
-
-;Enable icahce and dcache
- mrc p15,0,r1,c1,c0,0
- ldr r0, =0x1005
- orr r1,r1,r0
- dsb
- mcr p15,0,r1,c1,c0,0 ;Enable cache
- isb ;isb flush prefetch buffer
-
-;Set vector table in TCM/LOVEC
-#ifndef VEC_TABLE_IN_OCM
- mrc p15, 0, r0, c1, c0, 0
- mvn r1, #0x2000
- and r0, r0, r1
- mcr p15, 0, r0, c1, c0, 0
-
-;Check if processor is having access to RPU address space
-#if (PROCESSOR_ACCESS_VALUE & RPU_TZ_MASK)
-;Clear VINITHI to enable LOVEC on reset
-#if XPAR_CPU_ID == 0
- ldr r0, =RPU_0_CFG
-#else
- ldr r0, =RPU_1_CFG
-#endif
- ldr r1, [r0]
- bic r1, r1, #(0x1 << 2)
- str r1, [r0]
-#endif
-#endif
-;enable asynchronous abort exception
- mrs r0, cpsr
- bic r0, r0, #0x100
- msr cpsr_xsf, r0
-
- bl _startup
-
-Ldone
- b Ldone ;Paranoia: we should never get here
-
- END
-;@} End of "addtogroup r5_boot_code".
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ac/e0b4af595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ac/e0b4af595243001d18b399c1eb9b3628
deleted file mode 100644
index 5007212..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ac/e0b4af595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,111 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2017 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_sleeptimer.h
-*
-* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs.
-* For sleep related functions that can be used across all Xilinx supported
-* processors, please use xil_sleeptimer.h.
-*
-*
-*
-* MODIFICATION HISTORY :
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 6.6 srm 10/18/17 First Release.
-* 7.0 mus 01/07/19 Add cpp extern macro
-*
-*
-*****************************************************************************/
-
-/**
- *@cond nocomments
- */
-#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */
-#define XIL_SLEEPTIMER_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**************************** Include Files ********************************/
-
-#include "xil_io.h"
-#include "xparameters.h"
-#include "bspconfig.h"
-
-/************************** Constant Definitions *****************************/
-
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
-#define XSLEEP_TIMER_REG_SHIFT 32U
-#define XSleep_ReadCounterVal Xil_In32
-#define XCntrVal u32
-#else
-#define XSLEEP_TIMER_REG_SHIFT 16U
-#define XSleep_ReadCounterVal Xil_In16
-#define XCntrVal u16
-#endif
-
-#if defined(ARMR5) || (defined (__aarch64__) && EL3==1) || defined (ARMA53_32)
-#if defined (versal)
-#define CRL_TTC_RST 0xFF5E0344U
-#define CRL_TTC_BASE_RST_MASK 0x1U
-#else
-#define RST_LPD_IOU2 0xFF5E0238U
-#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U
-#endif
-#endif
-
-#if defined (SLEEP_TIMER_BASEADDR)
-/** @name Register Map
-*
-* Register offsets from the base address of the TTC device
-*
-* @{
-*/
- #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U
- /**< Clock Control Register */
- #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU
- /**< Counter Control Register*/
- #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U
- /**< Current Counter Value */
-/* @} */
-/** @name Clock Control Register
-* Clock Control Register definitions of TTC
-* @{
-*/
- #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U
- /**< Prescale enable */
-/* @} */
-/** @name Counter Control Register
-* Counter Control Register definitions of TTC
-* @{
-*/
-#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U
- /**< Disable the counter */
-#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U
- /**< Reset counter */
-/* @} */
-
-/**************************** Type Definitions *******************************/
-/**
- *@endcond
- */
-/************************** Function Prototypes ******************************/
-
-void Xil_SleepTTCCommon(u32 delay, u64 frequency);
-void XTime_StartTTCTimer();
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_SLEEPTIMER_H */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ad/04024e585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ad/04024e585243001d18b399c1eb9b3628
deleted file mode 100644
index a22ecf5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ad/04024e585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,324 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xparameters_ps.h
-*
-* This file contains the address definitions for the hard peripherals
-* attached to the ARM Cortex A53 core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 6.0 mus 18/08/16 Defined ARMA53_32 flag
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#ifndef _XPARAMETERS_PS_H_
-#define _XPARAMETERS_PS_H_
-
-#ifndef ARMA53_32
-#define ARMA53_32 ARMA53_32
-#endif
-
-/**
- *@cond nocomments
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/***************************** Include Files *********************************/
-
-
-/************************** Constant Definitions *****************************/
-
-/*
- * This block contains constant declarations for the peripherals
- * within the hardblock
- */
-
-/* Canonical definitions for DDR MEMORY */
-#define XPAR_DDR_MEM_BASEADDR 0x00000000U
-#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
-
-/* Canonical definitions for Interrupts */
-#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
-#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
-#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
-#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
-#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
-#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
-#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
-#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
-#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
-#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
-#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
-#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
-#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
-#define XPAR_XEMACPS_2_INTR XPS_GEM2_INT_ID
-#define XPAR_XEMACPS_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID
-#define XPAR_XEMACPS_3_INTR XPS_GEM3_INT_ID
-#define XPAR_XEMACPS_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
-#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
-#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
-#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
-#define XPAR_XWDTPS_0_INTR XPS_LPD_SWDT_INT_ID
-#define XPAR_XWDTPS_1_INTR XPS_FPD_SWDT_INT_ID
-#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
-#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
-#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
-#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
-#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
-#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
-#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
-#define XPAR_XTTCPS_6_INTR XPS_TTC2_0_INT_ID
-#define XPAR_XTTCPS_7_INTR XPS_TTC2_1_INT_ID
-#define XPAR_XTTCPS_8_INTR XPS_TTC2_2_INT_ID
-#define XPAR_XTTCPS_9_INTR XPS_TTC3_0_INT_ID
-#define XPAR_XTTCPS_10_INTR XPS_TTC3_1_INT_ID
-#define XPAR_XTTCPS_11_INTR XPS_TTC3_2_INT_ID
-#define XPAR_XNANDPS8_0_INTR XPS_NAND_INT_ID
-#define XPAR_XADMAPS_0_INTR XPS_ADMA_CH0_INT_ID
-#define XPAR_XADMAPS_1_INTR XPS_ADMA_CH1_INT_ID
-#define XPAR_XADMAPS_2_INTR XPS_ADMA_CH2_INT_ID
-#define XPAR_XADMAPS_3_INTR XPS_ADMA_CH3_INT_ID
-#define XPAR_XADMAPS_4_INTR XPS_ADMA_CH4_INT_ID
-#define XPAR_XADMAPS_5_INTR XPS_ADMA_CH5_INT_ID
-#define XPAR_XADMAPS_6_INTR XPS_ADMA_CH6_INT_ID
-#define XPAR_XADMAPS_7_INTR XPS_ADMA_CH7_INT_ID
-#define XPAR_XCSUDMA_INTR XPS_CSU_DMA_INT_ID
-#define XPAR_PSU_ADMA_0_INTR XPS_ADMA_CH0_INT_ID
-#define XPAR_PSU_ADMA_1_INTR XPS_ADMA_CH1_INT_ID
-#define XPAR_PSU_ADMA_2_INTR XPS_ADMA_CH2_INT_ID
-#define XPAR_PSU_ADMA_3_INTR XPS_ADMA_CH3_INT_ID
-#define XPAR_PSU_ADMA_4_INTR XPS_ADMA_CH4_INT_ID
-#define XPAR_PSU_ADMA_5_INTR XPS_ADMA_CH5_INT_ID
-#define XPAR_PSU_ADMA_6_INTR XPS_ADMA_CH6_INT_ID
-#define XPAR_PSU_ADMA_7_INTR XPS_ADMA_CH7_INT_ID
-#define XPAR_PSU_CSUDMA_INTR XPS_CSU_DMA_INT_ID
-#define XPAR_XMPU_LPD_INTR XPS_XMPU_LPD_INT_ID
-#define XPAR_XZDMAPS_0_INTR XPS_ZDMA_CH0_INT_ID
-#define XPAR_XZDMAPS_1_INTR XPS_ZDMA_CH1_INT_ID
-#define XPAR_XZDMAPS_2_INTR XPS_ZDMA_CH2_INT_ID
-#define XPAR_XZDMAPS_3_INTR XPS_ZDMA_CH3_INT_ID
-#define XPAR_XZDMAPS_4_INTR XPS_ZDMA_CH4_INT_ID
-#define XPAR_XZDMAPS_5_INTR XPS_ZDMA_CH5_INT_ID
-#define XPAR_XZDMAPS_6_INTR XPS_ZDMA_CH6_INT_ID
-#define XPAR_XZDMAPS_7_INTR XPS_ZDMA_CH7_INT_ID
-#define XPAR_PSU_GDMA_0_INTR XPS_ZDMA_CH0_INT_ID
-#define XPAR_PSU_GDMA_1_INTR XPS_ZDMA_CH1_INT_ID
-#define XPAR_PSU_GDMA_2_INTR XPS_ZDMA_CH2_INT_ID
-#define XPAR_PSU_GDMA_3_INTR XPS_ZDMA_CH3_INT_ID
-#define XPAR_PSU_GDMA_4_INTR XPS_ZDMA_CH4_INT_ID
-#define XPAR_PSU_GDMA_5_INTR XPS_ZDMA_CH5_INT_ID
-#define XPAR_PSU_GDMA_6_INTR XPS_ZDMA_CH6_INT_ID
-#define XPAR_PSU_GDMA_7_INTR XPS_ZDMA_CH7_INT_ID
-#define XPAR_XMPU_FPD_INTR XPS_XMPU_FPD_INT_ID
-#define XPAR_XCCI_FPD_INTR XPS_FPD_CCI_INT_ID
-#define XPAR_XSMMU_FPD_INTR XPS_FPD_SMMU_INT_ID
-#define XPAR_XUSBPS_0_INTR XPS_USB3_0_ENDPT_INT_ID
-#define XPAR_XUSBPS_1_INTR XPS_USB3_1_ENDPT_INT_ID
-#define XPAR_XRTCPSU_ALARM_INTR XPS_RTC_ALARM_INT_ID
-#define XPAR_XRTCPSU_SECONDS_INTR XPS_RTC_SEC_INT_ID
-#define XPAR_XAPMPS_0_INTR XPS_APM0_INT_ID
-#define XPAR_XAPMPS_1_INTR XPS_APM1_INT_ID
-#define XPAR_XAPMPS_2_INTR XPS_APM2_INT_ID
-#define XPAR_XAPMPS_5_INTR XPS_APM5_INT_ID
-#define XPAR_XSYSMONPSU_INTR XPS_AMS_INT_ID
-
-/* Canonical definitions for SCU GIC */
-#define XPAR_SCUGIC_NUM_INSTANCES 1U
-#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
-#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
-#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00002000U)
-#define XPAR_SCUGIC_ACK_BEFORE 0U
-
-#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
-
-
-/*
- * This block contains constant declarations for the peripherals
- * within the hardblock. These have been put for backwards compatibility
- */
-
-
-#define XPS_SYS_CTRL_BASEADDR 0xFF180000U
-#define XPS_SCU_PERIPH_BASE 0xF9000000U
-
-
-
-/* Shared Peripheral Interrupts (SPI) */
-#define XPS_FPGA0_INT_ID 121U
-#define XPS_FPGA1_INT_ID 122U
-#define XPS_FPGA2_INT_ID 123U
-#define XPS_FPGA3_INT_ID 124U
-#define XPS_FPGA4_INT_ID 125U
-#define XPS_FPGA5_INT_ID 126U
-#define XPS_FPGA6_INT_ID 127U
-#define XPS_FPGA7_INT_ID 128U
-#define XPS_FPGA8_INT_ID 136U
-#define XPS_FPGA9_INT_ID 137U
-#define XPS_FPGA10_INT_ID 138U
-#define XPS_FPGA11_INT_ID 139U
-#define XPS_FPGA12_INT_ID 140U
-#define XPS_FPGA13_INT_ID 141U
-#define XPS_FPGA14_INT_ID 142U
-#define XPS_FPGA15_INT_ID 143U
-
-/* Updated Interrupt-IDs */
-#define XPS_OCMINTR_INT_ID (10U + 32U)
-#define XPS_NAND_INT_ID (14U + 32U)
-#define XPS_QSPI_INT_ID (15U + 32U)
-#define XPS_GPIO_INT_ID (16U + 32U)
-#define XPS_I2C0_INT_ID (17U + 32U)
-#define XPS_I2C1_INT_ID (18U + 32U)
-#define XPS_SPI0_INT_ID (19U + 32U)
-#define XPS_SPI1_INT_ID (20U + 32U)
-#define XPS_UART0_INT_ID (21U + 32U)
-#define XPS_UART1_INT_ID (22U + 32U)
-#define XPS_CAN0_INT_ID (23U + 32U)
-#define XPS_CAN1_INT_ID (24U + 32U)
-#define XPS_RTC_ALARM_INT_ID (26U + 32U)
-#define XPS_RTC_SEC_INT_ID (27U + 32U)
-#define XPS_LPD_SWDT_INT_ID (52U + 32U)
-#define XPS_FPD_SWDT_INT_ID (113U + 32U)
-#define XPS_TTC0_0_INT_ID (36U + 32U)
-#define XPS_TTC0_1_INT_ID (37U + 32U)
-#define XPS_TTC0_2_INT_ID (38U + 32U)
-#define XPS_TTC1_0_INT_ID (39U + 32U)
-#define XPS_TTC1_1_INT_ID (40U + 32U)
-#define XPS_TTC1_2_INT_ID (41U + 32U)
-#define XPS_TTC2_0_INT_ID (42U + 32U)
-#define XPS_TTC2_1_INT_ID (43U + 32U)
-#define XPS_TTC2_2_INT_ID (44U + 32U)
-#define XPS_TTC3_0_INT_ID (45U + 32U)
-#define XPS_TTC3_1_INT_ID (46U + 32U)
-#define XPS_TTC3_2_INT_ID (47U + 32U)
-#define XPS_SDIO0_INT_ID (48U + 32U)
-#define XPS_SDIO1_INT_ID (49U + 32U)
-#define XPS_AMS_INT_ID (56U + 32U)
-#define XPS_GEM0_INT_ID (57U + 32U)
-#define XPS_GEM0_WAKE_INT_ID (58U + 32U)
-#define XPS_GEM1_INT_ID (59U + 32U)
-#define XPS_GEM1_WAKE_INT_ID (60U + 32U)
-#define XPS_GEM2_INT_ID (61U + 32U)
-#define XPS_GEM2_WAKE_INT_ID (62U + 32U)
-#define XPS_GEM3_INT_ID (63U + 32U)
-#define XPS_GEM3_WAKE_INT_ID (64U + 32U)
-#define XPS_USB3_0_ENDPT_INT_ID (65U + 32U)
-#define XPS_USB3_1_ENDPT_INT_ID (70U + 32U)
-#define XPS_ADMA_CH0_INT_ID (77U + 32U)
-#define XPS_ADMA_CH1_INT_ID (78U + 32U)
-#define XPS_ADMA_CH2_INT_ID (79U + 32U)
-#define XPS_ADMA_CH3_INT_ID (80U + 32U)
-#define XPS_ADMA_CH4_INT_ID (81U + 32U)
-#define XPS_ADMA_CH5_INT_ID (82U + 32U)
-#define XPS_ADMA_CH6_INT_ID (83U + 32U)
-#define XPS_ADMA_CH7_INT_ID (84U + 32U)
-#define XPS_CSU_DMA_INT_ID (86U + 32U)
-#define XPS_XMPU_LPD_INT_ID (88U + 32U)
-#define XPS_ZDMA_CH0_INT_ID (124U + 32U)
-#define XPS_ZDMA_CH1_INT_ID (125U + 32U)
-#define XPS_ZDMA_CH2_INT_ID (126U + 32U)
-#define XPS_ZDMA_CH3_INT_ID (127U + 32U)
-#define XPS_ZDMA_CH4_INT_ID (128U + 32U)
-#define XPS_ZDMA_CH5_INT_ID (129U + 32U)
-#define XPS_ZDMA_CH6_INT_ID (130U + 32U)
-#define XPS_ZDMA_CH7_INT_ID (131U + 32U)
-#define XPS_XMPU_FPD_INT_ID (134U + 32U)
-#define XPS_FPD_CCI_INT_ID (154U + 32U)
-#define XPS_FPD_SMMU_INT_ID (155U + 32U)
-#define XPS_APM0_INT_ID (123U + 32U)
-#define XPS_APM1_INT_ID (25U + 32U)
-#define XPS_APM2_INT_ID (25U + 32U)
-#define XPS_APM5_INT_ID (123U + 32U)
-
-/* REDEFINES for TEST APP */
-#define XPAR_PSU_UART_0_INTR XPS_UART0_INT_ID
-#define XPAR_PSU_UART_1_INTR XPS_UART1_INT_ID
-#define XPAR_PSU_USB_0_INTR XPS_USB0_INT_ID
-#define XPAR_PSU_USB_1_INTR XPS_USB1_INT_ID
-#define XPAR_PSU_I2C_0_INTR XPS_I2C0_INT_ID
-#define XPAR_PSU_I2C_1_INTR XPS_I2C1_INT_ID
-#define XPAR_PSU_SPI_0_INTR XPS_SPI0_INT_ID
-#define XPAR_PSU_SPI_1_INTR XPS_SPI1_INT_ID
-#define XPAR_PSU_CAN_0_INTR XPS_CAN0_INT_ID
-#define XPAR_PSU_CAN_1_INTR XPS_CAN1_INT_ID
-#define XPAR_PSU_GPIO_0_INTR XPS_GPIO_INT_ID
-#define XPAR_PSU_ETHERNET_0_INTR XPS_GEM0_INT_ID
-#define XPAR_PSU_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
-#define XPAR_PSU_ETHERNET_1_INTR XPS_GEM1_INT_ID
-#define XPAR_PSU_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
-#define XPAR_PSU_ETHERNET_2_INTR XPS_GEM2_INT_ID
-#define XPAR_PSU_ETHERNET_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID
-#define XPAR_PSU_ETHERNET_3_INTR XPS_GEM3_INT_ID
-#define XPAR_PSU_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
-#define XPAR_PSU_QSPI_0_INTR XPS_QSPI_INT_ID
-#define XPAR_PSU_WDT_0_INTR XPS_LPD_SWDT_INT_ID
-#define XPAR_PSU_WDT_1_INTR XPS_FPD_SWDT_INT_ID
-#define XPAR_PSU_XADC_0_INTR XPS_SYSMON_INT_ID
-#define XPAR_PSU_TTC_0_INTR XPS_TTC0_0_INT_ID
-#define XPAR_PSU_TTC_1_INTR XPS_TTC0_1_INT_ID
-#define XPAR_PSU_TTC_2_INTR XPS_TTC0_2_INT_ID
-#define XPAR_PSU_TTC_3_INTR XPS_TTC1_0_INT_ID
-#define XPAR_PSU_TTC_4_INTR XPS_TTC1_1_INT_ID
-#define XPAR_PSU_TTC_5_INTR XPS_TTC1_2_INT_ID
-#define XPAR_PSU_TTC_6_INTR XPS_TTC2_0_INT_ID
-#define XPAR_PSU_TTC_7_INTR XPS_TTC2_1_INT_ID
-#define XPAR_PSU_TTC_8_INTR XPS_TTC2_2_INT_ID
-#define XPAR_PSU_TTC_9_INTR XPS_TTC3_0_INT_ID
-#define XPAR_PSU_TTC_10_INTR XPS_TTC3_1_INT_ID
-#define XPAR_PSU_TTC_11_INTR XPS_TTC3_2_INT_ID
-#define XPAR_PSU_AMS_INTR XPS_AMS_INT_ID
-
-#define XPAR_XADCPS_NUM_INSTANCES 1U
-#define XPAR_XADCPS_0_DEVICE_ID 0U
-#define XPAR_XADCPS_0_BASEADDR (0xF8007000U)
-#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
-
-/* For backwards compatibility */
-#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
-#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
-#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
-#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
-#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
-
-#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
-
-#ifdef XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
-#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ
-#endif
-
-#ifdef XPAR_CPU_CORTEXA53_1_CPU_CLK_FREQ_HZ
-#define XPAR_CPU_CORTEXA53_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA53_1_CPU_CLK_FREQ_HZ
-#endif
-
-#define XPAR_SCUWDT_DEVICE_ID 0U
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/**
- *@endcond
- */
-
-#endif /* protection macro */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ad/22238e595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ad/22238e595243001d18b399c1eb9b3628
deleted file mode 100644
index 1f20eea..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ad/22238e595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,78 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/* read.c -- read bytes from a input device.
- */
-#ifndef UNDEFINE_FILE_OPS
-#include "xil_printf.h"
-#include "xparameters.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes);
-}
-#endif
-
-/*
- * read -- read bytes from the serial port. Ignore fd, since
- * we only have stdin.
- */
-__attribute__((weak)) s32
-read (s32 fd, char8* buf, s32 nbytes)
-{
-#ifdef STDIN_BASEADDRESS
- s32 i;
- s32 numbytes = 0;
- char8* LocalBuf = buf;
-
- (void)fd;
- if(LocalBuf != NULL) {
- for (i = 0; i < nbytes; i++) {
- numbytes++;
- *(LocalBuf + i) = inbyte();
- if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
- break;
- }
- }
- }
-
- return numbytes;
-#else
- (void)fd;
- (void)buf;
- (void)nbytes;
- return 0;
-#endif
-}
-
-__attribute__((weak)) s32
-_read (s32 fd, char8* buf, s32 nbytes)
-{
-#ifdef STDIN_BASEADDRESS
- s32 i;
- s32 numbytes = 0;
- char8* LocalBuf = buf;
-
- (void)fd;
- if(LocalBuf != NULL) {
- for (i = 0; i < nbytes; i++) {
- numbytes++;
- *(LocalBuf + i) = inbyte();
- if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
- break;
- }
- }
- }
-
- return numbytes;
-#else
- (void)fd;
- (void)buf;
- (void)nbytes;
- return 0;
-#endif
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ad/309223545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ad/309223545243001d18b399c1eb9b3628
deleted file mode 100644
index e567699..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ad/309223545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,377 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xdevcfg.h
-* @addtogroup devcfg_v3_7
-* @{
-* @details
-*
-* The is the main header file for the Device Configuration Interface of the Zynq
-* device. The device configuration interface has three main functionality.
-* 1. AXI-PCAP
-* 2. Security Policy
-* 3. XADC
-* This current version of the driver supports only the AXI-PCAP and Security
-* Policy blocks. There is a separate driver for XADC.
-*
-* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream.
-* DMA embedded in the AXI PCAP provides the master interface to
-* the Device configuration block for any DMA transfers. The data transfer can
-* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip
-* RAM/DDR/peripheral memory).
-*
-* The current driver only supports the downloading the FPGA bitstream and
-* readback of the decrypted image (sort of loopback).
-* The driver does not know what information needs to be written to the FPGA to
-* readback FPGA configuration register or memory data. The application above the
-* driver should take care of creating the data that needs to be downloaded to
-* the FPGA so that the bitstream can be readback.
-* This driver also does not support the reading of the internal registers of the
-* PCAP. The driver has no knowledge of the PCAP internals.
-*
-* Initialization and Configuration
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate with the Device Configuration device.
-*
-* XDcfg_CfgInitialize() API is used to initialize the Device Configuration
-* Interface. The user needs to first call the XDcfg_LookupConfig() API which
-* returns the Configuration structure pointer which is passed as a parameter to
-* the XDcfg_CfgInitialize() API.
-*
-* Interrupts
-* The Driver implements an interrupt handler to support the interrupts provided
-* by this interface.
-*
-* Threads
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* Asserts
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* Building the driver
-*
-* The XDcfg driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
-* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
-* APIs is words (32 bit) and not bytes.
-* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
-* to add information that 2 LSBs of the Source/Destination
-* address when equal to 2�b01 indicate the last DMA command
-* of an overall transfer.
-* Destination Address passed to this API for secure transfers
-* instead of using 0xFFFFFFFF for CR 662197. This issue was
-* resulting in the failure of secure transfers of
-* non-bitstream images.
-* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
-* set the mask instead of oring it with the
-* value read from the interrupt status register
-* Added defines for the PS Version bits,
-* removed the FIFO Flush bits from the
-* Miscellaneous Control Reg.
-* Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
-* and XDcfg_SelectPcapInterface APIs for CR 643295
-* The user has to call the XDcfg_SelectIcapInterface API
-* for the PL reconfiguration using AXI HwIcap.
-* Updated the XDcfg_Transfer API to clear the
-* QUARTER_PCAP_RATE_EN bit in the control register for
-* non secure writes for CR 675543.
-* 2.02a nm 01/31/13 Fixed CR# 679335.
-* Added Setting and Clearing the internal PCAP loopback.
-* Removed code for enabling/disabling AES engine as BootROM
-* locks down this setting.
-* Fixed CR# 681976.
-* Skip Checking the PCFG_INIT in case of non-secure DMA
-* loopback.
-* Fixed CR# 699558.
-* XDcfg_Transfer fails to transfer data in loopback mode.
-* Fixed CR# 701348.
-* Peripheral test fails with Running
-* DcfgSelfTestExample() in SECURE bootmode.
-* 2.03a nm 04/19/13 Fixed CR# 703728.
-* Updated the register definitions as per the latest TRM
-* version UG585 (v1.4) November 16, 2012.
-* 3.0 adk 10/12/13 Updated as per the New Tcl API's
-* 3.0 kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
-* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
-* updated driver code with != instead of ==,
-* while checking for Interrupt Status with DMA and
-* PCAP Done Mask
-* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
-* XDCFG_INT_STS_OFFSET) &
-* XDCFG_IXR_D_P_DONE_MASK) !=
-* XDCFG_IXR_D_P_DONE_MASK);
-* A new example has been added to read back the
-* configuration registers from the PL region.
-* xdevcfg_reg_readback_example.c
-* 3.3 sk 04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/10/17 Modified filename tag in interrupt and polled examples
-* to include them in doxygen examples.
-* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros
-* definitions of devcfg in xparameters.h
-* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
-*
-*
-******************************************************************************/
-#ifndef XDCFG_H /* prevent circular inclusions */
-#define XDCFG_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xdevcfg_hw.h"
-#include "xstatus.h"
-#include "xil_assert.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/* Types of PCAP transfers */
-
-#define XDCFG_NON_SECURE_PCAP_WRITE 1
-#define XDCFG_SECURE_PCAP_WRITE 2
-#define XDCFG_PCAP_READBACK 3
-#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4
-#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5
-
-
-/**************************** Type Definitions *******************************/
-/**
-* The handler data type allows the user to define a callback function to
-* respond to interrupt events in the system. This function is executed
-* in interrupt context, so amount of processing should be minimized.
-*
-* @param CallBackRef is the callback reference passed in by the upper
-* layer when setting the callback functions, and passed back to
-* the upper layer when the callback is invoked. Its type is
-* unimportant to the driver component, so it is a void pointer.
-* @param Status is the Interrupt status of the XDcfg device.
-*/
-typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddr; /**< Base address of the device */
-} XDcfg_Config;
-
-/**
- * The XDcfg driver instance data.
- */
-typedef struct {
- XDcfg_Config Config; /**< Hardware Configuration */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStarted; /**< Device Configuration Interface
- * is running
- */
- XDcfg_IntrHandler StatusHandler; /* Event handler function */
- void *CallBackRef; /* Callback reference for event handler */
-} XDcfg;
-
-/****************************************************************************/
-/**
-*
-* Unlock the Device Config Interface block.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_Unlock(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_Unlock(InstancePtr) \
- XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \
- XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
-
-
-
-/****************************************************************************/
-/**
-*
-* Get the version number of the PS from the Miscellaneous Control Register.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return Version of the PS.
-*
-* @note C-style signature:
-* void XDcfg_GetPsVersion(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_GetPsVersion(InstancePtr) \
- ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
- XDCFG_MCTRL_OFFSET)) & \
- XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \
- XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
-
-
-
-/****************************************************************************/
-/**
-*
-* Read the multiboot config register value.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_ReadMultiBootConfig(InstancePtr) \
- XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
- XDCFG_MULTIBOOT_ADDR_OFFSET)
-
-
-/****************************************************************************/
-/**
-*
-* Selects ICAP interface for reconfiguration after the initial configuration
-* of the PL.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_SelectIcapInterface(InstancePtr) \
- XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
- ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
- & ( ~XDCFG_CTRL_PCAP_PR_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Selects PCAP interface for reconfiguration after the initial configuration
-* of the PL.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_SelectPcapInterface(InstancePtr) \
- XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
- ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
- | XDCFG_CTRL_PCAP_PR_MASK))
-
-
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Lookup configuration in xdevcfg_sinit.c.
- */
-XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId);
-
-/*
- * Selftest function in xdevcfg_selftest.c
- */
-int XDcfg_SelfTest(XDcfg *InstancePtr);
-
-/*
- * Interface functions in xdevcfg.c
- */
-int XDcfg_CfgInitialize(XDcfg *InstancePtr,
- XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
-
-void XDcfg_EnablePCAP(XDcfg *InstancePtr);
-
-void XDcfg_DisablePCAP(XDcfg *InstancePtr);
-
-void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask);
-
-void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask);
-
-u32 XDcfg_GetControlRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetLockRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask);
-
-u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr);
-
-u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr);
-
-void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
- u32 SrcWordLength, u32 DestWordLength);
-
-u32 XDcfg_Transfer(XDcfg *InstancePtr,
- void *SourcePtr, u32 SrcWordLength,
- void *DestPtr, u32 DestWordLength,
- u32 TransferType);
-
-/*
- * Interrupt related function prototypes implemented in xdevcfg_intr.c
- */
-void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask);
-
-void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask);
-
-u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr);
-
-u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr);
-
-void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask);
-
-void XDcfg_InterruptHandler(XDcfg *InstancePtr);
-
-void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
- void *CallBackRef);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ad/41eea0565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ad/41eea0565243001d18b399c1eb9b3628
deleted file mode 100644
index 559ae46..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ad/41eea0565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,101 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2008 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-*
-* microblaze_invalidate_dcache_range (unsigned int cacheaddr, unsigned int len)
-*
-* Invalidate a Dcache range
-*
-* Parameters:
-* 'cacheaddr' - address in the Dcache where invalidation begins
-* 'len ' - length (in bytes) worth of Dcache to be invalidated
-*
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-#include "microblaze_instructions.h"
-
-#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
-#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
-
-#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
-#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
-#endif
-
-#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
-#define MB_VERSION_LT_v720
-#define MB_HAS_WRITEBACK_SET 0
-#else
-#define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
-#endif
-
- .text
- .globl microblaze_invalidate_dcache_range
- .ent microblaze_invalidate_dcache_range
- .align 2
-
-microblaze_invalidate_dcache_range:
-#if (XPAR_MICROBLAZE_USE_DCACHE==1) && (XPAR_MICROBLAZE_ALLOW_DCACHE_WR==1)
-
-#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
- mfs r9, rmsr
- andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
- mts rmsr, r10
-#endif
-
- BEQI r6, L_done /* Skip loop if size is zero */
-
- ADD r6, r5, r6 /* Compute end address */
- ADDIK r6, r6, -1
-
- ANDI r6, r6, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align end down to cache line */
- ANDI r5, r5, -(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN) /* Align start down to cache line */
-
-#if MB_HAS_WRITEBACK_SET == 0 /* Use a different scheme for MB version < v7.20 or when caches are write-through */
-
-L_start:
- CMPU r18, r5, r6 /* Are we at the end? */
- BLTI r18, L_done
-
- wdc r5, r0
-
-#if defined (__arch64__ )
- addlik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the address by 4 */
- breai L_start /* Branch to the beginning of the loop */
-#else
- brid L_start /* Branch to the beginning of the loop */
- addik r5, r5, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4) /* Increment the address by 4 (delay slot) */
-#endif
-#else
-
- RSUBK r6, r5, r6
- /* r6 will now contain (count of bytes - (4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN)) */
-L_start:
- wdc.clear r5, r6 /* Invalidate the cache line only if the address matches */
-#if defined (__arch64__ )
- addlik r6, r6, -(XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
- beagei r6, L_start
-#else
- bneid r6, L_start
- addik r6, r6, -(XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
-#endif
-
-#endif
-
-L_done:
- rtsd r15, 8
-#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
- mts rmsr, r9
-#else
- nop
-#endif
-
-#else
- rtsd r15, 8
- nop
-#endif
- .end microblaze_invalidate_dcache_range
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ad/810b3c595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ad/810b3c595243001d18b399c1eb9b3628
deleted file mode 100644
index f101c14..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ad/810b3c595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,341 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_testcache.c
-* @addtogroup common_test_utils
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/28/09 Initial release
-* 4.1 asa 05/09/14 Ensured that the address uses for cache test is aligned
-* cache line.
-*
-*
-******************************************************************************/
-#ifdef __ARM__
-#include "xil_cache.h"
-#include "xil_testcache.h"
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#ifdef __aarch64__
-#include "xreg_cortexa53.h"
-#else
-#include "xreg_cortexr5.h"
-#endif
-
-#include "xil_types.h"
-
-extern void xil_printf(const char8 *ctrl1, ...);
-
-#define DATA_LENGTH 128
-
-#ifdef __aarch64__
-static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64)));
-#else
-static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32)));
-#endif
-
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform DCache range related API test such as Xil_DCacheFlushRange
-* and Xil_DCacheInvalidateRange. This test function writes a constant
-* value to the Data array, flushes the range, writes a new value, then
-* invalidates the corresponding range.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-s32 Xil_TestDCacheRange(void)
-{
- s32 Index;
- s32 Status = 0;
- u32 CtrlReg;
- INTPTR Value;
-
- xil_printf("-- Cache Range Test --\n\r");
-
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0xA0A00505;
-
- xil_printf(" initialize Data done:\r\n");
-
- Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
-
- xil_printf(" flush range done\r\n");
-
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
-
- Status = 0;
-
- for (Index = 0; Index < DATA_LENGTH; Index++) {
- Value = Data[Index];
- if (Value != 0xA0A00505) {
- Status = -1;
- xil_printf("Data[%d] = %x\r\n", Index, Value);
- break;
- }
- }
-
- if (!Status) {
- xil_printf(" Flush worked\r\n");
- }
- else {
- xil_printf("Error: flush dcache range not working\r\n");
- }
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0xA0A0C505;
-
-
-
- Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
-
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = Index + 3;
-
- Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
-
- xil_printf(" invalidate dcache range done\r\n");
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0xA0A0A05;
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
-
- Status = 0;
-
- for (Index = 0; Index < DATA_LENGTH; Index++) {
- Value = Data[Index];
- if (Value != 0xA0A0A05) {
- Status = -1;
- xil_printf("Data[%d] = %x\r\n", Index, Value);
- break;
- }
- }
-
-
- if (!Status) {
- xil_printf(" Invalidate worked\r\n");
- }
- else {
- xil_printf("Error: Invalidate dcache range not working\r\n");
- }
- xil_printf("-- Cache Range Test Complete --\r\n");
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-* @brief Perform DCache all related API test such as Xil_DCacheFlush and
-* Xil_DCacheInvalidate. This test function writes a constant value
-* to the Data array, flushes the DCache, writes a new value,
-* then invalidates the DCache.
-*
-* @return
-* - 0 is returned for a pass
-* - -1 is returned for a failure
-*****************************************************************************/
-s32 Xil_TestDCacheAll(void)
-{
- s32 Index;
- s32 Status;
- INTPTR Value;
- u32 CtrlReg;
-
- xil_printf("-- Cache All Test --\n\r");
-
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0x50500A0A;
- xil_printf(" initialize Data done:\r\n");
-
- Xil_DCacheFlush();
- xil_printf(" flush all done\r\n");
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
- Status = 0;
-
- for (Index = 0; Index < DATA_LENGTH; Index++) {
- Value = Data[Index];
-
- if (Value != 0x50500A0A) {
- Status = -1;
- xil_printf("Data[%d] = %x\r\n", Index, Value);
- break;
- }
- }
-
- if (!Status) {
- xil_printf(" Flush all worked\r\n");
- }
- else {
- xil_printf("Error: Flush dcache all not working\r\n");
- }
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0x505FFA0A;
-
- Xil_DCacheFlush();
-
-
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = Index + 3;
-
- Xil_DCacheInvalidate();
-
- xil_printf(" invalidate all done\r\n");
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0x50CFA0A;
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
- Status = 0;
-
- for (Index = 0; Index < DATA_LENGTH; Index++) {
- Value = Data[Index];
- if (Value != 0x50CFA0A) {
- Status = -1;
- xil_printf("Data[%d] = %x\r\n", Index, Value);
- break;
- }
- }
-
- if (!Status) {
- xil_printf(" Invalidate all worked\r\n");
- }
- else {
- xil_printf("Error: Invalidate dcache all not working\r\n");
- }
-
- xil_printf("-- DCache all Test Complete --\n\r");
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief Perform Xil_ICacheInvalidateRange() on a few function pointers.
-*
-* @return
-* - 0 is returned for a pass
-*
-* @note The function will hang if it fails.
-*****************************************************************************/
-s32 Xil_TestICacheRange(void)
-{
-
- Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024);
- Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024);
- Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024);
-
- xil_printf("-- Invalidate icache range done --\r\n");
-
- return 0;
-}
-
-/*****************************************************************************/
-/**
-* @brief Perform Xil_ICacheInvalidate() on a few function pointers.
-*
-* @return
-* - 0 is returned for a pass
-*
-* @note The function will hang if it fails.
-*****************************************************************************/
-s32 Xil_TestICacheAll(void)
-{
- Xil_ICacheInvalidate();
- xil_printf("-- Invalidate icache all done --\r\n");
- return 0;
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ad/b07d87575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ad/b07d87575243001d18b399c1eb9b3628
deleted file mode 100644
index 5007212..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ad/b07d87575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,111 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2017 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_sleeptimer.h
-*
-* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs.
-* For sleep related functions that can be used across all Xilinx supported
-* processors, please use xil_sleeptimer.h.
-*
-*
-*
-* MODIFICATION HISTORY :
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 6.6 srm 10/18/17 First Release.
-* 7.0 mus 01/07/19 Add cpp extern macro
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.02a hk 08/22/13 First Release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
-* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
-* in safety mode and modified the code such as
-* Use of mixed mode arithmetic,Declared the pointer param
-* as Pointer to const,Casting operation to a pointer,
-* Literal value requires a U suffix.
-* 3.5 sne 03/14/19 Added versal support.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 6.0 mus 27/07/16 Consolidated exceptions for a53,a9 and r5
-* processors and added Xil_UndefinedExceptionHandler
-* for a53 32 bit and r5 as well.
-* 6.4 mus 08/06/17 Updated debug prints to replace %x with the %lx, to
-* fix the warnings.
-* 6.7 mna 26/04/18 Add an API to obtain a corresponding
-* Xil_ExceptionHandler entry from XExc_VectorTable.
-* 6.7 asa 18/05/18 Fix bugs in the API Xil_GetExceptionRegisterHandler.
-* 7.0 mus 07/03/19 Tweak Xil_ExceptionRegisterHandler and
-* Xil_GetExceptionRegisterHandler to support legacy
-* examples for Cortexa72 EL3 exception level.
-* 7.3 mus 07/27/20 Updated Xil_ExceptionRegisterHandler and
-* Xil_GetExceptionRegisterHandler to ignore
-* Exception_id, only if its pointing to IRQ.
-* It fixes CR#1069524
-*
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_exception.h"
-#include "xpseudo_asm.h"
-#include "xdebug.h"
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-typedef struct {
- Xil_ExceptionHandler Handler;
- void *Data;
-} XExc_VectorTableEntry;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Function Prototypes *****************************/
-static void Xil_ExceptionNullHandler(void *Data);
-/************************** Variable Definitions *****************************/
-/*
- * Exception vector table to store handlers for each exception vector.
- */
-#if defined (__aarch64__)
-XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
-{
- {Xil_ExceptionNullHandler, NULL},
- {Xil_SyncAbortHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
- {Xil_SErrorAbortHandler, NULL},
-
-};
-#else
-XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
-{
- {Xil_ExceptionNullHandler, NULL},
- {Xil_UndefinedExceptionHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
- {Xil_PrefetchAbortHandler, NULL},
- {Xil_DataAbortHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
-};
-#endif
-#if !defined (__aarch64__)
-u32 DataAbortAddr; /* Address of instruction causing data abort */
-u32 PrefetchAbortAddr; /* Address of instruction causing prefetch abort */
-u32 UndefinedExceptionAddr; /* Address of instruction causing Undefined
- exception */
-#endif
-
-/*****************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* This function is a stub Handler that is the default Handler that gets called
-* if the application has not setup a Handler for a specific exception. The
-* function interface has to match the interface specified for a Handler even
-* though none of the arguments are used.
-*
-* @param Data is unused by this function.
-*
-* @return None.
-*
-*****************************************************************************/
-static void Xil_ExceptionNullHandler(void *Data)
-{
- (void) Data;
-DieLoop: goto DieLoop;
-}
-
-/****************************************************************************/
-/**
-* @brief The function is a common API used to initialize exception handlers
-* across all supported arm processors. For ARM Cortex-A53, Cortex-R5,
-* and Cortex-A9, the exception handlers are being initialized
-* statically and this function does not do anything.
-* However, it is still present to take care of backward compatibility
-* issues (in earlier versions of BSPs, this API was being used to
-* initialize exception handlers).
-*
-* @return None.
-*
-*****************************************************************************/
-void Xil_ExceptionInit(void)
-{
- return;
-}
-
-/*****************************************************************************/
-/**
-* @brief Register a handler for a specific exception. This handler is being
-* called when the processor encounters the specified exception.
-*
-* @param Exception_id contains the ID of the exception source and should
-* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
-* See xil_exception.h for further information.
-* @param Handler to the Handler for that exception.
-* @param Data is a reference to Data that will be passed to the
-* Handler when it gets called.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler Handler,
- void *Data)
-{
-#if defined (versal) && !defined(ARMR5) && EL3
- if ( XIL_EXCEPTION_ID_IRQ_INT == Exception_id )
- {
- /*
- * Cortexa72 processor in versal is coupled with GIC-500, and
- * GIC-500 supports only FIQ at EL3. Hence, tweaking this API
- * to act on IRQ, if Exception_id is pointing to IRQ
- */
- Exception_id = XIL_EXCEPTION_ID_FIQ_INT;
- }
-#endif
- XExc_VectorTable[Exception_id].Handler = Handler;
- XExc_VectorTable[Exception_id].Data = Data;
-}
-
-/*****************************************************************************/
-/**
-* @brief Get a handler for a specific exception. This handler is being
-* called when the processor encounters the specified exception.
-*
-* @param Exception_id contains the ID of the exception source and should
-* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
-* See xil_exception.h for further information.
-* @param Handler to the Handler for that exception.
-* @param Data is a reference to Data that will be passed to the
-* Handler when it gets called.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_GetExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler *Handler,
- void **Data)
-{
-#if defined (versal) && !defined(ARMR5) && EL3
- if ( XIL_EXCEPTION_ID_IRQ_INT == Exception_id )
- {
- /*
- * Cortexa72 processor in versal is coupled with GIC-500, and
- * GIC-500 supports only FIQ at EL3. Hence, tweaking this API
- * to act on IRQ, if Exception_id is pointing to IRQ
- */
-
- Exception_id = XIL_EXCEPTION_ID_FIQ_INT;
- }
-#endif
-
- *Handler = XExc_VectorTable[Exception_id].Handler;
- *Data = XExc_VectorTable[Exception_id].Data;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Removes the Handler for a specific exception Id. The stub Handler
-* is then registered for this exception Id.
-*
-* @param Exception_id contains the ID of the exception source and should
-* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
-* See xil_exception.h for further information.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ExceptionRemoveHandler(u32 Exception_id)
-{
- Xil_ExceptionRegisterHandler(Exception_id,
- Xil_ExceptionNullHandler,
- NULL);
-}
-
-#if defined (__aarch64__)
-/*****************************************************************************/
-/**
-*
-* Default Synchronous abort handler which prints a debug message on console if
-* Debug flag is enabled
-*
-* @return None.
-*
-****************************************************************************/
-
-void Xil_SyncAbortHandler(void *CallBackRef){
- (void) CallBackRef;
- xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
- while(1) {
- ;
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Default SError abort handler which prints a debug message on console if
-* Debug flag is enabled
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_SErrorAbortHandler(void *CallBackRef){
- (void) CallBackRef;
- xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
- while(1) {
- ;
- }
-}
-#else
-/*****************************************************************************/
-/**
-*
-* Default Data abort handler which prints data fault status register through
-* which information about data fault can be acquired
-*
-* @return None.
-*
-****************************************************************************/
-
-void Xil_DataAbortHandler(void *CallBackRef){
- (void) CallBackRef;
-#ifdef DEBUG
- u32 FaultStatus;
-
- xdbg_printf(XDBG_DEBUG_ERROR, "Data abort \n");
- #ifdef __GNUC__
- FaultStatus = mfcp(XREG_CP15_DATA_FAULT_STATUS);
- #elif defined (__ICCARM__)
- mfcp(XREG_CP15_DATA_FAULT_STATUS,FaultStatus);
- #else
- { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS);
- FaultStatus = Reg; }
- #endif
- xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register %lx\n",FaultStatus);
- xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Data abort %lx\n",DataAbortAddr);
-#endif
- while(1) {
- ;
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Default Prefetch abort handler which prints prefetch fault status register through
-* which information about instruction prefetch fault can be acquired
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_PrefetchAbortHandler(void *CallBackRef){
- (void) CallBackRef;
-#ifdef DEBUG
- u32 FaultStatus;
-
- xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort \n");
- #ifdef __GNUC__
- FaultStatus = mfcp(XREG_CP15_INST_FAULT_STATUS);
- #elif defined (__ICCARM__)
- mfcp(XREG_CP15_INST_FAULT_STATUS,FaultStatus);
- #else
- { volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS);
- FaultStatus = Reg; }
- #endif
- xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register %lx\n",FaultStatus);
- xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Prefetch abort %lx\n",PrefetchAbortAddr);
-#endif
- while(1) {
- ;
- }
-}
-/*****************************************************************************/
-/**
-*
-* Default undefined exception handler which prints address of the undefined
-* instruction if debug prints are enabled
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_UndefinedExceptionHandler(void *CallBackRef){
- (void) CallBackRef;
- xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %lx\n",UndefinedExceptionAddr);
- while(1) {
- ;
- }
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ae/313b58585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ae/313b58585243001d18b399c1eb9b3628
deleted file mode 100644
index 3d5b832..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ae/313b58585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,136 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2019 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm_armclang.h
-*
-* This header file contains macros for using __inline assembler code.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 7.0 cjp 02/26/19 First Release
-* 7.2 asa 04/03/20 Renamed the str macro to strw.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 02/01/10 Initial version
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef _XL2CC_H_
-#define _XL2CC_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-/* L2CC Register Offsets */
-#define XPS_L2CC_ID_OFFSET 0x0000U
-#define XPS_L2CC_TYPE_OFFSET 0x0004U
-#define XPS_L2CC_CNTRL_OFFSET 0x0100U
-#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104U
-#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108U
-#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010CU
-
-#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200U
-#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204U
-#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208U
-#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020CU
-#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210U
-
-#define XPS_L2CC_IER_OFFSET 0x0214U /* Interrupt Mask */
-#define XPS_L2CC_IPR_OFFSET 0x0218U /* Masked interrupt status */
-#define XPS_L2CC_ISR_OFFSET 0x021CU /* Raw Interrupt Status */
-#define XPS_L2CC_IAR_OFFSET 0x0220U /* Interrupt Clear */
-
-#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730U /* Cache Sync */
-#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740U /* Dummy Register for Cache Sync */
-#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770U /* Cache Invalid by PA */
-#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077CU /* Cache Invalid by Way */
-#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0U /* Cache Clean by PA */
-#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8U /* Cache Clean by Index */
-#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BCU /* Cache Clean by Way */
-#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0U /* Cache Invalidate and Clean by PA */
-#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8U /* Cache Invalidate and Clean by Index */
-#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FCU /* Cache Invalidate and Clean by Way */
-
-#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900U /* Cache Data Lockdown 0 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904U /* Cache Instruction Lockdown 0 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908U /* Cache Data Lockdown 1 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090CU /* Cache Instruction Lockdown 1 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910U /* Cache Data Lockdown 2 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914U /* Cache Instruction Lockdown 2 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918U /* Cache Data Lockdown 3 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091CU /* Cache Instruction Lockdown 3 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920U /* Cache Data Lockdown 4 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924U /* Cache Instruction Lockdown 4 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928U /* Cache Data Lockdown 5 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092CU /* Cache Instruction Lockdown 5 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930U /* Cache Data Lockdown 6 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934U /* Cache Instruction Lockdown 6 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938U /* Cache Data Lockdown 7 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093CU /* Cache Instruction Lockdown 7 by Way */
-
-#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U /* Cache Lockdown Line Enable */
-#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954U /* Cache Unlock All Lines by Way */
-
-#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00U /* Start of address filtering */
-#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04U /* Start of address filtering */
-
-#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40U /* Debug Control Register */
-
-/* XPS_L2CC_CNTRL_OFFSET bit masks */
-#define XPS_L2CC_ENABLE_MASK 0x00000001U /* enables the L2CC */
-
-/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */
-#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000U /* Early BRESP Enable */
-#define XPS_L2CC_AUX_IPFE_MASK 0x20000000U /* Instruction Prefetch Enable */
-#define XPS_L2CC_AUX_DPFE_MASK 0x10000000U /* Data Prefetch Enable */
-#define XPS_L2CC_AUX_NSIC_MASK 0x08000000U /* Non-secure interrupt access control */
-#define XPS_L2CC_AUX_NSLE_MASK 0x04000000U /* Non-secure lockdown enable */
-#define XPS_L2CC_AUX_CRP_MASK 0x02000000U /* Cache replacement policy */
-#define XPS_L2CC_AUX_FWE_MASK 0x01800000U /* Force write allocate */
-#define XPS_L2CC_AUX_SAOE_MASK 0x00400000U /* Shared attribute override enable */
-#define XPS_L2CC_AUX_PE_MASK 0x00200000U /* Parity enable */
-#define XPS_L2CC_AUX_EMBE_MASK 0x00100000U /* Event monitor bus enable */
-#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000U /* Way-size */
-#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000U /* Associativity */
-#define XPS_L2CC_AUX_SAIE_MASK 0x00002000U /* Shared attribute invalidate enable */
-#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000U /* Exclusive cache configuration */
-#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800U /* Store buffer device limitation Enable */
-#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400U /* High Priority for SO and Dev Reads Enable */
-#define XPS_L2CC_AUX_FLZE_MASK 0x00000001U /* Full line of zero enable */
-
-#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000U /* Enable all prefetching, */
- /* Cache replacement policy, Parity enable, */
- /* Event monitor bus enable and Way Size (64 KB) */
-#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFFU /* */
-
-#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111U /* latency for TAG RAM */
-#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121U /* latency for DATA RAM */
-
-/* Interrupt bit masks */
-#define XPS_L2CC_IXR_DECERR_MASK 0x00000100U /* DECERR from L3 */
-#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080U /* SLVERR from L3 */
-#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040U /* Error on L2 data RAM (Read) */
-#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020U /* Error on L2 tag RAM (Read) */
-#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010U /* Error on L2 data RAM (Write) */
-#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008U /* Error on L2 tag RAM (Write) */
-#define XPS_L2CC_IXR_PARRD_MASK 0x00000004U /* Parity Error on L2 data RAM (Read) */
-#define XPS_L2CC_IXR_PARRT_MASK 0x00000002U /* Parity Error on L2 tag RAM (Read) */
-#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001U /* Event Counter1/0 Overflow Increment */
-
-/* Address filtering mask and enable bit */
-#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000U /* Address filtering valid bits*/
-#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U /* Address filtering enable bit*/
-
-/* Debug control bits */
-#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004U /* Debug SPIDEN bit */
-#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002U /* Debug DWB bit, forces write through */
-#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002U /* Debug DCL bit, disables cache line fill */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* protection macro */
-
-/**
- *@endcond
- */
\ No newline at end of file
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ae/d0abaa595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ae/d0abaa595243001d18b399c1eb9b3628
deleted file mode 100644
index d21e13a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ae/d0abaa595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,92 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2012 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_mmu.h
-*
-* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions
-*
-* MMU functions equip users to enable MMU, disable MMU and modify default
-* memory attributes of MMU table as per the need.
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 01/12/12 Initial version
-* 4.2 pkp 07/21/14 Included xil_types.h file which contains definition for
-* u32 which resolves issue of CR#805869
-* 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 First release
-* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
-* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
-* changed to volatile.
-*
-*
-*
-******************************************************************************/
-
-#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */
-#define XEMACPS_BDRING_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/**************************** Type Definitions *******************************/
-
-/** This is an internal structure used to maintain the DMA list */
-typedef struct {
- UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
- UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */
- UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */
- u32 Length; /**< Total size of ring in bytes */
- u32 RunState; /**< Flag to indicate DMA is started */
- u32 Separation; /**< Number of bytes between the starting address
- of adjacent BDs */
- XEmacPs_Bd *FreeHead;
- /**< First BD in the free group */
- XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
- XEmacPs_Bd *HwHead; /**< First BD in the work group */
- XEmacPs_Bd *HwTail; /**< Last BD in the work group */
- XEmacPs_Bd *PostHead;
- /**< First BD in the post-work group */
- XEmacPs_Bd *BdaRestart;
- /**< BDA to load when channel is started */
-
- volatile u32 HwCnt; /**< Number of BDs in work group */
- u32 PreCnt; /**< Number of BDs in pre-work group */
- u32 FreeCnt; /**< Number of allocatable BDs in the free group */
- u32 PostCnt; /**< Number of BDs in post-work group */
- u32 AllCnt; /**< Total Number of BDs for channel */
-} XEmacPs_BdRing;
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
-* Use this macro at initialization time to determine how many BDs will fit
-* in a BD list within the given memory constraints.
-*
-* The results of this macro can be provided to XEmacPs_BdRingCreate().
-*
-* @param Alignment specifies what byte alignment the BDs must fall on and
-* must be a power of 2 to get an accurate calculation (32, 64, 128,...)
-* @param Bytes is the number of bytes to be used to store BDs.
-*
-* @return Number of BDs that can fit in the given memory area
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
-*
-******************************************************************************/
-#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \
- (u32)((Bytes) / (sizeof(XEmacPs_Bd)))
-
-/*****************************************************************************/
-/**
-* Use this macro at initialization time to determine how many bytes of memory
-* is required to contain a given number of BDs at a given alignment.
-*
-* @param Alignment specifies what byte alignment the BDs must fall on. This
-* parameter must be a power of 2 to get an accurate calculation (32, 64,
-* 128,...)
-* @param NumBd is the number of BDs to calculate memory size requirements for
-*
-* @return The number of bytes of memory required to create a BD list with the
-* given memory constraints.
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
-*
-******************************************************************************/
-#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \
- (u32)(sizeof(XEmacPs_Bd) * (NumBd))
-
-/****************************************************************************/
-/**
-* Return the total number of BDs allocated by this channel with
-* XEmacPs_BdRingCreate().
-*
-* @param RingPtr is the DMA channel to operate on.
-*
-* @return The total number of BDs allocated for this channel.
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
-
-/****************************************************************************/
-/**
-* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
-* processing.
-*
-* @param RingPtr is the DMA channel to operate on.
-*
-* @return The number of BDs currently allocatable.
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt)
-
-/****************************************************************************/
-/**
-* Return the next BD from BdPtr in a list.
-*
-* @param RingPtr is the DMA channel to operate on.
-* @param BdPtr is the BD to operate on.
-*
-* @return The next BD in the list relative to the BdPtr parameter.
-*
-* @note
-* C-style signature:
-* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
-* XEmacPs_Bd *BdPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingNext(RingPtr, BdPtr) \
- (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ? \
- (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) : \
- (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
-
-/****************************************************************************/
-/**
-* Return the previous BD from BdPtr in the list.
-*
-* @param RingPtr is the DMA channel to operate on.
-* @param BdPtr is the BD to operate on
-*
-* @return The previous BD in the list relative to the BdPtr parameter.
-*
-* @note
-* C-style signature:
-* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
-* XEmacPs_Bd *BdPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \
- (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \
- (XEmacPs_Bd*)(RingPtr)->HighBdAddr : \
- (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Scatter gather DMA related functions in xemacps_bdring.c
- */
-LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
- UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
-LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
- u8 Direction);
-LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd ** BdSetPtr);
-LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr);
-LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr);
-LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr);
-u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
- XEmacPs_Bd ** BdSetPtr);
-u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
- XEmacPs_Bd ** BdSetPtr);
-LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
-
-void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* end of protection macros */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/af/10f7a3525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/af/10f7a3525243001d18b399c1eb9b3628
deleted file mode 100644
index 9d33a6c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/af/10f7a3525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,193 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xgpio.h
-* @addtogroup gpio_v4_8
-* @{
-* @details
-*
-* This file contains the software API definition of the Xilinx General Purpose
-* I/O (XGpio) device driver.
-*
-* The Xilinx GPIO controller is a soft IP core designed for Xilinx FPGAs and
-* contains the following general features:
-* - Support for up to 32 I/O discretes for each channel (64 bits total).
-* - Each of the discretes can be configured for input or output.
-* - Configurable support for dual channels and interrupt generation.
-*
-* The driver provides interrupt management functions. Implementation of
-* interrupt handlers is left to the user. Refer to the provided interrupt
-* example in the examples directory for details.
-*
-* This driver is intended to be RTOS and processor independent. Any needs for
-* dynamic memory management, threads or thread mutual exclusion, virtual
-* memory, or cache control must be satisfied by the layer above this driver.
-*
-* Initialization & Configuration
-*
-* The XGpio_Config structure is used by the driver to configure itself. This
-* configuration structure is typically created by the tool-chain based on HW
-* build properties.
-*
-* To support multiple runtime loading and initialization strategies employed
-* by various operating systems, the driver instance can be initialized in one
-* of the following ways:
-*
-* - XGpio_Initialize(InstancePtr, DeviceId) - The driver looks up its own
-* configuration structure created by the tool-chain based on an ID provided
-* by the tool-chain.
-*
-* - XGpio_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-* configuration structure provided by the caller. If running in a system
-* with address translation, the provided virtual memory base address
-* replaces the physical address present in the configuration structure.
-*
-* @note
-*
-* This API utilizes 32 bit I/O to the GPIO registers. With less than 32 bits,
-* the unused bits from registers are read as zero and written as don't cares.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 03/13/02 First release
-* 2.00a jhl 11/26/03 Added support for dual channels and interrupts
-* 2.01a jvb 12/14/05 I separated dependency on the static config table and
-* xparameters.h from the driver initialization by moving
-* _Initialize and _LookupConfig to _sinit.c. I also added
-* the new _CfgInitialize routine.
-* 2.11a mta 03/21/07 Updated to new coding style, added GetDataDirection
-* 2.12a sv 11/21/07 Updated driver to support access through DCR bus
-* 2.12a sv 06/05/08 Updated driver to fix the XGpio_InterruptDisable function
-* to properly update the Interrupt Enable register
-* 2.13a sdm 08/22/08 Removed support for static interrupt handlers from the MDD
-* file
-* 3.00a sv 11/21/09 Updated to use HAL Processor APIs.
-* Renamed the macros XGpio_mWriteReg to XGpio_WriteReg and
-* XGpio_mReadReg to XGpio_ReadReg. Removed the macros
-* XGpio_mSetDataDirection, XGpio_mGetDataReg and
-* XGpio_mSetDataReg. Users should use XGpio_WriteReg and
-* XGpio_ReadReg to achieve the same functionality.
-* 3.01a bss 04/18/13 Updated driver tcl to generate Canonical params in
-* xparameters.h. CR#698589
-* 4.0 adk 19/12/13 Updated as per the New Tcl API's
-* 4.1 lks 11/18/15 Updated to use canonical xparameters in examples and
-* clean up of the comments, removed support for DCR bridge
-* and removed xgpio_intr_example for CR 900381
-* 4.2 sk 08/16/16 Used UINTPTR instead of u32 for Baseaddress as part of
-* adding 64 bit support. CR# 867425.
-* Changed the prototype of XGpio_CfgInitialize API.
-* 4.3 sk 09/29/16 Modified the example to make it work when LED_bits are
-* configured as an output. CR# 958644
-* ms 01/23/17 Added xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 4.4 sne 04/25/19 Updated Makefile for IAR compier (CR-1029421).
-* 4.5 sne 06/14/19 Fixed IAR compiler warnings on example files.
-* 4.6 sne 08/11/19 Fixed compilation error of armcc compiler.
-* 4.7 sne 08/28/20 Modify Makefile to support parallel make execution.
-* 4.8 sne 02/10/21 Fixed doxygen warnings.
-*
-*
-*****************************************************************************/
-
-#ifndef XGPIO_H /* prevent circular inclusions */
-#define XGPIO_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xgpio_l.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- UINTPTR BaseAddress; /**< Device base address */
- int InterruptPresent; /**< Are interrupts supported in h/w */
- int IsDual; /**< Are 2 channels supported in h/w */
-} XGpio_Config;
-
-/**
- * The XGpio driver instance data. The user is required to allocate a
- * variable of this type for every GPIO device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- UINTPTR BaseAddress; /**< Device base address */
- u32 IsReady; /**< Device is initialized and ready */
- int InterruptPresent; /**< Are interrupts supported in h/w */
- int IsDual; /**< Are 2 channels supported in h/w */
-} XGpio;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Function Prototypes *****************************/
-
-/*
- * Initialization functions in xgpio_sinit.c
- */
-int XGpio_Initialize(XGpio *InstancePtr, u16 DeviceId);
-XGpio_Config *XGpio_LookupConfig(u16 DeviceId);
-
-/*
- * API Basic functions implemented in xgpio.c
- */
-int XGpio_CfgInitialize(XGpio *InstancePtr, XGpio_Config * Config,
- UINTPTR EffectiveAddr);
-void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
- u32 DirectionMask);
-u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel);
-u32 XGpio_DiscreteRead(XGpio *InstancePtr, unsigned Channel);
-void XGpio_DiscreteWrite(XGpio *InstancePtr, unsigned Channel, u32 Mask);
-
-
-/*
- * API Functions implemented in xgpio_extra.c
- */
-void XGpio_DiscreteSet(XGpio *InstancePtr, unsigned Channel, u32 Mask);
-void XGpio_DiscreteClear(XGpio *InstancePtr, unsigned Channel, u32 Mask);
-
-/*
- * API Functions implemented in xgpio_selftest.c
- */
-int XGpio_SelfTest(XGpio *InstancePtr);
-
-/*
- * API Functions implemented in xgpio_intr.c
- */
-void XGpio_InterruptGlobalEnable(XGpio *InstancePtr);
-void XGpio_InterruptGlobalDisable(XGpio *InstancePtr);
-void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask);
-void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask);
-void XGpio_InterruptClear(XGpio *InstancePtr, u32 Mask);
-u32 XGpio_InterruptGetEnabled(XGpio *InstancePtr);
-u32 XGpio_InterruptGetStatus(XGpio *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/af/11d828565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/af/11d828565243001d18b399c1eb9b3628
deleted file mode 100644
index f233224..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/af/11d828565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,552 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.c
-*
-* Contains required functions for the ARM cache functionality.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.00 pkp 02/20/14 First release
-* 6.2 mus 01/27/17 Updated to support IAR compiler
-* 7.3 dp 06/25/20 Updated to support armclang compiler
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xil_io.h"
-#include "xpseudo_asm.h"
-#include "xparameters.h"
-#include "xreg_cortexr5.h"
-#include "xil_exception.h"
-
-
-/************************** Variable Definitions *****************************/
-
-#define IRQ_FIQ_MASK 0xC0 /* Mask IRQ and FIQ interrupts in cpsr */
-
-#if defined (__clang__)
-extern s32 Image$$ARM_LIB_STACK$$Limit;
-extern s32 Image$$ARM_UNDEF_STACK$$Base;
-#elif defined (__GNUC__)
-extern s32 _stack_end;
-extern s32 __undef_stack;
-#endif
-
-/****************************************************************************/
-/************************** Function Prototypes ******************************/
-
-/****************************************************************************/
-/**
-* @brief Enable the Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheEnable(void)
-{
- register u32 CtrlReg;
-
- /* enable caches only if they are disabled */
-#if defined (__GNUC__)
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
-#endif
- if ((CtrlReg & XREG_CP15_CONTROL_C_BIT)==0x00000000U) {
- /* invalidate the Data cache */
- Xil_DCacheInvalidate();
-
- /* enable the Data cache */
- CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- }
-}
-
-/****************************************************************************/
-/**
-* @brief Disable the Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheDisable(void)
-{
- register u32 CtrlReg;
-
- /* clean and invalidate the Data cache */
- Xil_DCacheFlush();
-
- /* disable the Data cache */
-#if defined (__GNUC__)
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
-#endif
-
- CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the entire Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheInvalidate(void)
-{
- u32 currmask;
- u32 stack_start,stack_end,stack_size;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
-#if defined (__clang__)
- stack_end = (u32 )&Image$$ARM_LIB_STACK$$Limit;
- stack_start = (u32 )&Image$$ARM_UNDEF_STACK$$Base;
-#elif defined (__GNUC__)
- stack_end = (u32 )&_stack_end;
- stack_start = (u32 )&__undef_stack;
-#endif
-
-#if defined(__GNUC__) || defined(__clang__)
- stack_size = stack_start-stack_end;
-
- /* Flush stack memory to save return address */
- Xil_DCacheFlushRange(stack_end, stack_size);
-#endif
-
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
-
- /*invalidate all D cache*/
- mtcp(XREG_CP15_INVAL_DC_ALL, 0);
-
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate a Data cache line. If the byte specified by the
-* address (adr) is cached by the data cache, the cacheline
-* containing that byte is invalidated.If the cacheline is modified
-* (dirty), the modified contents are lost and are NOT written
-* to system memory before the line is invalidated.
-*
-*
-* @param adr: 32bit address of the data to be flushed.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_DCacheInvalidateLine(INTPTR adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
- mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
-
- /* Wait for invalidate to complete */
- dsb();
-
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the Data cache for the given address range.
-* If the bytes specified by the address (adr) are cached by the
-* Data cache,the cacheline containing that byte is invalidated.
-* If the cacheline is modified (dirty), the modified contents are
-* lost and are NOT written to system memory before the line is
-* invalidated.
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
-{
- const u32 cacheline = 32U;
- u32 end;
- u32 tempadr = adr;
- u32 tempend;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- end = tempadr + len;
- tempend = end;
- /* Select L1 Data cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
-
- if ((tempadr & (cacheline-1U)) != 0U) {
- tempadr &= (~(cacheline - 1U));
-
- Xil_DCacheFlushLine(tempadr);
- }
- if ((tempend & (cacheline-1U)) != 0U) {
- tempend &= (~(cacheline - 1U));
-
- Xil_DCacheFlushLine(tempend);
- }
-
- while (tempadr < tempend) {
-
- /* Invalidate Data cache line */
- asm_inval_dc_line_mva_poc(tempadr);
-
- tempadr += cacheline;
- }
- }
-
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the entire Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheFlush(void)
-{
- register u32 CsidReg, C7Reg;
- u32 CacheSize, LineSize, NumWays;
- u32 Way, WayIndex, Set, SetIndex, NumSet;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- /* Select cache level 0 and D cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
-
-#if defined (__GNUC__)
- CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_CACHE_SIZE_ID,CsidReg);
-#endif
- /* Determine Cache Size */
-
- CacheSize = (CsidReg >> 13U) & 0x000001FFU;
- CacheSize += 0x00000001U;
- CacheSize *= (u32)128; /* to get number of bytes */
-
- /* Number of Ways */
- NumWays = (CsidReg & 0x000003ffU) >> 3U;
- NumWays += 0x00000001U;
-
- /* Get the cacheline size, way size, index size from csidr */
- LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
-
- NumSet = CacheSize/NumWays;
- NumSet /= (0x00000001U << LineSize);
-
- Way = 0U;
- Set = 0U;
-
- /* Invalidate all the cachelines */
- for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set;
- /* Flush by Set/Way */
- asm_clean_inval_dc_line_sw(C7Reg);
-
- Set += (0x00000001U << LineSize);
- }
- Set = 0U;
- Way += 0x40000000U;
- }
-
- /* Wait for flush to complete */
- dsb();
- mtcpsr(currmask);
-
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush a Data cache line. If the byte specified by the address (adr)
-* is cached by the Data cache, the cacheline containing that byte is
-* invalidated. If the cacheline is modified (dirty), the entire
-* contents of the cacheline are written to system memory before the
-* line is invalidated.
-*
-* @param adr: 32bit address of the data to be flushed.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_DCacheFlushLine(INTPTR adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
-
- mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
-
- /* Wait for flush to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the Data cache for the given address range.
-* If the bytes specified by the address (adr) are cached by the
-* Data cache, the cacheline containing those bytes is invalidated.If
-* the cacheline is modified (dirty), the written to system memory
-* before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be flushed.
-* @param len: Length of the range to be flushed in bytes
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheFlushRange(INTPTR adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0x00000000U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr &= ~(cacheline - 1U);
-
- while (LocalAddr < end) {
- /* Flush Data cache line */
- asm_clean_inval_dc_line_mva_poc(LocalAddr);
-
- LocalAddr += cacheline;
- }
- }
- dsb();
- mtcpsr(currmask);
-}
-/****************************************************************************/
-/**
-* @brief Store a Data cache line. If the byte specified by the address
-* (adr) is cached by the Data cache and the cacheline is modified
-* (dirty), the entire contents of the cacheline are written to
-* system memory.After the store completes, the cacheline is marked
-* as unmodified (not dirty).
-*
-* @param adr: 32bit address of the data to be stored
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_DCacheStoreLine(INTPTR adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
- mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1F)));
-
- /* Wait for store to complete */
- dsb();
- isb();
-
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Enable the instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ICacheEnable(void)
-{
- register u32 CtrlReg;
-
- /* enable caches only if they are disabled */
-#if defined (__GNUC__)
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-#endif
- if ((CtrlReg & XREG_CP15_CONTROL_I_BIT)==0x00000000U) {
- /* invalidate the instruction cache */
- mtcp(XREG_CP15_INVAL_IC_POU, 0);
-
- /* enable the instruction cache */
- CtrlReg |= (XREG_CP15_CONTROL_I_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- }
-}
-
-/****************************************************************************/
-/**
-* @brief Disable the instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ICacheDisable(void)
-{
- register u32 CtrlReg;
-
- dsb();
-
- /* invalidate the instruction cache */
- mtcp(XREG_CP15_INVAL_IC_POU, 0);
-
- /* disable the instruction cache */
-#if defined (__GNUC__)
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
-#endif
-
- CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the entire instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ICacheInvalidate(void)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1);
-
- /* invalidate the instruction cache */
- mtcp(XREG_CP15_INVAL_IC_POU, 0);
-
- /* Wait for invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate an instruction cache line.If the instruction specified
-* by the address is cached by the instruction cache, the
-* cacheline containing that instruction is invalidated.
-*
-* @param adr: 32bit address of the instruction to be invalidated.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_ICacheInvalidateLine(INTPTR adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1);
- mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1F)));
-
- /* Wait for invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the instruction cache for the given address range.
-* If the bytes specified by the address (adr) are cached by the
-* Data cache, the cacheline containing that byte is invalidated.
-* If the cachelineis modified (dirty), the modified contents are
-* lost and are NOT written to system memory before the line is
-* invalidated.
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- if (len != 0x00000000U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Select cache L0 I-cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
-
- while (LocalAddr < end) {
-
- /* Invalidate L1 I-cache line */
- asm_inval_ic_line_mva_pou(LocalAddr);
-
- LocalAddr += cacheline;
- }
- }
-
- /* Wait for invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/af/249490595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/af/249490595243001d18b399c1eb9b3628
deleted file mode 100644
index 90efcf4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/af/249490595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,23 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#include
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) clock_t clock(void);
-}
-#endif
-/*
- * clock -- It supposed to return processor time. We are not implementing
- * this function, as timekeeping is tightly coupled with system, hence
- * always returning 0. Users can override this with their system
- * specific implementation.
- *
- */
-__attribute__((weak)) clock_t clock(void)
-{
- return (0);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/af/6156f6555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/af/6156f6555243001d18b399c1eb9b3628
deleted file mode 100644
index 75cd6f6..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/af/6156f6555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,105 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.h
-*
-* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions
-*
-* Cache functions provide access to cache related operations such as flush
-* and invalidate for instruction and data caches. It gives option to perform
-* the cache operations on a single cacheline, a range of memory and an entire
-* cache.
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 01/29/10 First release
-* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
-* APIs.
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 02/04/02 First release
-* 2.00a jhl 12/16/02 Update for dual channel and interrupt support
-* 2.01a jvb 12/13/05 Changed Initialize() into CfgInitialize(), and made
-* CfgInitialize() take a pointer to a config structure
-* instead of a device id. Moved Initialize() into
-* xgpio_sinit.c, and had Initialize() call CfgInitialize()
-* after it retrieved the config structure using the device
-* id. Removed include of xparameters.h along with any
-* dependencies on xparameters.h and the _g.c config table.
-* 2.11a mta 03/21/07 Updated to new coding style, added GetDataDirection
-* 2.12a sv 11/21/07 Updated driver to support access through DCR bus
-* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the
-* macros to remove _m from the name.
-* 4.1 lks 11/18/15 Clean up of the comments in the code and
-* removed support for DCR bridge
-* 4.2 sk 08/16/16 Used UINTPTR instead of u32 for Baseaddress as part of
-* adding 64 bit support. CR# 867425.
-* Changed the prototype of XGpio_CfgInitialize API.
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xgpio.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-
-/************************** Function Prototypes *****************************/
-
-
-/****************************************************************************/
-/**
-* Initialize the XGpio instance provided by the caller based on the
-* given configuration data.
-*
-* Nothing is done except to initialize the InstancePtr.
-*
-* @param InstancePtr is a pointer to an XGpio instance. The memory the
-* pointer references must be pre-allocated by the caller. Further
-* calls to manipulate the driver through the XGpio API must be
-* made with this pointer.
-* @param Config is a reference to a structure containing information
-* about a specific GPIO device. This function initializes an
-* InstancePtr object for a specific device specified by the
-* contents of Config. This function can initialize multiple
-* instance objects with the use of multiple calls giving different
-* Config information on each call.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. The caller is responsible for keeping the address
-* mapping from EffectiveAddr to the device physical base address
-* unchanged once this function is invoked. Unexpected errors may
-* occur if the address mapping changes after this function is
-* called. If address translation is not used, use
-* Config->BaseAddress for this parameters, passing the physical
-* address instead.
-*
-* @return
-* - XST_SUCCESS if the initialization is successful.
-*
-* @note None.
-*
-*****************************************************************************/
-int XGpio_CfgInitialize(XGpio * InstancePtr, XGpio_Config * Config,
- UINTPTR EffectiveAddr)
-{
- /* Assert arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /* Set some default values. */
- InstancePtr->BaseAddress = EffectiveAddr;
-
- InstancePtr->InterruptPresent = Config->InterruptPresent;
- InstancePtr->IsDual = Config->IsDual;
-
- /*
- * Indicate the instance is now ready to use, initialized without error
- */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
- return (XST_SUCCESS);
-}
-
-
-/****************************************************************************/
-/**
-* Set the input/output direction of all discrete signals for the specified
-* GPIO channel.
-*
-* @param InstancePtr is a pointer to an XGpio instance to be worked on.
-* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
-* @param DirectionMask is a bitmask specifying which discretes are input
-* and which are output. Bits set to 0 are output and bits set to 1
-* are input.
-*
-* @return None.
-*
-* @note The hardware must be built for dual channels if this function
-* is used with any channel other than 1. If it is not, this
-* function will assert.
-*
-*****************************************************************************/
-void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
- u32 DirectionMask)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((Channel == 1) ||
- ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
-
- XGpio_WriteReg(InstancePtr->BaseAddress,
- ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_TRI_OFFSET,
- DirectionMask);
-}
-
-/****************************************************************************/
-/**
-* Get the input/output direction of all discrete signals for the specified
-* GPIO channel.
-*
-* @param InstancePtr is a pointer to an XGpio instance to be worked on.
-* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
-*
-* @return Bitmask specifying which discretes are input and
-* which are output. Bits set to 0 are output and bits set to 1 are
-* input.
-*
-* @note
-*
-* The hardware must be built for dual channels if this function is used
-* with any channel other than 1. If it is not, this function will assert.
-*
-*****************************************************************************/
-u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((Channel == 1) ||
- ((Channel == 2) &&
- (InstancePtr->IsDual == TRUE)));
-
- return XGpio_ReadReg(InstancePtr->BaseAddress,
- ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_TRI_OFFSET);
-}
-
-/****************************************************************************/
-/**
-* Read state of discretes for the specified GPIO channel.
-*
-* @param InstancePtr is a pointer to an XGpio instance to be worked on.
-* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
-*
-* @return Current copy of the discretes register.
-*
-* @note The hardware must be built for dual channels if this function
-* is used with any channel other than 1. If it is not, this
-* function will assert.
-*
-*****************************************************************************/
-u32 XGpio_DiscreteRead(XGpio * InstancePtr, unsigned Channel)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((Channel == 1) ||
- ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
-
- return XGpio_ReadReg(InstancePtr->BaseAddress,
- ((Channel - 1) * XGPIO_CHAN_OFFSET) +
- XGPIO_DATA_OFFSET);
-}
-
-/****************************************************************************/
-/**
-* Write to discretes register for the specified GPIO channel.
-*
-* @param InstancePtr is a pointer to an XGpio instance to be worked on.
-* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
-* @param Data is the value to be written to the discretes register.
-*
-* @return None.
-*
-* @note The hardware must be built for dual channels if this function
-* is used with any channel other than 1. If it is not, this
-* function will assert. See also XGpio_DiscreteSet() and
-* XGpio_DiscreteClear().
-*
-*****************************************************************************/
-void XGpio_DiscreteWrite(XGpio * InstancePtr, unsigned Channel, u32 Data)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((Channel == 1) ||
- ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
-
- XGpio_WriteReg(InstancePtr->BaseAddress,
- ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET,
- Data);
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/af/c25688595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/af/c25688595243001d18b399c1eb9b3628
deleted file mode 100644
index 27b3df1..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/af/c25688595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,105 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#ifndef PROFILE_H
-#define PROFILE_H 1
-
-#include
-#include "xil_types.h"
-#include "profile_config.h"
-
-#ifdef PROC_MICROBLAZE
-#include "mblaze_nt_types.h"
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void _system_init( void ) ;
-void _system_clean( void ) ;
-void mcount(u32 frompc, u32 selfpc);
-void profile_intr_handler( void ) ;
-void _profile_init( void );
-
-
-
-/****************************************************************************
- * Profiling on hardware - Hash table maintained on hardware and data sent
- * to xmd for gmon.out generation.
- ****************************************************************************/
-/*
- * histogram counters are unsigned shorts (according to the kernel).
- */
-#define HISTCOUNTER u16
-
-struct tostruct {
- u32 selfpc;
- s32 count;
- s16 link;
- u16 pad;
-};
-
-struct fromstruct {
- u32 frompc ;
- s16 link ;
- u16 pad ;
-} ;
-
-/*
- * general rounding functions.
- */
-#define ROUNDDOWN(x,y) (((x)/(y))*(y))
-#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y))
-
-/*
- * The profiling data structures are housed in this structure.
- */
-struct gmonparam {
- s32 state;
-
- /* Histogram Information */
- u16 *kcount; /* No. of bins in histogram */
- u32 kcountsize; /* Histogram samples */
-
- /* Call-graph Information */
- struct fromstruct *froms;
- u32 fromssize;
- struct tostruct *tos;
- u32 tossize;
-
- /* Initialization I/Ps */
- u32 lowpc;
- u32 highpc;
- u32 textsize;
- /* u32 cg_froms, */
- /* u32 cg_tos, */
-};
-extern struct gmonparam *_gmonparam;
-extern s32 n_gmon_sections;
-
-/*
- * Possible states of profiling.
- */
-#define GMON_PROF_ON 0
-#define GMON_PROF_BUSY 1
-#define GMON_PROF_ERROR 2
-#define GMON_PROF_OFF 3
-
-/*
- * Sysctl definitions for extracting profiling information from the kernel.
- */
-#define GPROF_STATE 0 /* int: profiling enabling variable */
-#define GPROF_COUNT 1 /* struct: profile tick count buffer */
-#define GPROF_FROMS 2 /* struct: from location hash bucket */
-#define GPROF_TOS 3 /* struct: destination/count structure */
-#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PROFILE_H */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/af/d2a4c0595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/af/d2a4c0595243001d18b399c1eb9b3628
deleted file mode 100644
index 2a4fff2..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/af/d2a4c0595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,573 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xreg_cortexa9.h
-*
-* This header file contains definitions for using inline assembler code. It is
-* written specifically for the GNU, ARMCC compiler.
-*
-* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
-* with the positions of the bits within the registers.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm 10/20/09 First release
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 11/03/09 Initial release.
-* 4.2 pkp 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
-* as smc.c is removed
-*
-*
-* @note None.
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef SMC_H /* prevent circular inclusions */
-#define SMC_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xparameters.h"
-#include "xil_io.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/* Memory controller configuration register offset */
-#define XSMCPSS_MC_STATUS 0x000U /* Controller status reg, RO */
-#define XSMCPSS_MC_INTERFACE_CONFIG 0x004U /* Interface config reg, RO */
-#define XSMCPSS_MC_SET_CONFIG 0x008U /* Set configuration reg, WO */
-#define XSMCPSS_MC_CLR_CONFIG 0x00CU /* Clear config reg, WO */
-#define XSMCPSS_MC_DIRECT_CMD 0x010U /* Direct command reg, WO */
-#define XSMCPSS_MC_SET_CYCLES 0x014U /* Set cycles register, WO */
-#define XSMCPSS_MC_SET_OPMODE 0x018U /* Set opmode register, WO */
-#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020U /* Refresh period_0 reg, RW */
-#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024U /* Refresh period_1 reg, RW */
-
-/* Chip select configuration register offset */
-#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100U /* Interface 0 chip 0 config */
-#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120U /* Interface 0 chip 1 config */
-#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140U /* Interface 0 chip 2 config */
-#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160U /* Interface 0 chip 3 config */
-#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180U /* Interface 1 chip 0 config */
-#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0U /* Interface 1 chip 1 config */
-#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0U /* Interface 1 chip 2 config */
-#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0U /* Interface 1 chip 3 config */
-
-/* User configuration register offset */
-#define XSMCPSS_UC_STATUS_OFFSET 0x200U /* User status reg, RO */
-#define XSMCPSS_UC_CONFIG_OFFSET 0x204U /* User config reg, WO */
-
-/* Integration test register offset */
-#define XSMCPSS_IT_OFFSET 0xE00U
-
-/* ID configuration register offset */
-#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0U
-#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4U
-#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8U
-#define XSMCPSS_ID_PERIP_3_OFFSET 0xFECU
-#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0U
-#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4U
-#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8U
-#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFCU
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* SMC_H */
-
-/**
- *@endcond
- */
\ No newline at end of file
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b/a07919575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b/a07919575243001d18b399c1eb9b3628
deleted file mode 100644
index 0e49078..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b/a07919575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,31 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 2021.2
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2022 Xilinx, Inc. All Rights Reserved.
-* SPDX-License-Identifier: MIT
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xusbps.h"
-
-/*
-* The configuration table for devices
-*/
-
-XUsbPs_Config XUsbPs_ConfigTable[XPAR_XUSBPS_NUM_INSTANCES] =
-{
- {
- XPAR_PS7_USB_0_DEVICE_ID,
- XPAR_PS7_USB_0_BASEADDR
- }
-};
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b/e154c5585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b/e154c5585243001d18b399c1eb9b3628
deleted file mode 100644
index 6719ab0..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b/e154c5585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,62 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file vectors.h
-*
-* This file contains the C level vector prototypes for the ARM Cortex A9 core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 10/20/10 Initial version, moved over from bsp area
-* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 First release.
-* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration.
-* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype
-* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
-* to 0x1fff. This fixes the CR#744902.
-* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
-* 3.0 kvn 12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
-* XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
-* 3.0 kpc 1/23/15 Corrected the extended descriptor macro values.
-* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.0 hk 03/18/15 Added support for jumbo frames.
-* Remove "used bit set" from TX error interrupt masks.
-* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
-* 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
-* 3.8 hk 09/17/18 Fix PTP interrupt masks.
-* 3.9 hk 01/23/19 Add RX watermark support
-* 3.10 hk 05/16/19 Clear status registers properly in reset
-*
-*
-******************************************************************************/
-
-#ifndef XEMACPS_HW_H /* prevent circular inclusions */
-#define XEMACPS_HW_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address
- supported */
-#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */
-
-#ifdef __aarch64__
-#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment
- on the local bus */
-#else
-
-#define XEMACPS_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment
- on the local bus */
-#endif
-#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using
- options that impose alignment
- restrictions on the buffer data on
- the local bus */
-
-/** @name Direction identifiers
- *
- * These are used by several functions and callbacks that need
- * to specify whether an operation specifies a send or receive channel.
- * @{
- */
-#define XEMACPS_SEND 1U /**< send direction */
-#define XEMACPS_RECV 2U /**< receive direction */
-/*@}*/
-
-/** @name MDC clock division
- * currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
- * @{
- */
-typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
- MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
-} XEmacPs_MdcDiv;
-
-/*@}*/
-
-#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
- bytes, 64, 128, ... 10240 */
-#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
-
-#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a
- unit, this is HW setup */
-
-#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */
-#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */
-
-#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
-
-/* Register offset definitions. Unless otherwise noted, register access is
- * 32 bit. Names are self explained here.
- */
-
-#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */
-#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */
-#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */
-
-#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */
-#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */
-#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */
-#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */
-#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */
-
-#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */
-#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */
-#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */
-#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */
-
-#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */
-#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */
-#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */
-
-#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */
-
-#define XEMACPS_RXWATERMARK_OFFSET 0x0000007CU /**< RX watermark reg */
-
-#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */
-#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */
-
-#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */
-#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */
-#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */
-#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */
-#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */
-#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */
-#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */
-#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */
-
-#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */
-#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */
-#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */
-#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */
-
-#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */
-
-#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low
- reg */
-#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High
- reg */
-
-#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes
- transmitted counter */
-#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast
- Frames counter*/
-#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast
- Frame counter */
-#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted
- Counter */
-#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames
- Transmitted counter */
-#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte
- Frames Transmitted
- counter */
-#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte
- Frames Transmitted
- counter*/
-#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte
- Frames transmitted
- counter */
-#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte
- Frames transmitted
- counter */
-#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte
- Frames transmitted
- counter */
-#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than
- 1519 byte Frames
- transmitted counter */
-#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error
- counter */
-
-#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame
- Counter */
-#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame
- Counter */
-#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
- Counter */
-#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame
- Counter */
-#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission
- Frame Counter */
-#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense
- Error Counter */
-
-#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register
- Low */
-#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register
- High */
-
-#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames
- Received Counter */
-#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast
- Frames Received Counter */
-#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast
- Frames Received Counter */
-#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames
- Received Counter */
-#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames
- Received Counter */
-#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte
- Frames Received Counter */
-#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte
- Frames Received Counter */
-#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte
- Frames Received Counter */
-#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte
- Frames Received Counter */
-#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte
- Frames Received Counter */
-#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte
- Frames Received Counter */
-#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received
- Counter */
-#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received
- Counter */
-#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received
- Counter */
-#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence
- Error Counter */
-#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error
- Counter */
-#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */
-#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */
-#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error
- Counter */
-#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */
-#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error
- Counter */
-#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error
- Counter */
-#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error
- Counter */
-#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter
- offset, for clearing */
-
-#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */
-#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */
-#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond
- adjustment counter */
-#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond
- increment counter */
-#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second
- counter */
-#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
- nanosecond counter */
-#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second
- counter */
-#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
- nanosecond counter */
-#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit
- second counter */
-#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
- nanosecond counter */
-#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive
- second counter */
-#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
- nanosecond counter */
-
-#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status
- reg */
-#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address
- reg */
-#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address
- reg */
-#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base
- reg */
-#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base
- reg */
-#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable
- reg */
-#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable
- reg */
-#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask
- reg */
-
-/* Define some bit positions for registers. */
-
-/** @name network control register bit definitions
- * @{
- */
-#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from
- Rx SRAM */
-#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
- pause frame */
-#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */
-#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission
- after current frame */
-#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */
-
-#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to
- stat counters */
-#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic
- registers */
-#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic
- registers */
-#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */
-#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */
-#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */
-#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */
-/*@}*/
-
-/** @name network configuration register bit definitions
- * @{
- */
-#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
- non-standard preamble */
-#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */
-#define XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U /**< SGMII Enable */
-#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of
- FCS error */
-#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */
-#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum
- offload */
-#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
- Frames to memory */
-#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */
-#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */
-#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */
-#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from
- received frames */
-#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
-/**< RX length error discard */
-#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */
-#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */
-#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
-#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
-/**< External address match enable */
-#define XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U /**< PCS Select */
-#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */
-#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte
- frames reception */
-#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
- frames */
-#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
- frames */
-#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive
- broadcast frames */
-#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */
-#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */
-#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN
- frames */
-#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */
-#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */
-#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */
-/*@}*/
-
-/** @name network status register bit definitaions
- * @{
- */
-#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */
-#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */
-/*@}*/
-
-
-/** @name MAC address register word 1 mask
- * @{
- */
-#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32]
- bit[31:0] are in BOTTOM */
-/*@}*/
-
-
-/** @name DMA control register bit definitions
- * @{
- */
-#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */
-#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */
-#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */
-#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer
- size */
-#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer
- size */
-#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX
- checksum offload */
-#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */
-#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */
-#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */
-#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */
-#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */
-#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */
-#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */
-#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */
-/*@}*/
-
-/** @name transmit status register bit definitions
- * @{
- */
-#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */
-#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */
-#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */
-#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted
- mid frame */
-#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */
-#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */
-#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */
-#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */
-
-#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
- (u32)XEMACPS_TXSR_URUN_MASK | \
- (u32)XEMACPS_TXSR_BUFEXH_MASK | \
- (u32)XEMACPS_TXSR_RXOVR_MASK | \
- (u32)XEMACPS_TXSR_FRAMERX_MASK | \
- (u32)XEMACPS_TXSR_USEDREAD_MASK)
-/*@}*/
-
-/**
- * @name receive status register bit definitions
- * @{
- */
-#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */
-#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */
-#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */
-#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */
-
-#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
- (u32)XEMACPS_RXSR_RXOVR_MASK | \
- (u32)XEMACPS_RXSR_BUFFNA_MASK)
-
-#define XEMACPS_SR_ALL_MASK 0xFFFFFFFFU /**< Mask for full register */
-
-/*@}*/
-
-/**
- * @name Interrupt Q1 status register bit definitions
- * @{
- */
-#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */
-#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */
-
-#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
- (u32)XEMACPS_INTQ1SR_TXERR_MASK)
-
-/*@}*/
-
-/**
- * @name interrupts bit definitions
- * Bits definitions are same in XEMACPS_ISR_OFFSET,
- * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
- * @{
- */
-#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Pdelay_resp TXed */
-#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req TXed */
-#define XEMACPS_IXR_PTPPSRX_MASK 0x00800000U /**< PTP Pdelay_resp RXed */
-#define XEMACPS_IXR_PTPPDRRX_MASK 0x00400000U /**< PTP Pdelay_req RXed */
-
-#define XEMACPS_IXR_PTPSTX_MASK 0x00200000U /**< PTP Sync TXed */
-#define XEMACPS_IXR_PTPDRTX_MASK 0x00100000U /**< PTP Delay_req TXed */
-#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync RXed */
-#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req RXed */
-
-#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */
-#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached
- zero */
-#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
-#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */
-#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */
-#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */
-#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or
- no buffers*/
-#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */
-#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */
-#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */
-#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */
-#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */
-#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */
-#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */
-
-#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \
- (u32)XEMACPS_IXR_RETRY_MASK | \
- (u32)XEMACPS_IXR_URUN_MASK)
-
-
-#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \
- (u32)XEMACPS_IXR_RXUSED_MASK | \
- (u32)XEMACPS_IXR_RXOVR_MASK)
-
-/*@}*/
-
-/** @name PHY Maintenance bit definitions
- * @{
- */
-#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */
-#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */
-#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */
-#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */
-#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */
-#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */
-#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */
-#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */
-/*@}*/
-
-/** @name RX watermark bit definitions
- * @{
- */
-#define XEMACPS_RXWM_HIGH_MASK 0x0000FFFFU /**< RXWM high mask */
-#define XEMACPS_RXWM_LOW_MASK 0xFFFF0000U /**< RXWM low mask */
-#define XEMACPS_RXWM_LOW_SHFT_MSK 16U /**< Shift for RXWM low */
-/*@}*/
-
-/* Transmit buffer descriptor status words offset
- * @{
- */
-#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */
-#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */
-#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */
-
-/*
- * @}
- */
-
-/* Transmit buffer descriptor status words bit positions.
- * Transmit buffer descriptor consists of two 32-bit registers,
- * the first - word0 contains a 32-bit address pointing to the location of
- * the transmit data.
- * The following register - word1, consists of various information to control
- * the XEmacPs transmit process. After transmit, this is updated with status
- * information, whether the frame was transmitted OK or why it had failed.
- * @{
- */
-#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */
-#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */
-#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
-#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */
-#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */
-#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */
-#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
-#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */
-#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */
-/*
- * @}
- */
-
-/* Receive buffer descriptor status words bit positions.
- * Receive buffer descriptor consists of two 32-bit registers,
- * the first - word0 contains a 32-bit word aligned address pointing to the
- * address of the buffer. The lower two bits make up the wrap bit indicating
- * the last descriptor and the ownership bit to indicate it has been used by
- * the XEmacPs.
- * The following register - word1, contains status information regarding why
- * the frame was received (the filter match condition) as well as other
- * useful info.
- * @{
- */
-#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */
-#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
-#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */
-#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */
-#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address
- matched */
-#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */
-#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */
-#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */
-#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */
-#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */
-#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */
-#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */
-#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */
-#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */
-#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
-
-#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */
-#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */
-#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */
-/*
- * @}
- */
-
-/*
- * Define appropriate I/O access method to memory mapped I/O or other
- * interface if necessary.
- */
-
-#define XEmacPs_In32 Xil_In32
-#define XEmacPs_Out32 Xil_Out32
-
-
-/****************************************************************************/
-/**
-*
-* Read the given register.
-*
-* @param BaseAddress is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
- XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
-
-
-/****************************************************************************/
-/**
-*
-* Write the given register.
-*
-* @param BaseAddress is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
-* u32 Data)
-*
-*****************************************************************************/
-#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
- XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
-
-/************************** Function Prototypes *****************************/
-/*
- * Perform reset operation to the emacps interface
- */
-void XEmacPs_ResetHw(u32 BaseAddr);
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b0/e0f55a545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b0/e0f55a545243001d18b399c1eb9b3628
deleted file mode 100644
index ce4b290..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b0/e0f55a545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,597 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xscugic.h
-* @addtogroup scugic_v4_6
-* @{
-* @details
-*
-* The generic interrupt controller driver component.
-*
-* The interrupt controller driver uses the idea of priority for the various
-* handlers. Priority is an integer within the range of 1 and 31 inclusive with
-* default of 1 being the highest priority interrupt source. The priorities
-* of the various sources can be dynamically altered as needed through
-* hardware configuration.
-*
-* The generic interrupt controller supports the following
-* features:
-*
-* - specific individual interrupt enabling/disabling
-* - specific individual interrupt acknowledging
-* - attaching specific callback function to handle interrupt source
-* - assigning desired priority to interrupt source if default is not
-* acceptable.
-*
-* Details about connecting the interrupt handler of the driver are contained
-* in the source file specific to interrupt processing, xscugic_intr.c.
-*
-* This driver is intended to be RTOS and processor independent. It works with
-* physical addresses only. Any needs for dynamic memory management, threads
-* or thread mutual exclusion, virtual memory, or cache control must be
-* satisfied by the layer above this driver.
-*
-* Interrupt Vector Tables
-*
-* The device ID of the interrupt controller device is used by the driver as a
-* direct index into the configuration data table. The user should populate the
-* vector table with handlers and callbacks at run-time using the
-* XScuGic_Connect() and XScuGic_Disconnect() functions.
-*
-* Each vector table entry corresponds to a device that can generate an
-* interrupt. Each entry contains an interrupt handler function and an
-* argument to be passed to the handler when an interrupt occurs. The
-* user must use XScuGic_Connect() when the interrupt handler takes an
-* argument other than the base address.
-*
-* Nested Interrupts Processing
-*
-* Nested interrupts are not supported by this driver.
-*
-* NOTE:
-* The generic interrupt controller is not a part of the snoop control unit
-* as indicated by the prefix "scu" in the name of the driver.
-* It is an independent module in APU.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------------
-* 1.00a drg 01/19/00 First release
-* 1.01a sdm 11/09/11 The XScuGic and XScuGic_Config structures have changed.
-* The HandlerTable (of type XScuGic_VectorTableEntry) is
-* moved to XScuGic_Config structure from XScuGic structure.
-*
-* The "Config" entry in XScuGic structure is made as
-* pointer for better efficiency.
-*
-* A new file named as xscugic_hw.c is now added. It is
-* to implement low level driver routines without using
-* any xscugic instance pointer. They are useful when the
-* user wants to use xscugic through device id or
-* base address. The driver routines provided are explained
-* below.
-* XScuGic_DeviceInitialize that takes device id as
-* argument and initializes the device (without calling
-* XScuGic_CfgInitialize).
-* XScuGic_DeviceInterruptHandler that takes device id
-* as argument and calls appropriate handlers from the
-* HandlerTable.
-* XScuGic_RegisterHandler that registers a new handler
-* by taking xscugic hardware base address as argument.
-* LookupConfigByBaseAddress is used to return the
-* corresponding config structure from XScuGic_ConfigTable
-* based on the scugic base address passed.
-* 1.02a sdm 12/20/11 Removed AckBeforeService from the XScuGic_Config
-* structure.
-* 1.03a srt 02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
-* *_hw.h
-* Added APIs
-* - XScuGic_SetPriTrigTypeByDistAddr()
-* - XScuGic_GetPriTrigTypeByDistAddr()
-* (CR 702687)
-* Added support to direct interrupts to the appropriate CPU. Earlier
-* interrupts were directed to CPU1 (hard coded). Now depending
-* upon the CPU selected by the user (xparameters.h), interrupts
-* will be directed to the relevant CPU. This fixes CR 699688.
-* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
-* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
-* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
-* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
-* This is fix for CR#705621.
-* 1.05a hk 06/26/13 Modified tcl to export external interrupts correctly to
-* xparameters.h. Fix for CR's 690505, 708928 & 719359.
-* 2.0 adk 12/10/13 Updated as per the New Tcl API's
-* 2.1 adk 25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.2 asa 02/29/16 Modified DistributorInit function for Zynq AMP case. The
-* distributor is left uninitialized for Zynq AMP. It is assumed
-* that the distributor will be initialized by Linux master. However
-* for CortexR5 case, the earlier code is left unchanged where the
-* the interrupt processor target registers in the distributor is
-* initialized with the corresponding CPU ID on which the application
-* built over the scugic driver runs.
-* These changes fix CR#937243.
-*
-* 3.4 asa 04/07/16 Created a new static function DoDistributorInit to simplify
-* the flow and avoid code duplication. Changes are made for
-* USE_AMP use case for R5. In a scenario (in R5 split mode) when
-* one R5 is operating with A53 in open amp config and other
-* R5 running baremetal app, the existing code
-* had the potential to stop the whole AMP solution to work (if
-* for some reason the R5 running the baremetal app tasked to
-* initialize the Distributor hangs or crashes before initializing).
-* Changes are made so that the R5 under AMP first checks if
-* the distributor is enabled or not and if not, it does the
-* standard Distributor initialization.
-* This fixes the CR#952962.
-* 3.6 ms 01/23/17 Modified xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* kvn 02/17/17 Add support for changing GIC CPU master at run time.
-* kvn 02/28/17 Make the CpuId as static variable and Added new
-* XScugiC_GetCpuId to access CpuId.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 3.7 ms 04/11/17 Modified tcl file to add suffix U for all macro
-* definitions of scugic in xparameters.h
-* 3.8 mus 07/05/17 Updated scugic.tcl to add support for interrupts connected
-* through util_reduced_vector IP(OR gate)
-* mus 07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize
-* the HandlerTable in XScuGic_ConfigTable to 0, it removes
-* the compilation warning in xscugic_g.c. Fix for CR#978736.
-* mus 07/25/17 Updated xdefine_gic_params proc to export correct canonical
-* definitions for pl to ps interrupts.Fix for CR#980534
-* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
-* XScuGic_InterruptUnmapFromCpu, These API's can be used
-* by applications to unmap specific/all interrupts from
-* target CPU.
-* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
-* 4.0 mus 11/22/18 Fixed bugs in software interrupt generation through
-* XScuGic_SoftwareIntr API
-* 4.1 asa 03/30/19 Made changes not to direct each interrupt to all
-* available CPUs by default. This was breaking AMP
-* behavior. Instead every time an interrupt enable
-* request is received, the interrupt was mapped to
-* the respective CPU. There were several other changes
-* made to implement this. This set of changes was to
-* fix CR-1024716.
-* 4.1 mus 06/19/19 Added API's XScuGic_MarkCoreAsleep and
-* XScuGic_MarkCoreAwake to mark processor core as
-* asleep or awake. Fix for CR#1027220.
-* 4.5 asa 03/07/21 Included a header file xil_spinlock.h to ensure that
-* GIC driver can use newly introduced spinlock
-* functionality.
-* 4.6 sk 08/05/21 Fix scugic misrac violations.
-*
-*
-*
-******************************************************************************/
-
-#ifndef XSCUGIC_H /* prevent circular inclusions */
-#define XSCUGIC_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xil_io.h"
-#include "xscugic_hw.h"
-#include "xil_exception.h"
-#include "xil_spinlock.h"
-
-/************************** Constant Definitions *****************************/
-
-#define EFUSE_STATUS_OFFSET 0x10
-#define EFUSE_STATUS_CPU_MASK 0x80
-
-#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
-#define ARMA9
-#endif
-
-#define XSCUGIC500_DCTLR_ARE_NS_ENABLE 0x20
-#define XSCUGIC500_DCTLR_ARE_S_ENABLE 0x10
-/**************************** Type Definitions *******************************/
-
-/* The following data type defines each entry in an interrupt vector table.
- * The callback reference is the base address of the interrupting device
- * for the low level driver and an instance pointer for the high level driver.
- */
-typedef struct
-{
- Xil_InterruptHandler Handler;
- void *CallBackRef;
-} XScuGic_VectorTableEntry;
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct
-{
- u16 DeviceId; /**< Unique ID of device */
- u32 CpuBaseAddress; /**< CPU Interface Register base address */
- u32 DistBaseAddress; /**< Distributor Register base address */
- XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
- Vector table of interrupt handlers */
-} XScuGic_Config;
-
-/**
- * The XScuGic driver instance data. The user is required to allocate a
- * variable of this type for every intc device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct
-{
- XScuGic_Config *Config; /**< Configuration table entry */
- u32 IsReady; /**< Device is initialized and ready */
- u32 UnhandledInterrupts; /**< Intc Statistics */
-} XScuGic;
-
-/************************** Variable Definitions *****************************/
-
-extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Write the given CPU Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
- ((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given CPU Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
- (XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given Distributor Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
- ((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given Distributor Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
-(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given ReDistributor Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_ReDistWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress)+ \
- XSCUGIC_RDIST_OFFSET, (RegOffset), ((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given ReDistributor Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_ReDistReadReg(InstancePtr, RegOffset) \
-(XScuGic_ReadReg((((InstancePtr)->Config->DistBaseAddress)+ \
-XSCUGIC_RDIST_OFFSET), (RegOffset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given ReDistributor SGI PPI Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_ReDistSGIPPIWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress)+ \
- XSCUGIC_RDIST_SGI_PPI_OFFSET, (RegOffset), ((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given ReDistributor SGI PPI Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_ReDistSGIPPIReadReg(InstancePtr, RegOffset) \
-(XScuGic_ReadReg((((InstancePtr)->Config->DistBaseAddress)+ \
- XSCUGIC_RDIST_SGI_PPI_OFFSET), (RegOffset)))
-
-/****************************************************************************/
-/**
-* This function enables system register interface for GIC CPU Interface
-*
-* @param value to be written
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_Enable_SystemReg_CPU_Interface_EL3() mtcp(S3_6_C12_C12_5, 0xF);
-#define XScuGic_Enable_SystemReg_CPU_Interface_EL1() mtcp(S3_0_C12_C12_5, 0xF);
-/****************************************************************************/
-/**
-* This function enables Grou0 interrupts
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_Enable_Group0_Interrupts() mtcp(S3_0_C12_C12_6,0x1);
-/****************************************************************************/
-/**
-* This function enables Group1 interrupts
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#if defined (__aarch64__)
-#if EL1_NONSECURE
-#define XScuGic_Enable_Group1_Interrupts() \
- mtcp (S3_0_C12_C12_7, 0x1 | mfcp(S3_0_C12_C12_7) );
-#else
-#define XScuGic_Enable_Group1_Interrupts() \
- mtcp (S3_6_C12_C12_7, 0x1 | mfcp(S3_6_C12_C12_7) );
-#endif
-#endif
-/****************************************************************************/
-/**
-* This function writes to ICC_SGI0R_EL1
-*
-* @param value to be written
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_WriteICC_SGI0R_EL1(val) mtcp(S3_0_C12_C11_7,val)
-
-/****************************************************************************/
-/**
-* This function writes to ICC_SGI1R_EL1
-*
-* @param value to be written
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_WriteICC_SGI1R_EL1(val) mtcp(S3_0_C12_C11_5,val)
-
-/****************************************************************************/
-/**
-* This function reads ICC_SGI1R_EL1 register
-*
-* @param None
-*
-* @return Value of ICC_SGI1R_EL1 register
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_ReadICC_SGI1R_EL1() mfcp(S3_0_C12_C11_5)
-/****************************************************************************/
-/**
-* This function sets interrupt priority filter
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_set_priority_filter(val) __asm__ __volatile__("msr S3_0_C4_C6_0,%0" : : "r" (val))
-/****************************************************************************/
-/**
-* This function returns interrupt id of highest priority pending interrupt
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#if defined (__aarch64__)
-#if EL3
-#define XScuGic_get_IntID() mfcp(S3_0_C12_C8_0)
-#else
-#define XScuGic_get_IntID() mfcp(S3_0_C12_C12_0)
-#endif
-#endif
-/****************************************************************************/
-/**
-* This function acks the interrupt
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#if defined (__aarch64__)
-#if EL3
-#define XScuGic_ack_Int(val) mtcp(S3_0_C12_C8_1,val)
-#else
-#define XScuGic_ack_Int(val) mtcp(S3_0_C12_C12_1,val)
-#endif
-#endif
-/****************************************************************************/
-/**
-* This macro returns bit position for the specific interrupt's trigger type
-* configuration within GICR_ICFGR0/GICR_ICFGR1 register
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_Get_Rdist_Int_Trigger_Index(IntrId) (((Int_Id%16) & 0x1f) << 2) +1
-/************************** Function Prototypes ******************************/
-
-/*
- * Required functions in xscugic.c
- */
-
-s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
- Xil_InterruptHandler Handler, void *CallBackRef);
-void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id);
-
-void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id);
-void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id);
-
-s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr,
- u32 EffectiveAddr);
-
-s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Identifier);
-
-void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
- u8 *Priority, u8 *Trigger);
-void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
- u8 Priority, u8 Trigger);
-void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Identifier, u32 Int_Id);
-void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Identifier, u32 Int_Id);
-void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Identifier);
-void XScuGic_Stop(XScuGic *InstancePtr);
-void XScuGic_SetCpuID(u32 CpuCoreId);
-u32 XScuGic_GetCpuID(void);
-/*
- * Initialization functions in xscugic_sinit.c
- */
-XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
-
-/*
- * Interrupt functions in xscugic_intr.c
- */
-void XScuGic_InterruptHandler(XScuGic *InstancePtr);
-
-/*
- * Self-test functions in xscugic_selftest.c
- */
-s32 XScuGic_SelfTest(XScuGic *InstancePtr);
-
-#if defined (GICv3)
-void XScuGic_MarkCoreAsleep(XScuGic *InstancePtr);
-void XScuGic_MarkCoreAwake(XScuGic *InstancePtr);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b1/d015c3595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b1/d015c3595243001d18b399c1eb9b3628
deleted file mode 100644
index a2443fe..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b1/d015c3595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,100 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xtime_l.c
-*
-* This file contains low level functions to get/set time from the Global Timer
-* register in the ARM Cortex A9 MP core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 1.00a rp/sdm 11/03/09 Initial release.
-* 3.07a sgd 07/05/12 Updated get/set time functions to make use Global Timer
-* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
-* displaying same warnings multiple times. It fixes CR#1090562.
-*
-*
-* @note None.
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "xtime_l.h"
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER)
-#pragma message ("For the sleep routines, Global timer is being used")
-#endif
-/****************************************************************************/
-/**
-* @brief Set the time in the Global Timer Counter Register.
-*
-* @param Xtime_Global: 64-bit Value to be written to the Global Timer
-* Counter Register.
-*
-* @return None.
-*
-* @note When this function is called by any one processor in a multi-
-* processor environment, reference time will reset/lost for all
-* processors.
-*
-****************************************************************************/
-void XTime_SetTime(XTime Xtime_Global)
-{
- /* Disable Global Timer */
- Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x0);
-
- /* Updating Global Timer Counter Register */
- Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_LOWER_OFFSET, (u32)Xtime_Global);
- Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_UPPER_OFFSET,
- (u32)((u32)(Xtime_Global>>32U)));
-
- /* Enable Global Timer */
- Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x1);
-}
-
-/****************************************************************************/
-/**
-* @brief Get the time from the Global Timer Counter Register.
-*
-* @param Xtime_Global: Pointer to the 64-bit location which will be
-* updated with the current timer value.
-*
-* @return None.
-*
-* @note None.
-*
-****************************************************************************/
-void XTime_GetTime(XTime *Xtime_Global)
-{
- u32 low;
- u32 high;
-
- /* Reading Global Timer Counter Register */
- do
- {
- high = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET);
- low = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_LOWER_OFFSET);
- } while(Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET) != high);
-
- *Xtime_Global = (((XTime) high) << 32U) | (XTime) low;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b2/21ca1c565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b2/21ca1c565243001d18b399c1eb9b3628
deleted file mode 100644
index 4cd1a71..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b2/21ca1c565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,320 +0,0 @@
-;******************************************************************************
-; Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
-; SPDX-License-Identifier: MIT
-; *****************************************************************************/
-; ****************************************************************************/
-; **
-; @file boot.S
-;
-; This file contains the initial startup code for the Cortex R5 processor
-;
-;
-; MODIFICATION HISTORY:
-;
-; Ver Who Date Changes
-; ----- ---- -------- ---------------------------------------------------
-; 5.00 mus 01/27/17 Initial version
-; 6.6 srm 10/18/17 Updated the timer configuration with XTime_StartTTCTimer.
-; Now the timer instance as specified by the user will be
-; started.
-; 6.6 mus 02/23/17 Disable the debug logic in non-JTAG boot mode(when
-; processor is in lockstep configuration), based
-; on the mld parameter "lockstep_mode_debug".
-* 6.8 mus 09/20/18 Clear VINITHI field in RPU_0_CFG/RPU_1_CFG
-* registers to initialize CortexR5 core with LOVEC
-* on reset. It fixes CR#1010656.
-* 7.0 mus 03/19/19 Disable FPU only in case of softp, otherwise enable it by
-* default. CR#1021638
-;
-;
-;
-; @note
-;
-; None.
-;
-; *****************************************************************************/
-
- MODULE ?boot
- ;; Forward declaration of sections.
- SECTION IRQ_STACK:DATA:NOROOT(3)
- SECTION FIQ_STACK:DATA:NOROOT(3)
- SECTION SVC_STACK:DATA:NOROOT(3)
- SECTION ABT_STACK:DATA:NOROOT(3)
- SECTION UND_STACK:DATA:NOROOT(3)
- SECTION CSTACK:DATA:NOROOT(3)
-
-#include "xparameters.h"
-
-#define UART_BAUDRATE 115200
- PUBLIC _prestart
- PUBLIC __iar_program_start
- IMPORT _vector_table
- IMPORT Init_MPU
-#ifdef SLEEP_TIMER_BASEADDR
- IMPORT XTime_StartTTCTimer
-#endif
- IMPORT __cmain
-vector_base EQU _vector_table
-RPU_GLBL_CNTL EQU 0xFF9A0000
-RPU_ERR_INJ EQU 0xFF9A0020
-RPU_0_CFG EQU 0xFF9A0100
-RPU_1_CFG EQU 0xFF9A0200
-RST_LPD_DBG EQU 0xFF5E0240
-BOOT_MODE_USER EQU 0xFF5E0200
-fault_log_enable EQU 0x101
-
- SECTION .boot:CODE:NOROOT(2)
-
-
-/* this initializes the various processor modes */
-
-_prestart
-__iar_program_start
-
-OKToRun
-
- REQUIRE _vector_table
-/* Initialize processor registers to 0 */
- mov r0,#0
- mov r1,#0
- mov r2,#0
- mov r3,#0
- mov r4,#0
- mov r5,#0
- mov r6,#0
- mov r7,#0
- mov r8,#0
- mov r9,#0
- mov r10,#0
- mov r11,#0
- mov r12,#0
-
-/* Initialize stack pointer and banked registers for various mode */
- mrs r0, cpsr ; get the current PSR
- mvn r1, #0x1f ; set up the irq stack pointer
- and r2, r1, r0
- orr r2, r2, #0x12 ; IRQ mode
- msr cpsr, r2
- ldr r13,=SFE(IRQ_STACK) ; IRQ stack pointer
- mov r14,#0
-
- mrs r0, cpsr ; get the current PSR
- mvn r1, #0x1f ; set up the supervisor stack pointer
- and r2, r1, r0
- orr r2, r2, #0x13 ; supervisor mode
- msr cpsr, r2
- ldr r13,=SFE(SVC_STACK) ; Supervisor stack pointer
- mov r14,#0
-
- mrs r0, cpsr ; get the current PSR
- mvn r1, #0x1f ; set up the Abort stack pointer
- and r2, r1, r0
- orr r2, r2, #0x17 ; Abort mode
- msr cpsr, r2
- ldr r13,=SFE(ABT_STACK) ; Abort stack pointer
- mov r14,#0
-
- mrs r0, cpsr ; get the current PSR
- mvn r1, #0x1f ; set up the FIQ stack pointer
- and r2, r1, r0
- orr r2, r2, #0x11 ; FIQ mode
- msr cpsr, r2
- mov r8, #0
- mov r9, #0
- mov r10, #0
- mov r11, #0
- mov r12, #0
- ldr r13,=SFE(FIQ_STACK) ; FIQ stack pointer
- mov r14,#0
-
- mrs r0, cpsr ; get the current PSR
- mvn r1, #0x1f ; set up the Undefine stack pointer
- and r2, r1, r0
- orr r2, r2, #0x1b ; Undefine mode
- msr cpsr, r2
- ldr r13,=SFE(UND_STACK) ; Undefine stack pointer
- mov r14,#0
-
- mrs r0, cpsr ; get the current PSR
- mvn r1, #0x1f ; set up the system stack pointer
- and r2, r1, r0
- orr r2, r2, #0x1F ; SYS mode
- msr cpsr, r2
- ldr r13,=SFE(CSTACK) ; SYS stack pointer
- mov r14,#0
-
- ;
- ; Enable access to VFP by enabling access to Coprocessors 10 and 11.
- ; Enables Full Access i.e. in both privileged and non privileged modes
- ;
- mrc p15, 0, r0, c1, c0, 2 ; Read Coprocessor Access Control Register (CPACR)
- orr r0, r0, #(0xF << 20) ; Enable access to CP 10 & 11
- mcr p15, 0, r0, c1, c0, 2 ; Write Coprocessor Access Control Register (CPACR)
- isb
-
-; enable fpu access
- vmrs r3, FPEXC
- orr r1, r3, #(1<<30)
- vmsr FPEXC, r1
-
- ; clear the floating point register
- mov r1,#0
- vmov d0,r1,r1
- vmov d1,r1,r1
- vmov d2,r1,r1
- vmov d3,r1,r1
- vmov d4,r1,r1
- vmov d5,r1,r1
- vmov d6,r1,r1
- vmov d7,r1,r1
- vmov d8,r1,r1
- vmov d9,r1,r1
- vmov d10,r1,r1
- vmov d11,r1,r1
- vmov d12,r1,r1
- vmov d13,r1,r1
- vmov d14,r1,r1
- vmov d15,r1,r1
-
-#ifdef __SOFTFP__
- ; Disable FPU by restoring previous value for FPU access
- vmsr FPEXC,r3
-#endif
-
- ; Disable MPU and caches
- mrc p15, 0, r0, c1, c0, 0 ; Read CP15 Control Register
- bic r0, r0, #0x05 ; Disable MPU (M bit) and data cache (C bit)
- bic r0, r0, #0x1000 ; Disable instruction cache (I bit)
- dsb ; Ensure all previous loads/stores have completed
- mcr p15, 0, r0, c1, c0, 0 ; Write CP15 Control Register
- isb ; Ensure subsequent insts execute wrt new MPU settings
-
- ; Disable Branch prediction, TCM ECC checks
- mrc p15, 0, r0, c1, c0, 1 ; Read ACTLR
- orr r0, r0, #(0x1 << 17) ; Enable RSDIS bit 17 to disable the return stack
- orr r0, r0, #(0x1 << 16) ; Clear BP bit 15 and set BP bit 16
- bic r0, r0, #(0x1 << 15) ; Branch always not taken and history table updates disabled
- bic r0, r0, #(0x1 << 27) ; Disable B1TCM ECC check
- bic r0, r0, #(0x1 << 26) ; Disable B0TCM ECC check
- bic r0, r0, #(0x1 << 25) ; Disable ATCM ECC check
- orr r0, r0, #(0x1 << 5) ; Enable ECC with no forced write through with [5:3]=b'101
- bic r0, r0, #(0x1 << 4)
- orr r0, r0, #(0x1 << 3)
- mcr p15, 0, r0, c1, c0, 1 ; Write ACTLR*/
- dsb ; Complete all outstanding explicit memory operations*/
-
- ; Invalidate caches
- mov r0,#0 ; r0 = 0
- dsb
- mcr p15, 0, r0, c7, c5, 0 ; invalidate icache
- mcr p15, 0, r0, c15, c5, 0 ; Invalidate entire data cache
- isb
-
-#if LOCKSTEP_MODE_DEBUG == 0
- ; enable fault log for lock step
- ldr r0,=RPU_GLBL_CNTL
- ldr r1, [r0]
- ands r1, r1, #0x8
- ; branch to initialization if split mode
- bne init
- ; check for boot mode if in lock step, branch to init if JTAG boot mode
- ldr r0,=BOOT_MODE_USER
- ldr r1, [r0]
- ands r1, r1, #0xF
- beq init
- ; reset the debug logic
- ldr r0,=RST_LPD_DBG
- ldr r1, [r0]
- orr r1, r1, #(0x1 << 1)
- orr r1, r1, #(0x1 << 4)
- orr r1, r1, #(0x1 << 5)
- str r1, [r0]
- ; enable fault log
- ldr r0,=RPU_ERR_INJ
- ldr r1,=fault_log_enable
- ldr r2, [r0]
- orr r2, r2, r1
- str r2, [r0]
- nop
- nop
- #endif
-
-init
- bl Init_MPU ; Initialize MPU
-
- ; Enable Branch prediction
- mrc p15, 0, r0, c1, c0, 1 ; Read ACTLR
- bic r0, r0, #(0x1 << 17) ; Clear RSDIS bit 17 to enable return stack
- bic r0, r0, #(0x1 << 16) ; Clear BP bit 15 and BP bit 16:
- bic r0, r0, #(0x1 << 15) ; Normal operation, BP is taken from the global history table.
- orr r0, r0, #(0x1 << 14) ; Disable DBWR for errata 780125
- mcr p15, 0, r0, c1, c0, 1 ; Write ACTLR
-
- ; Enable icahce and dcache
- mrc p15,0,r1,c1,c0,0
- ldr r0, =0x1005
- orr r1,r1,r0
- dsb
- mcr p15,0,r1,c1,c0,0 ; Enable cache
- isb ; isb flush prefetch buffer
-
-
-
- ; Set vector table in TCM/LOVEC
-#ifndef VEC_TABLE_IN_OCM
- mrc p15, 0, r0, c1, c0, 0
- mvn r1, #0x2000
- and r0, r0, r1
- mcr p15, 0, r0, c1, c0, 0
-
- ; Clear VINITHI to enable LOVEC on reset
-#if XPAR_CPU_ID == 0
- ldr r0, =RPU_0_CFG
-#else
- ldr r0, =RPU_1_CFG
-#endif
- ldr r1, [r0]
- bic r1, r1, #(0x1 << 2)
- str r1, [r0]
-#endif
-
- ; enable asynchronous abort exception
- mrs r0, cpsr
- bic r0, r0, #0x100
- msr cpsr_xsf, r0
-
- ; Clear cp15 regs with unknown reset values
- mov r0, #0x0
- mcr p15, 0, r0, c5, c0, 0 ; DFSR
- mcr p15, 0, r0, c5, c0, 1 ; IFSR
- mcr p15, 0, r0, c6, c0, 0 ; DFAR
- mcr p15, 0, r0, c6, c0, 2 ; IFAR
- mcr p15, 0, r0, c9, c13, 2 ; PMXEVCNTR
- mcr p15, 0, r0, c13, c0, 2 ; TPIDRURW
- mcr p15, 0, r0, c13, c0, 3 ; TPIDRURO
-
-
- ; Reset and start Cycle Counter
- mov r2, #0x80000000 ; clear overflow
- mcr p15, 0, r2, c9, c12, 3
- mov r2, #0xd ; D, C, E
- mcr p15, 0, r2, c9, c12, 0
- mov r2, #0x80000000 ; enable cycle counter
- mcr p15, 0, r2, c9, c12, 1
-
- ; configure the timer if TTC is present
- #ifdef SLEEP_TIMER_BASEADDR
- bl XTime_StartTTCTimer
- #endif
-
- ; make sure argc and argv are valid
- mov r0, #0
- mov r1, #0
-
- b __cmain ; jump to C startup code
-
-
-Ldone b Ldone ; Paranoia: we should never get here
-
-
- END
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b2/605667585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b2/605667585243001d18b399c1eb9b3628
deleted file mode 100644
index c584f31..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b2/605667585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,111 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************
-*
-* @file sleep.c
-*
-* This function provides a second delay using the Global Timer register in
-* the ARM Cortex A53 MP core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/29/14 First release
-* 5.04 pkp 28/01/16 Modified the sleep API to configure Time Stamp
-* generator only when disable using frequency from
-* xparamters.h instead of hardcoding
-* 5.05 pkp 13/04/16 Modified sleep routine to call XTime_StartTimer
-* which enables timer only when it is disabled and
-* read counter value directly from register instead
-* of calling XTime_GetTime for optimization
-* 6.0 asa 08/15/16 Updated the sleep/usleep signature. Fix for CR#956899.
-* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
-* implementation. Now sleep routines will use Timer
-* specified by the user (i.e. Global timer/TTC timer)
-* srm 01/11/18 Fixed the compilation warning.
-* 7.5 dp 01/05/21 Updated COUNTS_PER_USECOND macros to round it off to
-* nearest possible value so that delta error in time
-* calculations can be minimized.
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "sleep.h"
-#include "xtime_l.h"
-#include "xparameters.h"
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#include "xil_sleeptimer.h"
-#endif
-/**************************** Constant Definitions ************************/
-
-/* Global Timer is always clocked at half of the CPU frequency */
-#define COUNTS_PER_USECOND ((COUNTS_PER_SECOND + 500000)/1000000)
-
-/************************************************************************/
-#if !defined (SLEEP_TIMER_BASEADDR)
-static void sleep_common(u32 n, u32 count)
-{
- XTime tEnd, tCur;
- /* Start global timer counter, it will only be enabled if it is disabled */
- XTime_StartTimer();
-
- tCur = mfcp(CNTPCT_EL0);
- tEnd = tCur + (((XTime) n) * count);
- do {
- tCur = mfcp(CNTPCT_EL0);
- } while (tCur < tEnd);
-}
-#endif
-/*****************************************************************************/
-/**
-*
-* This API gives a delay in microseconds
-*
-* @param useconds requested
-*
-* @return 0 if the delay can be achieved, -1 if the requested delay
-* is out of range
-*
-* @note None.
-*
-****************************************************************************/
-int usleep_A53(unsigned long useconds)
-{
-#if defined (SLEEP_TIMER_BASEADDR)
- Xil_SleepTTCCommon(useconds, COUNTS_PER_USECOND);
-#else
- sleep_common((u32)useconds, COUNTS_PER_USECOND);
-#endif
-
- return 0;
-}
-
-/*****************************************************************************/
-/*
-*
-* This API is used to provide delays in seconds
-*
-* @param seconds requested
-*
-* @return 0 always
-*
-* @note None.
-*
-****************************************************************************/
-unsigned sleep_A53(unsigned int seconds)
-{
-#if defined (SLEEP_TIMER_BASEADDR)
- Xil_SleepTTCCommon(seconds, COUNTS_PER_SECOND);
-#else
- sleep_common(seconds, COUNTS_PER_SECOND);
-#endif
-
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b2/80c788555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b2/80c788555243001d18b399c1eb9b3628
deleted file mode 100644
index 9c39cba..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b2/80c788555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,15 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: MIT
-*
-******************************************************************************/
-#include "xil_types.h"
-
-/* Stub for exit() sys-call */
-__attribute__((weak)) void _sys_exit(__attribute__((unused)) s32 rc)
-{
- while(1) {
- ;
- }
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b2/914bbe545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b2/914bbe545243001d18b399c1eb9b3628
deleted file mode 100644
index abc67b7..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b2/914bbe545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,73 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xgpiops_sinit.c
-* @addtogroup gpiops_v3_9
-* @{
-*
-* This file contains the implementation of the XGpioPs driver's static
-* initialization functionality.
-*
-* @note None.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sv 01/15/10 First Release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xgpiops.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-
-/*****************************************************************************/
-/**
-*
-* This function looks for the device configuration based on the unique device
-* ID. The table XGpioPs_ConfigTable[] contains the configuration information
-* for each device in the system.
-*
-* @param DeviceId is the unique device ID of the device being looked up.
-*
-* @return A pointer to the configuration table entry corresponding to the
-* given device ID, or NULL if no match is found.
-*
-* @note None.
-*
-******************************************************************************/
-XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
-{
- XGpioPs_Config *CfgPtr = NULL;
- u32 Index;
-
- for (Index = 0U; Index < (u32)XPAR_XGPIOPS_NUM_INSTANCES; Index++) {
- if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XGpioPs_ConfigTable[Index];
- break;
- }
- }
-
- return (XGpioPs_Config *)CfgPtr;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b3/10d828565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b3/10d828565243001d18b399c1eb9b3628
deleted file mode 100644
index 368a2db..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b3/10d828565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,108 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file usleep.c
-*
-* This function supports user configurable sleep implementation.
-* This provides a microsecond delay using the timer specified by the user in
-* the ARM Cortex R5 MP core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 02/20/14 First release
-* 5.04 pkp 02/19/16 usleep routine is modified to use TTC3 if present
-* else it will use set of assembly instructions to
-* provide the required delay
-* 5.04 pkp 03/09/16 Assembly routine for usleep is modified to avoid
-* disabling the interrupt
-* 5.04 pkp 03/11/16 Compare the counter value to previously read value
-* to detect the overflow for TTC3
-* 6.0 asa 08/15/16 Updated the usleep signature. Fix for CR#956899.
-* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
-* implementation. Now sleep routines will use TTC
-* instance specified by user.
-* 7.2 mus 01/29/20 Updated sleep routines to use CortexR5 PMU for delay
-* generation, in case TTC3/TTC2 instances are not
-* present in HW design. If user dont want to use PMU
-* counter for sleep routines, BSP needs to be compiled
-* with "DONT_USE_PMU_FOR_SLEEP_ROUTINES" flag. It fixes
-* CR#1051591.
-*
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "sleep.h"
-#include "xtime_l.h"
-#include "xparameters.h"
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#include "xreg_cortexr5.h"
-#include "xpm_counter.h"
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#include "xil_sleeptimer.h"
-#endif
-
-/*****************************************************************************/
-/**
-*
-* This API gives a delay in microseconds
-*
-* @param useconds requested
-*
-* @return 0 always
-*
-* @note By default, usleep is implemented using TTC3. Although user is
-* given an option to select other instances of TTC. When the user
-* selects other instances of TTC, usleep is implemented by that
-* specific TTC instance. If the user didn't select any other instance
-* of TTC specifically and when TTC3 is absent, usleep is implemented
-* using assembly instructions which is tested with instruction and
-* data caches enabled and it gives proper delay. It may give more
-* delay than exepcted when caches are disabled. If interrupt comes
-* when usleep using assembly instruction is being executed, the delay
-* may be greater than what is expected since once the interrupt is
-* served count resumes from where it was interrupted unlike the case
-* of TTC3 where counter keeps running while interrupt is being served.
-*
-****************************************************************************/
-
-int usleep_R5(unsigned long useconds)
-{
-#if defined (SLEEP_TIMER_BASEADDR)
- Xil_SleepTTCCommon(useconds, COUNTS_PER_USECOND);
-#elif !defined (DONT_USE_PMU_FOR_SLEEP_ROUTINES)
- Xpm_SleepPerfCounter(useconds, COUNTS_PER_USECOND);
-#else
-#if defined (__GNUC__)
- __asm__ __volatile__ (
-#elif defined (__ICCARM__)
- __asm volatile (
-#endif
- "push {r0,r1,r3} \n"
- "mov r0, %[usec] \n"
- "mov r1, %[iter] \n"
- "1: \n"
- "mov r3, r1 \n"
- "2: \n"
- "subs r3, r3, #0x1\n"
- "bne 2b \n"
- "subs r0, r0, #0x1 \n"
- "bne 1b \n"
- "pop {r0,r1,r3} \n"
- ::[iter] "r" (ITERS_PER_USEC), [usec] "r" (useconds)
- );
-#endif
-
-return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b3/11f7a3525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b3/11f7a3525243001d18b399c1eb9b3628
deleted file mode 100644
index 9397afc..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b3/11f7a3525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,61 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/******************************************************************************/
-/**
-* @file xgpio_i.h
-* @addtogroup gpio_v4_8
-* @{
-*
-* This header file contains internal identifiers, which are those shared
-* between the files of the driver. It is intended for internal use only.
-*
-* NOTES:
-*
-* None.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 03/13/02 First release
-* 2.11a mta 03/21/07 Updated to new coding style
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
-* 7.0 aru 01/21/19 Modified the typedef of u32,u16,u8
-* 7.0 aru 02/06/19 Included stdint.h and stddef.h
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
-#define XBASIC_TYPES_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include
-#include
-
-/** @name Legacy types
- * Deprecated legacy types.
- * @{
- */
-typedef uint8_t Xuint8; /**< unsigned 8-bit */
-typedef char Xint8; /**< signed 8-bit */
-typedef uint16_t Xuint16; /**< unsigned 16-bit */
-typedef short Xint16; /**< signed 16-bit */
-typedef uint32_t Xuint32; /**< unsigned 32-bit */
-typedef long Xint32; /**< signed 32-bit */
-typedef float Xfloat32; /**< 32-bit floating point */
-typedef double Xfloat64; /**< 64-bit double precision FP */
-typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
-
-#if !defined __XUINT64__
-typedef struct
-{
- Xuint32 Upper;
- Xuint32 Lower;
-} Xuint64;
-#endif
-
-/** @name New types
- * New simple types.
- * @{
- */
-#ifndef __KERNEL__
-#ifndef XIL_TYPES_H
-typedef Xuint32 u32;
-typedef Xuint16 u16;
-typedef Xuint8 u8;
-#endif
-#else
-#include
-#endif
-
-#ifndef TRUE
-# define TRUE 1U
-#endif
-
-#ifndef FALSE
-# define FALSE 0U
-#endif
-
-#ifndef NULL
-#define NULL 0U
-#endif
-
-/*
- * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
- * Please use NULL, TRUE and FALSE
- */
-#define XNULL NULL
-#define XTRUE TRUE
-#define XFALSE FALSE
-
-/*
- * This file is deprecated and users
- * should use xil_types.h and xil_assert.h\n\r
- */
-#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
-#warning Please refer the Standalone BSP UG647 for further details
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b3/722032595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b3/722032595243001d18b399c1eb9b3628
deleted file mode 100644
index b3dd7e9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b3/722032595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,126 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_assert.c
-* @addtogroup common_assert_apis Assert APIs and Macros
-* @{
-*
-* This file contains basic assert related functions for Xilinx software IP.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 Initial release
-* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/**
- * @brief This variable allows testing to be done easier with asserts. An assert
- * sets this variable such that a driver can evaluate this variable
- * to determine if an assert occurred.
- */
-u32 Xil_AssertStatus;
-
-/**
- * @brief This variable allows the assert functionality to be changed for testing
- * such that it does not wait infinitely. Use the debugger to disable the
- * waiting during testing of asserts.
- */
-s32 Xil_AssertWait = 1;
-
-/* The callback function to be invoked when an assert is taken */
-static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* @brief Implement assert. Currently, it calls a user-defined callback
-* function if one has been set. Then, it potentially enters an
-* infinite loop depending on the value of the Xil_AssertWait
-* variable.
-*
-* @param File: filename of the source
-* @param Line: linenumber within File
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void Xil_Assert(const char8 *File, s32 Line)
-{
- /* if the callback has been set then invoke it */
- if (Xil_AssertCallbackRoutine != 0) {
- (*Xil_AssertCallbackRoutine)(File, Line);
- }
-
- /* if specified, wait indefinitely such that the assert will show up
- * in testing
- */
- while (Xil_AssertWait != 0) {
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Set up a callback function to be invoked when an assert occurs.
-* If a callback is already installed, then it will be replaced.
-*
-* @param Routine: callback to be invoked when an assert is taken
-*
-* @return None.
-*
-* @note This function has no effect if NDEBUG is set
-*
-******************************************************************************/
-void Xil_AssertSetCallback(Xil_AssertCallback Routine)
-{
- Xil_AssertCallbackRoutine = Routine;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Null handler function. This follows the XInterruptHandler
-* signature for interrupt handlers. It can be used to assign a null
-* handler (a stub) to an interrupt controller vector table.
-*
-* @param NullParameter: arbitrary void pointer and not used.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XNullHandler(void *NullParameter)
-{
- (void) NullParameter;
-}
-/**
-* @} End of "addtogroup common_assert_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b3/90f8608c4046001d13a480ec55035cc1 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b3/90f8608c4046001d13a480ec55035cc1
deleted file mode 100644
index 8b31d48..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b3/90f8608c4046001d13a480ec55035cc1
+++ /dev/null
@@ -1,19 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b3/a0f3e7545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b3/a0f3e7545243001d18b399c1eb9b3628
deleted file mode 100644
index 7834953..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b3/a0f3e7545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,31 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 2021.2
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2022 Xilinx, Inc. All Rights Reserved.
-* SPDX-License-Identifier: MIT
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xscuwdt.h"
-
-/*
-* The configuration table for devices
-*/
-
-XScuWdt_Config XScuWdt_ConfigTable[XPAR_XSCUWDT_NUM_INSTANCES] =
-{
- {
- XPAR_PS7_SCUWDT_0_DEVICE_ID,
- XPAR_PS7_SCUWDT_0_BASEADDR
- }
-};
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b3/a294d0575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b3/a294d0575243001d18b399c1eb9b3628
deleted file mode 100644
index be5fccb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b3/a294d0575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,41 +0,0 @@
-DRIVER_LIB_VERSION = 1.0
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I$(INCLUDEDIR)
-
-INCLUDEFILES:=*.h
-
-SRCFILES:=$(wildcard *.c)
-
-OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
-
-libs: $(OBJECTS)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf $(DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b4/30357d525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b4/30357d525243001d18b399c1eb9b3628
deleted file mode 100644
index 6b51ea9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b4/30357d525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,28 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-
-#ifndef _MBLAZE_NT_TYPES_H
-#define _MBLAZE_NT_TYPES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef char byte;
-typedef short half;
-typedef int word;
-typedef unsigned char ubyte;
-typedef unsigned short uhalf;
-typedef unsigned int uword;
-typedef ubyte boolean;
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b4/6092ec555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b4/6092ec555243001d18b399c1eb9b3628
deleted file mode 100644
index 994854a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b4/6092ec555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,59 +0,0 @@
-###############################################################################
-# Copyright (c) 2011 - 2020 Xilinx, Inc. All rights reserved.
-# SPDX-License-Identifier: MIT
-###############################################################################
-DRIVER_LIB_VERSION = v1.0
-
-include config.make
-
-AS=$(ASSEMBLER)
-COMPILER=$(COMPILER)
-ARCHIVER=$(ARCHIVER)
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-ECC_FLAGS += --fpu=VFPv3
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-
-INCLUDES=-I./. -I${INCLUDEDIR}
-INCLUDEFILES=*.h
-
-SRCFILES:=$(wildcard *.c)
-
-ASSEMBLY_SRCFILES:=$(wildcard *.S)
-
-OBJECTS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(wildcard *.c))))
-OBJECTS += $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(wildcard *.s))))
-
-libs: $(LIBS)
-standalone_libs: ${OBJECTS}
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.s
- ${AS} --cpu Cortex-A9 --fpu VFPv3 $(INCLUDES) -o $@ $<
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $<
-
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf $(DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b4/90b365595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b4/90b365595243001d18b399c1eb9b3628
deleted file mode 100644
index 72243f0..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b4/90b365595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,90 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file microblaze_interrupt_handler.c
-*
-* This file contains the standard interrupt handler for the MicroBlaze processor.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Date Changes
-* ----- -------- -----------------------------------------------
-* 1.00b 10/03/03 First release
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
-* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
-* APIs is words (32 bit) and not bytes.
-* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
-* to add information that 2 LSBs of the Source/Destination
-* address when equal to 2�b01 indicate the last DMA command
-* of an overall transfer.
-* Destination Address passed to this API for secure transfers
-* instead of using 0xFFFFFFFF for CR 662197. This issue was
-* resulting in the failure of secure transfers of
-* non-bitstream images.
-* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
-* set the mask instead of oring it with the
-* value read from the interrupt status register
-* Added defines for the PS Version bits,
-* removed the FIFO Flush bits from the
-* Miscellaneous Control Reg.
-* Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
-* and XDcfg_SelectPcapInterface APIs for CR 643295
-* The user has to call the XDcfg_SelectIcapInterface API
-* for the PL reconfiguration using AXI HwIcap.
-* Updated the XDcfg_Transfer API to clear the
-* QUARTER_PCAP_RATE_EN bit in the control register for
-* non secure writes for CR 675543.
-* 2.02a nm 01/31/13 Fixed CR# 679335.
-* Added Setting and Clearing the internal PCAP loopback.
-* Removed code for enabling/disabling AES engine as BootROM
-* locks down this setting.
-* Fixed CR# 681976.
-* Skip Checking the PCFG_INIT in case of non-secure DMA
-* loopback.
-* Fixed CR# 699558.
-* XDcfg_Transfer fails to transfer data in loopback mode.
-* Fixed CR# 701348.
-* Peripheral test fails with Running
-* DcfgSelfTestExample() in SECURE bootmode.
-* 2.03a nm 04/19/13 Fixed CR# 703728.
-* Updated the register definitions as per the latest TRM
-* version UG585 (v1.4) November 16, 2012.
-* 3.0 adk 10/12/13 Updated as per the New Tcl API's
-* 3.0 kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
-* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
-* updated driver code with != instead of ==,
-* while checking for Interrupt Status with DMA and
-* PCAP Done Mask
-* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
-* XDCFG_INT_STS_OFFSET) &
-* XDCFG_IXR_D_P_DONE_MASK) !=
-* XDCFG_IXR_D_P_DONE_MASK);
-* A new example has been added to read back the
-* configuration registers from the PL region.
-* xdevcfg_reg_readback_example.c
-* 3.3 sk 04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/10/17 Modified filename tag in interrupt and polled examples
-* to include them in doxygen examples.
-* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros
-* definitions of devcfg in xparameters.h
-* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
-*
-*
-******************************************************************************/
-#ifndef XDCFG_H /* prevent circular inclusions */
-#define XDCFG_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xdevcfg_hw.h"
-#include "xstatus.h"
-#include "xil_assert.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/* Types of PCAP transfers */
-
-#define XDCFG_NON_SECURE_PCAP_WRITE 1
-#define XDCFG_SECURE_PCAP_WRITE 2
-#define XDCFG_PCAP_READBACK 3
-#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4
-#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5
-
-
-/**************************** Type Definitions *******************************/
-/**
-* The handler data type allows the user to define a callback function to
-* respond to interrupt events in the system. This function is executed
-* in interrupt context, so amount of processing should be minimized.
-*
-* @param CallBackRef is the callback reference passed in by the upper
-* layer when setting the callback functions, and passed back to
-* the upper layer when the callback is invoked. Its type is
-* unimportant to the driver component, so it is a void pointer.
-* @param Status is the Interrupt status of the XDcfg device.
-*/
-typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddr; /**< Base address of the device */
-} XDcfg_Config;
-
-/**
- * The XDcfg driver instance data.
- */
-typedef struct {
- XDcfg_Config Config; /**< Hardware Configuration */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStarted; /**< Device Configuration Interface
- * is running
- */
- XDcfg_IntrHandler StatusHandler; /* Event handler function */
- void *CallBackRef; /* Callback reference for event handler */
-} XDcfg;
-
-/****************************************************************************/
-/**
-*
-* Unlock the Device Config Interface block.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_Unlock(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_Unlock(InstancePtr) \
- XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \
- XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
-
-
-
-/****************************************************************************/
-/**
-*
-* Get the version number of the PS from the Miscellaneous Control Register.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return Version of the PS.
-*
-* @note C-style signature:
-* void XDcfg_GetPsVersion(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_GetPsVersion(InstancePtr) \
- ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
- XDCFG_MCTRL_OFFSET)) & \
- XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \
- XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
-
-
-
-/****************************************************************************/
-/**
-*
-* Read the multiboot config register value.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_ReadMultiBootConfig(InstancePtr) \
- XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
- XDCFG_MULTIBOOT_ADDR_OFFSET)
-
-
-/****************************************************************************/
-/**
-*
-* Selects ICAP interface for reconfiguration after the initial configuration
-* of the PL.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_SelectIcapInterface(InstancePtr) \
- XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
- ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
- & ( ~XDCFG_CTRL_PCAP_PR_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Selects PCAP interface for reconfiguration after the initial configuration
-* of the PL.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_SelectPcapInterface(InstancePtr) \
- XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
- ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
- | XDCFG_CTRL_PCAP_PR_MASK))
-
-
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Lookup configuration in xdevcfg_sinit.c.
- */
-XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId);
-
-/*
- * Selftest function in xdevcfg_selftest.c
- */
-int XDcfg_SelfTest(XDcfg *InstancePtr);
-
-/*
- * Interface functions in xdevcfg.c
- */
-int XDcfg_CfgInitialize(XDcfg *InstancePtr,
- XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
-
-void XDcfg_EnablePCAP(XDcfg *InstancePtr);
-
-void XDcfg_DisablePCAP(XDcfg *InstancePtr);
-
-void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask);
-
-void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask);
-
-u32 XDcfg_GetControlRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetLockRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask);
-
-u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr);
-
-u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr);
-
-void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
- u32 SrcWordLength, u32 DestWordLength);
-
-u32 XDcfg_Transfer(XDcfg *InstancePtr,
- void *SourcePtr, u32 SrcWordLength,
- void *DestPtr, u32 DestWordLength,
- u32 TransferType);
-
-/*
- * Interrupt related function prototypes implemented in xdevcfg_intr.c
- */
-void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask);
-
-void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask);
-
-u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr);
-
-u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr);
-
-void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask);
-
-void XDcfg_InterruptHandler(XDcfg *InstancePtr);
-
-void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
- void *CallBackRef);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b5/403090575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b5/403090575243001d18b399c1eb9b3628
deleted file mode 100644
index b3cd2ea..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b5/403090575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,113 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xplatform_info.h
-*
-*
-* @addtogroup common_platform_info APIs to Get Platform Information
-*
-*
-* The xplatform_info.h file contains definitions for various available Xilinx®
-* platforms. Also, it contains prototype of APIs, which can be used to get the
-* platform information.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- --------- -------------------------------------------------------
-* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
-* function for PMUFW.
-* 7.2 adk 08/01/20 Added versal support for the XGetPSVersion_Info function.
-* 7.6 mus 08/23/21 Updated prototypes for functions which are not taking any
-* arguments with void keyword. This has been done to fix
-* compilation warnings with "-Wstrict-prototypes" flag.
-* It fixes CR#1108601.
-* 7.6 mus 08/30/21 Updated flag checking to fix compilation warnings
-* reported with "-Wundef" flag.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00 sdm 11/25/10 First release
-* 2.01a sg 02/03/13 Delay Register test is added with DelayNss parameter.
-* 3.1 hk 06/19/14 Remove checks for CR and ISR register values as they are
-* reset in the previous step.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xqspips.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-*
-* Runs a self-test on the driver/device. The self-test is destructive in that
-* a reset of the device is performed in order to check the reset values of
-* the registers and to get the device into a known state.
-*
-* Upon successful return from the self-test, the device is reset.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return
-* - XST_SUCCESS if successful
-* - XST_REGISTER_ERROR indicates a register did not read or write
-* correctly.
-*
-* @note None.
-*
-******************************************************************************/
-int XQspiPs_SelfTest(XQspiPs *InstancePtr)
-{
- int Status;
- u8 DelayTestNss;
- u8 DelayTestBtwn;
- u8 DelayTestAfter;
- u8 DelayTestInit;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Reset the QSPI device to leave it in a known good state
- */
- XQspiPs_Reset(InstancePtr);
-
- DelayTestNss = 0x5A;
- DelayTestBtwn = 0xA5;
- DelayTestAfter = 0xAA;
- DelayTestInit = 0x55;
-
- /*
- * Write and read the delay register, just to be sure there is some
- * hardware out there.
- */
- Status = XQspiPs_SetDelays(InstancePtr, DelayTestNss, DelayTestBtwn,
- DelayTestAfter, DelayTestInit);
- if (Status != XST_SUCCESS) {
- return Status;
- }
-
- XQspiPs_GetDelays(InstancePtr, &DelayTestNss, &DelayTestBtwn,
- &DelayTestAfter, &DelayTestInit);
- if ((0x5A != DelayTestNss) || (0xA5 != DelayTestBtwn) ||
- (0xAA != DelayTestAfter) || (0x55 != DelayTestInit)) {
- return XST_REGISTER_ERROR;
- }
-
- Status = XQspiPs_SetDelays(InstancePtr, 0, 0, 0, 0);
- if (Status != XST_SUCCESS) {
- return Status;
- }
-
- /*
- * Reset the QSPI device to leave it in a known good state
- */
- XQspiPs_Reset(InstancePtr);
-
- return XST_SUCCESS;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b6/216166575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b6/216166575243001d18b399c1eb9b3628
deleted file mode 100644
index 6f40407..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b6/216166575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,52 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xcoresightpsdcc.h
-* @addtogroup coresightps_dcc_v1_8
-* @{
-* @details
-*
-* CoreSight driver component.
-*
-* The coresight is a part of debug communication channel (DCC) group. Jtag UART
-* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
-* ARM target in XSDB console before running the jtag terminal command. Using the
-* coresight driver component, the output stream can be directed to a log file.
-*
-* @note None.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------
-* 1.00 kvn 02/14/15 First release
-* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
-* kvn 08/18/15 Modified Makefile according to compiler changes.
-* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
-* for MB BSPs. Instead it throws up a warning. This
-* fixes the CR#953056.
-* 1.5 sne 01/19/19 Fixed MISRA-C Violations CR#1025101.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#ifndef XCORESIGHTPSDCC_H /* prevent circular inclusions */
-#define XCORESIGHTPSDCC_H /* by using protection macros */
-#ifndef __MICROBLAZE__
-#include
-
-void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
-
-u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
-#endif
-#endif
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b7/10d9fb595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b7/10d9fb595243001d18b399c1eb9b3628
deleted file mode 100644
index b3c70ca..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b7/10d9fb595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,36 +0,0 @@
-/*-------------------------------------------*/
-/* Integer type definitions for FatFs module */
-/*-------------------------------------------*/
-
-#ifndef FF_INTEGER
-#define FF_INTEGER
-
-#ifdef _WIN32 /* FatFs development platform */
-
-#include
-typedef unsigned __int64 QWORD;
-
-#else /* Embedded platform */
-
-/* These types MUST be 16-bit or 32-bit */
-typedef int INT;
-typedef unsigned int UINT;
-
-/* This type MUST be 8-bit */
-typedef unsigned char BYTE;
-
-/* These types MUST be 16-bit */
-typedef short SHORT;
-typedef unsigned short WORD;
-typedef unsigned short WCHAR;
-
-/* These types MUST be 32-bit */
-typedef long LONG;
-typedef unsigned long DWORD;
-
-/* This type MUST be 64-bit (Remove this for ANSI C (C89) compatibility) */
-typedef unsigned long long QWORD;
-
-#endif
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b7/20ca1c565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b7/20ca1c565243001d18b399c1eb9b3628
deleted file mode 100644
index d7c4c3c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b7/20ca1c565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,141 +0,0 @@
-;******************************************************************************
-; Copyright (c) 2017 - 2020 Xilinx, Inc. All rights reserved.
-; SPDX-License-Identifier: MIT
-;*****************************************************************************/
-;*****************************************************************************/
-;**
-; @file asm_vectors.s
-;
-; This file contains the initial vector table for the Cortex R5 processor
-;
-;
-; MODIFICATION HISTORY:
-;
-; Ver Who Date Changes
-; ----- ------- -------- ---------------------------------------------------
-; 6.2 mus 01/27/17 Initial version
-;
-;
-; @note
-;
-; None.
-;
-;*****************************************************************************/
-
- MODULE ?asm_vectors
-
- ;; Forward declaration of sections.
- SECTION IRQ_STACK:DATA:NOROOT(3)
- SECTION FIQ_STACK:DATA:NOROOT(3)
- SECTION SVC_STACK:DATA:NOROOT(3)
- SECTION ABT_STACK:DATA:NOROOT(3)
- SECTION UND_STACK:DATA:NOROOT(3)
- SECTION CSTACK:DATA:NOROOT(3)
-
-#define UART_BAUDRATE 115200
-
- IMPORT _prestart
- IMPORT __iar_program_start
-
- SECTION .intvec:CODE:NOROOT(2)
-
-
-
- PUBLIC _vector_table
-
- IMPORT FIQInterrupt
- IMPORT IRQInterrupt
- IMPORT SWInterrupt
- IMPORT DataAbortInterrupt
- IMPORT PrefetchAbortInterrupt
- IMPORT UndefinedException
- IMPORT UndefinedExceptionAddr
- IMPORT PrefetchAbortAddr
- IMPORT DataAbortAddr
-
- IMPORT prof_pc
-
-
-_vector_table
- ARM
- ldr pc,=__iar_program_start
- ldr pc,=Undefined
- ldr pc,=SVCHandler
- ldr pc,=PrefetchAbortHandler
- ldr pc,=DataAbortHandler
- NOP ; Placeholder for address exception vector
- ldr pc,=IRQHandler
- ldr pc,=FIQHandler
-
- SECTION .text:CODE:NOROOT(2)
- REQUIRE _vector_table
-
- ARM
-IRQHandler ; IRQ vector handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
-#ifndef __SOFTFP__
- vpush {d0-d7} /* Store floating point registers */
- vmrs r1, FPSCR
- push {r1}
- vmrs r1, FPEXC
- push {r1}
-#endif
- bl IRQInterrupt ; IRQ vector
-#ifndef __SOFTFP__
- pop {r1} /* Restore floating point registers */
- vmsr FPEXC, r1
- pop {r1}
- vmsr FPSCR, r1
- vpop {d0-d7}
-#endif
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- subs pc, lr, #4 ; adjust return
-
-FIQHandler ; FIQ vector handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
-FIQLoop
- bl FIQInterrupt ; FIQ vector
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- subs pc, lr, #4 ; adjust return
-
-Undefined ; Undefined handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- ldr r0, =UndefinedExceptionAddr
- sub r1, lr, #4
- str r1, [r0] ; Store address of instruction causing undefined exception
-
- bl UndefinedException ; UndefinedException: call C function here
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- movs pc, lr
-
-SVCHandler ; SWI handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- tst r0, #0x20 ; check the T bit
- ldrneh r0, [lr,#-2] ; Thumb mode
- bicne r0, r0, #0xff00 ; Thumb mode
- ldreq r0, [lr,#-4] ; ARM mode
- biceq r0, r0, #0xff000000 ; ARM mode
- bl SWInterrupt ; SWInterrupt: call C function here
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- movs pc, lr ; adjust return
-
-DataAbortHandler ; Data Abort handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- ldr r0, =DataAbortAddr
- sub r1, lr, #8
- str r1, [r0] ; Stores instruction causing data abort
- bl DataAbortInterrupt ;DataAbortInterrupt :call C function here
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- subs pc, lr, #8 ; adjust return
-
-PrefetchAbortHandler ; Prefetch Abort handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- ldr r0, =PrefetchAbortAddr
- sub r1, lr, #4
- str r1, [r0] ; Stores instruction causing prefetch abort */
- bl PrefetchAbortInterrupt ; PrefetchAbortInterrupt: call C function here */
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code */
- subs pc, lr, #4 ; adjust return */
-
-
- END
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b7/60abc1585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b7/60abc1585243001d18b399c1eb9b3628
deleted file mode 100644
index ef8a0e6..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b7/60abc1585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,43 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm_iccarm.c
-*
-* This file contains functions for ARM register handling.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 3.12a asa 11/2/13 First Release
-*
-*
-******************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xpseudo_asm_iccarm.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-/* embedded assembler instructions */
-s32 mfcpsr (void)
-{
- s32 rval;
- asm("mrs %0, cpsr" : "=r"(rval));
- return rval;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b7/92ff82595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b7/92ff82595243001d18b399c1eb9b3628
deleted file mode 100644
index 15c4254..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b7/92ff82595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,51 +0,0 @@
-###############################################################################
-# Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved.
-# SPDX-License-Identifier: MIT
-###############################################################################
-#
-# Makefile for profiler
-#
-#######################################################################
-
-# PROFILE_ARCH_OBJS - Processor Architecture Dependent files defined here
-include ../config.make
-
-AS=mb-as
-COMPILER = mb-gcc
-ARCHIVER = mb-ar
-CP = cp
-COMPILER_FLAGS=-O2
-EXTRA_COMPILER_FLAGS=
-LIB = libxil.a
-DUMMYLIB = libxilprofile.a
-
-CC_FLAGS = $(subst -pg, , $(COMPILER_FLAGS))
-ECC_FLAGS = $(subst -pg, , $(EXTRA_COMPILER_FLAGS))
-
-RELEASEDIR = ../../../../lib
-INCLUDEDIR = ../../../../include
-INCLUDES = -I./. -I${INCLUDEDIR}
-
-OBJS = _profile_init.o _profile_clean.o _profile_timer_hw.o profile_hist.o profile_cg.o
-DUMMYOBJ = dummy.o
-INCLUDEFILES = profile.h mblaze_nt_types.h _profile_timer_hw.h
-
-libs : reallibs dummylibs
-
-reallibs : $(OBJS) $(PROFILE_ARCH_OBJS)
- $(ARCHIVER) -r $(RELEASEDIR)/$(LIB) $(OBJS) $(PROFILE_ARCH_OBJS)
-
-dummylibs : $(DUMMYOBJ)
- $(ARCHIVER) -r $(RELEASEDIR)/$(DUMMYLIB) $(DUMMYOBJ)
-
-%.o:%.c
- $(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
-
-%.o:%.S
- $(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
-
-include:
- $(CP) -rf $(INCLUDEFILES) $(INCLUDEDIR)
-
-clean:
- rm -f $(OBJS) $(PROFILE_ARCH_OBJS) $(LIB)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b7/f1db3e575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b7/f1db3e575243001d18b399c1eb9b3628
deleted file mode 100644
index 0fdda9b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b7/f1db3e575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,484 +0,0 @@
-/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
- * All rights reserved.
- *
- * This package is an SSL implementation written
- * by Eric Young (eay@cryptsoft.com).
- * The implementation was written so as to conform with Netscapes SSL.
- *
- * This library is free for commercial and non-commercial use as long as
- * the following conditions are adhered to. The following conditions
- * apply to all code found in this distribution, be it the RC4, RSA,
- * lhash, DES, etc., code; not just the SSL code. The SSL documentation
- * included with this distribution is covered by the same copyright terms
- * except that the holder is Tim Hudson (tjh@cryptsoft.com).
- *
- * Copyright remains Eric Young's, and as such any Copyright notices in
- * the code are not to be removed.
- * If this package is used in a product, Eric Young should be given attribution
- * as the author of the parts of the library used.
- * This can be in the form of a textual message at program startup or
- * in documentation (online or textual) provided with the package.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * "This product includes cryptographic software written by
- * Eric Young (eay@cryptsoft.com)"
- * The word 'cryptographic' can be left out if the routines from the library
- * being used are not cryptographic related :-).
- * 4. If you include any Windows specific code (or a derivative thereof) from
- * the apps directory (application code) you must include an acknowledgement:
- * "This product includes software written by Tim Hudson (tjh@cryptsoft.com)"
- *
- * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * The licence and distribution terms for any publicly available version or
- * derivative of this code cannot be changed. i.e. this code cannot simply be
- * copied and put under another distribution licence
- * [including the GNU Public Licence.]
- */
-/*****************************************************************************/
-/**
-*
-* @file md5.c
-*
-* Contains code to calculate checksum using md5 algorithm
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 5.00a sgd 05/17/13 Initial release
-*
-*
-*
-*
-* @note
-*
-******************************************************************************/
-/****************************** Include Files *********************************/
-
-#include "md5.h"
-
-/******************************************************************************/
-/**
-*
-* This function sets the memory
-*
-* @param dest
-*
-* @param ch
-*
-* @param count
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-inline void * MD5Memset( void *dest, int ch, u32 count )
-{
- register char *dst8 = (char*)dest;
-
- while( count-- )
- *dst8++ = ch;
-
- return dest;
-}
-
-/******************************************************************************/
-/**
-*
-* This function copy the memory
-*
-* @param dest
-*
-* @param ch
-*
-* @param count
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-inline void * MD5Memcpy( void *dest, const void *src,
- u32 count, boolean doByteSwap )
-{
- register char * dst8 = (char*)dest;
- register char * src8 = (char*)src;
-
- if( doByteSwap == FALSE ) {
- while( count-- )
- *dst8++ = *src8++;
- } else {
- count /= sizeof( u32 );
-
- while( count-- ) {
- dst8[ 0 ] = src8[ 3 ];
- dst8[ 1 ] = src8[ 2 ];
- dst8[ 2 ] = src8[ 1 ];
- dst8[ 3 ] = src8[ 0 ];
-
- dst8 += 4;
- src8 += 4;
- }
- }
-
- return dest;
-}
-
-/******************************************************************************/
-/**
-*
-* This function is the core of the MD5 algorithm,
-* this alters an existing MD5 hash to
-* reflect the addition of 16 longwords of new data. MD5Update blocks
-* the data and converts bytes into longwords for this routine.
-*
-* Use binary integer part of the sine of integers (Radians) as constants.
-* Calculated as:
-*
-* for( i = 0; i < 63; i++ )
-* k[ i ] := floor( abs( sin( i + 1 ) ) × pow( 2, 32 ) )
-*
-* Following number is the per-round shift amount.
-*
-* @param dest
-*
-* @param ch
-*
-* @param count
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-void MD5Transform( u32 *buffer, u32 *intermediate )
-{
- register u32 a, b, c, d;
-
- a = buffer[ 0 ];
- b = buffer[ 1 ];
- c = buffer[ 2 ];
- d = buffer[ 3 ];
-
- MD5_STEP( F1, a, b, c, d, intermediate[ 0 ] + 0xd76aa478, 7 );
- MD5_STEP( F1, d, a, b, c, intermediate[ 1 ] + 0xe8c7b756, 12 );
- MD5_STEP( F1, c, d, a, b, intermediate[ 2 ] + 0x242070db, 17 );
- MD5_STEP( F1, b, c, d, a, intermediate[ 3 ] + 0xc1bdceee, 22 );
- MD5_STEP( F1, a, b, c, d, intermediate[ 4 ] + 0xf57c0faf, 7 );
- MD5_STEP( F1, d, a, b, c, intermediate[ 5 ] + 0x4787c62a, 12 );
- MD5_STEP( F1, c, d, a, b, intermediate[ 6 ] + 0xa8304613, 17 );
- MD5_STEP( F1, b, c, d, a, intermediate[ 7 ] + 0xfd469501, 22 );
- MD5_STEP( F1, a, b, c, d, intermediate[ 8 ] + 0x698098d8, 7 );
- MD5_STEP( F1, d, a, b, c, intermediate[ 9 ] + 0x8b44f7af, 12 );
- MD5_STEP( F1, c, d, a, b, intermediate[ 10 ] + 0xffff5bb1, 17 );
- MD5_STEP( F1, b, c, d, a, intermediate[ 11 ] + 0x895cd7be, 22 );
- MD5_STEP( F1, a, b, c, d, intermediate[ 12 ] + 0x6b901122, 7 );
- MD5_STEP( F1, d, a, b, c, intermediate[ 13 ] + 0xfd987193, 12 );
- MD5_STEP( F1, c, d, a, b, intermediate[ 14 ] + 0xa679438e, 17 );
- MD5_STEP( F1, b, c, d, a, intermediate[ 15 ] + 0x49b40821, 22 );
-
- MD5_STEP( F2, a, b, c, d, intermediate[ 1 ] + 0xf61e2562, 5 );
- MD5_STEP( F2, d, a, b, c, intermediate[ 6 ] + 0xc040b340, 9 );
- MD5_STEP( F2, c, d, a, b, intermediate[ 11 ] + 0x265e5a51, 14 );
- MD5_STEP( F2, b, c, d, a, intermediate[ 0 ] + 0xe9b6c7aa, 20 );
- MD5_STEP( F2, a, b, c, d, intermediate[ 5 ] + 0xd62f105d, 5 );
- MD5_STEP( F2, d, a, b, c, intermediate[ 10 ] + 0x02441453, 9 );
- MD5_STEP( F2, c, d, a, b, intermediate[ 15 ] + 0xd8a1e681, 14 );
- MD5_STEP( F2, b, c, d, a, intermediate[ 4 ] + 0xe7d3fbc8, 20 );
- MD5_STEP( F2, a, b, c, d, intermediate[ 9 ] + 0x21e1cde6, 5 );
- MD5_STEP( F2, d, a, b, c, intermediate[ 14 ] + 0xc33707d6, 9 );
- MD5_STEP( F2, c, d, a, b, intermediate[ 3 ] + 0xf4d50d87, 14 );
- MD5_STEP( F2, b, c, d, a, intermediate[ 8 ] + 0x455a14ed, 20 );
- MD5_STEP( F2, a, b, c, d, intermediate[ 13 ] + 0xa9e3e905, 5 );
- MD5_STEP( F2, d, a, b, c, intermediate[ 2 ] + 0xfcefa3f8, 9 );
- MD5_STEP( F2, c, d, a, b, intermediate[ 7 ] + 0x676f02d9, 14 );
- MD5_STEP( F2, b, c, d, a, intermediate[ 12 ] + 0x8d2a4c8a, 20 );
-
- MD5_STEP( F3, a, b, c, d, intermediate[ 5 ] + 0xfffa3942, 4 );
- MD5_STEP( F3, d, a, b, c, intermediate[ 8 ] + 0x8771f681, 11 );
- MD5_STEP( F3, c, d, a, b, intermediate[ 11 ] + 0x6d9d6122, 16 );
- MD5_STEP( F3, b, c, d, a, intermediate[ 14 ] + 0xfde5380c, 23 );
- MD5_STEP( F3, a, b, c, d, intermediate[ 1 ] + 0xa4beea44, 4 );
- MD5_STEP( F3, d, a, b, c, intermediate[ 4 ] + 0x4bdecfa9, 11 );
- MD5_STEP( F3, c, d, a, b, intermediate[ 7 ] + 0xf6bb4b60, 16 );
- MD5_STEP( F3, b, c, d, a, intermediate[ 10 ] + 0xbebfbc70, 23 );
- MD5_STEP( F3, a, b, c, d, intermediate[ 13 ] + 0x289b7ec6, 4 );
- MD5_STEP( F3, d, a, b, c, intermediate[ 0 ] + 0xeaa127fa, 11 );
- MD5_STEP( F3, c, d, a, b, intermediate[ 3 ] + 0xd4ef3085, 16 );
- MD5_STEP( F3, b, c, d, a, intermediate[ 6 ] + 0x04881d05, 23 );
- MD5_STEP( F3, a, b, c, d, intermediate[ 9 ] + 0xd9d4d039, 4 );
- MD5_STEP( F3, d, a, b, c, intermediate[ 12 ] + 0xe6db99e5, 11 );
- MD5_STEP( F3, c, d, a, b, intermediate[ 15 ] + 0x1fa27cf8, 16 );
- MD5_STEP( F3, b, c, d, a, intermediate[ 2 ] + 0xc4ac5665, 23 );
-
- MD5_STEP( F4, a, b, c, d, intermediate[ 0 ] + 0xf4292244, 6 );
- MD5_STEP( F4, d, a, b, c, intermediate[ 7 ] + 0x432aff97, 10 );
- MD5_STEP( F4, c, d, a, b, intermediate[ 14 ] + 0xab9423a7, 15 );
- MD5_STEP( F4, b, c, d, a, intermediate[ 5 ] + 0xfc93a039, 21 );
- MD5_STEP( F4, a, b, c, d, intermediate[ 12 ] + 0x655b59c3, 6 );
- MD5_STEP( F4, d, a, b, c, intermediate[ 3 ] + 0x8f0ccc92, 10 );
- MD5_STEP( F4, c, d, a, b, intermediate[ 10 ] + 0xffeff47d, 15 );
- MD5_STEP( F4, b, c, d, a, intermediate[ 1 ] + 0x85845dd1, 21 );
- MD5_STEP( F4, a, b, c, d, intermediate[ 8 ] + 0x6fa87e4f, 6 );
- MD5_STEP( F4, d, a, b, c, intermediate[ 15 ] + 0xfe2ce6e0, 10 );
- MD5_STEP( F4, c, d, a, b, intermediate[ 6 ] + 0xa3014314, 15 );
- MD5_STEP( F4, b, c, d, a, intermediate[ 13 ] + 0x4e0811a1, 21 );
- MD5_STEP( F4, a, b, c, d, intermediate[ 4 ] + 0xf7537e82, 6 );
- MD5_STEP( F4, d, a, b, c, intermediate[ 11 ] + 0xbd3af235, 10 );
- MD5_STEP( F4, c, d, a, b, intermediate[ 2 ] + 0x2ad7d2bb, 15 );
- MD5_STEP( F4, b, c, d, a, intermediate[ 9 ] + 0xeb86d391, 21 );
-
- buffer[ 0 ] += a;
- buffer[ 1 ] += b;
- buffer[ 2 ] += c;
- buffer[ 3 ] += d;
-
-}
-
-/******************************************************************************/
-/**
-*
-* This function Start MD5 accumulation
-* Set bit count to 0 and buffer to mysterious initialization constants
-*
-* @param
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-inline void MD5Init( MD5Context *context )
-{
-
- context->buffer[ 0 ] = 0x67452301;
- context->buffer[ 1 ] = 0xefcdab89;
- context->buffer[ 2 ] = 0x98badcfe;
- context->buffer[ 3 ] = 0x10325476;
-
- context->bits[ 0 ] = 0;
- context->bits[ 1 ] = 0;
-
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function updates context to reflect the concatenation of another
-* buffer full of bytes
-*
-* @param
-*
-* @param
-*
-* @param
-*
-* @param
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-inline void MD5Update( MD5Context *context, u8 *buffer,
- u32 len, boolean doByteSwap )
-{
- register u32 temp;
- register u8 * p;
-
- /*
- * Update bitcount
- */
-
- temp = context->bits[ 0 ];
-
- if( ( context->bits[ 0 ] = temp + ( (u32)len << 3 ) ) < temp ) {
- /*
- * Carry from low to high
- */
- context->bits[ 1 ]++;
- }
-
- context->bits[ 1 ] += len >> 29;
-
- /*
- * Bytes already in shsInfo->data
- */
-
- temp = ( temp >> 3 ) & 0x3f;
-
- /*
- * Handle any leading odd-sized chunks
- */
-
- if( temp ) {
- p = (u8 *)context->intermediate + temp;
-
- temp = MD5_SIGNATURE_BYTE_SIZE - temp;
-
- if( len < temp ) {
- MD5Memcpy( p, buffer, len, doByteSwap );
- return;
- }
-
- MD5Memcpy( p, buffer, temp, doByteSwap );
-
- MD5Transform( context->buffer, (u32 *)context->intermediate );
-
- buffer += temp;
- len -= temp;
-
- }
-
- /*
- * Process data in 64-byte, 512 bit, chunks
- */
-
- while( len >= MD5_SIGNATURE_BYTE_SIZE ) {
- MD5Memcpy( context->intermediate, buffer, MD5_SIGNATURE_BYTE_SIZE,
- doByteSwap );
-
- MD5Transform( context->buffer, (u32 *)context->intermediate );
-
- buffer += MD5_SIGNATURE_BYTE_SIZE;
- len -= MD5_SIGNATURE_BYTE_SIZE;
-
- }
-
- /*
- * Handle any remaining bytes of data
- */
- MD5Memcpy( context->intermediate, buffer, len, doByteSwap );
-
-}
-
-/******************************************************************************/
-/**
-*
-* This function final wrap-up - pad to 64-byte boundary with the bit pattern
-* 1 0* (64-bit count of bits processed, MSB-first
-*
-* @param
-*
-* @param
-*
-* @param
-*
-* @param
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-inline void MD5Final( MD5Context *context, u8 *digest,
- boolean doByteSwap )
-{
- u32 count;
- u8 * p;
-
- /*
- * Compute number of bytes mod 64
- */
- count = ( context->bits[ 0 ] >> 3 ) & 0x3F;
-
- /*
- * Set the first char of padding to 0x80. This is safe since there is
- * always at least one byte free
- */
- p = context->intermediate + count;
- *p++ = 0x80;
-
- /*
- * Bytes of padding needed to make 64 bytes
- */
- count = MD5_SIGNATURE_BYTE_SIZE - 1 - count;
-
- /*
- * Pad out to 56 mod 64
- */
- if( count < 8 ) {
- /*
- * Two lots of padding: Pad the first block to 64 bytes
- */
- MD5Memset( p, 0, count );
-
- MD5Transform( context->buffer, (u32 *)context->intermediate );
-
- /*
- * Now fill the next block with 56 bytes
- */
- MD5Memset( context->intermediate, 0, 56 );
- } else {
- /*
- * Pad block to 56 bytes
- */
- MD5Memset( p, 0, count - 8 );
- }
-
- /*
- * Append length in bits and transform
- */
- ( (u32 *)context->intermediate )[ 14 ] = context->bits[ 0 ];
- ( (u32 *)context->intermediate )[ 15 ] = context->bits[ 1 ];
-
- MD5Transform( context->buffer, (u32 *)context->intermediate );
-
- /*
- * Now return the digest
- */
- MD5Memcpy( digest, context->buffer, 16, doByteSwap );
-}
-
-/******************************************************************************/
-/**
-*
-* This function calculate and store in 'digest' the MD5 digest of 'len' bytes at
-* 'input'. 'digest' must have enough space to hold 16 bytes
-*
-* @param
-*
-* @param
-*
-* @param
-*
-* @param
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-void md5( u8 *input, u32 len, u8 *digest, boolean doByteSwap )
-{
- MD5Context context;
-
- MD5Init( &context );
-
- MD5Update( &context, input, len, doByteSwap );
-
- MD5Final( &context, digest, doByteSwap );
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b8/50348d555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b8/50348d555243001d18b399c1eb9b3628
deleted file mode 100644
index 5c98317..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b8/50348d555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,38 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: MIT
-*
-******************************************************************************/
-#ifndef UNDEFINE_FILE_OPS
-#include "xil_printf.h"
-#include "xparameters.h"
-
-/* Stub for read() sys-call */
-__attribute__((weak)) s32 _sys_read(__attribute__((unused)) u32 fh,
- __attribute__((unused)) u8 *buf,
- u32 len,
- __attribute__((unused)) s32 mode)
-{
-#ifdef STDIN_BASEADDRESS
- u32 i;
- s32 numbytes = 0;
- char8* LocalBuf = (char8 *)buf;
-
- if(LocalBuf != NULL) {
- for (i = 0; i < len; i++) {
- numbytes++;
- *(LocalBuf + i) = inbyte();
- if ((*(LocalBuf + i) == '\n' ) ||
- (*(LocalBuf + i) == '\r')) {
- break;
- }
- }
- }
-
- return numbytes;
-#endif
- /* Return the number of character read */
- return 0;
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b8/92b365595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b8/92b365595243001d18b399c1eb9b3628
deleted file mode 100644
index 362b6e9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b8/92b365595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,59 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2008 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file microblaze_interrupts_i.h
-*
-* This header file contains identifiers and low-level driver functions (or
-* macros) that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-* High-level driver functions are defined in xintc.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Date Changes
-* ----- -------- -----------------------------------------------
-* 1.00b 10/03/03 First release
-*
-* translation_table.S contains a static page table required by MMU for
-* cortex-A53. This translation table is flat mapped (input address = output
-* address) with default memory attributes defined for zynq ultrascale+
-* architecture. It utilizes translation granual size of 4KB with 2MB section
-* size for initial 4GB memory and 1GB section size for memory after 4GB.
-* The overview of translation table memory attributes is described below.
-*
-*| | Memory Range | Definition in Translation Table |
-*|-----------------------|-----------------------------|-----------------------------------|
-*| DDR | 0x0000000000 - 0x007FFFFFFF | Normal write-back Cacheable |
-*| PL | 0x0080000000 - 0x00BFFFFFFF | Strongly Ordered |
-*| QSPI, lower PCIe | 0x00C0000000 - 0x00EFFFFFFF | Strongly Ordere |
-*| Reserved | 0x00F0000000 - 0x00F7FFFFFF | Unassigned |
-*| STM Coresight | 0x00F8000000 - 0x00F8FFFFFF | Strongly Ordered |
-*| GIC | 0x00F9000000 - 0x00F91FFFFF | Strongly Ordered |
-*| Reserved | 0x00F9200000 - 0x00FCFFFFFF | Unassigned |
-*| FPS, LPS slaves | 0x00FD000000 - 0x00FFBFFFFF | Strongly Ordered |
-*| CSU, PMU | 0x00FFC00000 - 0x00FFDFFFFF | Strongly Ordered |
-*| TCM, OCM | 0x00FFE00000 - 0x00FFFFFFFF | Normal inner write-back cacheable |
-*| Reserved | 0x0100000000 - 0x03FFFFFFFF | Unassigned |
-*| PL, PCIe | 0x0400000000 - 0x07FFFFFFFF | Strongly Ordered |
-*| DDR | 0x0800000000 - 0x0FFFFFFFFF | Normal inner write-back cacheable |
-*| PL, PCIe | 0x1000000000 - 0xBFFFFFFFFF | Strongly Ordered |
-*| Reserved | 0xC000000000 - 0xFFFFFFFFFF | Unassigned |
-*
-* @note
-*
-* For DDR region 0x0000000000 - 0x007FFFFFFF, a system where DDR is less than
-* 2GB, region after DDR and before PL is marked as undefined/reserved in
-* translation table. Region 0xF9100000 - 0xF91FFFFF is reserved memory in
-* 0x00F9000000 - 0x00F91FFFFF range, but it is marked as strongly ordered
-* because minimum section size in translation table section is 2MB. Region
-* 0x00FFC00000 - 0x00FFDFFFFF contains CSU and PMU memory which are marked as
-* Device since it is less than 1MB and falls in a region with device memory.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00 pkp 05/21/14 Initial version
-* 5.04 pkp 12/18/15 Updated the address map according to proper address map
-* 6.0 mus 07/20/16 Added warning for ddrless HW design CR-954977
-* 6.2 pkp 12/14/16 DDR memory in 0x800000000 - 0xFFFFFFFFF range is marked
-* as normal writeback for the size defined in hdf and rest
-* of the memory in that 32GB range is marked as reserved.
-* 6.4 mus 08/10/17 Marked memory as a outer shareable for EL1 NS execution,
-* to support CCI enabled IP's.
-*
-*
-******************************************************************************/
-#include "xparameters.h"
-#include "bspconfig.h"
-
- .globl MMUTableL0
- .globl MMUTableL1
- .globl MMUTableL2
-
- .set reserved, 0x0 /* Fault*/
- #if EL1_NONSECURE
- .set Memory, 0x405 | (2 << 8) | (0x0) /* normal writeback write allocate outer shared read write */
- #else
- .set Memory, 0x405 | (3 << 8) | (0x0) /* normal writeback write allocate inner shared read write */
- #endif
- .set Device, 0x409 | (1 << 53)| (1 << 54) |(0x0) /* strongly ordered read write non executable*/
- .section .mmu_tbl0,"a"
-
-MMUTableL0:
-
-.set SECT, MMUTableL1 /* 0x0000_0000 - 0x7F_FFFF_FFFF */
-.8byte SECT + 0x3
-.set SECT, MMUTableL1+0x1000 /* 0x80_0000_0000 - 0xFF_FFFF_FFFF */
-.8byte SECT + 0x3
-
- .section .mmu_tbl1,"a"
-
-MMUTableL1:
-
-.set SECT, MMUTableL2 /* 0x0000_0000 - 0x3FFF_FFFF */
-.8byte SECT + 0x3 /* 1GB DDR */
-
-.rept 0x3 /* 0x4000_0000 - 0xFFFF_FFFF */
-.set SECT, SECT + 0x1000 /*1GB DDR, 1GB PL, 2GB other devices n memory */
-.8byte SECT + 0x3
-.endr
-
-.set SECT,0x100000000
-.rept 0xC /* 0x0001_0000_0000 - 0x0003_FFFF_FFFF */
-.8byte SECT + reserved /* 12GB Reserved */
-.set SECT, SECT + 0x40000000
-.endr
-
-.rept 0x10 /* 0x0004_0000_0000 - 0x0007_FFFF_FFFF */
-.8byte SECT + Device /* 8GB PL, 8GB PCIe */
-.set SECT, SECT + 0x40000000
-.endr
-
-
-#ifdef XPAR_PSU_DDR_1_S_AXI_BASEADDR
-.set DDR_1_START, XPAR_PSU_DDR_1_S_AXI_BASEADDR
-.set DDR_1_END, XPAR_PSU_DDR_1_S_AXI_HIGHADDR
-.set DDR_1_SIZE, (DDR_1_END - DDR_1_START)+1
-.if DDR_1_SIZE > 0x800000000
-/* If DDR size is larger than 32GB, truncate to 32GB */
-.set DDR_1_REG, 0x20
-.else
-.set DDR_1_REG, DDR_1_SIZE/0x40000000
-.endif
-#else
-.set DDR_1_REG, 0
-#warning "There's no DDR_1 in the HW design. MMU translation table marks 32 GB DDR address space as undefined"
-#endif
-
-.set UNDEF_1_REG, 0x20 - DDR_1_REG
-
-.rept DDR_1_REG /* DDR based on size in hdf*/
-.8byte SECT + Memory
-.set SECT, SECT+0x40000000
-.endr
-
-.rept UNDEF_1_REG /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-
-.rept 0x1C0 /* 0x0010_0000_0000 - 0x007F_FFFF_FFFF */
-.8byte SECT + Device /* 448 GB PL */
-.set SECT, SECT + 0x40000000
-.endr
-
-
-.rept 0x100 /* 0x0080_0000_0000 - 0x00BF_FFFF_FFFF */
-.8byte SECT + Device /* 256GB PCIe */
-.set SECT, SECT + 0x40000000
-.endr
-
-
-.rept 0x100 /* 0x00C0_0000_0000 - 0x00FF_FFFF_FFFF */
-.8byte SECT + reserved /* 256GB reserved */
-.set SECT, SECT + 0x40000000
-.endr
-
-
-.section .mmu_tbl2,"a"
-
-MMUTableL2:
-
-.set SECT, 0
-
-#ifdef XPAR_PSU_DDR_0_S_AXI_BASEADDR
-.set DDR_0_START, XPAR_PSU_DDR_0_S_AXI_BASEADDR
-.set DDR_0_END, XPAR_PSU_DDR_0_S_AXI_HIGHADDR
-.set DDR_0_SIZE, (DDR_0_END - DDR_0_START)+1
-.if DDR_0_SIZE > 0x80000000
-/* If DDR size is larger than 2GB, truncate to 2GB */
-.set DDR_0_REG, 0x400
-.else
-.set DDR_0_REG, DDR_0_SIZE/0x200000
-.endif
-#else
-.set DDR_0_REG, 0
-#warning "There's no DDR_0 in the HW design. MMU translation table marks 2 GB DDR address space as undefined"
-#endif
-
-.set UNDEF_0_REG, 0x400 - DDR_0_REG
-
-.rept DDR_0_REG /* DDR based on size in hdf*/
-.8byte SECT + Memory
-.set SECT, SECT+0x200000
-.endr
-
-.rept UNDEF_0_REG /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x0200 /* 0x8000_0000 - 0xBFFF_FFFF */
-.8byte SECT + Device /* 1GB lower PL */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x0100 /* 0xC000_0000 - 0xDFFF_FFFF */
-.8byte SECT + Device /* 512MB QSPI */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x080 /* 0xE000_0000 - 0xEFFF_FFFF */
-.8byte SECT + Device /* 256MB lower PCIe */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x040 /* 0xF000_0000 - 0xF7FF_FFFF */
-.8byte SECT + reserved /* 128MB Reserved */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x8 /* 0xF800_0000 - 0xF8FF_FFFF */
-.8byte SECT + Device /* 16MB coresight */
-.set SECT, SECT+0x200000
-.endr
-
-/* 1MB RPU LLP is marked for 2MB region as the minimum block size in
- translation table is 2MB and adjacent 63MB reserved region is
- converted to 62MB */
-
-.rept 0x1 /* 0xF900_0000 - 0xF91F_FFFF */
-.8byte SECT + Device /* 2MB RPU low latency port */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x1F /* 0xF920_0000 - 0xFCFF_FFFF */
-.8byte SECT + reserved /* 62MB Reserved */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x8 /* 0xFD00_0000 - 0xFDFF_FFFF */
-.8byte SECT + Device /* 16MB FPS */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0xE /* 0xFE00_0000 - 0xFFBF_FFFF */
-.8byte SECT + Device /* 28MB LPS */
-.set SECT, SECT+0x200000
-.endr
-
- /* 0xFFC0_0000 - 0xFFDF_FFFF */
-.8byte SECT + Device /*2MB PMU/CSU */
-
-.set SECT, SECT+0x200000 /* 0xFFE0_0000 - 0xFFFF_FFFF*/
-.8byte SECT + Memory /*2MB OCM/TCM*/
-
-.end
-/**
-* @} End of "addtogroup a53_64_boot_code".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b9/01fe36555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b9/01fe36555243001d18b399c1eb9b3628
deleted file mode 100644
index c584f31..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b9/01fe36555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,111 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************
-*
-* @file sleep.c
-*
-* This function provides a second delay using the Global Timer register in
-* the ARM Cortex A53 MP core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/29/14 First release
-* 5.04 pkp 28/01/16 Modified the sleep API to configure Time Stamp
-* generator only when disable using frequency from
-* xparamters.h instead of hardcoding
-* 5.05 pkp 13/04/16 Modified sleep routine to call XTime_StartTimer
-* which enables timer only when it is disabled and
-* read counter value directly from register instead
-* of calling XTime_GetTime for optimization
-* 6.0 asa 08/15/16 Updated the sleep/usleep signature. Fix for CR#956899.
-* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
-* implementation. Now sleep routines will use Timer
-* specified by the user (i.e. Global timer/TTC timer)
-* srm 01/11/18 Fixed the compilation warning.
-* 7.5 dp 01/05/21 Updated COUNTS_PER_USECOND macros to round it off to
-* nearest possible value so that delta error in time
-* calculations can be minimized.
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "sleep.h"
-#include "xtime_l.h"
-#include "xparameters.h"
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#include "xil_sleeptimer.h"
-#endif
-/**************************** Constant Definitions ************************/
-
-/* Global Timer is always clocked at half of the CPU frequency */
-#define COUNTS_PER_USECOND ((COUNTS_PER_SECOND + 500000)/1000000)
-
-/************************************************************************/
-#if !defined (SLEEP_TIMER_BASEADDR)
-static void sleep_common(u32 n, u32 count)
-{
- XTime tEnd, tCur;
- /* Start global timer counter, it will only be enabled if it is disabled */
- XTime_StartTimer();
-
- tCur = mfcp(CNTPCT_EL0);
- tEnd = tCur + (((XTime) n) * count);
- do {
- tCur = mfcp(CNTPCT_EL0);
- } while (tCur < tEnd);
-}
-#endif
-/*****************************************************************************/
-/**
-*
-* This API gives a delay in microseconds
-*
-* @param useconds requested
-*
-* @return 0 if the delay can be achieved, -1 if the requested delay
-* is out of range
-*
-* @note None.
-*
-****************************************************************************/
-int usleep_A53(unsigned long useconds)
-{
-#if defined (SLEEP_TIMER_BASEADDR)
- Xil_SleepTTCCommon(useconds, COUNTS_PER_USECOND);
-#else
- sleep_common((u32)useconds, COUNTS_PER_USECOND);
-#endif
-
- return 0;
-}
-
-/*****************************************************************************/
-/*
-*
-* This API is used to provide delays in seconds
-*
-* @param seconds requested
-*
-* @return 0 always
-*
-* @note None.
-*
-****************************************************************************/
-unsigned sleep_A53(unsigned int seconds)
-{
-#if defined (SLEEP_TIMER_BASEADDR)
- Xil_SleepTTCCommon(seconds, COUNTS_PER_SECOND);
-#else
- sleep_common(seconds, COUNTS_PER_SECOND);
-#endif
-
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b9/508a49575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b9/508a49575243001d18b399c1eb9b3628
deleted file mode 100644
index a44f0d5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/b9/508a49575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,82 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file pcap.h
-*
-* This file contains the interface for intiializing and accessing the PCAP
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 02/10/10 Initial release
-* 2.00a mb 16/08/12 Added the macros and function prototypes
-* 15.00a gan 07/21/16 953654 -(2016.3)FSBL -In pcap.c/pcap.h/main.c,
-* Fabric Initialization sequence is modified to check
-* the PL power before sequence starts and checking INIT_B
-* reset status twice in case of failure.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 First release
-* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
-* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
-* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
-* Define LONG and ULONG datatypes and mask values
-* 7.00 mus 01/07/19 Add cpp extern macro
-* 7.1 aru 08/19/19 Shift the value in UPPER_32_BITS only if it
-* is 64-bit processor
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-#ifndef XIL_TYPES_H /* prevent circular inclusions */
-#define XIL_TYPES_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include
-#include
-
-/************************** Constant Definitions *****************************/
-
-#ifndef TRUE
-# define TRUE 1U
-#endif
-
-#ifndef FALSE
-# define FALSE 0U
-#endif
-
-#ifndef NULL
-#define NULL 0U
-#endif
-
-#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be
- assigend to "IsReady" member of driver
- instance to indicate that driver
- instance is initialized and ready to use. */
-#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to
- "IsStarted" member of driver instance
- to indicate that driver instance is
- started and it can be enabled. */
-
-/* @name New types
- * New simple types.
- * @{
- */
-#ifndef __KERNEL__
-#ifndef XBASIC_TYPES_H
-/*
- * guarded against xbasic_types.h.
- */
-typedef uint8_t u8;
-typedef uint16_t u16;
-typedef uint32_t u32;
-/** @}*/
-#define __XUINT64__
-typedef struct
-{
- u32 Upper;
- u32 Lower;
-} Xuint64;
-
-
-/*****************************************************************************/
-/**
-* @brief Return the most significant half of the 64 bit data type.
-*
-* @param x is the 64 bit word.
-*
-* @return The upper 32 bits of the 64 bit word.
-*
-******************************************************************************/
-#define XUINT64_MSW(x) ((x).Upper)
-
-/*****************************************************************************/
-/**
-* @brief Return the least significant half of the 64 bit data type.
-*
-* @param x is the 64 bit word.
-*
-* @return The lower 32 bits of the 64 bit word.
-*
-******************************************************************************/
-#define XUINT64_LSW(x) ((x).Lower)
-
-#endif /* XBASIC_TYPES_H */
-
-/*
- * xbasic_types.h does not typedef s* or u64
- */
-/** @{ */
-typedef char char8;
-typedef int8_t s8;
-typedef int16_t s16;
-typedef int32_t s32;
-typedef int64_t s64;
-typedef uint64_t u64;
-typedef int sint32;
-
-typedef intptr_t INTPTR;
-typedef uintptr_t UINTPTR;
-typedef ptrdiff_t PTRDIFF;
-/** @}*/
-#if !defined(LONG) || !defined(ULONG)
-typedef long LONG;
-typedef unsigned long ULONG;
-#endif
-
-#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
-#define ULONG64_LO_MASK ~ULONG64_HI_MASK
-
-#else
-#include
-#endif
-
-/** @{ */
-/**
- * This data type defines an interrupt handler for a device.
- * The argument points to the instance of the component
- */
-typedef void (*XInterruptHandler) (void *InstancePtr);
-
-/**
- * This data type defines an exception handler for a processor.
- * The argument points to the instance of the component
- */
-typedef void (*XExceptionHandler) (void *InstancePtr);
-
-/**
- * @brief Returns 32-63 bits of a number.
- * @param n : Number being accessed.
- * @return Bits 32-63 of number.
- *
- * @note A basic shift-right of a 64- or 32-bit quantity.
- * Use this to suppress the "right shift count >= width of type"
- * warning when that quantity is 32-bits.
- */
-#if defined (__aarch64__) || defined (__arch64__)
-#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
-#else
-#define UPPER_32_BITS(n) 0U
-#endif
-/**
- * @brief Returns 0-31 bits of a number
- * @param n : Number being accessed.
- * @return Bits 0-31 of number
- */
-#define LOWER_32_BITS(n) ((u32)(n))
-
-
-
-
-/************************** Constant Definitions *****************************/
-
-#ifndef TRUE
-#define TRUE 1U
-#endif
-
-#ifndef FALSE
-#define FALSE 0U
-#endif
-
-#ifndef NULL
-#define NULL 0U
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
- *@endcond
- */
-/**
-* @} End of "addtogroup common_types".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ba/509a8e525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ba/509a8e525243001d18b399c1eb9b3628
deleted file mode 100644
index 6f40407..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ba/509a8e525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,52 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xcoresightpsdcc.h
-* @addtogroup coresightps_dcc_v1_8
-* @{
-* @details
-*
-* CoreSight driver component.
-*
-* The coresight is a part of debug communication channel (DCC) group. Jtag UART
-* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
-* ARM target in XSDB console before running the jtag terminal command. Using the
-* coresight driver component, the output stream can be directed to a log file.
-*
-* @note None.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------
-* 1.00 kvn 02/14/15 First release
-* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
-* kvn 08/18/15 Modified Makefile according to compiler changes.
-* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
-* for MB BSPs. Instead it throws up a warning. This
-* fixes the CR#953056.
-* 1.5 sne 01/19/19 Fixed MISRA-C Violations CR#1025101.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#ifndef XCORESIGHTPSDCC_H /* prevent circular inclusions */
-#define XCORESIGHTPSDCC_H /* by using protection macros */
-#ifndef __MICROBLAZE__
-#include
-
-void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
-
-u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
-#endif
-#endif
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ba/709134595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ba/709134595243001d18b399c1eb9b3628
deleted file mode 100644
index e8b87b5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ba/709134595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,176 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_assert.h
-*
-* @addtogroup common_assert_apis Assert APIs and Macros
-*
-* The xil_assert.h file contains assert related functions and macros.
-* Assert APIs/Macros specifies that a application program satisfies certain
-* conditions at particular points in its execution. These function can be
-* used by application programs to ensure that, application code is satisfying
-* certain conditions.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 First release
-* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_ASSERT_H /* prevent circular inclusions */
-#define XIL_ASSERT_H /* by using protection macros */
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-
-
-/************************** Constant Definitions *****************************/
-
-#define XIL_ASSERT_NONE 0U
-#define XIL_ASSERT_OCCURRED 1U
-#define XNULL NULL
-
-extern u32 Xil_AssertStatus;
-extern s32 Xil_AssertWait;
-extern void Xil_Assert(const char8 *File, s32 Line);
-/**
- *@endcond
- */
-void XNullHandler(void *NullParameter);
-
-/**
- * This data type defines a callback to be invoked when an
- * assert occurs. The callback is invoked only when asserts are enabled
- */
-typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#ifndef NDEBUG
-
-/*****************************************************************************/
-/**
-* @brief This assert macro is to be used for void functions. This in
-* conjunction with the Xil_AssertWait boolean can be used to
-* accommodate tests so that asserts which fail allow execution to
-* continue.
-*
-* @param Expression: expression to be evaluated. If it evaluates to
-* false, the assert occurs.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertVoid(Expression) \
-{ \
- if (Expression) { \
- Xil_AssertStatus = XIL_ASSERT_NONE; \
- } else { \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* @brief This assert macro is to be used for functions that do return a
-* value. This in conjunction with the Xil_AssertWait boolean can be
-* used to accommodate tests so that asserts which fail allow execution
-* to continue.
-*
-* @param Expression: expression to be evaluated. If it evaluates to false,
-* the assert occurs.
-*
-* @return Returns 0 unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertNonvoid(Expression) \
-{ \
- if (Expression) { \
- Xil_AssertStatus = XIL_ASSERT_NONE; \
- } else { \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return 0; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* @brief Always assert. This assert macro is to be used for void functions.
-* Use for instances where an assert should always occur.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertVoidAlways() \
-{ \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return; \
-}
-
-/*****************************************************************************/
-/**
-* @brief Always assert. This assert macro is to be used for functions that
-* do return a value. Use for instances where an assert should always
-* occur.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertNonvoidAlways() \
-{ \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return 0; \
-}
-
-
-#else
-
-#define Xil_AssertVoid(Expression)
-#define Xil_AssertVoidAlways()
-#define Xil_AssertNonvoid(Expression)
-#define Xil_AssertNonvoidAlways()
-
-#endif
-
-/************************** Function Prototypes ******************************/
-
-void Xil_AssertSetCallback(Xil_AssertCallback Routine);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_assert_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ba/b1341f595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ba/b1341f595243001d18b399c1eb9b3628
deleted file mode 100644
index ff13d1e..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ba/b1341f595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,610 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_mpu.c
-*
-* This file provides APIs for enabling/disabling MPU and setting the memory
-* attributes for sections, in the MPU translation table.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00 pkp 02/10/14 Initial version
-* 6.2 mus 01/27/17 Updated to support IAR compiler
-* 6.4 asa 08/16/17 Added many APIs for MPU access to make MPU usage
-* user-friendly. The APIs added are: Xil_UpdateMPUConfig,
-* Xil_GetMPUConfig, Xil_GetNumOfFreeRegions,
-* Xil_GetNextMPURegion, Xil_DisableMPURegionByRegNum,
-* Xil_GetMPUFreeRegMask, Xil_SetMPURegionByRegNum, and
-* Xil_InitializeExistingMPURegConfig.
-* Added a new array of structure of type XMpuConfig to
-* represent the MPU configuration table.
-* 6.8 aru 07/02/18 Returned the pointer instead of address
-* of that pointer in Xil_MemMap().
-* 7.5 asa 03/01/21 Ensure that Mpu_Config does not stay in .boot/.vector
-* sections which generally should be executable code
-* which can be allocated and not written.
-* Mpu_Config array is populated during boot time, hence
-* cannot be placed in .bss or .data section. Putting
-* Mpu_Config in a new .bootdata section.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-#include "xil_mpu.h"
-#include "xdebug.h"
-#include "xstatus.h"
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-#define MPU_REGION_SIZE_MIN 0x20
-/************************** Variable Definitions *****************************/
-
-static const struct {
- u64 size;
- unsigned int encoding;
-}region_size[] = {
- { 0x20, REGION_32B },
- { 0x40, REGION_64B },
- { 0x80, REGION_128B },
- { 0x100, REGION_256B },
- { 0x200, REGION_512B },
- { 0x400, REGION_1K },
- { 0x800, REGION_2K },
- { 0x1000, REGION_4K },
- { 0x2000, REGION_8K },
- { 0x4000, REGION_16K },
- { 0x8000, REGION_32K },
- { 0x10000, REGION_64K },
- { 0x20000, REGION_128K },
- { 0x40000, REGION_256K },
- { 0x80000, REGION_512K },
- { 0x100000, REGION_1M },
- { 0x200000, REGION_2M },
- { 0x400000, REGION_4M },
- { 0x800000, REGION_8M },
- { 0x1000000, REGION_16M },
- { 0x2000000, REGION_32M },
- { 0x4000000, REGION_64M },
- { 0x8000000, REGION_128M },
- { 0x10000000, REGION_256M },
- { 0x20000000, REGION_512M },
- { 0x40000000, REGION_1G },
- { 0x80000000, REGION_2G },
- { 0x100000000, REGION_4G },
-};
-
-#if defined (__GNUC__)
-XMpu_Config Mpu_Config __attribute__((section(".bootdata")));
-#elif defined (__ICCARM__)
-#pragma default_function_attributes = @ ".bootdata"
-XMpu_Config Mpu_Config;
-#endif
-
-/************************** Function Prototypes ******************************/
-void Xil_InitializeExistingMPURegConfig(void);
-/*****************************************************************************/
-/**
-* @brief This function sets the memory attributes for a section covering
-* 1MB, of memory in the translation table.
-*
-* @param addr: 32-bit address for which memory attributes need to be set.
-* @param attrib: Attribute for the given memory region.
-* @return None.
-*
-*
-******************************************************************************/
-void Xil_SetTlbAttributes(INTPTR addr, u32 attrib)
-{
- INTPTR Localaddr = addr;
- Localaddr &= (~(0xFFFFFU));
- /* Setting the MPU region with given attribute with 1MB size */
- Xil_SetMPURegion(Localaddr, 0x100000, attrib);
-}
-
-/*****************************************************************************/
-/**
-* @brief Set the memory attributes for a section of memory in the
-* translation table.
-*
-* @param addr: 32-bit address for which memory attributes need to be set..
-* @param size: size is the size of the region.
-* @param attrib: Attribute for the given memory region.
-* @return None.
-*
-*
-******************************************************************************/
-u32 Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib)
-{
- u32 Regionsize = 0;
- INTPTR Localaddr = addr;
- u32 NextAvailableMemRegion;
- unsigned int i;
-
- NextAvailableMemRegion = Xil_GetNextMPURegion();
- if (NextAvailableMemRegion == 0xFF) {
- xdbg_printf(DEBUG, "No regions available\r\n");
- return XST_FAILURE;
- }
-
- Xil_DCacheFlush();
- Xil_ICacheInvalidate();
-
- mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,NextAvailableMemRegion);
- isb();
-
- /* Lookup the size. */
- for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) {
- if (size <= region_size[i].size) {
- Regionsize = region_size[i].encoding;
- break;
- }
- }
-
- Localaddr &= ~(region_size[i].size - 1);
-
- Regionsize <<= 1;
- Regionsize |= REGION_EN;
- dsb();
- mtcp(XREG_CP15_MPU_REG_BASEADDR, Localaddr); /* Set base address of a region */
- mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL, attrib); /* Set the control attribute */
- mtcp(XREG_CP15_MPU_REG_SIZE_EN, Regionsize); /* set the region size and enable it*/
- dsb();
- isb();
- Xil_UpdateMPUConfig(NextAvailableMemRegion, Localaddr, Regionsize, attrib);
- return XST_SUCCESS;
-}
-/*****************************************************************************/
-/**
-* @brief Enable MPU for Cortex R5 processor. This function invalidates I
-* cache and flush the D Caches, and then enables the MPU.
-*
-* @return None.
-*
-******************************************************************************/
-void Xil_EnableMPU(void)
-{
- u32 CtrlReg, Reg;
- s32 DCacheStatus=0, ICacheStatus=0;
- /* enable caches only if they are disabled */
-#if defined (__GNUC__)
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
-#endif
- if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) {
- DCacheStatus=1;
- }
- if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) {
- ICacheStatus=1;
- }
-
- if(DCacheStatus != 0) {
- Xil_DCacheDisable();
- }
- if(ICacheStatus != 0){
- Xil_ICacheDisable();
- }
-#if defined (__GNUC__)
- Reg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL,Reg);
-#endif
- Reg |= 0x00000001U;
- dsb();
- mtcp(XREG_CP15_SYS_CONTROL, Reg);
- isb();
- /* enable caches only if they are disabled in routine*/
- if(DCacheStatus != 0) {
- Xil_DCacheEnable();
- }
- if(ICacheStatus != 0) {
- Xil_ICacheEnable();
- }
-}
-
-/*****************************************************************************/
-/**
-* @brief Disable MPU for Cortex R5 processors. This function invalidates I
-* cache and flush the D Caches, and then disabes the MPU.
-*
-* @return None.
-*
-******************************************************************************/
-void Xil_DisableMPU(void)
-{
- u32 CtrlReg, Reg;
- s32 DCacheStatus=0, ICacheStatus=0;
- /* enable caches only if they are disabled */
-
-#if defined (__GNUC__)
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
-#endif
- if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) {
- DCacheStatus=1;
- }
- if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) {
- ICacheStatus=1;
- }
-
- if(DCacheStatus != 0) {
- Xil_DCacheDisable();
- }
- if(ICacheStatus != 0){
- Xil_ICacheDisable();
- }
-
- mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0);
-#if defined (__GNUC__)
- Reg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL,Reg);
-#endif
- Reg &= ~(0x00000001U);
- dsb();
- mtcp(XREG_CP15_SYS_CONTROL, Reg);
- isb();
- /* enable caches only if they are disabled in routine*/
- if(DCacheStatus != 0) {
- Xil_DCacheEnable();
- }
- if(ICacheStatus != 0) {
- Xil_ICacheEnable();
- }
-}
-
-/*****************************************************************************/
-/**
-* @brief Update the MPU configuration for the requested region number in
-* the global MPU configuration table.
-*
-* @param reg_num: The requested region number to be updated information for.
-* @param address: 32 bit address for start of the region.
-* @param size: Requested size of the region.
-* @param attrib: Attribute for the corresponding region.
-* @return XST_FAILURE: When the requested region number if 16 or more.
-* XST_SUCCESS: When the MPU configuration table is updated.
-*
-*
-******************************************************************************/
-u32 Xil_UpdateMPUConfig(u32 reg_num, INTPTR address, u32 size, u32 attrib)
-{
- u32 ReturnVal = XST_SUCCESS;
- u32 Tempsize = size;
- u32 Index;
-
- if (reg_num >= MAX_POSSIBLE_MPU_REGS) {
- xdbg_printf(DEBUG, "Invalid region number\r\n");
- ReturnVal = XST_FAILURE;
- goto exit;
- }
-
- if (size & REGION_EN) {
- Mpu_Config[reg_num].RegionStatus = MPU_REG_ENABLED;
- Mpu_Config[reg_num].BaseAddress = address;
- Tempsize &= (~REGION_EN);
- Tempsize >>= 1;
- /* Lookup the size. */
- for (Index = 0; Index <
- sizeof region_size / sizeof region_size[0]; Index++) {
- if (Tempsize <= region_size[Index].encoding) {
- Mpu_Config[reg_num].Size = region_size[Index].size;
- break;
- }
- }
- Mpu_Config[reg_num].Attribute = attrib;
- } else {
- Mpu_Config[reg_num].RegionStatus = 0U;
- Mpu_Config[reg_num].BaseAddress = 0U;
- Mpu_Config[reg_num].Size = 0U;
- Mpu_Config[reg_num].Attribute = 0U;
- }
-
-exit:
- return ReturnVal;
-}
-
-/*****************************************************************************/
-/**
-* @brief The MPU configuration table is passed to the caller.
-*
-* @param mpuconfig: This is of type XMpu_Config which is an array of
-* 16 entries of type structure representing the MPU config table
-* @return none
-*
-*
-******************************************************************************/
-void Xil_GetMPUConfig (XMpu_Config mpuconfig) {
- u32 Index = 0U;
-
- while (Index < MAX_POSSIBLE_MPU_REGS) {
- mpuconfig[Index].RegionStatus = Mpu_Config[Index].RegionStatus;
- mpuconfig[Index].BaseAddress = Mpu_Config[Index].BaseAddress;
- mpuconfig[Index].Attribute = Mpu_Config[Index].Attribute;
- mpuconfig[Index].Size = Mpu_Config[Index].Size;
- Index++;
- }
-}
-
-/*****************************************************************************/
-/**
-* @brief Returns the total number of free MPU regions available.
-*
-* @return Number of free regions available to users
-*
-*
-******************************************************************************/
-u32 Xil_GetNumOfFreeRegions (void) {
- u32 Index = 0U;
- int NumofFreeRegs = 0U;
-
- while (Index < MAX_POSSIBLE_MPU_REGS) {
- if (MPU_REG_DISABLED == Mpu_Config[Index].RegionStatus) {
- NumofFreeRegs++;
- }
- Index++;
- }
- return NumofFreeRegs;
-}
-
-/*****************************************************************************/
-/**
-* @brief Returns the total number of free MPU regions available in the form
-* of a mask. A bit of 1 in the returned 16 bit value represents the
-* corresponding region number to be available.
-* For example, if this function returns 0xC0000, this would mean, the
-* regions 14 and 15 are available to users.
-*
-* @return The free region mask as a 16 bit value
-*
-*
-******************************************************************************/
-u16 Xil_GetMPUFreeRegMask (void) {
- u32 Index = 0U;
- u16 FreeRegMask = 0U;
-
- while (Index < MAX_POSSIBLE_MPU_REGS) {
- if (MPU_REG_DISABLED == Mpu_Config[Index].RegionStatus) {
- FreeRegMask |= (1U << Index);
- }
- Index++;
- }
- return FreeRegMask;
-}
-
-/*****************************************************************************/
-/**
-* @brief Disables the corresponding region number as passed by the user.
-*
-* @param reg_num: The region number to be disabled
-* @return XST_SUCCESS: If the region could be disabled successfully
-* XST_FAILURE: If the requested region number is 16 or more.
-*
-*
-******************************************************************************/
-u32 Xil_DisableMPURegionByRegNum (u32 reg_num) {
- u32 Temp = 0U;
- u32 ReturnVal = XST_FAILURE;
-
- if (reg_num >= 16U) {
- xdbg_printf(DEBUG, "Invalid region number\r\n");
- goto exit1;
- }
- Xil_DCacheFlush();
- Xil_ICacheInvalidate();
-
- mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num);
-#if defined (__GNUC__)
- Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
-#endif
- Temp &= (~REGION_EN);
- dsb();
- mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
- dsb();
- isb();
- Xil_UpdateMPUConfig(reg_num, 0U, 0U, 0U);
- ReturnVal = XST_SUCCESS;
-
-exit1:
- return ReturnVal;
-}
-
-/*****************************************************************************/
-/**
-* @brief Enables the corresponding region number as passed by the user.
-*
-* @param reg_num: The region number to be enabled
-* @param addr: 32 bit address for start of the region.
-* @param size: Requested size of the region.
-* @param attrib: Attribute for the corresponding region.
-* @return XST_SUCCESS: If the region could be created successfully
-* XST_FAILURE: If the requested region number is 16 or more.
-*
-*
-******************************************************************************/
-u32 Xil_SetMPURegionByRegNum (u32 reg_num, INTPTR addr, u64 size, u32 attrib)
-{
- u32 ReturnVal = XST_SUCCESS;
- INTPTR Localaddr = addr;
- u32 Regionsize = 0;
- u32 Index;
-
- if (reg_num >= 16U) {
- xdbg_printf(DEBUG, "Invalid region number\r\n");
- ReturnVal = XST_FAILURE;
- goto exit2;
- }
-
- if (Mpu_Config[reg_num].RegionStatus == MPU_REG_ENABLED) {
- xdbg_printf(DEBUG, "Region already enabled\r\n");
- ReturnVal = XST_FAILURE;
- goto exit2;
- }
-
- Xil_DCacheFlush();
- Xil_ICacheInvalidate();
- mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num);
- isb();
-
- /* Lookup the size. */
- for (Index = 0; Index <
- sizeof region_size / sizeof region_size[0]; Index++) {
- if (size <= region_size[Index].size) {
- Regionsize = region_size[Index].encoding;
- break;
- }
- }
-
- Localaddr &= ~(region_size[Index].size - 1);
- Regionsize <<= 1;
- Regionsize |= REGION_EN;
- dsb();
- mtcp(XREG_CP15_MPU_REG_BASEADDR, Localaddr);
- mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL, attrib);
- mtcp(XREG_CP15_MPU_REG_SIZE_EN, Regionsize);
- dsb();
- isb();
- Xil_UpdateMPUConfig(reg_num, Localaddr, Regionsize, attrib);
-exit2:
- return ReturnVal;
-
-}
-
-/*****************************************************************************/
-/**
-* @brief Initializes the MPU configuration table that are setup in the
-* R5 boot code in the Init_Mpu function called before C main.
-*
-* @return none
-*
-*
-******************************************************************************/
-void Xil_InitializeExistingMPURegConfig(void)
-{
- u32 Index = 0U;
- u32 Index1 = 0U;
- u32 MPURegSize;
- INTPTR MPURegBA;
- u32 MPURegAttrib;
- u32 Tempsize;
-
- while (Index < MAX_POSSIBLE_MPU_REGS) {
- mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index);
-#if defined (__GNUC__)
- MPURegSize = mfcp(XREG_CP15_MPU_REG_SIZE_EN);
- MPURegBA = mfcp(XREG_CP15_MPU_REG_BASEADDR);
- MPURegAttrib = mfcp(XREG_CP15_MPU_REG_ACCESS_CTRL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_MPU_REG_SIZE_EN,MPURegSize);
- mfcp(XREG_CP15_MPU_REG_BASEADDR, MPURegBA);
- mfcp(XREG_CP15_MPU_REG_ACCESS_CTRL, MPURegAttrib);
-#endif
- if (MPURegSize & REGION_EN) {
- Mpu_Config[Index].RegionStatus = MPU_REG_ENABLED;
- Mpu_Config[Index].BaseAddress = MPURegBA;
- Mpu_Config[Index].Attribute = MPURegAttrib;
- Tempsize = MPURegSize & (~REGION_EN);
- Tempsize >>= 1;
- for (Index1 = 0; Index1 <
- (sizeof (region_size) / sizeof (region_size[0])); Index1++) {
- if (Tempsize <= region_size[Index1].encoding) {
- Mpu_Config[Index].Size = region_size[Index1].size;
- break;
- }
- }
- }
- Index++;
- }
-}
-
-/*****************************************************************************/
-/**
-* @brief Returns the next available free MPU region
-*
-* @return The free MPU region available
-*
-*
-******************************************************************************/
-u32 Xil_GetNextMPURegion(void)
-{
- u32 Index = 0U;
- u32 NextAvailableReg = 0xFF;
- while (Index < MAX_POSSIBLE_MPU_REGS) {
- if (Mpu_Config[Index].RegionStatus != MPU_REG_ENABLED) {
- NextAvailableReg = Index;
- break;
- }
- Index++;
- }
- return NextAvailableReg;
-}
-
-#ifdef __GNUC__
-#define u32overflow(a, b) ({typeof(a) s; __builtin_uadd_overflow(a, b, &s); })
-#else
-#define u32overflow(a, b) ((a) > ((a) + (b)))
-#endif /* __GNUC__ */
-
-/*****************************************************************************/
-/**
-* @brief Memory mapping for Cortex-R5F. If successful, the mapped
-* region will include all of the memory requested, but may
-* include more. Specifically, it will be a power of 2 in
-* size, aligned on a boundary of that size.
-*
-* @param Physaddr is base physical address at which to start mapping.
-* NULL in Physaddr masks possible mapping errors.
-* @param size of region to be mapped.
-* @param flags used to set translation table.
-*
-* @return Physaddr on success, NULL on error. Ambiguous if Physaddr==NULL
-*
-* @cond Xil_MemMap_internal
-* @note: u32overflow() is defined for readability and (for __GNUC__) to
-* - force the type of the check to be the same as the first argument
-* - hide the otherwise unused third argument of the builtin
-* - improve safety by choosing the explicit _uadd_ version.
-* Consider __builtin_add_overflow_p() when available.
-* Use an alternative (less optimal?) for compilers w/o the builtin.
-* @endcond
-******************************************************************************/
-void *Xil_MemMap(UINTPTR Physaddr, size_t size, u32 flags)
-{
- size_t Regionsize = MPU_REGION_SIZE_MIN;
- UINTPTR Basephysaddr = 0, end = Physaddr + size;
-
- if (!flags)
- return (void *)Physaddr;
- if (u32overflow(Physaddr, size))
- return NULL;
- for ( ; Regionsize != 0; Regionsize <<= 1) {
- if (Regionsize >= size) {
- Basephysaddr = Physaddr & ~(Regionsize - 1);
- if (u32overflow(Basephysaddr, Regionsize))
- break;
- if ((Basephysaddr + Regionsize) >= end)
- return Xil_SetMPURegion(Basephysaddr,
- Regionsize, flags) == XST_SUCCESS ?
- (void *)Physaddr : NULL;
- }
- }
- return NULL;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bb/41fb12555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bb/41fb12555243001d18b399c1eb9b3628
deleted file mode 100644
index c1258fb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bb/41fb12555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,588 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
- *
- * @file xil_cache.c
- *
- * Contains required functions for the ARM cache functionality.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -----------------------------------------------
- * 5.2 pkp 28/05/15 First release
- * 5.5 pkp 04/15/16 Updated the Xil_DCacheInvalidate,
- * Xil_DCacheInvalidateLine and Xil_DCacheInvalidateRange
- * functions description for proper explanation
- * 6.8 aru 06/15/18 Removed unused variables.
- * 6.8 aru 07/04/18 Optimized code in Xil_DCacheInvalidate and
- * Xil_DCacheFlush
- * 6.8 asa 11/10/18 Fix issues in cache Xil_DCacheInvalidate and
- * Xil_DCacheFlush that got introduced in the optimization
- * changes done in the previous patch for this file.
- *
- *
- ******************************************************************************/
- /***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xil_cache_l.h"
-#include "xil_io.h"
-#include "xpseudo_asm.h"
-#include "xparameters.h"
-#include "xreg_cortexa53.h"
-#include "xil_exception.h"
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#define IRQ_FIQ_MASK 0xC0U /* Mask IRQ and FIQ interrupts in cpsr */
-
-extern s32 _stack_end;
-extern s32 __undef_stack;
-#define SELECT_D_CACHE 0
-
-/****************************************************************************/
-/**
- * @brief Enable the Data cache.
- *
- * @return None.
- *
- ****************************************************************************/
-void Xil_DCacheEnable(void)
-{
- u32 CtrlReg;
-
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- /* enable caches only if they are disabled */
- if ((CtrlReg & XREG_CONTROL_DCACHE_BIT) == 0X00000000U) {
-
- /* invalidate the Data cache */
- Xil_DCacheInvalidate();
-
- CtrlReg |= XREG_CONTROL_DCACHE_BIT;
-
- /* enable the Data cache */
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- }
-}
-
-/****************************************************************************/
-/**
- * @brief Disable the Data cache.
- *
- * @return None.
- *
- ****************************************************************************/
-void Xil_DCacheDisable(void)
-{
- u32 CtrlReg;
- /* clean and invalidate the Data cache */
- Xil_DCacheFlush();
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-
- CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
- /* disable the Data cache */
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/****************************************************************************/
-/**
- * @brief Invalidate the Data cache. The contents present in
- * the data cache are cleaned and invalidated.
- *
- * @return None.
- *
- * @note In Cortex-A53, functionality to simply invalid the
- * cachelines is not present. Such operations are a
- * problem for an environment that supports virtualisation.
- * It would allow one OS to invalidate a line belonging to
- * another OS. This could lead to the other OS crashing
- * because of the loss of essential data. Hence, such
- * operations are promoted to clean and invalidate to avoid
- * such corruption.
- *
- ****************************************************************************/
-void Xil_DCacheInvalidate(void)
-{
- register u32 CsidReg;
- register u32 C7Reg;
- u32 LineSize;
- u32 NumWays;
- u32 Way;
- u32 WayIndex;
- u32 WayAdjust;
- u32 Set;
- u32 SetIndex;
- u32 NumSet;
- u32 NumCacheLevel;
- u32 CacheLevel;
- u32 currmask;
- u32 stack_start;
- u32 stack_end;
- u32 stack_size;
-
- stack_end = (u32) &_stack_end;
- stack_start = (u32) &__undef_stack;
- stack_size = stack_start - stack_end;
-
- /*Flush stack memory to save return address */
- Xil_DCacheFlushRange(stack_end, stack_size);
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
-
- /* Number of level of cache */
- NumCacheLevel = (mfcp(XREG_CP15_CACHE_LEVEL_ID) >> 24U) & 0x00000007U;
-
- for (CacheLevel = 0U, WayAdjust = 0x1E; CacheLevel < NumCacheLevel;
- CacheLevel++, WayAdjust = WayAdjust - 2) {
-
- mtcp(XREG_CP15_CACHE_SIZE_SEL, ((CacheLevel << 1) | SELECT_D_CACHE));
- isb();
-
- CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
-
- /* Get the cacheline size, way size, index size from csidr */
- LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
-
- /* Number of Ways */
- NumWays = (CsidReg & 0x00001FFFU) >> 3U;
- NumWays += 0X00000001U;
-
- /*Number of Set */
- NumSet = (CsidReg >> 13U) & 0x00007FFFU;
- NumSet += 0X00000001U;
-
- Way = 0U;
- Set = 0U;
-
- /* Invalidate all the cachelines */
- for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set | (CacheLevel << 1);
- mtcp(XREG_CP15_INVAL_DC_LINE_SW, C7Reg);
- Set += (0x00000001U << LineSize);
- }
- Set = 0U;
- Way += (0x00000001U << WayAdjust);
- }
-
- /* Wait for invalidate to complete */
- dsb();
- }
- mtcpsr(currmask);
-}
-/****************************************************************************/
-/**
- * @brief Invalidate a Data cache line. The cacheline is cleaned and
- * invalidated.
- *
- * @param adr: 32 bit address of the data to be invalidated.
- *
- * @return None.
- *
- * @note In Cortex-A53, functionality to simply invalid
- * the cachelines is not present. Such operations
- * are a problem for an environment that supports
- * virtualisation. It would allow one OS to invalidate
- * a line belonging to another OS. This could lead to
- * the other OS crashing because of the loss of essential
- * data. Hence, such operations are promoted to clean and
- * invalidate to avoid such corruption.
- *
- ****************************************************************************/
-void Xil_DCacheInvalidateLine(u32 adr)
-{
-
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- /* Select cache level 0 and D cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x0);
- isb();
- mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x3F)));
- /* Wait for invalidate to complete */
- dsb();
- /* Select cache level 1 and D cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x2);
- isb();
- mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x3F)));
- /* Wait for invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
- * @brief Invalidate the Data cache for the given address range.
- * The cachelines present in the adderss range are cleaned and
- * invalidated
- *
- * @param adr: 32bit start address of the range to be invalidated.
- * @param len: Length of the range to be invalidated in bytes.
- *
- * @return None.
- *
- * @note In Cortex-A53, functionality to simply invalid the cachelines
- * is not present. Such operations are a problem for an
- * environment that supports virtualisation. It would allow
- * one OS to invalidate a line belonging to another OS.
- * This could lead to the other OS crashing because of the
- * loss of essential data. Hence, such operations are promoted
- * to clean and invalidate to avoid such corruption.
- *
- ****************************************************************************/
-void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
-{
- const u32 cacheline = 64U;
- u32 end;
- u32 tempadr = adr;
- u32 tempend;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- if (len != 0U) {
- end = tempadr + len;
- tempend = end;
-
- if ((tempadr & (cacheline-1U)) != 0U) {
- tempadr &= (~(cacheline - 1U));
- Xil_DCacheFlushLine(tempadr);
- tempadr += cacheline;
- }
- if ((tempend & (cacheline-1U)) != 0U) {
- tempend &= (~(cacheline - 1U));
- Xil_DCacheFlushLine(tempend);
- }
-
- while (tempadr < tempend) {
- /* Select cache level 0 and D cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x0);
- /* Invalidate Data cache line */
- mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC,
- (tempadr & (~0x3F)));
- /* Wait for invalidate to complete */
- dsb();
- /* Select cache level 0 and D cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x2);
- /* Invalidate Data cache line */
- mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC,
- (tempadr & (~0x3F)));
- /* Wait for invalidate to complete */
- dsb();
- tempadr += cacheline;
- }
- }
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
- * @brief Flush the Data cache.
- *
- * @return None.
- *
- ****************************************************************************/
-void Xil_DCacheFlush(void)
-{
- register u32 CsidReg;
- register u32 C7Reg;
- u32 LineSize;
- u32 NumWays;
- u32 Way;
- u32 WayIndex;
- u32 WayAdjust;
- u32 Set;
- u32 SetIndex;
- u32 NumSet;
- u32 NumCacheLevel;
- u32 CacheLevel;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
-
- /* Number of level of cache*/
- NumCacheLevel = (mfcp(XREG_CP15_CACHE_LEVEL_ID)>>24U) & 0x00000007U;
-
- for (CacheLevel = 0U, WayAdjust = 0x1E; CacheLevel < NumCacheLevel;
- CacheLevel++, WayAdjust = WayAdjust - 2) {
- /* Select cache level and D cache in CSSELR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, ((CacheLevel << 1) | SELECT_D_CACHE));
- isb();
-
- CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
-
- /* Get the cacheline size, way size, index size from csidr */
- LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
-
- /* Number of Ways */
- NumWays = (CsidReg & 0x00001FFFU) >> 3U;
- NumWays += 0X00000001U;
-
- /*Number of Set*/
- NumSet = (CsidReg >> 13U) & 0x00007FFFU;
- NumSet += 0X00000001U;
-
- Way = 0U;
- Set = 0U;
-
- /* Invalidate all the cachelines */
- for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set | (CacheLevel << 1);
- mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_SW, C7Reg);
- Set += (0x00000001U << LineSize);
- }
- Set = 0U;
- Way += (0x00000001U << WayAdjust);
- }
-
- /* Wait for invalidate to complete */
- dsb();
- }
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
- * @brief Flush a Data cache line. If the byte specified by the
- * address (adr) is cached by the Data cache, the cacheline
- * containing that byte is invalidated. If the cacheline is
- * modified (dirty), the entire contents of the cacheline are
- * written to system memory before the line is invalidated.
- *
- * @param adr: 32bit address of the data to be flushed.
- *
- * @return None.
- *
- * @note The bottom 4 bits are set to 0, forced by architecture.
- *
- ****************************************************************************/
-void Xil_DCacheFlushLine(u32 adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- /* Select cache level 0 and D cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x0);
- isb();
- mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x3F)));
- /* Wait for invalidate to complete */
- dsb();
- /* Select cache level 1 and D cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x2);
- isb();
- mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x3F)));
- /* Wait for invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
- * @brief Flush the Data cache for the given address range.
- * If the bytes specified by the address range are cached
- * by the Data cache, the cachelines containing those bytes
- * are invalidated. If the cachelines are modified (dirty),
- * they are written to system memory before the lines are
- * invalidated.
- *
- * @param adr: 32bit start address of the range to be flushed.
- * @param len: Length of range to be flushed in bytes.
- *
- * @return None.
- *
- ****************************************************************************/
-void Xil_DCacheFlushRange(INTPTR adr, u32 len)
-{
- const u32 cacheline = 64U;
- u32 end;
- u32 tempadr = adr;
- u32 tempend;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- if (len != 0U) {
- end = tempadr + len;
- tempend = end;
-
- if ((tempadr & (cacheline-1U)) != 0U) {
- tempadr &= (~(cacheline - 1U));
- Xil_DCacheFlushLine(tempadr);
- tempadr += cacheline;
- }
- if ((tempend & (cacheline-1U)) != 0U) {
- tempend &= (~(cacheline - 1U));
- Xil_DCacheFlushLine(tempend);
- }
-
- while (tempadr < tempend) {
- /* Select cache level 0 and D cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x0);
- /* Invalidate Data cache line */
- mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC,
- (tempadr & (~0x3F)));
- /* Wait for invalidate to complete */
- dsb();
- /* Select cache level 0 and D cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x2);
- /* Invalidate Data cache line */
- mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC,
- (tempadr & (~0x3F)));
- /* Wait for invalidate to complete */
- dsb();
- tempadr += cacheline;
- }
- }
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
- * @brief Enable the instruction cache.
- *
- * @return None.
- *
- ****************************************************************************/
-void Xil_ICacheEnable(void)
-{
- u32 CtrlReg;
-
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- /* enable caches only if they are disabled */
- if ((CtrlReg & XREG_CONTROL_ICACHE_BIT) == 0x00000000U) {
- /* invalidate the instruction cache */
- Xil_ICacheInvalidate();
- CtrlReg |= XREG_CONTROL_ICACHE_BIT;
- /* enable the instruction cache */
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- }
-}
-
-/****************************************************************************/
-/**
- * @brief Disable the instruction cache.
- *
- * @return None.
- *
- ****************************************************************************/
-void Xil_ICacheDisable(void)
-{
- u32 CtrlReg;
-
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- /* invalidate the instruction cache */
- Xil_ICacheInvalidate();
- CtrlReg &= ~(XREG_CONTROL_ICACHE_BIT);
- /* disable the instruction cache */
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-
-}
-
-/****************************************************************************/
-/**
- * @brief Invalidate the entire instruction cache.
- *
- * @return None.
- *
- ****************************************************************************/
-void Xil_ICacheInvalidate(void)
-{
- unsigned int currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x1);
- dsb();
- /* invalidate the instruction cache */
- mtcp(XREG_CP15_INVAL_IC_POU, 0x0);
- /* Wait for invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-/****************************************************************************/
-/**
- * @brief Invalidate an instruction cache line. If the instruction
- * specified by the address is cached by the instruction cache,
- * the cachecline containing that instruction is invalidated.
- *
- * @param adr: 32bit address of the instruction to be invalidated..
- *
- * @return None.
- *
- * @note The bottom 4 bits are set to 0, forced by architecture.
- *
- ****************************************************************************/
-void Xil_ICacheInvalidateLine(u32 adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x1);
- /*Invalidate I Cache line*/
- mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, adr & (~0x3F));
- /* Wait for invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
- * @brief Invalidate the instruction cache for the given address range.
- * If the instructions specified by the address range are cached
- * by the instrunction cache, the cachelines containing those
- * instructions are invalidated.
- *
- * @param adr: 32bit start address of the range to be invalidated.
- * @param len: Length of the range to be invalidated in bytes.
- *
- * @return None.
- *
- ****************************************************************************/
-void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
-{
- const u32 cacheline = 64U;
- u32 end;
- u32 tempadr = adr;
- u32 tempend;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0x00000000U) {
- end = tempadr + len;
- tempend = end;
- tempadr &= ~(cacheline - 0x00000001U);
-
- /* Select cache Level 0 I-cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0x1);
- while (tempadr < tempend) {
- /*Invalidate I Cache line*/
- mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, adr & (~0x3F));
-
- tempadr += cacheline;
- }
- }
-/* Wait for invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bb/42d5ad585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bb/42d5ad585243001d18b399c1eb9b3628
deleted file mode 100644
index 811d2b0..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bb/42d5ad585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,23 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#ifndef UNDEFINE_FILE_OPS
-#include "xil_types.h"
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) s32 _close(s32 fd);
-}
-#endif
-
-/*
- * close -- We don't need to do anything, but pretend we did.
- */
-
-__attribute__((weak)) s32 _close(s32 fd)
-{
- (void)fd;
- return (0);
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bb/80adc2535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bb/80adc2535243001d18b399c1eb9b3628
deleted file mode 100644
index e22e04d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bb/80adc2535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,181 +0,0 @@
-/******************************************************************************/
-/**
-* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-* @file xil_util.h
-* @addtogroup common_utilities Common Utility APIs
-* @{
-* @details
-*
-* This file contains xil utility functions declaration
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.4 mmd 04/21/19 First release.
-* 6.5 kal 02/29/20 Added Xil_ConvertStringToHexBE API
-* 7.3 kal 06/30/20 Converted Xil_Ceil macro to API
-* rpo 08/19/20 Added function for read, modify and write
-* bsv 08/21/20 Added XSECURE_TEMPORAL_CHECK macro to add
-* redundancy in security critical functions, to avoid
-* glitches from altering the return values of security
-* critical functions. The macro requires a label to be
-* passed to "go to" in case of error.
-* kpt 09/03/20 Added XSECURE_TEMPORAL_IMPL macro for redundancy
-* kal 09/22/20 Changed the param type from const char to const char*
-* to avoid copying key onto stack
-* td 10/16/20 Added Xil_Strcpy, Xil_Strcat, Xil_SecureMemCpy and
-* Xil_MemCmp functions
-* am 10/13/20 Resolved Coverity warning
-* td 11/19/20 Updated XSECURE_TEMPORAL_CHECK and
-* XSECURE_TEMPORAL_IMPL to fix MISRA C Rule 15.3
-* 7.4 am 11/26/20 Added Xil_StrCpyRange function
-* 7.6 kpt 07/15/21 Added Xil_SecureZeroize function
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- --------- -------------------------------------------------------
-* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
-* function for PMUFW.
-* 7.2 adk 08/01/20 Added versal support for the XGetPSVersion_Info function.
-* 7.6 mus 08/23/21 Updated prototypes for functions which are not taking any
-* arguments with void keyword. This has been done to fix
-* compilation warnings with "-Wstrict-prototypes" flag.
-* It fixes CR#1108601.
-* 7.6 mus 08/30/21 Updated flag checking to fix compilation warnings
-* reported with "-Wundef" flag.
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */
-#define XPLATFORM_INFO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-#if defined (versal)
-#define XPAR_PMC_TAP_BASEADDR 0xF11A0000U
-#define XPAR_PMC_TAP_VERSION_OFFSET 0x00000004U
-#define XPLAT_PS_VERSION_ADDRESS (XPAR_PMC_TAP_BASEADDR + \
- XPAR_PMC_TAP_VERSION_OFFSET)
-#else
-#define XPAR_CSU_BASEADDR 0xFFCA0000U
-#define XPAR_CSU_VER_OFFSET 0x00000044U
-#define XPLAT_PS_VERSION_ADDRESS (XPAR_CSU_BASEADDR + \
- XPAR_CSU_VER_OFFSET)
-#endif
-#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
-#define XPLAT_ZYNQ_ULTRA_MP 0x1
-#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
-#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
-#define XPLAT_ZYNQ 0x4
-#define XPLAT_MICROBLAZE 0x5
-#define XPLAT_VERSAL 0x6U
-
-#define XPS_VERSION_1 0x0
-#define XPS_VERSION_2 0x1
-#define XPLAT_INFO_MASK (0xF)
-
-#if defined (versal)
-#define XPS_VERSION_INFO_MASK 0xFF00U
-#define XPS_VERSION_INFO_SHIFT 0x8U
-#define XPLAT_INFO_SHIFT 0x18U
-#else
-#define XPS_VERSION_INFO_MASK (0xF)
-#define XPS_VERSION_INFO_SHIFT 0x0U
-#define XPLAT_INFO_SHIFT 0xCU
-#endif
-
-/**************************** Type Definitions *******************************/
-/**
- *@endcond
- */
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-u32 XGetPlatform_Info(void);
-
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU) || defined (versal)
-u32 XGetPSVersion_Info(void);
-#endif
-
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
-u32 XGet_Zynq_UltraMp_Platform_info(void);
-#endif
-/************************** Function Prototypes ******************************/
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_platform_info".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bd/30e59b565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bd/30e59b565243001d18b399c1eb9b3628
deleted file mode 100644
index fe72661..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bd/30e59b565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,38 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file microblaze_interrupts_g.c
-*
-* This file contains the interrupt handler table for the MicroBlaze processor.
-* This file is usually generated by LibGen.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Date Changes
-* ----- -------- -----------------------------------------------
-* 1.00b 10/03/03 First release
-*
-*
-******************************************************************************/
-
-#include "microblaze_interrupts_i.h"
-#include "xparameters.h"
-
-
-/* extern void XNullHandler (void *NullParameter) */
-
-/*
-* The interrupt handler table for microblaze processor
-*/
-
-MB_InterruptVectorTableEntry MB_InterruptVectorTable[MB_INTERRUPT_VECTOR_TABLE_ENTRIES] =
-{
- {XNullHandler,
- (void*)XNULL}
-};
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bd/31cd28555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bd/31cd28555243001d18b399c1eb9b3628
deleted file mode 100644
index 9a87752..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bd/31cd28555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,361 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file asm_vectors.S
-*
-* This file contains the initial vector table for the Cortex A53 processor
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 5.00 pkp 05/21/14 Initial version
-* 6.02 pkp 12/21/16 Added support for floating point access
-* 6.02 pkp 01/22/17 Added support for EL1 non-secure and hypervisor
-* baremetal guest
-* 6.4 mus 06/14/17 Fixed bug in IRQInterruptHandler code snippet,
-* which checks for the FPEN bit of CPACR_EL1
-* 6.6 mus 01/19/18 Added isb after writing to the cpacr_el1/cptr_el3,
-* to ensure enabling/disabling of floating-point unit
-* is completed, before any subsequent instruction.
-* 7.5 mus 05/20/21 Fixed speculative execution past ERET and BR instructions.
-* As per CVE-2020-13844, Cortex-A72 is affected with
-* vulnearability, hence changes are targeted only for Cortex-A72.
-* It fixes CR#1083649.
-*
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#include "bspconfig.h"
-
-.org 0
-.text
-
-.globl _boot
-.globl _vector_table
-
-.globl FIQInterrupt
-.globl IRQInterrupt
-.globl SErrorInterrupt
-.globl SynchronousInterrupt
-.globl FPUStatus
-
-/*
- * FPUContextSize is the size of the array where floating point registers are
- * stored when required. The default size corresponds to the case when there is no
- * nested interrupt. If there are nested interrupts in application which are using
- * floating point operation, the size of FPUContextSize need to be increased as per
- * requirement
- */
-
-.set FPUContextSize, 528
-
-.macro saveregister
- stp X0,X1, [sp,#-0x10]!
- stp X2,X3, [sp,#-0x10]!
- stp X4,X5, [sp,#-0x10]!
- stp X6,X7, [sp,#-0x10]!
- stp X8,X9, [sp,#-0x10]!
- stp X10,X11, [sp,#-0x10]!
- stp X12,X13, [sp,#-0x10]!
- stp X14,X15, [sp,#-0x10]!
- stp X16,X17, [sp,#-0x10]!
- stp X18,X19, [sp,#-0x10]!
- stp X29,X30, [sp,#-0x10]!
-.endm
-
-.macro restoreregister
- ldp X29,X30, [sp], #0x10
- ldp X18,X19, [sp], #0x10
- ldp X16,X17, [sp], #0x10
- ldp X14,X15, [sp], #0x10
- ldp X12,X13, [sp], #0x10
- ldp X10,X11, [sp], #0x10
- ldp X8,X9, [sp], #0x10
- ldp X6,X7, [sp], #0x10
- ldp X4,X5, [sp], #0x10
- ldp X2,X3, [sp], #0x10
- ldp X0,X1, [sp], #0x10
-.endm
-
-.macro savefloatregister
-
-/* Load the floating point context array address from FPUContextBase */
- ldr x1,=FPUContextBase
- ldr x0, [x1]
-
-/* Save all the floating point register to the array */
- stp q0,q1, [x0], #0x20
- stp q2,q3, [x0], #0x20
- stp q4,q5, [x0], #0x20
- stp q6,q7, [x0], #0x20
- stp q8,q9, [x0], #0x20
- stp q10,q11, [x0], #0x20
- stp q12,q13, [x0], #0x20
- stp q14,q15, [x0], #0x20
- stp q16,q17, [x0], #0x20
- stp q18,q19, [x0], #0x20
- stp q20,q21, [x0], #0x20
- stp q22,q23, [x0], #0x20
- stp q24,q25, [x0], #0x20
- stp q26,q27, [x0], #0x20
- stp q28,q29, [x0], #0x20
- stp q30,q31, [x0], #0x20
- mrs x2, FPCR
- mrs x3, FPSR
- stp x2, x3, [x0], #0x10
-
-/* Save current address of floating point context array to FPUContextBase */
- str x0, [x1]
-.endm
-
-.macro restorefloatregister
-
-/* Restore the address of floating point context array from FPUContextBase */
- ldr x1,=FPUContextBase
- ldr x0, [x1]
-
-/* Restore all the floating point register from the array */
- ldp x2, x3, [x0,#-0x10]!
- msr FPCR, x2
- msr FPSR, x3
- ldp q30,q31, [x0,#-0x20]!
- ldp q28,q29, [x0,#-0x20]!
- ldp q26,q27, [x0,#-0x20]!
- ldp q24,q25, [x0,#-0x20]!
- ldp q22,q23, [x0,#-0x20]!
- ldp q20,q21, [x0,#-0x20]!
- ldp q18,q19, [x0,#-0x20]!
- ldp q16,q17, [x0,#-0x20]!
- ldp q14,q15, [x0,#-0x20]!
- ldp q12,q13, [x0,#-0x20]!
- ldp q10,q11, [x0,#-0x20]!
- ldp q8,q9, [x0,#-0x20]!
- ldp q6,q7, [x0,#-0x20]!
- ldp q4,q5, [x0,#-0x20]!
- ldp q2,q3, [x0,#-0x20]!
- ldp q0,q1, [x0,#-0x20]!
-
-/* Save current address of floating point context array to FPUContextBase */
- str x0, [x1]
-.endm
-
-.macro exception_return
- eret
-#if defined (versal)
- dsb nsh
- isb
-#endif
-.endm
-
-.org 0
-
-.section .vectors, "a"
-
-_vector_table:
-.set VBAR, _vector_table
-.org VBAR
-/*
- * if application is built for XEN GUEST as EL1 Non-secure following image
- * header is required by XEN.
- */
-.if (HYP_GUEST == 1)
-
- /* Valid Image header. */
- /* HW reset vector. */
- ldr x16, =_boot
- br x16
-#if defined (versal)
- dsb nsh
- isb
-#endif
- /* text offset. */
- .dword 0
- /* image size. */
- .dword 0
- /* flags. */
- .dword 8
- /* RES0 */
- .dword 0
- .dword 0
- .dword 0
-
- /* magic */
- .dword 0x644d5241
- /* RES0 */
- .dword 0
- /* End of Image header. */
-.endif
-
- b _boot
-.org (VBAR + 0x200)
- b SynchronousInterruptHandler
-
-.org (VBAR + 0x280)
- b IRQInterruptHandler
-
-.org (VBAR + 0x300)
- b FIQInterruptHandler
-
-.org (VBAR + 0x380)
- b SErrorInterruptHandler
-
-
-SynchronousInterruptHandler:
- saveregister
-
-/* Check if the Synchronous abort is occurred due to floating point access. */
-.if (EL3 == 1)
- mrs x0, ESR_EL3
-.else
- mrs x0, ESR_EL1
-.endif
- and x0, x0, #(0x3F << 26)
- mov x1, #(0x7 << 26)
- cmp x0, x1
-/* If exception is not due to floating point access go to synchronous handler */
- bne synchronoushandler
-
-/*
- * If excpetion occurred due to floating point access, Enable the floating point
- * access i.e. do not trap floating point instruction
- */
- .if (EL3 == 1)
- mrs x1,CPTR_EL3
- bic x1, x1, #(0x1<<10)
- msr CPTR_EL3, x1
-.else
- mrs x1,CPACR_EL1
- orr x1, x1, #(0x1<<20)
- msr CPACR_EL1, x1
-.endif
- isb
-
-/* If the floating point access was previously enabled, store FPU context
- * registers(storefloat).
- */
- ldr x0, =FPUStatus
- ldrb w1,[x0]
- cbnz w1, storefloat
-/*
- * If the floating point access was not enabled previously, save the status of
- * floating point accessibility i.e. enabled and store floating point context
- * array address(FPUContext) to FPUContextBase.
- */
- mov w1, #0x1
- strb w1, [x0]
- ldr x0, =FPUContext
- ldr x1, =FPUContextBase
- str x0,[x1]
- b restorecontext
-storefloat:
- savefloatregister
- b restorecontext
-synchronoushandler:
- bl SynchronousInterrupt
-restorecontext:
- restoreregister
- exception_return
-
-IRQInterruptHandler:
-
- saveregister
-/* Save the status of SPSR, ELR and CPTR to stack */
- .if (EL3 == 1)
- mrs x0, CPTR_EL3
- mrs x1, ELR_EL3
- mrs x2, SPSR_EL3
-.else
- mrs x0, CPACR_EL1
- mrs x1, ELR_EL1
- mrs x2, SPSR_EL1
-.endif
- stp x0, x1, [sp,#-0x10]!
- str x2, [sp,#-0x10]!
-
-/* Trap floating point access */
- .if (EL3 == 1)
- mrs x1,CPTR_EL3
- orr x1, x1, #(0x1<<10)
- msr CPTR_EL3, x1
-.else
- mrs x1,CPACR_EL1
- bic x1, x1, #(0x1<<20)
- msr CPACR_EL1, x1
-.endif
- isb
-
- bl IRQInterrupt
-/*
- * If floating point access is enabled during interrupt handling,
- * restore floating point registers.
- */
-
- .if (EL3 == 1)
- mrs x0, CPTR_EL3
- ands x0, x0, #(0x1<<10)
- bne RestorePrevState
-.else
- mrs x0,CPACR_EL1
- ands x0, x0, #(0x1<<20)
- beq RestorePrevState
-.endif
-
- restorefloatregister
-
-/* Restore the status of SPSR, ELR and CPTR from stack */
-RestorePrevState:
- ldr x2,[sp],0x10
- ldp x0, x1, [sp],0x10
- .if (EL3 == 1)
- msr CPTR_EL3, x0
- msr ELR_EL3, x1
- msr SPSR_EL3, x2
-.else
- msr CPACR_EL1, x0
- msr ELR_EL1, x1
- msr SPSR_EL1, x2
-.endif
- restoreregister
- exception_return
-
-FIQInterruptHandler:
-
- saveregister
-
- bl FIQInterrupt
-
- restoreregister
-
- exception_return
-
-SErrorInterruptHandler:
-
- saveregister
-
- bl SErrorInterrupt
-
- restoreregister
-
- exception_return
-
-
-.align 8
-/* Array to store floating point registers */
-FPUContext: .skip FPUContextSize
-
-/* Stores address for floating point context array */
-FPUContextBase: .skip 8
-
-FPUStatus: .skip 1
-
-.end
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bd/a0165c595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bd/a0165c595243001d18b399c1eb9b3628
deleted file mode 100644
index e654a6c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bd/a0165c595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,38 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-* File : microblaze_enable_icache.s
-* Date : 2002, March 20.
-* Company: Xilinx
-* Group : Emerging Software Technologies
-*
-* Summary:
-* Enable icache on the microblaze.
-*
-*
-******************************************************************************/
-#include "xparameters.h"
-
- .text
- .globl microblaze_enable_icache
- .ent microblaze_enable_icache
- .align 2
-microblaze_enable_icache:
-#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
- rtsd r15, 8
- msrset r0, 0x20
-#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- #Read the MSR register
- mfs r8, rmsr
- #Set the interrupt enable bit
- ori r8, r8, 0x20
- #Save the MSR register
- mts rmsr, r8
- #Return
- rtsd r15, 8
- nop
-#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- .end microblaze_enable_icache
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bd/c16d28575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bd/c16d28575243001d18b399c1eb9b3628
deleted file mode 100644
index 51cc7c5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bd/c16d28575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,477 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xadcps_hw.h
-* @addtogroup xadcps_v2_6
-* @{
-*
-* This header file contains identifiers and basic driver functions (or
-* macros) that can be used to access the XADC device through the Device
-* Config Interface of the Zynq.
-*
-*
-* Refer to the device specification for more information about this driver.
-*
-* @note None.
-*
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a bss 12/22/11 First release based on the XPS/AXI xadc driver
-* 1.03a bss 11/01/13 Modified macros to use correct Register offsets
-* CR#749687
-* 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors.
-*
-*
-*
-*****************************************************************************/
-#ifndef XADCPS_HW_H /* Prevent circular inclusions */
-#define XADCPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**@name Register offsets of XADC in the Device Config
- *
- * The following constants provide access to each of the registers of the
- * XADC device.
- * @{
- */
-
-#define XADCPS_CFG_OFFSET 0x00U /**< Configuration Register */
-#define XADCPS_INT_STS_OFFSET 0x04U /**< Interrupt Status Register */
-#define XADCPS_INT_MASK_OFFSET 0x08U /**< Interrupt Mask Register */
-#define XADCPS_MSTS_OFFSET 0x0CU /**< Misc status register */
-#define XADCPS_CMDFIFO_OFFSET 0x10U /**< Command FIFO Register */
-#define XADCPS_RDFIFO_OFFSET 0x14U /**< Read FIFO Register */
-#define XADCPS_MCTL_OFFSET 0x18U /**< Misc control register */
-
-/* @} */
-
-
-
-
-
-/** @name XADC Config Register Bit definitions
- * @{
- */
-#define XADCPS_CFG_ENABLE_MASK 0x80000000U /**< Enable access from PS mask */
-#define XADCPS_CFG_CFIFOTH_MASK 0x00F00000U /**< Command FIFO Threshold mask */
-#define XADCPS_CFG_DFIFOTH_MASK 0x000F0000U /**< Data FIFO Threshold mask */
-#define XADCPS_CFG_WEDGE_MASK 0x00002000U /**< Write Edge Mask */
-#define XADCPS_CFG_REDGE_MASK 0x00001000U /**< Read Edge Mask */
-#define XADCPS_CFG_TCKRATE_MASK 0x00000300U /**< Clock freq control */
-#define XADCPS_CFG_IGAP_MASK 0x0000001FU /**< Idle Gap between
- * successive commands */
-/* @} */
-
-
-/** @name XADC Interrupt Status/Mask Register Bit definitions
- *
- * The definitions are same for the Interrupt Status Register and
- * Interrupt Mask Register. They are defined only once.
- * @{
- */
-#define XADCPS_INTX_ALL_MASK 0x000003FFU /**< Alarm Signals Mask */
-#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200U /**< CMD FIFO less than threshold */
-#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100U /**< Data FIFO greater than threshold */
-#define XADCPS_INTX_OT_MASK 0x00000080U /**< Over temperature Alarm Status */
-#define XADCPS_INTX_ALM_ALL_MASK 0x0000007FU /**< Alarm Signals Mask */
-#define XADCPS_INTX_ALM6_MASK 0x00000040U /**< Alarm 6 Mask */
-#define XADCPS_INTX_ALM5_MASK 0x00000020U /**< Alarm 5 Mask */
-#define XADCPS_INTX_ALM4_MASK 0x00000010U /**< Alarm 4 Mask */
-#define XADCPS_INTX_ALM3_MASK 0x00000008U /**< Alarm 3 Mask */
-#define XADCPS_INTX_ALM2_MASK 0x00000004U /**< Alarm 2 Mask */
-#define XADCPS_INTX_ALM1_MASK 0x00000002U /**< Alarm 1 Mask */
-#define XADCPS_INTX_ALM0_MASK 0x00000001U /**< Alarm 0 Mask */
-
-/* @} */
-
-
-/** @name XADC Miscellaneous Register Bit definitions
- * @{
- */
-#define XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000U /**< Command FIFO Level mask */
-#define XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000U /**< Data FIFO Level Mask */
-#define XADCPS_MSTS_CFIFOF_MASK 0x00000800U /**< Command FIFO Full Mask */
-#define XADCPS_MSTS_CFIFOE_MASK 0x00000400U /**< Command FIFO Empty Mask */
-#define XADCPS_MSTS_DFIFOF_MASK 0x00000200U /**< Data FIFO Full Mask */
-#define XADCPS_MSTS_DFIFOE_MASK 0x00000100U /**< Data FIFO Empty Mask */
-#define XADCPS_MSTS_OT_MASK 0x00000080U /**< Over Temperature Mask */
-#define XADCPS_MSTS_ALM_MASK 0x0000007FU /**< Alarms Mask */
-/* @} */
-
-
-/** @name XADC Miscellaneous Control Register Bit definitions
- * @{
- */
-#define XADCPS_MCTL_RESET_MASK 0x00000010U /**< Reset XADC */
-#define XADCPS_MCTL_FLUSH_MASK 0x00000001U /**< Flush the FIFOs */
-/* @} */
-
-
-/**@name Internal Register offsets of the XADC
- *
- * The following constants provide access to each of the internal registers of
- * the XADC device.
- * @{
- */
-
-/*
- * XADC Internal Channel Registers
- */
-#define XADCPS_TEMP_OFFSET 0x00U /**< On-chip Temperature Reg */
-#define XADCPS_VCCINT_OFFSET 0x01U /**< On-chip VCCINT Data Reg */
-#define XADCPS_VCCAUX_OFFSET 0x02U /**< On-chip VCCAUX Data Reg */
-#define XADCPS_VPVN_OFFSET 0x03U /**< ADC out of VP/VN */
-#define XADCPS_VREFP_OFFSET 0x04U /**< On-chip VREFP Data Reg */
-#define XADCPS_VREFN_OFFSET 0x05U /**< On-chip VREFN Data Reg */
-#define XADCPS_VBRAM_OFFSET 0x06U /**< On-chip VBRAM , 7 Series */
-#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08U /**< ADC A Supply Offset Reg */
-#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09U /**< ADC A Offset Data Reg */
-#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0AU /**< ADC A Gain Error Reg */
-#define XADCPS_VCCPINT_OFFSET 0x0DU /**< On-chip VCCPINT Reg, Zynq */
-#define XADCPS_VCCPAUX_OFFSET 0x0EU /**< On-chip VCCPAUX Reg, Zynq */
-#define XADCPS_VCCPDRO_OFFSET 0x0FU /**< On-chip VCCPDRO Reg, Zynq */
-
-/*
- * XADC External Channel Registers
- */
-#define XADCPS_AUX00_OFFSET 0x10U /**< ADC out of VAUXP0/VAUXN0 */
-#define XADCPS_AUX01_OFFSET 0x11U /**< ADC out of VAUXP1/VAUXN1 */
-#define XADCPS_AUX02_OFFSET 0x12U /**< ADC out of VAUXP2/VAUXN2 */
-#define XADCPS_AUX03_OFFSET 0x13U /**< ADC out of VAUXP3/VAUXN3 */
-#define XADCPS_AUX04_OFFSET 0x14U /**< ADC out of VAUXP4/VAUXN4 */
-#define XADCPS_AUX05_OFFSET 0x15U /**< ADC out of VAUXP5/VAUXN5 */
-#define XADCPS_AUX06_OFFSET 0x16U /**< ADC out of VAUXP6/VAUXN6 */
-#define XADCPS_AUX07_OFFSET 0x17U /**< ADC out of VAUXP7/VAUXN7 */
-#define XADCPS_AUX08_OFFSET 0x18U /**< ADC out of VAUXP8/VAUXN8 */
-#define XADCPS_AUX09_OFFSET 0x19U /**< ADC out of VAUXP9/VAUXN9 */
-#define XADCPS_AUX10_OFFSET 0x1AU /**< ADC out of VAUXP10/VAUXN10 */
-#define XADCPS_AUX11_OFFSET 0x1BU /**< ADC out of VAUXP11/VAUXN11 */
-#define XADCPS_AUX12_OFFSET 0x1CU /**< ADC out of VAUXP12/VAUXN12 */
-#define XADCPS_AUX13_OFFSET 0x1DU /**< ADC out of VAUXP13/VAUXN13 */
-#define XADCPS_AUX14_OFFSET 0x1EU /**< ADC out of VAUXP14/VAUXN14 */
-#define XADCPS_AUX15_OFFSET 0x1FU /**< ADC out of VAUXP15/VAUXN15 */
-
-/*
- * XADC Registers for Maximum/Minimum data captured for the
- * on chip Temperature/VCCINT/VCCAUX data.
- */
-#define XADCPS_MAX_TEMP_OFFSET 0x20U /**< Max Temperature Reg */
-#define XADCPS_MAX_VCCINT_OFFSET 0x21U /**< Max VCCINT Register */
-#define XADCPS_MAX_VCCAUX_OFFSET 0x22U /**< Max VCCAUX Register */
-#define XADCPS_MAX_VCCBRAM_OFFSET 0x23U /**< Max BRAM Register, 7 series */
-#define XADCPS_MIN_TEMP_OFFSET 0x24U /**< Min Temperature Reg */
-#define XADCPS_MIN_VCCINT_OFFSET 0x25U /**< Min VCCINT Register */
-#define XADCPS_MIN_VCCAUX_OFFSET 0x26U /**< Min VCCAUX Register */
-#define XADCPS_MIN_VCCBRAM_OFFSET 0x27U /**< Min BRAM Register, 7 series */
-#define XADCPS_MAX_VCCPINT_OFFSET 0x28U /**< Max VCCPINT Register, Zynq */
-#define XADCPS_MAX_VCCPAUX_OFFSET 0x29U /**< Max VCCPAUX Register, Zynq */
-#define XADCPS_MAX_VCCPDRO_OFFSET 0x2AU /**< Max VCCPDRO Register, Zynq */
-#define XADCPS_MIN_VCCPINT_OFFSET 0x2CU /**< Min VCCPINT Register, Zynq */
-#define XADCPS_MIN_VCCPAUX_OFFSET 0x2DU /**< Min VCCPAUX Register, Zynq */
-#define XADCPS_MIN_VCCPDRO_OFFSET 0x2EU /**< Min VCCPDRO Register,Zynq */
- /* Undefined 0x2F to 0x3E */
-#define XADCPS_FLAG_OFFSET 0x3FU /**< Flag Register */
-
-/*
- * XADC Configuration Registers
- */
-#define XADCPS_CFR0_OFFSET 0x40U /**< Configuration Register 0 */
-#define XADCPS_CFR1_OFFSET 0x41U /**< Configuration Register 1 */
-#define XADCPS_CFR2_OFFSET 0x42U /**< Configuration Register 2 */
-
-/* Test Registers 0x43 to 0x47 */
-
-/*
- * XADC Sequence Registers
- */
-#define XADCPS_SEQ00_OFFSET 0x48U /**< Seq Reg 00 Adc Channel Selection */
-#define XADCPS_SEQ01_OFFSET 0x49U /**< Seq Reg 01 Adc Channel Selection */
-#define XADCPS_SEQ02_OFFSET 0x4AU /**< Seq Reg 02 Adc Average Enable */
-#define XADCPS_SEQ03_OFFSET 0x4BU /**< Seq Reg 03 Adc Average Enable */
-#define XADCPS_SEQ04_OFFSET 0x4CU /**< Seq Reg 04 Adc Input Mode Select */
-#define XADCPS_SEQ05_OFFSET 0x4DU /**< Seq Reg 05 Adc Input Mode Select */
-#define XADCPS_SEQ06_OFFSET 0x4EU /**< Seq Reg 06 Adc Acquisition Select */
-#define XADCPS_SEQ07_OFFSET 0x4FU /**< Seq Reg 07 Adc Acquisition Select */
-
-/*
- * XADC Alarm Threshold/Limit Registers (ATR)
- */
-#define XADCPS_ATR_TEMP_UPPER_OFFSET 0x50U /**< Temp Upper Alarm Register */
-#define XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51U /**< VCCINT Upper Alarm Reg */
-#define XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52U /**< VCCAUX Upper Alarm Reg */
-#define XADCPS_ATR_OT_UPPER_OFFSET 0x53U /**< Over Temp Upper Alarm Reg */
-#define XADCPS_ATR_TEMP_LOWER_OFFSET 0x54U /**< Temp Lower Alarm Register */
-#define XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55U /**< VCCINT Lower Alarm Reg */
-#define XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56U /**< VCCAUX Lower Alarm Reg */
-#define XADCPS_ATR_OT_LOWER_OFFSET 0x57U /**< Over Temp Lower Alarm Reg */
-#define XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58U /**< VBRAM Upper Alarm, 7 series */
-#define XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59U /**< VCCPINT Upper Alarm, Zynq */
-#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5AU /**< VCCPAUX Upper Alarm, Zynq */
-#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5BU /**< VCCPDRO Upper Alarm, Zynq */
-#define XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5CU /**< VRBAM Lower Alarm, 7 Series */
-#define XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5DU /**< VCCPINT Lower Alarm, Zynq */
-#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5EU /**< VCCPAUX Lower Alarm, Zynq */
-#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5FU /**< VCCPDRO Lower Alarm, Zynq */
-
-/* Undefined 0x60 to 0x7F */
-
-/*@}*/
-
-
-
-/**
- * @name Configuration Register 0 (CFR0) mask(s)
- * @{
- */
-#define XADCPS_CFR0_CAL_AVG_MASK 0x00008000U /**< Averaging enable Mask */
-#define XADCPS_CFR0_AVG_VALID_MASK 0x00003000U /**< Averaging bit Mask */
-#define XADCPS_CFR0_AVG1_MASK 0x00000000U /**< No Averaging */
-#define XADCPS_CFR0_AVG16_MASK 0x00001000U /**< Average 16 samples */
-#define XADCPS_CFR0_AVG64_MASK 0x00002000U /**< Average 64 samples */
-#define XADCPS_CFR0_AVG256_MASK 0x00003000U /**< Average 256 samples */
-#define XADCPS_CFR0_AVG_SHIFT 12U /**< Averaging bits shift */
-#define XADCPS_CFR0_MUX_MASK 0x00000800U /**< External Mask Enable */
-#define XADCPS_CFR0_DU_MASK 0x00000400U /**< Bipolar/Unipolar mode */
-#define XADCPS_CFR0_EC_MASK 0x00000200U /**< Event driven/
- * Continuous mode selection
- */
-#define XADCPS_CFR0_ACQ_MASK 0x00000100U /**< Add acquisition by 6 ADCCLK */
-#define XADCPS_CFR0_CHANNEL_MASK 0x0000001FU /**< Channel number bit Mask */
-
-/*@}*/
-
-/**
- * @name Configuration Register 1 (CFR1) mask(s)
- * @{
- */
-#define XADCPS_CFR1_SEQ_VALID_MASK 0x0000F000U /**< Sequence bit Mask */
-#define XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x00000000U /**< Default Safe Mode */
-#define XADCPS_CFR1_SEQ_ONEPASS_MASK 0x00001000U /**< Onepass through Seq */
-#define XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x00002000U /**< Continuous Cycling Seq */
-#define XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x00003000U /**< Single channel - No Seq */
-#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x00004000U /**< Simulataneous Sampling Mask */
-#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x00008000U /**< Independent Mode */
-#define XADCPS_CFR1_SEQ_SHIFT 12U /**< Sequence bit shift */
-#define XADCPS_CFR1_ALM_VCCPDRO_MASK 0x00000800U /**< Alm 6 - VCCPDRO, Zynq */
-#define XADCPS_CFR1_ALM_VCCPAUX_MASK 0x00000400U /**< Alm 5 - VCCPAUX, Zynq */
-#define XADCPS_CFR1_ALM_VCCPINT_MASK 0x00000200U /**< Alm 4 - VCCPINT, Zynq */
-#define XADCPS_CFR1_ALM_VBRAM_MASK 0x00000100U /**< Alm 3 - VBRAM, 7 series */
-#define XADCPS_CFR1_CAL_VALID_MASK 0x000000F0U /**< Valid Calibration Mask */
-#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x00000080U /**< Calibration 3 -Power
- Supply Gain/Offset
- Enable */
-#define XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x00000040U /**< Calibration 2 -Power
- Supply Offset Enable */
-#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x00000020U /**< Calibration 1 -ADC Gain
- Offset Enable */
-#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x00000010U /**< Calibration 0 -ADC Offset
- Enable */
-#define XADCPS_CFR1_CAL_DISABLE_MASK 0x00000000U /**< No Calibration */
-#define XADCPS_CFR1_ALM_ALL_MASK 0x00000F0FU /**< Mask for all alarms */
-#define XADCPS_CFR1_ALM_VCCAUX_MASK 0x00000008U /**< Alarm 2 - VCCAUX Enable */
-#define XADCPS_CFR1_ALM_VCCINT_MASK 0x00000004U /**< Alarm 1 - VCCINT Enable */
-#define XADCPS_CFR1_ALM_TEMP_MASK 0x00000002U /**< Alarm 0 - Temperature */
-#define XADCPS_CFR1_OT_MASK 0x00000001U /**< Over Temperature Enable */
-
-/*@}*/
-
-/**
- * @name Configuration Register 2 (CFR2) mask(s)
- * @{
- */
-#define XADCPS_CFR2_CD_VALID_MASK 0xFF00U /**
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- ----------------------------------------------------------
- * 1.00a jz 10/10/10 First release
- * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet
- * handling.
- * 2.3 bss 01/19/16 Modified XUsbPs_EpQueueRequest function to fix CR#873972
- * (moving of dTD Head/Tail Pointers properly).
- * 2.5 pm 02/20/20 Added ISO endpoint support.
- *
- ******************************************************************************/
-
-/***************************** Include Files **********************************/
-
-#include "xusbps.h"
-#include "xusbps_endpoint.h"
-
-/************************** Constant Definitions ******************************/
-
-/**************************** Type Definitions ********************************/
-
-/***************** Macros (Inline Functions) Definitions **********************/
-
-/************************** Variable Definitions ******************************/
-
-/************************** Function Prototypes *******************************/
-
-static void XUsbPs_IntrHandleTX(XUsbPs *InstancePtr, u32 EpCompl);
-static void XUsbPs_IntrHandleRX(XUsbPs *InstancePtr, u32 EpCompl);
-static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts);
-static void XUsbPs_IntrHandleEp0Setup(XUsbPs *InstancePtr);
-
-/*****************************************************************************/
-/**
-* This function is the first-level interrupt handler for the USB core. All USB
-* interrupts will be handled here. Depending on the type of the interrupt,
-* second level interrupt handler may be called. Second level interrupt
-* handlers will be registered by the user using the:
-* XUsbPs_IntrSetHandler()
-* and/or
-* XUsbPs_EpSetHandler()
-* functions.
-*
-*
-* @param HandlerRef is a Reference passed to the interrupt register
-* function. In our case this will be a pointer to the XUsbPs
-* instance.
-*
-* @return None
-*
-* @note None
-*
-******************************************************************************/
-void XUsbPs_IntrHandler(void *HandlerRef)
-{
- XUsbPs *InstancePtr;
-
- u32 IrqSts;
-
- Xil_AssertVoid(HandlerRef != NULL);
-
- InstancePtr = (XUsbPs *) HandlerRef;
-
- /* Handle controller (non-endpoint) related interrupts. */
- IrqSts = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_ISR_OFFSET);
-
- /* Clear the interrupt status register. */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_ISR_OFFSET, IrqSts);
-
- /* Nak interrupt, used to respond to host's IN request */
- if(IrqSts & XUSBPS_IXR_NAK_MASK) {
- /* Ack the hardware */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPNAKISR_OFFSET,
- XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPNAKISR_OFFSET));
- }
-
-
- /***************************************************************
- *
- * Handle general interrupts. Endpoint interrupts will be handler
- * later.
- *
- */
-
- /* RESET interrupt.*/
- if (IrqSts & XUSBPS_IXR_UR_MASK) {
- XUsbPs_IntrHandleReset(InstancePtr, IrqSts);
- return;
- }
-
- /* Check if we have a user handler that needs to be called. Note that
- * this is the handler for general interrupts. Endpoint interrupts will
- * be handled below.
- */
- if ((IrqSts & InstancePtr->HandlerMask) && InstancePtr->HandlerFunc) {
- (InstancePtr->HandlerFunc)(InstancePtr->HandlerRef, IrqSts);
- }
-
-
- /***************************************************************
- *
- * Handle Endpoint interrupts.
- *
- */
- if (IrqSts & XUSBPS_IXR_UI_MASK) {
- u32 EpStat;
- u32 EpCompl;
-
- /* ENDPOINT 0 SETUP PACKET HANDLING
- *
- * Check if we got a setup packet on endpoint 0. Currently we
- * only check for setup packets on endpoint 0 as we would not
- * expect setup packets on any other endpoint (even though it
- * is possible to send setup packets on other endpoints).
- */
- EpStat = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPSTAT_OFFSET);
- if (EpStat & 0x0001) {
- /* Handle the setup packet */
- XUsbPs_IntrHandleEp0Setup(InstancePtr);
-
- /* Re-Prime the endpoint.
- * Endpoint is de-primed if a setup packet comes in.
- */
- XUsbPs_EpPrime(InstancePtr, 0, XUSBPS_EP_DIRECTION_OUT);
- }
-
- /* Check for RX and TX complete interrupts. */
- EpCompl = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPCOMPL_OFFSET);
-
-
- /* ACK the complete interrupts. */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPCOMPL_OFFSET, EpCompl);
-
- /* Check OUT (RX) endpoints. */
- if (EpCompl & XUSBPS_EP_OUT_MASK) {
- XUsbPs_IntrHandleRX(InstancePtr, EpCompl);
- }
-
- /* Check IN (TX) endpoints. */
- if (EpCompl & XUSBPS_EP_IN_MASK) {
- XUsbPs_IntrHandleTX(InstancePtr, EpCompl);
- }
- }
-}
-
-
-/*****************************************************************************/
-/**
-* This function registers the user callback handler for controller
-* (non-endpoint) interrupts.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param CallBackFunc is the Callback function to register.
-* CallBackFunc may be NULL to clear the entry.
-* @param CallBackRef is the user data reference passed to the
-* callback function. CallBackRef may be NULL.
-* @param Mask is the User interrupt mask. Defines which interrupts
-* will cause the callback to be called.
-*
-* @return
-* - XST_SUCCESS: Callback registered successfully.
-* - XST_FAILURE: Callback could not be registered.
-*
-* @note None.
-*
-******************************************************************************/
-int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
- XUsbPs_IntrHandlerFunc CallBackFunc,
- void *CallBackRef, u32 Mask)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- InstancePtr->HandlerFunc = CallBackFunc;
- InstancePtr->HandlerRef = CallBackRef;
- InstancePtr->HandlerMask = Mask;
-
- return XST_SUCCESS;
-}
-
-
-/*****************************************************************************/
-/**
-* This function handles TX buffer interrupts. It is called by the interrupt
-* when a transmit complete interrupt occurs. It returns buffers of completed
-* descriptors to the caller.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpCompl is the Bit mask of endpoints that caused a transmit
-* complete interrupt.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-static void XUsbPs_IntrHandleTX(XUsbPs *InstancePtr, u32 EpCompl)
-{
- int Index;
- u32 Mask;
- int NumEp;
-
- /* Check all endpoints for TX complete bits.
- */
- Mask = 0x00010000;
- NumEp = InstancePtr->DeviceConfig.NumEndpoints;
-
- /* Check for every endpoint if its TX complete bit is
- * set.
- */
- for (Index = 0; Index < NumEp; Index++, Mask <<= 1) {
- XUsbPs_EpIn *Ep;
-
- if (!(EpCompl & Mask)) {
- continue;
- }
- /* The TX complete bit for this endpoint is
- * set. Walk the list of descriptors to see
- * which ones are completed.
- */
- Ep = &InstancePtr->DeviceConfig.Ep[Index].In;
- do {
-
- XUsbPs_dTDInvalidateCache(Ep->dTDTail);
-
- /* If the descriptor is not active then the buffer has
- * not been sent yet.
- */
- if (XUsbPs_dTDIsActive(Ep->dTDTail)) {
- break;
- }
-
-
- if (InstancePtr->DeviceConfig.EpCfg[Index].In.Type ==
- XUSBPS_EP_TYPE_ISOCHRONOUS) {
- if (Ep->HandlerIsoFunc) {
- Ep->HandlerIsoFunc(Ep->HandlerRef,
- Ep->RequestedBytes,
- Ep->BytesTxed);
- }
- } else {
- if (Ep->HandlerFunc) {
- void *BufPtr;
-
- BufPtr = (void *) XUsbPs_ReaddTD(Ep->dTDTail,
- XUSBPS_dTDUSERDATA);
-
- Ep->HandlerFunc(Ep->HandlerRef, Index,
- XUSBPS_EP_EVENT_DATA_TX,
- BufPtr);
- }
- }
-
- Ep->dTDTail = XUsbPs_dTDGetNLP(Ep->dTDTail);
- } while(Ep->dTDTail != Ep->dTDHead);
- }
-}
-
-
-/*****************************************************************************/
-/**
- * This function handles RX buffer interrupts. It is called by the interrupt
- * when a receive complete interrupt occurs. It notifies the callback functions
- * that have been registered with the individual endpoints that data has been
- * received.
- *
- * @param InstancePtr
- * Pointer to the XUsbPs instance of the controller.
- *
- * @param EpCompl
- * Bit mask of endpoints that caused a receive complete interrupt.
- * @return
- * none
- *
- ******************************************************************************/
-static void XUsbPs_IntrHandleRX(XUsbPs *InstancePtr, u32 EpCompl)
-{
- XUsbPs_EpOut *Ep;
- int Index;
- u32 Mask;
- int NumEp;
-
- /* Check all endpoints for RX complete bits. */
- Mask = 0x00000001;
- NumEp = InstancePtr->DeviceConfig.NumEndpoints;
-
-
- /* Check for every endpoint if its RX complete bit is set.*/
- for (Index = 0; Index < NumEp; Index++, Mask <<= 1) {
- int numP = 0;
-
- if (!(EpCompl & Mask)) {
- continue;
- }
- Ep = &InstancePtr->DeviceConfig.Ep[Index].Out;
-
- XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
-
- /* Handle all finished dTDs */
- while (!XUsbPs_dTDIsActive(Ep->dTDCurr)) {
- numP += 1;
- /* We get data RX events for 0 length packets on
- * endpoint 0. We receive and immediately release
- * them again here, but there's no action to be
- * taken.
- */
- if (InstancePtr->DeviceConfig.EpCfg[Index].Out.Type ==
- XUSBPS_EP_TYPE_ISOCHRONOUS){
- if (Index == 0) {
- u8 BufferPtr[64] = {0};
-
- /* Get the data buffer. */
- XUsbPs_EpDataBufferReceive(InstancePtr,
- 0, &BufferPtr[0], 64);
- Ep->MemAlloted = 0;
- }
-
- if (Ep->MemAlloted == 1) {
- XUsbPs_EpGetData(InstancePtr, Index,
- Ep->RequestedBytes);
- } else
- break;
- } else {
- if (Ep->HandlerFunc) {
- Ep->HandlerFunc(Ep->HandlerRef, Index,
- XUSBPS_EP_EVENT_DATA_RX, NULL);
- }
-
- Ep->dTDCurr = XUsbPs_dTDGetNLP(Ep->dTDCurr);
- XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
- }
- }
- /* Re-Prime the endpoint.*/
- XUsbPs_EpPrime(InstancePtr, Index, XUSBPS_EP_DIRECTION_OUT);
- }
-}
-
-
-/*****************************************************************************/
-/**
-* This function handles a RESET interrupt. It will notify the interrupt
-* handler callback of the RESET condition.
-*
-* @param InstancePtr is pointer to the XUsbPs instance of the controller
-* @param IrqSts is the Interrupt status register content.
-* To be passed on to the user.
-*
-* @return None
-*
-* @Note None.
-*
-******************************************************************************/
-static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts)
-{
- u32 Timeout;
- u8 Index;
-
- if (InstancePtr->AppData != NULL)
- InstancePtr->AppData->State = XUSBPS_STATE_DEFAULT;
-
- for (Index = 0; Index < InstancePtr->DeviceConfig.NumEndpoints;
- Index++) {
- InstancePtr->DeviceConfig.Ep[Index].Out.MemAlloted = 0;
- InstancePtr->DeviceConfig.Ep[Index].Out.BufferPtr = NULL;
- InstancePtr->DeviceConfig.Ep[Index].Out.BytesTxed = 0;
- InstancePtr->DeviceConfig.Ep[Index].Out.RequestedBytes = 0;
- InstancePtr->DeviceConfig.Ep[Index].In.BufferPtr = NULL;
- InstancePtr->DeviceConfig.Ep[Index].In.BytesTxed = 0;
- InstancePtr->DeviceConfig.Ep[Index].In.RequestedBytes = 0;
- }
-
- /* Clear all setup token semaphores by reading the
- * XUSBPS_EPSTAT_OFFSET register and writing its value back to
- * itself.
- */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPSTAT_OFFSET,
- XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPSTAT_OFFSET));
-
- /* Clear all the endpoint complete status bits by reading the
- * XUSBPS_EPCOMPL_OFFSET register and writings its value back
- * to itself.
- */
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPCOMPL_OFFSET,
- XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPCOMPL_OFFSET));
-
- /* Cancel all endpoint prime status by waiting until all bits
- * in XUSBPS_EPPRIME_OFFSET are 0 and then writing 0xFFFFFFFF
- * to XUSBPS_EPFLUSH_OFFSET.
- *
- * Avoid hanging here by using a Timeout counter...
- */
- Timeout = XUSBPS_TIMEOUT_COUNTER;
- while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPPRIME_OFFSET) &
- XUSBPS_EP_ALL_MASK) && --Timeout) {
- /* NOP */
- }
- XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF);
-
- /* Make sure that the reset bit in XUSBPS_PORTSCR1_OFFSET is
- * still set at this point. If the code gets to this point and
- * the reset bit has already been cleared we are in trouble and
- * hardware reset is necessary.
- */
- if (!(XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUSBPS_PORTSCR1_OFFSET) &
- XUSBPS_PORTSCR_PR_MASK)) {
- /* Send a notification to the user that a hardware
- * RESET is required. At this point we can only hope
- * that the user registered an interrupt handler and
- * will issue a hardware RESET.
- */
- if (InstancePtr->HandlerFunc) {
- (InstancePtr->HandlerFunc)(InstancePtr->HandlerRef,
- IrqSts);
- }
- else {
- for (;;);
- }
-
- /* If we get here there is nothing more to do. The user
- * should have reset the core.
- */
- return;
- }
-
- /* Check if we have a user handler that needs to be called.
- */
- if (InstancePtr->HandlerFunc) {
- (InstancePtr->HandlerFunc)(InstancePtr->HandlerRef, IrqSts);
- }
-
- /* We are done. After RESET we don't proceed in the interrupt
- * handler.
- */
-}
-
-
-/*****************************************************************************/
-/**
-* This function handles a Setup Packet interrupt. It will notify the interrupt
-* handler callback of the RESET condition.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-*
-* @return None
-*
-* @Note None
-*
-******************************************************************************/
-static void XUsbPs_IntrHandleEp0Setup(XUsbPs *InstancePtr)
-{
-
- XUsbPs_EpOut *Ep;
-
- /* Notify the user. */
- Ep = &InstancePtr->DeviceConfig.Ep[0].Out;
-
- if (Ep->HandlerFunc) {
- Ep->HandlerFunc(Ep->HandlerRef, 0,
- XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED, NULL);
- }
-}
-
-
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bd/f11aea585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bd/f11aea585243001d18b399c1eb9b3628
deleted file mode 100644
index 0f7eb74..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bd/f11aea585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,174 +0,0 @@
-;******************************************************************************
-; Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-; SPDX-License-Identifier: MIT
-;*****************************************************************************
-;****************************************************************************
-;**
-; @file translation_table.s
-;
-; This file contains the initialization for the MMU table in RAM
-; needed by the Cortex A9 processor
-;
-;
-; MODIFICATION HISTORY:
-;
-; Ver Who Date Changes
-; ----- ---- -------- ---------------------------------------------------
-; 1.00a ecm 10/20/09 Initial version
-; 3.07a sgd 07/05/12 Configuring device address spaces as shareable device
-; instead of strongly-ordered.
-; 4.2 pkp 09/02/14 modified translation table entries according to address map
-; 4.2 pkp 09/11/14 modified translation table entries to resolve compilation
-; error for solving CR#822897
-; 6.1 pkp 07/11/16 Corrected comments for memory attributes
-; 6.8 mus 07/12/2018 Mark DDR memory as inner cacheable, if BSP is built
-; with the USE_AMP flag.
-;
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 5.4 pkp 28/01/16 Modified the sleep API to configure Time Stamp
-* generator only when disable using frequency from
-* xparamters.h instead of hardcoding
-* 5.05 pkp 13/04/16 Modified sleep routine to call XTime_StartTimer
-* which enables timer only when it is disabled and
-* read counter value directly from register instead
-* of calling XTime_GetTime for optimization
-* 6.0 mus 08/18/16 Updated the sleep signature. Fix for CR#956899
-* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
-* implementation. Now sleep routines will use Timer
-* specified by the user (i.e. Global timer/TTC timer)
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "sleep.h"
-#include "xtime_l.h"
-#include "xparameters.h"
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#include "xil_sleeptimer.h"
-#endif
-
-/*****************************************************************************/
-/**
-*
-* This API is used to provide delays in seconds
-*
-* @param seconds requested
-*
-* @return 0 always
-*
-* @note None.
-*
-****************************************************************************/
-unsigned sleep_A53(unsigned int seconds)
-{
-#if defined (SLEEP_TIMER_BASEADDR)
- Xil_SleepTTCCommon(seconds, COUNTS_PER_SECOND);
-#else
- XTime tEnd, tCur;
- /* Start global timer counter, it will only be enabled if it is disabled */
- XTime_StartTimer();
-
- tCur = arch_counter_get_cntvct();
- tEnd = tCur + (((XTime) seconds) * COUNTS_PER_SECOND);
- do
- {
- tCur = arch_counter_get_cntvct();
- } while (tCur < tEnd);
-#endif
-
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bf/116bcc565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bf/116bcc565243001d18b399c1eb9b3628
deleted file mode 100644
index 90efcf4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bf/116bcc565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,23 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#include
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) clock_t clock(void);
-}
-#endif
-/*
- * clock -- It supposed to return processor time. We are not implementing
- * this function, as timekeeping is tightly coupled with system, hence
- * always returning 0. Users can override this with their system
- * specific implementation.
- *
- */
-__attribute__((weak)) clock_t clock(void)
-{
- return (0);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bf/60c7f8555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bf/60c7f8555243001d18b399c1eb9b3628
deleted file mode 100644
index 21c8ced..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bf/60c7f8555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,75 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache_l.h
-*
-* Contains L1 and L2 specific functions for the ARM cache functionality
-* used by xcache.c. This functionality is being made available here for
-* more sophisticated users.
-*
-* @addtogroup a9_cache_apis
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 01/24/10 First release
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
-* inside the APIs
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include
-#include "xparameters_ps.h"
-#include "xl2cc_counter.h"
-#include "xl2cc.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void XL2cc_EventCtrReset(void);
-
-/******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @brief This function initializes the event counters in L2 Cache controller
-* with a set of event codes specified by the user.
-*
-* @param Event0: Event code for counter 0.
-* @param Event1: Event code for counter 1.
-*
-* @return None.
-*
-* @note The definitions for event codes XL2CC_* can be found in
-* xl2cc_counter.h.
-*
-*****************************************************************************/
-void XL2cc_EventCtrInit(s32 Event0, s32 Event1)
-{
-
- /* Write event code into cnt1 cfg reg */
- *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_CTRL_OFFSET)) = (((u32)Event1) << 2);
-
- /* Write event code into cnt0 cfg reg */
- *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_CTRL_OFFSET)) = (((u32)Event0) << 2);
-
- /* Reset counters */
- XL2cc_EventCtrReset();
-}
-
-
-/****************************************************************************/
-/**
-*
-* @brief This function starts the event counters in L2 Cache controller.
-*
-* @return None.
-*
-*****************************************************************************/
-void XL2cc_EventCtrStart(void)
-{
- u32 *LocalPtr;
- LocalPtr = (u32 *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET);
- XL2cc_EventCtrReset();
-
- /* Enable counter */
- /* *((volatile u32*)((void *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET))) = 1 */
- *LocalPtr = (u32)1;
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function disables the event counters in L2 Cache controller,
-* saves the counter values and resets the counters.
-*
-* @param EveCtr0: Output parameter which is used to return the value
-* in event counter 0.
-* @param EveCtr1: Output parameter which is used to return the value
-* in event counter 1.
-*
-* @return None.
-*
-*****************************************************************************/
-void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1)
-{
- /* Disable counter */
- *((volatile u32*) (XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0U;
-
- /* Save counter values */
- *EveCtr1 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_VAL_OFFSET));
- *EveCtr0 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_VAL_OFFSET));
-
- XL2cc_EventCtrReset();
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function resets the event counters in L2 Cache controller.
-*
-* @return None.
-*
-*****************************************************************************/
-void XL2cc_EventCtrReset(void)
-{
- *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0x6U;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bf/701713545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bf/701713545243001d18b399c1eb9b3628
deleted file mode 100644
index c1debf9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bf/701713545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,49 +0,0 @@
-# Makefile generated by Xilinx.
-
-DRIVER_LIB_VERSION = 1.0
-PROCESSOR = ps7_cortexa9_0
-LIBRARIES = ${PROCESSOR}/lib/libxil.a
-BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile)
-SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES))
-BSP_SEQUENTIAL_MAKEFILES :=
-BSP_PARALLEL_MAKEFILES := $(filter-out $(BSP_SEQUENTIAL_MAKEFILES),$(BSP_MAKEFILES))
-SEQ_SUBDIRS := $(patsubst %/Makefile, %, $(BSP_SEQUENTIAL_MAKEFILES))
-PAR_SUBDIRS := $(patsubst %/Makefile, %, $(BSP_PARALLEL_MAKEFILES))
-
-ifneq (,$(findstring win,$(RDI_PLATFORM)))
- SHELL = CMD
-endif
-
-all:
- $(MAKE) --no-print-directory seq_libs
- $(MAKE) -j 6 --no-print-directory par_libs
- $(MAKE) --no-print-directory archive
- @echo 'Finished building libraries'
-
-include: $(addsuffix /make.include,$(SUBDIRS))
-
-seq_libs: $(addsuffix /make.libs,$(SEQ_SUBDIRS))
- @echo 'Finished building libraries sequentially.'
-
-par_libs: $(addsuffix /make.libs,$(PAR_SUBDIRS))
- @echo 'Finished building libraries parallelly.'
-
-archive:
- arm-none-eabi-ar -r $(LIBRARIES) $(wildcard $(PROCESSOR)/lib/*.o)
-
-clean: $(addsuffix /make.clean,$(SUBDIRS))
- rm -f ${PROCESSOR}/lib/libxil.a
-
-$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
- cp -f $< $@
-
-%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
- @echo "Running Make include in $(subst /make.include,,$@)"
- $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-%/make.libs: include
- @echo "Running Make libs in $(subst /make.libs,,$@)"
- $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-%/make.clean:
- $(MAKE) -C $(subst /make.clean,,$@) -s clean
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bf/8004ff515243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bf/8004ff515243001d18b399c1eb9b3628
deleted file mode 100644
index fbbab1c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bf/8004ff515243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,325 +0,0 @@
-make all --print-data-base --no-builtin-variables --no-builtin-rules --question
-make: *** No rule to make target 'all'. Stop.
-
-# GNU Make 4.2.1
-# Built for x86_64-pc-linux-gnu
-# Copyright (C) 1988-2016 Free Software Foundation, Inc.
-# License GPLv3+: GNU GPL version 3 or later
-# This is free software: you are free to change and redistribute it.
-# There is NO WARRANTY, to the extent permitted by law.
-
-# Make data base, printed on Fri Sep 16 11:16:57 2022
-
-# Variables
-
-# 'override' directive
-GNUMAKEFLAGS :=
-# automatic
-
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.00 pkp 02/10/14 Initial version
-* 7.1 aru 04/15/19 Updated the events correctly
-* 7.2 mus 01/29/20 Added new macro Xpm_ReadCycleCounterVal, to
-* read PMU cycle counter value
-* 7.2 asa 03/18/20 Add prototypes for new APIs. Deprecate older
-* APIs. Add new macros being used in the new APIs.
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XPMCOUNTER_H /* prevent circular inclusions */
-#define XPMCOUNTER_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/************************** Constant Definitions ****************************/
-
-/* Number of performance counters */
-#define XPM_CTRCOUNT 3U
-
-/* The following constants define the Cortex-R5 Performance Monitor Events */
-
-/*
- * Software increment. The register is incremented only on writes to the
- * Software Increment Register
- */
-#define XPM_EVENT_SOFTINCR 0x00U
-
-/*
- * Instruction cache miss
- * Each Instruction fetch from normal cacheable memory that causes a refill from
- * the level 2 memory system generates this event.Accesses that do not cause a new
- * cache refill, but are satisfied from refilling data of a previous miss are not
- * counted. Where instruction fetches consists of multiple instructions, these
- * accesses count as single events.
- */
-#define XPM_EVENT_INSTRCACHEMISS 0x01
-
-/*
- * Data cache miss
- * Each data read from or write to normal cacheable memory that causes a refill
- * from the level 2 memory system generates this event.Accesses that do not cause
- * a new cache refill, but are satisfied from refilling data of a previous miss are
- * not counted. Each access to a cache line to normal cacheable memory that causes
- * a new linefill is counted,including the multiple transactions of an LDM and STM
- */
-
-#define XPM_EVENT_DATACACHEMISS 0x03
-
-/*
- * Each access to a cache line is counted including the multiple transactions of
- * an LDM, STM, or other operations.
- */
-
-#define XPM_EVENT_DATACACHEACCESS 0x04
-
-/*
- *Data read architecturally executed
- *This evevt occurs for every every instruction that explicitly reads data,
- *including SWP.
- */
-
-#define XPM_EVENT_DATAREAD 0x06
-
-/*
- *Data write architecturally executed
- *This evevt occurs for every every instruction that explicitly writes data,
- *including SWP.
- */
-
-#define XPM_EVENT_DATAWRITE 0x07
-
-/*
- *Instruction architecturally executed
- */
-
-#define XPM_EVENT_INSTR 0x08
-/*
- * Dual-issued pair of instructions architecturally executed
- */
-
-#define XPM_EVENT_DUALINSTR 0x5E
-
-/*
- * Exception taken
- * This event occurs on each exception taken
- */
-
-#define XPM_EVENT_EXCEPTION 0x09
-
-/*
- * Exception return architecturally executed.
- * This event occurs on every exception return
- * for example:
- * RFE,MOVS PC,LDM Rn, {..,PC}^
- */
-
-#define XPM_EVENT_EXCEPTIONRET 0x0A
-
-/*
- * Change to Context ID Executed
- */
-
-#define XPM_EVENT_CHANGETOCONTEXID 0x0B
-
-/*
- * Software Change of PC, except by an exception,
- * architecturally executed
- */
-
-#define XPM_EVENT_SWCHANGE 0x0C
-
-/*
- * B immediate, BL immediate or BLX immediate instruction
- * architecturally executed
- *
- */
-
-#define XPM_EVENT_IMMEDIATEINSTR 0x0D
-
-/*
- * Procedure return architecturally executed, other than exception returns
- * For example:
- * BZ Rm, "LDM Rn, {..,PC}"
- */
-
-#define XPM_EVENT_PROCEDURERET 0x0E
-
-/*
- * Unaligned access architecturally executed
- * This event occurs for each instruction that was to an unaligned
- * address that either triggered an alignment fault, or would have done
- * so if the SCTLR A-bit had been set.
- */
-
-#define XPM_EVENT_UNALIGNACCESS 0x0F
-
-/*
- * Branch mispredicted or not predicted
- * This event ocurs for every pipeline flush
- * caused by a branch
- */
-
-#define XPM_EVENT_BRANCHMISPREDICT 0x10
-
-/*
- * Counts clock cycles when the Cortex-r5 processor is not in WFE/WFI. This
- * event is not exported on the EVENT bus
- */
-
-#define XPM_EVENT_CLOCKCYCLES 0x11U
-
-/*
- * Branches or other change in program flow that could have
- * been predicted by the branch prediction resources of the processor.
- */
-
-#define XPM_EVENT_BRANCHPREDICT 0x12
-
-/*
- * Stall because instruction buffer cannot deliver an instruction
- * This can indicate a cache miss. This event occurs every cycle where
- * the conditions is present.
- */
-
-#define XPM_EVENT_INSTRSTALL 0x40
-
-/*
- * Stall because of data dependency between instructions.
- * This event occurs every cycle where the condition is present.
- */
-
-#define XPM_EVENT_DATASTALL 0x41
-
-/*
- * Data cache write-back
- * This event occurs once for each line that is written back from the cache.
- */
-
-#define XPM_EVENT_DATACACHEWRITE 0x42
-
-/*
- * External memory request
- * Examples of this are cache refill, Non-cacheable accesses, write through
- * writes, cache line evictions(write-back)
- */
-
-#define XPM_EVENT_EXTERNALMEMREQ 0x43U
-
-/*
- * Stall because of LSU being busy
- * This event takes place each clock cycle where the condition is met.
- * A high incidence of this event indicates the pipeline is often waiting
- * for transactions to complete on the external bus.
- */
-
-#define XPM_EVENT_LSUSTALL 0x44
-
-/*
- * Store Buffer was forced to drain completely
- * Examples of this Fir cortex-R5 are DMB, Strongly ordered memory access,
- * or similar events.
- *
- */
-
-#define XPM_EVENT_FORCEDRAINSTORE 0x45
-
-/*
- * Instruction cache tag RAm parity or correctable ECC error
- */
-
-#define XPM_EVENT_INSTRTAGPARITY 0x4A
-
-/*
- * Instruction cache data RAm parity or correctable ECC error
- */
-
-#define XPM_EVENT_INSTRDATAPARITY 0x4B
-
-/*
- * Data cache tag or dirty RAM parity error or correctable ECC error,
- * from data-side or ACP
- */
-
-#define XPM_EVENT_DATATAGPARITY 0x4C
-
-/*
- * Data cache data RAM parity error or correctable ECC error
- */
-
-#define XPM_EVENT_DATADATAPARITY 0x4D
-
-/*
- * TCM fatal ECC error reported from the prefetch unit
- */
-
-#define XPM_EVENT_TCMERRORPREFETCH 0x4E
-
-/*
- * TCM fatal ECC error reported from the load/store unit
- */
-
-#define XPM_EVENT_TCMERRORSTORE 0x4F
-
-/*
- * Instruction cache access
- */
-
-#define XPM_EVENT_INSTRCACHEACCESS 0x58
-
-/*
- * Dual issue case A(branch)
- */
-
-#define XPM_EVENT_DUALISSUEA 0x5A
-
-/*
- * Dual issue case B1,B2,F2(load/store), F2D.
- */
-
-#define XPM_EVENT_DUALISSUEB 0x5B
-
-/*
- * Dual issue other case
- */
-
-#define XPM_EVENT_DUALISSUEOTHER 0x5C
-
-/*
- * Double precision floating point arithmetic or
- * conversion instruction executed.
- */
-
-#define XPM_EVENT_FPA 0x5D
-
-/*
- * Data cache data RAM fatal ECC error
- */
-
-#define XPM_EVENT_DATACACHEDATAERROR 0x60
-
-/*
- * Data cache tag/dirty RAM fatal ECC error, from data-side or ACP
- */
-
-#define XPM_EVENT_DATACACHETAGERROR 0x61
-
-/*
- * Processor livelock because of hard errors or exception vector
- */
-
-#define XPM_EVENT_PROCESSORLIVELOCK 0x62
-
-/*
- * ATCM Multi-bit error
- */
-
-#define XPM_EVENT_ATCMMULTIBITERROR 0x64
-
-/*
- * B0TCM Multi-bit error
- */
-
-#define XPM_EVENT_B0TCMMULTIBITERROR 0x65
-
-/*
- * B1TCM Multi-bit error
- */
-
-#define XPM_EVENT_B1TCMMULTIBITERROR 0x66
-
-/*
- * ATCM Single-bit error
- */
-
-#define XPM_EVENT_ATCMSINGLEBITERROR 0x67
-
-/*
- * B0TCM Single-bit error
- */
-
-#define XPM_EVENT_B0TCMSINGLEBITERROR 0x68
-
-/*
- * B1TCM Single-bit error
- */
-
-#define XPM_EVENT_B1TCMSINGLEBITERROR 0x69
-
-/*
- * TCM correctable ECC error reported by load/store unit
- */
-
-#define XPM_EVENT_TCMERRORLSU 0x6A
-
-/*
- * TCM correctable ECC error reported by prefetch unit
- */
-
-#define XPM_EVENT_TCMERRORPFU 0x6B
-
-/*
- * TCM fatal ECC error reported by AXI slave unit
- */
-
-#define XPM_EVENT_TCMFATALERRORAXI 0x6C
-
-/*
- * TCM correctable ECC error reported by AXI slave unit
- */
-
-#define XPM_EVENT_TCMERRORAXI 0x6D
-
-/*
- * ACP D-cache access, lookup or invalidate
- */
-
-
-#define XPM_EVENT_DCACHEACCESS 0x72
-
-/*
- * ACP D-cache invalidate
- */
-
-#define XPM_EVENT_DCACHEINVALIDATE 0x73
-
-
-/*
- * The following constants define the configurations for Cortex-R5 Performance
- * Monitor Events. Each configuration configures the event counters for a set
- * of events.
- * -----------------------------------------------
- * Config PmCtr0... PmCtr5
- * -----------------------------------------------
- * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR,
- * XPM_EVENT_INSTRCACHEMISS,
- * XPM_EVENT_DATACACHEMISS }
- *
- * XPM_CNTRCFG2 { XPM_EVENT_DATACACHEACCESS,
- * XPM_EVENT_DATAREAD,
- * XPM_EVENT_DATAWRITE }
- *
- * XPM_CNTRCFG3 { XPM_EVENT_INSTR,
- * XPM_EVENT_DUALINSTR,
- * XPM_EVENT_EXCEPTION }
- *
- * XPM_CNTRCFG4 { XPM_EVENT_EXCEPTIONRET,
- * XPM_EVENT_CHANGETOCONTEXID,
- * XPM_EVENT_SWCHANGE }
- *
- * XPM_CNTRCFG5 { XPM_EVENT_IMMEDIATEINSTR,
- * XPM_EVENT_PROCEDURERET,
- * XPM_EVENT_UNALIGNACCESS }
- *
- * XPM_CNTRCFG6 { XPM_EVENT_BRANCHMISPREDICT,
- * XPM_EVENT_CLOCKCYCLES,
- * XPM_EVENT_BRANCHPREDICT }
- *
- * XPM_CNTRCFG7 { XPM_EVENT_INSTRSTALL,
- * XPM_EVENT_DATASTALL,
- * XPM_EVENT_DATACACHEWRITE }
- *
- * XPM_CNTRCFG8 { XPM_EVENT_EXTERNALMEMREQ,
- * XPM_EVENT_LSUSTALL,
- * XPM_EVENT_FORCEDRAINSTORE }
- *
- * XPM_CNTRCFG9 { XPM_EVENT_INSTRTAGPARITY,
- * XPM_EVENT_INSTRDATAPARITY,
- * XPM_EVENT_DATATAGPARITY }
- *
- * XPM_CNTRCFG10 { XPM_EVENT_DATADATAPARITY,
- * XPM_EVENT_TCMERRORPREFETCH,
- * XPM_EVENT_TCMERRORSTORE }
- *
- * XPM_CNTRCFG11 { XPM_EVENT_INSTRCACHEACCESS,
- * XPM_EVENT_DUALISSUEA,
- * XPM_EVENT_DUALISSUEB }
- *
- * XPM_CNTRCFG12 { XPM_EVENT_DUALISSUEOTHER,
- * XPM_EVENT_FPA,
- * XPM_EVENT_DATACACHEDATAERROR }
- *
- * XPM_CNTRCFG13 { XPM_EVENT_DATACACHETAGERROR,
- * XPM_EVENT_PROCESSORLIVELOCK,
- * XPM_EVENT_ATCMMULTIBITERROR }
- *
- * XPM_CNTRCFG14 { XPM_EVENT_B0TCMMULTIBITERROR,
- * XPM_EVENT_B1TCMMULTIBITERROR,
- * XPM_EVENT_ATCMSINGLEBITERROR }
- *
- * XPM_CNTRCFG15 { XPM_EVENT_B0TCMSINGLEBITERROR,
- * XPM_EVENT_B1TCMSINGLEBITERROR,
- * XPM_EVENT_TCMERRORLSU }
- *
- * XPM_CNTRCFG16 { XPM_EVENT_TCMERRORPFU,
- * XPM_EVENT_TCMFATALERRORAXI,
- * XPM_EVENT_TCMERRORAXI }
- */
-#define XPM_CNTRCFG1 0
-#define XPM_CNTRCFG2 1
-#define XPM_CNTRCFG3 2
-#define XPM_CNTRCFG4 3
-#define XPM_CNTRCFG5 4
-#define XPM_CNTRCFG6 5
-#define XPM_CNTRCFG7 6
-#define XPM_CNTRCFG8 7
-#define XPM_CNTRCFG9 8
-#define XPM_CNTRCFG10 9
-#define XPM_CNTRCFG11 10
-#define XPM_CNTRCFG12 11
-#define XPM_CNTRCFG13 12
-#define XPM_CNTRCFG14 13
-#define XPM_CNTRCFG15 14
-#define XPM_CNTRCFG16 15
-#endif
-
-#define XPM_NO_COUNTERS_AVAILABLE 0xFFU
-#define XPM_MAX_EVENTHANDLER_ID 0x2U
-#define XPM_EVENT_CNTRS_BIT_MASK 0x7U
-#define XPM_ALL_EVENT_CNTRS_IN_USE 0x7U
-#define XPM_EVENT_CNTRS_MASK 0x3U
-
-/**************************** Type Definitions ******************************/
-/**
- *@endcond
- */
-/***************** Macros (Inline Functions) Definitions ********************/
-#if defined(__GNUC__)
-#define Xpm_ReadCycleCounterVal() mfcp(XREG_CP15_PERF_CYCLE_COUNTER)
-#elif defined (__ICCARM__)
-#define Xpm_ReadCycleCounterVal(val) mfcp(XREG_CP15_PERF_CYCLE_COUNTER,val)
-#endif
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-/* Interface functions to access performance counters from abstraction layer */
-#if defined(__GNUC__)
-void Xpm_SetEvents(s32 PmcrCfg) __attribute__ ((deprecated));
-void Xpm_GetEventCounters(u32 *PmCtrValue) __attribute__ ((deprecated));
-#else
-void Xpm_SetEvents(s32 PmcrCfg);
-void Xpm_GetEventCounters(u32 *PmCtrValue);
-#endif
-u32 Xpm_DisableEvent(u32 EventHandlerId);
-u32 Xpm_SetUpAnEvent(u32 EventID);
-u32 Xpm_GetEventCounter(u32 EventHandlerId, u32 *CntVal);
-void Xpm_DisableEventCounters(void);
-void Xpm_EnableEventCounters (void);
-void Xpm_ResetEventCounters (void);
-
-/* This is helper function for sleep/usleep APIs */
-void Xpm_SleepPerfCounter(u32 delay, u64 frequency);
-
-#ifdef __cplusplus
-}
-#endif
-
-/**
-* @} End of "addtogroup r5_event_counter_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bf/c091ab555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bf/c091ab555243001d18b399c1eb9b3628
deleted file mode 100644
index 2d1aad9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bf/c091ab555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,49 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/*
- * This module contains the function `__low_level_init', a function
- * that is called before the `main' function of the program. Normally
- * low-level initializations - such as setting the preferred interrupt
- * level or setting the watchdog - can be performed here.
- *
- * Note that this function is called before the data segments are
- * initialized, this means that this function cannot rely on the
- * values of global or static variables.
- *
- * When this function returns zero, the startup code will inhibit the
- * initialization of the data segments. The result is faster startup,
- * the drawback is that neither global nor static data will be
- * initialized.
- */
-
-#include "xil_types.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-s32 __low_level_init(void);
-
-s32 __low_level_init(void)
-{
- /*==================================*/
- /* Initialize hardware. */
- /*==================================*/
-
- /*==================================*/
- /* Choose if segment initialization */
- /* should be done or not. */
- /* Return: 0 to omit seg_init */
- /* 1 to run seg_init */
- /*==================================*/
- return 1;
-}
-
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bf/f016d3555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bf/f016d3555243001d18b399c1eb9b3628
deleted file mode 100644
index 63d535c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/bf/f016d3555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,12 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#include "xil_types.h"
-/* Stub for istty sys-call */
-__weak s32 _sys_istty(u32* f)
-{
- /* cannot read/write files */
- return 1;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c/803e13545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c/803e13545243001d18b399c1eb9b3628
deleted file mode 100644
index dc5ac1c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c/803e13545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,3 +0,0 @@
-# generated by Xilinx.
-
-DEPENDENCY_FLAGS= -MMD -MP
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c/80af15545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c/80af15545243001d18b399c1eb9b3628
deleted file mode 100644
index b80c577..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c/80af15545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,281 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#ifndef PROFILE_TIMER_HW_H
-#define PROFILE_TIMER_HW_H
-
-#include "profile.h"
-
-#ifdef PROC_PPC
-#if defined __GNUC__
-# define SYNCHRONIZE_IO __asm__ volatile ("eieio")
-#elif defined __DCC__
-# define SYNCHRONIZE_IO __asm volatile(" eieio")
-#else
-# define SYNCHRONIZE_IO
-#endif
-#endif
-
-#ifdef PROC_PPC
-#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
-#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
-#else
-#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
-#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
-#endif
-
-#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
- ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \
- (u32)(RegOffset)), (u32)(ValueToWrite))
-
-#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
- ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
-
-#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
- ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
- (RegisterValue))
-
-#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \
- ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
-
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef PROC_PPC
-#include "xexception_l.h"
-#include "xtime_l.h"
-#include "xpseudo_asm.h"
-#endif
-
-#ifdef TIMER_CONNECT_INTC
-#include "xintc_l.h"
-#include "xintc.h"
-#endif /* TIMER_CONNECT_INTC */
-
-#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
-#include "xtmrctr_l.h"
-#endif
-
-#ifdef PROC_CORTEXA9
-#include "xscutimer_hw.h"
-#include "xscugic.h"
-#endif
-
-extern u32 timer_clk_ticks ;
-
-/*--------------------------------------------------------------------
- * PowerPC Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_PPC
-
-#ifdef PPC_PIT_INTERRUPT
-u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */
-#endif
-
-#ifdef PROC_PPC440
-#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
-#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
-#define XREG_SPR_PIT XREG_SPR_DEC
-#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
-#endif
-
-/* --------------------------------------------------------------------
- * Disable the Timer - During Profiling
- *
- * For PIT Timer -
- * 1. XTime_PITDisableInterrupt() ;
- * 2. Store the remaining timer clk tick
- * 3. Stop the PIT Timer
- *-------------------------------------------------------------------- */
-
-#ifdef PPC_PIT_INTERRUPT
-#define disable_timer() \
- { \
- u32 val; \
- val=mfspr(XREG_SPR_TCR); \
- mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \
- timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
- mtspr(XREG_SPR_PIT, 0); \
- }
-#else
-#define disable_timer() \
- { \
- u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(addr); \
- tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
- ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
- }
-#endif
-
-
-
-/* --------------------------------------------------------------------
- * Enable the Timer
- *
- * For PIT Timer -
- * 1. Load the remaining timer clk ticks
- * 2. XTime_PITEnableInterrupt() ;
- *-------------------------------------------------------------------- */
-#ifdef PPC_PIT_INTERRUPT
-#define enable_timer() \
- { \
- u32 val; \
- val=mfspr(XREG_SPR_TCR); \
- mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
- mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
- }
-#else
-#define enable_timer() \
- { \
- u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(addr); \
- tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
- ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
- }
-#endif
-
-
-
-/* --------------------------------------------------------------------
- * Send Ack to Timer Interrupt
- *
- * For PIT Timer -
- * 1. Load the timer clk ticks
- * 2. Enable AutoReload and Interrupt
- * 3. Clear PIT Timer Status bits
- *-------------------------------------------------------------------- */
-#ifdef PPC_PIT_INTERRUPT
-#define timer_ack() \
- { \
- u32 val; \
- mtspr(XREG_SPR_PIT, timer_clk_ticks); \
- mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
- val=mfspr(XREG_SPR_TCR); \
- mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
- }
-#else
-#define timer_ack() \
- { \
- u32 csr; \
- csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
- ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
- }
-#endif
-
-/*-------------------------------------------------------------------- */
-#endif /* PROC_PPC */
-/* -------------------------------------------------------------------- */
-
-
-
-
-/* --------------------------------------------------------------------
- * MicroBlaze Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_MICROBLAZE
-
-/* --------------------------------------------------------------------
- * Disable the Timer during Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define disable_timer() \
- { \
- u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
- Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
- Addr += (u32)XTC_TCSR_OFFSET; \
- u32 tmp_v = ProfIo_In32(Addr); \
- tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
- u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
- OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
- OutAddr += (u32)XTC_TCSR_OFFSET; \
- ProfIo_Out32(OutAddr, (u32)tmp_v); \
- }
-
-
-/* --------------------------------------------------------------------
- * Enable the Timer after Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define enable_timer() \
- { \
- u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
- Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
- Addr += (u32)XTC_TCSR_OFFSET; \
- u32 tmp_v = (u32)ProfIo_In32(Addr); \
- tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \
- ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
- }
-
-
-/* --------------------------------------------------------------------
- * Send Ack to Timer Interrupt
- *
- *-------------------------------------------------------------------- */
-#define timer_ack() \
- { \
- u32 csr; \
- csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \
- ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \
- }
-
-/*-------------------------------------------------------------------- */
-#endif /* PROC_MICROBLAZE */
-/*-------------------------------------------------------------------- */
-
-/* --------------------------------------------------------------------
- * Cortex A9 Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_CORTEXA9
-
-/* --------------------------------------------------------------------
- * Disable the Timer during Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define disable_timer() \
-{ \
- u32 Reg; \
- Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
- Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
- Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
-}
-
-
-/* --------------------------------------------------------------------
- * Enable the Timer after Call-Graph Data collection
- *
- *-------------------------------------------------------------------- */
-#define enable_timer() \
-{ \
- u32 Reg; \
- Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
- Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
- Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
-}
-
-
-/* --------------------------------------------------------------------
- * Send Ack to Timer Interrupt
- *
- *-------------------------------------------------------------------- */
-#define timer_ack() \
-{ \
- Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
- (u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
-}
-
-/*-------------------------------------------------------------------- */
-#endif /* PROC_CORTEXA9 */
-/*-------------------------------------------------------------------- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c/814e1c595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c/814e1c595243001d18b399c1eb9b3628
deleted file mode 100644
index f233224..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c/814e1c595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,552 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.c
-*
-* Contains required functions for the ARM cache functionality.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.00 pkp 02/20/14 First release
-* 6.2 mus 01/27/17 Updated to support IAR compiler
-* 7.3 dp 06/25/20 Updated to support armclang compiler
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xil_io.h"
-#include "xpseudo_asm.h"
-#include "xparameters.h"
-#include "xreg_cortexr5.h"
-#include "xil_exception.h"
-
-
-/************************** Variable Definitions *****************************/
-
-#define IRQ_FIQ_MASK 0xC0 /* Mask IRQ and FIQ interrupts in cpsr */
-
-#if defined (__clang__)
-extern s32 Image$$ARM_LIB_STACK$$Limit;
-extern s32 Image$$ARM_UNDEF_STACK$$Base;
-#elif defined (__GNUC__)
-extern s32 _stack_end;
-extern s32 __undef_stack;
-#endif
-
-/****************************************************************************/
-/************************** Function Prototypes ******************************/
-
-/****************************************************************************/
-/**
-* @brief Enable the Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheEnable(void)
-{
- register u32 CtrlReg;
-
- /* enable caches only if they are disabled */
-#if defined (__GNUC__)
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
-#endif
- if ((CtrlReg & XREG_CP15_CONTROL_C_BIT)==0x00000000U) {
- /* invalidate the Data cache */
- Xil_DCacheInvalidate();
-
- /* enable the Data cache */
- CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- }
-}
-
-/****************************************************************************/
-/**
-* @brief Disable the Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheDisable(void)
-{
- register u32 CtrlReg;
-
- /* clean and invalidate the Data cache */
- Xil_DCacheFlush();
-
- /* disable the Data cache */
-#if defined (__GNUC__)
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
-#endif
-
- CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the entire Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheInvalidate(void)
-{
- u32 currmask;
- u32 stack_start,stack_end,stack_size;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
-#if defined (__clang__)
- stack_end = (u32 )&Image$$ARM_LIB_STACK$$Limit;
- stack_start = (u32 )&Image$$ARM_UNDEF_STACK$$Base;
-#elif defined (__GNUC__)
- stack_end = (u32 )&_stack_end;
- stack_start = (u32 )&__undef_stack;
-#endif
-
-#if defined(__GNUC__) || defined(__clang__)
- stack_size = stack_start-stack_end;
-
- /* Flush stack memory to save return address */
- Xil_DCacheFlushRange(stack_end, stack_size);
-#endif
-
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
-
- /*invalidate all D cache*/
- mtcp(XREG_CP15_INVAL_DC_ALL, 0);
-
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate a Data cache line. If the byte specified by the
-* address (adr) is cached by the data cache, the cacheline
-* containing that byte is invalidated.If the cacheline is modified
-* (dirty), the modified contents are lost and are NOT written
-* to system memory before the line is invalidated.
-*
-*
-* @param adr: 32bit address of the data to be flushed.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_DCacheInvalidateLine(INTPTR adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
- mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
-
- /* Wait for invalidate to complete */
- dsb();
-
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the Data cache for the given address range.
-* If the bytes specified by the address (adr) are cached by the
-* Data cache,the cacheline containing that byte is invalidated.
-* If the cacheline is modified (dirty), the modified contents are
-* lost and are NOT written to system memory before the line is
-* invalidated.
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
-{
- const u32 cacheline = 32U;
- u32 end;
- u32 tempadr = adr;
- u32 tempend;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- end = tempadr + len;
- tempend = end;
- /* Select L1 Data cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
-
- if ((tempadr & (cacheline-1U)) != 0U) {
- tempadr &= (~(cacheline - 1U));
-
- Xil_DCacheFlushLine(tempadr);
- }
- if ((tempend & (cacheline-1U)) != 0U) {
- tempend &= (~(cacheline - 1U));
-
- Xil_DCacheFlushLine(tempend);
- }
-
- while (tempadr < tempend) {
-
- /* Invalidate Data cache line */
- asm_inval_dc_line_mva_poc(tempadr);
-
- tempadr += cacheline;
- }
- }
-
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the entire Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheFlush(void)
-{
- register u32 CsidReg, C7Reg;
- u32 CacheSize, LineSize, NumWays;
- u32 Way, WayIndex, Set, SetIndex, NumSet;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- /* Select cache level 0 and D cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
-
-#if defined (__GNUC__)
- CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_CACHE_SIZE_ID,CsidReg);
-#endif
- /* Determine Cache Size */
-
- CacheSize = (CsidReg >> 13U) & 0x000001FFU;
- CacheSize += 0x00000001U;
- CacheSize *= (u32)128; /* to get number of bytes */
-
- /* Number of Ways */
- NumWays = (CsidReg & 0x000003ffU) >> 3U;
- NumWays += 0x00000001U;
-
- /* Get the cacheline size, way size, index size from csidr */
- LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
-
- NumSet = CacheSize/NumWays;
- NumSet /= (0x00000001U << LineSize);
-
- Way = 0U;
- Set = 0U;
-
- /* Invalidate all the cachelines */
- for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set;
- /* Flush by Set/Way */
- asm_clean_inval_dc_line_sw(C7Reg);
-
- Set += (0x00000001U << LineSize);
- }
- Set = 0U;
- Way += 0x40000000U;
- }
-
- /* Wait for flush to complete */
- dsb();
- mtcpsr(currmask);
-
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush a Data cache line. If the byte specified by the address (adr)
-* is cached by the Data cache, the cacheline containing that byte is
-* invalidated. If the cacheline is modified (dirty), the entire
-* contents of the cacheline are written to system memory before the
-* line is invalidated.
-*
-* @param adr: 32bit address of the data to be flushed.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_DCacheFlushLine(INTPTR adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
-
- mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
-
- /* Wait for flush to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the Data cache for the given address range.
-* If the bytes specified by the address (adr) are cached by the
-* Data cache, the cacheline containing those bytes is invalidated.If
-* the cacheline is modified (dirty), the written to system memory
-* before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be flushed.
-* @param len: Length of the range to be flushed in bytes
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheFlushRange(INTPTR adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0x00000000U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr &= ~(cacheline - 1U);
-
- while (LocalAddr < end) {
- /* Flush Data cache line */
- asm_clean_inval_dc_line_mva_poc(LocalAddr);
-
- LocalAddr += cacheline;
- }
- }
- dsb();
- mtcpsr(currmask);
-}
-/****************************************************************************/
-/**
-* @brief Store a Data cache line. If the byte specified by the address
-* (adr) is cached by the Data cache and the cacheline is modified
-* (dirty), the entire contents of the cacheline are written to
-* system memory.After the store completes, the cacheline is marked
-* as unmodified (not dirty).
-*
-* @param adr: 32bit address of the data to be stored
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_DCacheStoreLine(INTPTR adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
- mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1F)));
-
- /* Wait for store to complete */
- dsb();
- isb();
-
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Enable the instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ICacheEnable(void)
-{
- register u32 CtrlReg;
-
- /* enable caches only if they are disabled */
-#if defined (__GNUC__)
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-#endif
- if ((CtrlReg & XREG_CP15_CONTROL_I_BIT)==0x00000000U) {
- /* invalidate the instruction cache */
- mtcp(XREG_CP15_INVAL_IC_POU, 0);
-
- /* enable the instruction cache */
- CtrlReg |= (XREG_CP15_CONTROL_I_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- }
-}
-
-/****************************************************************************/
-/**
-* @brief Disable the instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ICacheDisable(void)
-{
- register u32 CtrlReg;
-
- dsb();
-
- /* invalidate the instruction cache */
- mtcp(XREG_CP15_INVAL_IC_POU, 0);
-
- /* disable the instruction cache */
-#if defined (__GNUC__)
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
-#endif
-
- CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the entire instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ICacheInvalidate(void)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1);
-
- /* invalidate the instruction cache */
- mtcp(XREG_CP15_INVAL_IC_POU, 0);
-
- /* Wait for invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate an instruction cache line.If the instruction specified
-* by the address is cached by the instruction cache, the
-* cacheline containing that instruction is invalidated.
-*
-* @param adr: 32bit address of the instruction to be invalidated.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_ICacheInvalidateLine(INTPTR adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1);
- mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1F)));
-
- /* Wait for invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the instruction cache for the given address range.
-* If the bytes specified by the address (adr) are cached by the
-* Data cache, the cacheline containing that byte is invalidated.
-* If the cachelineis modified (dirty), the modified contents are
-* lost and are NOT written to system memory before the line is
-* invalidated.
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- if (len != 0x00000000U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Select cache L0 I-cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
-
- while (LocalAddr < end) {
-
- /* Invalidate L1 I-cache line */
- asm_inval_ic_line_mva_pou(LocalAddr);
-
- LocalAddr += cacheline;
- }
- }
-
- /* Wait for invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c/9036e2595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c/9036e2595243001d18b399c1eb9b3628
deleted file mode 100644
index dfb1d2d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c/9036e2595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,224 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xadcps_intr.c
-* @addtogroup xadcps_v2_6
-* @{
-*
-* This file contains interrupt handling API functions of the XADC
-* device.
-*
-* The device must be configured at hardware build time to support interrupt
-* for all the functions in this file to work.
-*
-* Refer to xadcps.h header file and device specification for more information.
-*
-* @note
-*
-* Calling the interrupt functions without including the interrupt component will
-* result in asserts if asserts are enabled, and will result in a unpredictable
-* behavior if the asserts are not enabled.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xadcps.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-
-/****************************************************************************/
-/**
-*
-* This function enables the specified interrupts in the device.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Mask is the bit-mask of the interrupts to be enabled.
-* Bit positions of 1 will be enabled. Bit positions of 0 will
-* keep the previous setting. This mask is formed by OR'ing
-* XADCPS_INTX_* bits defined in xadcps_hw.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Disable the specified interrupts in the IPIER.
- */
- RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
- XADCPS_INT_MASK_OFFSET);
- RegValue &= ~(Mask & XADCPS_INTX_ALL_MASK);
- XAdcPs_WriteReg(InstancePtr->Config.BaseAddress,
- XADCPS_INT_MASK_OFFSET,
- RegValue);
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function disables the specified interrupts in the device.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Mask is the bit-mask of the interrupts to be disabled.
-* Bit positions of 1 will be disabled. Bit positions of 0 will
-* keep the previous setting. This mask is formed by OR'ing
-* XADCPS_INTX_* bits defined in xadcps_hw.h.
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Enable the specified interrupts in the IPIER.
- */
- RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
- XADCPS_INT_MASK_OFFSET);
- RegValue |= (Mask & XADCPS_INTX_ALL_MASK);
- XAdcPs_WriteReg(InstancePtr->Config.BaseAddress,
- XADCPS_INT_MASK_OFFSET,
- RegValue);
-}
-/****************************************************************************/
-/**
-*
-* This function returns the enabled interrupts read from the Interrupt Mask
-* Register (IPIER). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h to
-* interpret the returned value.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return A 32-bit value representing the contents of the I.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Return the value read from the Interrupt Enable Register.
- */
- return (~ XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
- XADCPS_INT_MASK_OFFSET) & XADCPS_INTX_ALL_MASK);
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the interrupt status read from Interrupt Status
-* Register(IPISR). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h
-* to interpret the returned value.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return A 32-bit value representing the contents of the IPISR.
-*
-* @note The device must be configured at hardware build time to include
-* interrupt component for this function to work.
-*
-*****************************************************************************/
-u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Return the value read from the Interrupt Status register.
- */
- return XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
- XADCPS_INT_STS_OFFSET) & XADCPS_INTX_ALL_MASK;
-}
-
-/****************************************************************************/
-/**
-*
-* This function clears the specified interrupts in the Interrupt Status
-* Register (IPISR).
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Mask is the bit-mask of the interrupts to be cleared.
-* Bit positions of 1 will be cleared. Bit positions of 0 will not
-* change the previous interrupt status. This mask is formed by
-* OR'ing XADCPS_IPIXR_* bits which are defined in xadcps_hw.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Clear the specified interrupts in the Interrupt Status register.
- */
- RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
- XADCPS_INT_STS_OFFSET);
- RegValue &= (Mask & XADCPS_INTX_ALL_MASK);
- XAdcPs_WriteReg(InstancePtr->Config.BaseAddress, XADCPS_INT_STS_OFFSET,
- RegValue);
-
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c0/01b0a8595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c0/01b0a8595243001d18b399c1eb9b3628
deleted file mode 100644
index 85a1af4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c0/01b0a8595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,202 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2012 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_mmu.c
-*
-* This file provides APIs for enabling/disabling MMU and setting the memory
-* attributes for sections, in the MMU translation table.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 01/12/12 Initial version
-* 3.05a asa 03/10/12 Modified the Xil_EnableMMU to invalidate the caches
-* before enabling back.
-* 3.05a asa 04/15/12 Modified the Xil_SetTlbAttributes routine so that
-* translation table and branch predictor arrays are
-* invalidated, D-cache flushed before the attribute
-* change is applied. This is done so that the user
-* need not call Xil_DisableMMU before calling
-* Xil_SetTlbAttributes.
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-* 3.11a asa 09/23/13 Modified Xil_SetTlbAttributes to flush the complete
-* D cache after the translation table update. Removed the
-* redundant TLB invalidation in the same API at the beginning.
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-* It fixes CR#1008309.
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-#include "xil_mmu.h"
-#include "xil_errata.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-#define ARM_AR_MEM_TTB_SECT_SIZE 1024*1024
-#define ARM_AR_MEM_TTB_SECT_SIZE_MASK (~(ARM_AR_MEM_TTB_SECT_SIZE-1UL))
-/************************** Variable Definitions *****************************/
-
-extern u32 MMUTable;
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-* @brief This function sets the memory attributes for a section covering 1MB
-* of memory in the translation table.
-*
-* @param Addr: 32-bit address for which memory attributes need to be set.
-* @param attrib: Attribute for the given memory region. xil_mmu.h contains
-* definitions of commonly used memory attributes which can be
-* utilized for this function.
-*
-*
-* @return None.
-*
-* @note The MMU or D-cache does not need to be disabled before changing a
-* translation table entry.
-*
-******************************************************************************/
-void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib)
-{
- u32 *ptr;
- u32 section;
-
- section = Addr / 0x100000U;
- ptr = &MMUTable;
- ptr += section;
- if(ptr != NULL) {
- *ptr = (Addr & 0xFFF00000U) | attrib;
- }
-
- Xil_DCacheFlush();
-
- mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
- /* Invalidate all branch predictors */
- mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
-
- dsb(); /* ensure completion of the BP and TLB invalidation */
- isb(); /* synchronize context on this processor */
-}
-
-/*****************************************************************************/
-/**
-* @brief Enable MMU for cortex A9 processor. This function invalidates the
-* instruction and data caches, and then enables MMU.
-*
-* @return None.
-*
-******************************************************************************/
-void Xil_EnableMMU(void)
-{
- u32 Reg;
- Xil_DCacheInvalidate();
- Xil_ICacheInvalidate();
-
-#ifdef __GNUC__
- Reg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, Reg);
-#else
- { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
- Reg = Cp15Reg; }
-#endif
- Reg |= (u32)0x05U;
- mtcp(XREG_CP15_SYS_CONTROL, Reg);
-
- dsb();
- isb();
-}
-
-/*****************************************************************************/
-/**
-* @brief Disable MMU for Cortex A9 processors. This function invalidates
-* the TLBs, Branch Predictor Array and flushed the D Caches before
-* disabling the MMU.
-*
-* @return None.
-*
-* @note When the MMU is disabled, all the memory accesses are treated as
-* strongly ordered.
-******************************************************************************/
-void Xil_DisableMMU(void)
-{
- u32 Reg;
-
- mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
- mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
- Xil_DCacheFlush();
-
-#ifdef __GNUC__
- Reg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, Reg);
-#else
- { volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
- Reg = Cp15Reg; }
-#endif
- Reg &= (u32)(~0x05U);
-#ifdef CONFIG_ARM_ERRATA_794073
- /* Disable Branch Prediction */
- Reg &= (u32)(~0x800U);
-#endif
- mtcp(XREG_CP15_SYS_CONTROL, Reg);
-}
-
-/*****************************************************************************/
-/**
-* @brief Memory mapping for Cortex A9 processor.
-*
-* @param PhysAddr is physical address.
-* @param size is size of region.
-* @param flags is flags used to set translation table.
-*
-* @return Pointer to virtual address.
-*
-* @note: Previously this was implemented in libmetal. Move to embeddedsw as this
-* functionality is specific to A9 processor.
-*
-******************************************************************************/
-void* Xil_MemMap(UINTPTR PhysAddr, size_t size, u32 flags)
-{
- u32 Sectionoffset;
- u32 Ttbaddr;
-
- if (!flags)
- return (void*)PhysAddr;
-
- /* Ensure alignment on a section boundary */
- PhysAddr &= ARM_AR_MEM_TTB_SECT_SIZE_MASK;
-
- /* Loop through entire region of memory (one MMU section at a time).
- Each section requires a TTB entry. */
- for (Sectionoffset = 0; Sectionoffset < size;
- Sectionoffset += ARM_AR_MEM_TTB_SECT_SIZE) {
- /* Calculate translation table entry for this memory section */
- Ttbaddr = (PhysAddr + Sectionoffset);
-
- /* Write translation table entry value to entry address */
- Xil_SetTlbAttributes(Ttbaddr, flags);
- }
- return (void*)PhysAddr;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c0/10b434555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c0/10b434555243001d18b399c1eb9b3628
deleted file mode 100644
index fa7d3f2..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c0/10b434555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,539 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2018 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file translation_table.s
-*
-* @addtogroup a53_64_boot_code
-* @{
-*
translation_table.S
-* The translation_table.S contains a static page table required by MMU for
-* cortex-A72. This translation table is flat mapped (input address = output
-* address) with default memory attributes defined for Versal
-* architecture. It utilizes translation granual size of 4KB with 2MB section
-* size for initial 5GB memory and 1GB section size for memory after 5GB.
-* The overview of translation table memory attributes is described below.
-*
-*| Name | Memory Range | Def. in Translation Table |
-*|-----------------------|-----------------------------------|-----------------------------|
-*| DDR | 0x000_0000_0000 - 0x000_7FFF_FFFF | Normal WB Cacheable |
-*| LPD_AFI_FS | 0x000_8000_0000 - 0x000_9FFF_FFFF | Strongly Ordered |
-*| Reserved | 0x000_A000_0000 - 0x000_A3FF_FFFF | Unassigned |
-*| FPD_AFI_0 | 0x000_A400_0000 - 0x000_AFFF_FFFF | Strongly Ordered |
-*| FPD_AFI_1 | 0x000_B000_0000 - 0x000_BFFF_FFFF | Strongly Ordered |
-*| QSPI | 0x000_C000_0000 - 0x000_DFFF_FFFF | Strongly Ordered |
-*| PCIE region 0 | 0x000_E000_0000 - 0x000_EFFF_FFFF | Strongly Ordered |
-*| PMC | 0x000_F000_0000 - 0x000_F7FF_FFFF | Strongly Ordered |
-*| STM_CORESIGHT | 0x000_F800_0000 - 0x000_F8FF_FFFF | Strongly Ordered |
-*| GIC | 0x000_F900_0000 - 0x000_F90F_FFFF | Strongly Ordered |
-*| Reserved | 0x000_F910_0000 - 0x000_FBFF_FFFF | Unassigned |
-*| CPM | 0x000_FC00_0000 - 0x000_FCFF_FFFF | Strongly Ordered |
-*| FPD slaves | 0x000_FD00_0000 - 0x000_FDFF_FFFF | Strongly Ordered |
-*| LPD slaves | 0x000_FE00_0000 - 0x000_FFDF_FFFF | Strongly Ordered |
-*| OCM | 0x000_FFE0_0000 - 0xFFF_FFFF_FFFF | Normal WB Cacheable |
-*| PMC region 0-3 | 0x001_0000_0000 - 0x001_1FFF_FFFF | Strongly Ordered |
-*| Reserved | 0x001_2000_0000 - 0x001_FFFF_FFFF | Unassigned |
-*| ME Array 0-3 | 0x002_0000_0000 - 0x002_FFFF_FFFF | Strongly Ordered |
-*| Reserved | 0x003_0000_0000 - 0x003_FFFF_FFFF | Unassigned |
-*| PL- via PS | 0x004_0000_0000 - 0x005_FFFF_FFFF | Strongly Ordered |
-*| PCIe region 1 | 0x006_0000_0000 - 0x007_FFFF_FFFF | Strongly Ordered |
-*| DDR | 0x008_0000_0000 - 0x00F_FFFF_FFFF | Normal WB Cacheable |
-*| Reserved | 0x010_0000_0000 - 0x03F_FFFF_FFFF | Unassigned |
-*| HBM 0-3 | 0x040_0000_0000 - 0x07F_FFFF_FFFF | Strongly Ordered |
-*| PCIe region 2 | 0x080_0000_0000 - 0x0BF_FFFF_FFFF | Strongly Ordered |
-*| DDR | 0x0C0_0000_0000 - 0x1B7_7FFF_FFFF | Normal WB Cacheable |
-*| Reserved | 0x1B7_8000_0000 - 0x1FF_FFFF_FFFF | Unassigned |
-*| PL- Via NoC | 0x200_0000_0000 - 0x3FF_FFFF_FFFF | Strongly Ordered |
-*| PL- Via PS | 0x400_0000_0000 - 0x4FF_FFFF_FFFF | Strongly Ordered |
-*| DDR CH1-CH3 | 0x500_0000_0000 - 0x7FF_FFFF_FFFF | Normal WB Cacheable |
-*| PL- Via NoC | 0x800_0000_0000 - 0xFFF_FFFF_FFFF | Strongly Ordered |
-*
-* @note
-*
-* For DDR region 0x0000000000 - 0x007FFFFFFF, a system where DDR is less than
-* 2GB, region after DDR and before PL is marked as undefined/reserved in
-* translation table. Region 0xF9100000 - 0xF91FFFFF is reserved memory in
-* 0x00F9000000 - 0x00F91FFFFF range, but it is marked as strongly ordered
-* because minimum section size in translation table section is 2MB.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 7.00 mus 05/21/14 Initial version
-* 7.00 mus 03/16/19 Updated translation table to mark DDR regions as
-* memory, based on the DDR size in hdf
-* 7.1 mus 08/29/19 Updated translation table entries for DDR_CH_1,
-* DDR_CH_2 and DDR_CH_3 based on respective size in hdf
-* 7.3 mus 09/10/20 Updated translation table entries for DDR regions, to
-* support HW designs, where DDR memory is mapped at
-* address other than DDR region base address. It fixes
-* CR#1073099.
-*
-*
-******************************************************************************/
-#include "xparameters.h"
-#include "bspconfig.h"
-
- .globl MMUTableL0
- .globl MMUTableL1
- .globl MMUTableL2
-
- .set UNDEF_START, 0
-
- /* Base addresses for all DDR regions in Versal SoC */
- .set DDR_LOW_0_REGION_START_ADDR, 0x0000000000 /* 0x0000_0000_0000 */
- .set DDR_LOW_1_REGION_START_ADDR, 0x800000000 /* 0x0008_0000_0000 */
- .set DDR_LOW_2_REGION_START_ADDR, 0xC000000000 /* 0x00C0_0000_0000 */
- .set DDR_LOW_3_REGION_START_ADDR, 0x10000000000 /* 0x0100_0000_0000 */
- .set DDR_CH_1_REGION_START_ADDR, 0x50000000000 /* 0x0500_0000_0000 */
- .set DDR_CH_2_REGION_START_ADDR, 0x60000000000 /* 0x0600_0000_0000 */
- .set DDR_CH_3_REGION_START_ADDR, 0x70000000000 /* 0x0700_0000_0000 */
-
- .set reserved, 0x0 /* Fault*/
- #if EL1_NONSECURE
- .set Memory, 0x405 | (2 << 8) | (0x0) /* normal writeback write allocate outer shared read write */
- #else
- .set Memory, 0x405 | (3 << 8) | (0x0) /* normal writeback write allocate inner shared read write */
- #endif
- .set Device, 0x409 | (1 << 53)| (1 << 54) |(0x0) /* strongly ordered read write non executable*/
- .section .mmu_tbl0,"a"
-
-MMUTableL0:
-
-.set SECT, MMUTableL1 /* 0x0000_0000 - 0x7F_FFFF_FFFF */
-.8byte SECT + 0x3
-
-.rept 0x1f
-.set SECT, SECT + 0x1000 /* 0x80_0000_0000 - 0xFFF_FFFF_FFFF */
-.8byte SECT + 0x3
-.endr
-
-
- .section .mmu_tbl1,"a"
-
-MMUTableL1:
-
-.set SECT, MMUTableL2 /* 0x0000_0000 - 0x3FFF_FFFF */
-.8byte SECT + 0x3 /* 1GB DDR */
-
-.rept 0x4 /* 0x4000_0000 - 0x1_3FFF_FFFF */
-.set SECT, SECT + 0x1000 /*1GB DDR, 512MB LPD_AFI_FS, 448MB FPD_AFI_0, 512MB QSPI,
- 256MB PCIe region 0, PMC 128MB, GIC 1 MB, reserved 47MB,
- 2GB other devices and memory, 512 MB PMC */
-.8byte SECT + 0x3
-.endr
-
-.set SECT,0x140000000
-
-.rept 0x3 /* 0x1_4000_0000 - 0x1_FFFF_FFFF */
-.8byte SECT + reserved /* 3GB Reserved */
-.set SECT, SECT + 0x40000000
-.endr
-
-.rept 0x4 /* 0x2_0000_0000 - 0x2_FFFF_FFFF */
-.8byte SECT + Device /* 4GB ME Array 0-3*/
-.set SECT, SECT + 0x40000000
-.endr
-
-.rept 0x4 /* 0x3_0000_0000 - 0x3_FFFF_FFFF */
-.8byte SECT + reserved /* 4GB Reserved */
-.set SECT, SECT + 0x40000000
-.endr
-
-.rept 0x10 /* 0x4_0000_0000 - 0x7_FFFF_FFFF */
-.8byte SECT + Device /* 8GB PL - via PS, 8GB PCIe region1 */
-.set SECT, SECT + 0x40000000
-.endr
-
-.set UNDEF_START, 0
-#ifdef XPAR_AXI_NOC_DDR_LOW_1_BASEADDR
-.set DDR_1_START, XPAR_AXI_NOC_DDR_LOW_1_BASEADDR
-.set DDR_1_END, XPAR_AXI_NOC_DDR_LOW_1_HIGHADDR
-
-.if DDR_1_START > DDR_LOW_1_REGION_START_ADDR
-.set UNDEF_START, (DDR_1_START - DDR_LOW_1_REGION_START_ADDR)
-.set UNDEF_START, (UNDEF_START)/0x40000000
-.endif
-
-.set DDR_1_SIZE, (DDR_1_END - DDR_1_START)+1
-.if DDR_1_SIZE > 0x800000000
-/* If DDR size is larger than 32GB, truncate to 32GB */
-.set DDR_1_REG, 0x20
-.else
-.set DDR_1_REG, DDR_1_SIZE/0x40000000
-.endif
-#else
-.set DDR_1_REG, 0
-#warning "There's no DDR_1 in the HW design. MMU translation table marks 32 GB DDR address space as undefined"
-#endif
-
-.set UNDEF_1_REG, (0x20 - DDR_1_REG - UNDEF_START)
-
-.rept UNDEF_START /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-
-.rept DDR_1_REG /* DDR based on size in hdf*/
-.8byte SECT + Memory
-.set SECT, SECT+0x40000000
-.endr
-
-.rept UNDEF_1_REG /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-.rept 0xC0 /* 0x10_0000_0000 - 0x3F_FFFF_FFFF */
-.8byte SECT + reserved /* 192GB Reserved */
-.set SECT, SECT + 0x40000000
-.endr
-
-.rept 0x100 /* 0x40_0000_0000 - 0x7F_FFFF_FFFF */
-.8byte SECT + Device /* 256GB HBM 0-3*/
-.set SECT, SECT + 0x40000000
-.endr
-
-.rept 0x100 /* 0x80_0000_0000 - 0xBF_FFFF_FFFF */
-.8byte SECT + Device /* 256GB PCIe 2 */
-.set SECT, SECT + 0x40000000
-.endr
-
-.set UNDEF_START, 0
-#ifdef XPAR_AXI_NOC_DDR_LOW_2_BASEADDR
-.set DDR_2_START, XPAR_AXI_NOC_DDR_LOW_2_BASEADDR
-.set DDR_2_END, XPAR_AXI_NOC_DDR_LOW_2_HIGHADDR
-
-.if DDR_2_START > DDR_LOW_2_REGION_START_ADDR
-.set UNDEF_START, (DDR_2_START - DDR_LOW_2_REGION_START_ADDR)
-.set UNDEF_START, (UNDEF_START)/0x40000000
-.endif
-
-.set DDR_2_SIZE, (DDR_2_END - DDR_2_START)+1
-.if DDR_2_SIZE > 0x4000000000
-/* If DDR size is larger than 256 GB, truncate to 256GB */
-.set DDR_2_REG, 0x100
-.else
-.set DDR_2_REG, DDR_2_SIZE/0x40000000
-.endif
-#else
-.set DDR_2_REG, 0
-#warning "There's no DDR_LOW_2 in the HW design. MMU translation table marks 256 GB DDR address space as undefined"
-#endif
-
-.set UNDEF_2_REG, (0x100 - DDR_2_REG - UNDEF_START)
-
-.rept UNDEF_START /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-
-.rept DDR_2_REG /* DDR based on size in hdf 0xC0_0000_0000 - 0xFF_FFFF_FFFF */
-.8byte SECT + Memory /* Maximum DDR region size - 256GB */
-.set SECT, SECT + 0x40000000
-.endr
-
-.rept UNDEF_2_REG /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-
-.set UNDEF_START, 0
-#ifdef XPAR_AXI_NOC_DDR_LOW_3_BASEADDR
-.set DDR_3_START, XPAR_AXI_NOC_DDR_LOW_3_BASEADDR
-.set DDR_3_END, XPAR_AXI_NOC_DDR_LOW_3_HIGHADDR
-
-.if DDR_3_START > DDR_LOW_3_REGION_START_ADDR
-.set UNDEF_START, (DDR_3_START - DDR_LOW_3_REGION_START_ADDR)
-.set UNDEF_START, (UNDEF_START)/0x40000000
-.endif
-
-.set DDR_3_SIZE, (DDR_3_END - DDR_3_START)+1
-.if DDR_3_SIZE > 0xB780000000
-/* If DDR size is larger than 734 GB, truncate to 734GB */
-.set DDR_3_REG, 0x2de
-.else
-.set DDR_3_REG, DDR_3_SIZE/0x40000000
-.endif
-#else
-.set DDR_3_REG, 0
-#warning "There's no DDR_LOW_3 in the HW design. MMU translation table marks 734 GB DDR address space as undefined"
-#endif
-
-.set UNDEF_3_REG, (0x2de - DDR_3_REG - UNDEF_START)
-
-.rept UNDEF_START /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-
-.rept DDR_3_REG /* DDR based on size in hdf 0x100_0000_0000 - 0x1B7_7FFF_FFFF */
-.8byte SECT + Memory /* Maximum DDR region size - 734GB DDR */
-.set SECT, SECT + 0x40000000
-.endr
-
-.rept UNDEF_3_REG /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-
-.rept 0x122 /* 0x1B7_8000_0000 - 0x1FF_FFFF_FFFF */
-.8byte SECT + reserved /* 290GB reserved */
-.set SECT, SECT + 0x40000000
-.endr
-
-.rept 0x800 /* 0x200_0000_0000 - 0x3FF_FFFF_FFFF */
-.8byte SECT + Device /* 2TB PL- via NoC */
-.set SECT, SECT + 0x40000000
-.endr
-
-.rept 0x400 /* 0x400_0000_0000 - 0x4FF_FFFF_FFFF */
-.8byte SECT + Device /* 1TB PL- via PS */
-.set SECT, SECT + 0x40000000
-.endr
-
-.set UNDEF_START, 0
-#ifdef XPAR_AXI_NOC_DDR_CH_1_BASEADDR
-.set DDR_CH_1_START, XPAR_AXI_NOC_DDR_CH_1_BASEADDR
-.set DDR_CH_1_END, XPAR_AXI_NOC_DDR_CH_1_HIGHADDR
-
-.if DDR_CH_1_START > DDR_CH_1_REGION_START_ADDR
-.set UNDEF_START, (DDR_CH_1_START - DDR_CH_1_REGION_START_ADDR)
-.set UNDEF_START, (UNDEF_START)/0x40000000
-.endif
-
-.set DDR_CH_1_SIZE, (DDR_CH_1_END - DDR_CH_1_START)+1
-.if DDR_CH_1_SIZE > 0x010000000000
-/* If DDR size is larger than 1TB, truncate to 1 TB */
-.set DDR_CH_1_REG, 0x400 /* 0x500_0000_0000 - 0x5FF_FFFF_FFFF */
-.else
-.set DDR_CH_1_REG, DDR_CH_1_SIZE/0x40000000
-.endif
-#else
-.set DDR_CH_1_REG, 0
-#warning "There's no DDR_CH_1 in the HW design. MMU translation table marks 1 TB DDR address space as undefined"
-#endif
-
-.set UNDEF_CH_1_REG, (0x400 - DDR_CH_1_REG - UNDEF_START)
-
-.rept UNDEF_START /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-
-.rept DDR_CH_1_REG /* DDR based on size in hdf, Max size 1 TB*/
-.8byte SECT + Memory
-.set SECT, SECT+0x40000000
-.endr
-
-.rept UNDEF_CH_1_REG /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-
-.set UNDEF_START, 0
-#ifdef XPAR_AXI_NOC_DDR_CH_2_BASEADDR
-.set DDR_CH_2_START, XPAR_AXI_NOC_DDR_CH_2_BASEADDR
-.set DDR_CH_2_END, XPAR_AXI_NOC_DDR_CH_2_HIGHADDR
-
-.if DDR_CH_2_START > DDR_CH_2_REGION_START_ADDR
-.set UNDEF_START, (DDR_CH_2_START - DDR_CH_2_REGION_START_ADDR)
-.set UNDEF_START, (UNDEF_START)/0x40000000
-.endif
-
-.set DDR_CH_2_SIZE, (DDR_CH_2_END - DDR_CH_2_START)+1
-.if DDR_CH_2_SIZE > 0x010000000000
-/* If DDR_CH_2 size is larger than 1TB, truncate to 1 TB */
-.set DDR_CH_2_REG, 0x400 /* 0x600_0000_0000 - 0x6FF_FFFF_FFFF */
-.else
-.set DDR_CH_2_REG, DDR_CH_2_SIZE/0x40000000
-.endif
-#else
-.set DDR_CH_2_REG, 0
-#warning "There's no DDR_CH_2 in the HW design. MMU translation table marks 1 TB DDR address space as undefined"
-#endif
-
-.set UNDEF_CH_2_REG, (0x400 - DDR_CH_2_REG - UNDEF_START)
-
-.rept UNDEF_START /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-
-.rept DDR_CH_2_REG /* DDR based on size in hdf, Max size 1 TB*/
-.8byte SECT + Memory
-.set SECT, SECT+0x40000000
-.endr
-
-.rept UNDEF_CH_2_REG /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-
-.set UNDEF_START, 0
-#ifdef XPAR_AXI_NOC_DDR_CH_3_BASEADDR
-.set DDR_CH_3_START, XPAR_AXI_NOC_DDR_CH_3_BASEADDR
-.set DDR_CH_3_END, XPAR_AXI_NOC_DDR_CH_3_HIGHADDR
-
-.if DDR_CH_3_START > DDR_CH_3_REGION_START_ADDR
-.set UNDEF_START, (DDR_CH_3_START - DDR_CH_3_REGION_START_ADDR)
-.set UNDEF_START, (UNDEF_START)/0x40000000
-.endif
-
-.set DDR_CH_3_SIZE, (DDR_CH_3_END - DDR_CH_3_START)+1
-.if DDR_CH_3_SIZE > 0x010000000000
-/* If DDR_CH_3 size is larger than 1TB, truncate to 1 TB */
-.set DDR_CH_3_REG, 0x400 /* 0x700_0000_0000 - 0x7FF_FFFF_FFFF */
-.else
-.set DDR_CH_3_REG, DDR_CH_3_SIZE/0x40000000
-.endif
-#else
-.set DDR_CH_3_REG, 0
-#warning "There's no DDR_CH_3 in the HW design. MMU translation table marks 1 TB DDR address space as undefined"
-#endif
-
-.set UNDEF_CH_3_REG, (0x400 - DDR_CH_3_REG - UNDEF_START)
-
-.rept UNDEF_START /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-
-.rept DDR_CH_3_REG /* DDR based on size in hdf, Max size 1 TB*/
-.8byte SECT + Memory
-.set SECT, SECT+0x40000000
-.endr
-
-.rept UNDEF_CH_3_REG /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x40000000
-.endr
-
-
-.rept 0x2000 /* 0x800_0000_0000 - 0xFFF_FFFF_FFFF */
-.8byte SECT + Device /* 8TB PL- via NoC*/
-.set SECT, SECT + 0x40000000
-.endr
-
-.section .mmu_tbl2,"a"
-
-MMUTableL2:
-
-.set SECT, 0
-
-.set UNDEF_START, 0
-#ifdef XPAR_AXI_NOC_DDR_LOW_0_BASEADDR
-.set DDR_0_START, XPAR_AXI_NOC_DDR_LOW_0_BASEADDR
-.set DDR_0_END, XPAR_AXI_NOC_DDR_LOW_0_HIGHADDR
-
-.if DDR_0_START > DDR_LOW_0_REGION_START_ADDR
-.set UNDEF_START, (DDR_0_START - DDR_LOW_0_REGION_START_ADDR)
-.set UNDEF_START, (UNDEF_START)/0x200000
-.endif
-
-.set DDR_0_SIZE, (DDR_0_END - DDR_0_START)+1
-.if DDR_0_SIZE > 0x80000000
-/* If DDR size is larger than 2GB, truncate to 2GB */
-.set DDR_0_REG, 0x400
-.else
-.set DDR_0_REG, DDR_0_SIZE/0x200000
-.endif
-#else
-.set DDR_0_REG, 0
-#warning "There's no DDR_0 in the HW design. MMU translation table marks 2 GB DDR address space as undefined"
-#endif
-
-.set UNDEF_0_REG, (0x400 - DDR_0_REG - UNDEF_START)
-
-.rept UNDEF_START /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x200000
-.endr
-
-.rept DDR_0_REG /* DDR based on size in hdf*/
-.8byte SECT + Memory
-.set SECT, SECT+0x200000
-.endr
-
-.rept UNDEF_0_REG /* reserved for region where ddr is absent */
-.8byte SECT + reserved
-.set SECT, SECT+0x200000
-.endr
-
-
-.rept 0x0100 /* 0x8000_0000 - 0xBFFF_FFFF */
-.8byte SECT + Device /* 512MB LPD AFI */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x020 /* 0xA000_0000 - 0xA3FF_FFFF */
-.8byte SECT + reserved /* 64MB reserved*/
-.set SECT, SECT+0x200000
-.endr
-
-
-.rept 0x60 /* 0xA400_0000 - 0xAFFF_FFFF */
-.8byte SECT + Device /* 192MB FPD AFI 0 */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x80 /* 0xB000_0000 - 0xBFFF_FFFF */
-.8byte SECT + Device /* 192MB FPD AFI 1 */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x100 /* 0xC000_0000 - 0xDFFF_FFFF */
-.8byte SECT + Device /* 512MB QSPI */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x080 /* 0xE000_0000 - 0xEFFF_FFFF */
-.8byte SECT + Device /* 256MB lower PCIe */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x040 /* 0xF000_0000 - 0xF7FF_FFFF */
-.8byte SECT + Device /* 128MB PMC */
-.set SECT, SECT+0x200000
-.endr
-
-.rept 0x08 /* 0xF800_0000 - 0xF8FF_FFFF */
-.8byte SECT + Device /* 16MB coresight */
-.set SECT, SECT+0x200000
-.endr
-
-/* 1MB GIC is marked for 2MB region as the minimum block size in
- translation table is 2MB and adjacent 47MB reserved region is
- converted to 46MB */
-.8byte SECT + Device /* 0xF910_0000 - 0xF90F_FFFF */
-
-/* Reserved 46MB 0xF91FFFFF - 0xFBFFFFFF*/
-.rept 0x17 /* 0xF91F_FFFF - 0xFBFF_FFFF */
-.set SECT, SECT+0x200000
-.8byte SECT + reserved /* 46MB reserved */
-.endr
-
-.rept 0x1F /* 0xFC00_0000 - 0xFFDF_FFFF */
-.set SECT, SECT+0x200000
-.8byte SECT + Device /* 16MB CPM,16MB FPS, 30MB LPS slaves */
-.endr
-
-.set SECT, SECT+0x200000 /* 0xFFE0_0000 - 0xFFFF_FFFF*/
-.8byte SECT + Memory /*2MB OCM/TCM*/
-
-.rept 0x100 /* 0x1_0000_0000 - 0x1_1FFF_FFFF */
-.set SECT, SECT+0x200000
-.8byte SECT + Device /* 512MB PMC 0-3 */
-.endr
-
-.rept 0x100 /* 0x1_2000_0000 - 0x1_3FFF_FFFF */
-.set SECT, SECT+0x200000
-.8byte SECT + reserved /* 512MB reserved */
-.endr
-.end
-/**
-* @} End of "addtogroup a53_64_boot_code".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c0/2034a6585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c0/2034a6585243001d18b399c1eb9b3628
deleted file mode 100644
index 146017b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c0/2034a6585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,17 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: MIT
-*
-******************************************************************************/
-#include "xil_types.h"
-
-/* Stub for iserror() function */
-__attribute__((weak)) s32 _sys_iserror(s32 status)
-{
- if (status < 0) {
- return 1;
- }
-
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c0/207460545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c0/207460545243001d18b399c1eb9b3628
deleted file mode 100644
index de98c61..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c0/207460545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,345 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xscutimer.h
-* @addtogroup scutimer_v2_3
-* @{
-* @details
-*
-* The timer driver supports the Cortex A9 private timer.
-*
-* The timer driver supports the following features:
-* - Normal mode and Auto reload mode
-* - Interrupts (Interrupt handler is not provided in this driver. Application
-* has to register it's own handler)
-*
-* Initialization and Configuration
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate with the Timer.
-*
-* XScuTimer_CfgInitialize() API is used to initialize the Timer. The
-* user needs to first call the XScuTimer_LookupConfig() API which returns
-* the Configuration structure pointer which is passed as a parameter to
-* the XScuTimer_CfgInitialize() API.
-*
-* Interrupts
-*
-* The Timer hardware supports interrupts.
-*
-* This driver does not provide a Interrupt Service Routine (ISR) for the device.
-* It is the responsibility of the application to provide one if needed. Refer to
-* the interrupt example provided with this driver for details on using the
-* Timer in interrupt mode.
-*
-* Virtual Memory
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-* Threads
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* Asserts
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* Building the driver
-*
-* The XScuTimer driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-*
-*
-* NOTE:
-* The timer is not a part of the snoop control unit as indicated by the
-* prefix "scu" in the name of the driver.
-* It is an independent module in APU.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm 03/10/10 First release
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 2.3 mus 08/31/20 Updated makefile to support parallel make and
-* incremental builds, it would help to reduce compilation
-* time.
-*
-*
-******************************************************************************/
-#ifndef XSCUTIMER_H /* prevent circular inclusions */
-#define XSCUTIMER_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xscutimer_hw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddr; /**< Base address of the device */
-} XScuTimer_Config;
-
-/**
- * The XScuTimer driver instance data. The user is required to allocate a
- * variable of this type for every timer device in the system.
- * A pointer to a variable of this type is then passed to the driver API
- * functions.
- */
-typedef struct {
- XScuTimer_Config Config; /**< Hardware Configuration */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStarted; /**< Device timer is running */
-} XScuTimer;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Check if the timer has expired.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return
-* - TRUE if the timer has expired.
-* - FALSE if the timer has not expired.
-*
-* @note C-style signature:
-* int XScuTimer_IsExpired(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_IsExpired(InstancePtr) \
- ((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_ISR_OFFSET) & \
- XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
- XSCUTIMER_ISR_EVENT_FLAG_MASK)
-
-/****************************************************************************/
-/**
-*
-* Re-start the timer. This macro will read the timer load register
-* and writes the same value to load register to update the counter register.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_RestartTimer(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_RestartTimer(InstancePtr) \
- XScuTimer_LoadTimer((InstancePtr), \
- XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_LOAD_OFFSET))
-
-/****************************************************************************/
-/**
-*
-* Write to the timer load register. This will also update the
-* timer counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-* @param Value is the count to be loaded in to the load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_LoadTimer(InstancePtr, Value) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_LOAD_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer counter register value. It can be called at any
-* time.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return Contents of the timer counter register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_GetCounterValue(InstancePtr) \
- XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_COUNTER_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Enable auto-reload mode.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_EnableAutoReload(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) | \
- XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
-
-/****************************************************************************/
-/**
-*
-* Disable auto-reload mode.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_DisableAutoReload(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) & \
- ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Enable the Timer interrupt.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_EnableInterrupt(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) | \
- XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
-
-/****************************************************************************/
-/**
-*
-* Disable the Timer interrupt.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_DisableInterrupt(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) & \
- ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
-
-/*****************************************************************************/
-/**
-*
-* This function reads the interrupt status.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_GetInterruptStatus(InstancePtr) \
- XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_ISR_OFFSET)
-
-/*****************************************************************************/
-/**
-*
-* This function clears the interrupt status.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_ClearInterruptStatus(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Lookup configuration in xscutimer_sinit.c
- */
-XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId);
-
-/*
- * Selftest function in xscutimer_selftest.c
- */
-s32 XScuTimer_SelfTest(XScuTimer *InstancePtr);
-
-/*
- * Interface functions in xscutimer.c
- */
-s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
- XScuTimer_Config *ConfigPtr, u32 EffectiveAddress);
-void XScuTimer_Start(XScuTimer *InstancePtr);
-void XScuTimer_Stop(XScuTimer *InstancePtr);
-void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue);
-u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c0/3091c1525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c0/3091c1525243001d18b399c1eb9b3628
deleted file mode 100644
index 5007212..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c0/3091c1525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,111 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2017 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_sleeptimer.h
-*
-* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs.
-* For sleep related functions that can be used across all Xilinx supported
-* processors, please use xil_sleeptimer.h.
-*
-*
-*
-* MODIFICATION HISTORY :
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 6.6 srm 10/18/17 First Release.
-* 7.0 mus 01/07/19 Add cpp extern macro
-*
-*
-*****************************************************************************/
-
-/**
- *@cond nocomments
- */
-#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */
-#define XIL_SLEEPTIMER_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**************************** Include Files ********************************/
-
-#include "xil_io.h"
-#include "xparameters.h"
-#include "bspconfig.h"
-
-/************************** Constant Definitions *****************************/
-
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
-#define XSLEEP_TIMER_REG_SHIFT 32U
-#define XSleep_ReadCounterVal Xil_In32
-#define XCntrVal u32
-#else
-#define XSLEEP_TIMER_REG_SHIFT 16U
-#define XSleep_ReadCounterVal Xil_In16
-#define XCntrVal u16
-#endif
-
-#if defined(ARMR5) || (defined (__aarch64__) && EL3==1) || defined (ARMA53_32)
-#if defined (versal)
-#define CRL_TTC_RST 0xFF5E0344U
-#define CRL_TTC_BASE_RST_MASK 0x1U
-#else
-#define RST_LPD_IOU2 0xFF5E0238U
-#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U
-#endif
-#endif
-
-#if defined (SLEEP_TIMER_BASEADDR)
-/** @name Register Map
-*
-* Register offsets from the base address of the TTC device
-*
-* @{
-*/
- #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U
- /**< Clock Control Register */
- #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU
- /**< Counter Control Register*/
- #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U
- /**< Current Counter Value */
-/* @} */
-/** @name Clock Control Register
-* Clock Control Register definitions of TTC
-* @{
-*/
- #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U
- /**< Prescale enable */
-/* @} */
-/** @name Counter Control Register
-* Counter Control Register definitions of TTC
-* @{
-*/
-#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U
- /**< Disable the counter */
-#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U
- /**< Reset counter */
-/* @} */
-
-/**************************** Type Definitions *******************************/
-/**
- *@endcond
- */
-/************************** Function Prototypes ******************************/
-
-void Xil_SleepTTCCommon(u32 delay, u64 frequency);
-void XTime_StartTTCTimer();
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_SLEEPTIMER_H */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c0/6038fb555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c0/6038fb555243001d18b399c1eb9b3628
deleted file mode 100644
index 878d575..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c0/6038fb555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,261 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_misc_psreset_api.h
-*
-* This file contains the various register definitions and function prototypes for
-* implementing the reset functionality of zynq ps devices
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00b kpc 03/07/13 First release.
-*
-*
-* This routine provides an internal self test of the MicroBlaze processor. The
-* register file and all integer execution units are tested. Long instructions
-* are also included if 64-bit mode is enabled. Currently FPU, MMU, BTC, data
-* and instruction caches, and GET/PUT instructions are not covered.
-*
-* The routine is not reentrant, and disables interrupts and exceptions during
-* execution. This can result in increased interrupt latency.
-*
-* Call this routine regularly from a timer interrupt.
-*
-* When called from C code the routine should be declared as:
-* extern int microblaze_selftest();
-*
-* @param None.
-*
-* @return
-* - 0 if self test was successful
-* - Error code if self test failed:
-* Bit 0: Register file test failed
-* Bit 1: ALU test failed
-* Bit 2: Shift unit test failed
-* Bit 3: Load-store test failed
-* Bit 4: Branch instruction test failed
-* Bit 5: Barrel shifter test failed
-* Bit 6: Multiplier test failed
-* Bit 7: Integer divide test failed
-* Bit 8: Pattern compare test failed
-* Bit 9: MSR instruction test failed
-* Bit 10: Reorder instruction test failed
-*
-* @note
-* This routine assumes that the processor is in privileged mode when it is
-* called, if the MMU is enabled.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sv 01/18/10 First Release
-* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
-* passed to API's. CR# 822636
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
-* 3.1 aru 07/13/18 Ressolved doxygen reported warnings. CR# 1006331.
-* 3.4 aru 08/09/18 Ressolved cppcheck warnings.
-* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
-* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
-* in safety mode and modified the code such as
-* Use of mixed mode arithmetic,Declared the pointer param
-* as Pointer to const,Casting operation to a pointer,
-* Literal value requires a U suffix.
-* 3.5 sne 03/14/19 Added Versal support.
-* 3.5 sne 03/20/19 Fixed multiple interrupts problem CR#1024556.
-* 3.6 sne 06/12/19 Fixed IAR compiler warning.
-* 3.6 sne 08/14/19 Added interrupt handler support on versal.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xgpiops.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-/****************************************************************************/
-/**
-*
-* This function enables the interrupts for the specified pins in the specified
-* bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param Mask is the bit mask of the pins for which interrupts are to
-* be enabled. Bit positions of 1 will be enabled. Bit positions
-* of 0 will keep the previous setting.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertVoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTEN_OFFSET, Mask);
-}
-
-/****************************************************************************/
-/**
-*
-* This function enables the interrupt for the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number for which the interrupt is to be enabled.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin)
-{
- u8 Bank;
- u8 PinNumber;
- u32 IntrReg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
-
- IntrReg = ((u32)1 << (u32)PinNumber);
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTEN_OFFSET, IntrReg);
-}
-
-/****************************************************************************/
-/**
-*
-* This function disables the interrupts for the specified pins in the specified
-* bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param Mask is the bit mask of the pins for which interrupts are
-* to be disabled. Bit positions of 1 will be disabled. Bit
-* positions of 0 will keep the previous setting.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertVoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTDIS_OFFSET, Mask);
-}
-
-/****************************************************************************/
-/**
-*
-* This function disables the interrupts for the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number for which the interrupt is to be disabled.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin)
-{
- u8 Bank;
- u8 PinNumber;
- u32 IntrReg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
-
- IntrReg = ((u32)1 << (u32)PinNumber);
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTDIS_OFFSET, IntrReg);
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the interrupt enable status for a bank.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-*
-* @return Enabled interrupt(s) in a 32-bit format. Bit positions with 1
-* indicate that the interrupt for that pin is enabled, bit
-* positions with 0 indicate that the interrupt for that pin is
-* disabled.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank)
-{
- u32 IntrMask;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertNonvoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- IntrMask = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTMASK_OFFSET);
- return (~IntrMask);
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns whether interrupts are enabled for the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number for which the interrupt enable status
-* is to be known.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*
-* @return
-* - TRUE if the interrupt is enabled.
-* - FALSE if the interrupt is disabled.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin)
-{
- u8 Bank;
- u8 PinNumber;
- u32 IntrReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
-
- IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTMASK_OFFSET);
-
- return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? (u32)FALSE : (u32)TRUE);
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns interrupt status read from Interrupt Status Register.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-*
-* @return The value read from Interrupt Status Register.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertNonvoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertNonvoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTSTS_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns interrupt enable status of the specified pin.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number for which the interrupt enable status
-* is to be known.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*
-* @return
-* - TRUE if the interrupt has occurred.
-* - FALSE if the interrupt has not occurred.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin)
-{
- u8 Bank;
- u8 PinNumber;
- u32 IntrReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
-
- IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTSTS_OFFSET);
-
- return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? (u32)TRUE : (u32)FALSE);
-}
-
-/****************************************************************************/
-/**
-*
-* This function clears pending interrupt(s) with the provided mask. This
-* function should be called after the software has serviced the interrupts
-* that are pending.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param Mask is the mask of the interrupts to be cleared. Bit positions
-* of 1 will be cleared. Bit positions of 0 will not change the
-* previous interrupt status.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertVoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- /* Clear the currently pending interrupts. */
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTSTS_OFFSET, Mask);
-}
-
-/****************************************************************************/
-/**
-*
-* This function clears the specified pending interrupt. This function should be
-* called after the software has serviced the interrupts that are pending.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param Pin is the pin number for which the interrupt status is to be
-* cleared. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin)
-{
- u8 Bank;
- u8 PinNumber;
- u32 IntrReg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
-
- /* Clear the specified pending interrupts. */
- IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTSTS_OFFSET);
-
- IntrReg &= ((u32)1 << PinNumber);
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTSTS_OFFSET, IntrReg);
-}
-
-/****************************************************************************/
-/**
-*
-* This function is used for setting the Interrupt Type, Interrupt Polarity and
-* Interrupt On Any for the specified GPIO Bank pins.
-*
-* @param InstancePtr is a pointer to an XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param IntrType is the 32 bit mask of the interrupt type.
-* 0 means Level Sensitive and 1 means Edge Sensitive.
-* @param IntrPolarity is the 32 bit mask of the interrupt polarity.
-* 0 means Active Low or Falling Edge and 1 means Active High or
-* Rising Edge.
-* @param IntrOnAny is the 32 bit mask of the interrupt trigger for
-* edge triggered interrupts. 0 means trigger on single edge using
-* the configured interrupt polarity and 1 means trigger on both
-* edges.
-*
-* @return None.
-*
-* @note This function is used for setting the interrupt related
-* properties of all the pins in the specified bank. The previous
-* state of the pins is not maintained.
-* To change the Interrupt properties of a single GPIO pin, use the
-* function XGpioPs_SetPinIntrType().
-*
-*****************************************************************************/
-void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
- u32 IntrPolarity, u32 IntrOnAny)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertVoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTTYPE_OFFSET, IntrType);
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTPOL_OFFSET, IntrPolarity);
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTANY_OFFSET, IntrOnAny);
-}
-
-/****************************************************************************/
-/**
-*
-* This function is used for getting the Interrupt Type, Interrupt Polarity and
-* Interrupt On Any for the specified GPIO Bank pins.
-*
-* @param InstancePtr is a pointer to an XGpioPs instance.
-* @param Bank is the bank number of the GPIO to operate on.
-* Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
-* @param IntrType returns the 32 bit mask of the interrupt type.
-* 0 means Level Sensitive and 1 means Edge Sensitive.
-* @param IntrPolarity returns the 32 bit mask of the interrupt
-* polarity. 0 means Active Low or Falling Edge and 1 means
-* Active High or Rising Edge.
-* @param IntrOnAny returns the 32 bit mask of the interrupt trigger for
-* edge triggered interrupts. 0 means trigger on single edge using
-* the configured interrupt polarity and 1 means trigger on both
-* edges.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
- u32 *IntrPolarity, u32 *IntrOnAny)
-
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- Xil_AssertVoid(Bank != XGPIOPS_TWO);
- } else {
- Xil_AssertVoid((Bank !=XGPIOPS_ONE) && (Bank !=XGPIOPS_TWO));
- }
-#endif
-
- *IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTTYPE_OFFSET);
-
- *IntrPolarity = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTPOL_OFFSET);
-
- *IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTANY_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* This function is used for setting the IRQ Type of a single GPIO pin.
-*
-* @param InstancePtr is a pointer to an XGpioPs instance.
-* @param Pin is the pin number whose IRQ type is to be set.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-* @param IrqType is the IRQ type for GPIO Pin. Use XGPIOPS_IRQ_TYPE_*
-* defined in xgpiops.h to specify the IRQ type.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType)
-{
- u32 IntrTypeReg;
- u32 IntrPolReg;
- u32 IntrOnAnyReg;
- u8 Bank;
- u8 PinNumber;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
- Xil_AssertVoid(IrqType <= XGPIOPS_IRQ_TYPE_LEVEL_LOW);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
-
- IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTTYPE_OFFSET);
-
- IntrPolReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTPOL_OFFSET);
-
- IntrOnAnyReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTANY_OFFSET);
-
- switch (IrqType) {
- case XGPIOPS_IRQ_TYPE_EDGE_RISING:
- IntrTypeReg |= ((u32)1 << (u32)PinNumber);
- IntrPolReg |= ((u32)1 << (u32)PinNumber);
- IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
- break;
- case XGPIOPS_IRQ_TYPE_EDGE_FALLING:
- IntrTypeReg |= ((u32)1 << (u32)PinNumber);
- IntrPolReg &= ~((u32)1 << (u32)PinNumber);
- IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
- break;
- case XGPIOPS_IRQ_TYPE_EDGE_BOTH:
- IntrTypeReg |= ((u32)1 << (u32)PinNumber);
- IntrOnAnyReg |= ((u32)1 << (u32)PinNumber);
- break;
- case XGPIOPS_IRQ_TYPE_LEVEL_HIGH:
- IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
- IntrPolReg |= ((u32)1 << (u32)PinNumber);
- break;
- case XGPIOPS_IRQ_TYPE_LEVEL_LOW:
- IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
- IntrPolReg &= ~((u32)1 << (u32)PinNumber);
- break;
- default:
- /**< Default statement is added for MISRA C compliance. */
- break;
- }
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTTYPE_OFFSET, IntrTypeReg);
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTPOL_OFFSET, IntrPolReg);
-
- XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTANY_OFFSET, IntrOnAnyReg);
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the IRQ Type of a given GPIO pin.
-*
-* @param InstancePtr is a pointer to an XGpioPs instance.
-* @param Pin is the pin number whose IRQ type is to be obtained.
-* Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
-*
-* @return None.
-*
-* @note Use XGPIOPS_IRQ_TYPE_* defined in xgpiops.h for the IRQ type
-* returned by this function.
-*
-*****************************************************************************/
-u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin)
-{
- u32 IntrType;
- u32 IntrPol;
- u32 IntrOnAny;
- u8 Bank;
- u8 PinNumber;
- u8 IrqType;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
-
- /* Get the Bank number and Pin number within the bank. */
-#ifdef versal
- XGpioPs_GetBankPin(InstancePtr,(u8)Pin, &Bank, &PinNumber);
-#else
- XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
-#endif
-
- IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTTYPE_OFFSET) & ((u32)1 << PinNumber);
-
- if (IntrType == ((u32)1 << PinNumber)) {
-
- IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTANY_OFFSET) & ((u32)1 << PinNumber);
-
- IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
-
-
- if (IntrOnAny == ((u32)1 << PinNumber)) {
- IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH;
- } else if (IntrPol == ((u32)1 << PinNumber)) {
- IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING;
- } else {
- IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING;
- }
- } else {
-
- IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
- ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
- XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
-
- if (IntrPol == ((u32)1 << PinNumber)) {
- IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH;
- } else {
- IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW;
- }
- }
-
- return IrqType;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets the status callback function. The callback function is
-* called by the XGpioPs_IntrHandler when an interrupt occurs.
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-* @param CallBackRef is the upper layer callback reference passed back
-* when the callback function is invoked.
-* @param FuncPointer is the pointer to the callback function.
-*
-*
-* @return None.
-*
-* @note The handler is called within interrupt context, so it should do
-* its work quickly and queue potentially time-consuming work to a
-* task-level thread.
-*
-******************************************************************************/
-void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
- XGpioPs_Handler FuncPointer)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(FuncPointer != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- InstancePtr->Handler = FuncPointer;
- InstancePtr->CallBackRef = CallBackRef;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function is the interrupt handler for GPIO interrupts.It checks the
-* interrupt status registers of all the banks to determine the actual bank in
-* which an interrupt has been triggered. It then calls the upper layer callback
-* handler set by the function XGpioPs_SetBankHandler(). The callback is called
-* when an interrupt
-*
-* @param InstancePtr is a pointer to the XGpioPs instance.
-*
-* @return None.
-*
-* @note This function does not save and restore the processor context
-* such that the user must provide this processing.
-*
-******************************************************************************/
-void XGpioPs_IntrHandler(const XGpioPs *InstancePtr)
-{
- u8 Bank;
- u32 IntrStatus;
- u32 IntrEnabled;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- for (Bank = 0U; Bank < InstancePtr->MaxBanks; Bank++) {
-#ifdef versal
- if(InstancePtr->PmcGpio == (u32)TRUE) {
- if(Bank == XGPIOPS_TWO) {
- continue;
- }
- } else {
- if((Bank == XGPIOPS_ONE) || (Bank == XGPIOPS_TWO)) {
- continue;
- }
- }
-#endif
- IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank);
- IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,Bank);
- if ((IntrStatus & IntrEnabled) != (u32)0) {
- XGpioPs_IntrClear(InstancePtr, Bank,
- (IntrStatus & IntrEnabled));
- InstancePtr->Handler(InstancePtr->
- CallBackRef, Bank,
- (IntrStatus & IntrEnabled));
- }
- }
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c0/f152c9555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c0/f152c9555243001d18b399c1eb9b3628
deleted file mode 100644
index 1de5c87..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c0/f152c9555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,6 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-void __ARM_argv_veneer(void) {};
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c0/f169da555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c0/f169da555243001d18b399c1eb9b3628
deleted file mode 100644
index 084de81..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c0/f169da555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,24 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#include "xil_types.h"
-#include "xparameters.h"
-
-__weak s32 _sys_write(u32 fh, const u8 *buf, u32 len, s32 mode)
-{
-#ifdef STDOUT_BASEADDRESS
- u32 volatile *uart_base = (u32 *)STDOUT_BASEADDRESS;
- s32 i;
-
- for (i =0; i < len;i++) {
- /* wait if TNFUL */
- while (*(uart_base + 11U) & (1U << 14U)) {
- ;
- }
- *(uart_base + 12U) = buf[i];
- }
-#endif
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c1/60e402575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c1/60e402575243001d18b399c1eb9b3628
deleted file mode 100644
index bb3765d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c1/60e402575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,504 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xuartps.h
-* @addtogroup uartps_v3_11
-* @{
-* @details
-*
-* This driver supports the following features:
-*
-* - Dynamic data format (baud rate, data bits, stop bits, parity)
-* - Polled mode
-* - Interrupt driven mode
-* - Transmit and receive FIFOs (32 byte FIFO depth)
-* - Access to the external modem control lines
-*
-* Initialization & Configuration
-*
-* The XUartPs_Config structure is used by the driver to configure itself.
-* Fields inside this structure are properties of XUartPs based on its hardware
-* build.
-*
-* To support multiple runtime loading and initialization strategies employed
-* by various operating systems, the driver instance can be initialized in the
-* following way:
-*
-* - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-* configuration structure provided by the caller. If running in a system
-* with address translation, the parameter EffectiveAddr should be the
-* virtual address.
-*
-* Baud Rate
-*
-* The UART has an internal baud rate generator, which furnishes the baud rate
-* clock for both the receiver and the transmitter. The input clock frequency
-* can be either the master clock or the master clock divided by 8, configured
-* through the mode register.
-*
-* Accompanied with the baud rate divider register, the baud rate is determined
-* by:
-*
-* where bgen is the value of the baud rate generator, and bdiv is the value of
-* baud rate divider.
-*
-* Interrupts
-*
-* The FIFOs are not flushed when the driver is initialized, but a function is
-* provided to allow the user to reset the FIFOs if desired.
-*
-* The driver defaults to no interrupts at initialization such that interrupts
-* must be enabled if desired. An interrupt is generated for one of the
-* following conditions.
-*
-* - A change in the modem signals
-* - Data in the receive FIFO for a configuable time without receiver activity
-* - A parity error
-* - A framing error
-* - An overrun error
-* - Transmit FIFO is full
-* - Transmit FIFO is empty
-* - Receive FIFO is full
-* - Receive FIFO is empty
-* - Data in the receive FIFO equal to the receive threshold
-*
-* The application can control which interrupts are enabled using the
-* XUartPs_SetInterruptMask() function.
-*
-* In order to use interrupts, it is necessary for the user to connect the
-* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
-* system of the application. A separate handler should be provided by the
-* application to communicate with the interrupt system, and conduct
-* application specific interrupt handling. An application registers its own
-* handler through the XUartPs_SetHandler() function.
-*
-* Data Transfer
-*
-* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
-* driver to allow data to be sent and received. They can be used in either
-* polled or interrupt mode.
-*
-* @note
-*
-* The default configuration for the UART after initialization is:
-*
-* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
-* - 8 data bits
-* - 1 stop bit
-* - no parity
-* - FIFO's are enabled with a receive threshold of 8 bytes
-* - The RX timeout is enabled with a timeout of 1 (4 char times)
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00a drg/jz 01/12/10 First Release
-* 1.00a sdm 09/27/11 Fixed compiler warnings and also a bug
-* in XUartPs_SetFlowDelay where the value was not
-* being written to the register.
-* 1.01a sdm 12/20/11 Removed the InputClockHz parameter from the XUartPs
-* instance structure and the driver is updated to use
-* InputClockHz parameter from the XUartPs_Config config
-* structure.
-* Added a parameter to XUartPs_Config structure which
-* specifies whether the user has selected Modem pins
-* to be connected to MIO or FMIO.
-* Added the tcl file to generate the xparameters.h
-* 1.02a sg 05/16/12 Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
-* 1.03a sg 07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
-* with the correct values for CR 666724
-* Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
-* and XUARTPS_IXR_TTRIG.
-* Modified the name of these defines
-* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
-* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
-* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
-* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
-* 1.05a hk 08/22/13 Added API for uart reset and related
-* constant definitions.
-* 2.0 hk 03/07/14 Version number revised.
-* 2.1 hk 04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
-* 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing
-* baud rate. CR# 804281.
-* 3.0 vm 12/09/14 Modified source code according to misrac guideline.
-* Support for Zynq Ultrascale Mp added.
-* 3.1 kvn 04/10/15 Modified code for latest RTL changes. Also added
-* platform variable in driver instance structure.
-* 3.1 adk 14/03/16 Include interrupt examples in the peripheral test when
-* uart is connected to a valid interrupt controller CR#946803.
-* 3.2 rk 07/20/16 Modified the logic for transmission break bit set
-* 3.4 ms 01/23/17 Added xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 3.6 ms 02/16/18 Updates the flow control mode offset value in modem
-* control register.
-* 3.7 aru 08/17/18 Resolved MISRA-C:2012 compliance mandatory violations.
-* 3.9 rna 12/03/19 Modified the XUARTPS_MAX_RATE macro.
-* 3.9 sd 02/06/20 Added clock support
-*
-*
-*
-*****************************************************************************/
-
-#ifndef XUARTPS_H /* prevent circular inclusions */
-#define XUARTPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xuartps_hw.h"
-#include "xplatform_info.h"
-#if defined (XCLOCKING)
-#include "xil_clocking.h"
-#endif
-
-/************************** Constant Definitions ****************************/
-
-/*
- * The following constants indicate the max and min baud rates and these
- * numbers are based only on the testing that has been done. The hardware
- * is capable of other baud rates.
- */
-#define XUARTPS_MAX_RATE 6240000U
-#define XUARTPS_MIN_RATE 110U
-
-#define XUARTPS_DFT_BAUDRATE 115200U /* Default baud rate */
-
-/** @name Configuration options
- * @{
- */
-/**
- * These constants specify the options that may be set or retrieved
- * with the driver, each is a unique bit mask such that multiple options
- * may be specified. These constants indicate the available options
- * in active state.
- *
- */
-
-#define XUARTPS_OPTION_SET_BREAK 0x0080U /**< Starts break transmission */
-#define XUARTPS_OPTION_STOP_BREAK 0x0040U /**< Stops break transmission */
-#define XUARTPS_OPTION_RESET_TMOUT 0x0020U /**< Reset the receive timeout */
-#define XUARTPS_OPTION_RESET_TX 0x0010U /**< Reset the transmitter */
-#define XUARTPS_OPTION_RESET_RX 0x0008U /**< Reset the receiver */
-#define XUARTPS_OPTION_ASSERT_RTS 0x0004U /**< Assert the RTS bit */
-#define XUARTPS_OPTION_ASSERT_DTR 0x0002U /**< Assert the DTR bit */
-#define XUARTPS_OPTION_SET_FCM 0x0001U /**< Turn on flow control mode */
-/*@}*/
-
-
-/** @name Channel Operational Mode
- *
- * The UART can operate in one of four modes: Normal, Local Loopback, Remote
- * Loopback, or automatic echo.
- *
- * @{
- */
-
-#define XUARTPS_OPER_MODE_NORMAL (u8)0x00U /**< Normal Mode */
-#define XUARTPS_OPER_MODE_AUTO_ECHO (u8)0x01U /**< Auto Echo Mode */
-#define XUARTPS_OPER_MODE_LOCAL_LOOP (u8)0x02U /**< Local Loopback Mode */
-#define XUARTPS_OPER_MODE_REMOTE_LOOP (u8)0x03U /**< Remote Loopback Mode */
-
-/* @} */
-
-/** @name Data format values
- *
- * These constants specify the data format that the driver supports.
- * The data format includes the number of data bits, the number of stop
- * bits and parity.
- *
- * @{
- */
-#define XUARTPS_FORMAT_8_BITS 0U /**< 8 data bits */
-#define XUARTPS_FORMAT_7_BITS 2U /**< 7 data bits */
-#define XUARTPS_FORMAT_6_BITS 3U /**< 6 data bits */
-
-#define XUARTPS_FORMAT_NO_PARITY 4U /**< No parity */
-#define XUARTPS_FORMAT_MARK_PARITY 3U /**< Mark parity */
-#define XUARTPS_FORMAT_SPACE_PARITY 2U /**< parity */
-#define XUARTPS_FORMAT_ODD_PARITY 1U /**< Odd parity */
-#define XUARTPS_FORMAT_EVEN_PARITY 0U /**< Even parity */
-
-#define XUARTPS_FORMAT_2_STOP_BIT 2U /**< 2 stop bits */
-#define XUARTPS_FORMAT_1_5_STOP_BIT 1U /**< 1.5 stop bits */
-#define XUARTPS_FORMAT_1_STOP_BIT 0U /**< 1 stop bit */
-/*@}*/
-
-/** @name Callback events
- *
- * These constants specify the handler events that an application can handle
- * using its specific handler function. Note that these constants are not bit
- * mask, so only one event can be passed to an application at a time.
- *
- * @{
- */
-#define XUARTPS_EVENT_RECV_DATA 1U /**< Data receiving done */
-#define XUARTPS_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */
-#define XUARTPS_EVENT_SENT_DATA 3U /**< Data transmission done */
-#define XUARTPS_EVENT_RECV_ERROR 4U /**< A receive error detected */
-#define XUARTPS_EVENT_MODEM 5U /**< Modem status changed */
-#define XUARTPS_EVENT_PARE_FRAME_BRKE 6U /**< A receive parity, frame, break
- * error detected */
-#define XUARTPS_EVENT_RECV_ORERR 7U /**< A receive overrun error detected */
-
-/*@}*/
-
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of device (IPIF) */
- u32 InputClockHz;/**< Input clock frequency */
- s32 ModemPinsConnected; /** Specifies whether modem pins are connected
- * to MIO or FMIO */
-#if defined (XCLOCKING)
- u32 RefClk; /**< Input clock frequency */
-#endif
-} XUartPs_Config;
-
-/* Keep track of state information about a data buffer in the interrupt mode. */
-typedef struct {
- u8 *NextBytePtr;
- u32 RequestedBytes;
- u32 RemainingBytes;
-} XUartPsBuffer;
-
-/**
- * Keep track of data format setting of a device.
- */
-typedef struct {
- u32 BaudRate; /**< In bps, ie 1200 */
- u32 DataBits; /**< Number of data bits */
- u32 Parity; /**< Parity */
- u8 StopBits; /**< Number of stop bits */
-} XUartPsFormat;
-
-/******************************************************************************/
-/**
- * This data type defines a handler that an application defines to communicate
- * with interrupt system to retrieve state information about an application.
- *
- * @param CallBackRef is a callback reference passed in by the upper layer
- * when setting the handler, and is passed back to the upper layer
- * when the handler is called. It is used to find the device driver
- * instance.
- * @param Event contains one of the event constants indicating events that
- * have occurred.
- * @param EventData contains the number of bytes sent or received at the
- * time of the call for send and receive events and contains the
- * modem status for modem events.
- *
- ******************************************************************************/
-typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
- u32 EventData);
-
-/**
- * The XUartPs driver instance data structure. A pointer to an instance data
- * structure is passed around by functions to refer to a specific driver
- * instance.
- */
-typedef struct {
- XUartPs_Config Config; /* Configuration data structure */
- u32 InputClockHz; /* Input clock frequency */
- u32 IsReady; /* Device is initialized and ready */
- u32 BaudRate; /* Current baud rate */
-
- XUartPsBuffer SendBuffer;
- XUartPsBuffer ReceiveBuffer;
-
- XUartPs_Handler Handler;
- void *CallBackRef; /* Callback reference for event handler */
- u32 Platform;
- u8 is_rxbs_error;
-} XUartPs;
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* Get the UART Channel Status Register.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_GetChannelStatus(InstancePtr) \
- Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
-
-/****************************************************************************/
-/**
-* Get the UART Mode Control Register.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XUartPs_GetControl(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_GetModeControl(InstancePtr) \
- Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
-
-/****************************************************************************/
-/**
-* Set the UART Mode Control Register.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
-*
-******************************************************************************/
-#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
- Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
- (u32)(RegisterValue))
-
-/****************************************************************************/
-/**
-* Enable the transmitter and receiver of the UART.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_EnableUart(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_EnableUart(InstancePtr) \
- Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
- ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
- (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
-
-/****************************************************************************/
-/**
-* Disable the transmitter and receiver of the UART.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_DisableUart(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_DisableUart(InstancePtr) \
- Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
- (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
- (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
-
-/****************************************************************************/
-/**
-* Determine if the transmitter FIFO is empty.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-* - TRUE if a byte can be sent
-* - FALSE if the Transmitter Fifo is not empty
-*
-* @note C-Style signature:
-* u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_IsTransmitEmpty(InstancePtr) \
- ((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
- (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
-
-
-/************************** Function Prototypes *****************************/
-
-/* Static lookup function implemented in xuartps_sinit.c */
-XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
-
-/* Interface functions implemented in xuartps.c */
-s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
- XUartPs_Config * Config, u32 EffectiveAddr);
-
-u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
- u32 NumBytes);
-
-u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
- u32 NumBytes);
-
-s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
-
-/* Options functions in xuartps_options.c */
-void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
-
-u16 XUartPs_GetOptions(XUartPs *InstancePtr);
-
-void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
-
-u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
-
-u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
-
-u32 XUartPs_IsSending(XUartPs *InstancePtr);
-
-u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
-
-void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
-
-u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
-
-void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
-
-u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
-
-void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
-
-s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
-
-void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
-
-/* interrupt functions in xuartps_intr.c */
-u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
-
-void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
-
-void XUartPs_InterruptHandler(XUartPs *InstancePtr);
-
-void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
- void *CallBackRef);
-
-/* self-test functions in xuartps_selftest.c */
-s32 XUartPs_SelfTest(XUartPs *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c1/7030e8565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c1/7030e8565243001d18b399c1eb9b3628
deleted file mode 100644
index ba7531d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c1/7030e8565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,143 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2017 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/*****************************************************************************/
-/**
-*
-* @file xil_sleeptimer.c
-*
-* This file provides the common helper routines for the sleep API's
-*
-*
-* MODIFICATION HISTORY :
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 6.6 srm 10/18/17 First Release.
-* 6.6 srm 04/20/18 Fixed compilation warning in Xil_SleepTTCCommon API
-* 7.0 mus 03/27/19 Updated XTime_StartTTCTimer to skip IOU slcr address
-* space access, if processor is nonsecure and IOU slcr
-* address space is secure. CR#1015725.
-*
-*
-*****************************************************************************/
-
-/**************************** Include Files ********************************/
-
-#include "xil_io.h"
-#include "xil_sleeptimer.h"
-#include "xtime_l.h"
-
-/**************************** Constant Definitions *************************/
-
-
-/* Function definitions are applicable only when TTC3 is present*/
-#if defined (SLEEP_TIMER_BASEADDR)
-/****************************************************************************/
-/**
-*
-* This is a helper function used by sleep/usleep APIs to
-* have delay in sec/usec
-*
-* @param delay - delay time in seconds/micro seconds
-*
-* @param frequency - Number of counts per second/micro second
-*
-* @return none
-*
-* @note none
-*
-*****************************************************************************/
-void Xil_SleepTTCCommon(u32 delay, u64 frequency)
-{
- u64 tEnd = 0U;
- u64 tCur = 0U;
- XCntrVal TimeHighVal = 0U;
- XCntrVal TimeLowVal1 = 0U;
- XCntrVal TimeLowVal2 = 0U;
-
- TimeLowVal1 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET);
- tEnd = (u64)TimeLowVal1 + ((u64)(delay) * frequency);
- do
- {
- TimeLowVal2 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET);
- if (TimeLowVal2 < TimeLowVal1) {
- TimeHighVal++;
- }
- TimeLowVal1 = TimeLowVal2;
- tCur = (((u64) TimeHighVal) << XSLEEP_TIMER_REG_SHIFT) |
- (u64)TimeLowVal2;
- }while (tCur < tEnd);
-}
-
-
-/*****************************************************************************/
-/**
-*
-* This API starts the Triple Timer Counter
-*
-* @param none
-*
-* @return none
-*
-* @note none
-*
-*****************************************************************************/
-void XTime_StartTTCTimer()
-{
- u32 TimerPrescalar;
- u32 TimerCntrl;
-
-#if (defined (__aarch64__) && EL3==1) || (defined (ARMR5) && (PROCESSOR_ACCESS_VALUE & IOU_SLCR_TZ_MASK)) || defined (ARMA53_32)
- u32 LpdRst;
-
-#if defined (versal)
- u32 RstAddr = CRL_TTC_RST;
- u32 RstMask = CRL_TTC_BASE_RST_MASK << XSLEEP_TTC_INSTANCE;
-#else
- u32 RstAddr = RST_LPD_IOU2;
- u32 RstMask = RST_LPD_IOU2_TTC_BASE_RESET_MASK << XSLEEP_TTC_INSTANCE;
-#endif
- /* check if the timer is reset */
- LpdRst = XSleep_ReadCounterVal(RstAddr);
- if ((LpdRst & RstMask) != 0 ) {
- LpdRst = LpdRst & (~RstMask);
- Xil_Out32(RstAddr, LpdRst);
- } else {
-#endif
- TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET);
- /* check if Timer is disabled */
- if ((TimerCntrl & XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK) == 0) {
- TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET);
- /* check if Timer is configured with proper functionalty for sleep */
- if ((TimerPrescalar & XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK) == 0)
- return;
- }
-#if (defined (__aarch64__) && EL3==1) || (defined (ARMR5) && (PROCESSOR_ACCESS_VALUE & IOU_SLCR_TZ_MASK)) || defined (ARMA53_32)
- }
-#endif
- /* Disable the timer to configure */
- TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET);
- TimerCntrl = TimerCntrl | XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK;
- Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET,
- TimerCntrl);
- /* Disable the prescalar */
- TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
- XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET);
- TimerPrescalar = TimerPrescalar & (~XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK);
- Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET,
- TimerPrescalar);
- /* Enable the Timer */
- TimerCntrl = TimerCntrl & (~XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK);
- Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET,
- TimerCntrl);
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c2/2097f2535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c2/2097f2535243001d18b399c1eb9b3628
deleted file mode 100644
index b924726..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c2/2097f2535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,507 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
- *
- * @file xusbps_endpoint.h
-* @addtogroup usbps_v2_7
-* @{
- *
- * This is an internal file containung the definitions for endpoints. It is
- * included by the xusbps_endpoint.c which is implementing the endpoint
- * functions and by xusbps_intr.c.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- --------------------------------------------------------
- * 1.00a wgr 10/10/10 First release
- * 2.5 pm 02/20/20 Added multiplier bit for ISO frame handling.
- *
- *
- ******************************************************************************/
-#ifndef XUSBPS_ENDPOINT_H
-#define XUSBPS_ENDPOINT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xusbps.h"
-#include "xil_types.h"
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-
-/**
- * Endpoint Device Transfer Descriptor
- *
- * The dTD describes to the device controller the location and quantity of data
- * to be sent/received for given transfer. The driver does not attempt to
- * modify any field in an active dTD except the Next Link Pointer.
- */
-#define XUSBPS_dTDNLP 0x00 /**< Pointer to the next descriptor */
-#define XUSBPS_dTDTOKEN 0x04 /**< Descriptor Token */
-#define XUSBPS_dTDBPTR0 0x08 /**< Buffer Pointer 0 */
-#define XUSBPS_dTDBPTR1 0x0C /**< Buffer Pointer 1 */
-#define XUSBPS_dTDBPTR2 0x10 /**< Buffer Pointer 2 */
-#define XUSBPS_dTDBPTR3 0x14 /**< Buffer Pointer 3 */
-#define XUSBPS_dTDBPTR4 0x18 /**< Buffer Pointer 4 */
-#define XUSBPS_dTDBPTR(n) (XUSBPS_dTDBPTR0 + (n) * 0x04)
-#define XUSBPS_dTDRSRVD 0x1C /**< Reserved field */
-
-/* We use the reserved field in the dTD to store user data. */
-#define XUSBPS_dTDUSERDATA XUSBPS_dTDRSRVD /**< Reserved field */
-
-
-/** @name dTD Next Link Pointer (dTDNLP) bit positions.
- * @{
- */
-#define XUSBPS_dTDNLP_T_MASK 0x00000001
- /**< USB dTD Next Link Pointer Terminate Bit */
-#define XUSBPS_dTDNLP_ADDR_MASK 0xFFFFFFE0
- /**< USB dTD Next Link Pointer Address [31:5] */
-/* @} */
-
-
-/** @name dTD Token (dTDTOKEN) bit positions.
- * @{
- */
-#define XUSBPS_dTDTOKEN_XERR_MASK 0x00000008 /**< dTD Transaction Error */
-#define XUSBPS_dTDTOKEN_BUFERR_MASK 0x00000020 /**< dTD Data Buffer Error */
-#define XUSBPS_dTDTOKEN_HALT_MASK 0x00000040 /**< dTD Halted Flag */
-#define XUSBPS_dTDTOKEN_ACTIVE_MASK 0x00000080 /**< dTD Active Bit */
-#define XUSBPS_dTDTOKEN_MULTO_MASK 0x00000C00 /**< Multiplier Override Field [1:0] */
-#define XUSBPS_dTDTOKEN_IOC_MASK 0x00008000 /**< Interrupt on Complete Bit */
-#define XUSBPS_dTDTOKEN_LEN_MASK 0x7FFF0000 /**< Transfer Length Field */
-/* @} */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- *
- * IMPORTANT NOTE:
- * ===============
- *
- * Many of the following macros modify Device Queue Head (dQH) data structures
- * and Device Transfer Descriptor (dTD) data structures. Those structures can
- * potentially reside in CACHED memory. Therefore, it's the callers
- * responsibility to ensure cache coherency by using provided
- *
- * XUsbPs_dQHInvalidateCache()
- * XUsbPs_dQHFlushCache()
- * XUsbPs_dTDInvalidateCache()
- * XUsbPs_dTDFlushCache()
- *
- * function calls.
- *
- ******************************************************************************/
-#define XUsbPs_dTDInvalidateCache(dTDPtr) \
- Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
-
-#define XUsbPs_dTDFlushCache(dTDPtr) \
- Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
-
-#define XUsbPs_dQHInvalidateCache(dQHPtr) \
- Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
-
-#define XUsbPs_dQHFlushCache(dQHPtr) \
- Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Transfer Length for the given Transfer Descriptor.
- *
- * @param dTDPtr is pointer to the dTD element.
- * @param Len is the length to be set. Range: 0..16384
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetTransferLen(dTDPtr, Len) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
- ~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16))
-
-
-/*****************************************************************************/
-/**
- *
- * This macro gets the Next Link pointer of the given Transfer Descriptor.
- *
- * @param dTDPtr is pointer to the dTD element.
- *
- * @return TransferLength field of the descriptor.
- *
- * @note C-style signature:
- * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDGetNLP(dTDPtr) \
- (XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\
- & XUSBPS_dTDNLP_ADDR_MASK))
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Next Link pointer of the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- * @param NLP is the Next Link Pointer
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetNLP(dTDPtr, NLP) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
- (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
- ~XUSBPS_dTDNLP_ADDR_MASK) | \
- ((NLP) & XUSBPS_dTDNLP_ADDR_MASK))
-
-
-/*****************************************************************************/
-/**
- *
- * This macro gets the Transfer Length for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @return TransferLength field of the descriptor.
- *
- * @note C-style signature:
- * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDGetTransferLen(dTDPtr) \
- (u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) \
- & XUSBPS_dTDTOKEN_LEN_MASK) >> 16)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Interrupt On Complete (IOC) bit for the given Transfer
- * Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetIOC(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetIOC(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
- XUSBPS_dTDTOKEN_IOC_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Terminate bit for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetTerminate(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetTerminate(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) | \
- XUSBPS_dTDNLP_T_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro clears the Terminate bit for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDClrTerminate(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDClrTerminate(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
- ~XUSBPS_dTDNLP_T_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro checks if the given descriptor is active.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @return
- * - TRUE: The buffer is active.
- * - FALSE: The buffer is not active.
- *
- * @note C-style signature:
- * int XUsbPs_dTDIsActive(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDIsActive(dTDPtr) \
- ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
- XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Active bit for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetActive(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetActive(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
- XUSBPS_dTDTOKEN_ACTIVE_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the multiplier bit for the Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- * @param val is the multiplier value.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetMultO(u32 dTDPtr, u32 val)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetMultO(dTDPtr, val) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
- (~XUSBPS_dTDTOKEN_MULTO_MASK)) | val)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro reads the content of a field in a Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- * @param Id is the field ID inside the dTD element to read.
- *
- * @note C-style signature:
- * u32 XUsbPs_ReaddTD(u32 dTDPtr, u32 Id)
- *
- ******************************************************************************/
-#define XUsbPs_ReaddTD(dTDPtr, Id) (*(u32 *)((u32)(dTDPtr) + (u32)(Id)))
-
-/*****************************************************************************/
-/**
- *
- * This macro writes a value to a field in a Transfer Descriptor.
- *
- * @param dTDPtr is pointer to the dTD element.
- * @param Id is the field ID inside the dTD element to read.
- * @param Val is the value to write to the field.
- *
- * @note C-style signature:
- * u32 XUsbPs_WritedTD(u32 dTDPtr, u32 Id, u32 Val)
- *
- ******************************************************************************/
-#define XUsbPs_WritedTD(dTDPtr, Id, Val) \
- (*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val))
-
-
-/******************************************************************************/
-/**
- * Endpoint Device Queue Head
- *
- * Device queue heads are arranged in an array in a continuous area of memory
- * pointed to by the ENDPOINTLISTADDR pointer. The device controller will index
- * into this array based upon the endpoint number received from the USB bus.
- * All information necessary to respond to transactions for all primed
- * transfers is contained in this list so the Device Controller can readily
- * respond to incoming requests without having to traverse a linked list.
- *
- * The device Endpoint Queue Head (dQH) is where all transfers are managed. The
- * dQH is a 48-byte data structure, but must be aligned on a 64-byte boundary.
- * During priming of an endpoint, the dTD (device transfer descriptor) is
- * copied into the overlay area of the dQH, which starts at the nextTD pointer
- * DWord and continues through the end of the buffer pointers DWords. After a
- * transfer is complete, the dTD status DWord is updated in the dTD pointed to
- * by the currentTD pointer. While a packet is in progress, the overlay area of
- * the dQH is used as a staging area for the dTD so that the Device Controller
- * can access needed information with little minimal latency.
- *
- * @note
- * Software must ensure that no interface data structure reachable by the
- * Device Controller spans a 4K-page boundary. The first element of the
- * Endpoint Queue Head List must be aligned on a 4K boundary.
- */
-#define XUSBPS_dQHCFG 0x00 /**< dQH Configuration */
-#define XUSBPS_dQHCPTR 0x04 /**< dQH Current dTD Pointer */
-#define XUSBPS_dQHdTDNLP 0x08 /**< dTD Next Link Ptr in dQH
- overlay */
-#define XUSBPS_dQHdTDTOKEN 0x0C /**< dTD Token in dQH overlay */
-#define XUSBPS_dQHSUB0 0x28 /**< USB dQH Setup Buffer 0 */
-#define XUSBPS_dQHSUB1 0x2C /**< USB dQH Setup Buffer 1 */
-
-
-/** @name dQH Configuration (dQHCFG) bit positions.
- * @{
- */
-#define XUSBPS_dQHCFG_IOS_MASK 0x00008000
- /**< USB dQH Interrupt on Setup Bit */
-#define XUSBPS_dQHCFG_MPL_MASK 0x07FF0000
- /**< USB dQH Maximum Packet Length
- * Field [10:0] */
-#define XUSBPS_dQHCFG_MPL_SHIFT 16
-#define XUSBPS_dQHCFG_ZLT_MASK 0x20000000
- /**< USB dQH Zero Length Termination
- * Select Bit */
-#define XUSBPS_dQHCFG_MULT_MASK 0xC0000000
- /* USB dQH Number of Transactions Field
- * [1:0] */
-#define XUSBPS_dQHCFG_MULT_SHIFT 30
-/* @} */
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Maximum Packet Length field of the give Queue Head.
- *
- * @param dQHPtr is a pointer to the dQH element.
- * @param Len is the length to be set.
- *
- * @note C-style signature:
- * void XUsbPs_dQHSetMaxPacketLen(u32 dQHPtr, u32 Len)
- *
- ******************************************************************************/
-#define XUsbPs_dQHSetMaxPacketLen(dQHPtr, Len) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
- ~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16))
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Interrupt On Setup (IOS) bit for an endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHSetIOS(u32 dQHPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dQHSetIOS(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
- XUSBPS_dQHCFG_IOS_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro clears the Interrupt On Setup (IOS) bit for an endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHClrIOS(u32 dQHPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dQHClrIOS(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
- ~XUSBPS_dQHCFG_IOS_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro enables Zero Length Termination for the endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHEnableZLT(u32 dQHPtr)
- *
- *
- ******************************************************************************/
-#define XUsbPs_dQHEnableZLT(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
- ~XUSBPS_dQHCFG_ZLT_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro disables Zero Length Termination for the endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHDisableZLT(u32 dQHPtr)
- *
- *
- ******************************************************************************/
-#define XUsbPs_dQHDisableZLT(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
- XUSBPS_dQHCFG_ZLT_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro reads the content of a field in a Queue Head.
- *
- * @param dQHPtr is a pointer to the dQH element.
- * @param Id is the Field ID inside the dQH element to read.
- *
- * @note C-style signature:
- * u32 XUsbPs_ReaddQH(u32 dQHPtr, u32 Id)
- *
- ******************************************************************************/
-#define XUsbPs_ReaddQH(dQHPtr, Id) (*(u32 *)((u32)(dQHPtr) + (u32) (Id)))
-
-/*****************************************************************************/
-/**
- *
- * This macro writes a value to a field in a Queue Head.
- *
- * @param dQHPtr is a pointer to the dQH element.
- * @param Id is the Field ID inside the dQH element to read.
- * @param Val is the Value to write to the field.
- *
- * @note C-style signature:
- * u32 XUsbPs_WritedQH(u32 dQHPtr, u32 Id, u32 Val)
- *
- ******************************************************************************/
-#define XUsbPs_WritedQH(dQHPtr, Id, Val) \
- (*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val))
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XUSBPS_ENDPOINT_H */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c2/41e7b6565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c2/41e7b6565243001d18b399c1eb9b3628
deleted file mode 100644
index 8b56036..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c2/41e7b6565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,15 +0,0 @@
-#include "xparameters.h"
-#include "xuartps_hw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-void outbyte(char c);
-
-#ifdef __cplusplus
-}
-#endif
-
-void outbyte(char c) {
- XUartPs_SendByte(STDOUT_BASEADDRESS, c);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c2/501947575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c2/501947575243001d18b399c1eb9b3628
deleted file mode 100644
index 7404bb7..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c2/501947575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,790 +0,0 @@
-/*****************************************************************************
-* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file pcap.c
-*
-* Contains code for enabling and accessing the PCAP
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 02/10/10 Initial release
-* 2.00a jz 05/28/11 Add SD support
-* 2.00a mb 25/05/12 using the EDK provided devcfg driver
-* Nand/SD encryption and review comments
-* 3.00a mb 16/08/12 Added the poll function
-* Removed the FPGA_RST_CTRL define
-* Added the flag for NON PS instantiated bitstream
-* 4.00a sgd 02/28/13 Fix for CR#681014 - ECC init in FSBL should not call
-* fabric_init()
-* Fix for CR#689026 - FSBL doesn't hold PL resets active
-* during bit download
-* Fix for CR#699475 - FSBL functionality is broken and
-* its not able to boot in QSPI/NAND
-* bootmode
-* Fix for CR#705664 - FSBL fails to decrypt the
-* bitstream when the image is AES
-* encrypted using non-zero key value
-* 6.00a kc 08/30/13 Fix for CR#722979 - Provide customer-friendly
-* changelogs in FSBL
-* 7.00a kc 10/25/13 Fix for CR#724620 - How to handle PCAP_MODE after
-* bitstream configuration
-* Fix for CR#726178 - FabricInit() PROG_B is kept active
-* for 5mS.
-* Fix for CR#731839 - FSBL has to check the
-* HMAC error status after decryption
-* 12/04/13 Fix for CR#764382 - How to handle PCAP_MODE after
-* bitstream configuration - PCAP_MODE
-* and PCAP_PR bits are not modified
-* 8.00a kc 2/20/14 Fix for CR#775631 - FSBL: FsblGetGlobalTimer()
-* is not proper
-* 10.00a kc 07/24/14 Fix for CR#809336 - Minor code cleanup
-* 13.00a ssc 04/10/15 Fix for CR#846899 - Corrected logic to clear
-* DMA done count
-* 15.00a gan 07/21/16 Fix for CR# 953654 -(2016.3)FSBL -
-* In pcap.c/pcap.h/main.h,
-* Fabric Initialization sequence
-* is modified to check the PL power
-* before sequence starts and checking
-* INIT_B reset status twice in case
-* of failure.
-* 16.00a gan 08/02/16 Fix for CR# 955897 -(2016.3)FSBL -
-* In pcap.c, check pl power
-* through MCTRL register for
-* 3.0 and later versions of silicon.
-*
-*
-* @note
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "pcap.h"
-#include "nand.h" /* For NAND geometry information */
-#include "fsbl.h"
-#include "image_mover.h" /* For MoveImage */
-#include "xparameters.h"
-#include "xil_exception.h"
-#include "xdevcfg.h"
-#include "sleep.h"
-#include "xtime_l.h"
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
-#include "xwdtps.h"
-#endif
-/************************** Constant Definitions *****************************/
-/*
- * The following constants map to the XPAR parameters created in the
- * xparameters.h file. They are only defined here such that a user can easily
- * change all the needed parameters in one place.
- */
-
-#define DCFG_DEVICE_ID XPAR_XDCFG_0_DEVICE_ID
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-extern int XDcfgPollDone(u32 MaskValue, u32 MaxCount);
-
-/************************** Variable Definitions *****************************/
-/* Devcfg driver instance */
-static XDcfg DcfgInstance;
-XDcfg *DcfgInstPtr;
-extern u32 Silicon_Version;
-#ifdef XPAR_XWDTPS_0_BASEADDR
-extern XWdtPs Watchdog; /* Instance of WatchDog Timer */
-#endif
-
-/******************************************************************************/
-/**
-*
-* This function transfer data using PCAP
-*
-* @param SourceDataPtr is a pointer to where the data is read from
-* @param DestinationDataPtr is a pointer to where the data is written to
-* @param SourceLength is the length of the data to be moved in words
-* @param DestinationLength is the length of the data to be moved in words
-* @param SecureTransfer indicated the encryption key location, 0 for
-* non-encrypted
-*
-* @return
-* - XST_SUCCESS if the transfer is successful
-* - XST_FAILURE if the transfer fails
-*
-* @note None
-*
-****************************************************************************/
-u32 PcapDataTransfer(u32 *SourceDataPtr, u32 *DestinationDataPtr,
- u32 SourceLength, u32 DestinationLength, u32 SecureTransfer)
-{
- u32 Status;
- u32 IntrStsReg;
- u32 PcapTransferType = XDCFG_CONCURRENT_NONSEC_READ_WRITE;
-
- /*
- * Check for secure transfer
- */
- if (SecureTransfer) {
- PcapTransferType = XDCFG_CONCURRENT_SECURE_READ_WRITE;
- }
-
-#ifdef FSBL_PERF
- XTime tXferCur = 0;
- FsblGetGlobalTime(&tXferCur);
-#endif
-
- /*
- * Clear the PCAP status registers
- */
- Status = ClearPcapStatus();
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO,"PCAP_CLEAR_STATUS_FAIL \r\n");
- return XST_FAILURE;
- }
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
- /*
- * Prevent WDT reset
- */
- XWdtPs_RestartWdt(&Watchdog);
-#endif
-
- /*
- * PCAP single DMA transfer setup
- */
- SourceDataPtr = (u32*)((u32)SourceDataPtr | PCAP_LAST_TRANSFER);
- DestinationDataPtr = (u32*)((u32)DestinationDataPtr | PCAP_LAST_TRANSFER);
-
- /*
- * Transfer using Device Configuration
- */
- Status = XDcfg_Transfer(DcfgInstPtr, (u8 *)SourceDataPtr,
- SourceLength,
- (u8 *)DestinationDataPtr,
- DestinationLength, PcapTransferType);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %lu \r \n",Status);
- return XST_FAILURE;
- }
-
- /*
- * Dump the PCAP registers
- */
- PcapDumpRegisters();
-
- /*
- * Poll for the DMA done
- */
- Status = XDcfgPollDone(XDCFG_IXR_DMA_DONE_MASK, MAX_COUNT);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO,"PCAP_DMA_DONE_FAIL \r\n");
- return XST_FAILURE;
- }
-
- fsbl_printf(DEBUG_INFO,"DMA Done ! \n\r");
-
- /*
- * Check for errors
- */
- IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
- if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
- fsbl_printf(DEBUG_INFO,"Errors in PCAP \r\n");
- return XST_FAILURE;
- }
-
- /*
- * For Performance measurement
- */
-#ifdef FSBL_PERF
- XTime tXferEnd = 0;
- fsbl_printf(DEBUG_GENERAL,"Time taken is ");
- FsblMeasurePerfTime(tXferCur,tXferEnd);
-#endif
-
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************/
-/**
-*
-* This function loads PL partition using PCAP
-*
-* @param SourceDataPtr is a pointer to where the data is read from
-* @param DestinationDataPtr is a pointer to where the data is written to
-* @param SourceLength is the length of the data to be moved in words
-* @param DestinationLength is the length of the data to be moved in words
-* @param SecureTransfer indicated the encryption key location, 0 for
-* non-encrypted
-*
-* @return
-* - XST_SUCCESS if the transfer is successful
-* - XST_FAILURE if the transfer fails
-*
-* @note None
-*
-****************************************************************************/
-u32 PcapLoadPartition(u32 *SourceDataPtr, u32 *DestinationDataPtr,
- u32 SourceLength, u32 DestinationLength, u32 SecureTransfer)
-{
- u32 Status;
- u32 IntrStsReg;
- u32 PcapTransferType = XDCFG_NON_SECURE_PCAP_WRITE;
-
- /*
- * Check for secure transfer
- */
- if (SecureTransfer) {
- PcapTransferType = XDCFG_SECURE_PCAP_WRITE;
- }
-
-#ifdef FSBL_PERF
- XTime tXferCur = 0;
- FsblGetGlobalTime(&tXferCur);
-#endif
-
- /*
- * Clear the PCAP status registers
- */
- Status = ClearPcapStatus();
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO,"PCAP_CLEAR_STATUS_FAIL \r\n");
- return XST_FAILURE;
- }
-
- /*
- * For Bitstream case destination address will be 0xFFFFFFFF
- */
- DestinationDataPtr = (u32*)XDCFG_DMA_INVALID_ADDRESS;
-
- /*
- * New Bitstream download initialization sequence
- */
- Status = FabricInit();
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
-
-#ifdef XPAR_XWDTPS_0_BASEADDR
- /*
- * Prevent WDT reset
- */
- XWdtPs_RestartWdt(&Watchdog);
-#endif
-
- /*
- * PCAP single DMA transfer setup
- */
- SourceDataPtr = (u32*)((u32)SourceDataPtr | PCAP_LAST_TRANSFER);
- DestinationDataPtr = (u32*)((u32)DestinationDataPtr | PCAP_LAST_TRANSFER);
-
- /*
- * Transfer using Device Configuration
- */
- Status = XDcfg_Transfer(DcfgInstPtr, (u8 *)SourceDataPtr,
- SourceLength,
- (u8 *)DestinationDataPtr,
- DestinationLength, PcapTransferType);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %lu \r \n",Status);
- return XST_FAILURE;
- }
-
-
- /*
- * Dump the PCAP registers
- */
- PcapDumpRegisters();
-
-
- /*
- * Poll for the DMA done
- */
- Status = XDcfgPollDone(XDCFG_IXR_DMA_DONE_MASK, MAX_COUNT);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO,"PCAP_DMA_DONE_FAIL \r\n");
- return XST_FAILURE;
- }
-
- fsbl_printf(DEBUG_INFO,"DMA Done ! \n\r");
-
- /*
- * Poll for FPGA Done
- */
- Status = XDcfgPollDone(XDCFG_IXR_PCFG_DONE_MASK, MAX_COUNT);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO,"PCAP_FPGA_DONE_FAIL\r\n");
- return XST_FAILURE;
- }
-
- fsbl_printf(DEBUG_INFO,"FPGA Done ! \n\r");
-
- /*
- * Check for errors
- */
- IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
- if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
- fsbl_printf(DEBUG_INFO,"Errors in PCAP \r\n");
- return XST_FAILURE;
- }
-
- /*
- * For Performance measurement
- */
-#ifdef FSBL_PERF
- XTime tXferEnd = 0;
- fsbl_printf(DEBUG_GENERAL,"Time taken is ");
- FsblMeasurePerfTime(tXferCur,tXferEnd);
-#endif
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************/
-/**
-*
-* This function Initializes the PCAP driver.
-*
-* @param none
-*
-* @return
-* - XST_SUCCESS if the pcap driver initialization is successful
-* - XST_FAILURE if the pcap driver initialization fails
-*
-* @note none
-*
-****************************************************************************/
-int InitPcap(void)
-{
- XDcfg_Config *ConfigPtr;
- int Status = XST_SUCCESS;
- DcfgInstPtr = &DcfgInstance;
-
- /*
- * Initialize the Device Configuration Interface driver.
- */
- ConfigPtr = XDcfg_LookupConfig(DCFG_DEVICE_ID);
-
- Status = XDcfg_CfgInitialize(DcfgInstPtr, ConfigPtr,
- ConfigPtr->BaseAddr);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO, "XDcfg_CfgInitialize failed \n\r");
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-/******************************************************************************/
-/**
-*
-* This function programs the Fabric for use.
-*
-* @param None
-*
-* @return
-* - XST_SUCCESS if the Fabric initialization is successful
-* - XST_FAILURE if the Fabric initialization fails
-* @note None
-*
-****************************************************************************/
-u32 FabricInit(void)
-{
- u32 PcapReg;
- u32 PcapCtrlRegVal;
- u32 StatusReg;
- u32 MctrlReg;
- u32 PcfgInit;
- u32 TimerExpired=0;
- XTime tCur=0;
- XTime tEnd=0;
-
-
- /*
- * Set Level Shifters DT618760 - PS to PL enabling
- */
- Xil_Out32(PS_LVL_SHFTR_EN, LVL_PS_PL);
- fsbl_printf(DEBUG_INFO,"Level Shifter Value = 0x%lx \r\n",
- Xil_In32(PS_LVL_SHFTR_EN));
-
- /*
- * Get DEVCFG controller settings
- */
- PcapReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET);
-
- /*
- * Check the PL power status
- */
- if(Silicon_Version >= SILICON_VERSION_3)
- {
- MctrlReg = XDcfg_GetMiscControlRegister(DcfgInstPtr);
-
- if((MctrlReg & XDCFG_MCTRL_PCAP_PCFG_POR_B_MASK) !=
- XDCFG_MCTRL_PCAP_PCFG_POR_B_MASK)
- {
- fsbl_printf(DEBUG_INFO,"Fabric not powered up\r\n");
- return XST_FAILURE;
- }
- }
-
-
- /*
- * Setting PCFG_PROG_B signal to high
- */
- XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
- (PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK));
-
- /*
- * Check for AES source key
- */
- PcapCtrlRegVal = XDcfg_GetControlRegister(DcfgInstPtr);
- if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
- /*
- * 5msec delay
- */
- usleep(5000);
- }
-
- /*
- * Setting PCFG_PROG_B signal to low
- */
- XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
- (PcapReg & ~XDCFG_CTRL_PCFG_PROG_B_MASK));
-
- /*
- * Check for AES source key
- */
- if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
- /*
- * 5msec delay
- */
- usleep(5000);
- }
-
- /*
- * Polling the PCAP_INIT status for Reset or timeout
- */
-
- XTime_GetTime(&tCur);
- do
- {
- PcfgInit = (XDcfg_GetStatusRegister(DcfgInstPtr) &
- XDCFG_STATUS_PCFG_INIT_MASK);
- if(PcfgInit == 0)
- {
- break;
- }
- XTime_GetTime(&tEnd);
- if((u64)((u64)tCur + (COUNTS_PER_MILLI_SECOND*30)) > (u64)tEnd)
- {
- TimerExpired = 1;
- }
-
- } while(!TimerExpired);
-
- if(TimerExpired == 1)
- {
- TimerExpired = 0;
- /*
- * Came here due to expiration and PCAP_INIT is set.
- * Retry PCFG_PROG_B High -> Low again
- */
-
- /*
- * Setting PCFG_PROG_B signal to high
- */
- XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
- (PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK));
-
- /*
- * Check for AES source key
- */
- PcapCtrlRegVal = XDcfg_GetControlRegister(DcfgInstPtr);
- if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
- /*
- * 5msec delay
- */
- usleep(5000);
- }
-
- /*
- * Setting PCFG_PROG_B signal to low
- */
- XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
- (PcapReg & ~XDCFG_CTRL_PCFG_PROG_B_MASK));
-
- /*
- * Check for AES source key
- */
- if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
- /*
- * 5msec delay
- */
- usleep(5000);
- }
- /*
- * Polling the PCAP_INIT status for Reset or timeout (second iteration)
- */
-
- XTime_GetTime(&tCur);
- do
- {
- PcfgInit = (XDcfg_GetStatusRegister(DcfgInstPtr) &
- XDCFG_STATUS_PCFG_INIT_MASK);
- if(PcfgInit == 0)
- {
- break;
- }
- XTime_GetTime(&tEnd);
- if((u64)((u64)tCur + (COUNTS_PER_MILLI_SECOND*30)) > (u64)tEnd)
- {
- TimerExpired = 1;
- }
-
- } while(!TimerExpired);
-
- if(TimerExpired == 1)
- {
- /*
- * Came here due to PCAP_INIT is not getting reset
- * for PCFG_PROG_B signal High -> Low
- */
- fsbl_printf(DEBUG_INFO,"Fabric Init failed\r\n");
- return XST_FAILURE;
- }
- }
-
- /*
- * Setting PCFG_PROG_B signal to high
- */
- XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
- (PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK));
-
- /*
- * Polling the PCAP_INIT status for Set
- */
- while(!(XDcfg_GetStatusRegister(DcfgInstPtr) &
- XDCFG_STATUS_PCFG_INIT_MASK));
-
- /*
- * Get Device configuration status
- */
- StatusReg = XDcfg_GetStatusRegister(DcfgInstPtr);
- fsbl_printf(DEBUG_INFO,"Devcfg Status register = 0x%lx \r\n",StatusReg);
-
- fsbl_printf(DEBUG_INFO,"PCAP:Fabric is Initialized done\r\n");
-
- return XST_SUCCESS;
-}
-/******************************************************************************/
-/**
-*
-* This function Clears the PCAP status registers.
-*
-* @param None
-*
-* @return
-* - XST_SUCCESS if the pcap status registers are cleared
-* - XST_FAILURE if errors are there
-* - XST_DEVICE_BUSY if Pcap device is busy
-* @note None
-*
-****************************************************************************/
-u32 ClearPcapStatus(void)
-{
-
- u32 StatusReg;
- u32 IntStatusReg;
-
- /*
- * Clear it all, so if Boot ROM comes back, it can proceed
- */
- XDcfg_IntrClear(DcfgInstPtr, 0xFFFFFFFF);
-
- /*
- * Get PCAP Interrupt Status Register
- */
- IntStatusReg = XDcfg_IntrGetStatus(DcfgInstPtr);
- if (IntStatusReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
- fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %lx\r\n",
- IntStatusReg);
- return XST_FAILURE;
- }
-
- /*
- * Read the PCAP status register for DMA status
- */
- StatusReg = XDcfg_GetStatusRegister(DcfgInstPtr);
-
- fsbl_printf(DEBUG_INFO,"PCAP:StatusReg = 0x%.8lx\r\n", StatusReg);
-
- /*
- * If the queue is full, return w/ XST_DEVICE_BUSY
- */
- if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_F_MASK) ==
- XDCFG_STATUS_DMA_CMD_Q_F_MASK) {
-
- fsbl_printf(DEBUG_INFO,"PCAP_DEVICE_BUSY\r\n");
- return XST_DEVICE_BUSY;
- }
-
- fsbl_printf(DEBUG_INFO,"PCAP:device ready\r\n");
-
- /*
- * There are unacknowledged DMA commands outstanding
- */
- if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_E_MASK) !=
- XDCFG_STATUS_DMA_CMD_Q_E_MASK) {
-
- IntStatusReg = XDcfg_IntrGetStatus(DcfgInstPtr);
-
- if ((IntStatusReg & XDCFG_IXR_DMA_DONE_MASK) !=
- XDCFG_IXR_DMA_DONE_MASK){
- /*
- * Error state, transfer cannot occur
- */
- fsbl_printf(DEBUG_INFO,"PCAP:IntStatus indicates error\r\n");
- return XST_FAILURE;
- }
- else {
- /*
- * clear out the status
- */
- XDcfg_IntrClear(DcfgInstPtr, XDCFG_IXR_DMA_DONE_MASK);
- }
- }
-
- if ((StatusReg & XDCFG_STATUS_DMA_DONE_CNT_MASK) != 0) {
- XDcfg_SetStatusRegister(DcfgInstPtr, StatusReg |
- XDCFG_STATUS_DMA_DONE_CNT_MASK);
- }
-
- fsbl_printf(DEBUG_INFO,"PCAP:Clear done\r\n");
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************/
-/**
-*
-* This function prints PCAP register status.
-*
-* @param none
-*
-* @return none
-*
-* @note none
-*
-****************************************************************************/
-void PcapDumpRegisters (void) {
-
- fsbl_printf(DEBUG_INFO,"PCAP register dump:\r\n");
-
- fsbl_printf(DEBUG_INFO,"PCAP CTRL 0x%x: 0x%08lx\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_CTRL_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_CTRL_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP LOCK 0x%x: 0x%08lx\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_LOCK_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_LOCK_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP CONFIG 0x%x: 0x%08lx\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_CFG_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_CFG_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP ISR 0x%x: 0x%08lx\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP IMR 0x%x: 0x%08lx\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_MASK_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_MASK_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP STATUS 0x%x: 0x%08lx\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_STATUS_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_STATUS_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP DMA SRC ADDR 0x%x: 0x%08lx\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_ADDR_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_ADDR_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP DMA DEST ADDR 0x%x: 0x%08lx\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_ADDR_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_ADDR_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP DMA SRC LEN 0x%x: 0x%08lx\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_LEN_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_LEN_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP DMA DEST LEN 0x%x: 0x%08lx\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_LEN_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_LEN_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP ROM SHADOW CTRL 0x%x: 0x%08lx\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_ROM_SHADOW_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_ROM_SHADOW_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP MBOOT 0x%x: 0x%08lx\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_MULTIBOOT_ADDR_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_MULTIBOOT_ADDR_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP SW ID 0x%x: 0x%08lx\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_SW_ID_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_SW_ID_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP UNLOCK 0x%x: 0x%08lx\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_UNLOCK_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_UNLOCK_OFFSET));
- fsbl_printf(DEBUG_INFO,"PCAP MCTRL 0x%x: 0x%08lx\r\n",
- XPS_DEV_CFG_APB_BASEADDR + XDCFG_MCTRL_OFFSET,
- Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_MCTRL_OFFSET));
-}
-
-/******************************************************************************/
-/**
-*
-* This function Polls for the DMA done or FPGA done.
-*
-* @param none
-*
-* @return
-* - XST_SUCCESS if polling for DMA/FPGA done is successful
-* - XST_FAILURE if polling for DMA/FPGA done fails
-*
-* @note none
-*
-****************************************************************************/
-int XDcfgPollDone(u32 MaskValue, u32 MaxCount)
-{
- int Count = MaxCount;
- u32 IntrStsReg = 0;
-
- /*
- * poll for the DMA done
- */
- IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
- while ((IntrStsReg & MaskValue) !=
- MaskValue) {
- IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
- Count -=1;
-
- if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
- fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %lx\r\n",
- IntrStsReg);
- PcapDumpRegisters();
- return XST_FAILURE;
- }
-
- if(!Count) {
- fsbl_printf(DEBUG_GENERAL,"PCAP transfer timed out \r\n");
- return XST_FAILURE;
- }
- if (Count > (MAX_COUNT-100)) {
- fsbl_printf(DEBUG_GENERAL,".");
- }
- }
-
- fsbl_printf(DEBUG_GENERAL,"\n\r");
-
- XDcfg_IntrClear(DcfgInstPtr, IntrStsReg & MaskValue);
-
- return XST_SUCCESS;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c2/719a71595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c2/719a71595243001d18b399c1eb9b3628
deleted file mode 100644
index 4831d67..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c2/719a71595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,84 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2006 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-*
-* File : microblaze_update_dcache.s
-* Date : 2003, September 24
-* Company: Xilinx
-* Group : Emerging Software Technologies
-*
-* Summary:
-* Update dcache on the microblaze.
-* Takes in three parameters
-* r5 : Cache Tag Line
-* r6 : Cache Data
-* r7 : Lock/Valid information
-* Bit 30 is Lock [ 1 indicates locked ]
-* Bit 31 is Valid [ 1 indicates valid ]
-*
-* --------------------------------------------------------------
-* | Lock | Valid | Effect
-* --------------------------------------------------------------
-* | 0 | 0 | Invalidate Cache
-* | 0 | 1 | Valid, but unlocked cacheline
-* | 1 | 0 | Invalidate Cache, No effect of lock
-* | 1 | 1 | Valid cache. Locked to a
-* | | | particular address
-* --------------------------------------------------------------
-*
-*
-**********************************************************************************/
-#include "xparameters.h"
-
-#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
-#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 1
-#endif
-
- .text
- .globl microblaze_update_dcache
- .ent microblaze_update_dcache
- .align 2
-microblaze_update_dcache:
-#if (XPAR_MICROBLAZE_USE_DCACHE==1) && (XPAR_MICROBLAZE_ALLOW_DCACHE_WR==1)
-
-#if XPAR_MICROBLAZE_DCACHE_LINE_LEN == 1
-
-/* Read the MSR register into a temp register */
- mfs r18, rmsr
-
-/* Clear the dcache enable bit to disable the cache
- Register r10,r18 are volatile registers and hence do not need to be saved before use */
- andi r10, r18, ~128
- mts rmsr, r10
-
-/* Update the lock and valid info */
- andi r5, r5, 0xfffffffc
- or r5, r5, r7
-
-/* Update dcache */
- wdc r5, r6
-
-/* Return */
- rtsd r15, 8
- mts rmsr, r18
-
-#else
-
- /* The only valid usage of this routine for larger cache line lengths is to invalidate a data cache line
- So call microblaze_init_dcache_range appropriately to do the job */
-
- brid microblaze_init_dcache_range
- addik r6, r0, (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
-
- /* We don't have a return instruction here. This is tail call optimization :) */
-
-#endif /* XPAR_MICROBLAZE_DCACHE_LINE_LEN == 1 */
-
-#else
- rtsd r15, 8
- nop
-#endif
- .end microblaze_update_dcache
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c2/81fd67595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c2/81fd67595243001d18b399c1eb9b3628
deleted file mode 100644
index 472cee4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c2/81fd67595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,54 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2008 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-* microblaze_invalidate_cache_ext_range (unsigned int cacheaddr, unsigned int len)
-*
-*Invalidate an L2 cache range
-*
-*Parameters:
-* 'cacheaddr' - address in the L2 cache where invalidation begins
-* 'len ' - length (in bytes) worth of Dcache to be invalidated
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-#include "microblaze_instructions.h"
-
-#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
-
- .text
- .globl microblaze_invalidate_cache_ext_range
- .ent microblaze_invalidate_cache_ext_range
- .align 2
-
-microblaze_invalidate_cache_ext_range:
-#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
- beqi r6, Loop_done
-
- ADD r6, r5, r6
- ADDIK r6, r6, -1
-
- ANDI r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
- ANDI r5, r5, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
-
- RSUBK r6, r5, r6
-
-Loop_start:
- wdc.ext.clear r5, r6
-#if defined (__arch64__ )
- addlik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
- beagei r6, Loop_start
-#else
- bneid r6, Loop_start
- addik r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
-#endif
-
-Loop_done:
-#endif
- rtsd r15, 8
- nop
-
- .end microblaze_invalidate_cache_ext_range
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c2/d1532a555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c2/d1532a555243001d18b399c1eb9b3628
deleted file mode 100644
index dd7972e..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c2/d1532a555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,26 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file initialise_monitor_handles.c
-*
-* Contains blank function to avoid compilation error
-*
-* @note
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/29/14 First release
-*
-* The boot code performs minimum configuration which is required for an
-* application to run starting from processor reset state of the processor. Below is a
-* sequence illustrating what all configuration is performed before control
-* reaches to main function.
-*
-* 1. Program vector table base for exception handling
-* 2. Invalidate instruction cache, data cache and TLBs
-* 3. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine,
-* abort, system)
-* 4. Configure MMU with short descriptor translation table format and program
-* base address of translation table
-* 5. Enable data cache, instruction cache and MMU
-* 6. Enable Floating point unit
-* 7. Transfer control to _start which clears BSS sections, initializes
-* global timer and runs global constructor before jumping to main
-* application
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 1.00a ecm/sdm 10/20/09 Initial version
-* 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
-* register settings.
-* 3.06a asa 06/17/12 Modified the TTBR settings and L2 Cache auxiliary
-* register settings.
-* 3.07a asa 07/16/12 Modified the L2 Cache controller settings to improve
-* performance. Changed the property of the ".boot"
-* section.
-* 3.07a sgd 08/21/12 Modified the L2 Cache controller and cp15 Aux Control
-* Register settings
-* 3.09a sgd 02/06/13 Updated SLCR l2c Ram Control register to a
-* value of 0x00020202. Fix for CR 697094 (SI#687034).
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-* 4.2 pkp 06/19/14 Enabled asynchronous abort exception
-* 5.0 pkp 16/15/14 Modified initialization code to enable scu after
-* MMU is enabled
-* 5.1 pkp 05/13/15 Changed the initialization order so to first invalidate
-* caches and TLB, enable MMU and caches, then enable SMP
-* bit in ACTLR. L2Cache invalidation and enabling of L2Cache
-* is done later.
-* 5.4 asa 12/6/15 Added code to initialize SPSR for all relevant modes.
-* 6.0 mus 08/04/16 Added code to detect zynq-7000 base silicon configuration and
-* attempt to enable dual core behavior on single cpu zynq-7000s
-* devices is prevented from corrupting system behavior.
-* 6.0 mus 08/24/16 Check CPU core before putting cpu1 to reset for single core
-* zynq-7000s devices
-* 7.6 mus 09/02/21 SCU invalidation should be done only from primary CPU, so
-* skipping it when USE_AMP is set to 1. It fixes CR#1109723
-*
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#include "xparameters.h"
-#include "xil_errata.h"
-
-.globl MMUTable
-.global _prestart
-.global _boot
-.global __stack
-.global __irq_stack
-.global __supervisor_stack
-.global __abort_stack
-.global __fiq_stack
-.global __undef_stack
-.global _vector_table
-
-.set PSS_L2CC_BASE_ADDR, 0xF8F02000
-.set PSS_SLCR_BASE_ADDR, 0xF8000000
-
-.set RESERVED, 0x0fffff00
-.set TblBase , MMUTable
-.set LRemap, 0xFE00000F /* set the base address of the peripheral block as not shared */
-.set L2CCWay, (PSS_L2CC_BASE_ADDR + 0x077C) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)*/
-.set L2CCSync, (PSS_L2CC_BASE_ADDR + 0x0730) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)*/
-.set L2CCCrtl, (PSS_L2CC_BASE_ADDR + 0x0100) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)*/
-.set L2CCAuxCrtl, (PSS_L2CC_BASE_ADDR + 0x0104) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)*/
-.set L2CCTAGLatReg, (PSS_L2CC_BASE_ADDR + 0x0108) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)*/
-.set L2CCDataLatReg, (PSS_L2CC_BASE_ADDR + 0x010C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)*/
-.set L2CCIntClear, (PSS_L2CC_BASE_ADDR + 0x0220) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)*/
-.set L2CCIntRaw, (PSS_L2CC_BASE_ADDR + 0x021C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)*/
-
-.set SLCRlockReg, (PSS_SLCR_BASE_ADDR + 0x04) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/
-.set SLCRUnlockReg, (PSS_SLCR_BASE_ADDR + 0x08) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/
-.set SLCRL2cRamReg, (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/
-.set SLCRCPURSTReg, (0xF8000000 + 0x244) /*(XPS_SYS_CTRL_BASEADDR + A9_CPU_RST_CTRL_OFFSET)*/
-.set EFUSEStaus, (0xF800D000 + 0x10) /*(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)*/
-
-/* workaround for simulation not working when L1 D and I caches,MMU and L2 cache enabled - DT568997 */
-.if SIM_MODE == 1
-.set CRValMmuCac, 0b00000000000000 /* Disable IDC, and MMU */
-.else
-.set CRValMmuCac, 0b01000000000101 /* Enable IDC, and MMU */
-.endif
-
-.set CRValHiVectorAddr, 0b10000000000000 /* Set the Vector address to high, 0xFFFF0000 */
-
-.set L2CCAuxControl, 0x72360000 /* Enable all prefetching, Cache replacement policy, Parity enable,
- Event monitor bus enable and Way Size (64 KB) */
-.set L2CCControl, 0x01 /* Enable L2CC */
-.set L2CCTAGLatency, 0x0111 /* latency for TAG RAM */
-.set L2CCDataLatency, 0x0121 /* latency for DATA RAM */
-
-.set SLCRlockKey, 0x767B /* SLCR lock key */
-.set SLCRUnlockKey, 0xDF0D /* SLCR unlock key */
-.set SLCRL2cRamConfig, 0x00020202 /* SLCR L2C ram configuration */
-
-/* Stack Pointer locations for boot code */
-.set Undef_stack, __undef_stack
-.set FIQ_stack, __fiq_stack
-.set Abort_stack, __abort_stack
-.set SPV_stack, __supervisor_stack
-.set IRQ_stack, __irq_stack
-.set SYS_stack, __stack
-
-.set vector_base, _vector_table
-
-.set FPEXC_EN, 0x40000000 /* FPU enable bit, (1 << 30) */
-
-.section .boot,"ax"
-
-
-/* this initializes the various processor modes */
-
-_prestart:
-_boot:
-
-#if XPAR_CPU_ID==0
- /* only allow cpu0 through */
- mrc p15,0,r1,c0,c0,5
- and r1, r1, #0xf
- cmp r1, #0
- beq CheckEFUSE
- EndlessLoop0:
- wfe
- b EndlessLoop0
-
-CheckEFUSE:
- ldr r0,=EFUSEStaus
- ldr r1,[r0] /* Read eFuse setting */
- ands r1,r1,#0x80 /* Check whether device is having single core */
- beq OKToRun
-
- /* single core device, reset cpu1 */
- ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
- ldr r1,=SLCRUnlockKey /* set unlock key */
- str r1, [r0] /* Unlock SLCR */
-
- ldr r0,=SLCRCPURSTReg
- ldr r1,[r0] /* Read CPU Software Reset Control register */
- orr r1,r1,#0x22
- str r1,[r0] /* Reset CPU1 */
-
- ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
- ldr r1,=SLCRlockKey /* set lock key */
- str r1, [r0] /* lock SLCR */
-
-#elif XPAR_CPU_ID==1
- /* only allow cpu1 through */
- mrc p15,0,r1,c0,c0,5
- and r1, r1, #0xf
- cmp r1, #1
- beq CheckEFUSE1
- b EndlessLoop1
-
-CheckEFUSE1:
- ldr r0,=EFUSEStaus
- ldr r1,[r0] /* Read eFuse setting */
- ands r1,r1,#0x80 /* Check whether device is having single core */
- beq OKToRun
- EndlessLoop1:
- wfe
- b EndlessLoop1
-#endif
-
-OKToRun:
- mrc p15, 0, r0, c0, c0, 0 /* Get the revision */
- and r5, r0, #0x00f00000
- and r6, r0, #0x0000000f
- orr r6, r6, r5, lsr #20-4
-
-#ifdef CONFIG_ARM_ERRATA_742230
- cmp r6, #0x22 /* only present up to r2p2 */
- mrcle p15, 0, r10, c15, c0, 1 /* read diagnostic register */
- orrle r10, r10, #1 << 4 /* set bit #4 */
- mcrle p15, 0, r10, c15, c0, 1 /* write diagnostic register */
-#endif
-
-#ifdef CONFIG_ARM_ERRATA_743622
- teq r5, #0x00200000 /* only present in r2p* */
- mrceq p15, 0, r10, c15, c0, 1 /* read diagnostic register */
- orreq r10, r10, #1 << 6 /* set bit #6 */
- mcreq p15, 0, r10, c15, c0, 1 /* write diagnostic register */
-#endif
-
- /* set VBAR to the _vector_table address in linker script */
- ldr r0, =vector_base
- mcr p15, 0, r0, c12, c0, 0
-
- /*invalidate scu*/
-#if USE_AMP!=1
- ldr r7, =0xf8f0000c
- ldr r6, =0xffff
- str r6, [r7]
-#endif
-
- /* Invalidate caches and TLBs */
- mov r0,#0 /* r0 = 0 */
- mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
- mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
- mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */
- bl invalidate_dcache /* invalidate dcache */
-
- /* Disable MMU, if enabled */
- mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */
- bic r0, r0, #0x1 /* clear bit 0 */
- mcr p15, 0, r0, c1, c0, 0 /* write value back */
-
-#ifdef SHAREABLE_DDR
- /* Mark the entire DDR memory as shareable */
- ldr r3, =0x3ff /* 1024 entries to cover 1G DDR */
- ldr r0, =TblBase /* MMU Table address in memory */
- ldr r2, =0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
-shareable_loop:
- str r2, [r0] /* write the entry to MMU table */
- add r0, r0, #0x4 /* next entry in the table */
- add r2, r2, #0x100000 /* next section */
- subs r3, r3, #1
- bge shareable_loop /* loop till 1G is covered */
-#endif
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the irq stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x12 /* IRQ mode */
- msr cpsr, r2
- ldr r13,=IRQ_stack /* IRQ stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the supervisor stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x13 /* supervisor mode */
- msr cpsr, r2
- ldr r13,=SPV_stack /* Supervisor stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the Abort stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x17 /* Abort mode */
- msr cpsr, r2
- ldr r13,=Abort_stack /* Abort stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the FIQ stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x11 /* FIQ mode */
- msr cpsr, r2
- ldr r13,=FIQ_stack /* FIQ stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the Undefine stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x1b /* Undefine mode */
- msr cpsr, r2
- ldr r13,=Undef_stack /* Undefine stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the system stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x1F /* SYS mode */
- msr cpsr, r2
- ldr r13,=SYS_stack /* SYS stack pointer */
-
- /*set scu enable bit in scu*/
- ldr r7, =0xf8f00000
- ldr r0, [r7]
- orr r0, r0, #0x1
- str r0, [r7]
-
- /* enable MMU and cache */
-
- ldr r0,=TblBase /* Load MMU translation table base */
- orr r0, r0, #0x5B /* Outer-cacheable, WB */
- mcr 15, 0, r0, c2, c0, 0 /* TTB0 */
-
- mvn r0,#0 /* Load MMU domains -- all ones=manager */
- mcr p15,0,r0,c3,c0,0
-
- /* Enable mmu, icahce and dcache */
- ldr r0,=CRValMmuCac
- mcr p15,0,r0,c1,c0,0 /* Enable cache and MMU */
- dsb /* dsb allow the MMU to start up */
- isb /* isb flush prefetch buffer */
-
- /* Write to ACTLR */
- mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/
- orr r0, r0, #(0x01 << 6) /* set SMP bit */
- orr r0, r0, #(0x01 ) /* Cache/TLB maintenance broadcast */
- mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/
-
-/* Invalidate L2 Cache and enable L2 Cache*/
-/* For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) */
-#if USE_AMP!=1
- ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */
- mov r1, #0 /* force the disable bit */
- str r1, [r0] /* disable the L2 Caches */
-
- ldr r0,=L2CCAuxCrtl /* Load L2CC base address base + Aux control register */
- ldr r1,[r0] /* read the register */
- ldr r2,=L2CCAuxControl /* set the default bits */
- orr r1,r1,r2
- str r1, [r0] /* store the Aux Control Register */
-
- ldr r0,=L2CCTAGLatReg /* Load L2CC base address base + TAG Latency address */
- ldr r1,=L2CCTAGLatency /* set the latencies for the TAG*/
- str r1, [r0] /* store the TAG Latency register Register */
-
- ldr r0,=L2CCDataLatReg /* Load L2CC base address base + Data Latency address */
- ldr r1,=L2CCDataLatency /* set the latencies for the Data*/
- str r1, [r0] /* store the Data Latency register Register */
-
- ldr r0,=L2CCWay /* Load L2CC base address base + way register*/
- ldr r2, =0xFFFF
- str r2, [r0] /* force invalidate */
-
- ldr r0,=L2CCSync /* need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET */
- /* Load L2CC base address base + sync register*/
- /* poll for completion */
-Sync: ldr r1, [r0]
- cmp r1, #0
- bne Sync
-
- ldr r0,=L2CCIntRaw /* clear pending interrupts */
- ldr r1,[r0]
- ldr r0,=L2CCIntClear
- str r1,[r0]
-
- ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
- ldr r1,=SLCRUnlockKey /* set unlock key */
- str r1, [r0] /* Unlock SLCR */
-
- ldr r0,=SLCRL2cRamReg /* Load SLCR base address base + l2c Ram Control register */
- ldr r1,=SLCRL2cRamConfig /* set the configuration value */
- str r1, [r0] /* store the L2c Ram Control Register */
-
- ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
- ldr r1,=SLCRlockKey /* set lock key */
- str r1, [r0] /* lock SLCR */
-
- ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */
- ldr r1,[r0] /* read the register */
- mov r2, #L2CCControl /* set the enable bit */
- orr r1,r1,r2
- str r1, [r0] /* enable the L2 Caches */
-#endif
-
- mov r0, r0
- mrc p15, 0, r1, c1, c0, 2 /* read cp access control register (CACR) into r1 */
- orr r1, r1, #(0xf << 20) /* enable full access for p10 & p11 */
- mcr p15, 0, r1, c1, c0, 2 /* write back into CACR */
-
- /* enable vfp */
- fmrx r1, FPEXC /* read the exception register */
- orr r1,r1, #FPEXC_EN /* set VFP enable bit, leave the others in orig state */
- fmxr FPEXC, r1 /* write back the exception register */
-
- mrc p15,0,r0,c1,c0,0 /* flow prediction enable */
- orr r0, r0, #(0x01 << 11) /* #0x8000 */
- mcr p15,0,r0,c1,c0,0
-
- mrc p15,0,r0,c1,c0,1 /* read Auxiliary Control Register */
- orr r0, r0, #(0x1 << 2) /* enable Dside prefetch */
- orr r0, r0, #(0x1 << 1) /* enable L2 Prefetch hint */
- mcr p15,0,r0,c1,c0,1 /* write Auxiliary Control Register */
-
- mrs r0, cpsr /* get the current PSR */
- bic r0, r0, #0x100 /* enable asynchronous abort exception */
- msr cpsr_xsf, r0
-
-
- b _start /* jump to C startup code */
- and r0, r0, r0 /* no op */
-
-.Ldone: b .Ldone /* Paranoia: we should never get here */
-
-
-/*
- *************************************************************************
- *
- * invalidate_dcache - invalidate the entire d-cache by set/way
- *
- * Note: for Cortex-A9, there is no cp instruction for invalidating
- * the whole D-cache. Need to invalidate each line.
- *
- *************************************************************************
- */
-invalidate_dcache:
- mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */
- ands r3, r0, #0x7000000
- mov r3, r3, lsr #23 /* cache level value (naturally aligned) */
- beq finished
- mov r10, #0 /* start with level 0 */
-loop1:
- add r2, r10, r10, lsr #1 /* work out 3xcachelevel */
- mov r1, r0, lsr r2 /* bottom 3 bits are the Cache type for this level */
- and r1, r1, #7 /* get those 3 bits alone */
- cmp r1, #2
- blt skip /* no cache or only instruction cache at this level */
- mcr p15, 2, r10, c0, c0, 0 /* write the Cache Size selection register */
- isb /* isb to sync the change to the CacheSizeID reg */
- mrc p15, 1, r1, c0, c0, 0 /* reads current Cache Size ID register */
- and r2, r1, #7 /* extract the line length field */
- add r2, r2, #4 /* add 4 for the line length offset (log2 16 bytes) */
- ldr r4, =0x3ff
- ands r4, r4, r1, lsr #3 /* r4 is the max number on the way size (right aligned) */
- clz r5, r4 /* r5 is the bit position of the way size increment */
- ldr r7, =0x7fff
- ands r7, r7, r1, lsr #13 /* r7 is the max number of the index size (right aligned) */
-loop2:
- mov r9, r4 /* r9 working copy of the max way size (right aligned) */
-loop3:
- orr r11, r10, r9, lsl r5 /* factor in the way number and cache number into r11 */
- orr r11, r11, r7, lsl r2 /* factor in the index number */
- mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */
- subs r9, r9, #1 /* decrement the way number */
- bge loop3
- subs r7, r7, #1 /* decrement the index */
- bge loop2
-skip:
- add r10, r10, #2 /* increment the cache number */
- cmp r3, r10
- bgt loop1
-
-finished:
- mov r10, #0 /* switch back to cache level 0 */
- mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
- dsb
- isb
-
- bx lr
-
-.end
-/**
-* @} End of "addtogroup a9_boot_code".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c3/201cc2545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c3/201cc2545243001d18b399c1eb9b3628
deleted file mode 100644
index 171e00b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c3/201cc2545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1603 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xqspips.c
-* @addtogroup qspips_v3_9
-* @{
-*
-* Contains implements the interface functions of the XQspiPs driver.
-* See xqspips.h for a detailed description of the device and driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00 sdm 11/25/10 First release
-* 2.00a kka 07/25/12 Removed XQspiPs_GetWriteData API.
-* The XQspiPs_SetSlaveSelect has been modified to remove
-* the argument of the slave select as the QSPI controller
-* only supports one slave.
-* XQspiPs_GetSlaveSelect API has been removed
-* Added logic to XQspiPs_GetReadData to handle data
-* shift for normal data reads and instruction/status
-* reads differently based on the ShiftReadData flag.
-* Removed the selection for the following options:
-* Master mode (XQSPIPS_MASTER_OPTION) and
-* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
-* as the QSPI driver supports the Master mode
-* and Flash Interface mode and doesnot support
-* Slave mode or the legacy mode.
-* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
-* APIs so that the last argument (IsInst) specifying whether
-* it is instruction or data has been removed. The first byte
-* in the SendBufPtr argument of these APIs specify the
-* instruction to be sent to the Flash Device.
-* The XQspiPs_PolledTransfer function has been updated
-* to fill the data to fifo depth.
-* This version of the driver fixes CRs 670197/663787.
-* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
-* Created macros XQspiPs_IsManualStart and
-* XQspiPs_IsManualChipSelect.
-* Changed QSPI transfer logic for polled and interrupt
-* modes to be based on filled tx fifo count and receive
-* based on it. RXNEMPTY interrupt is not used.
-* Added assertions to XQspiPs_LqspiRead function.
-*
-* 2.02a hk 05/14/13 Added enable and disable to the XQspiPs_LqspiRead()
-* function
-* Added instructions for bank selection, die erase and
-* flag status register to the flash instruction table
-* Handling for instructions not in flash instruction
-* table added. Checking for Tx FIFO empty when switching from
-* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
-* byte count 3 (spansion), instruction size and TXD register
-* changed accordingly. CR# 712502 and 703869.
-* Added (#ifdef linear base address) in the Linear read function.
-* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to
-* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
-* XQspiPs_LqspiRead function. Fix for CR#718141
-*
-* 2.03a hk 09/05/13 Modified polled and interrupt transfers to make use of
-* thresholds. This is to improve performance.
-* Added RX and TX threshold reset to one in XQspiPs_Abort.
-* Added RX threshold reset(1) after transfer in polled and
-* interrupt transfers. Made changes to make sure threshold
-* change is done only when no transfer is in progress.
-* 3.1 hk 08/13/14 When writing to the configuration register, set/reset
-* required bits leaving reserved bits untouched. CR# 796813.
-* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
-* controller does not update FIFO status flags as expected
-* when thresholds are used.
-* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
-* to remove compilation warnings. CR# 868893.
-* 3.5 tjs 13/08/18 Fixed compilation warnings for ARMCC.
-* 3.6 akm 03/28/19 Fixed memory leak issue while reading from qspi.(CR#1016357)
-* 3.6 akm 04/15/19 Modified the mask in XQspiPs_GetReadData() API to retrieve
-* configuration register values of both the Flashes in dual
-* parellel connection.
-* 3.7 akm 11/19/19 Fixed Coverity unused value warning in XQspiPs_PolledTransfer()
-* and XQspiPs_Transfer() APIs.
-* 3.7 akm 03/19/20 Modified XQspiPs_PolledTransfer(), XQspiPs_Transfer() and
-* XQspiPs_InterruptHandler() APIs to fill TX FIFO with valid
-* data when RX buffer is not NULL.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xqspips.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef defines qspi flash instruction format
- */
-typedef struct {
- u8 OpCode; /**< Operational code of the instruction */
- u8 InstSize; /**< Size of the instruction including address bytes */
- u8 TxOffset; /**< Register address where instruction has to be
- written */
-} XQspiPsInstFormat;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define ARRAY_SIZE(Array) (sizeof(Array) / sizeof((Array)[0]))
-
-/************************** Function Prototypes ******************************/
-static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size);
-static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
- unsigned ByteCount);
-
-/************************** Variable Definitions *****************************/
-
-/*
- * List of all the QSPI instructions and its format
- */
-static XQspiPsInstFormat FlashInst[] = {
- { XQSPIPS_FLASH_OPCODE_WREN, 1, XQSPIPS_TXD_01_OFFSET },
- { XQSPIPS_FLASH_OPCODE_WRDS, 1, XQSPIPS_TXD_01_OFFSET },
- { XQSPIPS_FLASH_OPCODE_RDSR1, 2, XQSPIPS_TXD_10_OFFSET },
- { XQSPIPS_FLASH_OPCODE_RDSR2, 2, XQSPIPS_TXD_10_OFFSET },
- { XQSPIPS_FLASH_OPCODE_WRSR, 2, XQSPIPS_TXD_10_OFFSET },
- { XQSPIPS_FLASH_OPCODE_PP, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_SE, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_BE_32K, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_BE_4K, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_BE, 1, XQSPIPS_TXD_01_OFFSET },
- { XQSPIPS_FLASH_OPCODE_ERASE_SUS, 1, XQSPIPS_TXD_01_OFFSET },
- { XQSPIPS_FLASH_OPCODE_ERASE_RES, 1, XQSPIPS_TXD_01_OFFSET },
- { XQSPIPS_FLASH_OPCODE_RDID, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_NORM_READ, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_FAST_READ, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_DUAL_READ, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_QUAD_READ, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_DUAL_IO_READ, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_QUAD_IO_READ, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_BRWR, 2, XQSPIPS_TXD_10_OFFSET },
- { XQSPIPS_FLASH_OPCODE_BRRD, 2, XQSPIPS_TXD_10_OFFSET },
- { XQSPIPS_FLASH_OPCODE_EARWR, 2, XQSPIPS_TXD_10_OFFSET },
- { XQSPIPS_FLASH_OPCODE_EARRD, 2, XQSPIPS_TXD_10_OFFSET },
- { XQSPIPS_FLASH_OPCODE_DIE_ERASE, 4, XQSPIPS_TXD_00_OFFSET },
- { XQSPIPS_FLASH_OPCODE_READ_FLAG_SR, 2, XQSPIPS_TXD_10_OFFSET },
- { XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR, 1, XQSPIPS_TXD_01_OFFSET },
- /* Add all the instructions supported by the flash device */
-};
-
-/*****************************************************************************/
-/**
-*
-* Initializes a specific XQspiPs instance such that the driver is ready to use.
-*
-* The state of the device after initialization is:
-* - Master mode
-* - Active high clock polarity
-* - Clock phase 0
-* - Baud rate divisor 2
-* - Transfer width 32
-* - Master reference clock = pclk
-* - No chip select active
-* - Manual CS and Manual Start disabled
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param ConfigPtr is a reference to a structure containing information
-* about a specific QSPI device. This function initializes an
-* InstancePtr object for a specific device specified by the
-* contents of Config.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. The caller is responsible for keeping the address
-* mapping from EffectiveAddr to the device physical base address
-* unchanged once this function is invoked. Unexpected errors may
-* occur if the address mapping changes after this function is
-* called. If address translation is not used, use
-* ConfigPtr->Config.BaseAddress for this device.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_DEVICE_IS_STARTED if the device is already started.
-* It must be stopped to re-initialize.
-*
-* @note None.
-*
-******************************************************************************/
-int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *ConfigPtr,
- u32 EffectiveAddr)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
-
- /*
- * If the device is busy, disallow the initialize and return a status
- * indicating it is already started. This allows the user to stop the
- * device and re-initialize, but prevents a user from inadvertently
- * initializing. This assumes the busy flag is cleared at startup.
- */
- if (InstancePtr->IsBusy == TRUE) {
- return XST_DEVICE_IS_STARTED;
- }
-
- /*
- * Set some default values.
- */
- InstancePtr->IsBusy = FALSE;
-
- InstancePtr->Config.BaseAddress = EffectiveAddr;
- InstancePtr->StatusHandler = StubStatusHandler;
-
- InstancePtr->SendBufferPtr = NULL;
- InstancePtr->RecvBufferPtr = NULL;
- InstancePtr->RequestedBytes = 0;
- InstancePtr->RemainingBytes = 0;
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- InstancePtr->Config.ConnectionMode = ConfigPtr->ConnectionMode;
-
- /*
- * Reset the QSPI device to get it into its initial state. It is
- * expected that device configuration will take place after this
- * initialization is done, but before the device is started.
- */
- XQspiPs_Reset(InstancePtr);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Resets the QSPI device. Reset must only be called after the driver has been
-* initialized. Any data transfer that is in progress is aborted.
-*
-* The upper layer software is responsible for re-configuring (if necessary)
-* and restarting the QSPI device after the reset.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XQspiPs_Reset(XQspiPs *InstancePtr)
-{
- u32 ConfigReg;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Abort any transfer that is in progress
- */
- XQspiPs_Abort(InstancePtr);
-
- /*
- * Write default value to configuration register.
- * Do not modify reserved bits.
- */
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_RESET_MASK_SET;
- ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET,
- ConfigReg);
-}
-
-/*****************************************************************************/
-/**
-*
-* Aborts a transfer in progress by disabling the device and flush the RxFIFO.
-* The byte counts are cleared, the busy flag is cleared.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return None.
-*
-* @note
-*
-* This function does a read/modify/write of the config register. The user of
-* this function needs to take care of critical sections.
-*
-******************************************************************************/
-void XQspiPs_Abort(XQspiPs *InstancePtr)
-{
- u32 ConfigReg;
- u32 IsLock;
-
- XQspiPs_Disable(InstancePtr);
-
- /*
- * De-assert slave select lines.
- */
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
-
- /*
- * QSPI Software Reset
- */
- IsLock = XQspiPs_ReadReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCKSTA);
- if (IsLock) {
- XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_UNLOCK,
- SLCR_UNLOCK_MASK);
- }
- XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL,
- LQSPI_RST_CTRL_MASK);
- XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL, 0x0);
- if (IsLock) {
- XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCK,
- SLCR_LOCK_MASK);
- }
-
- /*
- * Set the RX and TX FIFO threshold to reset value (one)
- */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
-
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_TXWR_OFFSET, XQSPIPS_TXWR_RESET_VALUE);
-
- InstancePtr->RemainingBytes = 0;
- InstancePtr->RequestedBytes = 0;
- InstancePtr->IsBusy = FALSE;
-}
-
-/*****************************************************************************/
-/**
-*
-* Transfers specified data on the QSPI bus. Initiates bus communication and
-* sends/receives data to/from the selected QSPI slave. For every byte sent,
-* a byte is received.
-*
-* The caller has the option of providing two different buffers for send and
-* receive, or one buffer for both send and receive, or no buffer for receive.
-* The receive buffer must be at least as big as the send buffer to prevent
-* unwanted memory writes. This implies that the byte count passed in as an
-* argument must be the smaller of the two buffers if they differ in size.
-* Here are some sample usages:
-*
-* XQspiPs_Transfer(InstancePtr, SendBuf, RecvBuf, ByteCount)
-* The caller wishes to send and receive, and provides two different
-* buffers for send and receive.
-*
-* XQspiPs_Transfer(InstancePtr, SendBuf, NULL, ByteCount)
-* The caller wishes only to send and does not care about the received
-* data. The driver ignores the received data in this case.
-*
-* XQspiPs_Transfer(InstancePtr, SendBuf, SendBuf, ByteCount)
-* The caller wishes to send and receive, but provides the same buffer
-* for doing both. The driver sends the data and overwrites the send
-* buffer with received data as it transfers the data.
-*
-* XQspiPs_Transfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
-* The caller wishes to only receive and does not care about sending
-* data. In this case, the caller must still provide a send buffer, but
-* it can be the same as the receive buffer if the caller does not care
-* what it sends. The device must send N bytes of data if it wishes to
-* receive N bytes of data.
-*
-* Although this function takes entire buffers as arguments, the driver can only
-* transfer a limited number of bytes at a time, limited by the size of the
-* FIFO. A call to this function only starts the transfer, then subsequent
-* transfers of the data is performed by the interrupt service routine until
-* the entire buffer has been transferred. The status callback function is
-* called when the entire buffer has been sent/received.
-*
-* This function is non-blocking. The SetSlaveSelect function must be called
-* prior to this function.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param SendBufPtr is a pointer to a data buffer that needs to be
-* transmitted. This buffer must not be NULL.
-* @param RecvBufPtr is a pointer to a buffer for received data.
-* This argument can be NULL if do not care about receiving.
-* @param ByteCount contains the number of bytes to send/receive.
-* The number of bytes received always equals the number of bytes
-* sent.
-*
-* @return
-* - XST_SUCCESS if the buffers are successfully handed off to the
-* device for transfer.
-* - XST_DEVICE_BUSY indicates that a data transfer is already in
-* progress. This is determined by the driver.
-*
-* @note
-*
-* This function is not thread-safe. The higher layer software must ensure that
-* no two threads are transferring data on the QSPI bus at the same time.
-*
-******************************************************************************/
-s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
- u32 ByteCount)
-{
- u32 StatusReg;
- u32 ConfigReg;
- u8 Instruction;
- u32 Data;
- unsigned int Index;
- u8 TransCount = 0;
- XQspiPsInstFormat *CurrInst;
- XQspiPsInstFormat NewInst[2];
- u8 SwitchFlag = 0;
-
- CurrInst = &NewInst[0];
-
- /*
- * The RecvBufPtr argument can be null
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(SendBufPtr != NULL);
- Xil_AssertNonvoid(ByteCount > 0);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Check whether there is another transfer in progress. Not thread-safe.
- */
- if (InstancePtr->IsBusy) {
- return XST_DEVICE_BUSY;
- }
-
- /*
- * Set the busy flag, which will be cleared in the ISR when the
- * transfer is entirely done.
- */
- InstancePtr->IsBusy = TRUE;
-
- /*
- * Set up buffer pointers.
- */
- InstancePtr->SendBufferPtr = SendBufPtr;
- InstancePtr->RecvBufferPtr = RecvBufPtr;
-
- InstancePtr->RequestedBytes = ByteCount;
- InstancePtr->RemainingBytes = ByteCount;
-
- /*
- * The first byte with every chip-select assertion is always
- * expected to be an instruction for flash interface mode
- */
- Instruction = *InstancePtr->SendBufferPtr;
-
- for (Index = 0 ; Index < ARRAY_SIZE(FlashInst); Index++) {
- if (Instruction == FlashInst[Index].OpCode) {
- break;
- }
- }
-
- /*
- * Set the RX FIFO threshold
- */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT);
-
- /*
- * If the slave select is "Forced" or under manual control,
- * set the slave select now, before beginning the transfer.
- */
- if (XQspiPs_IsManualChipSelect(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET,
- ConfigReg);
- }
-
- /*
- * Enable the device.
- */
- XQspiPs_Enable(InstancePtr);
-
- /*
- * Clear all the interrupts.
- */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_SR_OFFSET,
- XQSPIPS_IXR_WR_TO_CLR_MASK);
-
- if (Index < ARRAY_SIZE(FlashInst)) {
- CurrInst = &FlashInst[Index];
- /*
- * Check for WRSR instruction which has different size for
- * Spansion (3 bytes) and Micron (2 bytes)
- */
- if ((CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) &&
- (ByteCount == 3)) {
- CurrInst->InstSize = 3;
- CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
- }
- }
-
- /*
- * If instruction not present in table
- */
- if (Index == ARRAY_SIZE(FlashInst)) {
- /*
- * Assign current instruction, size and TXD register to be used
- * The InstSize mentioned in case of instructions greater than
- * 4 bytes is not the actual size, but is indicative of
- * the TXD register used.
- * The remaining bytes of the instruction will be transmitted
- * through TXD0 below.
- */
- switch (ByteCount%4) {
- case XQSPIPS_SIZE_ONE:
- CurrInst->OpCode = Instruction;
- CurrInst->InstSize = XQSPIPS_SIZE_ONE;
- CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET;
- if (ByteCount > 4) {
- SwitchFlag = 1;
- }
- break;
- case XQSPIPS_SIZE_TWO:
- CurrInst->OpCode = Instruction;
- CurrInst->InstSize = XQSPIPS_SIZE_TWO;
- CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET;
- if (ByteCount > 4) {
- SwitchFlag = 1;
- }
- break;
- case XQSPIPS_SIZE_THREE:
- CurrInst->OpCode = Instruction;
- CurrInst->InstSize = XQSPIPS_SIZE_THREE;
- CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
- if (ByteCount > 4) {
- SwitchFlag = 1;
- }
- break;
- default:
- CurrInst->OpCode = Instruction;
- CurrInst->InstSize = XQSPIPS_SIZE_FOUR;
- CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET;
- break;
- }
- }
-
- /*
- * If the instruction size in not 4 bytes then the data received needs
- * to be shifted
- */
- if (CurrInst->InstSize != 4) {
- InstancePtr->ShiftReadData = 1;
- } else {
- InstancePtr->ShiftReadData = 0;
- }
-
- /* Get the complete command (flash inst + address/data) */
- Data = *((u32 *)InstancePtr->SendBufferPtr);
- InstancePtr->SendBufferPtr += CurrInst->InstSize;
- InstancePtr->RemainingBytes -= CurrInst->InstSize;
- if (InstancePtr->RemainingBytes < 0) {
- InstancePtr->RemainingBytes = 0;
- }
-
- /* Write the command to the FIFO */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- CurrInst->TxOffset, Data);
- TransCount++;
-
- /*
- * If switching from TXD1/2/3 to TXD0, then start transfer and
- * check for FIFO empty
- */
- if (SwitchFlag == 1) {
- /*
- * If, in Manual Start mode, start the transfer.
- */
- if (XQspiPs_IsManualStart(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(
- InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
- }
- /*
- * Wait for the transfer to finish by polling Tx fifo status.
- */
- do {
- StatusReg = XQspiPs_ReadReg(
- InstancePtr->Config.BaseAddress,
- XQSPIPS_SR_OFFSET);
- } while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0);
-
- }
-
- /*
- * Fill the Tx FIFO with as many bytes as it takes (or as many as
- * we have to send).
- */
- while ((InstancePtr->RemainingBytes > 0) &&
- (TransCount < XQSPIPS_FIFO_DEPTH)) {
- /*
- * In case of Write fill the Tx FIFO with data to be transmitted.
- * In case of Read fill the TX FIFO with first 4bytes(1Byte Command + 3Byte Address)
- * of data from TX Buffer and the remaining bytes(i.e., RequestedBytes - 4)
- * with DUMMY.
- */
- if(InstancePtr->RecvBufferPtr &&
- ((InstancePtr->RequestedBytes - InstancePtr->RemainingBytes) > 4)) {
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_TXD_00_OFFSET, XQSPIPS_DUMMY_TX_DATA);
- } else {
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_TXD_00_OFFSET,
- *((u32 *)InstancePtr->SendBufferPtr));
-
- InstancePtr->SendBufferPtr += 4;
- }
- InstancePtr->RemainingBytes -= 4;
- if (InstancePtr->RemainingBytes < 0) {
- InstancePtr->RemainingBytes = 0;
- }
- TransCount++;
- }
-
- /*
- * Enable QSPI interrupts (connecting to the interrupt controller and
- * enabling interrupts should have been done by the caller).
- */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_IER_OFFSET, XQSPIPS_IXR_RXNEMPTY_MASK |
- XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXOVR_MASK |
- XQSPIPS_IXR_TXUF_MASK);
-
- /*
- * If, in Manual Start mode, Start the transfer.
- */
- if (XQspiPs_IsManualStart(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-* Transfers specified data on the QSPI bus in polled mode.
-*
-* The caller has the option of providing two different buffers for send and
-* receive, or one buffer for both send and receive, or no buffer for receive.
-* The receive buffer must be at least as big as the send buffer to prevent
-* unwanted memory writes. This implies that the byte count passed in as an
-* argument must be the smaller of the two buffers if they differ in size.
-* Here are some sample usages:
-*
-* XQspiPs_PolledTransfer(InstancePtr, SendBuf, RecvBuf, ByteCount)
-* The caller wishes to send and receive, and provides two different
-* buffers for send and receive.
-*
-* XQspiPs_PolledTransfer(InstancePtr, SendBuf, NULL, ByteCount)
-* The caller wishes only to send and does not care about the received
-* data. The driver ignores the received data in this case.
-*
-* XQspiPs_PolledTransfer(InstancePtr, SendBuf, SendBuf, ByteCount)
-* The caller wishes to send and receive, but provides the same buffer
-* for doing both. The driver sends the data and overwrites the send
-* buffer with received data as it transfers the data.
-*
-* XQspiPs_PolledTransfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
-* The caller wishes to only receive and does not care about sending
-* data. In this case, the caller must still provide a send buffer, but
-* it can be the same as the receive buffer if the caller does not care
-* what it sends. The device must send N bytes of data if it wishes to
-* receive N bytes of data.
-*
-*
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param SendBufPtr is a pointer to a data buffer that needs to be
-* transmitted. This buffer must not be NULL.
-* @param RecvBufPtr is a pointer to a buffer for received data.
-* This argument can be NULL if do not care about receiving.
-* @param ByteCount contains the number of bytes to send/receive.
-* The number of bytes received always equals the number of bytes
-* sent.
-* @return
-* - XST_SUCCESS if the buffers are successfully handed off to the
-* device for transfer.
-* - XST_DEVICE_BUSY indicates that a data transfer is already in
-* progress. This is determined by the driver.
-*
-* @note
-*
-* This function is not thread-safe. The higher layer software must ensure that
-* no two threads are transferring data on the QSPI bus at the same time.
-*
-******************************************************************************/
-s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
- u8 *RecvBufPtr, u32 ByteCount)
-{
- u32 StatusReg;
- u32 ConfigReg;
- u8 Instruction;
- u32 Data;
- u8 TransCount;
- unsigned int Index;
- XQspiPsInstFormat *CurrInst;
- XQspiPsInstFormat NewInst[2];
- u8 SwitchFlag = 0;
- u8 IsManualStart = FALSE;
- u32 RxCount = 0;
-
- CurrInst = &NewInst[0];
- /*
- * The RecvBufPtr argument can be NULL.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(SendBufPtr != NULL);
- Xil_AssertNonvoid(ByteCount > 0);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Check whether there is another transfer in progress. Not thread-safe.
- */
- if (InstancePtr->IsBusy) {
- return XST_DEVICE_BUSY;
- }
-
- /*
- * Set the busy flag, which will be cleared when the transfer is
- * entirely done.
- */
- InstancePtr->IsBusy = TRUE;
-
- /*
- * Set up buffer pointers.
- */
- InstancePtr->SendBufferPtr = SendBufPtr;
- InstancePtr->RecvBufferPtr = RecvBufPtr;
-
- InstancePtr->RequestedBytes = ByteCount;
- InstancePtr->RemainingBytes = ByteCount;
-
- /*
- * The first byte with every chip-select assertion is always
- * expected to be an instruction for flash interface mode
- */
- Instruction = *InstancePtr->SendBufferPtr;
-
- for (Index = 0 ; Index < ARRAY_SIZE(FlashInst); Index++) {
- if (Instruction == FlashInst[Index].OpCode) {
- break;
- }
- }
-
- /*
- * Set the RX FIFO threshold
- */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT);
-
- /*
- * If the slave select is "Forced" or under manual control,
- * set the slave select now, before beginning the transfer.
- */
- if (XQspiPs_IsManualChipSelect(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET,
- ConfigReg);
- }
-
- /*
- * Enable the device.
- */
- XQspiPs_Enable(InstancePtr);
-
- if (Index < ARRAY_SIZE(FlashInst)) {
-
- CurrInst = &FlashInst[Index];
- /*
- * Check for WRSR instruction which has different size for
- * Spansion (3 bytes) and Micron (2 bytes)
- */
- if ((CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) &&
- (ByteCount == 3)) {
- CurrInst->InstSize = 3;
- CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
- }
- }
-
- /*
- * If instruction not present in table
- */
- if (Index == ARRAY_SIZE(FlashInst)) {
- /*
- * Assign current instruction, size and TXD register to be used.
- * The InstSize mentioned in case of instructions greater than 4 bytes
- * is not the actual size, but is indicative of the TXD register used.
- * The remaining bytes of the instruction will be transmitted
- * through TXD0 below.
- */
- switch (ByteCount % 4) {
- case XQSPIPS_SIZE_ONE:
- CurrInst->OpCode = Instruction;
- CurrInst->InstSize = XQSPIPS_SIZE_ONE;
- CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET;
- if (ByteCount > 4) {
- SwitchFlag = 1;
- }
- break;
- case XQSPIPS_SIZE_TWO:
- CurrInst->OpCode = Instruction;
- CurrInst->InstSize = XQSPIPS_SIZE_TWO;
- CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET;
- if (ByteCount > 4) {
- SwitchFlag = 1;
- }
- break;
- case XQSPIPS_SIZE_THREE:
- CurrInst->OpCode = Instruction;
- CurrInst->InstSize = XQSPIPS_SIZE_THREE;
- CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
- if (ByteCount > 4) {
- SwitchFlag = 1;
- }
- break;
- default:
- CurrInst->OpCode = Instruction;
- CurrInst->InstSize = XQSPIPS_SIZE_FOUR;
- CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET;
- break;
- }
- }
-
- /*
- * If the instruction size in not 4 bytes then the data received needs
- * to be shifted
- */
- if (CurrInst->InstSize != 4) {
- InstancePtr->ShiftReadData = 1;
- } else {
- InstancePtr->ShiftReadData = 0;
- }
- TransCount = 0;
- /* Get the complete command (flash inst + address/data) */
- Data = *((u32 *)InstancePtr->SendBufferPtr);
- InstancePtr->SendBufferPtr += CurrInst->InstSize;
- InstancePtr->RemainingBytes -= CurrInst->InstSize;
- if (InstancePtr->RemainingBytes < 0) {
- InstancePtr->RemainingBytes = 0;
- }
-
- /* Write the command to the FIFO */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- CurrInst->TxOffset, Data);
- ++TransCount;
-
- /*
- * If switching from TXD1/2/3 to TXD0, then start transfer and
- * check for FIFO empty
- */
- if (SwitchFlag == 1) {
- /*
- * If, in Manual Start mode, start the transfer.
- */
- if (XQspiPs_IsManualStart(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(
- InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
- }
- /*
- * Wait for the transfer to finish by polling Tx fifo status.
- */
- do {
- StatusReg = XQspiPs_ReadReg(
- InstancePtr->Config.BaseAddress,
- XQSPIPS_SR_OFFSET);
- } while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0);
-
- }
-
- /*
- * Check if manual start is selected and store it in a
- * local variable for reference. This is to avoid reading
- * the config register every time.
- */
- IsManualStart = XQspiPs_IsManualStart(InstancePtr);
- /*
- * Fill the DTR/FIFO with as many bytes as it will take (or as
- * many as we have to send).
- */
- while ((InstancePtr->RemainingBytes > 0) &&
- (TransCount < XQSPIPS_FIFO_DEPTH)) {
- /*
- * In case of Write fill the Tx FIFO with data to be transmitted.
- * In case of Read fill the TX FIFO with first 4bytes(1Byte Command + 3Byte Address)
- * of data from TX Buffer and the remaining bytes(i.e., RequestedBytes - 4)
- * with DUMMY.
- */
- if(InstancePtr->RecvBufferPtr &&
- ((InstancePtr->RequestedBytes - InstancePtr->RemainingBytes) > 4)) {
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_TXD_00_OFFSET, XQSPIPS_DUMMY_TX_DATA);
- } else {
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_TXD_00_OFFSET,
- *((u32 *)InstancePtr->SendBufferPtr));
-
- InstancePtr->SendBufferPtr += 4;
- }
- InstancePtr->RemainingBytes -= 4;
- if (InstancePtr->RemainingBytes < 0) {
- InstancePtr->RemainingBytes = 0;
- }
- ++TransCount;
- }
-
- while ((InstancePtr->RemainingBytes > 0) ||
- (InstancePtr->RequestedBytes > 0)) {
-
- /*
- * Fill the TX FIFO with RX threshold no. of entries (or as
- * many as we have to send, in case that's less).
- */
- while ((InstancePtr->RemainingBytes > 0) &&
- (TransCount < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
- /*
- * In case of Write fill the Tx FIFO with data to be transmitted.
- * In case of Read fill the TX FIFO with first 4bytes(1Byte Command + 3Byte Address)
- * of data from TX Buffer and the remaining bytes(i.e., RequestedBytes - 4)
- * with DUMMY.
- */
- if(InstancePtr->RecvBufferPtr &&
- ((InstancePtr->RequestedBytes - InstancePtr->RemainingBytes) > 4)) {
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_TXD_00_OFFSET, XQSPIPS_DUMMY_TX_DATA);
- } else {
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_TXD_00_OFFSET,
- *((u32 *)InstancePtr->SendBufferPtr));
-
- InstancePtr->SendBufferPtr += 4;
- }
- InstancePtr->RemainingBytes -= 4;
- if (InstancePtr->RemainingBytes < 0) {
- InstancePtr->RemainingBytes = 0;
- }
- ++TransCount;
- }
-
- /*
- * If, in Manual Start mode, start the transfer.
- */
- if (IsManualStart == TRUE) {
- ConfigReg = XQspiPs_ReadReg(
- InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
- }
-
- /*
- * Reset TransCount - this is only used to fill TX FIFO
- * in the above loop;
- * RxCount is used to keep track of data received
- */
- TransCount = 0;
-
- /*
- * Wait for RX FIFO to reach threshold (or)
- * TX FIFO to become empty.
- * The latter check is required for
- * small transfers (<32 words) and
- * when the last chunk in a large data transfer is < 32 words.
- */
-
- do {
- StatusReg = XQspiPs_ReadReg(
- InstancePtr->Config.BaseAddress,
- XQSPIPS_SR_OFFSET);
- } while (((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0) &&
- ((StatusReg & XQSPIPS_IXR_RXNEMPTY_MASK) == 0));
-
- /*
- * A transmit has just completed. Process received data
- * and check for more data to transmit.
- * First get the data received as a result of the
- * transmit that just completed. Receive data based on the
- * count obtained while filling tx fifo. Always get
- * the received data, but only fill the receive
- * buffer if it points to something (the upper layer
- * software may not care to receive data).
- */
- while ((InstancePtr->RequestedBytes > 0) &&
- (RxCount < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
- u32 Data;
-
- RxCount++;
-
- if (InstancePtr->RecvBufferPtr != NULL) {
- if (InstancePtr->RequestedBytes < 4) {
- Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_RXD_OFFSET);
- XQspiPs_GetReadData(InstancePtr, Data,
- InstancePtr->RequestedBytes);
- } else {
- (*(u32 *)InstancePtr->RecvBufferPtr) =
- XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_RXD_OFFSET);
- InstancePtr->RecvBufferPtr += 4;
- InstancePtr->RequestedBytes -= 4;
- if (InstancePtr->RequestedBytes < 0) {
- InstancePtr->RequestedBytes = 0;
- }
- }
- } else {
- Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_RXD_OFFSET);
- InstancePtr->RequestedBytes -= 4;
- }
- }
- RxCount = 0;
- }
-
- /*
- * If the Slave select lines are being manually controlled, disable
- * them because the transfer is complete.
- */
- if (XQspiPs_IsManualChipSelect(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
- }
-
- /*
- * Clear the busy flag.
- */
- InstancePtr->IsBusy = FALSE;
-
- /*
- * Disable the device.
- */
- XQspiPs_Disable(InstancePtr);
-
- /*
- * Reset the RX FIFO threshold to one
- */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Read the flash in Linear QSPI mode.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RecvBufPtr is a pointer to a buffer for received data.
-* @param Address is the starting address within the flash from
-* from where data needs to be read.
-* @param ByteCount contains the number of bytes to receive.
-*
-* @return
-* - XST_SUCCESS if read is performed
-* - XST_FAILURE if Linear mode is not set
-*
-* @note None.
-*
-*
-******************************************************************************/
-int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
- u32 Address, unsigned ByteCount)
-{
- int Status = (int)XST_SUCCESS;
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(RecvBufPtr != NULL);
- Xil_AssertNonvoid(ByteCount > 0);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-#ifndef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
-#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
-#endif
- /*
- * Enable the controller
- */
- XQspiPs_Enable(InstancePtr);
-
- if (XQspiPs_GetLqspiConfigReg(InstancePtr) &
- XQSPIPS_LQSPI_CR_LINEAR_MASK) {
- memcpy((void *)RecvBufPtr,
- (const void *)(XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR +
- Address),
- (size_t)ByteCount);
- Status = (int)XST_SUCCESS;
- } else {
- Status = (int)XST_FAILURE;
- }
-
- /*
- * Disable the controller
- */
- XQspiPs_Disable(InstancePtr);
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* Selects the slave with which the master communicates.
-*
-* The user is not allowed to select the slave while a transfer is in progress.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return
-* - XST_SUCCESS if the slave is selected or deselected
-* successfully.
-* - XST_DEVICE_BUSY if a transfer is in progress, slave cannot be
-* changed.
-*
-* @note
-*
-* This function only sets the slave which will be selected when a transfer
-* occurs. The slave is not selected when the QSPI is idle.
-*
-******************************************************************************/
-int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr)
-{
- u32 ConfigReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Do not allow the slave select to change while a transfer is in
- * progress. Not thread-safe.
- */
- if (InstancePtr->IsBusy) {
- return XST_DEVICE_BUSY;
- }
-
- /*
- * Select the slave
- */
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* Sets the status callback function, the status handler, which the driver
-* calls when it encounters conditions that should be reported to upper
-* layer software. The handler executes in an interrupt context, so it must
-* minimize the amount of processing performed. One of the following status
-* events is passed to the status handler.
-*
-*
-*
-* XST_SPI_TRANSFER_DONE The requested data transfer is done
-*
-* XST_SPI_TRANSMIT_UNDERRUN As a slave device, the master clocked data
-* but there were none available in the transmit
-* register/FIFO. This typically means the slave
-* application did not issue a transfer request
-* fast enough, or the processor/driver could not
-* fill the transmit register/FIFO fast enough.
-*
-* XST_SPI_RECEIVE_OVERRUN The QSPI device lost data. Data was received
-* but the receive data register/FIFO was full.
-*
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param CallBackRef is the upper layer callback reference passed back
-* when the callback function is invoked.
-* @param FuncPtr is the pointer to the callback function.
-*
-* @return None.
-*
-* @note
-*
-* The handler is called within interrupt context, so it should do its work
-* quickly and queue potentially time-consuming work to a task-level thread.
-*
-******************************************************************************/
-void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
- XQspiPs_StatusHandler FuncPtr)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(FuncPtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- InstancePtr->StatusHandler = FuncPtr;
- InstancePtr->StatusRef = CallBackRef;
-}
-
-/*****************************************************************************/
-/**
-*
-* This is a stub for the status callback. The stub is here in case the upper
-* layers forget to set the handler.
-*
-* @param CallBackRef is a pointer to the upper layer callback reference
-* @param StatusEvent is the event that just occurred.
-* @param ByteCount is the number of bytes transferred up until the event
-* occurred.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
- unsigned ByteCount)
-{
- (void) CallBackRef;
- (void) StatusEvent;
- (void) ByteCount;
-
- Xil_AssertVoidAlways();
-}
-
-/*****************************************************************************/
-/**
-*
-* The interrupt handler for QSPI interrupts. This function must be connected
-* by the user to an interrupt controller.
-*
-* The interrupts that are handled are:
-*
-*
-* - Data Transmit Register (FIFO) Empty. This interrupt is generated when the
-* transmit register or FIFO is empty. The driver uses this interrupt during a
-* transmission to continually send/receive data until the transfer is done.
-*
-* - Data Transmit Register (FIFO) Underflow. This interrupt is generated when
-* the QSPI device, when configured as a slave, attempts to read an empty
-* DTR/FIFO. An empty DTR/FIFO usually means that software is not giving the
-* device data in a timely manner. No action is taken by the driver other than
-* to inform the upper layer software of the error.
-*
-* - Data Receive Register (FIFO) Overflow. This interrupt is generated when the
-* QSPI device attempts to write a received byte to an already full DRR/FIFO.
-* A full DRR/FIFO usually means software is not emptying the data in a timely
-* manner. No action is taken by the driver other than to inform the upper
-* layer software of the error.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return None.
-*
-* @note
-*
-* The slave select register is being set to deselect the slave when a transfer
-* is complete.
-*
-******************************************************************************/
-void XQspiPs_InterruptHandler(void *InstancePtr)
-{
- XQspiPs *QspiPtr = (XQspiPs *)InstancePtr;
- u32 IntrStatus;
- u32 ConfigReg;
- u32 Data;
- u32 TransCount;
- u32 Count = 0;
- unsigned BytesDone; /* Number of bytes done so far. */
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(QspiPtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Immediately clear the interrupts in case the ISR causes another
- * interrupt to be generated. If we clear at the end of the ISR,
- * we may miss newly generated interrupts. This occurs because we
- * transmit from within the ISR, which could potentially cause another
- * TX_EMPTY interrupt.
- */
- IntrStatus = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_SR_OFFSET);
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_SR_OFFSET,
- (IntrStatus & XQSPIPS_IXR_WR_TO_CLR_MASK));
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_IDR_OFFSET,
- XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXNEMPTY_MASK |
- XQSPIPS_IXR_RXOVR_MASK | XQSPIPS_IXR_TXUF_MASK);
-
- if ((IntrStatus & XQSPIPS_IXR_TXOW_MASK) ||
- (IntrStatus & XQSPIPS_IXR_RXNEMPTY_MASK)) {
-
- /*
- * Rx FIFO has just reached threshold no. of entries.
- * Read threshold no. of entries from RX FIFO
- * Another possibility of entering this loop is when
- * the last byte has been transmitted and TX FIFO is empty,
- * in which case, read all the data from RX FIFO.
- * Always get the received data, but only fill the
- * receive buffer if it is not null (it can be null when
- * the device does not care to receive data).
- */
- TransCount = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
- if (TransCount % 4) {
- TransCount = TransCount/4 + 1;
- } else {
- TransCount = TransCount/4;
- }
-
- while ((Count < TransCount) &&
- (Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
-
- if (QspiPtr->RecvBufferPtr != NULL) {
- if (QspiPtr->RequestedBytes < 4) {
- Data = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_RXD_OFFSET);
- XQspiPs_GetReadData(QspiPtr, Data,
- QspiPtr->RequestedBytes);
- } else {
- (*(u32 *)QspiPtr->RecvBufferPtr) =
- XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_RXD_OFFSET);
- QspiPtr->RecvBufferPtr += 4;
- QspiPtr->RequestedBytes -= 4;
- if (QspiPtr->RequestedBytes < 0) {
- QspiPtr->RequestedBytes = 0;
- }
- }
- } else {
- XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_RXD_OFFSET);
- QspiPtr->RequestedBytes -= 4;
- if (QspiPtr->RequestedBytes < 0) {
- QspiPtr->RequestedBytes = 0;
- }
-
- }
- Count++;
- }
- Count = 0;
- /*
- * Interrupt asserted as TX_OW got asserted
- * See if there is more data to send.
- * Fill TX FIFO with RX threshold no. of entries or
- * remaining entries (in case that is less than threshold)
- */
- while ((QspiPtr->RemainingBytes > 0) &&
- (Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
- /*
- * Send more data.
- * In case of Write fill the Tx FIFO with data to be transmitted.
- * In case of Read fill the TX FIFO with first 4bytes(1Byte Command + 3Byte Address)
- * of data from TX Buffer and the remaining bytes(i.e., RequestedBytes - 4)
- * with DUMMY.
- */
- if(QspiPtr->RecvBufferPtr &&
- ((QspiPtr->RequestedBytes - QspiPtr->RemainingBytes) > 4)) {
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_TXD_00_OFFSET, XQSPIPS_DUMMY_TX_DATA);
- } else {
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_TXD_00_OFFSET,
- *((u32 *)QspiPtr->SendBufferPtr));
-
- QspiPtr->SendBufferPtr += 4;
- }
- QspiPtr->RemainingBytes -= 4;
- if (QspiPtr->RemainingBytes < 0) {
- QspiPtr->RemainingBytes = 0;
- }
-
- Count++;
- }
-
- if ((QspiPtr->RemainingBytes == 0) &&
- (QspiPtr->RequestedBytes == 0)) {
- /*
- * No more data to send. Disable the interrupt
- * and inform the upper layer software that the
- * transfer is done. The interrupt will be re-enabled
- * when another transfer is initiated.
- */
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_IDR_OFFSET,
- XQSPIPS_IXR_RXNEMPTY_MASK |
- XQSPIPS_IXR_TXOW_MASK |
- XQSPIPS_IXR_RXOVR_MASK |
- XQSPIPS_IXR_TXUF_MASK);
-
- /*
- * If the Slave select is being manually controlled,
- * disable it because the transfer is complete.
- */
- if (XQspiPs_IsManualChipSelect(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(
- QspiPtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET,
- ConfigReg);
- }
-
- /*
- * Clear the busy flag.
- */
- QspiPtr->IsBusy = FALSE;
-
- /*
- * Disable the device.
- */
- XQspiPs_Disable(QspiPtr);
-
- /*
- * Reset the RX FIFO threshold to one
- */
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
-
- QspiPtr->StatusHandler(QspiPtr->StatusRef,
- XST_SPI_TRANSFER_DONE,
- QspiPtr->RequestedBytes);
- } else {
- /*
- * Enable the TXOW interrupt.
- */
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_IER_OFFSET,
- XQSPIPS_IXR_RXNEMPTY_MASK |
- XQSPIPS_IXR_TXOW_MASK |
- XQSPIPS_IXR_RXOVR_MASK |
- XQSPIPS_IXR_TXUF_MASK);
- /*
- * If, in Manual Start mode, start the transfer.
- */
- if (XQspiPs_IsManualStart(QspiPtr)) {
- ConfigReg = XQspiPs_ReadReg(
- QspiPtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
- XQspiPs_WriteReg(
- QspiPtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
- }
- }
- }
-
- /*
- * Check for overflow and underflow errors.
- */
- if (IntrStatus & XQSPIPS_IXR_RXOVR_MASK) {
- BytesDone = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
- QspiPtr->IsBusy = FALSE;
-
- /*
- * If the Slave select lines is being manually controlled,
- * disable it because the transfer is complete.
- */
- if (XQspiPs_IsManualChipSelect(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(
- QspiPtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
- }
-
- /*
- * Disable the device.
- */
- XQspiPs_Disable(QspiPtr);
-
- /*
- * Reset the RX FIFO threshold to one
- */
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
-
- QspiPtr->StatusHandler(QspiPtr->StatusRef,
- XST_SPI_RECEIVE_OVERRUN, BytesDone);
- }
-
- if (IntrStatus & XQSPIPS_IXR_TXUF_MASK) {
- BytesDone = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
-
- QspiPtr->IsBusy = FALSE;
- /*
- * If the Slave select lines is being manually controlled,
- * disable it because the transfer is complete.
- */
- if (XQspiPs_IsManualChipSelect(InstancePtr)) {
- ConfigReg = XQspiPs_ReadReg(
- QspiPtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET, ConfigReg);
- }
-
- /*
- * Disable the device.
- */
- XQspiPs_Disable(QspiPtr);
-
- /*
- * Reset the RX FIFO threshold to one
- */
- XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
- XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
-
- QspiPtr->StatusHandler(QspiPtr->StatusRef,
- XST_SPI_TRANSMIT_UNDERRUN, BytesDone);
- }
-}
-
-
-/*****************************************************************************/
-/**
-*
-* Copies data from Data to the Receive buffer.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param Data is the data which needs to be copied to the Rx buffer.
-* @param Size is the number of bytes to be copied to the Receive buffer.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size)
-{
- u8 DataByte3;
-
- if (InstancePtr->RecvBufferPtr) {
- switch (Size) {
- case 1:
- if (InstancePtr->ShiftReadData == 1) {
- *((u8 *)InstancePtr->RecvBufferPtr) =
- ((Data & 0xFF000000) >> 24);
- } else {
- *((u8 *)InstancePtr->RecvBufferPtr) =
- (Data & 0xFF);
- }
- InstancePtr->RecvBufferPtr += 1;
- break;
- case 2:
- if (InstancePtr->ShiftReadData == 1) {
- *((u16 *)InstancePtr->RecvBufferPtr) =
- ((Data >> 16) & 0xFF00) |
- ((Data >> 8) & 0xFF);
- } else {
- *((u16 *)InstancePtr->RecvBufferPtr) =
- (Data & 0xFFFF);
- }
- InstancePtr->RecvBufferPtr += 2;
- break;
- case 3:
- if (InstancePtr->ShiftReadData == 1) {
- *((u16 *)InstancePtr->RecvBufferPtr) =
- ((Data & 0x00FFFF00) >> 8);
- InstancePtr->RecvBufferPtr += 2;
- DataByte3 = ((Data & 0xFF000000) >> 24);
- *((u8 *)InstancePtr->RecvBufferPtr) = DataByte3;
- } else {
- *((u16 *)InstancePtr->RecvBufferPtr) =
- (Data & 0xFFFF);
- InstancePtr->RecvBufferPtr += 2;
- DataByte3 = ((Data & 0x00FF0000) >> 16);
- *((u8 *)InstancePtr->RecvBufferPtr) = DataByte3;
- }
- InstancePtr->RecvBufferPtr += 1;
- break;
- default:
- /* This will never execute */
- break;
- }
- }
- InstancePtr->ShiftReadData = 0;
- InstancePtr->RequestedBytes -= Size;
- if (InstancePtr->RequestedBytes < 0) {
- InstancePtr->RequestedBytes = 0;
- }
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c3/30767b545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c3/30767b545243001d18b399c1eb9b3628
deleted file mode 100644
index 3c23a5f..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c3/30767b545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,25 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xcpu_cortexa9.h
-* @addtogroup cpu_cortexa9_v2_11
-* @{
-* @details
-*
-* dummy file
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------------
-* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID
-* parameter of cpu_cortexa9 in xparameters.h
-# 2.7 mus 07/03/18 Updated tcl to not to add default flags forcefully into
-# extra compiler flags. Now, user can remove default flags
-# from extra compiler flags. It fixes CR#998768.
-******************************************************************************/
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c3/60447c555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c3/60447c555243001d18b399c1eb9b3628
deleted file mode 100644
index a06f161..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c3/60447c555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,185 +0,0 @@
-/*******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-*******************************************************************************/
-
-
-#ifndef __XIOU_SECURE_SLCR_H__
-#define __XIOU_SECURE_SLCR_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *@cond nocomments
- */
-
-/**
- * XiouSecureSlcr Base Address
- */
-#define XIOU_SECURE_SLCR_BASEADDR 0xFF240000UL
-
-/**
- * Register: XiouSecSlcrAxiWprtcn
- */
-#define XIOU_SEC_SLCR_AXI_WPRTCN ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000000UL )
-#define XIOU_SEC_SLCR_AXI_WPRTCN_RSTVAL 0x00000000UL
-
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_SHIFT 25UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_WIDTH 3UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_MASK 0x0e000000UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_DEFVAL 0x0UL
-
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_SHIFT 22UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_WIDTH 3UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_MASK 0x01c00000UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_DEFVAL 0x0UL
-
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT 19UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH 3UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK 0x00380000UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL 0x0UL
-
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT 16UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH 3UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK 0x00070000UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL 0x0UL
-
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 9UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000e00UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL
-
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 6UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x000001c0UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL
-
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 3UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000038UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL
-
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 0UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000007UL
-#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL
-
-/**
- * Register: XiouSecSlcrAxiRprtcn
- */
-#define XIOU_SEC_SLCR_AXI_RPRTCN ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000004UL )
-#define XIOU_SEC_SLCR_AXI_RPRTCN_RSTVAL 0x00000000UL
-
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_SHIFT 22UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_WIDTH 3UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_MASK 0x01c00000UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_DEFVAL 0x0UL
-
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT 19UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH 3UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK 0x00380000UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL 0x0UL
-
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT 16UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH 3UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK 0x00070000UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL 0x0UL
-
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 9UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000e00UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL
-
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 6UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x000001c0UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL
-
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 3UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000038UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL
-
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 0UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000007UL
-#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL
-
-/**
- * Register: XiouSecSlcrCtrl
- */
-#define XIOU_SEC_SLCR_CTRL ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000040UL )
-#define XIOU_SEC_SLCR_CTRL_RSTVAL 0x00000000UL
-
-#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_SHIFT 0UL
-#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_WIDTH 1UL
-#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL
-#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL
-
-/**
- * Register: XiouSecSlcrIsr
- */
-#define XIOU_SEC_SLCR_ISR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000044UL )
-#define XIOU_SEC_SLCR_ISR_RSTVAL 0x00000000UL
-
-#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL
-#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL
-#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL
-#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL
-
-/**
- * Register: XiouSecSlcrImr
- */
-#define XIOU_SEC_SLCR_IMR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000048UL )
-#define XIOU_SEC_SLCR_IMR_RSTVAL 0x00000001UL
-
-#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL
-#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL
-#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL
-#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL
-
-/**
- * Register: XiouSecSlcrIer
- */
-#define XIOU_SEC_SLCR_IER ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x0000004CUL )
-#define XIOU_SEC_SLCR_IER_RSTVAL 0x00000000UL
-
-#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL
-#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL
-#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL
-#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL
-
-/**
- * Register: XiouSecSlcrIdr
- */
-#define XIOU_SEC_SLCR_IDR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000050UL )
-#define XIOU_SEC_SLCR_IDR_RSTVAL 0x00000000UL
-
-#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL
-#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL
-#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL
-#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL
-
-/**
- * Register: XiouSecSlcrItr
- */
-#define XIOU_SEC_SLCR_ITR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000054UL )
-#define XIOU_SEC_SLCR_ITR_RSTVAL 0x00000000UL
-
-#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL
-#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL
-#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL
-#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL
-
-/**
- *@endcond
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XIOU_SECURE_SLCR_H__ */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c3/61a62a595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c3/61a62a595243001d18b399c1eb9b3628
deleted file mode 100644
index 50df3c5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c3/61a62a595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,128 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_clocking.c
-*
-* The xil_clocking.c file contains clocking related functions and macros.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 7.2 sd 02/06/20 First release of clocking
-* 7.2 sd 03/20/20 Added checking for isolation case
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 5.5 pkp 04/13/16 Added XTime_StartTimer API to start the global timer
-* counter if it is disabled. Also XTime_GetTime calls
-* this API to ensure the global timer counter is enabled
-* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
-* displaying same warnings multiple times. It fixes CR#1090562.
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "xtime_l.h"
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER)
-#pragma message ("For the sleep routines, Global timer is being used")
-#endif
-/****************************************************************************/
-/**
-* @brief Start the 64-bit physical timer counter.
-*
-* @return None.
-*
-* @note The timer is initialized only if it is disabled. If the timer is
-* already running this function does not perform any operation.
-*
-****************************************************************************/
-void XTime_StartTimer(void)
-{
- /* Enable the counter only if it is disable */
- if(((Xil_In32(XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET)) &
- XIOU_SCNTRS_CNT_CNTRL_REG_EN_MASK) != XIOU_SCNTRS_CNT_CNTRL_REG_EN){
-
- /*write frequency to System Time Stamp Generator Register*/
- Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_FREQ_REG_OFFSET),
- XIOU_SCNTRS_FREQ);
-
- /*Enable the counter*/
- Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET),
- XIOU_SCNTRS_CNT_CNTRL_REG_EN);
- }
-}
-/****************************************************************************/
-/**
-* @brief Timer of A53 runs continuously and the time can not be set as
-* desired. This API doesn't contain anything. It is defined to have
-* uniformity across platforms.
-*
-* @param Xtime_Global: 64bit Value to be written to the Global Timer Counter
-* Register. But since the function does not contain anything, the
-* value is not used for anything.
-*
-* @return None.
-*
-****************************************************************************/
-void XTime_SetTime(XTime Xtime_Global)
-{
- (void) Xtime_Global;
-/*As the generic timer of A53 runs constantly time can not be set as desired
-so the API is left unimplemented*/
-}
-
-/****************************************************************************/
-/**
-* @brief Get the time from the physical timer counter register.
-*
-* @param Xtime_Global: Pointer to the 64-bit location to be updated with
-* the current value in physical timer counter.
-*
-* @return None.
-*
-****************************************************************************/
-void XTime_GetTime(XTime *Xtime_Global)
-{
- /* Start global timer counter, it will only be enabled if it is disabled */
- XTime_StartTimer();
-
- *Xtime_Global = arch_counter_get_cntvct();
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c3/e03a8e545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c3/e03a8e545243001d18b399c1eb9b3628
deleted file mode 100644
index 27dffb9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c3/e03a8e545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1961 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xdmaps.c
-* @addtogroup dmaps_v2_8
-* @{
-*
-* This file contains the implementation of the interface functions for XDmaPs
-* driver. Refer to the header file xdmaps.h for more detailed information.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00 hbm 08/19/2010 First Release
-* 1.00 nm 05/25/2011 Updated for minor doxygen corrections
-* 1.02a sg 05/16/2012 Made changes for doxygen and moved some function
-* header from the xdmaps.h file to xdmaps.c file
-* Other cleanup for coding guidelines and CR 657109
-* and CR 657898
-* 1.03a sg 07/16/2012 changed inline to __inline for CR665681
-* 1.04a nm 10/22/2012 Fixed CR# 681671.
-* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled
-* with -Wall and -Wextra option in bsp.
-* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
-* function description.
-* Fixed CR# 704396. Removed unused variables
-* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
-* function.
-* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc.
-* Removed the PDBG prints. By default they were always
-* defined out and never used. The PDBG is non-standard for
-* Xilinx drivers and no other driver does something similar.
-* Since there is no easy way to fix compilation issues with
-* the IARCC compiler around PDBG, it is better to remove it.
-* Users can always use xil_printfs if they want to debug.
-* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
-* 2.2 mus 12/08/16 Remove definition of INLINE macro to avoid re-definition,
-* since it is being defined in xil_io.h
-* 2.3 kpc 14/10/16 Fixed the compiler error when optimization O0 is used.
-* 2.5 hk 08/16/19 Add a memory barrier before DMASEV as per specification.
-* 2.6 hk 02/14/20 Correct boundary check for Channel.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 1.00a ecm/sdm 02/01/10 Initial version
-* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
-* driver tcl
-* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
-* 6.6 srm 10/18/17 Added ARMA9 macro to identify CortexA9
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 5.00 pkp 05/29/14 First release
-* 5.04 pkp 02/19/16 Added timer configuration register offset definitions
-* 5.04 pkp 03/11/16 Removed definitions for overflow interrupt register
-* and mask
-* 6.6 srm 10/22/17 Added a warning message for the user configurable sleep
-* implementation when default timer is selected by the user
-* 7.2 mus 01/29/20 Updated #defines to support PMU cycle counter for sleep
-* routines.
-* 7.5 dp 01/05/21 Updated COUNTS_PER_SECOND/USECOND and ITERS_PER_SEC/USEC
-* macros to round it off to nearest possible value so that
-* delta error in time calculations can be minimized.
-* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
-* displaying same warnings multiple times. It fixes CR#1090562.
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XTIME_H /* prevent circular inclusions */
-#define XTIME_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xparameters.h"
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Constant Definitions *****************************/
-
-#ifdef SLEEP_TIMER_BASEADDR
-
-#define COUNTS_PER_SECOND SLEEP_TIMER_FREQUENCY
-
-#else
-#define ITERS_PER_SEC ((XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ + 2)/ 4)
-#define ITERS_PER_USEC ((XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ + 2000000)/ 4000000)
-
-/*
- * These constants are applicable for the CortexR5 PMU cycle counter.
- * As boot code is setting up "D" bit in PMCR, cycle counter increments
- * on every 64th bit of processor cycle
- */
-
-#define COUNTS_PER_SECOND ((XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ + 32)/ 64)
-#endif
-
-#define COUNTS_PER_USECOND ((COUNTS_PER_SECOND + 500000) / 1000000)
-
-#define IRQ_FIQ_MASK 0xC0 /* Mask IRQ and FIQ interrupts in cpsr */
-
-/*
- * 1st bit of PROCESSOR_ACCESS_VALUE macro signifies trustzone
- * setting for IOU slcr address space
- */
-#define IOU_SLCR_TZ_MASK 0x2U
-/**************************** Type Definitions *******************************/
-
-typedef u32 XTime;
-
-/**
- *@endcond
- */
-
-void XTime_SetTime(XTime Xtime_Global);
-void XTime_GetTime(XTime *Xtime_Global);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XTIME_H */
-/**
-* @} End of "@addtogroup r5_time_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c5/61882f595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c5/61882f595243001d18b399c1eb9b3628
deleted file mode 100644
index 08af00b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c5/61882f595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,93 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/*****************************************************************************/
-/**
-* @file sleep.h
-*
-* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep
-* related APIs.
-*
-*
-* MODIFICATION HISTORY :
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 6.6 srm 11/02/17 Added processor specific sleep routines
-* function prototypes.
-*
-*
-*
-******************************************************************************/
-
-#ifndef SLEEP_H
-#define SLEEP_H
-
-#include "xil_types.h"
-#include "xil_io.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*****************************************************************************/
-/**
-*
-* This macro polls an address periodically until a condition is met or till the
-* timeout occurs.
-* The minimum timeout for calling this macro is 100us. If the timeout is less
-* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
-* If the timeout is not a multiple of 100us, it waits for a timeout of
-* the next usec value which is a multiple of 100us.
-*
-* @param IO_func - accessor function to read the register contents.
-* Depends on the register width.
-* @param ADDR - Address to be polled
-* @param VALUE - variable to read the value
-* @param COND - Condition to checked (usually involves VALUE)
-* @param TIMEOUT_US - timeout in micro seconds
-*
-* @return 0 - when the condition is met
-* -1 - when the condition is not met till the timeout period
-*
-* @note none
-*
-*****************************************************************************/
-#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
- ( { \
- u64 timeout = TIMEOUT_US/100; \
- if(TIMEOUT_US%100!=0) \
- timeout++; \
- for(;;) { \
- VALUE = IO_func(ADDR); \
- if(COND) \
- break; \
- else { \
- usleep(100); \
- timeout--; \
- if(timeout==0) \
- break; \
- } \
- } \
- (timeout>0) ? 0 : -1; \
- } )
-
-void usleep(unsigned long useconds);
-void sleep(unsigned int seconds);
-int usleep_R5(unsigned long useconds);
-unsigned sleep_R5(unsigned int seconds);
-int usleep_MB(unsigned long useconds);
-unsigned sleep_MB(unsigned int seconds);
-int usleep_A53(unsigned long useconds);
-unsigned sleep_A53(unsigned int seconds);
-int usleep_A9(unsigned long useconds);
-unsigned sleep_A9(unsigned int seconds);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c5/61e5f3555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c5/61e5f3555243001d18b399c1eb9b3628
deleted file mode 100644
index 26966bf..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c5/61e5f3555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,81 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file usleep.c
-*
-* This function provides a microsecond delay using the Global Timer register in
-* the ARM Cortex A9 MP core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm 11/11/09 First release
-* 3.07a sgd 07/05/12 Updated micro sleep function to make use Global Timer
-* 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine as it is not
-* possible to generate timer in nanosecond due to
-* limited cpu frequency
-* 6.0 asa 08/15/16 Updated the usleep signature. Fix for CR#956899.
-* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
-* implementation. Now sleep routines will use Timer
-* specified by the user (i.e. Global timer/TTC timer)
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "sleep.h"
-#include "xtime_l.h"
-#include "xparameters.h"
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#include "xreg_cortexa9.h"
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#include "xil_sleeptimer.h"
-#endif
-
-/**************************** Constant Definitions ************************/
-#if defined (SLEEP_TIMER_BASEADDR)
-#define COUNTS_PER_USECOND (SLEEP_TIMER_FREQUENCY / 1000000)
-#else
-/* Global Timer is always clocked at half of the CPU frequency */
-#define COUNTS_PER_USECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / (2U*1000000U))
-#endif
-
-/*****************************************************************************/
-/**
-*
-* This API gives a delay in microseconds
-*
-* @param useconds requested
-*
-* @return 0 if the delay can be achieved, -1 if the requested delay
-* is out of range
-*
-* @note None.
-*
-****************************************************************************/
-int usleep_A9(unsigned long useconds)
-{
-#if defined (SLEEP_TIMER_BASEADDR)
- Xil_SleepTTCCommon(useconds, COUNTS_PER_USECOND);
-#else
- XTime tEnd, tCur;
-
- XTime_GetTime(&tCur);
- tEnd = tCur + (((XTime) useconds) * COUNTS_PER_USECOND);
- do
- {
- XTime_GetTime(&tCur);
- } while (tCur < tEnd);
-#endif
-
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c5/b14446595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c5/b14446595243001d18b399c1eb9b3628
deleted file mode 100644
index b3cd2ea..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c5/b14446595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,113 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xplatform_info.h
-*
-*
-* @addtogroup common_platform_info APIs to Get Platform Information
-*
-*
-* The xplatform_info.h file contains definitions for various available Xilinx®
-* platforms. Also, it contains prototype of APIs, which can be used to get the
-* platform information.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- --------- -------------------------------------------------------
-* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
-* function for PMUFW.
-* 7.2 adk 08/01/20 Added versal support for the XGetPSVersion_Info function.
-* 7.6 mus 08/23/21 Updated prototypes for functions which are not taking any
-* arguments with void keyword. This has been done to fix
-* compilation warnings with "-Wstrict-prototypes" flag.
-* It fixes CR#1108601.
-* 7.6 mus 08/30/21 Updated flag checking to fix compilation warnings
-* reported with "-Wundef" flag.
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */
-#define XPLATFORM_INFO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-#if defined (versal)
-#define XPAR_PMC_TAP_BASEADDR 0xF11A0000U
-#define XPAR_PMC_TAP_VERSION_OFFSET 0x00000004U
-#define XPLAT_PS_VERSION_ADDRESS (XPAR_PMC_TAP_BASEADDR + \
- XPAR_PMC_TAP_VERSION_OFFSET)
-#else
-#define XPAR_CSU_BASEADDR 0xFFCA0000U
-#define XPAR_CSU_VER_OFFSET 0x00000044U
-#define XPLAT_PS_VERSION_ADDRESS (XPAR_CSU_BASEADDR + \
- XPAR_CSU_VER_OFFSET)
-#endif
-#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
-#define XPLAT_ZYNQ_ULTRA_MP 0x1
-#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
-#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
-#define XPLAT_ZYNQ 0x4
-#define XPLAT_MICROBLAZE 0x5
-#define XPLAT_VERSAL 0x6U
-
-#define XPS_VERSION_1 0x0
-#define XPS_VERSION_2 0x1
-#define XPLAT_INFO_MASK (0xF)
-
-#if defined (versal)
-#define XPS_VERSION_INFO_MASK 0xFF00U
-#define XPS_VERSION_INFO_SHIFT 0x8U
-#define XPLAT_INFO_SHIFT 0x18U
-#else
-#define XPS_VERSION_INFO_MASK (0xF)
-#define XPS_VERSION_INFO_SHIFT 0x0U
-#define XPLAT_INFO_SHIFT 0xCU
-#endif
-
-/**************************** Type Definitions *******************************/
-/**
- *@endcond
- */
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-u32 XGetPlatform_Info(void);
-
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU) || defined (versal)
-u32 XGetPSVersion_Info(void);
-#endif
-
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
-u32 XGet_Zynq_UltraMp_Platform_info(void);
-#endif
-/************************** Function Prototypes ******************************/
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_platform_info".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c6/00e452585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c6/00e452585243001d18b399c1eb9b3628
deleted file mode 100644
index 5cf252c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c6/00e452585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,108 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xtime_l.c
-*
-* This file contains low level functions to get/set time from the Generic Counter
-* register in the ARM Cortex A53 MPcore.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 5.5 pkp 04/13/16 Added XTime_StartTimer API to start the global timer
-* counter if it is disabled. Also XTime_GetTime calls
-* this API to ensure the global timer counter is enabled
-* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
-* displaying same warnings multiple times. It fixes CR#1090562.
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "xtime_l.h"
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER)
-#pragma message ("For the sleep routines, Global timer is being used")
-#endif
-/****************************************************************************/
-/**
-* @brief Start the 64-bit physical timer counter.
-*
-* @return None.
-*
-* @note The timer is initialized only if it is disabled. If the timer is
-* already running this function does not perform any operation.
-*
-****************************************************************************/
-void XTime_StartTimer(void)
-{
- /* Enable the counter only if it is disable */
- if(((Xil_In32(XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET)) &
- XIOU_SCNTRS_CNT_CNTRL_REG_EN_MASK) != XIOU_SCNTRS_CNT_CNTRL_REG_EN){
-
- /*write frequency to System Time Stamp Generator Register*/
- Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_FREQ_REG_OFFSET),
- XIOU_SCNTRS_FREQ);
-
- /*Enable the counter*/
- Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET),
- XIOU_SCNTRS_CNT_CNTRL_REG_EN);
- }
-}
-/****************************************************************************/
-/**
-* @brief Timer of A53 runs continuously and the time can not be set as
-* desired. This API doesn't contain anything. It is defined to have
-* uniformity across platforms.
-*
-* @param Xtime_Global: 64bit Value to be written to the Global Timer Counter
-* Register. But since the function does not contain anything, the
-* value is not used for anything.
-*
-* @return None.
-*
-****************************************************************************/
-void XTime_SetTime(XTime Xtime_Global)
-{
- (void) Xtime_Global;
-/*As the generic timer of A53 runs constantly time can not be set as desired
-so the API is left unimplemented*/
-}
-
-/****************************************************************************/
-/**
-* @brief Get the time from the physical timer counter register.
-*
-* @param Xtime_Global: Pointer to the 64-bit location to be updated with
-* the current value in physical timer counter.
-*
-* @return None.
-*
-****************************************************************************/
-void XTime_GetTime(XTime *Xtime_Global)
-{
- /* Start global timer counter, it will only be enabled if it is disabled */
- XTime_StartTimer();
-
- *Xtime_Global = arch_counter_get_cntvct();
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c6/801ec5535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c6/801ec5535243001d18b399c1eb9b3628
deleted file mode 100644
index 379023c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c6/801ec5535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,154 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xl2cc.h
-*
-* This file contains the address definitions for the PL310 Level-2 Cache
-* Controller.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 02/01/10 Initial version
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef _XL2CC_H_
-#define _XL2CC_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-/* L2CC Register Offsets */
-#define XPS_L2CC_ID_OFFSET 0x0000U
-#define XPS_L2CC_TYPE_OFFSET 0x0004U
-#define XPS_L2CC_CNTRL_OFFSET 0x0100U
-#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104U
-#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108U
-#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010CU
-
-#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200U
-#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204U
-#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208U
-#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020CU
-#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210U
-
-#define XPS_L2CC_IER_OFFSET 0x0214U /* Interrupt Mask */
-#define XPS_L2CC_IPR_OFFSET 0x0218U /* Masked interrupt status */
-#define XPS_L2CC_ISR_OFFSET 0x021CU /* Raw Interrupt Status */
-#define XPS_L2CC_IAR_OFFSET 0x0220U /* Interrupt Clear */
-
-#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730U /* Cache Sync */
-#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740U /* Dummy Register for Cache Sync */
-#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770U /* Cache Invalid by PA */
-#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077CU /* Cache Invalid by Way */
-#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0U /* Cache Clean by PA */
-#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8U /* Cache Clean by Index */
-#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BCU /* Cache Clean by Way */
-#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0U /* Cache Invalidate and Clean by PA */
-#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8U /* Cache Invalidate and Clean by Index */
-#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FCU /* Cache Invalidate and Clean by Way */
-
-#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900U /* Cache Data Lockdown 0 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904U /* Cache Instruction Lockdown 0 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908U /* Cache Data Lockdown 1 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090CU /* Cache Instruction Lockdown 1 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910U /* Cache Data Lockdown 2 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914U /* Cache Instruction Lockdown 2 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918U /* Cache Data Lockdown 3 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091CU /* Cache Instruction Lockdown 3 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920U /* Cache Data Lockdown 4 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924U /* Cache Instruction Lockdown 4 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928U /* Cache Data Lockdown 5 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092CU /* Cache Instruction Lockdown 5 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930U /* Cache Data Lockdown 6 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934U /* Cache Instruction Lockdown 6 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938U /* Cache Data Lockdown 7 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093CU /* Cache Instruction Lockdown 7 by Way */
-
-#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U /* Cache Lockdown Line Enable */
-#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954U /* Cache Unlock All Lines by Way */
-
-#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00U /* Start of address filtering */
-#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04U /* Start of address filtering */
-
-#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40U /* Debug Control Register */
-
-/* XPS_L2CC_CNTRL_OFFSET bit masks */
-#define XPS_L2CC_ENABLE_MASK 0x00000001U /* enables the L2CC */
-
-/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */
-#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000U /* Early BRESP Enable */
-#define XPS_L2CC_AUX_IPFE_MASK 0x20000000U /* Instruction Prefetch Enable */
-#define XPS_L2CC_AUX_DPFE_MASK 0x10000000U /* Data Prefetch Enable */
-#define XPS_L2CC_AUX_NSIC_MASK 0x08000000U /* Non-secure interrupt access control */
-#define XPS_L2CC_AUX_NSLE_MASK 0x04000000U /* Non-secure lockdown enable */
-#define XPS_L2CC_AUX_CRP_MASK 0x02000000U /* Cache replacement policy */
-#define XPS_L2CC_AUX_FWE_MASK 0x01800000U /* Force write allocate */
-#define XPS_L2CC_AUX_SAOE_MASK 0x00400000U /* Shared attribute override enable */
-#define XPS_L2CC_AUX_PE_MASK 0x00200000U /* Parity enable */
-#define XPS_L2CC_AUX_EMBE_MASK 0x00100000U /* Event monitor bus enable */
-#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000U /* Way-size */
-#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000U /* Associativity */
-#define XPS_L2CC_AUX_SAIE_MASK 0x00002000U /* Shared attribute invalidate enable */
-#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000U /* Exclusive cache configuration */
-#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800U /* Store buffer device limitation Enable */
-#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400U /* High Priority for SO and Dev Reads Enable */
-#define XPS_L2CC_AUX_FLZE_MASK 0x00000001U /* Full line of zero enable */
-
-#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000U /* Enable all prefetching, */
- /* Cache replacement policy, Parity enable, */
- /* Event monitor bus enable and Way Size (64 KB) */
-#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFFU /* */
-
-#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111U /* latency for TAG RAM */
-#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121U /* latency for DATA RAM */
-
-/* Interrupt bit masks */
-#define XPS_L2CC_IXR_DECERR_MASK 0x00000100U /* DECERR from L3 */
-#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080U /* SLVERR from L3 */
-#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040U /* Error on L2 data RAM (Read) */
-#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020U /* Error on L2 tag RAM (Read) */
-#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010U /* Error on L2 data RAM (Write) */
-#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008U /* Error on L2 tag RAM (Write) */
-#define XPS_L2CC_IXR_PARRD_MASK 0x00000004U /* Parity Error on L2 data RAM (Read) */
-#define XPS_L2CC_IXR_PARRT_MASK 0x00000002U /* Parity Error on L2 tag RAM (Read) */
-#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001U /* Event Counter1/0 Overflow Increment */
-
-/* Address filtering mask and enable bit */
-#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000U /* Address filtering valid bits*/
-#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U /* Address filtering enable bit*/
-
-/* Debug control bits */
-#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004U /* Debug SPIDEN bit */
-#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002U /* Debug DWB bit, forces write through */
-#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002U /* Debug DCL bit, disables cache line fill */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* protection macro */
-
-/**
- *@endcond
- */
\ No newline at end of file
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c6/e05889545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c6/e05889545243001d18b399c1eb9b3628
deleted file mode 100644
index f1fa391..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c6/e05889545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,88 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xdevcfg_selftest.c
-* @addtogroup devcfg_v3_7
-* @{
-*
-* Contains diagnostic self-test functions for the XDcfg driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.02a nm 02/27/13 Fixed CR# 701348.
-* Peripheral test fails with Running
-* DcfgSelfTestExample() in SECURE bootmode.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xdevcfg.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/****************************************************************************/
-/**
-*
-* Run a self-test on the Device Configuration Interface. This test does a
-* control register write and reads back the same value.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return
-* - XST_SUCCESS if self-test was successful.
-* - XST_FAILURE if fails.
-*
-* @note None.
-*
-******************************************************************************/
-int XDcfg_SelfTest(XDcfg *InstancePtr)
-{
- u32 OldCfgReg;
- u32 CfgReg;
- int Status = XST_SUCCESS;
-
- /*
- * Assert to ensure the inputs are valid and the instance has been
- * initialized.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- OldCfgReg = XDcfg_GetControlRegister(InstancePtr);
-
- XDcfg_SetControlRegister(InstancePtr, XDCFG_CTRL_NIDEN_MASK);
-
- CfgReg = XDcfg_GetControlRegister(InstancePtr);
-
- if ((CfgReg & XDCFG_CTRL_NIDEN_MASK) != XDCFG_CTRL_NIDEN_MASK) {
-
- Status = XST_FAILURE;
- }
-
- /*
- * Restore the original values of the register
- */
- XDcfg_SetControlRegister(InstancePtr, OldCfgReg);
-
- return Status;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c7/50a8d3545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c7/50a8d3545243001d18b399c1eb9b3628
deleted file mode 100644
index 6d1f418..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c7/50a8d3545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,163 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xscugic_intr.c
-* @addtogroup scugic_v4_6
-* @{
-*
-* This file contains the interrupt processing for the driver for the Xilinx
-* Interrupt Controller. The interrupt processing is partitioned separately such
-* that users are not required to use the provided interrupt processing. This
-* file requires other files of the driver to be linked in also.
-*
-* The interrupt handler, XScuGic_InterruptHandler, uses an input argument which
-* is an instance pointer to an interrupt controller driver such that multiple
-* interrupt controllers can be supported. This handler requires the calling
-* function to pass it the appropriate argument, so another level of indirection
-* may be required.
-*
-* The interrupt processing may be used by connecting the interrupt handler to
-* the interrupt system. The handler does not save and restore the processor
-* context but only handles the processing of the Interrupt Controller. The user
-* is encouraged to supply their own interrupt handler when performance tuning is
-* deemed necessary.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------------
-* 1.00a drg 01/19/10 First release
-* 1.01a sdm 11/09/11 XScuGic_InterruptHandler has changed correspondingly
-* since the HandlerTable has now moved to XScuGic_Config.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.10 mus 07/17/18 Updated XScuGic_InterruptHandler to fix array overrun
-* reported by coverity tool. It fixes CR#1006344.
-* 3.10 mus 07/17/18 Updated file to fix the various coding style issues
-* reported by checkpatch. It fixes CR#1006344.
-*
-*
-*
-* @internal
-*
-* This driver assumes that the context of the processor has been saved prior to
-* the calling of the Interrupt Controller interrupt handler and then restored
-* after the handler returns. This requires either the running RTOS to save the
-* state of the machine or that a wrapper be used as the destination of the
-* interrupt vector to save the state of the processor and restore the state
-* after the interrupt handler returns.
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xscugic.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-* This function is the primary interrupt handler for the driver. It must be
-* connected to the interrupt source such that it is called when an interrupt of
-* the interrupt controller is active. It will resolve which interrupts are
-* active and enabled and call the appropriate interrupt handler. It uses
-* the Interrupt Type information to determine when to acknowledge the interrupt.
-* Highest priority interrupts are serviced first.
-*
-* This function assumes that an interrupt vector table has been previously
-* initialized. It does not verify that entries in the table are valid before
-* calling an interrupt handler.
-*
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XScuGic_InterruptHandler(XScuGic *InstancePtr)
-{
-
- u32 InterruptID;
-#if !defined (GICv3)
- u32 IntIDFull;
-#endif
- XScuGic_VectorTableEntry *TablePtr;
-
- /* Assert that the pointer to the instance is valid
- */
- Xil_AssertVoid(InstancePtr != NULL);
-
- /*
- * Read the int_ack register to identify the highest priority
- * interrupt ID and make sure it is valid. Reading Int_Ack will
- * clear the interrupt in the GIC.
- */
-#if defined (GICv3)
- InterruptID = XScuGic_get_IntID();
-#else
- IntIDFull = XScuGic_CPUReadReg(InstancePtr, XSCUGIC_INT_ACK_OFFSET);
- InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
-#endif
- if (XSCUGIC_MAX_NUM_INTR_INPUTS <= InterruptID) {
- goto IntrExit;
- }
-
- /*
- * If the interrupt is shared, do some locking here if
- * there are multiple processors.
- */
- /*
- * If pre-eption is required:
- * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
- * interrupts or the F bit for secure interrupts
- */
-
- /*
- * If we need to change security domains, issue a SMC
- * instruction here.
- */
-
- /*
- * Execute the ISR. Jump into the Interrupt service routine
- * based on the IRQSource. A software trigger is cleared by
- *.the ACK.
- */
- TablePtr = &(InstancePtr->Config->HandlerTable[InterruptID]);
- if (TablePtr != NULL) {
- TablePtr->Handler(TablePtr->CallBackRef);
- }
-
-IntrExit:
- /*
- * Write to the EOI register, we are all done here.
- * Let this function return, the boot code will restore the stack.
- */
-#if defined (GICv3)
- XScuGic_ack_Int(InterruptID);
-
-#else
- XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_EOI_OFFSET, IntIDFull);
-#endif
- /*
- * Return from the interrupt. Change security domains
- * could happen here.
- */
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c7/7020c1565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c7/7020c1565243001d18b399c1eb9b3628
deleted file mode 100644
index 6b51ea9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c7/7020c1565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,28 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-
-#ifndef _MBLAZE_NT_TYPES_H
-#define _MBLAZE_NT_TYPES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef char byte;
-typedef short half;
-typedef int word;
-typedef unsigned char ubyte;
-typedef unsigned short uhalf;
-typedef unsigned int uword;
-typedef ubyte boolean;
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c7/812f4e555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c7/812f4e555243001d18b399c1eb9b3628
deleted file mode 100644
index 2f30d77..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c7/812f4e555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * xen_events.h
- *
- * Created on: Sep 14, 2016
- * Author: jarvis
- */
-/*
-Copyright DornerWorks 2016
-
-Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-following conditions are met:
-1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
-following disclaimer.
-
-THIS SOFTWARE IS PROVIDED BY DORNERWORKS FOR USE ON THE CONTRACTED PROJECT, AND ANY EXPRESS OR IMPLIED WARRANTY
-IS LIMITED TO THIS USE. FOR ALL OTHER USES THIS SOFTWARE IS PROVIDED ''AS IS'' AND ANY EXPRESS OR IMPLIED
-WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL DORNERWORKS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-#ifndef _XEN_EVENTS_H_
-#define _XEN_EVENTS_H_
-
-#include "xil_types.h"
-
-#define PAGE_SHIFT 12 // not really a good place for this
-#define PAGE_SIZE (1< struct evtchn_* */
-#define EVTCHNOP_bind_interdomain 0
-#define EVTCHNOP_bind_virq 1
-#define EVTCHNOP_bind_pirq 2
-#define EVTCHNOP_close 3
-#define EVTCHNOP_send 4
-#define EVTCHNOP_status 5
-#define EVTCHNOP_alloc_unbound 6
-#define EVTCHNOP_bind_ipi 7
-#define EVTCHNOP_bind_vcpu 8
-#define EVTCHNOP_unmask 9
-#define EVTCHNOP_reset 10
-#define EVTCHNOP_init_control 11
-#define EVTCHNOP_expand_array 12
-#define EVTCHNOP_set_priority 13
-
-
-void notify_evtch(u32 evtch_id);
-void init_events(void);
-int register_event_handler(u32 evtch_id, void (*fptr)(void));
-void unmask_evtchn(u32 port);
-void handle_event_irq(void* data);
-
-#endif /* _XEN_EVENTS_H_ */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c7/904e73565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c7/904e73565243001d18b399c1eb9b3628
deleted file mode 100644
index 53eac10..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c7/904e73565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,25 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/* The errno variable is stored in the reentrancy structure. This
- function returns its address for use by the macro errno defined in
- errno.h. */
-
-#include
-#include
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) sint32 * __errno (void);
-}
-#endif
-
-__attribute__((weak)) sint32 *
-__errno (void)
-{
- return &_REENT->_errno;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/03024e585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/03024e585243001d18b399c1eb9b3628
deleted file mode 100644
index df332c7..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/03024e585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,77 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_mmu.h
-*
-* @addtogroup a53_32_mmu_apis Cortex A53 32bit Processor MMU Handling
-* @{
-* MMU functions equip users to enable MMU, disable MMU and modify default
-* memory attributes of MMU table as per the need.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 7.1 mus 30/07/19 Added constant definitions for memory attributes.
-*
-*
-*
-******************************************************************************/
-
-#ifndef XIL_MMU_H
-#define XIL_MMU_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-/* Memory type */
-#define NORM_NONCACHE 0x11DE2 /* Normal Non-cacheable */
-#define STRONG_ORDERED 0xC02 /* Strongly ordered */
-#define DEVICE_MEMORY 0xC06 /* Device memory */
-#define RESERVED 0x0 /* reserved memory */
-
-/* Normal write-through cacheable shareable */
-#define NORM_WT_CACHE 0x16DEA
-
-/* Normal write back cacheable shareable */
-#define NORM_WB_CACHE 0x15DE6
-
-/* shareability attribute */
-#define SHAREABLE (0x1 << 16)
-#define NON_SHAREABLE (~(0x1 << 16))
-
-/* Execution type */
-#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0))
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void Xil_SetTlbAttributes(UINTPTR Addr, u32 attrib);
-void Xil_EnableMMU(void);
-void Xil_DisableMMU(void);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_MMU_H */
-/**
-* @} End of "addtogroup a53_32_mmu_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/2087ad585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/2087ad585243001d18b399c1eb9b3628
deleted file mode 100644
index f2d44ce..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/2087ad585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,28 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#ifndef UNDEFINE_FILE_OPS
-#include
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode);
-}
-#endif
-
-/*
- * _open -- open a file descriptor. We don't have a filesystem, so
- * we return an error.
- */
-__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode)
-{
- (void)buf;
- (void)flags;
- (void)mode;
- errno = EIO;
- return (-1);
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/210593595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/210593595243001d18b399c1eb9b3628
deleted file mode 100644
index 26966bf..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/210593595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,81 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file usleep.c
-*
-* This function provides a microsecond delay using the Global Timer register in
-* the ARM Cortex A9 MP core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm 11/11/09 First release
-* 3.07a sgd 07/05/12 Updated micro sleep function to make use Global Timer
-* 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine as it is not
-* possible to generate timer in nanosecond due to
-* limited cpu frequency
-* 6.0 asa 08/15/16 Updated the usleep signature. Fix for CR#956899.
-* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
-* implementation. Now sleep routines will use Timer
-* specified by the user (i.e. Global timer/TTC timer)
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "sleep.h"
-#include "xtime_l.h"
-#include "xparameters.h"
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#include "xreg_cortexa9.h"
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#include "xil_sleeptimer.h"
-#endif
-
-/**************************** Constant Definitions ************************/
-#if defined (SLEEP_TIMER_BASEADDR)
-#define COUNTS_PER_USECOND (SLEEP_TIMER_FREQUENCY / 1000000)
-#else
-/* Global Timer is always clocked at half of the CPU frequency */
-#define COUNTS_PER_USECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / (2U*1000000U))
-#endif
-
-/*****************************************************************************/
-/**
-*
-* This API gives a delay in microseconds
-*
-* @param useconds requested
-*
-* @return 0 if the delay can be achieved, -1 if the requested delay
-* is out of range
-*
-* @note None.
-*
-****************************************************************************/
-int usleep_A9(unsigned long useconds)
-{
-#if defined (SLEEP_TIMER_BASEADDR)
- Xil_SleepTTCCommon(useconds, COUNTS_PER_USECOND);
-#else
- XTime tEnd, tCur;
-
- XTime_GetTime(&tCur);
- tEnd = tCur + (((XTime) useconds) * COUNTS_PER_USECOND);
- do
- {
- XTime_GetTime(&tCur);
- } while (tCur < tEnd);
-#endif
-
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/405504555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/405504555243001d18b399c1eb9b3628
deleted file mode 100644
index 105c913..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/405504555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,39 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include "xil_types.h"
-
-extern u8 _heap_start[];
-extern u8 _heap_end[];
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) caddr_t _sbrk ( s32 incr );
-}
-#endif
-
-__attribute__((weak)) caddr_t _sbrk ( s32 incr )
-{
- static u8 *heap = NULL;
- u8 *prev_heap;
- static u8 *HeapEndPtr = (u8 *)&_heap_end;
- caddr_t Status;
-
- if (heap == NULL) {
- heap = (u8 *)&_heap_start;
- }
- prev_heap = heap;
-
- if (((heap + incr) <= HeapEndPtr) && (prev_heap != NULL)) {
- heap += incr;
- Status = (caddr_t) ((void *)prev_heap);
- } else {
- Status = (caddr_t) -1;
- }
-
- return Status;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/6056f6555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/6056f6555243001d18b399c1eb9b3628
deleted file mode 100644
index b828612..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/6056f6555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1534 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.c
-*
-* Contains required functions for the ARM cache functionality.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 01/29/10 First release
-* 1.00a ecm 06/24/10 Moved the L1 and L2 specific function prototypes
-* to xil_cache_mach.h to give access to sophisticated users
-* 3.02a sdm 04/07/11 Updated Flush/InvalidateRange APIs to flush/invalidate
-* L1 and L2 caches in a single loop and used dsb, L2 sync
-* at the end of the loop.
-* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
-* APIs.
-* 3.07a asa 07/16/12 Corrected the L1 and L2 cache invalidation order.
-* 3.07a sgd 09/18/12 Corrected the L2 cache enable and disable sequence.
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-* 3.10a asa 05/13/13 Modified cache disable APIs. The L2 cache disable
-* operation was being done with L1 Data cache disabled. This is
-* fixed so that L2 cache disable operation happens independent of
-* L1 cache disable operation. This fixes CR #706464.
-* Changes are done to do a L2 cache sync (poll reg7_?cache_?sync).
-* This is done to fix the CR #700542.
-* 3.11a asa 09/23/13 Modified the Xil_DCacheFlushRange and
-* Xil_DCacheInvalidateRange to fix potential issues. Fixed other
-* relevant cache APIs to disable and enable back the interrupts.
-* This fixes CR #663885.
-* 3.11a asa 09/28/13 Made changes for L2 cache sync operation. It is found
-* out that for L2 cache flush/clean/invalidation by cache lines
-* does not need a cache sync as these are atomic nature. Similarly
-* figured out that for complete L2 cache flush/invalidation by way
-* we need to wait for some more time in a loop till the status
-* shows that the cache operation is completed.
-* 4.00 pkp 24/01/14 Modified Xil_DCacheInvalidateRange to fix the bug. Few
-* cache lines were missed to invalidate when unaligned address
-* invalidation was accommodated. That fixes CR #766768.
-* Also in Xil_L1DCacheInvalidate, while invalidating all L1D cache
-* stack memory which contains return address was invalidated. So
-* stack memory was flushed first and then L1D cache is invalidated.
-* This is done to fix CR #763829
-* 4.01 asa 05/09/14 Made changes in cortexa9/xil_cache.c to fix CR# 798230.
-* 4.02 pkp 06/27/14 Added notes to Xil_L1DCacheInvalidateRange function for
-* explanation of CR#785243
-* 5.00 kvn 12/15/14 Xil_L2CacheInvalidate was modified to fix CR# 838835. L2 Cache
-* has stack memory which has return address. Before invalidating
-* cache, stack memory was flushed first and L2 Cache is invalidated.
-* 5.01 pkp 05/12/15 Xil_DCacheInvalidateRange and Xil_DCacheFlushRange is modified
-* to remove unnecessary dsb in the APIs. Instead of using dsb
-* for L2 Cache, L2CacheSync has been used for each L2 cache line
-* and single dsb has been used for L1 cache. Also L2CacheSync is
-* added into Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate
-* and Xil_L2CacheInvalidate APIs are modified to flush the complete
-* stack instead of just System Stack
-* 5.03 pkp 10/07/15 L2 Cache functionalities are avoided for the OpenAMP slave
-* application(when USE_AMP flag is defined for BSP) as master CPU
-* would be utilizing L2 cache for its operation
-* 6.6 mus 12/07/17 Errata 753970 is not applicable for the PL130 cache controller
-* version r0p2, which is present in zynq. So,removed the handling
-* related to same.It fixes CR#989132.
-* 6.6 asa 16/01/18 Changes made in Xil_L1DCacheInvalidate and Xil_L2CacheInvalidate
-* routines to ensure the stack data flushed only when the respective
-* caches are enabled. This fixes CR-992023.
-* 7.5 mus 01/19/21 Implement workaround for errata#588369 in Xil_DCacheFlushRange.
-* It fixes CR#1086022.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xil_cache_l.h"
-#include "xil_io.h"
-#include "xpseudo_asm.h"
-#include "xparameters.h"
-#include "xreg_cortexa9.h"
-#include "xl2cc.h"
-#include "xil_errata.h"
-#include "xil_exception.h"
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#define IRQ_FIQ_MASK 0xC0U /* Mask IRQ and FIQ interrupts in cpsr */
-
-#ifdef __GNUC__
- extern s32 _stack_end;
- extern s32 __undef_stack;
-#endif
-
-#ifndef USE_AMP
-/****************************************************************************
-*
-* Access L2 Debug Control Register.
-*
-* @param Value, value to be written to Debug Control Register.
-*
-* @return None.
-*
-****************************************************************************/
-#ifdef __GNUC__
-static inline void Xil_L2WriteDebugCtrl(u32 Value)
-#else
-static void Xil_L2WriteDebugCtrl(u32 Value)
-#endif
-{
-#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DEBUG_CTRL_OFFSET, Value);
-#else
- (void)(Value);
-#endif
-}
-
-/****************************************************************************
-*
-* Perform L2 Cache Sync Operation.
-*
-* @return None.
-*
-****************************************************************************/
-#ifdef __GNUC__
-static inline void Xil_L2CacheSync(void)
-#else
-static void Xil_L2CacheSync(void)
-#endif
-{
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0U);
-}
-#endif
-/****************************************************************************/
-/**
-* @brief Enable the Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheEnable(void)
-{
- Xil_L1DCacheEnable();
-#ifndef USE_AMP
- Xil_L2CacheEnable();
-#endif
-}
-
-/****************************************************************************/
-/**
-* @brief Disable the Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheDisable(void)
-{
-#ifndef USE_AMP
- Xil_L2CacheDisable();
-#endif
- Xil_L1DCacheDisable();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the entire Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheInvalidate(void)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-#ifndef USE_AMP
- Xil_L2CacheInvalidate();
-#endif
- Xil_L1DCacheInvalidate();
-
- mtcpsr(currmask);
-}
-
-/*****************************************************************************/
-/**
-* @brief Invalidate a Data cache line. If the byte specified by the address
-* (adr) is cached by the Data cache, the cacheline containing that
-* byte is invalidated. If the cacheline is modified (dirty), the
-* modified contents are lost and are NOT written to the system memory
-* before the line is invalidated.
-*
-* @param adr: 32bit address of the data to be flushed.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_DCacheInvalidateLine(u32 adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-#ifndef USE_AMP
- Xil_L2CacheInvalidateLine(adr);
-#endif
- Xil_L1DCacheInvalidateLine(adr);
-
- mtcpsr(currmask);
-}
-
-
-/*****************************************************************************/
-/**
-* Invalidate the Data cache for the given address range.
-* If the bytes specified by the address range are cached by the Data
-* cache, the cachelines containing those bytes are invalidated. If
-* the cachelines are modified (dirty), the modified contents are lost
-* and NOT written to the system memory before the lines are
-* invalidated.
-*
-* In this function, if start address or end address is not aligned to
-* cache-line, particular cache-line containing unaligned start or end
-* address is flush first and then invalidated the others as
-* invalidating the same unaligned cache line may result into loss of
-* data. This issue raises few possibilities.
-*
-* If the address to be invalidated is not cache-line aligned, the
-* following choices are available:
-* 1. Invalidate the cache line when required and do not bother much
-* for the side effects. Though it sounds good, it can result in
-* hard-to-debug issues. The problem is, if some other variable are
-* allocated in the same cache line and had been recently updated
-* (in cache), the invalidation would result in loss of data.
-* 2. Flush the cache line first. This will ensure that if any other
-* variable present in the same cache line and updated recently are
-* flushed out to memory. Then it can safely be invalidated. Again it
-* sounds good, but this can result in issues. For example, when the
-* invalidation happens in a typical ISR (after a DMA transfer has
-* updated the memory), then flushing the cache line means, losing
-* data that were updated recently before the ISR got invoked.
-*
-* Linux prefers the second one. To have uniform implementation
-* (across standalone and Linux), the second option is implemented.
-* This being the case, following needs to be taken care of:
-* 1. Whenever possible, the addresses must be cache line aligned.
-* Please nore that, not just start address, even the end address must
-* be cache line aligned. If that is taken care of, this will always
-* work.
-* 2. Avoid situations where invalidation has to be done after the
-* data is updated by peripheral/DMA directly into the memory. It is
-* not tough to achieve (may be a bit risky). The common use case to
-* do invalidation is when a DMA happens. Generally for such use
-* cases, buffers can be allocated first and then start the DMA. The
-* practice that needs to be followed here is, immediately after
-* buffer allocation and before starting the DMA, do the invalidation.
-* With this approach, invalidation need not to be done after the DMA
-* transfer is over.
-*
-* This is going to always work if done carefully.
-* However, the concern is, there is no guarantee that invalidate has
-* not needed to be done after DMA is complete. For example, because
-* of some reasons if the first cache line or last cache line
-* (assuming the buffer in question comprises of multiple cache lines)
-* are brought into cache (between the time it is invalidated and DMA
-* completes) because of some speculative prefetching or reading data
-* for a variable present in the same cache line, then we will have to
-* invalidate the cache after DMA is complete.
-*
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
-{
- const u32 cacheline = 32U;
- u32 end;
- u32 tempadr = adr;
- u32 tempend;
- u32 currmask;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INVLD_PA_OFFSET);
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- end = tempadr + len;
- tempend = end;
- /* Select L1 Data cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
-
- if ((tempadr & (cacheline-1U)) != 0U) {
- tempadr &= (~(cacheline - 1U));
-
- Xil_L1DCacheFlushLine(tempadr);
-#ifndef USE_AMP
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
- Xil_L2CacheFlushLine(tempadr);
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- Xil_L2CacheSync();
-#endif
- tempadr += cacheline;
- }
- if ((tempend & (cacheline-1U)) != 0U) {
- tempend &= (~(cacheline - 1U));
-
- Xil_L1DCacheFlushLine(tempend);
-#ifndef USE_AMP
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
- Xil_L2CacheFlushLine(tempend);
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- Xil_L2CacheSync();
-#endif
- }
-
- while (tempadr < tempend) {
-#ifndef USE_AMP
- /* Invalidate L2 cache line */
- *L2CCOffset = tempadr;
- Xil_L2CacheSync();
-#endif
-
- /* Invalidate L1 Data cache line */
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_dc_line_mva_poc(tempadr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
- Reg = tempadr; }
-#endif
- tempadr += cacheline;
- }
- }
-
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the entire Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheFlush(void)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- Xil_L1DCacheFlush();
-#ifndef USE_AMP
- Xil_L2CacheFlush();
-#endif
- mtcpsr(currmask);
-}
-
-
-/****************************************************************************/
-/**
-* @brief Flush a Data cache line. If the byte specified by the address (adr)
-* is cached by the Data cache, the cacheline containing that byte is
-* invalidated. If the cacheline is modified (dirty), the entire
-* contents of the cacheline are written to system memory before the
-* line is invalidated.
-*
-* @param adr: 32bit address of the data to be flushed.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_DCacheFlushLine(u32 adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- Xil_L1DCacheFlushLine(adr);
-#ifndef USE_AMP
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
-
- Xil_L2CacheFlushLine(adr);
-
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- Xil_L2CacheSync();
-#endif
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the Data cache for the given address range.
-* If the bytes specified by the address range are cached by the
-* data cache, the cachelines containing those bytes are invalidated.
-* If the cachelines are modified (dirty), they are written to the
-* system memory before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be flushed.
-* @param len: Length of the range to be flushed in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheFlushRange(INTPTR adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- u32 currmask;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr &= ~(cacheline - 1U);
-#ifndef USE_AMP
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
-#endif
- while (LocalAddr < end) {
-
- /* Flush L1 Data cache line */
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
- Reg = LocalAddr; }
-#endif
-#ifndef USE_AMP
- /* Flush L2 cache line */
- *L2CCOffset = LocalAddr;
- Xil_L2CacheSync();
-#endif
- LocalAddr += cacheline;
- }
-#ifndef USE_AMP
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
-#endif
- }
- dsb();
- mtcpsr(currmask);
-}
-/****************************************************************************/
-/**
-* @brief Store a Data cache line. If the byte specified by the address (adr)
-* is cached by the Data cache and the cacheline is modified (dirty),
-* the entire contents of the cacheline are written to system memory.
-* After the store completes, the cacheline is marked as unmodified
-* (not dirty).
-*
-* @param adr: 32bit address of the data to be stored.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_DCacheStoreLine(u32 adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- Xil_L1DCacheStoreLine(adr);
-#ifndef USE_AMP
- Xil_L2CacheStoreLine(adr);
-#endif
- mtcpsr(currmask);
-}
-
-/***************************************************************************/
-/**
-* @brief Enable the instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ICacheEnable(void)
-{
- Xil_L1ICacheEnable();
-#ifndef USE_AMP
- Xil_L2CacheEnable();
-#endif
-}
-
-/***************************************************************************/
-/**
-* @brief Disable the instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ICacheDisable(void)
-{
-#ifndef USE_AMP
- Xil_L2CacheDisable();
-#endif
- Xil_L1ICacheDisable();
-}
-
-
-/****************************************************************************/
-/**
-* @brief Invalidate the entire instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ICacheInvalidate(void)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-#ifndef USE_AMP
- Xil_L2CacheInvalidate();
-#endif
- Xil_L1ICacheInvalidate();
-
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate an instruction cache line. If the instruction specified
-* by the address is cached by the instruction cache, the cacheline
-* containing that instruction is invalidated.
-*
-* @param adr: 32bit address of the instruction to be invalidated.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_ICacheInvalidateLine(u32 adr)
-{
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-#ifndef USE_AMP
- Xil_L2CacheInvalidateLine(adr);
-#endif
- Xil_L1ICacheInvalidateLine(adr);
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the instruction cache for the given address range.
-* If the instructions specified by the address range are cached by
-* the instrunction cache, the cachelines containing those
-* instructions are invalidated.
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INVLD_PA_OFFSET);
-
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Select cache L0 I-cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
-
- while (LocalAddr < end) {
-#ifndef USE_AMP
- /* Invalidate L2 cache line */
- *L2CCOffset = LocalAddr;
- dsb();
-#endif
-
- /* Invalidate L1 I-cache line */
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_ic_line_mva_pou(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
- Reg = LocalAddr; }
-#endif
-
- LocalAddr += cacheline;
- }
- }
-
- /* Wait for L1 and L2 invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Enable the level 1 Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1DCacheEnable(void)
-{
- register u32 CtrlReg;
-
- /* enable caches only if they are disabled */
-#ifdef __GNUC__
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
- CtrlReg = Reg; }
-#endif
- if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) {
- return;
- }
-
- /* clean and invalidate the Data cache */
- Xil_L1DCacheInvalidate();
-
- /* enable the Data cache */
- CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/***************************************************************************/
-/**
-* @brief Disable the level 1 Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1DCacheDisable(void)
-{
- register u32 CtrlReg;
-
- /* clean and invalidate the Data cache */
- Xil_L1DCacheFlush();
-
-#ifdef __GNUC__
- /* disable the Data cache */
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
- CtrlReg = Reg; }
-#endif
-
- CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the level 1 Data cache.
-*
-* @return None.
-*
-* @note In Cortex A9, there is no cp instruction for invalidating
-* the whole D-cache. This function invalidates each line by
-* set/way.
-*
-****************************************************************************/
-void Xil_L1DCacheInvalidate(void)
-{
- register u32 CsidReg, C7Reg;
- u32 CacheSize, LineSize, NumWays;
- u32 Way, WayIndex, Set, SetIndex, NumSet;
- u32 currmask;
-
-#ifdef __GNUC__
- u32 stack_start,stack_end,stack_size;
- register u32 CtrlReg;
-#endif
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
-#ifdef __GNUC__
- stack_end = (u32)&_stack_end;
- stack_start = (u32)&__undef_stack;
- stack_size=stack_start-stack_end;
-
- /* Check for the cache status. If cache is enabled, then only
- * flush stack memory to save return address. If cache is disabled,
- * don't flush anything as it might result in flushing stale date into
- * memory which is undesirable.
- * */
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) {
- Xil_DCacheFlushRange(stack_end, stack_size);
- }
-#endif
-
- /* Select cache level 0 and D cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
-
-#ifdef __GNUC__
- CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID);
- CsidReg = Reg; }
-#endif
- /* Determine Cache Size */
- CacheSize = (CsidReg >> 13U) & 0x1FFU;
- CacheSize +=1U;
- CacheSize *=128U; /* to get number of bytes */
-
- /* Number of Ways */
- NumWays = (CsidReg & 0x3ffU) >> 3U;
- NumWays += 1U;
-
- /* Get the cacheline size, way size, index size from csidr */
- LineSize = (CsidReg & 0x07U) + 4U;
-
- NumSet = CacheSize/NumWays;
- NumSet /= (0x00000001U << LineSize);
-
- Way = 0U;
- Set = 0U;
-
- /* Invalidate all the cachelines */
- for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set;
-
- /* Invalidate by Set/Way */
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_dc_line_sw(C7Reg);
-#else
- /*mtcp(XREG_CP15_INVAL_DC_LINE_SW, C7Reg), */
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_DC_LINE_SW);
- Reg = C7Reg; }
-#endif
- Set += (0x00000001U << LineSize);
- }
- Set=0U;
- Way += 0x40000000U;
- }
-
- /* Wait for L1 invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate a level 1 Data cache line. If the byte specified by the
-* address (Addr) is cached by the Data cache, the cacheline
-* containing that byte is invalidated. If the cacheline is modified
-* (dirty), the modified contents are lost and are NOT written to
-* system memory before the line is invalidated.
-*
-* @param adr: 32bit address of the data to be invalidated.
-*
-* @return None.
-*
-* @note The bottom 5 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L1DCacheInvalidateLine(u32 adr)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
- mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU)));
-
- /* Wait for L1 invalidate to complete */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the level 1 Data cache for the given address range.
-* If the bytes specified by the address range are cached by the Data
-* cache, the cachelines containing those bytes are invalidated. If the
-* cachelines are modified (dirty), the modified contents are lost and
-* NOT written to the system memory before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1DCacheInvalidateRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Select cache L0 D-cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
-
- while (LocalAddr < end) {
-
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_dc_line_mva_poc(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
- Reg = LocalAddr; }
-#endif
- LocalAddr += cacheline;
- }
- }
-
- /* Wait for L1 invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the level 1 Data cache.
-*
-* @return None.
-*
-* @note In Cortex A9, there is no cp instruction for flushing
-* the whole D-cache. Need to flush each line.
-*
-****************************************************************************/
-void Xil_L1DCacheFlush(void)
-{
- register u32 CsidReg, C7Reg;
- u32 CacheSize, LineSize, NumWays;
- u32 Way;
- u32 WayIndex, Set, SetIndex, NumSet;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- /* Select cache level 0 and D cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
-
-#ifdef __GNUC__
- CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID);
- CsidReg = Reg; }
-#endif
-
- /* Determine Cache Size */
-
- CacheSize = (CsidReg >> 13U) & 0x1FFU;
- CacheSize +=1U;
- CacheSize *=128U; /* to get number of bytes */
-
- /* Number of Ways */
- NumWays = (CsidReg & 0x3ffU) >> 3U;
- NumWays += 1U;
-
- /* Get the cacheline size, way size, index size from csidr */
- LineSize = (CsidReg & 0x07U) + 4U;
-
- NumSet = CacheSize/NumWays;
- NumSet /= (0x00000001U << LineSize);
-
- Way = 0U;
- Set = 0U;
-
- /* Invalidate all the cachelines */
- for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set;
- /* Flush by Set/Way */
-
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_clean_inval_dc_line_sw(C7Reg);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_SW);
- Reg = C7Reg; }
-#endif
- Set += (0x00000001U << LineSize);
- }
- Set = 0U;
- Way += 0x40000000U;
- }
-
- /* Wait for L1 flush to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush a level 1 Data cache line. If the byte specified by the
-* address (adr) is cached by the Data cache, the cacheline containing
-* that byte is invalidated. If the cacheline is modified (dirty), the
-* entire contents of the cacheline are written to system memory
-* before the line is invalidated.
-*
-* @param adr: 32bit address of the data to be flushed.
-*
-* @return None.
-*
-* @note The bottom 5 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L1DCacheFlushLine(u32 adr)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
- mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU)));
-
- /* Wait for L1 flush to complete */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the level 1 Data cache for the given address range.
-* If the bytes specified by the address range are cached by the Data
-* cache, the cacheline containing those bytes are invalidated. If the
-* cachelines are modified (dirty), they are written to system memory
-* before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be flushed.
-* @param len: Length of the range to be flushed in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1DCacheFlushRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Select cache L0 D-cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
-
- while (LocalAddr < end) {
-
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
- Reg = LocalAddr; }
-#endif
- LocalAddr += cacheline;
- }
- }
-
- /* Wait for L1 flush to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Store a level 1 Data cache line. If the byte specified by the
-* address (adr) is cached by the Data cache and the cacheline is
-* modified (dirty), the entire contents of the cacheline are written
-* to system memory. After the store completes, the cacheline is
-* marked as unmodified (not dirty).
-*
-* @param adr: Address to be stored.
-*
-* @return None.
-*
-* @note The bottom 5 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L1DCacheStoreLine(u32 adr)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
- mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1FU)));
-
- /* Wait for L1 store to complete */
- dsb();
-}
-
-
-/****************************************************************************/
-/**
-* @brief Enable the level 1 instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1ICacheEnable(void)
-{
- register u32 CtrlReg;
-
- /* enable caches only if they are disabled */
-#ifdef __GNUC__
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
- CtrlReg = Reg; }
-#endif
- if ((CtrlReg & (XREG_CP15_CONTROL_I_BIT)) != 0U) {
- return;
- }
-
- /* invalidate the instruction cache */
- mtcp(XREG_CP15_INVAL_IC_POU, 0U);
-
- /* enable the instruction cache */
- CtrlReg |= (XREG_CP15_CONTROL_I_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/****************************************************************************/
-/**
-* @brief Disable level 1 the instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1ICacheDisable(void)
-{
- register u32 CtrlReg;
-
- dsb();
-
- /* invalidate the instruction cache */
- mtcp(XREG_CP15_INVAL_IC_POU, 0U);
-
- /* disable the instruction cache */
-#ifdef __GNUC__
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-#else
- { volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
- CtrlReg = Reg; }
-#endif
- CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT);
-
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the entire level 1 instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1ICacheInvalidate(void)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
- /* invalidate the instruction cache */
- mtcp(XREG_CP15_INVAL_IC_POU, 0U);
-
- /* Wait for L1 invalidate to complete */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate a level 1 instruction cache line. If the instruction
-* specified by the address is cached by the instruction cache, the
-* cacheline containing that instruction is invalidated.
-*
-* @param adr: 32bit address of the instruction to be invalidated.
-*
-* @return None.
-*
-* @note The bottom 5 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L1ICacheInvalidateLine(u32 adr)
-{
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
- mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1FU)));
-
- /* Wait for L1 invalidate to complete */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the level 1 instruction cache for the given address
-* range. If the instrucions specified by the address range are cached
-* by the instruction cache, the cacheline containing those bytes are
-* invalidated.
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L1ICacheInvalidateRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Select cache L0 I-cache in CSSR */
- mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
-
- while (LocalAddr < end) {
-
-#if defined (__GNUC__) || defined (__ICCARM__)
- asm_cp15_inval_ic_line_mva_pou(LocalAddr);
-#else
- { volatile register u32 Reg
- __asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
- Reg = LocalAddr; }
-#endif
- LocalAddr += cacheline;
- }
- }
-
- /* Wait for L1 invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-#ifndef USE_AMP
-/****************************************************************************/
-/**
-* @brief Enable the L2 cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L2CacheEnable(void)
-{
- register u32 L2CCReg;
-
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
-
- /* only enable if L2CC is currently disabled */
- if ((L2CCReg & 0x01U) == 0U) {
- /* set up the way size and latencies */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
- XPS_L2CC_AUX_CNTRL_OFFSET);
- L2CCReg &= XPS_L2CC_AUX_REG_ZERO_MASK;
- L2CCReg |= XPS_L2CC_AUX_REG_DEFAULT_MASK;
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_AUX_CNTRL_OFFSET,
- L2CCReg);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_TAG_RAM_CNTRL_OFFSET,
- XPS_L2CC_TAG_RAM_DEFAULT_MASK);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DATA_RAM_CNTRL_OFFSET,
- XPS_L2CC_DATA_RAM_DEFAULT_MASK);
-
- /* Clear the pending interrupts */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
- XPS_L2CC_ISR_OFFSET);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_IAR_OFFSET, L2CCReg);
-
- Xil_L2CacheInvalidate();
- /* Enable the L2CC */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
- XPS_L2CC_CNTRL_OFFSET);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
- (L2CCReg | (0x01U)));
-
- Xil_L2CacheSync();
- /* synchronize the processor */
- dsb();
-
- }
-}
-
-/****************************************************************************/
-/**
-* @brief Disable the L2 cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L2CacheDisable(void)
-{
- register u32 L2CCReg;
-
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
-
- if((L2CCReg & 0x1U) != 0U) {
-
- /* Clean and Invalidate L2 Cache */
- Xil_L2CacheFlush();
-
- /* Disable the L2CC */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
- (L2CCReg & (~0x01U)));
- /* Wait for the cache operations to complete */
-
- dsb();
- }
-}
-
-/*****************************************************************************/
-/**
-* @brief Invalidate the entire level 2 cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L2CacheInvalidate(void)
-{
- #ifdef __GNUC__
- u32 stack_start,stack_end,stack_size;
- register u32 L2CCReg;
- stack_end = (u32)&_stack_end;
- stack_start = (u32)&__undef_stack;
- stack_size=stack_start-stack_end;
-
- /* Check for the cache status. If cache is enabled, then only
- * flush stack memory to save return address. If cache is disabled,
- * don't flush anything as it might result in flushing stale date into
- * memory which is undesirable.
- */
- L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
- if ((L2CCReg & 0x01U) != 0U) {
- /*Flush stack memory to save return address*/
- Xil_DCacheFlushRange(stack_end, stack_size);
- }
-
- #endif
- u32 ResultDCache;
- /* Invalidate the caches */
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET,
- 0x0000FFFFU);
- ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)
- & 0x0000FFFFU;
- while(ResultDCache != (u32)0U) {
- ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)
- & 0x0000FFFFU;
- }
-
- /* Wait for the invalidate to complete */
- Xil_L2CacheSync();
-
- /* synchronize the processor */
- dsb();
-}
-
-/*****************************************************************************/
-/**
-* @brief Invalidate a level 2 cache line. If the byte specified by the
-* address (adr) is cached by the Data cache, the cacheline containing
-* that byte is invalidated. If the cacheline is modified (dirty),
-* the modified contents are lost and are NOT written to system memory
-* before the line is invalidated.
-*
-* @param adr: 32bit address of the data/instruction to be invalidated.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L2CacheInvalidateLine(u32 adr)
-{
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, (u32)adr);
- /* synchronize the processor */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the level 2 cache for the given address range.
-* If the bytes specified by the address range are cached by the L2
-* cache, the cacheline containing those bytes are invalidated. If the
-* cachelines are modified (dirty), the modified contents are lost and
-* are NOT written to system memory before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L2CacheInvalidateRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INVLD_PA_OFFSET);
-
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
-
- while (LocalAddr < end) {
- *L2CCOffset = LocalAddr;
- Xil_L2CacheSync();
- LocalAddr += cacheline;
- }
-
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- }
-
- /* synchronize the processor */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the entire level 2 cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L2CacheFlush(void)
-{
- u32 ResultL2Cache;
-
- /* Flush the caches */
-
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
-
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET,
- 0x0000FFFFU);
- ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
- & 0x0000FFFFU;
-
- while(ResultL2Cache != (u32)0U) {
- ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
- & 0x0000FFFFU;
- }
-
- Xil_L2CacheSync();
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
-
- /* synchronize the processor */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Flush a level 2 cache line. If the byte specified by the address
-* (adr) is cached by the L2 cache, the cacheline containing that
-* byte is invalidated. If the cacheline is modified (dirty), the
-* entire contents of the cacheline are written to system memory
-* before the line is invalidated.
-*
-* @param adr: 32bit address of the data/instruction to be flushed.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L2CacheFlushLine(u32 adr)
-{
-#ifdef CONFIG_PL310_ERRATA_588369
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, adr);
-#else
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET, adr);
-#endif
- /* synchronize the processor */
- dsb();
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the level 2 cache for the given address range.
-* If the bytes specified by the address range are cached by the L2
-* cache, the cacheline containing those bytes are invalidated. If the
-* cachelines are modified (dirty), they are written to the system
-* memory before the lines are invalidated.
-*
-* @param adr: 32bit start address of the range to be flushed.
-* @param len: Length of the range to be flushed in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_L2CacheFlushRange(u32 adr, u32 len)
-{
- u32 LocalAddr = adr;
- const u32 cacheline = 32U;
- u32 end;
- volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
- XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
-
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- if (len != 0U) {
- /* Back the starting address up to the start of a cache line
- * perform cache operations until adr+len
- */
- end = LocalAddr + len;
- LocalAddr = LocalAddr & ~(cacheline - 1U);
-
- /* Disable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x3U);
-
- while (LocalAddr < end) {
- *L2CCOffset = LocalAddr;
- Xil_L2CacheSync();
- LocalAddr += cacheline;
- }
-
- /* Enable Write-back and line fills */
- Xil_L2WriteDebugCtrl(0x0U);
- }
- /* synchronize the processor */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Store a level 2 cache line. If the byte specified by the address
-* (adr) is cached by the L2 cache and the cacheline is modified
-* (dirty), the entire contents of the cacheline are written to
-* system memory. After the store completes, the cacheline is marked
-* as unmodified (not dirty).
-*
-* @param adr: 32bit address of the data/instruction to be stored.
-*
-* @return None.
-*
-* @note The bottom 4 bits are set to 0, forced by architecture.
-*
-****************************************************************************/
-void Xil_L2CacheStoreLine(u32 adr)
-{
- Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
- /* synchronize the processor */
- dsb();
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/90ceab575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/90ceab575243001d18b399c1eb9b3628
deleted file mode 100644
index 27a10ad..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/90ceab575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,425 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xuartps_hw.h
-* @addtogroup uartps_v3_11
-* @{
-*
-* This header file contains the hardware interface of an XUartPs device.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00 drg/jz 01/12/10 First Release
-* 1.03a sg 09/04/12 Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
-* and XUARTPS_IXR_TTRIG.
-* Modified the names of these defines
-* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
-* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
-* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
-* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
-* 1.05a hk 08/22/13 Added prototype for uart reset and related
-* constant definitions.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
-* 3.6 ms 02/16/18 Updates flow control mode offset value in
-* modem control register.
-*
-*
-*
-******************************************************************************/
-#ifndef XUARTPS_HW_H /* prevent circular inclusions */
-#define XUARTPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets for the UART.
- * @{
- */
-#define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */
-#define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */
-#define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */
-#define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */
-#define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */
-#define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/
-#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */
-#define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */
-#define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */
-#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */
-#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */
-#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */
-#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */
-#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */
-#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */
-#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */
-#define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */
-/* @} */
-
-/** @name Control Register
- *
- * The Control register (CR) controls the major functions of the device.
- *
- * Control Register Bit Definition
- */
-
-#define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */
-#define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */
-#define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */
-#define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */
-#define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */
-#define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */
-#define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */
-#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */
-#define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */
-#define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */
-/* @}*/
-
-
-/** @name Mode Register
- *
- * The mode register (MR) defines the mode of transfer as well as the data
- * format. If this register is modified during transmission or reception,
- * data validity cannot be guaranteed.
- *
- * Mode Register Bit Definition
- * @{
- */
-#define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */
-#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */
-#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */
-#define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */
-#define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */
-#define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */
-#define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */
-#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */
-#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */
-#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */
-#define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */
-#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */
-#define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */
-#define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */
-#define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */
-#define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */
-#define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */
-#define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */
-#define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */
-#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */
-#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */
-#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */
-#define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */
-#define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */
-#define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */
-/* @} */
-
-
-/** @name Interrupt Registers
- *
- * Interrupt control logic uses the interrupt enable register (IER) and the
- * interrupt disable register (IDR) to set the value of the bits in the
- * interrupt mask register (IMR). The IMR determines whether to pass an
- * interrupt to the interrupt status register (ISR).
- * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
- * interrupt. IMR and ISR are read only, and IER and IDR are write only.
- * Reading either IER or IDR returns 0x00.
- *
- * All four registers have the same bit definitions.
- *
- * @{
- */
-#define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */
-#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */
-#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */
-#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */
-#define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */
-#define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */
-#define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */
-#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */
-#define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */
-#define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */
-#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */
-#define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */
-#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */
-#define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */
-#define XUARTPS_IXR_MASK 0x00003FFFU /**< Valid bit mask */
-/* @} */
-
-
-/** @name Baud Rate Generator Register
- *
- * The baud rate generator control register (BRGR) is a 16 bit register that
- * controls the receiver bit sample clock and baud rate.
- * Valid values are 1 - 65535.
- *
- * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
- * in the MR register.
- * @{
- */
-#define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */
-#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */
-#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */
-
-/** @name Baud Divisor Rate register
- *
- * The baud rate divider register (BDIV) controls how much the bit sample
- * rate is divided by. It sets the baud rate.
- * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
- *
- * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
- * the MR_CCLK bit in the MR register.
- * @{
- */
-#define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */
-#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */
-/* @} */
-
-
-/** @name Receiver Timeout Register
- *
- * Use the receiver timeout register (RTR) to detect an idle condition on
- * the receiver data line.
- *
- * @{
- */
-#define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */
-#define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */
-
-/** @name Receiver FIFO Trigger Level Register
- *
- * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
- * which the RX FIFO triggers an interrupt event.
- * @{
- */
-
-#define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */
-#define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */
-#define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */
-/* @} */
-
-/** @name Transmit FIFO Trigger Level Register
- *
- * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
- * which the TX FIFO triggers an interrupt event.
- * @{
- */
-
-#define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */
-#define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */
-/* @} */
-
-/** @name Modem Control Register
- *
- * This register (MODEMCR) controls the interface with the modem or data set,
- * or a peripheral device emulating a modem.
- *
- * @{
- */
-#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */
-#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */
-#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */
-/* @} */
-
-/** @name Modem Status Register
- *
- * This register (MODEMSR) indicates the current state of the control lines
- * from a modem, or another peripheral device, to the CPU. In addition, four
- * bits of the modem status register provide change information. These bits
- * are set to a logic 1 whenever a control input from the modem changes state.
- *
- * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
- * status interrupt is generated and this is reflected in the modem status
- * register.
- *
- * @{
- */
-#define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */
-#define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */
-#define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */
-#define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */
-#define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */
-#define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */
-#define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */
-#define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */
-#define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */
-/* @} */
-
-/** @name Channel Status Register
- *
- * The channel status register (CSR) is provided to enable the control logic
- * to monitor the status of bits in the channel interrupt status register,
- * even if these are masked out by the interrupt mask register.
- *
- * @{
- */
-#define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */
-#define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */
-#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */
-#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */
-#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */
-#define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */
-#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */
-#define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */
-#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */
-#define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */
-/* @} */
-
-/** @name Flow Delay Register
- *
- * Operation of the flow delay register (FLOWDEL) is very similar to the
- * receive FIFO trigger register. An internal trigger signal activates when the
- * FIFO is filled to the level set by this register. This trigger will not
- * cause an interrupt, although it can be read through the channel status
- * register. In hardware flow control mode, RTS is deactivated when the trigger
- * becomes active. RTS only resets when the FIFO level is four less than the
- * level of the flow delay trigger and the flow delay trigger is not activated.
- * A value less than 4 disables the flow delay.
- * @{
- */
-#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */
-/* @} */
-
-/** @name Receiver FIFO Byte Status Register
- *
- * The Receiver FIFO Status register is used to have a continuous
- * monitoring of the raw unmasked byte status information. The register
- * contains frame, parity and break status information for the top
- * four bytes in the RX FIFO.
- *
- * Receiver FIFO Byte Status Register Bit Definition
- * @{
- */
-#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /**< Byte3 Break Error */
-#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /**< Byte3 Frame Error */
-#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /**< Byte3 Parity Error */
-#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /**< Byte2 Break Error */
-#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /**< Byte2 Frame Error */
-#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /**< Byte2 Parity Error */
-#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /**< Byte1 Break Error */
-#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /**< Byte1 Frame Error */
-#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /**< Byte1 Parity Error */
-#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /**< Byte0 Break Error */
-#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /**< Byte0 Frame Error */
-#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /**< Byte0 Parity Error */
-#define XUARTPS_RXBS_MASK 0x00000007U /**< 3 bit RX byte status mask */
-/* @} */
-
-
-/*
- * Defines for backwards compatibility, will be removed
- * in the next version of the driver
- */
-#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD
-#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI
-#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR
-#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS
-
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-* Read a UART register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the base address of the
-* device.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
-*
-******************************************************************************/
-#define XUartPs_ReadReg(BaseAddress, RegOffset) \
- Xil_In32((BaseAddress) + (u32)(RegOffset))
-
-/***************************************************************************/
-/**
-* Write a UART register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the base address of the
-* device.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u16 RegisterValue)
-*
-******************************************************************************/
-#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
-
-/****************************************************************************/
-/**
-* Determine if there is receive data in the receiver and/or FIFO.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return TRUE if there is receive data, FALSE otherwise.
-*
-* @note C-Style signature:
-* u32 XUartPs_IsReceiveData(u32 BaseAddress)
-*
-******************************************************************************/
-#define XUartPs_IsReceiveData(BaseAddress) \
- !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
- (u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
-
-/****************************************************************************/
-/**
-* Determine if a byte of data can be sent with the transmitter.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the
-* FIFO.
-*
-* @note C-Style signature:
-* u32 XUartPs_IsTransmitFull(u32 BaseAddress)
-*
-******************************************************************************/
-#define XUartPs_IsTransmitFull(BaseAddress) \
- ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
- (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
-
-/************************** Function Prototypes ******************************/
-
-void XUartPs_SendByte(u32 BaseAddress, u8 Data);
-
-u8 XUartPs_RecvByte(u32 BaseAddress);
-
-void XUartPs_ResetHw(u32 BaseAddress);
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/a0b59e545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/a0b59e545243001d18b399c1eb9b3628
deleted file mode 100644
index e1bcd93..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/a0b59e545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,762 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
- *
- * @file xemacps_bd.h
-* @addtogroup emacps_v3_15
-* @{
- *
- * This header provides operations to manage buffer descriptors in support
- * of scatter-gather DMA.
- *
- * The API exported by this header defines abstracted macros that allow the
- * user to read/write specific BD fields.
- *
- * Buffer Descriptors
- *
- * A buffer descriptor (BD) defines a DMA transaction. The macros defined by
- * this header file allow access to most fields within a BD to tailor a DMA
- * transaction according to user and hardware requirements. See the hardware
- * IP DMA spec for more information on BD fields and how they affect transfers.
- *
- * The XEmacPs_Bd structure defines a BD. The organization of this structure
- * is driven mainly by the hardware for use in scatter-gather DMA transfers.
- *
- * Performance
- *
- * Limiting I/O to BDs can improve overall performance of the DMA channel.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -------------------------------------------------------
- * 1.00a wsy 01/10/10 First release
- * 2.1 srt 07/15/14 Add support for Zynq Ultrascale MP GEM specification
- * and 64-bit changes.
- * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
- * 3.0 hk 02/20/15 Added support for jumbo frames.
- * Disable extended mode. Perform all 64 bit changes under
- * check for arch64.
- * 3.2 hk 11/18/15 Change BD typedef and number of words.
- * 3.8 hk 08/18/18 Remove duplicate definition of XEmacPs_BdSetLength
- * 3.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
- *
- *
- *
- * ***************************************************************************
- */
-
-#ifndef XEMACPS_BD_H /* prevent circular inclusions */
-#define XEMACPS_BD_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-#ifdef __aarch64__
-/* Minimum BD alignment */
-#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U
-#define XEMACPS_BD_NUM_WORDS 4U
-#else
-/* Minimum BD alignment */
-#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U
-#define XEMACPS_BD_NUM_WORDS 2U
-#endif
-
-/**
- * The XEmacPs_Bd is the type for buffer descriptors (BDs).
- */
-typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- * Zero out BD fields
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Nothing
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClear(BdPtr) \
- memset((BdPtr), 0, sizeof(XEmacPs_Bd))
-
-/****************************************************************************/
-/**
-*
-* Read the given Buffer Descriptor word.
-*
-* @param BaseAddress is the base address of the BD to read
-* @param Offset is the word offset to be read
-*
-* @return The 32-bit value of the field
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)
-*
-*****************************************************************************/
-#define XEmacPs_BdRead(BaseAddress, Offset) \
- (*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given Buffer Descriptor word.
-*
-* @param BaseAddress is the base address of the BD to write
-* @param Offset is the word offset to be written
-* @param Data is the 32-bit value to write to the field
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)
-*
-*****************************************************************************/
-#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \
- (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
-
-/*****************************************************************************/
-/**
- * Set the BD's Address field (word 0).
- *
- * @param BdPtr is the BD pointer to operate on
- * @param Addr is the value to write to BD's status field.
- *
- * @note :
- *
- * C-style signature:
- * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
- *
- *****************************************************************************/
-#if defined(__aarch64__) || defined(__arch64__)
-#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- (u32)((Addr) & ULONG64_LO_MASK)); \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
- (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
-#else
-#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
-#endif
-
-/*****************************************************************************/
-/**
- * Set the BD's Address field (word 0).
- *
- * @param BdPtr is the BD pointer to operate on
- * @param Addr is the value to write to BD's status field.
- *
- * @note : Due to some bits are mixed within receive BD's address field,
- * read-modify-write is performed.
- *
- * C-style signature:
- * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
- *
- *****************************************************************************/
-#ifdef __aarch64__
-#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- ~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
- (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
-#else
-#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))
-#endif
-
-/*****************************************************************************/
-/**
- * Set the BD's Status field (word 1).
- *
- * @param BdPtr is the BD pointer to operate on
- * @param Data is the value to write to BD's status field.
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetStatus(BdPtr, Data) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))
-
-
-/*****************************************************************************/
-/**
- * Retrieve the BD's Packet DMA transfer status word (word 1).
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Status word
- *
- * @note
- * C-style signature:
- * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)
- *
- * Due to the BD bit layout differences in transmit and receive. User's
- * caution is required.
- *****************************************************************************/
-#define XEmacPs_BdGetStatus(BdPtr) \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
-
-
-/*****************************************************************************/
-/**
- * Get the address (bits 0..31) of the BD's buffer address (word 0)
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#if defined(__aarch64__) || defined(__arch64__)
-#define XEmacPs_BdGetBufAddr(BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
-#else
-#define XEmacPs_BdGetBufAddr(BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
-#endif
-
-/*****************************************************************************/
-/**
- * Set transfer length in bytes for the given BD. The length must be set each
- * time a BD is submitted to hardware.
- *
- * @param BdPtr is the BD pointer to operate on
- * @param LenBytes is the number of bytes to transfer.
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
-
-
-/*****************************************************************************/
-/**
- * Retrieve the BD length field.
- *
- * For Tx channels, the returned value is the same as that written with
- * XEmacPs_BdSetLength().
- *
- * For Rx channels, the returned value is the size of the received packet.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Length field processed by hardware or set by
- * XEmacPs_BdSetLength().
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
- * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
- *
- *****************************************************************************/
-#define XEmacPs_BdGetLength(BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_LEN_MASK)
-
-/*****************************************************************************/
-/**
- * Retrieve the RX frame size.
- *
- * The returned value is the size of the received packet.
- * This API supports jumbo frame sizes if enabled.
- *
- * @param InstancePtr is the pointer to XEmacps instance
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Length field processed by hardware or set by
- * XEmacPs_BdSetLength().
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr)
- * RxBufMask is dependent on whether jumbo is enabled or not.
- *
- *****************************************************************************/
-#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- (InstancePtr)->RxBufMask)
-
-/*****************************************************************************/
-/**
- * Test whether the given BD has been marked as the last BD of a packet.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsLast(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Tell the DMA engine that the given transmit BD marks the end of the current
- * packet to be processed.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetLast(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_LAST_MASK))
-
-
-/*****************************************************************************/
-/**
- * Tell the DMA engine that the current packet does not end with the given
- * BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearLast(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_LAST_MASK))
-
-
-/*****************************************************************************/
-/**
- * Set this bit to mark the last descriptor in the receive buffer descriptor
- * list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-/*#define XEmacPs_BdSetRxWrap(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
- XEMACPS_RXBUF_WRAP_MASK))
-*/
-
-/*****************************************************************************/
-/**
- * Determine the wrap bit of the receive BD which indicates end of the
- * BD list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxWrap(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Sets this bit to mark the last descriptor in the transmit buffer
- * descriptor list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-/*#define XEmacPs_BdSetTxWrap(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_WRAP_MASK))
-*/
-
-/*****************************************************************************/
-/**
- * Determine the wrap bit of the transmit BD which indicates end of the
- * BD list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxWrap(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/*
- * Must clear this bit to enable the MAC to write data to the receive
- * buffer. Hardware sets this bit once it has successfully written a frame to
- * memory. Once set, software has to clear the bit before the buffer can be
- * used again. This macro clear the new bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearRxNew(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- ~XEMACPS_RXBUF_NEW_MASK))
-
-
-/*****************************************************************************/
-/**
- * Determine the new bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxNew(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Software sets this bit to disable the buffer to be read by the hardware.
- * Hardware sets this bit for the first buffer of a frame once it has been
- * successfully transmitted. This macro sets this bit of transmit BD to avoid
- * confusion.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetTxUsed(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_USED_MASK))
-
-
-/*****************************************************************************/
-/**
- * Software clears this bit to enable the buffer to be read by the hardware.
- * Hardware sets this bit for the first buffer of a frame once it has been
- * successfully transmitted. This macro clears this bit of transmit BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearTxUsed(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_USED_MASK))
-
-
-/*****************************************************************************/
-/**
- * Determine the used bit of the transmit BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxUsed(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if a frame fails to be transmitted due to too many retries.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxRetry(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if a frame fails to be transmitted due to data can not be
- * feteched in time or buffers are exhausted.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxUrun(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if a frame fails to be transmitted due to buffer is exhausted
- * mid-frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxExh(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Sets this bit, no CRC will be appended to the current frame. This control
- * bit must be set for the first buffer in a frame and will be ignored for
- * the subsequent buffers of a frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * This bit must be clear when using the transmit checksum generation offload,
- * otherwise checksum generation and substitution will not occur.
- *
- * C-style signature:
- * UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetTxNoCRC(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_NOCRC_MASK))
-
-
-/*****************************************************************************/
-/**
- * Clear this bit, CRC will be appended to the current frame. This control
- * bit must be set for the first buffer in a frame and will be ignored for
- * the subsequent buffers of a frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * This bit must be clear when using the transmit checksum generation offload,
- * otherwise checksum generation and substitution will not occur.
- *
- * C-style signature:
- * UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearTxNoCRC(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_NOCRC_MASK))
-
-
-/*****************************************************************************/
-/**
- * Determine the broadcast bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxBcast(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the multicast hash bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxMultiHash(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the unicast hash bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxUniHash(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if the received frame is a VLAN Tagged frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxVlan(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if the received frame has Type ID of 8100h and null VLAN
- * identifier(Priority tag).
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxPri(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if the received frame's Concatenation Format Indicator (CFI) of
- * the frames VLANTCI field was set.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxCFI(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the End Of Frame (EOF) bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxEOF(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the Start Of Frame (SOF) bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxSOF(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
-
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/f0054a545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/f0054a545243001d18b399c1eb9b3628
deleted file mode 100644
index 5798c21..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/f0054a545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,54 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_testcache.h
-*
-* @addtogroup common_test_utils
-*
Cache test
-* The xil_testcache.h file contains utility functions to test cache.
-*
-* @{
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 07/29/09 First release
-*
-*
-******************************************************************************/
-
-/**
-*@cond nocomments
-*/
-
-#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */
-#define XIL_TESTCACHE_H /* by using protection macros */
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern s32 Xil_TestDCacheRange(void);
-extern s32 Xil_TestDCacheAll(void);
-extern s32 Xil_TestICacheRange(void);
-extern s32 Xil_TestICacheAll(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
-
-/**
-* @} End of "addtogroup common_test_utils".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/f0764c545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/f0764c545243001d18b399c1eb9b3628
deleted file mode 100644
index e22e04d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c8/f0764c545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,181 +0,0 @@
-/******************************************************************************/
-/**
-* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-* @file xil_util.h
-* @addtogroup common_utilities Common Utility APIs
-* @{
-* @details
-*
-* This file contains xil utility functions declaration
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.4 mmd 04/21/19 First release.
-* 6.5 kal 02/29/20 Added Xil_ConvertStringToHexBE API
-* 7.3 kal 06/30/20 Converted Xil_Ceil macro to API
-* rpo 08/19/20 Added function for read, modify and write
-* bsv 08/21/20 Added XSECURE_TEMPORAL_CHECK macro to add
-* redundancy in security critical functions, to avoid
-* glitches from altering the return values of security
-* critical functions. The macro requires a label to be
-* passed to "go to" in case of error.
-* kpt 09/03/20 Added XSECURE_TEMPORAL_IMPL macro for redundancy
-* kal 09/22/20 Changed the param type from const char to const char*
-* to avoid copying key onto stack
-* td 10/16/20 Added Xil_Strcpy, Xil_Strcat, Xil_SecureMemCpy and
-* Xil_MemCmp functions
-* am 10/13/20 Resolved Coverity warning
-* td 11/19/20 Updated XSECURE_TEMPORAL_CHECK and
-* XSECURE_TEMPORAL_IMPL to fix MISRA C Rule 15.3
-* 7.4 am 11/26/20 Added Xil_StrCpyRange function
-* 7.6 kpt 07/15/21 Added Xil_SecureZeroize function
-*
-*
-*
-*****************************************************************************/
-
-#ifndef XIL_UTIL_H_
-#define XIL_UTIL_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xstatus.h"
-
-/*************************** Constant Definitions *****************************/
-#define XIL_SIZE_OF_NIBBLE_IN_BITS 4U
-#define XIL_SIZE_OF_BYTE_IN_BITS 8U
-
-/* Maximum string length handled by Xil_ValidateHexStr function */
-#define XIL_MAX_HEX_STR_LEN 512U
-
-
-/****************** Macros (Inline Functions) Definitions *********************/
-#ifdef __GNUC__
-/******************************************************************************/
-/**
- *
- * Updates the return value of the called function into Var and VarTmp variables
- * for redundancy. This is to avoid glitches from altering the return values of
- * security critical functions.
- *
- * @param Var is the variable which holds the return value of function
- * executed
- * @param VarTmp is the variable which holds the value stored in Var
- * @param Function is the function to be executed
- * @param Other params are arguments to the called function
- *
- * @return None
- *
- ******************************************************************************/
-#define XSECURE_TEMPORAL_IMPL(Var, VarTmp, Function, ...) \
- { \
- Var = XST_FAILURE; \
- VarTmp = XST_FAILURE; \
- Var = Function(__VA_ARGS__); \
- VarTmp = Var; \
- }
-
-/******************************************************************************/
-/**
- *
- * Adds redundancy while checking the status of the called function.
- * This is to avoid glitches from altering the return values of security
- * critical functions. The macro requires a label to be passed to "go to"
- * in case of error.
- *
- * @param Label is the label defined in function and the control
- * will jump to the label in case of XST_FAILURE
- * @param Status is the variable which holds the return value of
- * function executed
- * @param Function is the function to be executed
- * @param Other params are arguments to the called function
- *
- * @return None
- *
- ******************************************************************************/
-#define XSECURE_TEMPORAL_CHECK(Label, Status, Function, ...) \
- { \
- volatile int StatusTmp = XST_FAILURE; \
- XSECURE_TEMPORAL_IMPL(Status, StatusTmp, Function, __VA_ARGS__); \
- if ((Status != XST_SUCCESS) || \
- (StatusTmp != XST_SUCCESS)) { \
- Status |= StatusTmp;\
- goto Label; \
- } \
- }
-#endif
-
-/*************************** Function Prototypes ******************************/
-/* Ceils the provided float value */
-int Xil_Ceil(float Value);
-
-/* Converts input character to nibble */
-u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num);
-
-/* Convert input hex string to array of 32-bits integers */
-u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len);
-
-/* Waits for specified event */
-u32 Xil_WaitForEvent(u32 RegAddr, u32 EventMask, u32 Event, u32 Timeout);
-
-/* Waits for specified events */
-u32 Xil_WaitForEvents(u32 EventsRegAddr, u32 EventsMask, u32 WaitEvents,
- u32 Timeout, u32* Events);
-
-/* Validate input hex character */
-u32 Xil_IsValidHexChar(const char *Ch);
-
-/* Validate the input string contains only hexadecimal characters */
-u32 Xil_ValidateHexStr(const char *HexStr);
-
-/* Convert string to hex numbers in little enidian format */
-u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len);
-
-/* Returns length of the input string */
-u32 Xil_Strnlen(const char *Str, u32 MaxLen);
-
-/* Convert string to hex numbers in big endian format */
-u32 Xil_ConvertStringToHexBE(const char * Str, u8 * Buf, u32 Len);
-
-/*Read, Modify and Write to an address*/
-void Xil_UtilRMW32(u32 Addr, u32 Mask, u32 Value);
-
-/* Copies source string to destination string */
-int Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size);
-
-/* Copies specified range from source string to destination string */
-int Xil_StrCpyRange(const u8 *Src, u8 *Dst, u32 From, u32 To, u32 MaxSrcLen,
- u32 MaxDstLen);
-
-/* Appends string2 to string1 */
-int Xil_Strcat(char* Str1Ptr, const char* Str2Ptr, const u32 Size);
-
-/* Copies Len bytes from source memory to destination memory */
-int Xil_SecureMemCpy(void * DestPtr, u32 DestPtrLen, const void * SrcPtr, u32 Len);
-
-/* Compares Len bytes from memory1 and memory2 */
-int Xil_MemCmp(const void * Buf1Ptr, const void * Buf2Ptr, u32 Len);
-
-/* Zeroizes the memory of given length */
-int Xil_SecureZeroize(u8 *DataPtr, const u32 Length);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_UTIL_H_ */
-/**
-* @} End of "addtogroup common_utilities".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c9/004963565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c9/004963565243001d18b399c1eb9b3628
deleted file mode 100644
index 9681975..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c9/004963565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,273 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_testio.c
-* @addtogroup common_test_utils
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 08/25/09 First release
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xil_testio.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ****************************/
-/************************** Function Prototypes *****************************/
-
-
-
-/**
- *
- * Endian swap a 16-bit word.
- * @param Data is the 16-bit word to be swapped.
- * @return The endian swapped value.
- *
- */
-static u16 Swap16(u16 Data)
-{
- return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U);
-}
-
-/**
- *
- * Endian swap a 32-bit word.
- * @param Data is the 32-bit word to be swapped.
- * @return The endian swapped value.
- *
- */
-static u32 Swap32(u32 Data)
-{
- u16 Lo16;
- u16 Hi16;
-
- u16 Swap16Lo;
- u16 Swap16Hi;
-
- Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU);
- Lo16 = (u16)(Data & 0x0000FFFFU);
-
- Swap16Lo = Swap16(Lo16);
- Swap16Hi = Swap16(Hi16);
-
- return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi);
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 8-bit wide register IO test where the
-* register is accessed using Xil_Out8 and Xil_In8, and comparing
-* the written values by reading them back.
-*
-* @param Addr: a pointer to the region of memory to be tested.
-* @param Length: Length of the block.
-* @param Value: constant used for writing the memory.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-
-s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value)
-{
- u8 ValueIn;
- s32 Index;
- s32 Status = 0;
-
- for (Index = 0; Index < Length; Index++) {
- Xil_Out8((INTPTR)Addr, Value);
-
- ValueIn = Xil_In8((INTPTR)Addr);
-
- if ((Value != ValueIn) && (Status == 0)) {
- Status = -1;
- break;
- }
- }
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 16-bit wide register IO test. Each location
-* is tested by sequentially writing a 16-bit wide register, reading
-* the register, and comparing value. This function tests three kinds
-* of register IO functions, normal register IO, little-endian register
-* IO, and big-endian register IO. When testing little/big-endian IO,
-* the function performs the following sequence, Xil_Out16LE/Xil_Out16BE,
-* Xil_In16, Compare In-Out values, Xil_Out16, Xil_In16LE/Xil_In16BE,
-* Compare In-Out values. Whether to swap the read-in value before
-* comparing is controlled by the 5th argument.
-*
-* @param Addr: a pointer to the region of memory to be tested.
-* @param Length: Length of the block.
-* @param Value: constant used for writing the memory.
-* @param Kind: Type of test. Acceptable values are:
-* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
-* @param Swap: indicates whether to byte swap the read-in value.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-
-s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap)
-{
- u16 *TempAddr16;
- u16 ValueIn = 0U;
- s32 Index;
- TempAddr16 = Addr;
- Xil_AssertNonvoid(TempAddr16 != NULL);
-
- for (Index = 0; Index < Length; Index++) {
- switch (Kind) {
- case XIL_TESTIO_LE:
- Xil_Out16LE((INTPTR)TempAddr16, Value);
- break;
- case XIL_TESTIO_BE:
- Xil_Out16BE((INTPTR)TempAddr16, Value);
- break;
- default:
- Xil_Out16((INTPTR)TempAddr16, Value);
- break;
- }
-
- ValueIn = Xil_In16((INTPTR)TempAddr16);
-
- if ((Kind != 0) && (Swap != 0)) {
- ValueIn = Swap16(ValueIn);
- }
-
- if (Value != ValueIn) {
- return -1;
- }
-
- /* second round */
- Xil_Out16((INTPTR)TempAddr16, Value);
-
- switch (Kind) {
- case XIL_TESTIO_LE:
- ValueIn = Xil_In16LE((INTPTR)TempAddr16);
- break;
- case XIL_TESTIO_BE:
- ValueIn = Xil_In16BE((INTPTR)TempAddr16);
- break;
- default:
- ValueIn = Xil_In16((INTPTR)TempAddr16);
- break;
- }
-
-
- if ((Kind != 0) && (Swap != 0)) {
- ValueIn = Swap16(ValueIn);
- }
-
- if (Value != ValueIn) {
- return -1;
- }
- TempAddr16 += sizeof(u16);
- }
- return 0;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 32-bit wide register IO test. Each location
-* is tested by sequentially writing a 32-bit wide register, reading
-* the register, and comparing value. This function tests three kinds
-* of register IO functions, normal register IO, little-endian register IO,
-* and big-endian register IO. When testing little/big-endian IO,
-* the function perform the following sequence, Xil_Out32LE/
-* Xil_Out32BE, Xil_In32, Compare, Xil_Out32, Xil_In32LE/Xil_In32BE, Compare.
-* Whether to swap the read-in value *before comparing is controlled
-* by the 5th argument.
-* @param Addr: a pointer to the region of memory to be tested.
-* @param Length: Length of the block.
-* @param Value: constant used for writing the memory.
-* @param Kind: type of test. Acceptable values are:
-* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
-* @param Swap: indicates whether to byte swap the read-in value.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
-{
- u32 *TempAddr;
- u32 ValueIn = 0U;
- s32 Index;
- TempAddr = Addr;
- Xil_AssertNonvoid(TempAddr != NULL);
-
- for (Index = 0; Index < Length; Index++) {
- switch (Kind) {
- case XIL_TESTIO_LE:
- Xil_Out32LE((INTPTR)TempAddr, Value);
- break;
- case XIL_TESTIO_BE:
- Xil_Out32BE((INTPTR)TempAddr, Value);
- break;
- default:
- Xil_Out32((INTPTR)TempAddr, Value);
- break;
- }
-
- ValueIn = Xil_In32((INTPTR)TempAddr);
-
- if ((Kind != 0) && (Swap != 0)) {
- ValueIn = Swap32(ValueIn);
- }
-
- if (Value != ValueIn) {
- return -1;
- }
-
- /* second round */
- Xil_Out32((INTPTR)TempAddr, Value);
-
-
- switch (Kind) {
- case XIL_TESTIO_LE:
- ValueIn = Xil_In32LE((INTPTR)TempAddr);
- break;
- case XIL_TESTIO_BE:
- ValueIn = Xil_In32BE((INTPTR)TempAddr);
- break;
- default:
- ValueIn = Xil_In32((INTPTR)TempAddr);
- break;
- }
-
- if ((Kind != 0) && (Swap != 0)) {
- ValueIn = Swap32(ValueIn);
- }
-
- if (Value != ValueIn) {
- return -1;
- }
- TempAddr += sizeof(u32);
- }
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c9/100cb5595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c9/100cb5595243001d18b399c1eb9b3628
deleted file mode 100644
index 9681975..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c9/100cb5595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,273 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_testio.c
-* @addtogroup common_test_utils
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 08/25/09 First release
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xil_testio.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ****************************/
-/************************** Function Prototypes *****************************/
-
-
-
-/**
- *
- * Endian swap a 16-bit word.
- * @param Data is the 16-bit word to be swapped.
- * @return The endian swapped value.
- *
- */
-static u16 Swap16(u16 Data)
-{
- return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U);
-}
-
-/**
- *
- * Endian swap a 32-bit word.
- * @param Data is the 32-bit word to be swapped.
- * @return The endian swapped value.
- *
- */
-static u32 Swap32(u32 Data)
-{
- u16 Lo16;
- u16 Hi16;
-
- u16 Swap16Lo;
- u16 Swap16Hi;
-
- Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU);
- Lo16 = (u16)(Data & 0x0000FFFFU);
-
- Swap16Lo = Swap16(Lo16);
- Swap16Hi = Swap16(Hi16);
-
- return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi);
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 8-bit wide register IO test where the
-* register is accessed using Xil_Out8 and Xil_In8, and comparing
-* the written values by reading them back.
-*
-* @param Addr: a pointer to the region of memory to be tested.
-* @param Length: Length of the block.
-* @param Value: constant used for writing the memory.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-
-s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value)
-{
- u8 ValueIn;
- s32 Index;
- s32 Status = 0;
-
- for (Index = 0; Index < Length; Index++) {
- Xil_Out8((INTPTR)Addr, Value);
-
- ValueIn = Xil_In8((INTPTR)Addr);
-
- if ((Value != ValueIn) && (Status == 0)) {
- Status = -1;
- break;
- }
- }
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 16-bit wide register IO test. Each location
-* is tested by sequentially writing a 16-bit wide register, reading
-* the register, and comparing value. This function tests three kinds
-* of register IO functions, normal register IO, little-endian register
-* IO, and big-endian register IO. When testing little/big-endian IO,
-* the function performs the following sequence, Xil_Out16LE/Xil_Out16BE,
-* Xil_In16, Compare In-Out values, Xil_Out16, Xil_In16LE/Xil_In16BE,
-* Compare In-Out values. Whether to swap the read-in value before
-* comparing is controlled by the 5th argument.
-*
-* @param Addr: a pointer to the region of memory to be tested.
-* @param Length: Length of the block.
-* @param Value: constant used for writing the memory.
-* @param Kind: Type of test. Acceptable values are:
-* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
-* @param Swap: indicates whether to byte swap the read-in value.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-
-s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap)
-{
- u16 *TempAddr16;
- u16 ValueIn = 0U;
- s32 Index;
- TempAddr16 = Addr;
- Xil_AssertNonvoid(TempAddr16 != NULL);
-
- for (Index = 0; Index < Length; Index++) {
- switch (Kind) {
- case XIL_TESTIO_LE:
- Xil_Out16LE((INTPTR)TempAddr16, Value);
- break;
- case XIL_TESTIO_BE:
- Xil_Out16BE((INTPTR)TempAddr16, Value);
- break;
- default:
- Xil_Out16((INTPTR)TempAddr16, Value);
- break;
- }
-
- ValueIn = Xil_In16((INTPTR)TempAddr16);
-
- if ((Kind != 0) && (Swap != 0)) {
- ValueIn = Swap16(ValueIn);
- }
-
- if (Value != ValueIn) {
- return -1;
- }
-
- /* second round */
- Xil_Out16((INTPTR)TempAddr16, Value);
-
- switch (Kind) {
- case XIL_TESTIO_LE:
- ValueIn = Xil_In16LE((INTPTR)TempAddr16);
- break;
- case XIL_TESTIO_BE:
- ValueIn = Xil_In16BE((INTPTR)TempAddr16);
- break;
- default:
- ValueIn = Xil_In16((INTPTR)TempAddr16);
- break;
- }
-
-
- if ((Kind != 0) && (Swap != 0)) {
- ValueIn = Swap16(ValueIn);
- }
-
- if (Value != ValueIn) {
- return -1;
- }
- TempAddr16 += sizeof(u16);
- }
- return 0;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 32-bit wide register IO test. Each location
-* is tested by sequentially writing a 32-bit wide register, reading
-* the register, and comparing value. This function tests three kinds
-* of register IO functions, normal register IO, little-endian register IO,
-* and big-endian register IO. When testing little/big-endian IO,
-* the function perform the following sequence, Xil_Out32LE/
-* Xil_Out32BE, Xil_In32, Compare, Xil_Out32, Xil_In32LE/Xil_In32BE, Compare.
-* Whether to swap the read-in value *before comparing is controlled
-* by the 5th argument.
-* @param Addr: a pointer to the region of memory to be tested.
-* @param Length: Length of the block.
-* @param Value: constant used for writing the memory.
-* @param Kind: type of test. Acceptable values are:
-* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
-* @param Swap: indicates whether to byte swap the read-in value.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
-{
- u32 *TempAddr;
- u32 ValueIn = 0U;
- s32 Index;
- TempAddr = Addr;
- Xil_AssertNonvoid(TempAddr != NULL);
-
- for (Index = 0; Index < Length; Index++) {
- switch (Kind) {
- case XIL_TESTIO_LE:
- Xil_Out32LE((INTPTR)TempAddr, Value);
- break;
- case XIL_TESTIO_BE:
- Xil_Out32BE((INTPTR)TempAddr, Value);
- break;
- default:
- Xil_Out32((INTPTR)TempAddr, Value);
- break;
- }
-
- ValueIn = Xil_In32((INTPTR)TempAddr);
-
- if ((Kind != 0) && (Swap != 0)) {
- ValueIn = Swap32(ValueIn);
- }
-
- if (Value != ValueIn) {
- return -1;
- }
-
- /* second round */
- Xil_Out32((INTPTR)TempAddr, Value);
-
-
- switch (Kind) {
- case XIL_TESTIO_LE:
- ValueIn = Xil_In32LE((INTPTR)TempAddr);
- break;
- case XIL_TESTIO_BE:
- ValueIn = Xil_In32BE((INTPTR)TempAddr);
- break;
- default:
- ValueIn = Xil_In32((INTPTR)TempAddr);
- break;
- }
-
- if ((Kind != 0) && (Swap != 0)) {
- ValueIn = Swap32(ValueIn);
- }
-
- if (Value != ValueIn) {
- return -1;
- }
- TempAddr += sizeof(u32);
- }
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c9/601a00565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c9/601a00565243001d18b399c1eb9b3628
deleted file mode 100644
index d21e13a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c9/601a00565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,92 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2012 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_mmu.h
-*
-* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions
-*
-* MMU functions equip users to enable MMU, disable MMU and modify default
-* memory attributes of MMU table as per the need.
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 01/12/12 Initial version
-* 4.2 pkp 07/21/14 Included xil_types.h file which contains definition for
-* u32 which resolves issue of CR#805869
-* 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00b kpc 03/07/13 First release
-* 5.4 pkp 09/11/15 Change the description for XOcm_Remap function
-*
-*
-******************************************************************************/
-
-
-/***************************** Include Files *********************************/
-#include "xil_misc_psreset_api.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for ddr reset.
-*
-*
-* @return N/A.
-*
-******************************************************************************/
-void XDdr_ResetHw(void)
-{
- u32 RegVal;
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert and deassert the ddr softreset bit */
- RegVal = Xil_In32(XDDRC_CTRL_BASEADDR);
- RegVal &= (u32)(~XDDRPS_CTRL_RESET_MASK);
- Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
- RegVal |= ((u32)XDDRPS_CTRL_RESET_MASK);
- Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
-
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for remapping the ocm memory region
-* to postbootrom state.
-*
-* @return N/A.
-*
-******************************************************************************/
-void XOcm_Remap(void)
-{
- u32 RegVal;
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Map the ocm region to postbootrom state */
- RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR);
- RegVal = (RegVal & (u32)(~XSLCR_OCM_CFG_HIADDR_MASK)) | (u32)XSLCR_OCM_CFG_RESETVAL;
- Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for SMC reset sequence
-*
-* @param BaseAddress of the interface
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSmc_ResetHw(u32 BaseAddress)
-{
- u32 RegVal;
-
- /* Clear the interuupts */
- RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET);
- RegVal = RegVal | (u32)XSMC_MEMC_CLR_CONFIG_MASK;
- Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal);
- /* Clear the idle counter registers */
- Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0U);
- Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0U);
- /* Update the ecc registers with reset values */
- Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET,
- XSMC_ECC_MEMCFG1_RESET_VAL);
- Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD1_OFFSET,
- XSMC_ECC_MEMCMD1_RESET_VAL);
- Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD2_OFFSET,
- XSMC_ECC_MEMCMD2_RESET_VAL);
-
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for updating the slcr mio registers
-* with reset values
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_MioWriteResetValues(void)
-{
- u32 i;
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Update all the MIO registers with reset values */
- for (i=0U; i<=1U;i++)
- {
- Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
- XSLCR_MIO_PIN_00_RESET_VAL);
- }
- for (; i<=8U;i++)
- {
- Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
- XSLCR_MIO_PIN_02_RESET_VAL);
- }
- for (; i<=53U ;i++)
- {
- Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
- XSLCR_MIO_PIN_00_RESET_VAL);
- }
-
-
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for updating the slcr pll registers
-* with reset values
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_PllWriteResetValues(void)
-{
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
-
- /* update the pll control registers with reset values */
- Xil_Out32(XSLCR_IO_PLL_CTRL_ADDR, XSLCR_IO_PLL_CTRL_RESET_VAL);
- Xil_Out32(XSLCR_ARM_PLL_CTRL_ADDR, XSLCR_ARM_PLL_CTRL_RESET_VAL);
- Xil_Out32(XSLCR_DDR_PLL_CTRL_ADDR, XSLCR_DDR_PLL_CTRL_RESET_VAL);
- /* update the pll config registers with reset values */
- Xil_Out32(XSLCR_IO_PLL_CFG_ADDR, XSLCR_IO_PLL_CFG_RESET_VAL);
- Xil_Out32(XSLCR_ARM_PLL_CFG_ADDR, XSLCR_ARM_PLL_CFG_RESET_VAL);
- Xil_Out32(XSLCR_DDR_PLL_CFG_ADDR, XSLCR_DDR_PLL_CFG_RESET_VAL);
- /* update the clock control registers with reset values */
- Xil_Out32(XSLCR_ARM_CLK_CTRL_ADDR, XSLCR_ARM_CLK_CTRL_RESET_VAL);
- Xil_Out32(XSLCR_DDR_CLK_CTRL_ADDR, XSLCR_DDR_CLK_CTRL_RESET_VAL);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for disabling the level shifters
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_DisableLevelShifters(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Disable the level shifters */
- RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_LVL_SHFTR_EN_MASK);
- Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal);
-
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for OCM software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_OcmReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_OCM_RST_CTRL_VAL);
- Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_OCM_RST_CTRL_VAL);
- Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for Ethernet software reset from
-* the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_EmacPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_GEM_RST_CTRL_VAL);
- Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_GEM_RST_CTRL_VAL);
- Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for USB software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_UsbPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_USB_RST_CTRL_VAL);
- Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_USB_RST_CTRL_VAL);
- Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for QSPI software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_QspiPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_QSPI_RST_CTRL_VAL);
- Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_QSPI_RST_CTRL_VAL);
- Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for SPI software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_SpiPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_SPI_RST_CTRL_VAL);
- Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_SPI_RST_CTRL_VAL);
- Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for i2c software reset from the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_I2cPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_I2C_RST_CTRL_VAL);
- Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_I2C_RST_CTRL_VAL);
- Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for UART software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_UartPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_UART_RST_CTRL_VAL);
- Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_UART_RST_CTRL_VAL);
- Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for CAN software reset from slcr
-* registers
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_CanPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_CAN_RST_CTRL_VAL);
- Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_CAN_RST_CTRL_VAL);
- Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for SMC software reset from the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_SmcPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_SMC_RST_CTRL_VAL);
- Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_SMC_RST_CTRL_VAL);
- Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for DMA controller software reset
-* from the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_DmaPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_DMAC_RST_CTRL_VAL);
- Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_DMAC_RST_CTRL_VAL);
- Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for Gpio AMBA software reset from
-* the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_GpioPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
- RegVal = RegVal | ((u32)XSLCR_GPIO_RST_CTRL_VAL);
- Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_GPIO_RST_CTRL_VAL);
- Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c9/a04f9d575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c9/a04f9d575243001d18b399c1eb9b3628
deleted file mode 100644
index a270af6..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c9/a04f9d575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,691 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xscugic_hw.h
-* @addtogroup scugic_v4_6
-* @{
-*
-* This header file contains identifiers and HW access functions (or
-* macros) that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-* The driver functions/APIs are defined in xscugic.h.
-*
-* This GIC device has two parts, a distributor and CPU interface(s). Each part
-* has separate register definition sections.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------------
-* 1.00a drg 01/19/10 First release
-* 1.01a sdm 11/09/11 "xil_exception.h" added as include.
-* Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
-* added to enable or disable interrupts based on
-* Distributor Register base address. Normally users use
-* XScuGic instance and call XScuGic_Enable or
-* XScuGic_Disable to enable/disable interrupts. These
-* new macros are provided when user does not want to
-* use an instance pointer but still wants to enable or
-* disable interrupts.
-* Function prototypes for functions (present in newly
-* added file xscugic_hw.c) are added.
-* 1.03a srt 02/27/13 Moved Offset calculation macros from *_hw.c (CR
-* 702687).
-* 1.04a hk 05/04/13 Fix for CR#705621. Moved function prototypes
-* XScuGic_SetPriTrigTypeByDistAddr and
-* XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
-* 3.0 pkp 12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
-* Zynq Ultrascale Mp
-* 3.0 kvn 02/13/14 Modified code for MISRA-C:2012 compliance.
-* 3.2 pkp 11/09/15 Corrected the interrupt processsor target mask value
-* for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
-* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
-* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
-* API's can be used by applications to unmap specific/all
-* interrupts from target CPU. It fixes CR#992490.
-* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
-* 4.1 asa 03/30/19 Removed macros for XScuGic_EnableIntr, and
-* XScuGic_DisableIntr. These are now C functions. This
-* change was to fix CR-1024716.
-* 4.1 mus 06/12/19 Updated XSCUGIC_MAX_NUM_INTR_INPUTS for Versal.
-* 4.6 sk 06/07/21 Delete the commented macro code to fix the MISRA-C warning.
-* 4.6 sk 08/05/21 Fix Scugic Misrac violations.
-*
-*
-*
-******************************************************************************/
-
-#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
-#define XSCUGIC_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-#include "xil_exception.h"
-#include "bspconfig.h"
-
-/************************** Constant Definitions *****************************/
-#if defined (versal) && !defined(ARMR5)
-#define GICv3
-#endif
-
-/*
- * The maximum number of interrupts supported by the hardware.
- */
-#ifdef PLATFORM_ZYNQ
-#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */
-#elif defined (versal)
-#define XSCUGIC_MAX_NUM_INTR_INPUTS 192U
-#else
-#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
-#endif
-
-/*
- * First Interrupt Id for SPI interrupts.
- */
-#define XSCUGIC_SPI_INT_ID_START 0x20
-/*
- * The maximum priority value that can be used in the GIC.
- */
-#define XSCUGIC_MAX_INTR_PRIO_VAL 248U
-#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U
-
-/** @name Distributor Interface Register Map
- *
- * Define the offsets from the base address for all Distributor registers of
- * the interrupt controller, some registers may be reserved in the hardware
- * device.
- * @{
- */
-#define XSCUGIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable
- Register */
-#define XSCUGIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller
- Type Register */
-#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID
- Register */
-#define XSCUGIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security
- Register */
-#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set
- Register */
-#define XSCUGIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */
-#define XSCUGIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set
- Register */
-#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear
- Register */
-#define XSCUGIC_ACTIVE_OFFSET 0x00000300U /**< Active Status Register */
-#define XSCUGIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */
-#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target
- Register 0x800-0x8FB */
-#define XSCUGIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration
- Register 0xC00-0xCFC */
-#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */
-#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register
- 0xd04-0xd7C */
-#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration
- Register */
-#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered
- Interrupt Register */
-#define XSCUGIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */
-#if defined (GICv3)
-#define XSCUGIC_PCELLID_OFFSET 0x0000FFF0U /**< Pcell ID Register */
-#else
-#define XSCUGIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */
-#endif
-/* @} */
-
-/** @name Distributor Enable Register
- * Controls if the distributor response to external interrupt inputs.
- * @{
- */
-#if defined (GICv3)
-#define XSCUGIC_EN_INT_MASK 0x00000003U /**< Interrupt In Enable */
-#else
-#define XSCUGIC_EN_INT_MASK 0x00000001U /**< Interrupt In Enable */
-#endif
-/* @} */
-
-/** @name Interrupt Controller Type Register
- * @{
- */
-#define XSCUGIC_LSPI_MASK 0x0000F800U /**< Number of Lockable
- Shared Peripheral
- Interrupts*/
-#define XSCUGIC_DOMAIN_MASK 0x00000400U /**< Number os Security domains*/
-#define XSCUGIC_CPU_NUM_MASK 0x000000E0U /**< Number of CPU Interfaces */
-#define XSCUGIC_NUM_INT_MASK 0x0000001FU /**< Number of Interrupt IDs */
-/* @} */
-
-/** @name Implementor ID Register
- * Implementor and revision information.
- * @{
- */
-#define XSCUGIC_REV_MASK 0x00FFF000U /**< Revision Number */
-#define XSCUGIC_IMPL_MASK 0x00000FFFU /**< Implementor */
-/* @} */
-
-/** @name Interrupt Security Registers
- * Each bit controls the security level of an interrupt, either secure or non
- * secure. These registers can only be accessed using secure read and write.
- * There are registers for each of the CPU interfaces at offset 0x080. A
- * register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x084.
- * @{
- */
-#define XSCUGIC_INT_NS_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Enable Set Register
- * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
- * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
- * bit to 0.
- * There are registers for each of the CPU interfaces at offset 0x100. With up
- * to 8 registers aliased to the same address. A register set for the SPI
- * interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x104.
- * @{
- */
-#define XSCUGIC_INT_EN_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Enable Clear Register
- * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
- * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
- * sets the corresponding bit to 0.
- * There are registers for each of the CPU interfaces at offset 0x180. With up
- * to 8 registers aliased to the same address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x184.
- * @{
- */
-#define XSCUGIC_INT_CLR_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Pending Set Register
- * Each bit controls the Pending or Active and Pending state of an interrupt, a
- * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
- * an interrupt to the pending state.
- * There are registers for each of the CPU interfaces at offset 0x200. With up
- * to 8 registers aliased to the same address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x204.
- * @{
- */
-#define XSCUGIC_PEND_SET_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Pending Clear Register
- * Each bit can clear the Pending or Active and Pending state of an interrupt, a
- * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
- * clears the pending state of an interrupt.
- * There are registers for each of the CPU interfaces at offset 0x280. With up
- * to 8 registers aliased to the same address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x284.
- * @{
- */
-#define XSCUGIC_PEND_CLR_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Active Status Register
- * Each bit provides the Active status of an interrupt, a
- * 0 is not Active, a 1 is Active. This is a read only register.
- * There are registers for each of the CPU interfaces at offset 0x300. With up
- * to 8 registers aliased to each address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 32 of these registers staring at location 0x380.
- * @{
- */
-#define XSCUGIC_ACTIVE_MASK 0x00000001U /**< Each bit corresponds to an
- INT_ID */
-/* @} */
-
-/** @name Priority Level Register
- * Each byte in a Priority Level Register sets the priority level of an
- * interrupt. Reading the register provides the priority level of an interrupt.
- * There are registers for each of the CPU interfaces at offset 0x400 through
- * 0x41C. With up to 8 registers aliased to each address.
- * 0 is highest priority, 0xFF is lowest.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 255 of these registers staring at location 0x420.
- * @{
- */
-#define XSCUGIC_PRIORITY_MASK 0x000000FFU /**< Each Byte corresponds to an
- INT_ID */
-#define XSCUGIC_PRIORITY_MAX 0x000000FFU /**< Highest value of a priority
- actually the lowest priority*/
-/* @} */
-
-/** @name SPI Target Register 0x800-0x8FB
- * Each byte references a separate SPI and programs which of the up to 8 CPU
- * interfaces are sent a Pending interrupt.
- * There are registers for each of the CPU interfaces at offset 0x800 through
- * 0x81C. With up to 8 registers aliased to each address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 255 of these registers staring at location 0x820.
- *
- * This driver does not support multiple CPU interfaces. These are included
- * for complete documentation.
- * @{
- */
-#define XSCUGIC_SPI_CPU7_MASK 0x00000080U /**< CPU 7 Mask*/
-#define XSCUGIC_SPI_CPU6_MASK 0x00000040U /**< CPU 6 Mask*/
-#define XSCUGIC_SPI_CPU5_MASK 0x00000020U /**< CPU 5 Mask*/
-#define XSCUGIC_SPI_CPU4_MASK 0x00000010U /**< CPU 4 Mask*/
-#define XSCUGIC_SPI_CPU3_MASK 0x00000008U /**< CPU 3 Mask*/
-#define XSCUGIC_SPI_CPU2_MASK 0x00000004U /**< CPU 2 Mask*/
-#define XSCUGIC_SPI_CPU1_MASK 0x00000002U /**< CPU 1 Mask*/
-#define XSCUGIC_SPI_CPU0_MASK 0x00000001U /**< CPU 0 Mask*/
-/* @} */
-
-/** @name Interrupt Configuration Register 0xC00-0xCFC
- * The interrupt configuration registers program an SFI to be active HIGH level
- * sensitive or rising edge sensitive.
- * Each bit pair describes the configuration for an INT_ID.
- * SFI Read Only b10 always
- * PPI Read Only depending on how the PPIs are configured.
- * b01 Active HIGH level sensitive
- * b11 Rising edge sensitive
- * SPI LSB is read only.
- * b01 Active HIGH level sensitive
- * b11 Rising edge sensitive/
- * There are registers for each of the CPU interfaces at offset 0xC00 through
- * 0xC04. With up to 8 registers aliased to each address.
- * A register set for the SPI interrupts is available to all CPU interfaces.
- * There are up to 255 of these registers staring at location 0xC08.
- * @{
- */
-#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */
-/* @} */
-
-/** @name PPI Status Register
- * Enables an external AMBA master to access the status of the PPI inputs.
- * A CPU can only read the status of its local PPI signals and cannot read the
- * status for other CPUs.
- * This register is aliased for each CPU interface.
- * @{
- */
-#define XSCUGIC_PPI_C15_MASK 0x00008000U /**< PPI Status */
-#define XSCUGIC_PPI_C14_MASK 0x00004000U /**< PPI Status */
-#define XSCUGIC_PPI_C13_MASK 0x00002000U /**< PPI Status */
-#define XSCUGIC_PPI_C12_MASK 0x00001000U /**< PPI Status */
-#define XSCUGIC_PPI_C11_MASK 0x00000800U /**< PPI Status */
-#define XSCUGIC_PPI_C10_MASK 0x00000400U /**< PPI Status */
-#define XSCUGIC_PPI_C09_MASK 0x00000200U /**< PPI Status */
-#define XSCUGIC_PPI_C08_MASK 0x00000100U /**< PPI Status */
-#define XSCUGIC_PPI_C07_MASK 0x00000080U /**< PPI Status */
-#define XSCUGIC_PPI_C06_MASK 0x00000040U /**< PPI Status */
-#define XSCUGIC_PPI_C05_MASK 0x00000020U /**< PPI Status */
-#define XSCUGIC_PPI_C04_MASK 0x00000010U /**< PPI Status */
-#define XSCUGIC_PPI_C03_MASK 0x00000008U /**< PPI Status */
-#define XSCUGIC_PPI_C02_MASK 0x00000004U /**< PPI Status */
-#define XSCUGIC_PPI_C01_MASK 0x00000002U /**< PPI Status */
-#define XSCUGIC_PPI_C00_MASK 0x00000001U /**< PPI Status */
-/* @} */
-
-/** @name SPI Status Register 0xd04-0xd7C
- * Enables an external AMBA master to access the status of the SPI inputs.
- * There are up to 63 registers if the maximum number of SPI inputs are
- * configured.
- * @{
- */
-#define XSCUGIC_SPI_N_MASK 0x00000001U /**< Each bit corresponds to an SPI
- input */
-/* @} */
-
-/** @name AHB Configuration Register
- * Provides the status of the CFGBIGEND input signal and allows the endianness
- * of the GIC to be set.
- * @{
- */
-#define XSCUGIC_AHB_END_MASK 0x00000004U /**< 0-GIC uses little Endian,
- 1-GIC uses Big Endian */
-#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002U /**< 0-Uses CFGBIGEND control,
- 1-use the AHB_END bit */
-#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U /**< State of CFGBIGEND */
-
-/* @} */
-
-/** @name Software Triggered Interrupt Register
- * Controls issuing of software interrupts.
- * @{
- */
-#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000U
-#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U /**< Target List filter
- b00-Use the target List
- b01-All CPUs except requester
- b10-To Requester
- b11-reserved */
-#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U /**< CPU Target list */
-#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U /**< 0= Use a secure interrupt */
-#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU /**< Set to the INTID
- signaled to the CPU*/
-/* @} */
-
-/** @name CPU Interface Register Map
- *
- * Define the offsets from the base address for all CPU registers of the
- * interrupt controller, some registers may be reserved in the hardware device.
- * @{
- */
-#define XSCUGIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control
- Register */
-#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */
-#define XSCUGIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */
-#define XSCUGIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */
-#define XSCUGIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */
-#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */
-#define XSCUGIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt
- Register */
-#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure
- Binary Point Register */
-
-/**< 0x00000020 to 0x00000FBC are reserved and should not be read or written
- * to. */
-/* @} */
-
-
-/** @name Control Register
- * CPU Interface Control register definitions
- * All bits are defined here although some are not available in the non-secure
- * mode.
- * @{
- */
-#define XSCUGIC_CNTR_SBPR_MASK 0x00000010U /**< Secure Binary Pointer,
- 0=separate registers,
- 1=both use bin_pt_s */
-#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008U /**< Use nFIQ_C for secure
- interrupts,
- 0= use IRQ for both,
- 1=Use FIQ for secure, IRQ for non*/
-#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U /**< Ack control for secure or non secure */
-#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002U /**< Non Secure enable */
-#define XSCUGIC_CNTR_EN_S_MASK 0x00000001U /**< Secure enable, 0=Disabled, 1=Enabled */
-/* @} */
-
-
-/** @name Binary Point Register
- * Binary Point register definitions
- * @{
- */
-
-#define XSCUGIC_BIN_PT_MASK 0x00000007U /**< Binary point mask value
- Value Secure Non-secure
- b000 0xFE 0xFF
- b001 0xFC 0xFE
- b010 0xF8 0xFC
- b011 0xF0 0xF8
- b100 0xE0 0xF0
- b101 0xC0 0xE0
- b110 0x80 0xC0
- b111 0x00 0x80
- */
-/*@}*/
-
-/** @name Interrupt Acknowledge Register
- * Interrupt Acknowledge register definitions
- * Identifies the current Pending interrupt, and the CPU ID for software
- * interrupts.
- */
-#define XSCUGIC_ACK_INTID_MASK 0x000003FFU /**< Interrupt ID */
-#define XSCUGIC_CPUID_MASK 0x00000C00U /**< CPU ID */
-/* @} */
-
-/** @name End of Interrupt Register
- * End of Interrupt register definitions
- * Allows the CPU to signal the GIC when it completes an interrupt service
- * routine.
- */
-#define XSCUGIC_EOI_INTID_MASK 0x000003FFU /**< Interrupt ID */
-
-/* @} */
-
-/** @name Running Priority Register
- * Running Priority register definitions
- * Identifies the interrupt priority level of the highest priority active
- * interrupt.
- */
-#define XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU /**< Interrupt Priority */
-/* @} */
-
-#if defined (GICv3)
-#define XSCUGIC_IROUTER_BASE_OFFSET 0x6000U
-#endif
-/*
- * Highest Pending Interrupt register definitions
- * Identifies the interrupt priority of the highest priority pending interrupt
- */
-#define XSCUGIC_PEND_INTID_MASK 0x000003FFU /**< Pending Interrupt ID */
-/* @} */
-#if defined (GICv3)
-/** @name ReDistributor Interface Register Map
- *
- * @{
- */
-#define XSCUGIC_RDIST_OFFSET 0x80000U
-#define XSCUGIC_RDIST_BASE_ADDRESS (XPAR_SCUGIC_0_DIST_BASEADDR + XSCUGIC_RDIST_OFFSET)
-#define XSCUGIC_RDIST_SGI_PPI_OFFSET 0x90000U
-#define XSCUGIC_RDIST_SGI_PPI_BASE_ADDRESS (XPAR_SCUGIC_0_DIST_BASEADDR + XSCUGIC_RDIST_SGI_PPI_OFFSET)
-#define XSCUGIC_RDIST_ISENABLE_OFFSET 0x100U
-#define XSCUGIC_RDIST_IPRIORITYR_OFFSET 0x400U
-#define XSCUGIC_RDIST_IGROUPR_OFFSET 0x80U
-#define XSCUGIC_RDIST_GRPMODR_OFFSET 0xD00U
-#define XSCUGIC_RDIST_INT_CONFIG_OFFSET 0xC00U
-#define XSCUGIC_RDIST_WAKER_OFFSET 0x14U
-#define XSCUGIC_SGIR_EL1_INITID_SHIFT 24U
-
-/*
- * GICR_IGROUPR register definitions
- */
-#if EL3
-#define XSCUGIC_DEFAULT_SECURITY 0x0U
-#else
-#define XSCUGIC_DEFAULT_SECURITY 0xFFFFFFFFU
-#endif
-/*
- * GICR_WAKER register definitions
- */
-#define XSCUGIC_RDIST_WAKER_LOW_POWER_STATE_MASK 0x7
-#endif
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Configuration Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Priority Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Routing Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_IROUTER_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_IROUTER_BASE_OFFSET + (InterruptID * 8))
-
-/****************************************************************************/
-/**
-*
-* Read the SPI Target Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
-/****************************************************************************/
-/**
-*
-* Read the SPI Target Register offset for an interrupt id.
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_SECURITY_TARGET_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_SECURITY_OFFSET + (((InterruptID)/32U)*4U))
-
-/****************************************************************************/
-/**
-*
-* Read the Re-distributor Interrupt configuration register offset
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_RDIST_INT_CONFIG_OFFSET + ((InterruptID /16)*4))
-
-/****************************************************************************/
-/**
-*
-* Read the Re-distributor Interrupt Priority register offset
-*
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC(InterruptID) \
- ((u32)XSCUGIC_RDIST_IPRIORITYR_OFFSET + (InterruptID * 4))
-/****************************************************************************/
-/**
-*
-* Read the Interrupt Clear-Enable Register offset for an interrupt ID
-*
-* @param Register is the register offset for the clear/enable bank.
-* @param InterruptID is the interrupt number.
-*
-* @return The 32-bit value of the offset
-*
-* @note
-*
-*****************************************************************************/
-#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
- ((Register) + (((InterruptID)/32U) * 4U))
-
-/****************************************************************************/
-/**
-*
-* Read the given Intc register.
-*
-* @param BaseAddress is the base address of the device.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_ReadReg(BaseAddress, RegOffset) \
- (Xil_In32((BaseAddress) + (RegOffset)))
-
-
-/****************************************************************************/
-/**
-*
-* Write the given Intc register.
-*
-* @param BaseAddress is the base address of the device.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
- (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
-
-
-/************************** Function Prototypes ******************************/
-
-void XScuGic_DeviceInterruptHandler(void *DeviceId);
-s32 XScuGic_DeviceInitialize(u32 DeviceId);
-void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
- Xil_InterruptHandler IntrHandler, void *CallBackRef);
-void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
- u8 Priority, u8 Trigger);
-void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
- u8 *Priority, u8 *Trigger);
-void XScuGic_InterruptMapFromCpuByDistAddr(u32 DistBaseAddress,
- u8 Cpu_Id, u32 Int_Id);
-void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
- u8 Cpu_Id, u32 Int_Id);
-void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
- u8 Cpu_Id);
-void XScuGic_EnableIntr (u32 DistBaseAddress, u32 Int_Id);
-void XScuGic_DisableIntr (u32 DistBaseAddress, u32 Int_Id);
-/************************** Variable Definitions *****************************/
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c9/c0555db75243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c9/c0555db75243001d18b399c1eb9b3628
deleted file mode 100644
index c63db8f..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c9/c0555db75243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,11 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c9/f08bec585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c9/f08bec585243001d18b399c1eb9b3628
deleted file mode 100644
index efa60da..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/c9/f08bec585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,66 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************
-*
-* @file sleep.c
-*
-* This function provides a second delay using the Global Timer register in
-* the ARM Cortex A9 MP core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm 11/11/09 First release
-* 3.07a sgd 07/05/12 Updated sleep function to make use Global
-* 6.0 asa 08/15/16 Updated the sleep signature. Fix for CR#956899.
-* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
-* implementation. Now sleep routines will use Timer
-* specified by the user (i.e. Global timer/TTC timer)
-*
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "sleep.h"
-#include "xtime_l.h"
-#include "xparameters.h"
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#include "xil_sleeptimer.h"
-#endif
-
-/*****************************************************************************/
-/*
-*
-* This API is used to provide delays in seconds
-*
-* @param seconds requested
-*
-* @return 0 always
-*
-* @note None.
-*
-****************************************************************************/
-unsigned sleep_A9(unsigned int seconds)
-{
-#if defined (SLEEP_TIMER_BASEADDR)
- Xil_SleepTTCCommon(seconds, COUNTS_PER_SECOND);
-#else
- XTime tEnd, tCur;
-
- XTime_GetTime(&tCur);
- tEnd = tCur + (((XTime) seconds) * COUNTS_PER_SECOND);
- do
- {
- XTime_GetTime(&tCur);
- } while (tCur < tEnd);
-#endif
-
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ca/0141f9595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ca/0141f9595243001d18b399c1eb9b3628
deleted file mode 100644
index cd9ec37..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ca/0141f9595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,380 +0,0 @@
-/*---------------------------------------------------------------------------/
-/ FatFs - Configuration file
-/---------------------------------------------------------------------------*/
-
-
-#define FFCONF_DEF 63463 /* Revision ID */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xparameters.h"
-
-/*---------------------------------------------------------------------------/
-/ Function Configurations
-/---------------------------------------------------------------------------*/
-
-#ifdef FILE_SYSTEM_READ_ONLY
-#define FF_FS_READONLY 1 /* 1:Read only */
-#else
-#define FF_FS_READONLY 0 /* 0:Read/Write */
-#endif
-/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
-/ Read-only configuration removes writing API functions, f_write(), f_sync(),
-/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
-/ and optional writing functions as well. */
-
-
-#define FF_FS_MINIMIZE 0
-/* This option defines minimization level to remove some basic API functions.
-/
-/ 0: Basic functions are fully enabled.
-/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
-/ are removed.
-/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
-/ 3: f_lseek() function is removed in addition to 2. */
-
-
-#if FILE_SYSTEM_USE_STRFUNC == 0
-#define FF_USE_STRFUNC 0 /* 0:Disable */
-#elif FILE_SYSTEM_USE_STRFUNC == 1
-#define FF_USE_STRFUNC 1 /* 1:Enable */
-#elif FILE_SYSTEM_USE_STRFUNC == 2
-#define FF_USE_STRFUNC 2 /* 2:Enable */
-#endif
-/* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf().
-/
-/ 0: Disable string functions.
-/ 1: Enable without LF-CRLF conversion.
-/ 2: Enable with LF-CRLF conversion. */
-
-
-#define FF_USE_FIND 0
-/* This option switches filtered directory read functions, f_findfirst() and
-/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
-
-#ifdef FILE_SYSTEM_USE_MKFS
-#define FF_USE_MKFS 1 /* 1:Enable */
-#else
-#define FF_USE_MKFS 0 /* 0:Disable */
-#endif
-/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
-
-
-#define FF_USE_FASTSEEK 0
-/* This option switches fast seek function. (0:Disable or 1:Enable) */
-
-
-#define FF_USE_EXPAND 0
-/* This option switches f_expand function. (0:Disable or 1:Enable) */
-
-
-#ifdef FILE_SYSTEM_USE_CHMOD
-#define FF_USE_CHMOD 1 /* 1:Enable */
-#else
-#define FF_USE_CHMOD 0 /* 0:Disable */
-#endif
-/* This option switches attribute manipulation functions, f_chmod() and f_utime().
-/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */
-
-
-#define FF_USE_LABEL 0
-/* This option switches volume label functions, f_getlabel() and f_setlabel().
-/ (0:Disable or 1:Enable) */
-
-
-#define FF_USE_FORWARD 0
-/* This option switches f_forward() function. (0:Disable or 1:Enable) */
-
-
-/*---------------------------------------------------------------------------/
-/ Locale and Namespace Configurations
-/---------------------------------------------------------------------------*/
-
-#define FF_CODE_PAGE 932
-/* This option specifies the OEM code page to be used on the target system.
-/ Incorrect code page setting can cause a file open failure.
-/
-/ 437 - U.S.
-/ 720 - Arabic
-/ 737 - Greek
-/ 771 - KBL
-/ 775 - Baltic
-/ 850 - Latin 1
-/ 852 - Latin 2
-/ 855 - Cyrillic
-/ 857 - Turkish
-/ 860 - Portuguese
-/ 861 - Icelandic
-/ 862 - Hebrew
-/ 863 - Canadian French
-/ 864 - Arabic
-/ 865 - Nordic
-/ 866 - Russian
-/ 869 - Greek 2
-/ 932 - Japanese (DBCS)
-/ 936 - Simplified Chinese (DBCS)
-/ 949 - Korean (DBCS)
-/ 950 - Traditional Chinese (DBCS)
-/ 0 - Include all code pages above and configured by f_setcp()
-*/
-
-
-#ifdef FILE_SYSTEM_USE_LFN
-#define FF_USE_LFN FILE_SYSTEM_USE_LFN /* 0 to 3 */
-#else
-#define FF_USE_LFN 0 /* 0 to 3 */
-#endif
-#define FF_MAX_LFN 255
-/* The FF_USE_LFN switches the support for LFN (long file name).
-/
-/ 0: Disable LFN. FF_MAX_LFN has no effect.
-/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
-/ 2: Enable LFN with dynamic working buffer on the STACK.
-/ 3: Enable LFN with dynamic working buffer on the HEAP.
-/
-/ To enable the LFN, ffunicode.c needs to be added to the project. The LFN function
-/ requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and
-/ additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled.
-/ The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can
-/ be in range of 12 to 255. It is recommended to be set 255 to fully support LFN
-/ specification.
-/ When use stack for the working buffer, take care on stack overflow. When use heap
-/ memory for the working buffer, memory management functions, ff_memalloc() and
-/ ff_memfree() in ffsystem.c, need to be added to the project. */
-
-
-#define FF_LFN_UNICODE 0
-/* This option switches the character encoding on the API when LFN is enabled.
-/
-/ 0: ANSI/OEM in current CP (TCHAR = char)
-/ 1: Unicode in UTF-16 (TCHAR = WCHAR)
-/ 2: Unicode in UTF-8 (TCHAR = char)
-/ 3: Unicode in UTF-32 (TCHAR = DWORD)
-/
-/ Also behavior of string I/O functions will be affected by this option.
-/ When LFN is not enabled, this option has no effect. */
-
-
-#define FF_LFN_BUF 255
-#define FF_SFN_BUF 12
-/* This set of options defines size of file name members in the FILINFO structure
-/ which is used to read out directory items. These values should be suffcient for
-/ the file names to read. The maximum possible length of the read file name depends
-/ on character encoding. When LFN is not enabled, these options have no effect. */
-
-
-#define FF_STRF_ENCODE 3
-/* When FF_LFN_UNICODE >= 1 with LFN enabled, string I/O functions, f_gets(),
-/ f_putc(), f_puts and f_printf() convert the character encoding in it.
-/ This option selects assumption of character encoding ON THE FILE to be
-/ read/written via those functions.
-/
-/ 0: ANSI/OEM in current CP
-/ 1: Unicode in UTF-16LE
-/ 2: Unicode in UTF-16BE
-/ 3: Unicode in UTF-8
-*/
-
-
-#if FILE_SYSTEM_SET_FS_RPATH == 0
-#define FF_FS_RPATH 0U
-#elif FILE_SYSTEM_SET_FS_RPATH == 1
-#define FF_FS_RPATH 1U
-#elif FILE_SYSTEM_SET_FS_RPATH == 2
-#define FF_FS_RPATH 2U
-#endif
-/* This option configures support for relative path.
-/
-/ 0: Disable relative path and remove related functions.
-/ 1: Enable relative path. f_chdir() and f_chdrive() are available.
-/ 2: f_getcwd() function is available in addition to 1.
-*/
-
-
-/*---------------------------------------------------------------------------/
-/ Drive/Volume Configurations
-/---------------------------------------------------------------------------*/
-
-#if FILE_SYSTEM_NUM_LOGIC_VOL == 1
-#define FF_VOLUMES 1U
-#elif FILE_SYSTEM_NUM_LOGIC_VOL == 2
-#define FF_VOLUMES 2U
-#elif FILE_SYSTEM_NUM_LOGIC_VOL == 3
-#define FF_VOLUMES 3U
-#elif FILE_SYSTEM_NUM_LOGIC_VOL == 4
-#define FF_VOLUMES 4U
-#elif FILE_SYSTEM_NUM_LOGIC_VOL == 5
-#define FF_VOLUMES 5U
-#elif FILE_SYSTEM_NUM_LOGIC_VOL == 6
-#define FF_VOLUMES 6U
-#elif FILE_SYSTEM_NUM_LOGIC_VOL == 7
-#define FF_VOLUMES 7U
-#elif FILE_SYSTEM_NUM_LOGIC_VOL == 8
-#define FF_VOLUMES 8U
-#elif FILE_SYSTEM_NUM_LOGIC_VOL == 9
-#define FF_VOLUMES 9U
-#else
-#define FF_VOLUMES 10U
-#endif
-/* Number of volumes (logical drives) to be used. (1-10) */
-
-
-#define FF_STR_VOLUME_ID 0
-#define FF_VOLUME_STRS "RAM","NAND","CF","SD","SD2","USB","USB2","USB3"
-/* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings.
-/ When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive
-/ number in the path name. FF_VOLUME_STRS defines the volume ID strings for each
-/ logical drives. Number of items must not be less than FF_VOLUMES. Valid
-/ characters for the volume ID strings are A-Z, a-z and 0-9, however, they are
-/ compared in case-insensitive. If FF_STR_VOLUME_ID >= 1 and FF_VOLUME_STRS is
-/ not defined, a user defined volume string table needs to be defined as:
-/
-/ const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb",...
-*/
-
-
-#ifdef FILE_SYSTEM_MULTI_PARTITION
-#define FF_MULTI_PARTITION 1 /* 1:Enable multiple partition */
-#else
-#define FF_MULTI_PARTITION 0 /* 0:Single partition */
-#endif
-/* This option switches support for multiple volumes on the physical drive.
-/ By default (0), each logical drive number is bound to the same physical drive
-/ number and only an FAT volume found on the physical drive will be mounted.
-/ When this function is enabled (1), each logical drive number can be bound to
-/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
-/ function will be available. */
-
-
-#define FF_MIN_SS 512
-#define FF_MAX_SS 512
-/* This set of options configures the range of sector size to be supported. (512,
-/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and
-/ harddisk. But a larger value may be required for on-board flash memory and some
-/ type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured
-/ for variable sector size mode and disk_ioctl() function needs to implement
-/ GET_SECTOR_SIZE command. */
-
-
-#define FF_USE_TRIM 0
-/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable)
-/ To enable Trim function, also CTRL_TRIM command should be implemented to the
-/ disk_ioctl() function. */
-
-
-#define FF_FS_NOFSINFO 0
-/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
-/ option, and f_getfree() function at first time after volume mount will force
-/ a full FAT scan. Bit 1 controls the use of last allocated cluster number.
-/
-/ bit0=0: Use free cluster count in the FSINFO if available.
-/ bit0=1: Do not trust free cluster count in the FSINFO.
-/ bit1=0: Use last allocated cluster number in the FSINFO if available.
-/ bit1=1: Do not trust last allocated cluster number in the FSINFO.
-*/
-
-
-
-/*---------------------------------------------------------------------------/
-/ System Configurations
-/---------------------------------------------------------------------------*/
-
-#define FF_FS_TINY 0
-/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
-/ At the tiny configuration, size of file object (FIL) is shrunk FF_MAX_SS bytes.
-/ Instead of private sector buffer eliminated from the file object, common sector
-/ buffer in the filesystem object (FATFS) is used for the file data transfer. */
-
-
-#ifdef FILE_SYSTEM_FS_EXFAT
-#define FF_FS_EXFAT 1
-#else
-#define FF_FS_EXFAT 0
-#endif
-/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable)
-/ To enable exFAT, also LFN needs to be enabled.
-/ Note that enabling exFAT discards ANSI C (C89) compatibility. */
-
-
-#define FF_FS_NORTC 0
-#define FF_NORTC_MON 1
-#define FF_NORTC_MDAY 1
-#define FF_NORTC_YEAR 2018
-/* The option FF_FS_NORTC switches timestamp functiton. If the system does not have
-/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable
-/ the timestamp function. Every object modified by FatFs will have a fixed timestamp
-/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time.
-/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be
-/ added to the project to read current time form real-time clock. FF_NORTC_MON,
-/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect.
-/ These options have no effect at read-only configuration (FF_FS_READONLY = 1). */
-
-
-#define FF_FS_LOCK 0
-/* The option FF_FS_LOCK switches file lock function to control duplicated file open
-/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY
-/ is 1.
-/
-/ 0: Disable file lock function. To avoid volume corruption, application program
-/ should avoid illegal open, remove and rename to the open objects.
-/ >0: Enable file lock function. The value defines how many files/sub-directories
-/ can be opened simultaneously under file lock control. Note that the file
-/ lock control is independent of re-entrancy. */
-
-
-#define FF_FS_REENTRANT 0
-#define FF_FS_TIMEOUT 1000
-#define FF_SYNC_t HANDLE
-/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
-/ module itself. Note that regardless of this option, file access to different
-/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
-/ and f_fdisk() function, are always not re-entrant. Only file/directory access
-/ to the same volume is under control of this function.
-/
-/ 0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect.
-/ 1: Enable re-entrancy. Also user provided synchronization handlers,
-/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
-/ function, must be added to the project. Samples are available in
-/ option/syscall.c.
-/
-/ The FF_FS_TIMEOUT defines timeout period in unit of time tick.
-/ The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
-/ SemaphoreHandle_t and etc. A header file for O/S definitions needs to be
-/ included somewhere in the scope of ff.h. */
-
-/* #include // O/S definitions */
-
-#ifdef FILE_SYSTEM_WORD_ACCESS
-#define FF_WORD_ACCESS 1
-#else
-#define FF_WORD_ACCESS 0
-#endif
-/* The FF_WORD_ACCESS option is an only platform dependent option. It defines
-/ which access method is used to the word data on the FAT volume.
-/
-/ 0: Byte-by-byte access. Always compatible with all platforms.
-/ 1: Word access. Do not choose this unless under both the following conditions.
-/
-/ * Address misaligned memory access is always allowed for ALL instructions.
-/ * Byte order on the memory is little-endian.
-/
-/ If it is the case, FF_WORD_ACCESS can also be set to 1 to improve performance and
-/ reduce code size. Following table shows an example of some processor types.
-/
-/ ARM7TDMI 0 ColdFire 0 V850E 0
-/ Cortex-M3 0 Z80 0/1 V850ES 0/1
-/ Cortex-M0 0 RX600(LE) 0/1 TLCS-870 0/1
-/ AVR 0/1 RX600(BE) 0 TLCS-900 0/1
-/ AVR32 0 RL78 0 R32C 0
-/ PIC18 0/1 SH-2 0 M16C 0/1
-/ PIC24 0 H8S 0 MSP430 0
-/ PIC32 0 H8/300H 0 x86 0/1
-*/
-
-#ifdef __cplusplus
-}
-#endif
-
-/*--- End of configuration options ---*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ca/129ef6585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ca/129ef6585243001d18b399c1eb9b3628
deleted file mode 100644
index ea3a08c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ca/129ef6585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,133 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xl2cc_counter.c
-*
-* This file contains APIs for configuring and controlling the event counters
-* in PL310 L2 cache controller. For more information about the event counters,
-* see xl2cc_counter.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
-* inside the APIs
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include
-#include "xparameters_ps.h"
-#include "xl2cc_counter.h"
-#include "xl2cc.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void XL2cc_EventCtrReset(void);
-
-/******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @brief This function initializes the event counters in L2 Cache controller
-* with a set of event codes specified by the user.
-*
-* @param Event0: Event code for counter 0.
-* @param Event1: Event code for counter 1.
-*
-* @return None.
-*
-* @note The definitions for event codes XL2CC_* can be found in
-* xl2cc_counter.h.
-*
-*****************************************************************************/
-void XL2cc_EventCtrInit(s32 Event0, s32 Event1)
-{
-
- /* Write event code into cnt1 cfg reg */
- *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_CTRL_OFFSET)) = (((u32)Event1) << 2);
-
- /* Write event code into cnt0 cfg reg */
- *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_CTRL_OFFSET)) = (((u32)Event0) << 2);
-
- /* Reset counters */
- XL2cc_EventCtrReset();
-}
-
-
-/****************************************************************************/
-/**
-*
-* @brief This function starts the event counters in L2 Cache controller.
-*
-* @return None.
-*
-*****************************************************************************/
-void XL2cc_EventCtrStart(void)
-{
- u32 *LocalPtr;
- LocalPtr = (u32 *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET);
- XL2cc_EventCtrReset();
-
- /* Enable counter */
- /* *((volatile u32*)((void *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET))) = 1 */
- *LocalPtr = (u32)1;
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function disables the event counters in L2 Cache controller,
-* saves the counter values and resets the counters.
-*
-* @param EveCtr0: Output parameter which is used to return the value
-* in event counter 0.
-* @param EveCtr1: Output parameter which is used to return the value
-* in event counter 1.
-*
-* @return None.
-*
-*****************************************************************************/
-void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1)
-{
- /* Disable counter */
- *((volatile u32*) (XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0U;
-
- /* Save counter values */
- *EveCtr1 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_VAL_OFFSET));
- *EveCtr0 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_VAL_OFFSET));
-
- XL2cc_EventCtrReset();
-}
-
-/****************************************************************************/
-/**
-*
-* @brief This function resets the event counters in L2 Cache controller.
-*
-* @return None.
-*
-*****************************************************************************/
-void XL2cc_EventCtrReset(void)
-{
- *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0x6U;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ca/32767b545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ca/32767b545243001d18b399c1eb9b3628
deleted file mode 100644
index a8544b3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ca/32767b545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,40 +0,0 @@
-/*******************************************************************************
-* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-*******************************************************************************/
-
-/******************************************************************************/
-/**
- *
- * @file xddrps.h
- * @addtogroup ddrps_v1_2
- * @{
- * @details
- *
- * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps
- * IP core.
- *
- * @note None.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.0 nsk 08/06/15 First Release
- * 1.0 nsk 08/20/15 Updated define_addr_params in ddrps.tcl
- * to support PBD Designs (CR #876857)
- *
- *
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00b kpc 03/07/13 First release
-* 5.4 pkp 16/11/15 Change the description for XOcm_Remap function
-*
-*
-******************************************************************************/
-
-
-/***************************** Include Files *********************************/
-#include "xil_misc_psreset_api.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for ddr reset.
-*
-* @return N/A.
-*
-******************************************************************************/
-void XDdr_ResetHw(void)
-{
- u32 RegVal;
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert and deassert the ddr softreset bit */
- RegVal = Xil_In32(XDDRC_CTRL_BASEADDR);
- RegVal &= (u32)(~XDDRPS_CTRL_RESET_MASK);
- Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
- RegVal |= XDDRPS_CTRL_RESET_MASK;
- Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
-
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for remapping the ocm memory region
-* to postbootrom state.
-*
-* @return N/A.
-*
-******************************************************************************/
-void XOcm_Remap(void)
-{
- u32 RegVal;
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Map the ocm region to postbootrom state */
- RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR);
- RegVal = (RegVal & (u32)(~XSLCR_OCM_CFG_HIADDR_MASK)) | (u32)XSLCR_OCM_CFG_RESETVAL;
- Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for SMC reset sequence
-*
-* @param BaseAddress of the interface
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSmc_ResetHw(u32 BaseAddress)
-{
- u32 RegVal;
-
- /* Clear the interuupts */
- RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET);
- RegVal |= XSMC_MEMC_CLR_CONFIG_MASK;
- Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal);
- /* Clear the idle counter registers */
- Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0U);
- Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0U);
- /* Update the ecc registers with reset values */
- Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET,
- XSMC_ECC_MEMCFG1_RESET_VAL);
- Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD1_OFFSET,
- XSMC_ECC_MEMCMD1_RESET_VAL);
- Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD2_OFFSET,
- XSMC_ECC_MEMCMD2_RESET_VAL);
-
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for updating the slcr mio registers
-* with reset values
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_MioWriteResetValues(void)
-{
- u32 i;
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Update all the MIO registers with reset values */
- for (i=0U; i<=1U;i++)
- {
- Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
- XSLCR_MIO_PIN_00_RESET_VAL);
- }
- for (; i<=8U;i++)
- {
- Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
- XSLCR_MIO_PIN_02_RESET_VAL);
- }
- for (; i<=53U ;i++)
- {
- Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
- XSLCR_MIO_PIN_00_RESET_VAL);
- }
-
-
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for updating the slcr pll registers
-* with reset values
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_PllWriteResetValues(void)
-{
-
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
-
- /* update the pll control registers with reset values */
- Xil_Out32(XSLCR_IO_PLL_CTRL_ADDR, XSLCR_IO_PLL_CTRL_RESET_VAL);
- Xil_Out32(XSLCR_ARM_PLL_CTRL_ADDR, XSLCR_ARM_PLL_CTRL_RESET_VAL);
- Xil_Out32(XSLCR_DDR_PLL_CTRL_ADDR, XSLCR_DDR_PLL_CTRL_RESET_VAL);
- /* update the pll config registers with reset values */
- Xil_Out32(XSLCR_IO_PLL_CFG_ADDR, XSLCR_IO_PLL_CFG_RESET_VAL);
- Xil_Out32(XSLCR_ARM_PLL_CFG_ADDR, XSLCR_ARM_PLL_CFG_RESET_VAL);
- Xil_Out32(XSLCR_DDR_PLL_CFG_ADDR, XSLCR_DDR_PLL_CFG_RESET_VAL);
- /* update the clock control registers with reset values */
- Xil_Out32(XSLCR_ARM_CLK_CTRL_ADDR, XSLCR_ARM_CLK_CTRL_RESET_VAL);
- Xil_Out32(XSLCR_DDR_CLK_CTRL_ADDR, XSLCR_DDR_CLK_CTRL_RESET_VAL);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for disabling the level shifters
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_DisableLevelShifters(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Disable the level shifters */
- RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_LVL_SHFTR_EN_MASK);
- Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal);
-
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for OCM software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_OcmReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
- RegVal |= XSLCR_OCM_RST_CTRL_VAL;
- Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_OCM_RST_CTRL_VAL);
- Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for Ethernet software reset from
-* the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_EmacPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
- RegVal |= XSLCR_GEM_RST_CTRL_VAL;
- Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
- RegVal &= (u32)(~XSLCR_GEM_RST_CTRL_VAL);
- Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
-}
-
-/*****************************************************************************/
-/**
-* This function contains the implementation for USB software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_UsbPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
- RegVal |= XSLCR_USB_RST_CTRL_VAL;
- Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_USB_RST_CTRL_VAL);
- Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for QSPI software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_QspiPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
- RegVal |= XSLCR_QSPI_RST_CTRL_VAL;
- Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_QSPI_RST_CTRL_VAL);
- Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for SPI software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_SpiPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
- RegVal |= XSLCR_SPI_RST_CTRL_VAL;
- Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_SPI_RST_CTRL_VAL);
- Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for i2c software reset from the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_I2cPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
- RegVal |= XSLCR_I2C_RST_CTRL_VAL;
- Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_I2C_RST_CTRL_VAL);
- Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for UART software reset from the
-* slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_UartPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
- RegVal |= XSLCR_UART_RST_CTRL_VAL;
- Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_UART_RST_CTRL_VAL);
- Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for CAN software reset from slcr
-* registers
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_CanPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
- RegVal |= XSLCR_CAN_RST_CTRL_VAL;
- Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_CAN_RST_CTRL_VAL);
- Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for SMC software reset from the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_SmcPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
- RegVal |= XSLCR_SMC_RST_CTRL_VAL;
- Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_SMC_RST_CTRL_VAL);
- Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for DMA controller software reset
-* from the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_DmaPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
- RegVal |= XSLCR_DMAC_RST_CTRL_VAL;
- Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_DMAC_RST_CTRL_VAL);
- Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
-}
-/*****************************************************************************/
-/**
-* This function contains the implementation for Gpio AMBA software reset from
-* the slcr
-*
-* @return N/A.
-*
-******************************************************************************/
-void XSlcr_GpioPsReset(void)
-{
- u32 RegVal;
- /* Unlock the slcr register access lock */
- Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
- /* Assert the reset */
- RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
- RegVal |= XSLCR_GPIO_RST_CTRL_VAL;
- Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
- /* Release the reset */
- RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
- RegVal = RegVal & (u32)(~XSLCR_GPIO_RST_CTRL_VAL);
- Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ca/e125b2595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ca/e125b2595243001d18b399c1eb9b3628
deleted file mode 100644
index f101c14..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ca/e125b2595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,341 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_testcache.c
-* @addtogroup common_test_utils
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/28/09 Initial release
-* 4.1 asa 05/09/14 Ensured that the address uses for cache test is aligned
-* cache line.
-*
-*
-******************************************************************************/
-#ifdef __ARM__
-#include "xil_cache.h"
-#include "xil_testcache.h"
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#ifdef __aarch64__
-#include "xreg_cortexa53.h"
-#else
-#include "xreg_cortexr5.h"
-#endif
-
-#include "xil_types.h"
-
-extern void xil_printf(const char8 *ctrl1, ...);
-
-#define DATA_LENGTH 128
-
-#ifdef __aarch64__
-static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64)));
-#else
-static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32)));
-#endif
-
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform DCache range related API test such as Xil_DCacheFlushRange
-* and Xil_DCacheInvalidateRange. This test function writes a constant
-* value to the Data array, flushes the range, writes a new value, then
-* invalidates the corresponding range.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-s32 Xil_TestDCacheRange(void)
-{
- s32 Index;
- s32 Status = 0;
- u32 CtrlReg;
- INTPTR Value;
-
- xil_printf("-- Cache Range Test --\n\r");
-
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0xA0A00505;
-
- xil_printf(" initialize Data done:\r\n");
-
- Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
-
- xil_printf(" flush range done\r\n");
-
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
-
- Status = 0;
-
- for (Index = 0; Index < DATA_LENGTH; Index++) {
- Value = Data[Index];
- if (Value != 0xA0A00505) {
- Status = -1;
- xil_printf("Data[%d] = %x\r\n", Index, Value);
- break;
- }
- }
-
- if (!Status) {
- xil_printf(" Flush worked\r\n");
- }
- else {
- xil_printf("Error: flush dcache range not working\r\n");
- }
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0xA0A0C505;
-
-
-
- Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
-
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = Index + 3;
-
- Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
-
- xil_printf(" invalidate dcache range done\r\n");
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0xA0A0A05;
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
-
- Status = 0;
-
- for (Index = 0; Index < DATA_LENGTH; Index++) {
- Value = Data[Index];
- if (Value != 0xA0A0A05) {
- Status = -1;
- xil_printf("Data[%d] = %x\r\n", Index, Value);
- break;
- }
- }
-
-
- if (!Status) {
- xil_printf(" Invalidate worked\r\n");
- }
- else {
- xil_printf("Error: Invalidate dcache range not working\r\n");
- }
- xil_printf("-- Cache Range Test Complete --\r\n");
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-* @brief Perform DCache all related API test such as Xil_DCacheFlush and
-* Xil_DCacheInvalidate. This test function writes a constant value
-* to the Data array, flushes the DCache, writes a new value,
-* then invalidates the DCache.
-*
-* @return
-* - 0 is returned for a pass
-* - -1 is returned for a failure
-*****************************************************************************/
-s32 Xil_TestDCacheAll(void)
-{
- s32 Index;
- s32 Status;
- INTPTR Value;
- u32 CtrlReg;
-
- xil_printf("-- Cache All Test --\n\r");
-
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0x50500A0A;
- xil_printf(" initialize Data done:\r\n");
-
- Xil_DCacheFlush();
- xil_printf(" flush all done\r\n");
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
- Status = 0;
-
- for (Index = 0; Index < DATA_LENGTH; Index++) {
- Value = Data[Index];
-
- if (Value != 0x50500A0A) {
- Status = -1;
- xil_printf("Data[%d] = %x\r\n", Index, Value);
- break;
- }
- }
-
- if (!Status) {
- xil_printf(" Flush all worked\r\n");
- }
- else {
- xil_printf("Error: Flush dcache all not working\r\n");
- }
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0x505FFA0A;
-
- Xil_DCacheFlush();
-
-
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = Index + 3;
-
- Xil_DCacheInvalidate();
-
- xil_printf(" invalidate all done\r\n");
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0x50CFA0A;
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
- Status = 0;
-
- for (Index = 0; Index < DATA_LENGTH; Index++) {
- Value = Data[Index];
- if (Value != 0x50CFA0A) {
- Status = -1;
- xil_printf("Data[%d] = %x\r\n", Index, Value);
- break;
- }
- }
-
- if (!Status) {
- xil_printf(" Invalidate all worked\r\n");
- }
- else {
- xil_printf("Error: Invalidate dcache all not working\r\n");
- }
-
- xil_printf("-- DCache all Test Complete --\n\r");
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief Perform Xil_ICacheInvalidateRange() on a few function pointers.
-*
-* @return
-* - 0 is returned for a pass
-*
-* @note The function will hang if it fails.
-*****************************************************************************/
-s32 Xil_TestICacheRange(void)
-{
-
- Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024);
- Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024);
- Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024);
-
- xil_printf("-- Invalidate icache range done --\r\n");
-
- return 0;
-}
-
-/*****************************************************************************/
-/**
-* @brief Perform Xil_ICacheInvalidate() on a few function pointers.
-*
-* @return
-* - 0 is returned for a pass
-*
-* @note The function will hang if it fails.
-*****************************************************************************/
-s32 Xil_TestICacheAll(void)
-{
- Xil_ICacheInvalidate();
- xil_printf("-- Invalidate icache all done --\r\n");
- return 0;
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ca/f0b406575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ca/f0b406575243001d18b399c1eb9b3628
deleted file mode 100644
index c19c95a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ca/f0b406575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,154 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xuartps_hw.c
-* @addtogroup uartps_v3_11
-* @{
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00 drg/jz 01/12/10 First Release
-* 1.05a hk 08/22/13 Added reset function
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xuartps_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-/****************************************************************************/
-/**
-*
-* This function sends one byte using the device. This function operates in
-* polled mode and blocks until the data has been put into the TX FIFO register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param Data contains the byte to be sent.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartPs_SendByte(u32 BaseAddress, u8 Data)
-{
- /* Wait until there is space in TX FIFO */
- while (XUartPs_IsTransmitFull(BaseAddress)) {
- ;
- }
-
- /* Write the byte into the TX FIFO */
- XUartPs_WriteReg(BaseAddress, XUARTPS_FIFO_OFFSET, (u32)Data);
-}
-
-/****************************************************************************/
-/**
-*
-* This function receives a byte from the device. It operates in polled mode
-* and blocks until a byte has received.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return The data byte received.
-*
-* @note None.
-*
-*****************************************************************************/
-u8 XUartPs_RecvByte(u32 BaseAddress)
-{
- u32 RecievedByte;
- /* Wait until there is data */
- while (!XUartPs_IsReceiveData(BaseAddress)) {
- ;
- }
- RecievedByte = XUartPs_ReadReg(BaseAddress, XUARTPS_FIFO_OFFSET);
- /* Return the byte received */
- return (u8)RecievedByte;
-}
-
-/****************************************************************************/
-/**
-*
-* This function resets UART
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return None
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartPs_ResetHw(u32 BaseAddress)
-{
-
- /* Disable interrupts */
- XUartPs_WriteReg(BaseAddress, XUARTPS_IDR_OFFSET, XUARTPS_IXR_MASK);
-
- /* Disable receive and transmit */
- XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
- ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS));
-
- /*
- * Software reset of receive and transmit
- * This clears the FIFO.
- */
- XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
- ((u32)XUARTPS_CR_TXRST | (u32)XUARTPS_CR_RXRST));
-
- /* Clear status flags - SW reset wont clear sticky flags. */
- XUartPs_WriteReg(BaseAddress, XUARTPS_ISR_OFFSET, XUARTPS_IXR_MASK);
-
- /*
- * Mode register reset value : All zeroes
- * Normal mode, even parity, 1 stop bit
- */
- XUartPs_WriteReg(BaseAddress, XUARTPS_MR_OFFSET,
- XUARTPS_MR_CHMODE_NORM);
-
- /* Rx and TX trigger register reset values */
- XUartPs_WriteReg(BaseAddress, XUARTPS_RXWM_OFFSET,
- XUARTPS_RXWM_RESET_VAL);
- XUartPs_WriteReg(BaseAddress, XUARTPS_TXWM_OFFSET,
- XUARTPS_TXWM_RESET_VAL);
-
- /* Rx timeout disabled by default */
- XUartPs_WriteReg(BaseAddress, XUARTPS_RXTOUT_OFFSET,
- XUARTPS_RXTOUT_DISABLE);
-
- /* Baud rate generator and dividor reset values */
- XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDGEN_OFFSET,
- XUARTPS_BAUDGEN_RESET_VAL);
- XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDDIV_OFFSET,
- XUARTPS_BAUDDIV_RESET_VAL);
-
- /*
- * Control register reset value -
- * RX and TX are disable by default
- */
- XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
- ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS |
- (u32)XUARTPS_CR_STOPBRK));
-
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cb/00fa90545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cb/00fa90545243001d18b399c1eb9b3628
deleted file mode 100644
index 227d6a5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cb/00fa90545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,35 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 2021.2
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2022 Xilinx, Inc. All Rights Reserved.
-* SPDX-License-Identifier: MIT
-
-*
-* Description: Driver configuration
-*
-*******************************************************************/
-
-#include "xparameters.h"
-#include "xdmaps.h"
-
-/*
-* The configuration table for devices
-*/
-
-XDmaPs_Config XDmaPs_ConfigTable[XPAR_XDMAPS_NUM_INSTANCES] =
-{
- {
- XPAR_PS7_DMA_NS_DEVICE_ID,
- XPAR_PS7_DMA_NS_BASEADDR
- },
- {
- XPAR_PS7_DMA_S_DEVICE_ID,
- XPAR_PS7_DMA_S_BASEADDR
- }
-};
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cb/22e3f1585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cb/22e3f1585243001d18b399c1eb9b3628
deleted file mode 100644
index 878d575..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cb/22e3f1585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,261 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_misc_psreset_api.h
-*
-* This file contains the various register definitions and function prototypes for
-* implementing the reset functionality of zynq ps devices
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00b kpc 03/07/13 First release.
-*
-*
-******************************************************************************/
-
-#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */
-#define XIL_MISC_RESET_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/**
- *@cond nocomments
- */
-
-#define XDDRC_CTRL_BASEADDR 0xF8006000U
-#define XSLCR_BASEADDR 0xF8000000U
-/**< OCM configuration register */
-#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U)
-/**< SLCR unlock register */
-#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U)
-/**< SLCR GEM0 rx clock control register */
-#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U)
-/**< SLCR GEM1 rx clock control register */
-#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU)
-/**< SLCR GEM0 clock control register */
-#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U)
-/**< SLCR GEM1 clock control register */
-#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U)
-/**< SLCR SMC clock control register */
-#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U)
-/**< SLCR GEM reset control register */
-#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)
-/**< SLCR USB0 clock control register */
-#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U)
-/**< SLCR USB1 clock control register */
-#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U)
-/**< SLCR USB1 reset control register */
-#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)
-/**< SLCR SMC reset control register */
-#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)
-/**< SLCR Level shifter enable register */
-#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U)
-/**< SLCR ARM pll control register */
-#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U)
-/**< SLCR DDR pll control register */
-#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U)
-/**< SLCR IO pll control register */
-#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U)
-/**< SLCR ARM pll configuration register */
-#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U)
-/**< SLCR DDR pll configuration register */
-#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U)
-/**< SLCR IO pll configuration register */
-#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U)
-/**< SLCR ARM clock control register */
-#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U)
-/**< SLCR DDR clock control register */
-#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U)
-/**< SLCR MIO pin address register */
-#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U)
-/**< SLCR DMAC reset control address register */
-#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU)
-/**< SLCR USB reset control address register */
-/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/
-/**< SLCR GEM reset control address register */
-/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/
-/**< SLCR SDIO reset control address register */
-#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U)
-/**< SLCR SPI reset control address register */
-#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU)
-/**< SLCR CAN reset control address register */
-#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U)
-/**< SLCR I2C reset control address register */
-#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U)
-/**< SLCR UART reset control address register */
-#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U)
-/**< SLCR GPIO reset control address register */
-#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU)
-/**< SLCR LQSPI reset control address register */
-#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U)
-/**< SLCR SMC reset control address register */
-/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/
-/**< SLCR OCM reset control address register */
-#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U)
-
-/**< SMC mem controller clear config register */
-#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU
-/**< SMC idlecount configuration register */
-#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U
-#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U
-/**< SMC ECC configuration register */
-#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U
-/**< SMC ECC command 1 register */
-#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U
-/**< SMC ECC command 2 register */
-#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U
-
-/**< SLCR unlock code */
-#define XSLCR_UNLOCK_CODE 0x0000DF0DU
-
-/**< SMC mem clear configuration mask */
-#define XSMC_MEMC_CLR_CONFIG_MASK 0x000005FU
-/**< SMC ECC memconfig 1 reset value */
-#define XSMC_ECC_MEMCFG1_RESET_VAL 0x0000043U
-/**< SMC ECC memcommand 1 reset value */
-#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U
-/**< SMC ECC memcommand 2 reset value */
-#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U
-
-/**< DDR controller reset bit mask */
-#define XDDRPS_CTRL_RESET_MASK 0x00000001U
-/**< SLCR OCM configuration reset value*/
-#define XSLCR_OCM_CFG_RESETVAL 0x00000008U
-/**< SLCR OCM bank selection mask*/
-#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU
-/**< SLCR level shifter enable mask*/
-#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU
-
-/**< SLCR PLL register reset values */
-#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U
-#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U
-#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U
-#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U
-#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U
-#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U
-#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U
-#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U
-
-/**< SLCR MIO register default values */
-#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U
-#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U
-
-/**< SLCR Reset control registers default values */
-#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U
-#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U
-#define XSLCR_USB_RST_CTRL_VAL 0x00000003U
-#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U
-#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU
-#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU
-#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U
-#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U
-#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U
-#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U
-#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U
-#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U
-
-/**
- *@endcond
- */
-
-/**************************** Type Definitions *******************************/
-
-/* the following data type is used to hold a null terminated version string
- * consisting of the following format, "X.YYX"
- */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-/*
- * Performs reset operation to the ddr interface
- */
-void XDdr_ResetHw(void);
-/*
- * Map the ocm region to post bootrom state
- */
-void XOcm_Remap(void);
-/*
- * Performs the smc interface reset
- */
-void XSmc_ResetHw(u32 BaseAddress);
-/*
- * updates the MIO registers with reset values
- */
-void XSlcr_MioWriteResetValues(void);
-/*
- * updates the PLL and clock registers with reset values
- */
-void XSlcr_PllWriteResetValues(void);
-/*
- * Disables the level shifters
- */
-void XSlcr_DisableLevelShifters(void);
-/*
- * provides softreset to the GPIO interface
- */
-void XSlcr_GpioPsReset(void);
-/*
- * provides softreset to the DMA interface
- */
-void XSlcr_DmaPsReset(void);
-/*
- * provides softreset to the SMC interface
- */
-void XSlcr_SmcPsReset(void);
-/*
- * provides softreset to the CAN interface
- */
-void XSlcr_CanPsReset(void);
-/*
- * provides softreset to the Uart interface
- */
-void XSlcr_UartPsReset(void);
-/*
- * provides softreset to the I2C interface
- */
-void XSlcr_I2cPsReset(void);
-/*
- * provides softreset to the SPI interface
- */
-void XSlcr_SpiPsReset(void);
-/*
- * provides softreset to the QSPI interface
- */
-void XSlcr_QspiPsReset(void);
-/*
- * provides softreset to the USB interface
- */
-void XSlcr_UsbPsReset(void);
-/*
- * provides softreset to the GEM interface
- */
-void XSlcr_EmacPsReset(void);
-/*
- * provides softreset to the OCM interface
- */
-void XSlcr_OcmReset(void);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_MISC_RESET_H */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cb/3002c4525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cb/3002c4525243001d18b399c1eb9b3628
deleted file mode 100644
index fa58233..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cb/3002c4525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,78 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_spinlock.h
-*
-* This header file contains function prototypes to be used while using Xilinx
-* spinlocking mechanism.
-* Please refer to file header contents of xil_spinlock.c to understand in
-* detail the spinlocking mechanism.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 7.5 asa 02/16/21 First release
-* 7.6 sk 08/05/21 Add Boolean check and braces for Xil_IsSpinLockEnabled
-* if condition to fix misrac violations.
-*
-*
-******************************************************************************/
-
-#ifndef XIL_SPINLOCK_H /* prevent circular inclusions */
-#define XIL_SPINLOCK_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-#include "xil_types.h"
-#include "xstatus.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-#if !defined (__aarch64__) && defined(__GNUC__) && !defined(__clang__)
-/************************** Function Prototypes *****************************/
-u32 Xil_SpinLock(void);
-u32 Xil_SpinUnlock(void);
-u32 Xil_InitializeSpinLock(UINTPTR lockaddr, UINTPTR lockflagaddr,
- u32 lockflag);
-void Xil_ReleaseSpinLock(void);
-u32 Xil_IsSpinLockEnabled(void);
-
-/************************** MACRO Definitions ****************************/
-#define XIL_SPINLOCK_LOCKVAL 0x10203040
-#define XIL_SPINLOCK_RESETVAL 0x40302010
-#define XIL_SPINLOCK_ENABLE 0x17273747
-#define XIL_SPINLOCK_ENABLED 0x17273747
-/***************** Macros (Inline Functions) Definitions ********************/
-
-#endif /* !(__aarch64__) && (__GNUC__) && !(__clang__)*/
-/***************************************************************************/
-#if !defined (__aarch64__) && defined(__GNUC__) && !defined(__clang__)
-#define XIL_SPINLOCK() \
- if(Xil_IsSpinLockEnabled()!=(u32)0) { \
- Xil_SpinLock(); }
-#else
-#define XIL_SPINLOCK()
-#endif /* !(__aarch64__) && (__GNUC__) && !(__clang__)*/
-
-#if !defined (__aarch64__) && defined(__GNUC__) && !defined(__clang__)
-#define XIL_SPINUNLOCK() \
- if(Xil_IsSpinLockEnabled()!=(u32)0) { \
- Xil_SpinUnlock(); }
-#else
-#define XIL_SPINUNLOCK()
-#endif /* !(__aarch64__) && (__GNUC__) && !(__clang__)*/
-
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_SPINLOCK_H */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cb/52c38a555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cb/52c38a555243001d18b399c1eb9b3628
deleted file mode 100644
index 74ca3a8..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cb/52c38a555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,14 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: MIT
-*
-******************************************************************************/
-#include "xil_types.h"
-
-/* Stub for open sys-call */
-__attribute__((weak)) s32 _sys_open(__attribute__((unused)) const char8* name,
- __attribute__((unused)) s32 openmode)
-{
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cb/924e73565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cb/924e73565243001d18b399c1eb9b3628
deleted file mode 100644
index 8eb4638..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cb/924e73565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,24 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf);
-}
-#endif
-/*
- * fstat -- Since we have no file system, we just return an error.
- */
-__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf)
-{
- (void)fd;
- buf->st_mode = S_IFCHR; /* Always pretend to be a tty */
-
- return (0);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cb/d1496d585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cb/d1496d585243001d18b399c1eb9b3628
deleted file mode 100644
index 3c79b0b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cb/d1496d585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,56 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm.h
-*
-* @addtogroup a53_64_specific Cortex A53 64bit Processor Specific Include Files
-*
-* The xpseudo_asm.h includes xreg_cortexa53.h and xpseudo_asm_gcc.h.
-* The xreg_cortexa53.h file contains definitions for inline assembler code.
-* It provides inline definitions for Cortex A53 GPRs, SPRs and floating point
-* registers.
-*
-* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
-* assembler instructions, available as macros. These can be very useful for
-* tasks such as setting or getting special purpose registers, synchronization,
-* or cache manipulation etc. These inline assembler instructions can be used
-* from drivers and user applications written in C.
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.00 pkp 05/29/14 First release
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.6 srm 11/02/17 First release
-*
-******************************************************************************/
-
-
-/***************************** Include Files *********************************/
-#include "xil_io.h"
-#include "sleep.h"
-
-/**************************** Constant Definitions *************************/
-
-
-/*****************************************************************************/
-/**
-*
-* This API gives delay in sec
-*
-* @param seconds - delay time in seconds
-*
-* @return none
-*
-* @note none
-*
-*****************************************************************************/
- void sleep(unsigned int seconds)
- {
-#if defined (ARMR5)
- sleep_R5(seconds);
-#elif defined (__aarch64__) || defined (ARMA53_32)
- sleep_A53(seconds);
-#elif defined (__MICROBLAZE__)
- sleep_MB(seconds);
-#else
- sleep_A9(seconds);
-#endif
-
- }
-
-/****************************************************************************/
-/**
-*
-* This API gives delay in usec
-*
-* @param useconds - delay time in useconds
-*
-* @return none
-*
-* @note none
-*
-*****************************************************************************/
- void usleep(unsigned long useconds)
- {
-#if defined (ARMR5)
- usleep_R5(useconds);
-#elif defined (__aarch64__) || defined (ARMA53_32)
- usleep_A53(useconds);
-#elif defined (__MICROBLAZE__)
- usleep_MB(useconds);
-#else
- usleep_A9(useconds);
-#endif
-
- }
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cb/f0c69e525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cb/f0c69e525243001d18b399c1eb9b3628
deleted file mode 100644
index ee6ac60..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cb/f0c69e525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,646 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xemacps_hw.h
-* @addtogroup emacps_v3_15
-* @{
-*
-* This header file contains identifiers and low-level driver functions (or
-* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
-* High-level driver functions are defined in xemacps.h.
-*
-* @note
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 First release.
-* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration.
-* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype
-* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
-* to 0x1fff. This fixes the CR#744902.
-* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
-* 3.0 kvn 12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
-* XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
-* 3.0 kpc 1/23/15 Corrected the extended descriptor macro values.
-* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.0 hk 03/18/15 Added support for jumbo frames.
-* Remove "used bit set" from TX error interrupt masks.
-* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
-* 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
-* 3.8 hk 09/17/18 Fix PTP interrupt masks.
-* 3.9 hk 01/23/19 Add RX watermark support
-* 3.10 hk 05/16/19 Clear status registers properly in reset
-*
-*
-******************************************************************************/
-
-#ifndef XEMACPS_HW_H /* prevent circular inclusions */
-#define XEMACPS_HW_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address
- supported */
-#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */
-
-#ifdef __aarch64__
-#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment
- on the local bus */
-#else
-
-#define XEMACPS_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment
- on the local bus */
-#endif
-#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using
- options that impose alignment
- restrictions on the buffer data on
- the local bus */
-
-/** @name Direction identifiers
- *
- * These are used by several functions and callbacks that need
- * to specify whether an operation specifies a send or receive channel.
- * @{
- */
-#define XEMACPS_SEND 1U /**< send direction */
-#define XEMACPS_RECV 2U /**< receive direction */
-/*@}*/
-
-/** @name MDC clock division
- * currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
- * @{
- */
-typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
- MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
-} XEmacPs_MdcDiv;
-
-/*@}*/
-
-#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
- bytes, 64, 128, ... 10240 */
-#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
-
-#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a
- unit, this is HW setup */
-
-#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */
-#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */
-
-#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
-
-/* Register offset definitions. Unless otherwise noted, register access is
- * 32 bit. Names are self explained here.
- */
-
-#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */
-#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */
-#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */
-
-#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */
-#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */
-#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */
-#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */
-#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */
-
-#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */
-#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */
-#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */
-#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */
-
-#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */
-#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */
-#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */
-
-#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */
-
-#define XEMACPS_RXWATERMARK_OFFSET 0x0000007CU /**< RX watermark reg */
-
-#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */
-#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */
-
-#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */
-#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */
-#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */
-#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */
-#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */
-#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */
-#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */
-#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */
-
-#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */
-#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */
-#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */
-#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */
-
-#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */
-
-#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low
- reg */
-#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High
- reg */
-
-#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes
- transmitted counter */
-#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast
- Frames counter*/
-#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast
- Frame counter */
-#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted
- Counter */
-#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames
- Transmitted counter */
-#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte
- Frames Transmitted
- counter */
-#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte
- Frames Transmitted
- counter*/
-#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte
- Frames transmitted
- counter */
-#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte
- Frames transmitted
- counter */
-#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte
- Frames transmitted
- counter */
-#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than
- 1519 byte Frames
- transmitted counter */
-#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error
- counter */
-
-#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame
- Counter */
-#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame
- Counter */
-#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
- Counter */
-#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame
- Counter */
-#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission
- Frame Counter */
-#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense
- Error Counter */
-
-#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register
- Low */
-#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register
- High */
-
-#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames
- Received Counter */
-#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast
- Frames Received Counter */
-#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast
- Frames Received Counter */
-#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames
- Received Counter */
-#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames
- Received Counter */
-#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte
- Frames Received Counter */
-#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte
- Frames Received Counter */
-#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte
- Frames Received Counter */
-#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte
- Frames Received Counter */
-#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte
- Frames Received Counter */
-#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte
- Frames Received Counter */
-#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received
- Counter */
-#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received
- Counter */
-#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received
- Counter */
-#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence
- Error Counter */
-#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error
- Counter */
-#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */
-#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */
-#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error
- Counter */
-#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */
-#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error
- Counter */
-#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error
- Counter */
-#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error
- Counter */
-#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter
- offset, for clearing */
-
-#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */
-#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */
-#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond
- adjustment counter */
-#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond
- increment counter */
-#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second
- counter */
-#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
- nanosecond counter */
-#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second
- counter */
-#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
- nanosecond counter */
-#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit
- second counter */
-#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
- nanosecond counter */
-#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive
- second counter */
-#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
- nanosecond counter */
-
-#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status
- reg */
-#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address
- reg */
-#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address
- reg */
-#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base
- reg */
-#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base
- reg */
-#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable
- reg */
-#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable
- reg */
-#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask
- reg */
-
-/* Define some bit positions for registers. */
-
-/** @name network control register bit definitions
- * @{
- */
-#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from
- Rx SRAM */
-#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
- pause frame */
-#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */
-#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission
- after current frame */
-#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */
-
-#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to
- stat counters */
-#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic
- registers */
-#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic
- registers */
-#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */
-#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */
-#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */
-#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */
-/*@}*/
-
-/** @name network configuration register bit definitions
- * @{
- */
-#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
- non-standard preamble */
-#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */
-#define XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U /**< SGMII Enable */
-#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of
- FCS error */
-#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */
-#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum
- offload */
-#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
- Frames to memory */
-#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */
-#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */
-#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */
-#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from
- received frames */
-#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
-/**< RX length error discard */
-#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */
-#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */
-#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
-#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
-/**< External address match enable */
-#define XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U /**< PCS Select */
-#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */
-#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte
- frames reception */
-#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
- frames */
-#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
- frames */
-#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive
- broadcast frames */
-#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */
-#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */
-#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN
- frames */
-#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */
-#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */
-#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */
-/*@}*/
-
-/** @name network status register bit definitaions
- * @{
- */
-#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */
-#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */
-/*@}*/
-
-
-/** @name MAC address register word 1 mask
- * @{
- */
-#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32]
- bit[31:0] are in BOTTOM */
-/*@}*/
-
-
-/** @name DMA control register bit definitions
- * @{
- */
-#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */
-#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */
-#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */
-#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer
- size */
-#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer
- size */
-#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX
- checksum offload */
-#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */
-#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */
-#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */
-#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */
-#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */
-#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */
-#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */
-#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */
-/*@}*/
-
-/** @name transmit status register bit definitions
- * @{
- */
-#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */
-#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */
-#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */
-#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted
- mid frame */
-#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */
-#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */
-#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */
-#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */
-
-#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
- (u32)XEMACPS_TXSR_URUN_MASK | \
- (u32)XEMACPS_TXSR_BUFEXH_MASK | \
- (u32)XEMACPS_TXSR_RXOVR_MASK | \
- (u32)XEMACPS_TXSR_FRAMERX_MASK | \
- (u32)XEMACPS_TXSR_USEDREAD_MASK)
-/*@}*/
-
-/**
- * @name receive status register bit definitions
- * @{
- */
-#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */
-#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */
-#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */
-#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */
-
-#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
- (u32)XEMACPS_RXSR_RXOVR_MASK | \
- (u32)XEMACPS_RXSR_BUFFNA_MASK)
-
-#define XEMACPS_SR_ALL_MASK 0xFFFFFFFFU /**< Mask for full register */
-
-/*@}*/
-
-/**
- * @name Interrupt Q1 status register bit definitions
- * @{
- */
-#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */
-#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */
-
-#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
- (u32)XEMACPS_INTQ1SR_TXERR_MASK)
-
-/*@}*/
-
-/**
- * @name interrupts bit definitions
- * Bits definitions are same in XEMACPS_ISR_OFFSET,
- * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
- * @{
- */
-#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Pdelay_resp TXed */
-#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req TXed */
-#define XEMACPS_IXR_PTPPSRX_MASK 0x00800000U /**< PTP Pdelay_resp RXed */
-#define XEMACPS_IXR_PTPPDRRX_MASK 0x00400000U /**< PTP Pdelay_req RXed */
-
-#define XEMACPS_IXR_PTPSTX_MASK 0x00200000U /**< PTP Sync TXed */
-#define XEMACPS_IXR_PTPDRTX_MASK 0x00100000U /**< PTP Delay_req TXed */
-#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync RXed */
-#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req RXed */
-
-#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */
-#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached
- zero */
-#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
-#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */
-#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */
-#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */
-#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or
- no buffers*/
-#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */
-#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */
-#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */
-#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */
-#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */
-#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */
-#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */
-
-#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \
- (u32)XEMACPS_IXR_RETRY_MASK | \
- (u32)XEMACPS_IXR_URUN_MASK)
-
-
-#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \
- (u32)XEMACPS_IXR_RXUSED_MASK | \
- (u32)XEMACPS_IXR_RXOVR_MASK)
-
-/*@}*/
-
-/** @name PHY Maintenance bit definitions
- * @{
- */
-#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */
-#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */
-#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */
-#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */
-#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */
-#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */
-#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */
-#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */
-/*@}*/
-
-/** @name RX watermark bit definitions
- * @{
- */
-#define XEMACPS_RXWM_HIGH_MASK 0x0000FFFFU /**< RXWM high mask */
-#define XEMACPS_RXWM_LOW_MASK 0xFFFF0000U /**< RXWM low mask */
-#define XEMACPS_RXWM_LOW_SHFT_MSK 16U /**< Shift for RXWM low */
-/*@}*/
-
-/* Transmit buffer descriptor status words offset
- * @{
- */
-#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */
-#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */
-#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */
-
-/*
- * @}
- */
-
-/* Transmit buffer descriptor status words bit positions.
- * Transmit buffer descriptor consists of two 32-bit registers,
- * the first - word0 contains a 32-bit address pointing to the location of
- * the transmit data.
- * The following register - word1, consists of various information to control
- * the XEmacPs transmit process. After transmit, this is updated with status
- * information, whether the frame was transmitted OK or why it had failed.
- * @{
- */
-#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */
-#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */
-#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
-#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */
-#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */
-#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */
-#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
-#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */
-#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */
-/*
- * @}
- */
-
-/* Receive buffer descriptor status words bit positions.
- * Receive buffer descriptor consists of two 32-bit registers,
- * the first - word0 contains a 32-bit word aligned address pointing to the
- * address of the buffer. The lower two bits make up the wrap bit indicating
- * the last descriptor and the ownership bit to indicate it has been used by
- * the XEmacPs.
- * The following register - word1, contains status information regarding why
- * the frame was received (the filter match condition) as well as other
- * useful info.
- * @{
- */
-#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */
-#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
-#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */
-#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */
-#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address
- matched */
-#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */
-#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */
-#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */
-#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */
-#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */
-#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */
-#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */
-#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */
-#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */
-#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
-
-#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */
-#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */
-#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */
-/*
- * @}
- */
-
-/*
- * Define appropriate I/O access method to memory mapped I/O or other
- * interface if necessary.
- */
-
-#define XEmacPs_In32 Xil_In32
-#define XEmacPs_Out32 Xil_Out32
-
-
-/****************************************************************************/
-/**
-*
-* Read the given register.
-*
-* @param BaseAddress is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
- XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
-
-
-/****************************************************************************/
-/**
-*
-* Write the given register.
-*
-* @param BaseAddress is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
-* u32 Data)
-*
-*****************************************************************************/
-#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
- XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
-
-/************************** Function Prototypes *****************************/
-/*
- * Perform reset operation to the emacps interface
- */
-void XEmacPs_ResetHw(u32 BaseAddr);
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cc/5018e5555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cc/5018e5555243001d18b399c1eb9b3628
deleted file mode 100644
index 9be0b25..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cc/5018e5555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,176 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file asm_vectors.S
-*
-* This file contains the initial vector table for the Cortex A9 processor
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 1.00a ecm/sdm 10/20/09 Initial version
-* 3.05a sdm 02/02/12 Save lr when profiling is enabled
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-* 4.00a pkp 22/01/14 Modified return addresses for interrupt
-* handlers (DataAbortHandler and SVCHandler)
-* to fix CR#767251
-* 5.1 pkp 05/13/15 Saved the addresses of instruction causing data
-* abort and prefetch abort into DataAbortAddr and
-* PrefetchAbortAddr for further use to fix CR#854523
-* 5.4 pkp 12/03/15 Added handler for undefined exception
-* 6.8 mus 04/27/18 Removed __ARM_NEON__ flag definition. Now,
-* saving/restoring of of HW floating point register
-* would be done through newly introduced flag
-* FPU_HARD_FLOAT_ABI_ENABLED. This new flag will be
-* configured based on the -mfpu-abi option in extra
-* compiler flags.
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#include "xil_errata.h"
-#include "bspconfig.h"
-
-.org 0
-.text
-
-.globl _vector_table
-
-.section .vectors
-_vector_table:
- B _boot
- B Undefined
- B SVCHandler
- B PrefetchAbortHandler
- B DataAbortHandler
- NOP /* Placeholder for address exception vector*/
- B IRQHandler
- B FIQHandler
-
-
-IRQHandler: /* IRQ vector handler */
-
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/
-#if FPU_HARD_FLOAT_ABI_ENABLED
- vpush {d0-d7}
- vpush {d16-d31}
- vmrs r1, FPSCR
- push {r1}
- vmrs r1, FPEXC
- push {r1}
-#endif
-
-#ifdef PROFILING
- ldr r2, =prof_pc
- subs r3, lr, #0
- str r3, [r2]
-#endif
-
- bl IRQInterrupt /* IRQ vector */
-
-#if FPU_HARD_FLOAT_ABI_ENABLED
- pop {r1}
- vmsr FPEXC, r1
- pop {r1}
- vmsr FPSCR, r1
- vpop {d16-d31}
- vpop {d0-d7}
-#endif
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
-
- subs pc, lr, #4 /* adjust return */
-
-
-FIQHandler: /* FIQ vector handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
-#if FPU_HARD_FLOAT_ABI_ENABLED
- vpush {d0-d7}
- vpush {d16-d31}
- vmrs r1, FPSCR
- push {r1}
- vmrs r1, FPEXC
- push {r1}
-#endif
-
-FIQLoop:
- bl FIQInterrupt /* FIQ vector */
-
-#if FPU_HARD_FLOAT_ABI_ENABLED
- pop {r1}
- vmsr FPEXC, r1
- pop {r1}
- vmsr FPSCR, r1
- vpop {d16-d31}
- vpop {d0-d7}
-#endif
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
- subs pc, lr, #4 /* adjust return */
-
-
-Undefined: /* Undefined handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- ldr r0, =UndefinedExceptionAddr
- sub r1, lr, #4
- str r1, [r0] /* Store address of instruction causing undefined exception */
-
- bl UndefinedException /* UndefinedException: call C function here */
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
- movs pc, lr
-
-SVCHandler: /* SWI handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
-
- tst r0, #0x20 /* check the T bit */
- ldrneh r0, [lr,#-2] /* Thumb mode */
- bicne r0, r0, #0xff00 /* Thumb mode */
- ldreq r0, [lr,#-4] /* ARM mode */
- biceq r0, r0, #0xff000000 /* ARM mode */
-
- bl SWInterrupt /* SWInterrupt: call C function here */
-
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
- movs pc, lr /*return to the next instruction after the SWI instruction */
-
-
-DataAbortHandler: /* Data Abort handler */
-#ifdef CONFIG_ARM_ERRATA_775420
- dsb
-#endif
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- ldr r0, =DataAbortAddr
- sub r1, lr, #8
- str r1, [r0] /* Stores instruction causing data abort */
-
- bl DataAbortInterrupt /*DataAbortInterrupt :call C function here */
-
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
- subs pc, lr, #8 /* points to the instruction that caused the Data Abort exception */
-
-PrefetchAbortHandler: /* Prefetch Abort handler */
-#ifdef CONFIG_ARM_ERRATA_775420
- dsb
-#endif
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- ldr r0, =PrefetchAbortAddr
- sub r1, lr, #4
- str r1, [r0] /* Stores instruction causing prefetch abort */
-
- bl PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */
-
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
- subs pc, lr, #4 /* points to the instruction that caused the Prefetch Abort exception */
-
-.end
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cc/a4217b575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cc/a4217b575243001d18b399c1eb9b3628
deleted file mode 100644
index 77e1f3d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cc/a4217b575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,74 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache_vxworks.h
-*
-* Contains the cache related functions for VxWorks that is wrapped by
-* xil_cache.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 12/11/09 Initial release
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 7.00 mus 01/11/18 First release
-* mn 03/26/18 Change Interrupt IDs for versal
-* mn 03/26/18 Update SLCR base address
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#ifndef _XPARAMETERS_PS_H_
-#define _XPARAMETERS_PS_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "bspconfig.h"
-/************************** Constant Definitions *****************************/
-/**
- *@cond nocomments
- */
-
-/*
- * This block contains constant declarations for the peripherals
- * within the hardblock
- */
-
-/* Canonical definitions for DDR MEMORY */
-#define XPAR_DDR_MEM_BASEADDR 0x00000000U
-#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
-
-/* Canonical definitions for Interrupts */
-#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
-#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
-#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
-#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
-#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
-#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
-#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
-#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
-#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
-#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
-#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
-#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
-#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
-#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
-#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
-#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
-#define XPAR_XWDTPS_0_INTR XPS_LPD_SWDT_INT_ID
-#define XPAR_XWDTPS_1_INTR XPS_FPD_SWDT_INT_ID
-#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
-#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
-#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
-#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
-#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
-#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
-#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
-#define XPAR_XTTCPS_6_INTR XPS_TTC2_0_INT_ID
-#define XPAR_XTTCPS_7_INTR XPS_TTC2_1_INT_ID
-#define XPAR_XTTCPS_8_INTR XPS_TTC2_2_INT_ID
-#define XPAR_XTTCPS_9_INTR XPS_TTC3_0_INT_ID
-#define XPAR_XTTCPS_10_INTR XPS_TTC3_1_INT_ID
-#define XPAR_XTTCPS_11_INTR XPS_TTC3_2_INT_ID
-#define XPAR_XNANDPS8_0_INTR XPS_NAND_INT_ID
-#define XPAR_XADMAPS_0_INTR XPS_ADMA_CH0_INT_ID
-#define XPAR_XADMAPS_1_INTR XPS_ADMA_CH1_INT_ID
-#define XPAR_XADMAPS_2_INTR XPS_ADMA_CH2_INT_ID
-#define XPAR_XADMAPS_3_INTR XPS_ADMA_CH3_INT_ID
-#define XPAR_XADMAPS_4_INTR XPS_ADMA_CH4_INT_ID
-#define XPAR_XADMAPS_5_INTR XPS_ADMA_CH5_INT_ID
-#define XPAR_XADMAPS_6_INTR XPS_ADMA_CH6_INT_ID
-#define XPAR_XADMAPS_7_INTR XPS_ADMA_CH7_INT_ID
-#define XPAR_PSV_ADMA_0_INTR XPS_ADMA_CH0_INT_ID
-#define XPAR_PSV_ADMA_1_INTR XPS_ADMA_CH1_INT_ID
-#define XPAR_PSV_ADMA_2_INTR XPS_ADMA_CH2_INT_ID
-#define XPAR_PSV_ADMA_3_INTR XPS_ADMA_CH3_INT_ID
-#define XPAR_PSV_ADMA_4_INTR XPS_ADMA_CH4_INT_ID
-#define XPAR_PSV_ADMA_5_INTR XPS_ADMA_CH5_INT_ID
-#define XPAR_PSV_ADMA_6_INTR XPS_ADMA_CH6_INT_ID
-#define XPAR_PSV_ADMA_7_INTR XPS_ADMA_CH7_INT_ID
-#define XPAR_PSV_PMC_DMA_0_INTR XPS_PMCDMA0_INT_ID
-#define XPAR_PSV_PMC_DMA_1_INTR XPS_PMCDMA1_INT_ID
-#define XPAR_XMPU_LPD_INTR XPS_XMPU_LPD_INT_ID
-#define XPAR_PSV_GDMA_1_INTR XPS_ZDMA_CH1_INT_ID
-#define XPAR_PSV_GDMA_2_INTR XPS_ZDMA_CH2_INT_ID
-#define XPAR_PSV_GDMA_3_INTR XPS_ZDMA_CH3_INT_ID
-#define XPAR_PSV_GDMA_4_INTR XPS_ZDMA_CH4_INT_ID
-#define XPAR_PSV_GDMA_5_INTR XPS_ZDMA_CH5_INT_ID
-#define XPAR_PSV_GDMA_6_INTR XPS_ZDMA_CH6_INT_ID
-#define XPAR_PSV_GDMA_7_INTR XPS_ZDMA_CH7_INT_ID
-#define XPAR_XMPU_FPD_INTR XPS_XMPU_FPD_INT_ID
-#define XPAR_XCCI_FPD_INTR XPS_FPD_CCI_INT_ID
-#define XPAR_XSMMU_FPD_INTR XPS_FPD_SMMU_INT_ID
-#define XPAR_XUSBPS_0_INTR XPS_USB3_0_ENDPT_INT_ID
-#define XPAR_XUSBPS_1_INTR XPS_USB3_1_ENDPT_INT_ID
-#define XPAR_XRTCPSU_ALARM_INTR XPS_RTC_ALARM_INT_ID
-#define XPAR_XRTCPSU_SECONDS_INTR XPS_RTC_SEC_INT_ID
-#define XPAR_XSYSMONPSU_INTR XPS_AMS_INT_ID
-
-/* Canonical definitions for SCU GIC */
-#define XPAR_SCUGIC_NUM_INSTANCES 1U
-#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
-#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
-#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00002000U)
-#define XPAR_SCUGIC_ACK_BEFORE 0U
-
-#define XPAR_CPU_CORTEXA72_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA72_0_CPU_CLK_FREQ_HZ
-
-
-/*
- * This block contains constant declarations for the peripherals
- * within the hardblock. These have been put for backwards compatibility
- */
-
-#define XPS_SYS_CTRL_BASEADDR 0xF1060000U
-#define XPS_SCU_PERIPH_BASE 0xF9000000U
-#define XPS_CRP_BASEADDRESS 0xF1260000U
-#define XPS_PMC_GLOBAL_BASEADDRESS 0xF1110000U
-
-
-/* Shared Peripheral Interrupts (SPI) */
-#define XPS_FPGA0_INT_ID 121U
-#define XPS_FPGA1_INT_ID 122U
-#define XPS_FPGA2_INT_ID 123U
-#define XPS_FPGA3_INT_ID 124U
-#define XPS_FPGA4_INT_ID 125U
-#define XPS_FPGA5_INT_ID 126U
-#define XPS_FPGA6_INT_ID 127U
-#define XPS_FPGA7_INT_ID 128U
-#define XPS_FPGA8_INT_ID 136U
-#define XPS_FPGA9_INT_ID 137U
-#define XPS_FPGA10_INT_ID 138U
-#define XPS_FPGA11_INT_ID 139U
-#define XPS_FPGA12_INT_ID 140U
-#define XPS_FPGA13_INT_ID 141U
-#define XPS_FPGA14_INT_ID 142U
-#define XPS_FPGA15_INT_ID 143U
-
-/* Updated Interrupt-IDs */
-#define XPS_OCMINTR_INT_ID (10U + 32U)
-
-#define XPS_OSPI_INT_ID (124U + 32U)
-#define XPS_QSPI_INT_ID (125U + 32U)
-#define XPS_GPIO_INT_ID (13U + 32U)
-#define XPS_I2C0_INT_ID (14U + 32U)
-#define XPS_I2C1_INT_ID (15U + 32U)
-#define XPS_SPI0_INT_ID (16U + 32U)
-#define XPS_SPI1_INT_ID (17U + 32U)
-#define XPS_UART0_INT_ID (18U + 32U)
-#define XPS_UART1_INT_ID (19U + 32U)
-#define XPS_CAN0_INT_ID (20U + 32U)
-#define XPS_CAN1_INT_ID (21U + 32U)
-#define XPS_RTC_ALARM_INT_ID (142U + 32U)
-#define XPS_RTC_SEC_INT_ID (143U + 32U)
-#define XPS_TTC0_0_INT_ID (37U + 32U)
-#define XPS_TTC0_1_INT_ID (38U + 32U)
-#define XPS_TTC0_2_INT_ID (39U + 32U)
-#define XPS_TTC1_0_INT_ID (40U + 32U)
-#define XPS_TTC1_1_INT_ID (41U + 32U)
-#define XPS_TTC1_2_INT_ID (42U + 32U)
-#define XPS_TTC2_0_INT_ID (43U + 32U)
-#define XPS_TTC2_1_INT_ID (44U + 32U)
-#define XPS_TTC2_2_INT_ID (45U + 32U)
-#define XPS_TTC3_0_INT_ID (46U + 32U)
-#define XPS_TTC3_1_INT_ID (47U + 32U)
-#define XPS_TTC3_2_INT_ID (48U + 32U)
-#define XPS_SDIO0_INT_ID (126U + 32U)
-#define XPS_SDIO0_WAKE_INT_ID (127U + 32U)
-#define XPS_SDIO1_INT_ID (128U + 32U)
-#define XPS_SDIO1_WAKE_INT_ID (129U + 32U)
-#define XPS_AMS_INT_ID (53U + 32U)
-#define XPS_GEM0_INT_ID (56U + 32U)
-#define XPS_GEM0_WAKE_INT_ID (57U + 32U)
-#define XPS_GEM1_INT_ID (58U + 32U)
-#define XPS_GEM1_WAKE_INT_ID (59U + 32U)
-#define XPS_ADMA_CH0_INT_ID (60U + 32U)
-#define XPS_ADMA_CH1_INT_ID (61U + 32U)
-#define XPS_ADMA_CH2_INT_ID (62U + 32U)
-#define XPS_ADMA_CH3_INT_ID (63U + 32U)
-#define XPS_ADMA_CH4_INT_ID (64U + 32U)
-#define XPS_ADMA_CH5_INT_ID (65U + 32U)
-#define XPS_ADMA_CH6_INT_ID (66U + 32U)
-#define XPS_ADMA_CH7_INT_ID (67U + 32U)
-#define XPS_XMPU_LPD_INT_ID (68U + 32U)
-#define XPS_XMPU_FPD_INT_ID (102U + 32U)
-#define XPS_FPD_CCI_INT_ID (106U + 32U)
-#define XPS_FPD_SMMU_INT_ID (107U + 32U)
-#define XPS_PMCDMA0_INT_ID (131U + 32U)
-#define XPS_PMCDMA1_INT_ID (132U + 32U)
-
-/* REDEFINES for TEST APP */
-#define XPAR_PSV_SBSAUART_0_INTR XPS_UART0_INT_ID
-#define XPAR_PSV_SBSAUART_1_INTR XPS_UART1_INT_ID
-#define XPAR_PSV_USB_0_INTR XPS_USB0_INT_ID
-#define XPAR_PSV_USB_1_INTR XPS_USB1_INT_ID
-#define XPAR_PSV_I2C_0_INTR XPS_I2C0_INT_ID
-#define XPAR_PSV_I2C_1_INTR XPS_I2C1_INT_ID
-#define XPAR_PSV_SPI_0_INTR XPS_SPI0_INT_ID
-#define XPAR_PSV_SPI_1_INTR XPS_SPI1_INT_ID
-#define XPAR_PSV_CANFD_0_INTR XPS_CAN0_INT_ID
-#define XPAR_PSV_CANFD_1_INTR XPS_CAN1_INT_ID
-#define XPAR_PSV_GPIO_0_INTR XPS_GPIO_INT_ID
-#define XPAR_PSV_ETHERNET_0_INTR XPS_GEM0_INT_ID
-#define XPAR_PSV_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
-#define XPAR_PSV_ETHERNET_1_INTR XPS_GEM1_INT_ID
-#define XPAR_PSV_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
-#define XPAR_PSV_ETHERNET_2_INTR XPS_GEM2_INT_ID
-#define XPAR_PSV_ETHERNET_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID
-#define XPAR_PSV_ETHERNET_3_INTR XPS_GEM3_INT_ID
-#define XPAR_PSV_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
-#define XPAR_PSV_QSPI_0_INTR XPS_QSPI_INT_ID
-#define XPAR_PSV_WDT_0_INTR XPS_LPD_SWDT_INT_ID
-#define XPAR_PSV_WDT_1_INTR XPS_FPD_SWDT_INT_ID
-#define XPAR_PSV_XADC_0_INTR XPS_SYSMON_INT_ID
-#define XPAR_PSV_TTC_0_INTR XPS_TTC0_0_INT_ID
-#define XPAR_PSV_TTC_1_INTR XPS_TTC0_1_INT_ID
-#define XPAR_PSV_TTC_2_INTR XPS_TTC0_2_INT_ID
-#define XPAR_PSV_TTC_3_INTR XPS_TTC1_0_INT_ID
-#define XPAR_PSV_TTC_4_INTR XPS_TTC1_1_INT_ID
-#define XPAR_PSV_TTC_5_INTR XPS_TTC1_2_INT_ID
-#define XPAR_PSV_TTC_6_INTR XPS_TTC2_0_INT_ID
-#define XPAR_PSV_TTC_7_INTR XPS_TTC2_1_INT_ID
-#define XPAR_PSV_TTC_8_INTR XPS_TTC2_2_INT_ID
-#define XPAR_PSV_TTC_9_INTR XPS_TTC3_0_INT_ID
-#define XPAR_PSV_TTC_10_INTR XPS_TTC3_1_INT_ID
-#define XPAR_PSV_TTC_11_INTR XPS_TTC3_2_INT_ID
-#define XPAR_PSV_AMS_INTR XPS_AMS_INT_ID
-
-#define XPAR_XADCPS_NUM_INSTANCES 1U
-#define XPAR_XADCPS_0_DEVICE_ID 0U
-#define XPAR_XADCPS_0_BASEADDR (0xF8007000U)
-#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
-
-/* For backwards compatibility */
-#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
-#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
-#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
-#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
-#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
-#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
-
-#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
-
-#ifdef XPAR_CPU_CORTEXA72_0_CPU_CLK_FREQ_HZ
-#define XPAR_CPU_CORTEXA72_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA72_0_CPU_CLK_FREQ_HZ
-#endif
-
-#ifdef XPAR_CPU_CORTEXA72_1_CPU_CLK_FREQ_HZ
-#define XPAR_CPU_CORTEXA72_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA72_1_CPU_CLK_FREQ_HZ
-#endif
-
-#define XPAR_SCUWDT_DEVICE_ID 0U
-
-/**
- *@endcond
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* protection macro */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cc/e123ee565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cc/e123ee565243001d18b399c1eb9b3628
deleted file mode 100644
index 7e29233..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cc/e123ee565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,165 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_testmem.h
-* @addtogroup common_test_utils Test Utilities for Memory and Caches
-*
-* - Cache test: xil_testcache.h contains utility functions to test cache.
-*
-* - I/O test: The Xil_testio.h file contains endian related memory IO functions. A
-* subset of the memory tests can be selected or all of the tests can be run in order.
-* If there is an error detected by a subtest, the test stops and the failure code is
-* returned. Further tests are not run even if all of the tests are selected.
-*
-* - Memory test: The xil_testmem.h file contains utility functions to test memory.
-* A subset of the memory tests can be selected or all of the tests can be run
-* in order. If there is an error detected by a subtest, the test stops and the
-* failure code is returned. Further tests are not run even if all of the tests are selected.
-*
-*
-* Following list describes the supported memory tests:
-*
-* - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
-*
-* - XIL_TESTMEM_INCREMENT: This test
-* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
-* test value for memory.
-*
-* - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
-* uses a walking '1' as the test value for memory.
-* @code
-* location 1 = 0x00000001
-* location 2 = 0x00000002
-* ...
-* @endcode
-*
-* - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
-* This test uses the inverse value of the walking ones test
-* as the test value for memory.
-* @code
-* location 1 = 0xFFFFFFFE
-* location 2 = 0xFFFFFFFD
-* ...
-*@endcode
-*
-* - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
-* This test uses the inverse of the address of the location under test
-* as the test value for memory.
-*
-* - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
-* This test uses the provided patters as the test value for memory.
-* If zero is provided as the pattern the test uses '0xDEADBEEF".
-*
-* @warning
-* The tests are DESTRUCTIVE. Run before any initialized memory spaces
-* have been set up.
-* The address provided to the memory tests is not checked for
-* validity except for the NULL case. It is possible to provide a code-space
-* pointer for this test to start with and ultimately destroy executable code
-* causing random failures.
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 08/25/09 First release
-* 7.5 mus 03/10/21 Added new set of Xil_TestMem32, Xil_TestMem16 and
-* Xil_TestMem8 APIs to support memory test for memory
-* regions mapped at extended addresses
-* (addresses > 4 GB). These new set of APIs would be
-* compiled only for 32 bit Microblaze processor, if
-* XPAR_MICROBLAZE_ADDR_SIZE is greater than 32.
-* It fixes CR#1089129.
-*
-* translation_table.S contains a static page table required by MMU for
-* cortex-A72. This translation table is flat mapped (input address = output
-* address) with default memory attributes defined for versal
-* architecture. It utilizes translation granual size of 4KB with 2MB section
-* size for initial 5GB memory and 1GB section size for memory after 5GB.
-* The overview of translation table memory attributes is described below.
-*
-*| Name | Memory Range | Def. in Translation Table |
-*|-----------------------|-----------------------------------|-----------------------------|
-*| DDR | 0x000_0000_0000 - 0x000_7FFF_FFFF | Normal WB Cacheable |
-*| LPD_AFI_FS | 0x000_8000_0000 - 0x000_9FFF_FFFF | Strongly Ordered |
-*| Reserved | 0x000_A000_0000 - 0x000_A3FF_FFFF | Unassigned |
-*| FPD_AFI_0 | 0x000_A400_0000 - 0x000_AFFF_FFFF | Strongly Ordered |
-*| FPD_AFI_1 | 0x000_B000_0000 - 0x000_BFFF_FFFF | Strongly Ordered |
-*| QSPI | 0x000_C000_0000 - 0x000_DFFF_FFFF | Strongly Ordered |
-*| PCIE region 0 | 0x000_E000_0000 - 0x000_EFFF_FFFF | Strongly Ordered |
-*| PMC | 0x000_F000_0000 - 0x000_F7FF_FFFF | Strongly Ordered |
-*| STM_CORESIGHT | 0x000_F800_0000 - 0x000_F8FF_FFFF | Strongly Ordered |
-*| GIC | 0x000_F900_0000 - 0x000_F90F_FFFF | Strongly Ordered |
-*| Reserved | 0x000_F910_0000 - 0x000_FBFF_FFFF | Unassigned |
-*| CPM | 0x000_FC00_0000 - 0x000_FCFF_FFFF | Strongly Ordered |
-*| FPD slaves | 0x000_FD00_0000 - 0x000_FDFF_FFFF | Strongly Ordered |
-*| LPD slaves | 0x000_FE00_0000 - 0x000_FFDF_FFFF | Strongly Ordered |
-*| OCM | 0x000_FFE0_0000 - 0xFFF_FFFF_FFFF | Normal WB Cacheable |
-*| PMC region 0-3 | 0x001_0000_0000 - 0x001_1FFF_FFFF | Strongly Ordered |
-*| Reserved | 0x001_2000_0000 - 0x001_FFFF_FFFF | Unassigned |
-*| ME Array 0-3 | 0x002_0000_0000 - 0x002_FFFF_FFFF | Strongly Ordered |
-*| Reserved | 0x003_0000_0000 - 0x003_FFFF_FFFF | Unassigned |
-*| PL- via PS | 0x004_0000_0000 - 0x005_FFFF_FFFF | Strongly Ordered |
-*| PCIe region 1 | 0x006_0000_0000 - 0x007_FFFF_FFFF | Strongly Ordered |
-*| DDR | 0x008_0000_0000 - 0x00F_FFFF_FFFF | Normal WB Cacheable |
-*| Reserved | 0x010_0000_0000 - 0x03F_FFFF_FFFF | Unassigned |
-*| HBM 0-3 | 0x040_0000_0000 - 0x07F_FFFF_FFFF | Strongly Ordered |
-*| PCIe region 2 | 0x080_0000_0000 - 0x0BF_FFFF_FFFF | Strongly Ordered |
-*| DDR | 0x0C0_0000_0000 - 0x1B7_7FFF_FFFF | Normal WB Cacheable |
-*| Reserved | 0x1B7_8000_0000 - 0x1FF_FFFF_FFFF | Unassigned |
-*| PL- Via NoC | 0x200_0000_0000 - 0x3FF_FFFF_FFFF | Strongly Ordered |
-*| PL- Via PS | 0x400_0000_0000 - 0x4FF_FFFF_FFFF | Strongly Ordered |
-*| DDR CH1-CH3 | 0x500_0000_0000 - 0x7FF_FFFF_FFFF | Normal WB Cacheable |
-*| PL- Via NoC | 0x800_0000_0000 - 0xFFF_FFFF_FFFF | Strongly Ordered |
-*
-* @note
-*
-* For DDR region 0x0000000000 - 0x007FFFFFFF, a system where DDR is less than
-* 2GB, region after DDR and before PL is marked as undefined/reserved in
-* translation table. Region 0xF9100000 - 0xF91FFFFF is reserved memory in
-* 0x00F9000000 - 0x00F91FFFFF range, but it is marked as strongly ordered
-* because minimum section size in translation table section is 2MB.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 7.2 mus 01/09/20 Initial version
-*
-*
-******************************************************************************/
-#include "xparameters.h"
-#include "bspconfig.h"
-
- EXPORT MMUTableL0
- EXPORT MMUTableL1
- EXPORT MMUTableL2
-
- GBLA abscnt
- GBLA count
- GBLA sect
-
-Reserved EQU 0x0 ; Fault
-#if EL1_NONSECURE
-Memory EQU 0x405:OR:(2:SHL:8):OR:0x0 ; normal writeback write allocate outer shared read write */
-#else
-Memory EQU 0x405:OR:(3:SHL:8):OR:0x0 ; normal writeback write allocate inner shared read write */
-#endif
-Device EQU 0x409:OR:(1:SHL:53):OR:(1:SHL:54):OR:0x0 ; strongly ordered read write non executable
-
- AREA |.mmu_tbl0|, CODE, ALIGN=12
-
-MMUTableL0
-
-count SETA 0
- WHILE count<0x1f
- DCQU MMUTableL1+count*0x1000+0x3 ; 0x0000_0000 - 0x7F_FFFF_FFFF
-count SETA count+1
- WEND
-
-count SETA 1
- WHILE count<0x20
- DCQ MMUTableL1+count*0x1000+0x3 ; 0x80_0000_0000 - 0xFFF_FFFF_FFFF
-count SETA count+1
- WEND
-
- AREA |.mmu_tbl1|, CODE, ALIGN=12
-
-MMUTableL1
-
- DCQU MMUTableL2+0x3 ; 0x0000_0000 - 0x3FFF_FFFF
-count SETA 1 ; 0x4000_0000 - 0x1_3FFF_FFFF
- WHILE count<5
- DCQ MMUTableL2+count*0x1000+0x3 ; 1GB DDR, 512MB LPD_AFI_FS, 448MB FPD_AFI_0, 512MB QSPI,
- ; 256MB PCIe region 0, PMC 128MB, GIC 1 MB, reserved 47MB,
- ; 2GB other devices and memory, 512 MB PMC
-count SETA count+1
- WEND
-
-Fixlocl1 EQU 0x140000000
-abscnt SETA 0
-
-count SETA 0
- WHILE count<0x3
- DCQU Fixlocl1+abscnt*0x40000000+Reserved ; 0x1_4000_0000 - 0x1_FFFF_FFFF
- ; 3GB Reserved
-count SETA count+1
-abscnt SETA abscnt+1
- WEND
-count SETA 0
- WHILE count<0x4
- DCQU Fixlocl1+abscnt*0x40000000+Device ; 0x2_0000_0000 - 0x2_FFFF_FFFF
- ; 4GB ME Array 0-3
-count SETA count+1
-abscnt SETA abscnt+1
- WEND
-count SETA 0
- WHILE count<0x4
- DCQU Fixlocl1+abscnt*0x40000000+Reserved ; 0x3_0000_0000 - 0x3_FFFF_FFFF
- ; 4GB Reserved
-count SETA count+1
-abscnt SETA abscnt+1
- WEND
-
-count SETA 0
- WHILE count<0x10
- DCQU Fixlocl1+abscnt*0x40000000+Device ; 0x4_0000_0000 - 0x7_FFFF_FFFF
- ; 8GB PL - via PS, 8GB PCIe region1
-count SETA count+1
-abscnt SETA abscnt+1
- WEND
-
-#ifdef XPAR_AXI_NOC_DDR_LOW_1_BASEADDR
-DDR_1_START EQU XPAR_AXI_NOC_DDR_LOW_1_BASEADDR
-DDR_1_END EQU XPAR_AXI_NOC_DDR_LOW_1_HIGHADDR
-DDR_1_SIZE EQU (DDR_1_END - DDR_1_START+1)
-#if DDR_1_SIZE > 0x800000000
-; If DDR size is larger than 32GB, truncate to 32GB
-DDR_1_REG EQU 0x20
-#else
-DDR_1_REG EQU DDR_1_SIZE/0x40000000
-#endif
-#else
-DDR_1_REG EQU 0
-#endif
-
-UNDEF_1_REG EQU (0x20 - DDR_1_REG)
-
-; DDR based on size in hw design
-count SETA 0
- WHILE count 0x4000000000
-; If DDR size is larger than 256 GB, truncate to 256GB
-DDR_2_REG EQU 0x100
-#else
-DDR_2_REG EQU DDR_2_SIZE/0x40000000
-#endif
-#else
-DDR_2_REG EQU 0
-#endif
-
-UNDEF_2_REG EQU (0x100 - DDR_2_REG)
-
-; DDR based on size in hw design
-count SETA 0
- WHILE count 0xB780000000
-; If DDR size is larger than 734 GB, truncate to 734GB
-DDR_3_REG EQU 0x2de
-#else
-DDR_3_REG EQU DDR_3_SIZE/0x40000000
-#endif
-#else
-DDR_3_REG EQU 0
-#endif
-
-UNDEF_3_REG EQU (0x2de - DDR_3_REG)
-
-; DDR based on size in hw design
-count SETA 0
- WHILE count 0x010000000000
-; If DDR size is larger than 1TB, truncate to 1 TB
-DDR_CH_1_REG EQU 0x400 ; 0x500_0000_0000 - 0x5FF_FFFF_FFFF
-#else
-DDR_CH_1_REG EQU DDR_CH_1_SIZE/0x40000000
-#endif
-#else
-DDR_CH_1_REG EQU 0
-#endif
-
-UNDEF_CH_1_REG EQU (0x400 - DDR_CH_1_REG)
-
-; DDR based on size in hw design, Max size 1 TB
-count SETA 0
- WHILE count 0x010000000000
-; If DDR_CH_2 size is larger than 1TB, truncate to 1 TB
-DDR_CH_2_REG EQU 0x400 ; 0x600_0000_0000 - 0x6FF_FFFF_FFFF
-#else
-DDR_CH_2_REG EQU DDR_CH_2_SIZE/0x40000000
-#endif
-#else
-DDR_CH_2_REG EQU 0
-#endif
-
-UNDEF_CH_2_REG EQU (0x400 - DDR_CH_2_REG)
-
-; DDR based on size in hw design, Max size 1 TB
-count SETA 0
- WHILE count 0x010000000000
-; If DDR_CH_3 size is larger than 1TB, truncate to 1 TB */
-DDR_CH_3_REG EQU 0x400 ; 0x700_0000_0000 - 0x7FF_FFFF_FFFF
-#else
-DDR_CH_3_REG EQU DDR_CH_3_SIZE/0x40000000
-#endif
-#else
-DDR_CH_3_REG EQU 0
-#endif
-
-UNDEF_CH_3_REG EQU (0x400 - DDR_CH_3_REG)
-
-; DDR based on size in hw design, Max size 1 TB
-count SETA 0
- WHILE count 0x80000000
-; If DDR size is larger than 2GB, truncate to 2GB
-.set DDR_0_REG, 0x400
-#else
-DDR_0_REG EQU DDR_0_SIZE/0x200000
-#endif
-#else
-DDR_0_REG EQU 0
-#endif
-
-UNDEF_0_REG EQU (0x400 - DDR_0_REG)
-
-; DDR based on size in hw design
-count SETA 0
- WHILE count
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm 10/20/09 First release
-*
-*
-******************************************************************************/
-#ifndef XREG_CORTEXA9_H
-#define XREG_CORTEXA9_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/**
- *@cond nocomments
- */
-
-/* GPRs */
-#define XREG_GPR0 r0
-#define XREG_GPR1 r1
-#define XREG_GPR2 r2
-#define XREG_GPR3 r3
-#define XREG_GPR4 r4
-#define XREG_GPR5 r5
-#define XREG_GPR6 r6
-#define XREG_GPR7 r7
-#define XREG_GPR8 r8
-#define XREG_GPR9 r9
-#define XREG_GPR10 r10
-#define XREG_GPR11 r11
-#define XREG_GPR12 r12
-#define XREG_GPR13 r13
-#define XREG_GPR14 r14
-#define XREG_GPR15 r15
-#define XREG_CPSR cpsr
-
-/* Coprocessor number defines */
-#define XREG_CP0 0
-#define XREG_CP1 1
-#define XREG_CP2 2
-#define XREG_CP3 3
-#define XREG_CP4 4
-#define XREG_CP5 5
-#define XREG_CP6 6
-#define XREG_CP7 7
-#define XREG_CP8 8
-#define XREG_CP9 9
-#define XREG_CP10 10
-#define XREG_CP11 11
-#define XREG_CP12 12
-#define XREG_CP13 13
-#define XREG_CP14 14
-#define XREG_CP15 15
-
-/* Coprocessor control register defines */
-#define XREG_CR0 cr0
-#define XREG_CR1 cr1
-#define XREG_CR2 cr2
-#define XREG_CR3 cr3
-#define XREG_CR4 cr4
-#define XREG_CR5 cr5
-#define XREG_CR6 cr6
-#define XREG_CR7 cr7
-#define XREG_CR8 cr8
-#define XREG_CR9 cr9
-#define XREG_CR10 cr10
-#define XREG_CR11 cr11
-#define XREG_CR12 cr12
-#define XREG_CR13 cr13
-#define XREG_CR14 cr14
-#define XREG_CR15 cr15
-
-/* Current Processor Status Register (CPSR) Bits */
-#define XREG_CPSR_THUMB_MODE 0x20
-#define XREG_CPSR_MODE_BITS 0x1F
-#define XREG_CPSR_SYSTEM_MODE 0x1F
-#define XREG_CPSR_UNDEFINED_MODE 0x1B
-#define XREG_CPSR_DATA_ABORT_MODE 0x17
-#define XREG_CPSR_SVC_MODE 0x13
-#define XREG_CPSR_IRQ_MODE 0x12
-#define XREG_CPSR_FIQ_MODE 0x11
-#define XREG_CPSR_USER_MODE 0x10
-
-#define XREG_CPSR_IRQ_ENABLE 0x80
-#define XREG_CPSR_FIQ_ENABLE 0x40
-
-#define XREG_CPSR_N_BIT 0x80000000
-#define XREG_CPSR_Z_BIT 0x40000000
-#define XREG_CPSR_C_BIT 0x20000000
-#define XREG_CPSR_V_BIT 0x10000000
-
-
-/* CP15 defines */
-#if defined (__GNUC__) || defined (__ICCARM__)
-/* C0 Register defines */
-#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"
-#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"
-#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2"
-#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3"
-#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5"
-
-#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0"
-#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1"
-#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2"
-#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4"
-#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5"
-#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6"
-#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7"
-
-#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0"
-#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1"
-#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2"
-#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3"
-#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4"
-
-#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0"
-#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1"
-#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7"
-
-#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0"
-
-/* C1 Register Defines */
-#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0"
-#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1"
-#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2"
-
-#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0"
-#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1"
-#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2"
-#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3"
-
-#else /* RVCT */
-/* C0 Register defines */
-#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0"
-#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1"
-#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2"
-#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3"
-#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5"
-
-#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0"
-#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1"
-#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2"
-#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4"
-#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5"
-#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6"
-#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7"
-
-#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0"
-#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1"
-#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2"
-#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3"
-#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4"
-
-#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0"
-#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1"
-#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7"
-
-#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0"
-
-/* C1 Register Defines */
-#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0"
-#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1"
-#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2"
-
-#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0"
-#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1"
-#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2"
-#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3"
-#endif
-
-/* XREG_CP15_CONTROL bit defines */
-#define XREG_CP15_CONTROL_TE_BIT 0x40000000U
-#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U
-#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U
-#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U
-#define XREG_CP15_CONTROL_EE_BIT 0x02000000U
-#define XREG_CP15_CONTROL_HA_BIT 0x00020000U
-#define XREG_CP15_CONTROL_RR_BIT 0x00004000U
-#define XREG_CP15_CONTROL_V_BIT 0x00002000U
-#define XREG_CP15_CONTROL_I_BIT 0x00001000U
-#define XREG_CP15_CONTROL_Z_BIT 0x00000800U
-#define XREG_CP15_CONTROL_SW_BIT 0x00000400U
-#define XREG_CP15_CONTROL_B_BIT 0x00000080U
-#define XREG_CP15_CONTROL_C_BIT 0x00000004U
-#define XREG_CP15_CONTROL_A_BIT 0x00000002U
-#define XREG_CP15_CONTROL_M_BIT 0x00000001U
-
-#if defined (__GNUC__) || defined (__ICCARM__)
-/* C2 Register Defines */
-#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0"
-#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1"
-#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2"
-
-/* C3 Register Defines */
-#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0"
-
-/* C4 Register Defines */
-/* Not Used */
-
-/* C5 Register Defines */
-#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0"
-#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1"
-
-#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0"
-#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1"
-
-/* C6 Register Defines */
-#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0"
-#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2"
-
-/* C7 Register Defines */
-#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4"
-
-#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0"
-#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6"
-
-#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0"
-
-#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0"
-#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1"
-
-/* The CP15 register access below has been deprecated in favor of the new
- * isb instruction in Cortex A9.
- */
-#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4"
-#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6"
-
-#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1"
-#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2"
-
-#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0"
-#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1"
-#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2"
-#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3"
-
-#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4"
-#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5"
-#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6"
-#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7"
-
-#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1"
-#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2"
-
-/* The next two CP15 register accesses below have been deprecated in favor
- * of the new dsb and dmb instructions in Cortex A9.
- */
-#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4"
-#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5"
-
-#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1"
-
-#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1"
-
-#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1"
-#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2"
-
-/* C8 Register Defines */
-#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0"
-#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1"
-#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2"
-#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3"
-
-#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0"
-#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1"
-#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2"
-
-#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0"
-#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1"
-#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2"
-
-#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0"
-#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1"
-#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2"
-#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3"
-
-/* C9 Register Defines */
-#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0"
-#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1"
-#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2"
-#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3"
-#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4"
-#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5"
-
-#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0"
-#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1"
-#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2"
-
-#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0"
-#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1"
-#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2"
-
-/* C10 Register Defines */
-#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0"
-
-#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0"
-#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1"
-
-/* C11 Register Defines */
-/* Not used */
-
-/* C12 Register Defines */
-#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0"
-#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1"
-
-#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0"
-#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1"
-
-/* C13 Register Defines */
-#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1"
-#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2"
-#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3"
-#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4"
-
-/* C14 Register Defines */
-/* not used */
-
-/* C15 Register Defines */
-#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0"
-#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0"
-
-#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2"
-#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4"
-
-#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2"
-
-#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2"
-
-#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2"
-
-#else
-/* C2 Register Defines */
-#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0"
-#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1"
-#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2"
-
-/* C3 Register Defines */
-#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0"
-
-/* C4 Register Defines */
-/* Not Used */
-
-/* C5 Register Defines */
-#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0"
-#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1"
-
-#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0"
-#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1"
-
-/* C6 Register Defines */
-#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0"
-#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2"
-
-/* C7 Register Defines */
-#define XREG_CP15_NOP "cp15:0:c7:c0:4"
-
-#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0"
-#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6"
-
-#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0"
-
-#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0"
-#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1"
-
-/* The CP15 register access below has been deprecated in favor of the new
- * isb instruction in Cortex A9.
- */
-#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4"
-#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6"
-
-#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1"
-#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2"
-
-#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0"
-#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1"
-#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2"
-#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3"
-
-#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4"
-#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5"
-#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6"
-#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7"
-
-#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1"
-#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2"
-
-/* The next two CP15 register accesses below have been deprecated in favor
- * of the new dsb and dmb instructions in Cortex A9.
- */
-#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4"
-#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5"
-
-#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1"
-
-#define XREG_CP15_NOP2 "cp15:0:c7:c13:1"
-
-#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1"
-#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2"
-
-/* C8 Register Defines */
-#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0"
-#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1"
-#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2"
-#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3"
-
-#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0"
-#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1"
-#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2"
-
-#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0"
-#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1"
-#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2"
-
-#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0"
-#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1"
-#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2"
-#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3"
-
-/* C9 Register Defines */
-#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0"
-#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1"
-#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2"
-#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3"
-#define XREG_CP15_SW_INC "cp15:0:c9:c12:4"
-#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5"
-
-#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0"
-#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1"
-#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2"
-
-#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0"
-#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1"
-#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2"
-
-/* C10 Register Defines */
-#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0"
-
-#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0"
-#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1"
-
-/* C11 Register Defines */
-/* Not used */
-
-/* C12 Register Defines */
-#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0"
-#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1"
-
-#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0"
-#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1"
-
-/* C13 Register Defines */
-#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1"
-#define USER_RW_THREAD_PID "cp15:0:c13:c0:2"
-#define USER_RO_THREAD_PID "cp15:0:c13:c0:3"
-#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4"
-
-/* C14 Register Defines */
-/* not used */
-
-/* C15 Register Defines */
-#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0"
-#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0"
-
-#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2"
-#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4"
-
-#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2"
-
-#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2"
-
-#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2"
-#endif
-
-
-/* MPE register definitions */
-#define XREG_FPSID c0
-#define XREG_FPSCR c1
-#define XREG_MVFR1 c6
-#define XREG_MVFR0 c7
-#define XREG_FPEXC c8
-#define XREG_FPINST c9
-#define XREG_FPINST2 c10
-
-/* FPSID bits */
-#define XREG_FPSID_IMPLEMENTER_BIT (24)
-#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT)
-#define XREG_FPSID_SOFTWARE (1<<23)
-#define XREG_FPSID_ARCH_BIT (16)
-#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
-#define XREG_FPSID_PART_BIT (8)
-#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
-#define XREG_FPSID_VARIANT_BIT (4)
-#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
-#define XREG_FPSID_REV_BIT (0)
-#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT)
-
-/* FPSCR bits */
-#define XREG_FPSCR_N_BIT (1 << 31)
-#define XREG_FPSCR_Z_BIT (1 << 30)
-#define XREG_FPSCR_C_BIT (1 << 29)
-#define XREG_FPSCR_V_BIT (1 << 28)
-#define XREG_FPSCR_QC (1 << 27)
-#define XREG_FPSCR_AHP (1 << 26)
-#define XREG_FPSCR_DEFAULT_NAN (1 << 25)
-#define XREG_FPSCR_FLUSHTOZERO (1 << 24)
-#define XREG_FPSCR_ROUND_NEAREST (0 << 22)
-#define XREG_FPSCR_ROUND_PLUSINF (1 << 22)
-#define XREG_FPSCR_ROUND_MINUSINF (2 << 22)
-#define XREG_FPSCR_ROUND_TOZERO (3 << 22)
-#define XREG_FPSCR_RMODE_BIT (22)
-#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
-#define XREG_FPSCR_STRIDE_BIT (20)
-#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
-#define XREG_FPSCR_LENGTH_BIT (16)
-#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
-#define XREG_FPSCR_IDC (1 << 7)
-#define XREG_FPSCR_IXC (1 << 4)
-#define XREG_FPSCR_UFC (1 << 3)
-#define XREG_FPSCR_OFC (1 << 2)
-#define XREG_FPSCR_DZC (1 << 1)
-#define XREG_FPSCR_IOC (1 << 0)
-
-/* MVFR0 bits */
-#define XREG_MVFR0_RMODE_BIT (28)
-#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT)
-#define XREG_MVFR0_SHORT_VEC_BIT (24)
-#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT)
-#define XREG_MVFR0_SQRT_BIT (20)
-#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT)
-#define XREG_MVFR0_DIVIDE_BIT (16)
-#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT)
-#define XREG_MVFR0_EXEC_TRAP_BIT (12)
-#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT)
-#define XREG_MVFR0_DP_BIT (8)
-#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT)
-#define XREG_MVFR0_SP_BIT (4)
-#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT)
-#define XREG_MVFR0_A_SIMD_BIT (0)
-#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT)
-
-/* FPEXC bits */
-#define XREG_FPEXC_EX (1 << 31)
-#define XREG_FPEXC_EN (1 << 30)
-#define XREG_FPEXC_DEX (1 << 29)
-
-
-/**
- *@endcond
- */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XREG_CORTEXA9_H */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cd/200593595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cd/200593595243001d18b399c1eb9b3628
deleted file mode 100644
index 82dd34a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cd/200593595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,24 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) sint32 unlink(char8 *path);
-}
-#endif
-/*
- * unlink -- since we have no file system,
- * we just return an error.
- */
-__attribute__((weak)) sint32 unlink(char8 *path)
-{
- (void) path;
- errno = EIO;
- return (-1);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cd/b1600c545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cd/b1600c545243001d18b399c1eb9b3628
deleted file mode 100644
index 00e031a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cd/b1600c545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,3380 +0,0 @@
-TRACE::2022-07-11.20:23:18::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:18::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:18::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:18::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:18::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:18::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:18::SCWPlatform::Do not have an existing db opened.
-TRACE::2022-07-11.20:23:20::SCWPlatform::Opened new HwDB with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:20::SCWWriter::formatted JSON is {
- "platformName": "phased_array_platform",
- "sprVersion": "2.0",
- "mode": "gui",
- "dsaType": "Fixed",
- "platformDesc": "phased_array_platform",
- "platHandOff": "/home/dylan/Documents/FPGA/phased_array/design_1_wrapper.xsa",
- "platIntHandOff": "/hw/design_1_wrapper.xsa",
- "deviceType": "zynq",
- "platIsPrebuiltAutogen": "false",
- "platIsNoBootBsp": "false",
- "hasFsblMakeHasChanges": "false",
- "hasPmufwMakeHasChanges": "false",
- "platPreBuiltFlag": false,
- "platformSamplesDir": ""
-}
-TRACE::2022-07-11.20:23:20::SCWWriter::formatted JSON is {
- "platformName": "phased_array_platform",
- "sprVersion": "2.0",
- "mode": "gui",
- "dsaType": "Fixed",
- "platformDesc": "phased_array_platform",
- "platHandOff": "/home/dylan/Documents/FPGA/phased_array/design_1_wrapper.xsa",
- "platIntHandOff": "/hw/design_1_wrapper.xsa",
- "deviceType": "zynq",
- "platIsPrebuiltAutogen": "false",
- "platIsNoBootBsp": "false",
- "hasFsblMakeHasChanges": "false",
- "hasPmufwMakeHasChanges": "false",
- "platPreBuiltFlag": false,
- "platformSamplesDir": "",
- "platActiveSys": "phased_array_platform",
- "systems": [{
- "systemName": "phased_array_platform",
- "systemDesc": "phased_array_platform",
- "sysIsBootAutoGen": "true",
- "systemDispName": "phased_array_platform"
- }]
-}
-TRACE::2022-07-11.20:23:20::SCWPlatform::Boot application domains not present, creating them
-TRACE::2022-07-11.20:23:20::SCWDomain::checking for install qemu data :
-TRACE::2022-07-11.20:23:21::SCWDomain:: Using the QEMU Data from install at : /hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/
-TRACE::2022-07-11.20:23:21::SCWDomain:: Using the QEMU args from install at : /hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt
-TRACE::2022-07-11.20:23:21::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:21::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:21::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:21::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:21::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:21::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:21::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:21::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:21::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:21::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:21::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:21::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:21::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:21::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:21::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:21::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:21::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:21::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:21::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:21::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:21::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:21::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:21::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:21::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:21::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:21::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:21::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:21::SCWPlatform::Boot application domain added for zynq_fsbl
-TRACE::2022-07-11.20:23:21::SCWPlatform::Generating the sources .
-TRACE::2022-07-11.20:23:21::SCWBDomain::Generating boot domain sources.
-TRACE::2022-07-11.20:23:21::SCWBDomain:: Generating the zynq_fsbl Application.
-TRACE::2022-07-11.20:23:21::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:21::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:21::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:21::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:21::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:21::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:21::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:21::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:21::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:21::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:21::SCWMssOS::DEBUG: swdes dump
-TRACE::2022-07-11.20:23:21::SCWMssOS::No sw design opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:21::SCWMssOS::mss does not exists at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:21::SCWMssOS::Creating sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:21::SCWMssOS::Adding the swdes entry, created swdb /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss with des name /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:21::SCWMssOS::updating the scw layer changes to swdes at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:21::SCWMssOS::Writing mss at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:21::SCWMssOS::Completed writing the mss file at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp
-TRACE::2022-07-11.20:23:21::SCWMssOS::Picking up changes from newly written mss file into SCW Layer.
-TRACE::2022-07-11.20:23:21::SCWMssOS::Updated the changes from newly written mss file into SCW Layer.
-TRACE::2022-07-11.20:23:21::SCWBDomain::Completed writing the mss file at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp
-TRACE::2022-07-11.20:23:37::SCWPlatform::Generating sources Done.
-TRACE::2022-07-11.20:23:37::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:37::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:37::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:37::SCWMssOS::DEBUG: swdes dump
-TRACE::2022-07-11.20:23:37::SCWMssOS::No sw design opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:37::SCWMssOS::mss exists loading the mss file /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:37::SCWMssOS::Opened the sw design from mss /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:37::SCWMssOS::Adding the swdes entry /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss with des name system
-TRACE::2022-07-11.20:23:37::SCWMssOS::updating the scw layer about changes
-TRACE::2022-07-11.20:23:37::SCWMssOS::Opened the sw design. /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:37::SCWMssOS::Saving the mss changes /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:37::SCWMssOS::Found a swdesign opened with the mssfile.
-TRACE::2022-07-11.20:23:37::SCWMssOS::Completed writemss as part of save.
-TRACE::2022-07-11.20:23:37::SCWMssOS::Commit changes completed.
-TRACE::2022-07-11.20:23:37::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:37::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:37::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:37::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:37::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:37::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:37::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:37::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:37::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:37::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:37::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:37::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:37::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:37::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:37::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:37::SCWWriter::formatted JSON is {
- "platformName": "phased_array_platform",
- "sprVersion": "2.0",
- "mode": "gui",
- "dsaType": "Fixed",
- "platformDesc": "phased_array_platform",
- "platHandOff": "/home/dylan/Documents/FPGA/phased_array/design_1_wrapper.xsa",
- "platIntHandOff": "/hw/design_1_wrapper.xsa",
- "deviceType": "zynq",
- "platIsPrebuiltAutogen": "false",
- "platIsNoBootBsp": "false",
- "platFsblTarget": "ps7_cortexa9_0",
- "hasFsblMakeHasChanges": "false",
- "hasPmufwMakeHasChanges": "false",
- "fsblExtraCompilerFlags": "-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ",
- "platPreBuiltFlag": false,
- "platformSamplesDir": "",
- "platActiveSys": "phased_array_platform",
- "systems": [{
- "systemName": "phased_array_platform",
- "systemDesc": "phased_array_platform",
- "sysIsBootAutoGen": "true",
- "systemDispName": "phased_array_platform",
- "sysActiveDom": "zynq_fsbl",
- "sysDefaultDom": "",
- "domains": [{
- "domainName": "zynq_fsbl",
- "domainDispName": "zynq_fsbl",
- "domainDesc": "FSBL Application BSP - Auto Generated.",
- "processors": "ps7_cortexa9_0",
- "os": "standalone",
- "sdxOs": "standalone",
- "debugEnable": "",
- "domRuntimes": ["cpp"],
- "swRepo": "",
- "mssOsVer": "7.6",
- "mssFile": "",
- "md5Digest": "3ad66e6342e47cdeb46ebdacd606f8ba",
- "compatibleApp": "zynq_fsbl",
- "domType": "bootDomain",
- "arch": "32-bit",
- "appSettings": {
- "appCompilerFlags": "",
- "appLinkerFlags": ""
- },
- "addedLibs": ["xilffs:4.6", "xilrsa:1.6"],
- "libOptions": {
- "libsContainingOptions": []
- },
- "prebuiltLibs": {
- "prebuiltIncPath": [],
- "prebuiltLibPath": []
- },
- "isolation": {
- }
- }]
- }]
-}
-TRACE::2022-07-11.20:23:37::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:37::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:37::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:37::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:37::SCWDomain::checking for install qemu data :
-TRACE::2022-07-11.20:23:37::SCWDomain:: Using the QEMU Data from install at : /hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/
-TRACE::2022-07-11.20:23:37::SCWDomain:: Using the QEMU args from install at : /hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt
-TRACE::2022-07-11.20:23:37::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:37::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:37::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:37::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:37::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:37::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:37::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:37::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:37::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:37::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:37::SCWMssOS::No sw design opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:37::SCWMssOS::mss does not exists at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:37::SCWMssOS::Creating sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:37::SCWMssOS::Adding the swdes entry, created swdb /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss with des name /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:37::SCWMssOS::updating the scw layer changes to swdes at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:37::SCWMssOS::Writing mss at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:37::SCWMssOS::Completed writing the mss file at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp
-TRACE::2022-07-11.20:23:37::SCWMssOS::Picking up changes from newly written mss file into SCW Layer.
-TRACE::2022-07-11.20:23:37::SCWMssOS::Updated the changes from newly written mss file into SCW Layer.
-TRACE::2022-07-11.20:23:37::SCWMssOS::Completed writing the mss file at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp
-TRACE::2022-07-11.20:23:37::SCWMssOS::Forcing BSP Sources regeneration.
-TRACE::2022-07-11.20:23:38::SCWMssOS::Saving the mss changes /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:38::SCWMssOS::Found a swdesign opened with the mssfile.
-TRACE::2022-07-11.20:23:38::SCWMssOS::Completed writemss as part of save.
-TRACE::2022-07-11.20:23:38::SCWMssOS::Commit changes completed.
-TRACE::2022-07-11.20:23:38::SCWMssOS::Saving the mss changes /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:38::SCWMssOS::Adding the swdes entry, mss present, able to open swdb /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss with des name system_0
-TRACE::2022-07-11.20:23:38::SCWMssOS::Writing the mss file completed /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:38::SCWMssOS::Commit changes completed.
-TRACE::2022-07-11.20:23:38::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:38::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:38::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:38::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:38::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:38::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:38::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:38::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:38::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:38::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:38::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:38::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:38::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:38::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:38::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:38::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:38::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:38::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:38::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:38::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:38::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:38::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:38::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:38::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:38::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:38::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:38::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:38::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:38::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:38::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:38::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:38::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:38::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:38::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:38::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:38::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:38::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:38::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:38::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:38::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:38::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:38::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:38::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:38::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:38::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:38::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:38::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:38::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:38::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:38::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:38::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:38::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:38::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:38::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:38::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:38::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:38::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:38::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:38::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:38::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:38::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:38::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:38::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:38::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:38::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:38::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:38::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:38::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:38::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:38::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:38::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:38::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:38::SCWWriter::formatted JSON is {
- "platformName": "phased_array_platform",
- "sprVersion": "2.0",
- "mode": "gui",
- "dsaType": "Fixed",
- "platformDesc": "phased_array_platform",
- "platHandOff": "/home/dylan/Documents/FPGA/phased_array/design_1_wrapper.xsa",
- "platIntHandOff": "/hw/design_1_wrapper.xsa",
- "deviceType": "zynq",
- "platIsPrebuiltAutogen": "false",
- "platIsNoBootBsp": "false",
- "platFsblTarget": "ps7_cortexa9_0",
- "hasFsblMakeHasChanges": "false",
- "hasPmufwMakeHasChanges": "false",
- "fsblExtraCompilerFlags": "-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ",
- "platPreBuiltFlag": false,
- "platformSamplesDir": "",
- "platActiveSys": "phased_array_platform",
- "systems": [{
- "systemName": "phased_array_platform",
- "systemDesc": "phased_array_platform",
- "sysIsBootAutoGen": "true",
- "systemDispName": "phased_array_platform",
- "sysActiveDom": "standalone_domain",
- "sysDefaultDom": "standalone_domain",
- "domains": [{
- "domainName": "zynq_fsbl",
- "domainDispName": "zynq_fsbl",
- "domainDesc": "FSBL Application BSP - Auto Generated.",
- "processors": "ps7_cortexa9_0",
- "os": "standalone",
- "sdxOs": "standalone",
- "debugEnable": "",
- "domRuntimes": ["cpp"],
- "swRepo": "",
- "mssOsVer": "7.6",
- "mssFile": "",
- "md5Digest": "3ad66e6342e47cdeb46ebdacd606f8ba",
- "compatibleApp": "zynq_fsbl",
- "domType": "bootDomain",
- "arch": "32-bit",
- "appSettings": {
- "appCompilerFlags": "",
- "appLinkerFlags": ""
- },
- "addedLibs": ["xilffs:4.6", "xilrsa:1.6"],
- "libOptions": {
- "libsContainingOptions": []
- },
- "prebuiltLibs": {
- "prebuiltIncPath": [],
- "prebuiltLibPath": []
- },
- "isolation": {
- }
- }, {
- "domainName": "standalone_domain",
- "domainDispName": "standalone_domain",
- "domainDesc": "standalone_domain",
- "processors": "ps7_cortexa9_0",
- "os": "standalone",
- "sdxOs": "standalone",
- "qemuArgs": "/hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt",
- "qemuData": "/hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/",
- "debugEnable": "False",
- "domRuntimes": ["cpp"],
- "swRepo": "",
- "mssOsVer": "7.6",
- "mssFile": "",
- "md5Digest": "8f4cd5b2e4c0f3d4481583b0fc9b267f",
- "compatibleApp": "",
- "domType": "mssDomain",
- "appSettings": {
- "appCompilerFlags": "",
- "appLinkerFlags": ""
- },
- "addedLibs": [],
- "libOptions": {
- "libsContainingOptions": []
- },
- "prebuiltLibs": {
- "prebuiltIncPath": [],
- "prebuiltLibPath": []
- },
- "isolation": {
- }
- }]
- }]
-}
-LOG::2022-07-11.20:23:38::SCWPlatform::Started generating the artifacts platform phased_array_platform
-TRACE::2022-07-11.20:23:38::SCWPlatform::Sanity checking of platform is completed
-LOG::2022-07-11.20:23:38::SCWPlatform::Started generating the artifacts for system configuration phased_array_platform
-LOG::2022-07-11.20:23:38::SCWSystem::Checking the domain zynq_fsbl
-LOG::2022-07-11.20:23:38::SCWSystem::Doing application build for : zynq_fsbl
-TRACE::2022-07-11.20:23:38::SCWBDomain::Not a forced makefile updation, No changes are present.
-TRACE::2022-07-11.20:23:38::SCWDomain::Skipping the build for domain : zynq_fsbl
-LOG::2022-07-11.20:23:38::SCWSystem::Checking the domain standalone_domain
-LOG::2022-07-11.20:23:38::SCWSystem::Not a boot domain
-LOG::2022-07-11.20:23:39::SCWSystem::Started Processing the domain standalone_domain
-TRACE::2022-07-11.20:23:39::SCWDomain::Generating domain artifcats
-TRACE::2022-07-11.20:23:39::SCWMssOS::Generating standalone artifcats
-TRACE::2022-07-11.20:23:39::SCWMssOS::Copying the qemu file from /hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt To /home/dylan/workspace/phased_array_platform/export/phased_array_platform/sw/phased_array_platform/qemu/
-TRACE::2022-07-11.20:23:39::SCWMssOS::Copying the qemu file from /hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt To /home/dylan/workspace/phased_array_platform/export/phased_array_platform/sw/phased_array_platform/standalone_domain/qemu/
-TRACE::2022-07-11.20:23:39::SCWMssOS:: Copying the user libraries.
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::Completed writing the mss file at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp
-TRACE::2022-07-11.20:23:39::SCWMssOS::Mss edits present, copying mssfile into export location /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::bsp generated is upto date with the mss file. Skipping bsp generation.
-TRACE::2022-07-11.20:23:39::SCWMssOS::BSP is already built. skipping the bsp build ...
-TRACE::2022-07-11.20:23:39::SCWDomain::Skipping the build for domain : standalone_domain
-TRACE::2022-07-11.20:23:39::SCWMssOS::skipping the bsp build ...
-TRACE::2022-07-11.20:23:39::SCWMssOS::Copying to export directory.
-TRACE::2022-07-11.20:23:39::SCWMssOS:: Checking if to create the Supporting Applications
-TRACE::2022-07-11.20:23:39::SCWMssOS:: No Linux domain exists, trying to generate FSBL
-TRACE::2022-07-11.20:23:39::SCWMssOS:: Completed Standalone Artifacts creation
-LOG::2022-07-11.20:23:39::SCWSystem::Completed Processing the domain standalone_domain
-LOG::2022-07-11.20:23:39::SCWSystem::Completed Processing the sysconfig phased_array_platform
-LOG::2022-07-11.20:23:39::SCWPlatform::Completed generating the artifacts for system configuration phased_array_platform
-TRACE::2022-07-11.20:23:39::SCWPlatform::Started preparing the platform
-TRACE::2022-07-11.20:23:39::SCWSystem::Writing the bif file for system config phased_array_platform
-TRACE::2022-07-11.20:23:39::SCWSystem::dir created
-TRACE::2022-07-11.20:23:39::SCWSystem::Writing the bif
-TRACE::2022-07-11.20:23:39::SCWPlatform::Started writing the spfm file
-TRACE::2022-07-11.20:23:39::SCWPlatform::Started writing the xpfm file
-TRACE::2022-07-11.20:23:39::SCWPlatform::Completed generating the platform
-TRACE::2022-07-11.20:23:39::SCWMssOS::Saving the mss changes /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::Found a swdesign opened with the mssfile.
-TRACE::2022-07-11.20:23:39::SCWMssOS::Completed writemss as part of save.
-TRACE::2022-07-11.20:23:39::SCWMssOS::Commit changes completed.
-TRACE::2022-07-11.20:23:39::SCWMssOS::Saving the mss changes /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::Found a swdesign opened with the mssfile.
-TRACE::2022-07-11.20:23:39::SCWMssOS::Completed writemss as part of save.
-TRACE::2022-07-11.20:23:39::SCWMssOS::Commit changes completed.
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWWriter::formatted JSON is {
- "platformName": "phased_array_platform",
- "sprVersion": "2.0",
- "mode": "gui",
- "dsaType": "Fixed",
- "platformDesc": "phased_array_platform",
- "platHandOff": "/home/dylan/Documents/FPGA/phased_array/design_1_wrapper.xsa",
- "platIntHandOff": "/hw/design_1_wrapper.xsa",
- "deviceType": "zynq",
- "platIsPrebuiltAutogen": "false",
- "platIsNoBootBsp": "false",
- "platFsblTarget": "ps7_cortexa9_0",
- "hasFsblMakeHasChanges": "false",
- "hasPmufwMakeHasChanges": "false",
- "fsblExtraCompilerFlags": "-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ",
- "platPreBuiltFlag": false,
- "platformSamplesDir": "",
- "platActiveSys": "phased_array_platform",
- "systems": [{
- "systemName": "phased_array_platform",
- "systemDesc": "phased_array_platform",
- "sysIsBootAutoGen": "true",
- "systemDispName": "phased_array_platform",
- "sysActiveDom": "standalone_domain",
- "sysDefaultDom": "standalone_domain",
- "domains": [{
- "domainName": "zynq_fsbl",
- "domainDispName": "zynq_fsbl",
- "domainDesc": "FSBL Application BSP - Auto Generated.",
- "processors": "ps7_cortexa9_0",
- "os": "standalone",
- "sdxOs": "standalone",
- "debugEnable": "",
- "domRuntimes": ["cpp"],
- "swRepo": "",
- "mssOsVer": "7.6",
- "mssFile": "",
- "md5Digest": "3ad66e6342e47cdeb46ebdacd606f8ba",
- "compatibleApp": "zynq_fsbl",
- "domType": "bootDomain",
- "arch": "32-bit",
- "appSettings": {
- "appCompilerFlags": "",
- "appLinkerFlags": ""
- },
- "addedLibs": ["xilffs:4.6", "xilrsa:1.6"],
- "libOptions": {
- "libsContainingOptions": []
- },
- "prebuiltLibs": {
- "prebuiltIncPath": [],
- "prebuiltLibPath": []
- },
- "isolation": {
- }
- }, {
- "domainName": "standalone_domain",
- "domainDispName": "standalone_domain",
- "domainDesc": "standalone_domain",
- "processors": "ps7_cortexa9_0",
- "os": "standalone",
- "sdxOs": "standalone",
- "qemuArgs": "/hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt",
- "qemuData": "/hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/",
- "debugEnable": "False",
- "domRuntimes": ["cpp"],
- "swRepo": "",
- "mssOsVer": "7.6",
- "mssFile": "",
- "md5Digest": "8f4cd5b2e4c0f3d4481583b0fc9b267f",
- "compatibleApp": "",
- "domType": "mssDomain",
- "appSettings": {
- "appCompilerFlags": "",
- "appLinkerFlags": ""
- },
- "addedLibs": [],
- "libOptions": {
- "libsContainingOptions": []
- },
- "prebuiltLibs": {
- "prebuiltIncPath": [],
- "prebuiltLibPath": []
- },
- "isolation": {
- }
- }]
- }]
-}
-KEYINFO::2022-07-11.20:23:39::SCWPlatform::updated the xpfm file.
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::Saving the mss changes /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::Found a swdesign opened with the mssfile.
-TRACE::2022-07-11.20:23:39::SCWMssOS::Completed writemss as part of save.
-TRACE::2022-07-11.20:23:39::SCWMssOS::Commit changes completed.
-TRACE::2022-07-11.20:23:39::SCWMssOS::Saving the mss changes /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::Found a swdesign opened with the mssfile.
-TRACE::2022-07-11.20:23:39::SCWMssOS::Completed writemss as part of save.
-TRACE::2022-07-11.20:23:39::SCWMssOS::Commit changes completed.
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWWriter::formatted JSON is {
- "platformName": "phased_array_platform",
- "sprVersion": "2.0",
- "mode": "gui",
- "dsaType": "Fixed",
- "platformDesc": "phased_array_platform",
- "platHandOff": "/home/dylan/Documents/FPGA/phased_array/design_1_wrapper.xsa",
- "platIntHandOff": "/hw/design_1_wrapper.xsa",
- "deviceType": "zynq",
- "platIsPrebuiltAutogen": "false",
- "platIsNoBootBsp": "false",
- "platFsblTarget": "ps7_cortexa9_0",
- "hasFsblMakeHasChanges": "false",
- "hasPmufwMakeHasChanges": "false",
- "fsblExtraCompilerFlags": "-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ",
- "platPreBuiltFlag": false,
- "platformSamplesDir": "",
- "platActiveSys": "phased_array_platform",
- "systems": [{
- "systemName": "phased_array_platform",
- "systemDesc": "phased_array_platform",
- "sysIsBootAutoGen": "true",
- "systemDispName": "phased_array_platform",
- "sysActiveDom": "standalone_domain",
- "sysDefaultDom": "standalone_domain",
- "domains": [{
- "domainName": "zynq_fsbl",
- "domainDispName": "zynq_fsbl",
- "domainDesc": "FSBL Application BSP - Auto Generated.",
- "processors": "ps7_cortexa9_0",
- "os": "standalone",
- "sdxOs": "standalone",
- "debugEnable": "",
- "domRuntimes": ["cpp"],
- "swRepo": "",
- "mssOsVer": "7.6",
- "mssFile": "",
- "md5Digest": "3ad66e6342e47cdeb46ebdacd606f8ba",
- "compatibleApp": "zynq_fsbl",
- "domType": "bootDomain",
- "arch": "32-bit",
- "appSettings": {
- "appCompilerFlags": "",
- "appLinkerFlags": ""
- },
- "addedLibs": ["xilffs:4.6", "xilrsa:1.6"],
- "libOptions": {
- "libsContainingOptions": []
- },
- "prebuiltLibs": {
- "prebuiltIncPath": [],
- "prebuiltLibPath": []
- },
- "isolation": {
- }
- }, {
- "domainName": "standalone_domain",
- "domainDispName": "standalone_domain",
- "domainDesc": "standalone_domain",
- "processors": "ps7_cortexa9_0",
- "os": "standalone",
- "sdxOs": "standalone",
- "qemuArgs": "/hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt",
- "qemuData": "/hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/",
- "debugEnable": "False",
- "domRuntimes": ["cpp"],
- "swRepo": "",
- "mssOsVer": "7.6",
- "mssFile": "",
- "md5Digest": "8f4cd5b2e4c0f3d4481583b0fc9b267f",
- "compatibleApp": "",
- "domType": "mssDomain",
- "appSettings": {
- "appCompilerFlags": "",
- "appLinkerFlags": ""
- },
- "addedLibs": [],
- "libOptions": {
- "libsContainingOptions": []
- },
- "prebuiltLibs": {
- "prebuiltIncPath": [],
- "prebuiltLibPath": []
- },
- "isolation": {
- }
- }]
- }]
-}
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::Saving the mss changes /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::Found a swdesign opened with the mssfile.
-TRACE::2022-07-11.20:23:39::SCWMssOS::Completed writemss as part of save.
-TRACE::2022-07-11.20:23:39::SCWMssOS::Commit changes completed.
-TRACE::2022-07-11.20:23:39::SCWMssOS::Saving the mss changes /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::Found a swdesign opened with the mssfile.
-TRACE::2022-07-11.20:23:39::SCWMssOS::Completed writemss as part of save.
-TRACE::2022-07-11.20:23:39::SCWMssOS::Commit changes completed.
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWWriter::formatted JSON is {
- "platformName": "phased_array_platform",
- "sprVersion": "2.0",
- "mode": "gui",
- "dsaType": "Fixed",
- "platformDesc": "phased_array_platform",
- "platHandOff": "/home/dylan/Documents/FPGA/phased_array/design_1_wrapper.xsa",
- "platIntHandOff": "/hw/design_1_wrapper.xsa",
- "deviceType": "zynq",
- "platIsPrebuiltAutogen": "false",
- "platIsNoBootBsp": "false",
- "platFsblTarget": "ps7_cortexa9_0",
- "hasFsblMakeHasChanges": "false",
- "hasPmufwMakeHasChanges": "false",
- "fsblExtraCompilerFlags": "-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ",
- "platPreBuiltFlag": false,
- "platformSamplesDir": "",
- "platActiveSys": "phased_array_platform",
- "systems": [{
- "systemName": "phased_array_platform",
- "systemDesc": "phased_array_platform",
- "sysIsBootAutoGen": "true",
- "systemDispName": "phased_array_platform",
- "sysActiveDom": "standalone_domain",
- "sysDefaultDom": "standalone_domain",
- "domains": [{
- "domainName": "zynq_fsbl",
- "domainDispName": "zynq_fsbl",
- "domainDesc": "FSBL Application BSP - Auto Generated.",
- "processors": "ps7_cortexa9_0",
- "os": "standalone",
- "sdxOs": "standalone",
- "debugEnable": "",
- "domRuntimes": ["cpp"],
- "swRepo": "",
- "mssOsVer": "7.6",
- "mssFile": "",
- "md5Digest": "3ad66e6342e47cdeb46ebdacd606f8ba",
- "compatibleApp": "zynq_fsbl",
- "domType": "bootDomain",
- "arch": "32-bit",
- "appSettings": {
- "appCompilerFlags": "",
- "appLinkerFlags": ""
- },
- "addedLibs": ["xilffs:4.6", "xilrsa:1.6"],
- "libOptions": {
- "libsContainingOptions": []
- },
- "prebuiltLibs": {
- "prebuiltIncPath": [],
- "prebuiltLibPath": []
- },
- "isolation": {
- }
- }, {
- "domainName": "standalone_domain",
- "domainDispName": "standalone on ps7_cortexa9_0",
- "domainDesc": "standalone_domain",
- "processors": "ps7_cortexa9_0",
- "os": "standalone",
- "sdxOs": "standalone",
- "qemuArgs": "/hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt",
- "qemuData": "/hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/",
- "debugEnable": "False",
- "domRuntimes": ["cpp"],
- "swRepo": "",
- "mssOsVer": "7.6",
- "mssFile": "",
- "md5Digest": "8f4cd5b2e4c0f3d4481583b0fc9b267f",
- "compatibleApp": "",
- "domType": "mssDomain",
- "appSettings": {
- "appCompilerFlags": "",
- "appLinkerFlags": ""
- },
- "addedLibs": [],
- "libOptions": {
- "libsContainingOptions": []
- },
- "prebuiltLibs": {
- "prebuiltIncPath": [],
- "prebuiltLibPath": []
- },
- "isolation": {
- }
- }]
- }]
-}
-TRACE::2022-07-11.20:23:39::SCWMssOS::Saving the mss changes /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::Found a swdesign opened with the mssfile.
-TRACE::2022-07-11.20:23:39::SCWMssOS::Completed writemss as part of save.
-TRACE::2022-07-11.20:23:39::SCWMssOS::Commit changes completed.
-TRACE::2022-07-11.20:23:39::SCWMssOS::Saving the mss changes /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::Found a swdesign opened with the mssfile.
-TRACE::2022-07-11.20:23:39::SCWMssOS::Completed writemss as part of save.
-TRACE::2022-07-11.20:23:39::SCWMssOS::Commit changes completed.
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:39::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:39::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWWriter::formatted JSON is {
- "platformName": "phased_array_platform",
- "sprVersion": "2.0",
- "mode": "gui",
- "dsaType": "Fixed",
- "platformDesc": "phased_array_platform",
- "platHandOff": "/home/dylan/Documents/FPGA/phased_array/design_1_wrapper.xsa",
- "platIntHandOff": "/hw/design_1_wrapper.xsa",
- "deviceType": "zynq",
- "platIsPrebuiltAutogen": "false",
- "platIsNoBootBsp": "false",
- "platFsblTarget": "ps7_cortexa9_0",
- "hasFsblMakeHasChanges": "false",
- "hasPmufwMakeHasChanges": "false",
- "fsblExtraCompilerFlags": "-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ",
- "platPreBuiltFlag": false,
- "platformSamplesDir": "",
- "platActiveSys": "phased_array_platform",
- "systems": [{
- "systemName": "phased_array_platform",
- "systemDesc": "phased_array_platform",
- "sysIsBootAutoGen": "true",
- "systemDispName": "phased_array_platform",
- "sysActiveDom": "standalone_domain",
- "sysDefaultDom": "standalone_domain",
- "domains": [{
- "domainName": "zynq_fsbl",
- "domainDispName": "zynq_fsbl",
- "domainDesc": "FSBL Application BSP - Auto Generated.",
- "processors": "ps7_cortexa9_0",
- "os": "standalone",
- "sdxOs": "standalone",
- "debugEnable": "",
- "domRuntimes": ["cpp"],
- "swRepo": "",
- "mssOsVer": "7.6",
- "mssFile": "",
- "md5Digest": "3ad66e6342e47cdeb46ebdacd606f8ba",
- "compatibleApp": "zynq_fsbl",
- "domType": "bootDomain",
- "arch": "32-bit",
- "appSettings": {
- "appCompilerFlags": "",
- "appLinkerFlags": ""
- },
- "addedLibs": ["xilffs:4.6", "xilrsa:1.6"],
- "libOptions": {
- "libsContainingOptions": []
- },
- "prebuiltLibs": {
- "prebuiltIncPath": [],
- "prebuiltLibPath": []
- },
- "isolation": {
- }
- }, {
- "domainName": "standalone_domain",
- "domainDispName": "standalone on ps7_cortexa9_0",
- "domainDesc": "standalone_domain",
- "processors": "ps7_cortexa9_0",
- "os": "standalone",
- "sdxOs": "standalone",
- "qemuArgs": "/hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt",
- "qemuData": "/hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/",
- "debugEnable": "False",
- "domRuntimes": ["cpp"],
- "swRepo": "",
- "mssOsVer": "7.6",
- "mssFile": "",
- "md5Digest": "8f4cd5b2e4c0f3d4481583b0fc9b267f",
- "compatibleApp": "",
- "domType": "mssDomain",
- "appSettings": {
- "appCompilerFlags": "",
- "appLinkerFlags": ""
- },
- "addedLibs": [],
- "libOptions": {
- "libsContainingOptions": []
- },
- "prebuiltLibs": {
- "prebuiltIncPath": [],
- "prebuiltLibPath": []
- },
- "isolation": {
- }
- }]
- }]
-}
-TRACE::2022-07-11.20:23:39::SCWPlatform::Clearing the existing platform
-TRACE::2022-07-11.20:23:39::SCWSystem::Clearing the existing sysconfig
-TRACE::2022-07-11.20:23:39::SCWBDomain::clearing the fsbl build
-TRACE::2022-07-11.20:23:39::SCWMssOS::Removing the swdes entry for /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWMssOS::Removing the swdes entry for /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:39::SCWSystem::Clearing the domains completed.
-TRACE::2022-07-11.20:23:39::SCWPlatform::Clearing the opened hw db.
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform location is /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Removing the HwDB with name /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:39::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:39::SCWPlatform::Do not have an existing db opened.
-TRACE::2022-07-11.20:23:42::SCWPlatform::Opened new HwDB with name design_1_wrapper_1
-TRACE::2022-07-11.20:23:42::SCWReader::Active system found as phased_array_platform
-TRACE::2022-07-11.20:23:42::SCWReader::Handling sysconfig phased_array_platform
-TRACE::2022-07-11.20:23:42::SCWDomain::checking for install qemu data :
-TRACE::2022-07-11.20:23:42::SCWDomain:: Using the QEMU Data from install at : /hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/
-TRACE::2022-07-11.20:23:42::SCWDomain:: Using the QEMU args from install at : /hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt
-TRACE::2022-07-11.20:23:42::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:42::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:42::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_1
-TRACE::2022-07-11.20:23:42::SCWPlatform::Opened existing hwdb design_1_wrapper_1
-TRACE::2022-07-11.20:23:42::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:42::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:42::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:42::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_1
-TRACE::2022-07-11.20:23:42::SCWPlatform::Opened existing hwdb design_1_wrapper_1
-TRACE::2022-07-11.20:23:42::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:42::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:42::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:42::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_1
-TRACE::2022-07-11.20:23:42::SCWPlatform::Opened existing hwdb design_1_wrapper_1
-TRACE::2022-07-11.20:23:42::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:42::SCWReader::Boot application domain added for zynq_fsbl
-TRACE::2022-07-11.20:23:42::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:42::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:42::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_1
-TRACE::2022-07-11.20:23:42::SCWPlatform::Opened existing hwdb design_1_wrapper_1
-TRACE::2022-07-11.20:23:42::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:42::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:42::SCWMssOS::DEBUG: swdes dump
-TRACE::2022-07-11.20:23:42::SCWMssOS::No sw design opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:42::SCWMssOS::mss exists loading the mss file /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:42::SCWMssOS::Opened the sw design from mss /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:42::SCWMssOS::Adding the swdes entry /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss with des name system
-TRACE::2022-07-11.20:23:42::SCWMssOS::updating the scw layer about changes
-TRACE::2022-07-11.20:23:42::SCWMssOS::Opened the sw design. /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:42::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:42::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:42::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_1
-TRACE::2022-07-11.20:23:42::SCWPlatform::Opened existing hwdb design_1_wrapper_1
-TRACE::2022-07-11.20:23:42::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:42::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:42::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:42::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:42::SCWMssOS:: library already available in sw design: xilffs:4.6
-TRACE::2022-07-11.20:23:42::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:42::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:42::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_1
-TRACE::2022-07-11.20:23:42::SCWPlatform::Opened existing hwdb design_1_wrapper_1
-TRACE::2022-07-11.20:23:42::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:42::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:42::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:42::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:42::SCWMssOS:: library already available in sw design: xilrsa:1.6
-TRACE::2022-07-11.20:23:42::SCWMssOS::Saving the mss changes /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:42::SCWMssOS::Found a swdesign opened with the mssfile.
-TRACE::2022-07-11.20:23:42::SCWMssOS::Completed writemss as part of save.
-TRACE::2022-07-11.20:23:42::SCWMssOS::Commit changes completed.
-TRACE::2022-07-11.20:23:42::SCWReader::Adding prebuilt librarypaths as
-TRACE::2022-07-11.20:23:42::SCWReader::Adding prebuilt incpaths as
-TRACE::2022-07-11.20:23:42::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:42::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:42::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_1
-TRACE::2022-07-11.20:23:42::SCWPlatform::Opened existing hwdb design_1_wrapper_1
-TRACE::2022-07-11.20:23:42::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:42::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:42::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:42::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:42::SCWReader::No isolation master present
-TRACE::2022-07-11.20:23:42::SCWDomain::checking for install qemu data :
-TRACE::2022-07-11.20:23:42::SCWDomain:: Using the QEMU Data from install at : /hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/
-TRACE::2022-07-11.20:23:42::SCWDomain:: Using the QEMU args from install at : /hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt
-TRACE::2022-07-11.20:23:42::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:42::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:42::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_1
-TRACE::2022-07-11.20:23:42::SCWPlatform::Opened existing hwdb design_1_wrapper_1
-TRACE::2022-07-11.20:23:42::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:42::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:42::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:42::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_1
-TRACE::2022-07-11.20:23:42::SCWPlatform::Opened existing hwdb design_1_wrapper_1
-TRACE::2022-07-11.20:23:42::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:42::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:42::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:42::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_1
-TRACE::2022-07-11.20:23:42::SCWPlatform::Opened existing hwdb design_1_wrapper_1
-TRACE::2022-07-11.20:23:42::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:42::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:42::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:42::SCWMssOS::No sw design opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:42::SCWMssOS::mss exists loading the mss file /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:42::SCWMssOS::Opened the sw design from mss /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:42::SCWMssOS::Adding the swdes entry /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss with des name system_0
-TRACE::2022-07-11.20:23:42::SCWMssOS::updating the scw layer about changes
-TRACE::2022-07-11.20:23:42::SCWMssOS::Opened the sw design. /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:42::SCWMssOS::Saving the mss changes /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:42::SCWMssOS::Found a swdesign opened with the mssfile.
-TRACE::2022-07-11.20:23:42::SCWMssOS::Completed writemss as part of save.
-TRACE::2022-07-11.20:23:42::SCWMssOS::Commit changes completed.
-TRACE::2022-07-11.20:23:42::SCWReader::Adding prebuilt librarypaths as
-TRACE::2022-07-11.20:23:42::SCWReader::Adding prebuilt incpaths as
-TRACE::2022-07-11.20:23:42::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:42::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:42::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:42::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_1
-TRACE::2022-07-11.20:23:42::SCWPlatform::Opened existing hwdb design_1_wrapper_1
-TRACE::2022-07-11.20:23:42::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:42::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:42::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:42::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:23:42::SCWReader::No isolation master present
-LOG::2022-07-11.20:23:58::SCWPlatform::Started generating the artifacts platform phased_array_platform
-TRACE::2022-07-11.20:23:58::SCWPlatform::Sanity checking of platform is completed
-LOG::2022-07-11.20:23:58::SCWPlatform::Started generating the artifacts for system configuration phased_array_platform
-LOG::2022-07-11.20:23:58::SCWSystem::Checking the domain zynq_fsbl
-LOG::2022-07-11.20:23:58::SCWSystem::Doing application build for : zynq_fsbl
-TRACE::2022-07-11.20:23:58::SCWBDomain::Not a forced makefile updation, No changes are present.
-TRACE::2022-07-11.20:23:58::SCWDomain::Building the domain as part of full build : zynq_fsbl
-TRACE::2022-07-11.20:23:58::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:58::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:58::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:58::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:23:58::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:23:58::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:23:58::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_1
-TRACE::2022-07-11.20:23:58::SCWPlatform::Opened existing hwdb design_1_wrapper_1
-TRACE::2022-07-11.20:23:58::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:23:58::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:58::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:23:58::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:23:58::SCWBDomain::Completed writing the mss file at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp
-TRACE::2022-07-11.20:23:58::SCWBDomain::bsp generated is upto date with the mss file. Skipping bsp generation.
-TRACE::2022-07-11.20:23:58::SCWBDomain::Not a forced makefile updation, No changes are present.
-TRACE::2022-07-11.20:23:58::SCWBDomain::System Command Ran cd /home/dylan/workspace/phased_array_platform/zynq_fsbl ; bash -c " make -C zynq_fsbl_bsp ; make "
-TRACE::2022-07-11.20:23:58::SCWBDomain::make: Entering directory '/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp'
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make --no-print-directory seq_libs
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_9/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/gpiops_v3_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-11.20:23:58::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-11.20:23:58::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/sdps_v3_13/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/sdps_v3_13/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-11.20:23:58::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-11.20:23:58::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_4/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_4/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-11.20:23:58::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-11.20:23:58::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_7/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/devcfg_v3_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-11.20:23:58::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-11.20:23:58::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/scugic_v4_6/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scugic_v4_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-11.20:23:58::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-11.20:23:58::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/xilrsa_v1_6/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilrsa_v1_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-11.20:23:58::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-11.20:23:58::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/xilffs_v4_6/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilffs_v4_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-11.20:23:58::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-11.20:23:58::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_11/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/uartps_v3_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab
-TRACE::2022-07-11.20:23:58::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
-TRACE::2022-07-11.20:23:58::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/gpio_v4_8/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/gpio_v4_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a
-TRACE::2022-07-11.20:23:58::SCWBDomain::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no
-TRACE::2022-07-11.20:23:58::SCWBDomain::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/standalone_v7_6/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/standalone_v7_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-
-TRACE::2022-07-11.20:23:58::SCWBDomain::eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha
-TRACE::2022-07-11.20:23:58::SCWBDomain::rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_15/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/emacps_v3_15/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab
-TRACE::2022-07-11.20:23:58::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
-TRACE::2022-07-11.20:23:58::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/usbps_v2_7/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/usbps_v2_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-11.20:23:58::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-11.20:23:58::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-
-TRACE::2022-07-11.20:23:58::SCWBDomain::none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-a
-TRACE::2022-07-11.20:23:58::SCWBDomain::bi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_2/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-11.20:23:58::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-11.20:23:58::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_6/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xadcps_v2_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-11.20:23:58::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-11.20:23:58::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-no
-TRACE::2022-07-11.20:23:58::SCWBDomain::ne-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi
-TRACE::2022-07-11.20:23:58::SCWBDomain::=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_9/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/qspips_v3_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-11.20:23:58::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-11.20:23:58::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_8/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/dmaps_v2_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-11.20:23:58::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-11.20:23:58::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_3/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scutimer_v2_3/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-ea
-TRACE::2022-07-11.20:23:58::SCWBDomain::bi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
-TRACE::2022-07-11.20:23:58::SCWBDomain:: -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/xilrsa_v1_6/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilrsa_v1_6/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-11.20:23:58::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-11.20:23:58::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Finished building libraries sequentially.
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -j 6 --no-print-directory par_libs
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_9/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/sdps_v3_13/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_4/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/gpiops_v3_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-11.20:23:58::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-11.20:23:58::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/sdps_v3_13/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-11.20:23:58::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-11.20:23:58::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_7/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/xilrsa_v1_6/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/scugic_v4_6/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_4/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-11.20:23:58::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-11.20:23:58::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/devcfg_v3_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-11.20:23:58::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-11.20:23:58::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scugic_v4_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-11.20:23:58::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-11.20:23:58::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilrsa_v1_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-11.20:23:58::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-11.20:23:58::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/xilffs_v4_6/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_11/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilffs_v4_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-11.20:23:58::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-11.20:23:58::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/gpio_v4_8/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/standalone_v7_6/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/uartps_v3_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab
-TRACE::2022-07-11.20:23:58::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
-TRACE::2022-07-11.20:23:58::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/gpio_v4_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a
-TRACE::2022-07-11.20:23:58::SCWBDomain::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no
-TRACE::2022-07-11.20:23:58::SCWBDomain::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/standalone_v7_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-
-TRACE::2022-07-11.20:23:58::SCWBDomain::eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha
-TRACE::2022-07-11.20:23:58::SCWBDomain::rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_15/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/emacps_v3_15/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab
-TRACE::2022-07-11.20:23:58::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
-TRACE::2022-07-11.20:23:58::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/usbps_v2_7/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/usbps_v2_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-11.20:23:58::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-11.20:23:58::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-
-TRACE::2022-07-11.20:23:58::SCWBDomain::none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-a
-TRACE::2022-07-11.20:23:58::SCWBDomain::bi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_2/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_6/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-11.20:23:58::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-11.20:23:58::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xadcps_v2_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-11.20:23:58::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-11.20:23:58::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-no
-TRACE::2022-07-11.20:23:58::SCWBDomain::ne-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi
-TRACE::2022-07-11.20:23:58::SCWBDomain::=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_9/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/qspips_v3_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-11.20:23:58::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-11.20:23:58::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_8/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/dmaps_v2_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-11.20:23:58::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-11.20:23:58::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_3/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scutimer_v2_3/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-ea
-TRACE::2022-07-11.20:23:58::SCWBDomain::bi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
-TRACE::2022-07-11.20:23:58::SCWBDomain:: -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/gpiops_v3_9/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/sdps_v3_13/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/gpiops_v3_9/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-11.20:23:58::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-11.20:23:58::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/scuwdt_v2_4/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/sdps_v3_13/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
-TRACE::2022-07-11.20:23:58::SCWBDomain:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost
-TRACE::2022-07-11.20:23:58::SCWBDomain::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/devcfg_v3_7/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_4/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-11.20:23:58::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-11.20:23:58::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/scugic_v4_6/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/devcfg_v3_7/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-11.20:23:58::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-11.20:23:58::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/xilffs_v4_6/src
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scugic_v4_6/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-11.20:23:58::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-11.20:23:58::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:23:58::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilffs_v4_6/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-11.20:23:58::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-11.20:23:58::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:01::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/uartps_v3_11/src
-
-TRACE::2022-07-11.20:24:01::SCWBDomain::make -C ps7_cortexa9_0/libsrc/uartps_v3_11/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a
-TRACE::2022-07-11.20:24:01::SCWBDomain::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no
-TRACE::2022-07-11.20:24:01::SCWBDomain::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:02::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/gpio_v4_8/src
-
-TRACE::2022-07-11.20:24:02::SCWBDomain::make -C ps7_cortexa9_0/libsrc/gpio_v4_8/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
-TRACE::2022-07-11.20:24:02::SCWBDomain::"ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta
-TRACE::2022-07-11.20:24:02::SCWBDomain::rtfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:02::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/standalone_v7_6/src
-
-TRACE::2022-07-11.20:24:02::SCWBDomain::make -C ps7_cortexa9_0/libsrc/standalone_v7_6/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab
-TRACE::2022-07-11.20:24:02::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
-TRACE::2022-07-11.20:24:02::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:02::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/emacps_v3_15/src
-
-TRACE::2022-07-11.20:24:02::SCWBDomain::make -C ps7_cortexa9_0/libsrc/emacps_v3_15/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a
-TRACE::2022-07-11.20:24:02::SCWBDomain::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no
-TRACE::2022-07-11.20:24:02::SCWBDomain::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:02::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/usbps_v2_7/src
-
-TRACE::2022-07-11.20:24:02::SCWBDomain::make -C ps7_cortexa9_0/libsrc/usbps_v2_7/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
-TRACE::2022-07-11.20:24:02::SCWBDomain:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost
-TRACE::2022-07-11.20:24:02::SCWBDomain::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:03::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src
-
-TRACE::2022-07-11.20:24:03::SCWBDomain::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-non
-TRACE::2022-07-11.20:24:03::SCWBDomain::e-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=
-TRACE::2022-07-11.20:24:03::SCWBDomain::hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:03::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/ddrps_v1_2/src
-
-TRACE::2022-07-11.20:24:03::SCWBDomain::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
-TRACE::2022-07-11.20:24:03::SCWBDomain:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost
-TRACE::2022-07-11.20:24:03::SCWBDomain::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:03::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/xadcps_v2_6/src
-
-TRACE::2022-07-11.20:24:03::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xadcps_v2_6/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-11.20:24:03::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-11.20:24:03::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:03::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src
-
-TRACE::2022-07-11.20:24:03::SCWBDomain::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-
-TRACE::2022-07-11.20:24:03::SCWBDomain::eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha
-TRACE::2022-07-11.20:24:03::SCWBDomain::rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:03::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/qspips_v3_9/src
-
-TRACE::2022-07-11.20:24:03::SCWBDomain::make -C ps7_cortexa9_0/libsrc/qspips_v3_9/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-11.20:24:03::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-11.20:24:03::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:03::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/dmaps_v2_8/src
-
-TRACE::2022-07-11.20:24:03::SCWBDomain::make -C ps7_cortexa9_0/libsrc/dmaps_v2_8/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
-TRACE::2022-07-11.20:24:03::SCWBDomain:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost
-TRACE::2022-07-11.20:24:03::SCWBDomain::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:03::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/scutimer_v2_3/src
-
-TRACE::2022-07-11.20:24:03::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scutimer_v2_3/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-11.20:24:03::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-11.20:24:03::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:04::SCWBDomain::Finished building libraries parallelly.
-
-TRACE::2022-07-11.20:24:04::SCWBDomain::make --no-print-directory archive
-
-TRACE::2022-07-11.20:24:04::SCWBDomain::arm-none-eabi-ar -r ps7_cortexa9_0/lib/libxil.a ps7_cortexa9_0/lib/open.o ps7_cortexa9_0/lib/xemacps_control.o ps7_cortexa9_0/
-TRACE::2022-07-11.20:24:04::SCWBDomain::lib/xgpio.o ps7_cortexa9_0/lib/xil_exception.o ps7_cortexa9_0/lib/xqspips_selftest.o ps7_cortexa9_0/lib/xdevcfg_sinit.o ps7_cor
-TRACE::2022-07-11.20:24:04::SCWBDomain::texa9_0/lib/lseek.o ps7_cortexa9_0/lib/xsdps_sinit.o ps7_cortexa9_0/lib/xusbps_endpoint.o ps7_cortexa9_0/lib/xusbps.o ps7_corte
-TRACE::2022-07-11.20:24:04::SCWBDomain::xa9_0/lib/xqspips_g.o ps7_cortexa9_0/lib/xemacps_sinit.o ps7_cortexa9_0/lib/_sbrk.o ps7_cortexa9_0/lib/xpm_counter.o ps7_cortex
-TRACE::2022-07-11.20:24:04::SCWBDomain::a9_0/lib/xcoresightpsdcc.o ps7_cortexa9_0/lib/xscutimer.o ps7_cortexa9_0/lib/xemacps_hw.o ps7_cortexa9_0/lib/getpid.o ps7_corte
-TRACE::2022-07-11.20:24:04::SCWBDomain::xa9_0/lib/xscugic_intr.o ps7_cortexa9_0/lib/abort.o ps7_cortexa9_0/lib/usleep.o ps7_cortexa9_0/lib/asm_vectors.o ps7_cortexa9_0
-TRACE::2022-07-11.20:24:04::SCWBDomain::/lib/xl2cc_counter.o ps7_cortexa9_0/lib/xgpiops.o ps7_cortexa9_0/lib/xil_testmem.o ps7_cortexa9_0/lib/xgpiops_hw.o ps7_cortexa9
-TRACE::2022-07-11.20:24:04::SCWBDomain::_0/lib/outbyte.o ps7_cortexa9_0/lib/xuartps_selftest.o ps7_cortexa9_0/lib/xuartps_sinit.o ps7_cortexa9_0/lib/xadcps.o ps7_corte
-TRACE::2022-07-11.20:24:04::SCWBDomain::xa9_0/lib/xuartps_g.o ps7_cortexa9_0/lib/kill.o ps7_cortexa9_0/lib/xil_printf.o ps7_cortexa9_0/lib/time.o ps7_cortexa9_0/lib/xg
-TRACE::2022-07-11.20:24:04::SCWBDomain::pio_sinit.o ps7_cortexa9_0/lib/xil_clocking.o ps7_cortexa9_0/lib/xscuwdt.o ps7_cortexa9_0/lib/xgpio_g.o ps7_cortexa9_0/lib/xgpi
-TRACE::2022-07-11.20:24:04::SCWBDomain::ops_selftest.o ps7_cortexa9_0/lib/xgpiops_sinit.o ps7_cortexa9_0/lib/xemacps_g.o ps7_cortexa9_0/lib/close.o ps7_cortexa9_0/lib/
-TRACE::2022-07-11.20:24:04::SCWBDomain::xsdps.o ps7_cortexa9_0/lib/xusbps_g.o ps7_cortexa9_0/lib/xadcps_intr.o ps7_cortexa9_0/lib/xscutimer_selftest.o ps7_cortexa9_0/l
-TRACE::2022-07-11.20:24:04::SCWBDomain::ib/xdmaps_selftest.o ps7_cortexa9_0/lib/inbyte.o ps7_cortexa9_0/lib/xscutimer_sinit.o ps7_cortexa9_0/lib/xdmaps_sinit.o ps7_cor
-TRACE::2022-07-11.20:24:04::SCWBDomain::texa9_0/lib/xil_misc_psreset_api.o ps7_cortexa9_0/lib/xsdps_options.o ps7_cortexa9_0/lib/xscutimer_g.o ps7_cortexa9_0/lib/xdmap
-TRACE::2022-07-11.20:24:04::SCWBDomain::s_g.o ps7_cortexa9_0/lib/xqspips_options.o ps7_cortexa9_0/lib/xil_sleeptimer.o ps7_cortexa9_0/lib/xdevcfg_hw.o ps7_cortexa9_0/l
-TRACE::2022-07-11.20:24:04::SCWBDomain::ib/unlink.o ps7_cortexa9_0/lib/xusbps_sinit.o ps7_cortexa9_0/lib/sleep.o ps7_cortexa9_0/lib/xil_mem.o ps7_cortexa9_0/lib/xplatf
-TRACE::2022-07-11.20:24:04::SCWBDomain::orm_info.o ps7_cortexa9_0/lib/xadcps_selftest.o ps7_cortexa9_0/lib/xil_testcache.o ps7_cortexa9_0/lib/xgpio_selftest.o ps7_cort
-TRACE::2022-07-11.20:24:04::SCWBDomain::exa9_0/lib/xil_mmu.o ps7_cortexa9_0/lib/xadcps_sinit.o ps7_cortexa9_0/lib/xqspips_sinit.o ps7_cortexa9_0/lib/xgpiops_g.o ps7_co
-TRACE::2022-07-11.20:24:04::SCWBDomain::rtexa9_0/lib/xadcps_g.o ps7_cortexa9_0/lib/xscugic.o ps7_cortexa9_0/lib/xil-crt0.o ps7_cortexa9_0/lib/isatty.o ps7_cortexa9_0/l
-TRACE::2022-07-11.20:24:04::SCWBDomain::ib/xgpio_extra.o ps7_cortexa9_0/lib/xscuwdt_selftest.o ps7_cortexa9_0/lib/xemacps_intr.o ps7_cortexa9_0/lib/_exit.o ps7_cortexa
-TRACE::2022-07-11.20:24:04::SCWBDomain::9_0/lib/xscuwdt_g.o ps7_cortexa9_0/lib/vectors.o ps7_cortexa9_0/lib/xsdps_g.o ps7_cortexa9_0/lib/xuartps_options.o ps7_cortexa9
-TRACE::2022-07-11.20:24:04::SCWBDomain::_0/lib/xdevcfg_intr.o ps7_cortexa9_0/lib/errno.o ps7_cortexa9_0/lib/xqspips_hw.o ps7_cortexa9_0/lib/fstat.o ps7_cortexa9_0/lib/
-TRACE::2022-07-11.20:24:04::SCWBDomain::xusbps_hw.o ps7_cortexa9_0/lib/sbrk.o ps7_cortexa9_0/lib/xdmaps_hw.o ps7_cortexa9_0/lib/xsdps_card.o ps7_cortexa9_0/lib/xuartps
-TRACE::2022-07-11.20:24:04::SCWBDomain::_intr.o ps7_cortexa9_0/lib/xil_util.o ps7_cortexa9_0/lib/xscugic_selftest.o ps7_cortexa9_0/lib/xdmaps.o ps7_cortexa9_0/lib/xtim
-TRACE::2022-07-11.20:24:04::SCWBDomain::e_l.o ps7_cortexa9_0/lib/read.o ps7_cortexa9_0/lib/xgpio_intr.o ps7_cortexa9_0/lib/xscuwdt_sinit.o ps7_cortexa9_0/lib/putnum.o
-TRACE::2022-07-11.20:24:04::SCWBDomain::ps7_cortexa9_0/lib/xdevcfg_g.o ps7_cortexa9_0/lib/xscugic_sinit.o ps7_cortexa9_0/lib/xgpiops_intr.o ps7_cortexa9_0/lib/xscugic_
-TRACE::2022-07-11.20:24:04::SCWBDomain::g.o ps7_cortexa9_0/lib/xil_sleepcommon.o ps7_cortexa9_0/lib/cpu_init.o ps7_cortexa9_0/lib/xemacps_bdring.o ps7_cortexa9_0/lib/b
-TRACE::2022-07-11.20:24:04::SCWBDomain::oot.o ps7_cortexa9_0/lib/write.o ps7_cortexa9_0/lib/translation_table.o ps7_cortexa9_0/lib/xil_spinlock.o ps7_cortexa9_0/lib/xq
-TRACE::2022-07-11.20:24:04::SCWBDomain::spips.o ps7_cortexa9_0/lib/xil_testio.o ps7_cortexa9_0/lib/xil_cache.o ps7_cortexa9_0/lib/xemacps.o ps7_cortexa9_0/lib/xdevcfg_
-TRACE::2022-07-11.20:24:04::SCWBDomain::selftest.o ps7_cortexa9_0/lib/xdevcfg.o ps7_cortexa9_0/lib/xuartps_hw.o ps7_cortexa9_0/lib/print.o ps7_cortexa9_0/lib/fcntl.o p
-TRACE::2022-07-11.20:24:04::SCWBDomain::s7_cortexa9_0/lib/_open.o ps7_cortexa9_0/lib/cpputest_time.o ps7_cortexa9_0/lib/xuartps.o ps7_cortexa9_0/lib/xscugic_hw.o ps7_c
-TRACE::2022-07-11.20:24:04::SCWBDomain::ortexa9_0/lib/xsdps_host.o ps7_cortexa9_0/lib/xusbps_intr.o ps7_cortexa9_0/lib/xil_assert.o
-
-TRACE::2022-07-11.20:24:04::SCWBDomain::Finished building libraries
-
-TRACE::2022-07-11.20:24:04::SCWBDomain::make: Leaving directory '/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp'
-
-TRACE::2022-07-11.20:24:04::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c nand.c -o nand.o -Izynq_fsbl_bsp/ps7_
-TRACE::2022-07-11.20:24:04::SCWBDomain::cortexa9_0/include -I.
-
-TRACE::2022-07-11.20:24:04::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c pcap.c -o pcap.o -Izynq_fsbl_bsp/ps7_
-TRACE::2022-07-11.20:24:04::SCWBDomain::cortexa9_0/include -I.
-
-TRACE::2022-07-11.20:24:04::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c ps7_init.c -o ps7_init.o -Izynq_fsbl_
-TRACE::2022-07-11.20:24:04::SCWBDomain::bsp/ps7_cortexa9_0/include -I.
-
-TRACE::2022-07-11.20:24:04::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c qspi.c -o qspi.o -Izynq_fsbl_bsp/ps7_
-TRACE::2022-07-11.20:24:04::SCWBDomain::cortexa9_0/include -I.
-
-TRACE::2022-07-11.20:24:05::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c rsa.c -o rsa.o -Izynq_fsbl_bsp/ps7_co
-TRACE::2022-07-11.20:24:05::SCWBDomain::rtexa9_0/include -I.
-
-TRACE::2022-07-11.20:24:05::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c main.c -o main.o -Izynq_fsbl_bsp/ps7_
-TRACE::2022-07-11.20:24:05::SCWBDomain::cortexa9_0/include -I.
-
-TRACE::2022-07-11.20:24:05::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c md5.c -o md5.o -Izynq_fsbl_bsp/ps7_co
-TRACE::2022-07-11.20:24:05::SCWBDomain::rtexa9_0/include -I.
-
-TRACE::2022-07-11.20:24:05::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c image_mover.c -o image_mover.o -Izynq
-TRACE::2022-07-11.20:24:05::SCWBDomain::_fsbl_bsp/ps7_cortexa9_0/include -I.
-
-TRACE::2022-07-11.20:24:05::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c nor.c -o nor.o -Izynq_fsbl_bsp/ps7_co
-TRACE::2022-07-11.20:24:05::SCWBDomain::rtexa9_0/include -I.
-
-TRACE::2022-07-11.20:24:05::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c fsbl_hooks.c -o fsbl_hooks.o -Izynq_f
-TRACE::2022-07-11.20:24:05::SCWBDomain::sbl_bsp/ps7_cortexa9_0/include -I.
-
-TRACE::2022-07-11.20:24:05::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c sd.c -o sd.o -Izynq_fsbl_bsp/ps7_cort
-TRACE::2022-07-11.20:24:05::SCWBDomain::exa9_0/include -I.
-
-TRACE::2022-07-11.20:24:05::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c fsbl_handoff.S -o fsbl_handoff.o -Izy
-TRACE::2022-07-11.20:24:05::SCWBDomain::nq_fsbl_bsp/ps7_cortexa9_0/include -I.
-
-TRACE::2022-07-11.20:24:05::SCWBDomain::arm-none-eabi-gcc -o fsbl.elf fsbl_handoff.o fsbl_hooks.o image_mover.o main.o md5.o nand.o nor.o pcap.o ps7_init.o qspi.o rsa.
-TRACE::2022-07-11.20:24:05::SCWBDomain::o sd.o -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id
-TRACE::2022-07-11.20:24:05::SCWBDomain::=none -specs=Xilinx.spec -lrsa -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilffs,-lxil,-lgcc,-lc,--end-
-TRACE::2022-07-11.20:24:05::SCWBDomain::group -Wl,--start-group,-lrsa,-lxil,-lgcc,-lc,--end-group -Wl,--gc-sections -Lzyn
-TRACE::2022-07-11.20:24:05::SCWBDomain::q_fsbl_bsp/ps7_cortexa9_0/lib -L./ -Tlscript.ld
-
-LOG::2022-07-11.20:24:06::SCWSystem::Checking the domain standalone_domain
-LOG::2022-07-11.20:24:06::SCWSystem::Not a boot domain
-LOG::2022-07-11.20:24:06::SCWSystem::Started Processing the domain standalone_domain
-TRACE::2022-07-11.20:24:06::SCWDomain::Generating domain artifcats
-TRACE::2022-07-11.20:24:06::SCWMssOS::Generating standalone artifcats
-TRACE::2022-07-11.20:24:06::SCWMssOS::Copying the qemu file from /hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt To /home/dylan/workspace/phased_array_platform/export/phased_array_platform/sw/phased_array_platform/qemu/
-TRACE::2022-07-11.20:24:06::SCWMssOS::Copying the qemu file from /hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt To /home/dylan/workspace/phased_array_platform/export/phased_array_platform/sw/phased_array_platform/standalone_domain/qemu/
-TRACE::2022-07-11.20:24:06::SCWMssOS:: Copying the user libraries.
-TRACE::2022-07-11.20:24:06::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:24:06::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:24:06::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:24:06::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:24:06::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:24:06::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:24:06::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_1
-TRACE::2022-07-11.20:24:06::SCWPlatform::Opened existing hwdb design_1_wrapper_1
-TRACE::2022-07-11.20:24:06::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:24:06::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:24:06::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:24:06::SCWMssOS::Completed writing the mss file at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp
-TRACE::2022-07-11.20:24:06::SCWMssOS::Mss edits present, copying mssfile into export location /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:24:06::SCWMssOS::bsp generated is upto date with the mss file. Skipping bsp generation.
-TRACE::2022-07-11.20:24:06::SCWMssOS::BSP is already built. skipping the bsp build ...
-TRACE::2022-07-11.20:24:06::SCWDomain::Building the domain as part of full build : standalone_domain
-TRACE::2022-07-11.20:24:06::SCWMssOS::doing bsp build ...
-TRACE::2022-07-11.20:24:06::SCWMssOS::System Command Ran cd /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp ; bash -c "make "
-TRACE::2022-07-11.20:24:06::SCWMssOS::make --no-print-directory seq_libs
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Finished building libraries sequentially.
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::make -j 6 --no-print-directory par_libs
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_9/src
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/sdps_v3_13/src
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_4/src
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/gpiops_v3_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-11.20:24:06::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-11.20:24:06::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/sdps_v3_13/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-11.20:24:06::SCWMssOS::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-11.20:24:06::SCWMssOS::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_4/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-11.20:24:06::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-11.20:24:06::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_7/src
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/scugic_v4_6/src
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/devcfg_v3_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-11.20:24:06::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-11.20:24:06::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scugic_v4_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-11.20:24:06::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-11.20:24:06::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_15/src
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/emacps_v3_15/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab
-TRACE::2022-07-11.20:24:06::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
-TRACE::2022-07-11.20:24:06::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_11/src
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/gpio_v4_8/src
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/uartps_v3_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab
-TRACE::2022-07-11.20:24:06::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
-TRACE::2022-07-11.20:24:06::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/gpio_v4_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a
-TRACE::2022-07-11.20:24:06::SCWMssOS::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no
-TRACE::2022-07-11.20:24:06::SCWMssOS::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/usbps_v2_7/src
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/standalone_v7_6/src
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/usbps_v2_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-11.20:24:06::SCWMssOS::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-11.20:24:06::SCWMssOS::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/standalone_v7_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-
-TRACE::2022-07-11.20:24:06::SCWMssOS::eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha
-TRACE::2022-07-11.20:24:06::SCWMssOS::rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-
-TRACE::2022-07-11.20:24:06::SCWMssOS::none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-a
-TRACE::2022-07-11.20:24:06::SCWMssOS::bi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_2/src
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-11.20:24:06::SCWMssOS::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-11.20:24:06::SCWMssOS::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_6/src
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_9/src
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/xadcps_v2_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-11.20:24:06::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-11.20:24:06::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-no
-TRACE::2022-07-11.20:24:06::SCWMssOS::ne-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi
-TRACE::2022-07-11.20:24:06::SCWMssOS::=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/qspips_v3_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-11.20:24:06::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-11.20:24:06::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_8/src
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/dmaps_v2_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-11.20:24:06::SCWMssOS::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-11.20:24:06::SCWMssOS::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_3/src
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scutimer_v2_3/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-ea
-TRACE::2022-07-11.20:24:06::SCWMssOS::bi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
-TRACE::2022-07-11.20:24:06::SCWMssOS:: -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/gpiops_v3_9/src
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/gpiops_v3_9/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-11.20:24:06::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-11.20:24:06::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/sdps_v3_13/src
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/scuwdt_v2_4/src
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/sdps_v3_13/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
-TRACE::2022-07-11.20:24:06::SCWMssOS:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost
-TRACE::2022-07-11.20:24:06::SCWMssOS::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_4/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-11.20:24:06::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-11.20:24:06::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/devcfg_v3_7/src
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/devcfg_v3_7/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-11.20:24:06::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-11.20:24:06::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/scugic_v4_6/src
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scugic_v4_6/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-11.20:24:06::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-11.20:24:06::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/emacps_v3_15/src
-
-TRACE::2022-07-11.20:24:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/emacps_v3_15/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a
-TRACE::2022-07-11.20:24:06::SCWMssOS::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no
-TRACE::2022-07-11.20:24:06::SCWMssOS::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:07::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/uartps_v3_11/src
-
-TRACE::2022-07-11.20:24:07::SCWMssOS::make -C ps7_cortexa9_0/libsrc/uartps_v3_11/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a
-TRACE::2022-07-11.20:24:07::SCWMssOS::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no
-TRACE::2022-07-11.20:24:07::SCWMssOS::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:07::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/gpio_v4_8/src
-
-TRACE::2022-07-11.20:24:07::SCWMssOS::make -C ps7_cortexa9_0/libsrc/gpio_v4_8/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
-TRACE::2022-07-11.20:24:07::SCWMssOS::"ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta
-TRACE::2022-07-11.20:24:07::SCWMssOS::rtfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:07::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/standalone_v7_6/src
-
-TRACE::2022-07-11.20:24:07::SCWMssOS::make -C ps7_cortexa9_0/libsrc/standalone_v7_6/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab
-TRACE::2022-07-11.20:24:07::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
-TRACE::2022-07-11.20:24:07::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:07::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/usbps_v2_7/src
-
-TRACE::2022-07-11.20:24:07::SCWMssOS::make -C ps7_cortexa9_0/libsrc/usbps_v2_7/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
-TRACE::2022-07-11.20:24:07::SCWMssOS:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost
-TRACE::2022-07-11.20:24:07::SCWMssOS::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:08::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src
-
-TRACE::2022-07-11.20:24:08::SCWMssOS::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-non
-TRACE::2022-07-11.20:24:08::SCWMssOS::e-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=
-TRACE::2022-07-11.20:24:08::SCWMssOS::hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:08::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/ddrps_v1_2/src
-
-TRACE::2022-07-11.20:24:08::SCWMssOS::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
-TRACE::2022-07-11.20:24:08::SCWMssOS:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost
-TRACE::2022-07-11.20:24:08::SCWMssOS::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:08::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/xadcps_v2_6/src
-
-TRACE::2022-07-11.20:24:08::SCWMssOS::make -C ps7_cortexa9_0/libsrc/xadcps_v2_6/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-11.20:24:08::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-11.20:24:08::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:08::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src
-
-TRACE::2022-07-11.20:24:08::SCWMssOS::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-
-TRACE::2022-07-11.20:24:08::SCWMssOS::eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha
-TRACE::2022-07-11.20:24:08::SCWMssOS::rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:08::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/qspips_v3_9/src
-
-TRACE::2022-07-11.20:24:08::SCWMssOS::make -C ps7_cortexa9_0/libsrc/qspips_v3_9/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-11.20:24:08::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-11.20:24:08::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:08::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/dmaps_v2_8/src
-
-TRACE::2022-07-11.20:24:08::SCWMssOS::make -C ps7_cortexa9_0/libsrc/dmaps_v2_8/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
-TRACE::2022-07-11.20:24:08::SCWMssOS:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost
-TRACE::2022-07-11.20:24:08::SCWMssOS::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:08::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/scutimer_v2_3/src
-
-TRACE::2022-07-11.20:24:08::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scutimer_v2_3/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-11.20:24:08::SCWMssOS::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-11.20:24:08::SCWMssOS::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-11.20:24:09::SCWMssOS::Finished building libraries parallelly.
-
-TRACE::2022-07-11.20:24:09::SCWMssOS::make --no-print-directory archive
-
-TRACE::2022-07-11.20:24:09::SCWMssOS::arm-none-eabi-ar -r ps7_cortexa9_0/lib/libxil.a ps7_cortexa9_0/lib/open.o ps7_cortexa9_0/lib/xemacps_control.o ps7_cortexa9_0/
-TRACE::2022-07-11.20:24:09::SCWMssOS::lib/xgpio.o ps7_cortexa9_0/lib/xil_exception.o ps7_cortexa9_0/lib/xqspips_selftest.o ps7_cortexa9_0/lib/xdevcfg_sinit.o ps7_cor
-TRACE::2022-07-11.20:24:09::SCWMssOS::texa9_0/lib/lseek.o ps7_cortexa9_0/lib/xsdps_sinit.o ps7_cortexa9_0/lib/xusbps_endpoint.o ps7_cortexa9_0/lib/xusbps.o ps7_corte
-TRACE::2022-07-11.20:24:09::SCWMssOS::xa9_0/lib/xqspips_g.o ps7_cortexa9_0/lib/xemacps_sinit.o ps7_cortexa9_0/lib/_sbrk.o ps7_cortexa9_0/lib/xpm_counter.o ps7_cortex
-TRACE::2022-07-11.20:24:09::SCWMssOS::a9_0/lib/xcoresightpsdcc.o ps7_cortexa9_0/lib/xscutimer.o ps7_cortexa9_0/lib/xemacps_hw.o ps7_cortexa9_0/lib/getpid.o ps7_corte
-TRACE::2022-07-11.20:24:09::SCWMssOS::xa9_0/lib/xscugic_intr.o ps7_cortexa9_0/lib/abort.o ps7_cortexa9_0/lib/usleep.o ps7_cortexa9_0/lib/asm_vectors.o ps7_cortexa9_0
-TRACE::2022-07-11.20:24:09::SCWMssOS::/lib/xl2cc_counter.o ps7_cortexa9_0/lib/xgpiops.o ps7_cortexa9_0/lib/xil_testmem.o ps7_cortexa9_0/lib/xgpiops_hw.o ps7_cortexa9
-TRACE::2022-07-11.20:24:09::SCWMssOS::_0/lib/xuartps_selftest.o ps7_cortexa9_0/lib/xuartps_sinit.o ps7_cortexa9_0/lib/xadcps.o ps7_cortexa9_0/lib/xuartps_g.o ps7_cor
-TRACE::2022-07-11.20:24:09::SCWMssOS::texa9_0/lib/kill.o ps7_cortexa9_0/lib/xil_printf.o ps7_cortexa9_0/lib/time.o ps7_cortexa9_0/lib/xgpio_sinit.o ps7_cortexa9_0/li
-TRACE::2022-07-11.20:24:09::SCWMssOS::b/xil_clocking.o ps7_cortexa9_0/lib/xscuwdt.o ps7_cortexa9_0/lib/xgpio_g.o ps7_cortexa9_0/lib/xgpiops_selftest.o ps7_cortexa9_0
-TRACE::2022-07-11.20:24:09::SCWMssOS::/lib/xgpiops_sinit.o ps7_cortexa9_0/lib/xemacps_g.o ps7_cortexa9_0/lib/close.o ps7_cortexa9_0/lib/xsdps.o ps7_cortexa9_0/lib/xu
-TRACE::2022-07-11.20:24:09::SCWMssOS::sbps_g.o ps7_cortexa9_0/lib/xadcps_intr.o ps7_cortexa9_0/lib/putnum.o ps7_cortexa9_0/lib/xscutimer_selftest.o ps7_cortexa9_0/li
-TRACE::2022-07-11.20:24:09::SCWMssOS::b/xdmaps_selftest.o ps7_cortexa9_0/lib/inbyte.o ps7_cortexa9_0/lib/xscutimer_sinit.o ps7_cortexa9_0/lib/xdmaps_sinit.o ps7_cort
-TRACE::2022-07-11.20:24:09::SCWMssOS::exa9_0/lib/xil_misc_psreset_api.o ps7_cortexa9_0/lib/xsdps_options.o ps7_cortexa9_0/lib/xscutimer_g.o ps7_cortexa9_0/lib/xdmaps
-TRACE::2022-07-11.20:24:09::SCWMssOS::_g.o ps7_cortexa9_0/lib/xqspips_options.o ps7_cortexa9_0/lib/xil_sleeptimer.o ps7_cortexa9_0/lib/xdevcfg_hw.o ps7_cortexa9_0/li
-TRACE::2022-07-11.20:24:09::SCWMssOS::b/unlink.o ps7_cortexa9_0/lib/xusbps_sinit.o ps7_cortexa9_0/lib/sleep.o ps7_cortexa9_0/lib/xil_mem.o ps7_cortexa9_0/lib/xplatfo
-TRACE::2022-07-11.20:24:09::SCWMssOS::rm_info.o ps7_cortexa9_0/lib/xadcps_selftest.o ps7_cortexa9_0/lib/xil_testcache.o ps7_cortexa9_0/lib/xgpio_selftest.o ps7_corte
-TRACE::2022-07-11.20:24:09::SCWMssOS::xa9_0/lib/xil_mmu.o ps7_cortexa9_0/lib/xadcps_sinit.o ps7_cortexa9_0/lib/xqspips_sinit.o ps7_cortexa9_0/lib/xgpiops_g.o ps7_cor
-TRACE::2022-07-11.20:24:09::SCWMssOS::texa9_0/lib/xadcps_g.o ps7_cortexa9_0/lib/xscugic.o ps7_cortexa9_0/lib/xil-crt0.o ps7_cortexa9_0/lib/isatty.o ps7_cortexa9_0/li
-TRACE::2022-07-11.20:24:09::SCWMssOS::b/xgpio_extra.o ps7_cortexa9_0/lib/xscuwdt_selftest.o ps7_cortexa9_0/lib/xemacps_intr.o ps7_cortexa9_0/lib/_exit.o ps7_cortexa9
-TRACE::2022-07-11.20:24:09::SCWMssOS::_0/lib/xscuwdt_g.o ps7_cortexa9_0/lib/vectors.o ps7_cortexa9_0/lib/xsdps_g.o ps7_cortexa9_0/lib/xuartps_options.o ps7_cortexa9_
-TRACE::2022-07-11.20:24:09::SCWMssOS::0/lib/xdevcfg_intr.o ps7_cortexa9_0/lib/errno.o ps7_cortexa9_0/lib/xqspips_hw.o ps7_cortexa9_0/lib/fstat.o ps7_cortexa9_0/lib/x
-TRACE::2022-07-11.20:24:09::SCWMssOS::usbps_hw.o ps7_cortexa9_0/lib/sbrk.o ps7_cortexa9_0/lib/xdmaps_hw.o ps7_cortexa9_0/lib/xsdps_card.o ps7_cortexa9_0/lib/xuartps_
-TRACE::2022-07-11.20:24:09::SCWMssOS::intr.o ps7_cortexa9_0/lib/xil_util.o ps7_cortexa9_0/lib/xscugic_selftest.o ps7_cortexa9_0/lib/xdmaps.o ps7_cortexa9_0/lib/xtime
-TRACE::2022-07-11.20:24:09::SCWMssOS::_l.o ps7_cortexa9_0/lib/read.o ps7_cortexa9_0/lib/xgpio_intr.o ps7_cortexa9_0/lib/xscuwdt_sinit.o ps7_cortexa9_0/lib/outbyte.o
-TRACE::2022-07-11.20:24:09::SCWMssOS::ps7_cortexa9_0/lib/xdevcfg_g.o ps7_cortexa9_0/lib/xscugic_sinit.o ps7_cortexa9_0/lib/xgpiops_intr.o ps7_cortexa9_0/lib/xscugic_
-TRACE::2022-07-11.20:24:09::SCWMssOS::g.o ps7_cortexa9_0/lib/xil_sleepcommon.o ps7_cortexa9_0/lib/cpu_init.o ps7_cortexa9_0/lib/xemacps_bdring.o ps7_cortexa9_0/lib/b
-TRACE::2022-07-11.20:24:09::SCWMssOS::oot.o ps7_cortexa9_0/lib/write.o ps7_cortexa9_0/lib/translation_table.o ps7_cortexa9_0/lib/xil_spinlock.o ps7_cortexa9_0/lib/xq
-TRACE::2022-07-11.20:24:09::SCWMssOS::spips.o ps7_cortexa9_0/lib/xil_testio.o ps7_cortexa9_0/lib/xil_cache.o ps7_cortexa9_0/lib/xemacps.o ps7_cortexa9_0/lib/xdevcfg_
-TRACE::2022-07-11.20:24:09::SCWMssOS::selftest.o ps7_cortexa9_0/lib/xdevcfg.o ps7_cortexa9_0/lib/xuartps_hw.o ps7_cortexa9_0/lib/print.o ps7_cortexa9_0/lib/fcntl.o p
-TRACE::2022-07-11.20:24:09::SCWMssOS::s7_cortexa9_0/lib/_open.o ps7_cortexa9_0/lib/cpputest_time.o ps7_cortexa9_0/lib/xuartps.o ps7_cortexa9_0/lib/xscugic_hw.o ps7_c
-TRACE::2022-07-11.20:24:09::SCWMssOS::ortexa9_0/lib/xsdps_host.o ps7_cortexa9_0/lib/xusbps_intr.o ps7_cortexa9_0/lib/xil_assert.o
-
-TRACE::2022-07-11.20:24:09::SCWMssOS::Finished building libraries
-
-TRACE::2022-07-11.20:24:09::SCWMssOS::Copying to export directory.
-TRACE::2022-07-11.20:24:09::SCWMssOS:: Checking if to create the Supporting Applications
-TRACE::2022-07-11.20:24:09::SCWMssOS:: No Linux domain exists, trying to generate FSBL
-LOG::2022-07-11.20:24:09::SCWSystem::Completed Processing the domain standalone_domain
-LOG::2022-07-11.20:24:09::SCWSystem::Completed Processing the sysconfig phased_array_platform
-LOG::2022-07-11.20:24:09::SCWPlatform::Completed generating the artifacts for system configuration phased_array_platform
-TRACE::2022-07-11.20:24:09::SCWPlatform::Started preparing the platform
-TRACE::2022-07-11.20:24:09::SCWSystem::Writing the bif file for system config phased_array_platform
-TRACE::2022-07-11.20:24:09::SCWSystem::dir created
-TRACE::2022-07-11.20:24:09::SCWSystem::Writing the bif
-TRACE::2022-07-11.20:24:09::SCWPlatform::Started writing the spfm file
-TRACE::2022-07-11.20:24:09::SCWPlatform::Started writing the xpfm file
-TRACE::2022-07-11.20:24:09::SCWPlatform::Completed generating the platform
-TRACE::2022-07-11.20:24:09::SCWMssOS::Saving the mss changes /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:24:09::SCWMssOS::Found a swdesign opened with the mssfile.
-TRACE::2022-07-11.20:24:09::SCWMssOS::Completed writemss as part of save.
-TRACE::2022-07-11.20:24:09::SCWMssOS::Commit changes completed.
-TRACE::2022-07-11.20:24:09::SCWMssOS::Saving the mss changes /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:24:09::SCWMssOS::Found a swdesign opened with the mssfile.
-TRACE::2022-07-11.20:24:09::SCWMssOS::Completed writemss as part of save.
-TRACE::2022-07-11.20:24:09::SCWMssOS::Commit changes completed.
-TRACE::2022-07-11.20:24:09::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:24:09::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:24:09::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:24:09::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:24:09::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:24:09::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:24:09::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_1
-TRACE::2022-07-11.20:24:09::SCWPlatform::Opened existing hwdb design_1_wrapper_1
-TRACE::2022-07-11.20:24:09::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:24:09::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:24:09::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:24:09::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-11.20:24:09::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:24:09::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:24:09::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:24:09::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:24:09::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:24:09::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:24:09::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_1
-TRACE::2022-07-11.20:24:09::SCWPlatform::Opened existing hwdb design_1_wrapper_1
-TRACE::2022-07-11.20:24:09::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:24:09::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:24:09::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:24:09::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:24:09::SCWWriter::formatted JSON is {
- "platformName": "phased_array_platform",
- "sprVersion": "2.0",
- "mode": "gui",
- "dsaType": "Fixed",
- "platformDesc": "phased_array_platform",
- "platHandOff": "/home/dylan/Documents/FPGA/phased_array/design_1_wrapper.xsa",
- "platIntHandOff": "/hw/design_1_wrapper.xsa",
- "deviceType": "zynq",
- "platIsPrebuiltAutogen": "false",
- "platIsNoBootBsp": "false",
- "hasFsblMakeHasChanges": "false",
- "hasPmufwMakeHasChanges": "false",
- "fsblExtraCompilerFlags": "-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ",
- "platPreBuiltFlag": false,
- "platformSamplesDir": "",
- "platActiveSys": "phased_array_platform",
- "systems": [{
- "systemName": "phased_array_platform",
- "systemDesc": "phased_array_platform",
- "sysIsBootAutoGen": "true",
- "systemDispName": "phased_array_platform",
- "sysActiveDom": "standalone_domain",
- "sysDefaultDom": "standalone_domain",
- "domains": [{
- "domainName": "zynq_fsbl",
- "domainDispName": "zynq_fsbl",
- "domainDesc": "FSBL Application BSP - Auto Generated.",
- "processors": "ps7_cortexa9_0",
- "os": "standalone",
- "sdxOs": "standalone",
- "debugEnable": "",
- "domRuntimes": ["cpp"],
- "swRepo": "",
- "mssOsVer": "7.6",
- "mssFile": "",
- "md5Digest": "3ad66e6342e47cdeb46ebdacd606f8ba",
- "compatibleApp": "zynq_fsbl",
- "domType": "bootDomain",
- "arch": "32-bit",
- "appSettings": {
- "appCompilerFlags": "",
- "appLinkerFlags": ""
- },
- "addedLibs": ["xilffs:4.6", "xilrsa:1.6"],
- "libOptions": {
- "libsContainingOptions": []
- },
- "prebuiltLibs": {
- "prebuiltIncPath": [],
- "prebuiltLibPath": []
- },
- "isolation": {
- }
- }, {
- "domainName": "standalone_domain",
- "domainDispName": "standalone on ps7_cortexa9_0",
- "domainDesc": "standalone_domain",
- "processors": "ps7_cortexa9_0",
- "os": "standalone",
- "sdxOs": "standalone",
- "qemuArgs": "/hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt",
- "qemuData": "/hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/",
- "debugEnable": "False",
- "domRuntimes": ["cpp"],
- "swRepo": "",
- "mssOsVer": "7.6",
- "mssFile": "",
- "md5Digest": "8f4cd5b2e4c0f3d4481583b0fc9b267f",
- "compatibleApp": "",
- "domType": "mssDomain",
- "appSettings": {
- "appCompilerFlags": "",
- "appLinkerFlags": ""
- },
- "addedLibs": [],
- "libOptions": {
- "libsContainingOptions": []
- },
- "prebuiltLibs": {
- "prebuiltIncPath": [],
- "prebuiltLibPath": []
- },
- "isolation": {
- }
- }]
- }]
-}
-KEYINFO::2022-07-11.20:24:09::SCWPlatform::updated the xpfm file.
-TRACE::2022-07-11.20:24:09::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:24:09::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:24:09::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:24:09::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-11.20:24:09::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-11.20:24:09::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-11.20:24:09::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_1
-TRACE::2022-07-11.20:24:09::SCWPlatform::Opened existing hwdb design_1_wrapper_1
-TRACE::2022-07-11.20:24:09::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-11.20:24:09::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-11.20:24:09::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-11.20:24:09::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-31.18:23:57::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:57::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:57::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:57::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-31.18:23:57::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:57::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-31.18:23:57::SCWPlatform::Do not have an existing db opened.
-TRACE::2022-07-31.18:23:59::SCWPlatform::Opened new HwDB with name design_1_wrapper_0
-TRACE::2022-07-31.18:23:59::SCWReader::Active system found as phased_array_platform
-TRACE::2022-07-31.18:23:59::SCWReader::Handling sysconfig phased_array_platform
-TRACE::2022-07-31.18:23:59::SCWDomain::checking for install qemu data :
-TRACE::2022-07-31.18:23:59::SCWDomain:: Using the QEMU Data from install at : /hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/
-TRACE::2022-07-31.18:23:59::SCWDomain:: Using the QEMU args from install at : /hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt
-TRACE::2022-07-31.18:23:59::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-31.18:23:59::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-31.18:23:59::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-31.18:23:59::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-31.18:23:59::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-31.18:23:59::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-31.18:23:59::SCWReader::Boot application domain added for zynq_fsbl
-TRACE::2022-07-31.18:23:59::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-31.18:23:59::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-31.18:23:59::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-31.18:23:59::SCWMssOS::DEBUG: swdes dump
-TRACE::2022-07-31.18:23:59::SCWMssOS::No sw design opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-31.18:23:59::SCWMssOS::mss exists loading the mss file /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-31.18:23:59::SCWMssOS::Opened the sw design from mss /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-31.18:23:59::SCWMssOS::Adding the swdes entry /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss with des name system
-TRACE::2022-07-31.18:23:59::SCWMssOS::updating the scw layer about changes
-TRACE::2022-07-31.18:23:59::SCWMssOS::Opened the sw design. /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-31.18:23:59::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-31.18:23:59::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-31.18:23:59::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-31.18:23:59::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-31.18:23:59::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-31.18:23:59::SCWMssOS:: library already available in sw design: xilffs:4.6
-TRACE::2022-07-31.18:23:59::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-31.18:23:59::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-31.18:23:59::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-31.18:23:59::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-31.18:23:59::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-31.18:23:59::SCWMssOS:: library already available in sw design: xilrsa:1.6
-TRACE::2022-07-31.18:23:59::SCWMssOS::Saving the mss changes /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-31.18:23:59::SCWMssOS::Found a swdesign opened with the mssfile.
-TRACE::2022-07-31.18:23:59::SCWMssOS::Completed writemss as part of save.
-TRACE::2022-07-31.18:23:59::SCWMssOS::Commit changes completed.
-TRACE::2022-07-31.18:23:59::SCWReader::Adding prebuilt librarypaths as
-TRACE::2022-07-31.18:23:59::SCWReader::Adding prebuilt incpaths as
-TRACE::2022-07-31.18:23:59::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-31.18:23:59::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-31.18:23:59::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-31.18:23:59::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-31.18:23:59::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-31.18:23:59::SCWReader::No isolation master present
-TRACE::2022-07-31.18:23:59::SCWDomain::checking for install qemu data :
-TRACE::2022-07-31.18:23:59::SCWDomain:: Using the QEMU Data from install at : /hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/
-TRACE::2022-07-31.18:23:59::SCWDomain:: Using the QEMU args from install at : /hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt
-TRACE::2022-07-31.18:23:59::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-31.18:23:59::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-31.18:23:59::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-31.18:23:59::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-31.18:23:59::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-31.18:23:59::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:23:59::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-31.18:23:59::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-31.18:23:59::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-31.18:23:59::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-31.18:23:59::SCWMssOS::No sw design opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-31.18:23:59::SCWMssOS::mss exists loading the mss file /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-31.18:23:59::SCWMssOS::Opened the sw design from mss /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-31.18:23:59::SCWMssOS::Adding the swdes entry /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss with des name system_0
-TRACE::2022-07-31.18:23:59::SCWMssOS::updating the scw layer about changes
-TRACE::2022-07-31.18:24:00::SCWMssOS::Opened the sw design. /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-31.18:24:00::SCWMssOS::Saving the mss changes /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-31.18:24:00::SCWMssOS::Found a swdesign opened with the mssfile.
-TRACE::2022-07-31.18:24:00::SCWMssOS::Completed writemss as part of save.
-TRACE::2022-07-31.18:24:00::SCWMssOS::Commit changes completed.
-TRACE::2022-07-31.18:24:00::SCWReader::Adding prebuilt librarypaths as
-TRACE::2022-07-31.18:24:00::SCWReader::Adding prebuilt incpaths as
-TRACE::2022-07-31.18:24:00::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:24:00::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:24:00::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:24:00::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-31.18:24:00::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:24:00::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-31.18:24:00::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-31.18:24:00::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-31.18:24:00::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-31.18:24:00::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-31.18:24:00::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-31.18:24:00::SCWReader::No isolation master present
-LOG::2022-07-31.18:24:00::SCWPlatform::Started generating the artifacts platform phased_array_platform
-TRACE::2022-07-31.18:24:00::SCWPlatform::Sanity checking of platform is completed
-LOG::2022-07-31.18:24:00::SCWPlatform::Started generating the artifacts for system configuration phased_array_platform
-LOG::2022-07-31.18:24:00::SCWSystem::Checking the domain zynq_fsbl
-LOG::2022-07-31.18:24:00::SCWSystem::Doing application build for : zynq_fsbl
-TRACE::2022-07-31.18:24:00::SCWBDomain::Not a forced makefile updation, No changes are present.
-TRACE::2022-07-31.18:24:00::SCWDomain::Building the domain as part of full build : zynq_fsbl
-TRACE::2022-07-31.18:24:00::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:24:00::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:24:00::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:24:00::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-31.18:24:00::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:24:00::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-31.18:24:00::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-31.18:24:00::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-31.18:24:00::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-31.18:24:00::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-31.18:24:00::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-31.18:24:00::SCWBDomain::Completed writing the mss file at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp
-TRACE::2022-07-31.18:24:00::SCWBDomain::bsp generated is upto date with the mss file. Skipping bsp generation.
-TRACE::2022-07-31.18:24:00::SCWBDomain::Not a forced makefile updation, No changes are present.
-TRACE::2022-07-31.18:24:00::SCWBDomain::System Command Ran cd /home/dylan/workspace/phased_array_platform/zynq_fsbl ; bash -c " make -C zynq_fsbl_bsp ; make "
-TRACE::2022-07-31.18:24:00::SCWBDomain::make: Entering directory '/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp'
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make --no-print-directory seq_libs
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_9/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/gpiops_v3_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-31.18:24:00::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-31.18:24:00::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/sdps_v3_13/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/sdps_v3_13/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-31.18:24:00::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-31.18:24:00::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_4/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_4/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-31.18:24:00::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-31.18:24:00::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_7/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/devcfg_v3_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-31.18:24:00::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-31.18:24:00::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/scugic_v4_6/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scugic_v4_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-31.18:24:00::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-31.18:24:00::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/xilrsa_v1_6/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilrsa_v1_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-31.18:24:00::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-31.18:24:00::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/xilffs_v4_6/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilffs_v4_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-31.18:24:00::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-31.18:24:00::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_11/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/uartps_v3_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab
-TRACE::2022-07-31.18:24:00::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
-TRACE::2022-07-31.18:24:00::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/gpio_v4_8/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/gpio_v4_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a
-TRACE::2022-07-31.18:24:00::SCWBDomain::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no
-TRACE::2022-07-31.18:24:00::SCWBDomain::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/standalone_v7_6/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/standalone_v7_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-
-TRACE::2022-07-31.18:24:00::SCWBDomain::eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha
-TRACE::2022-07-31.18:24:00::SCWBDomain::rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_15/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/emacps_v3_15/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab
-TRACE::2022-07-31.18:24:00::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
-TRACE::2022-07-31.18:24:00::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/usbps_v2_7/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/usbps_v2_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-31.18:24:00::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-31.18:24:00::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-
-TRACE::2022-07-31.18:24:00::SCWBDomain::none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-a
-TRACE::2022-07-31.18:24:00::SCWBDomain::bi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_2/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-31.18:24:00::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-31.18:24:00::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_6/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xadcps_v2_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-31.18:24:00::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-31.18:24:00::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-no
-TRACE::2022-07-31.18:24:00::SCWBDomain::ne-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi
-TRACE::2022-07-31.18:24:00::SCWBDomain::=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_9/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/qspips_v3_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-31.18:24:00::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-31.18:24:00::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_8/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/dmaps_v2_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-31.18:24:00::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-31.18:24:00::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_3/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scutimer_v2_3/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-ea
-TRACE::2022-07-31.18:24:00::SCWBDomain::bi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
-TRACE::2022-07-31.18:24:00::SCWBDomain:: -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/xilrsa_v1_6/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilrsa_v1_6/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-31.18:24:00::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-31.18:24:00::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Finished building libraries sequentially.
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -j 6 --no-print-directory par_libs
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_9/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/sdps_v3_13/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/gpiops_v3_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-31.18:24:00::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-31.18:24:00::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_4/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_7/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/scugic_v4_6/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/sdps_v3_13/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-31.18:24:00::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-31.18:24:00::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/xilrsa_v1_6/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_4/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-31.18:24:00::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-31.18:24:00::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/devcfg_v3_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-31.18:24:00::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-31.18:24:00::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scugic_v4_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-31.18:24:00::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-31.18:24:00::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilrsa_v1_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-31.18:24:00::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-31.18:24:00::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_11/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/xilffs_v4_6/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilffs_v4_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-31.18:24:00::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-31.18:24:00::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/gpio_v4_8/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/uartps_v3_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab
-TRACE::2022-07-31.18:24:00::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
-TRACE::2022-07-31.18:24:00::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/gpio_v4_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a
-TRACE::2022-07-31.18:24:00::SCWBDomain::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no
-TRACE::2022-07-31.18:24:00::SCWBDomain::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/standalone_v7_6/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/standalone_v7_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-
-TRACE::2022-07-31.18:24:00::SCWBDomain::eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha
-TRACE::2022-07-31.18:24:00::SCWBDomain::rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_15/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/emacps_v3_15/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab
-TRACE::2022-07-31.18:24:00::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
-TRACE::2022-07-31.18:24:00::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/usbps_v2_7/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/usbps_v2_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-31.18:24:00::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-31.18:24:00::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-
-TRACE::2022-07-31.18:24:00::SCWBDomain::none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-a
-TRACE::2022-07-31.18:24:00::SCWBDomain::bi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_2/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-31.18:24:00::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-31.18:24:00::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_6/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xadcps_v2_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-31.18:24:00::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-31.18:24:00::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-no
-TRACE::2022-07-31.18:24:00::SCWBDomain::ne-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi
-TRACE::2022-07-31.18:24:00::SCWBDomain::=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_9/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/qspips_v3_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-31.18:24:00::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-31.18:24:00::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_8/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/dmaps_v2_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-31.18:24:00::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-31.18:24:00::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_3/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scutimer_v2_3/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-ea
-TRACE::2022-07-31.18:24:00::SCWBDomain::bi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
-TRACE::2022-07-31.18:24:00::SCWBDomain:: -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/gpiops_v3_9/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/sdps_v3_13/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/scuwdt_v2_4/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/gpiops_v3_9/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-31.18:24:00::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-31.18:24:00::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/sdps_v3_13/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
-TRACE::2022-07-31.18:24:00::SCWBDomain:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost
-TRACE::2022-07-31.18:24:00::SCWBDomain::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_4/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-31.18:24:00::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-31.18:24:00::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/scugic_v4_6/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/devcfg_v3_7/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scugic_v4_6/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-31.18:24:00::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-31.18:24:00::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/devcfg_v3_7/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-31.18:24:00::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-31.18:24:00::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/xilffs_v4_6/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilffs_v4_6/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-31.18:24:00::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-31.18:24:00::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/uartps_v3_11/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/uartps_v3_11/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a
-TRACE::2022-07-31.18:24:00::SCWBDomain::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no
-TRACE::2022-07-31.18:24:00::SCWBDomain::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/gpio_v4_8/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/gpio_v4_8/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
-TRACE::2022-07-31.18:24:00::SCWBDomain::"ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta
-TRACE::2022-07-31.18:24:00::SCWBDomain::rtfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/standalone_v7_6/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/standalone_v7_6/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab
-TRACE::2022-07-31.18:24:00::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
-TRACE::2022-07-31.18:24:00::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/emacps_v3_15/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/emacps_v3_15/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a
-TRACE::2022-07-31.18:24:00::SCWBDomain::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no
-TRACE::2022-07-31.18:24:00::SCWBDomain::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/usbps_v2_7/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/usbps_v2_7/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
-TRACE::2022-07-31.18:24:00::SCWBDomain:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost
-TRACE::2022-07-31.18:24:00::SCWBDomain::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-non
-TRACE::2022-07-31.18:24:00::SCWBDomain::e-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=
-TRACE::2022-07-31.18:24:00::SCWBDomain::hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/ddrps_v1_2/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
-TRACE::2022-07-31.18:24:00::SCWBDomain:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost
-TRACE::2022-07-31.18:24:00::SCWBDomain::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/xadcps_v2_6/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xadcps_v2_6/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-31.18:24:00::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-31.18:24:00::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-
-TRACE::2022-07-31.18:24:00::SCWBDomain::eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha
-TRACE::2022-07-31.18:24:00::SCWBDomain::rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/qspips_v3_9/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/qspips_v3_9/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-31.18:24:00::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-31.18:24:00::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/dmaps_v2_8/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/dmaps_v2_8/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
-TRACE::2022-07-31.18:24:00::SCWBDomain:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost
-TRACE::2022-07-31.18:24:00::SCWBDomain::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/scutimer_v2_3/src
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scutimer_v2_3/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-31.18:24:00::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-31.18:24:00::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Finished building libraries parallelly.
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make --no-print-directory archive
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::arm-none-eabi-ar -r ps7_cortexa9_0/lib/libxil.a ps7_cortexa9_0/lib/open.o ps7_cortexa9_0/lib/xemacps_control.o ps7_cortexa9_0/
-TRACE::2022-07-31.18:24:00::SCWBDomain::lib/xgpio.o ps7_cortexa9_0/lib/xil_exception.o ps7_cortexa9_0/lib/xqspips_selftest.o ps7_cortexa9_0/lib/xdevcfg_sinit.o ps7_cor
-TRACE::2022-07-31.18:24:00::SCWBDomain::texa9_0/lib/lseek.o ps7_cortexa9_0/lib/xsdps_sinit.o ps7_cortexa9_0/lib/xusbps_endpoint.o ps7_cortexa9_0/lib/xusbps.o ps7_corte
-TRACE::2022-07-31.18:24:00::SCWBDomain::xa9_0/lib/xqspips_g.o ps7_cortexa9_0/lib/xemacps_sinit.o ps7_cortexa9_0/lib/_sbrk.o ps7_cortexa9_0/lib/xpm_counter.o ps7_cortex
-TRACE::2022-07-31.18:24:00::SCWBDomain::a9_0/lib/xcoresightpsdcc.o ps7_cortexa9_0/lib/xscutimer.o ps7_cortexa9_0/lib/xemacps_hw.o ps7_cortexa9_0/lib/getpid.o ps7_corte
-TRACE::2022-07-31.18:24:00::SCWBDomain::xa9_0/lib/xscugic_intr.o ps7_cortexa9_0/lib/abort.o ps7_cortexa9_0/lib/usleep.o ps7_cortexa9_0/lib/asm_vectors.o ps7_cortexa9_0
-TRACE::2022-07-31.18:24:00::SCWBDomain::/lib/xl2cc_counter.o ps7_cortexa9_0/lib/xgpiops.o ps7_cortexa9_0/lib/xil_testmem.o ps7_cortexa9_0/lib/xgpiops_hw.o ps7_cortexa9
-TRACE::2022-07-31.18:24:00::SCWBDomain::_0/lib/outbyte.o ps7_cortexa9_0/lib/xuartps_selftest.o ps7_cortexa9_0/lib/xuartps_sinit.o ps7_cortexa9_0/lib/xadcps.o ps7_corte
-TRACE::2022-07-31.18:24:00::SCWBDomain::xa9_0/lib/xuartps_g.o ps7_cortexa9_0/lib/kill.o ps7_cortexa9_0/lib/xil_printf.o ps7_cortexa9_0/lib/time.o ps7_cortexa9_0/lib/xg
-TRACE::2022-07-31.18:24:00::SCWBDomain::pio_sinit.o ps7_cortexa9_0/lib/xil_clocking.o ps7_cortexa9_0/lib/xscuwdt.o ps7_cortexa9_0/lib/xgpio_g.o ps7_cortexa9_0/lib/xgpi
-TRACE::2022-07-31.18:24:00::SCWBDomain::ops_selftest.o ps7_cortexa9_0/lib/xgpiops_sinit.o ps7_cortexa9_0/lib/xemacps_g.o ps7_cortexa9_0/lib/close.o ps7_cortexa9_0/lib/
-TRACE::2022-07-31.18:24:00::SCWBDomain::xsdps.o ps7_cortexa9_0/lib/xusbps_g.o ps7_cortexa9_0/lib/xadcps_intr.o ps7_cortexa9_0/lib/xscutimer_selftest.o ps7_cortexa9_0/l
-TRACE::2022-07-31.18:24:00::SCWBDomain::ib/xdmaps_selftest.o ps7_cortexa9_0/lib/inbyte.o ps7_cortexa9_0/lib/xscutimer_sinit.o ps7_cortexa9_0/lib/xdmaps_sinit.o ps7_cor
-TRACE::2022-07-31.18:24:00::SCWBDomain::texa9_0/lib/xil_misc_psreset_api.o ps7_cortexa9_0/lib/xsdps_options.o ps7_cortexa9_0/lib/xscutimer_g.o ps7_cortexa9_0/lib/xdmap
-TRACE::2022-07-31.18:24:00::SCWBDomain::s_g.o ps7_cortexa9_0/lib/xqspips_options.o ps7_cortexa9_0/lib/xil_sleeptimer.o ps7_cortexa9_0/lib/xdevcfg_hw.o ps7_cortexa9_0/l
-TRACE::2022-07-31.18:24:00::SCWBDomain::ib/unlink.o ps7_cortexa9_0/lib/xusbps_sinit.o ps7_cortexa9_0/lib/sleep.o ps7_cortexa9_0/lib/xil_mem.o ps7_cortexa9_0/lib/xplatf
-TRACE::2022-07-31.18:24:00::SCWBDomain::orm_info.o ps7_cortexa9_0/lib/xadcps_selftest.o ps7_cortexa9_0/lib/xil_testcache.o ps7_cortexa9_0/lib/xgpio_selftest.o ps7_cort
-TRACE::2022-07-31.18:24:00::SCWBDomain::exa9_0/lib/xil_mmu.o ps7_cortexa9_0/lib/xadcps_sinit.o ps7_cortexa9_0/lib/xqspips_sinit.o ps7_cortexa9_0/lib/xgpiops_g.o ps7_co
-TRACE::2022-07-31.18:24:00::SCWBDomain::rtexa9_0/lib/xadcps_g.o ps7_cortexa9_0/lib/xscugic.o ps7_cortexa9_0/lib/xil-crt0.o ps7_cortexa9_0/lib/isatty.o ps7_cortexa9_0/l
-TRACE::2022-07-31.18:24:00::SCWBDomain::ib/xgpio_extra.o ps7_cortexa9_0/lib/xscuwdt_selftest.o ps7_cortexa9_0/lib/xemacps_intr.o ps7_cortexa9_0/lib/_exit.o ps7_cortexa
-TRACE::2022-07-31.18:24:00::SCWBDomain::9_0/lib/xscuwdt_g.o ps7_cortexa9_0/lib/vectors.o ps7_cortexa9_0/lib/xsdps_g.o ps7_cortexa9_0/lib/xuartps_options.o ps7_cortexa9
-TRACE::2022-07-31.18:24:00::SCWBDomain::_0/lib/xdevcfg_intr.o ps7_cortexa9_0/lib/errno.o ps7_cortexa9_0/lib/xqspips_hw.o ps7_cortexa9_0/lib/fstat.o ps7_cortexa9_0/lib/
-TRACE::2022-07-31.18:24:00::SCWBDomain::xusbps_hw.o ps7_cortexa9_0/lib/sbrk.o ps7_cortexa9_0/lib/xdmaps_hw.o ps7_cortexa9_0/lib/xsdps_card.o ps7_cortexa9_0/lib/xuartps
-TRACE::2022-07-31.18:24:00::SCWBDomain::_intr.o ps7_cortexa9_0/lib/xil_util.o ps7_cortexa9_0/lib/xscugic_selftest.o ps7_cortexa9_0/lib/xdmaps.o ps7_cortexa9_0/lib/xtim
-TRACE::2022-07-31.18:24:00::SCWBDomain::e_l.o ps7_cortexa9_0/lib/read.o ps7_cortexa9_0/lib/xgpio_intr.o ps7_cortexa9_0/lib/xscuwdt_sinit.o ps7_cortexa9_0/lib/putnum.o
-TRACE::2022-07-31.18:24:00::SCWBDomain::ps7_cortexa9_0/lib/xdevcfg_g.o ps7_cortexa9_0/lib/xscugic_sinit.o ps7_cortexa9_0/lib/xgpiops_intr.o ps7_cortexa9_0/lib/xscugic_
-TRACE::2022-07-31.18:24:00::SCWBDomain::g.o ps7_cortexa9_0/lib/xil_sleepcommon.o ps7_cortexa9_0/lib/cpu_init.o ps7_cortexa9_0/lib/xemacps_bdring.o ps7_cortexa9_0/lib/b
-TRACE::2022-07-31.18:24:00::SCWBDomain::oot.o ps7_cortexa9_0/lib/write.o ps7_cortexa9_0/lib/translation_table.o ps7_cortexa9_0/lib/xil_spinlock.o ps7_cortexa9_0/lib/xq
-TRACE::2022-07-31.18:24:00::SCWBDomain::spips.o ps7_cortexa9_0/lib/xil_testio.o ps7_cortexa9_0/lib/xil_cache.o ps7_cortexa9_0/lib/xemacps.o ps7_cortexa9_0/lib/xdevcfg_
-TRACE::2022-07-31.18:24:00::SCWBDomain::selftest.o ps7_cortexa9_0/lib/xdevcfg.o ps7_cortexa9_0/lib/xuartps_hw.o ps7_cortexa9_0/lib/print.o ps7_cortexa9_0/lib/fcntl.o p
-TRACE::2022-07-31.18:24:00::SCWBDomain::s7_cortexa9_0/lib/_open.o ps7_cortexa9_0/lib/cpputest_time.o ps7_cortexa9_0/lib/xuartps.o ps7_cortexa9_0/lib/xscugic_hw.o ps7_c
-TRACE::2022-07-31.18:24:00::SCWBDomain::ortexa9_0/lib/xsdps_host.o ps7_cortexa9_0/lib/xusbps_intr.o ps7_cortexa9_0/lib/xil_assert.o
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::Finished building libraries
-
-TRACE::2022-07-31.18:24:00::SCWBDomain::make: Leaving directory '/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp'
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-TRACE::2022-07-31.18:24:00::SCWBDomain::arm-none-eabi-gcc -o fsbl.elf fsbl_handoff.o fsbl_hooks.o image_mover.o main.o md5.o nand.o nor.o pcap.o ps7_init.o qspi.o rsa.
-TRACE::2022-07-31.18:24:00::SCWBDomain::o sd.o -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id
-TRACE::2022-07-31.18:24:00::SCWBDomain::=none -specs=Xilinx.spec -lrsa -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilffs,-lxil,-lgcc,-lc,--end-
-TRACE::2022-07-31.18:24:00::SCWBDomain::group -Wl,--start-group,-lrsa,-lxil,-lgcc,-lc,--end-group -Wl,--gc-sections -Lzyn
-TRACE::2022-07-31.18:24:00::SCWBDomain::q_fsbl_bsp/ps7_cortexa9_0/lib -L./ -Tlscript.ld
-
-LOG::2022-07-31.18:24:00::SCWSystem::Checking the domain standalone_domain
-LOG::2022-07-31.18:24:00::SCWSystem::Not a boot domain
-LOG::2022-07-31.18:24:00::SCWSystem::Started Processing the domain standalone_domain
-TRACE::2022-07-31.18:24:00::SCWDomain::Generating domain artifcats
-TRACE::2022-07-31.18:24:00::SCWMssOS::Generating standalone artifcats
-TRACE::2022-07-31.18:24:00::SCWMssOS::Copying the qemu file from /hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt To /home/dylan/workspace/phased_array_platform/export/phased_array_platform/sw/phased_array_platform/qemu/
-TRACE::2022-07-31.18:24:00::SCWMssOS::Copying the qemu file from /hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt To /home/dylan/workspace/phased_array_platform/export/phased_array_platform/sw/phased_array_platform/standalone_domain/qemu/
-TRACE::2022-07-31.18:24:00::SCWMssOS:: Copying the user libraries.
-TRACE::2022-07-31.18:24:00::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:24:00::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:24:00::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:24:00::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-31.18:24:00::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:24:00::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-31.18:24:00::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-31.18:24:00::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-31.18:24:00::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-31.18:24:00::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-31.18:24:00::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-31.18:24:00::SCWMssOS::Completed writing the mss file at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp
-TRACE::2022-07-31.18:24:00::SCWMssOS::Mss edits present, copying mssfile into export location /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-31.18:24:00::SCWMssOS::bsp generated is upto date with the mss file. Skipping bsp generation.
-TRACE::2022-07-31.18:24:00::SCWMssOS::BSP is already built. skipping the bsp build ...
-TRACE::2022-07-31.18:24:00::SCWDomain::Building the domain as part of full build : standalone_domain
-TRACE::2022-07-31.18:24:00::SCWMssOS::doing bsp build ...
-TRACE::2022-07-31.18:24:00::SCWMssOS::System Command Ran cd /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp ; bash -c "make "
-TRACE::2022-07-31.18:24:00::SCWMssOS::make --no-print-directory seq_libs
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Finished building libraries sequentially.
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -j 6 --no-print-directory par_libs
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_9/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/sdps_v3_13/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_4/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_7/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/gpiops_v3_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-31.18:24:00::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-31.18:24:00::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/sdps_v3_13/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-31.18:24:00::SCWMssOS::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-31.18:24:00::SCWMssOS::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_4/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-31.18:24:00::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-31.18:24:00::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/scugic_v4_6/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/devcfg_v3_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-31.18:24:00::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-31.18:24:00::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_15/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scugic_v4_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-31.18:24:00::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-31.18:24:00::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/emacps_v3_15/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab
-TRACE::2022-07-31.18:24:00::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
-TRACE::2022-07-31.18:24:00::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_11/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/uartps_v3_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab
-TRACE::2022-07-31.18:24:00::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
-TRACE::2022-07-31.18:24:00::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/gpio_v4_8/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/gpio_v4_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a
-TRACE::2022-07-31.18:24:00::SCWMssOS::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no
-TRACE::2022-07-31.18:24:00::SCWMssOS::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/standalone_v7_6/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/standalone_v7_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-
-TRACE::2022-07-31.18:24:00::SCWMssOS::eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha
-TRACE::2022-07-31.18:24:00::SCWMssOS::rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-
-TRACE::2022-07-31.18:24:00::SCWMssOS::none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-a
-TRACE::2022-07-31.18:24:00::SCWMssOS::bi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/usbps_v2_7/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/usbps_v2_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-31.18:24:00::SCWMssOS::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-31.18:24:00::SCWMssOS::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_2/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-31.18:24:00::SCWMssOS::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-31.18:24:00::SCWMssOS::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_6/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/xadcps_v2_6/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-31.18:24:00::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-31.18:24:00::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-no
-TRACE::2022-07-31.18:24:00::SCWMssOS::ne-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi
-TRACE::2022-07-31.18:24:00::SCWMssOS::=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_9/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_8/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/qspips_v3_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi
-TRACE::2022-07-31.18:24:00::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
-TRACE::2022-07-31.18:24:00::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/dmaps_v2_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-31.18:24:00::SCWMssOS::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-31.18:24:00::SCWMssOS::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_3/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scutimer_v2_3/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-ea
-TRACE::2022-07-31.18:24:00::SCWMssOS::bi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
-TRACE::2022-07-31.18:24:00::SCWMssOS:: -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/gpiops_v3_9/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/sdps_v3_13/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/gpiops_v3_9/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-31.18:24:00::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-31.18:24:00::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/scuwdt_v2_4/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_4/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-31.18:24:00::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-31.18:24:00::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/devcfg_v3_7/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/sdps_v3_13/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
-TRACE::2022-07-31.18:24:00::SCWMssOS:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost
-TRACE::2022-07-31.18:24:00::SCWMssOS::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/devcfg_v3_7/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-31.18:24:00::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-31.18:24:00::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/emacps_v3_15/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/scugic_v4_6/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scugic_v4_6/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-31.18:24:00::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-31.18:24:00::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/emacps_v3_15/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a
-TRACE::2022-07-31.18:24:00::SCWMssOS::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no
-TRACE::2022-07-31.18:24:00::SCWMssOS::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/uartps_v3_11/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/uartps_v3_11/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a
-TRACE::2022-07-31.18:24:00::SCWMssOS::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no
-TRACE::2022-07-31.18:24:00::SCWMssOS::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/gpio_v4_8/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/gpio_v4_8/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
-TRACE::2022-07-31.18:24:00::SCWMssOS::"ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta
-TRACE::2022-07-31.18:24:00::SCWMssOS::rtfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/standalone_v7_6/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/usbps_v2_7/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/ddrps_v1_2/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/standalone_v7_6/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab
-TRACE::2022-07-31.18:24:00::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
-TRACE::2022-07-31.18:24:00::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/usbps_v2_7/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
-TRACE::2022-07-31.18:24:00::SCWMssOS:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost
-TRACE::2022-07-31.18:24:00::SCWMssOS::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_8/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-non
-TRACE::2022-07-31.18:24:00::SCWMssOS::e-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=
-TRACE::2022-07-31.18:24:00::SCWMssOS::hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
-TRACE::2022-07-31.18:24:00::SCWMssOS:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost
-TRACE::2022-07-31.18:24:00::SCWMssOS::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/xadcps_v2_6/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/xadcps_v2_6/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-31.18:24:00::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-31.18:24:00::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/qspips_v3_9/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/qspips_v3_9/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as
-TRACE::2022-07-31.18:24:00::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos
-TRACE::2022-07-31.18:24:00::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:00::SCWMssOS::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_11/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-
-TRACE::2022-07-31.18:24:00::SCWMssOS::eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha
-TRACE::2022-07-31.18:24:00::SCWMssOS::rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:01::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/dmaps_v2_8/src
-
-TRACE::2022-07-31.18:24:01::SCWMssOS::make -C ps7_cortexa9_0/libsrc/dmaps_v2_8/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as"
-TRACE::2022-07-31.18:24:01::SCWMssOS:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost
-TRACE::2022-07-31.18:24:01::SCWMssOS::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:01::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/scutimer_v2_3/src
-
-TRACE::2022-07-31.18:24:01::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scutimer_v2_3/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-
-TRACE::2022-07-31.18:24:01::SCWMssOS::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n
-TRACE::2022-07-31.18:24:01::SCWMssOS::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
-
-TRACE::2022-07-31.18:24:01::SCWMssOS::Finished building libraries parallelly.
-
-TRACE::2022-07-31.18:24:01::SCWMssOS::make --no-print-directory archive
-
-TRACE::2022-07-31.18:24:01::SCWMssOS::arm-none-eabi-ar -r ps7_cortexa9_0/lib/libxil.a ps7_cortexa9_0/lib/open.o ps7_cortexa9_0/lib/xemacps_control.o ps7_cortexa9_0/
-TRACE::2022-07-31.18:24:01::SCWMssOS::lib/xgpio.o ps7_cortexa9_0/lib/xil_exception.o ps7_cortexa9_0/lib/xqspips_selftest.o ps7_cortexa9_0/lib/xdevcfg_sinit.o ps7_cor
-TRACE::2022-07-31.18:24:01::SCWMssOS::texa9_0/lib/lseek.o ps7_cortexa9_0/lib/xsdps_sinit.o ps7_cortexa9_0/lib/xusbps_endpoint.o ps7_cortexa9_0/lib/xusbps.o ps7_corte
-TRACE::2022-07-31.18:24:01::SCWMssOS::xa9_0/lib/xqspips_g.o ps7_cortexa9_0/lib/xemacps_sinit.o ps7_cortexa9_0/lib/_sbrk.o ps7_cortexa9_0/lib/xpm_counter.o ps7_cortex
-TRACE::2022-07-31.18:24:01::SCWMssOS::a9_0/lib/xcoresightpsdcc.o ps7_cortexa9_0/lib/xscutimer.o ps7_cortexa9_0/lib/xemacps_hw.o ps7_cortexa9_0/lib/getpid.o ps7_corte
-TRACE::2022-07-31.18:24:01::SCWMssOS::xa9_0/lib/xscugic_intr.o ps7_cortexa9_0/lib/abort.o ps7_cortexa9_0/lib/usleep.o ps7_cortexa9_0/lib/asm_vectors.o ps7_cortexa9_0
-TRACE::2022-07-31.18:24:01::SCWMssOS::/lib/xl2cc_counter.o ps7_cortexa9_0/lib/xgpiops.o ps7_cortexa9_0/lib/xil_testmem.o ps7_cortexa9_0/lib/xgpiops_hw.o ps7_cortexa9
-TRACE::2022-07-31.18:24:01::SCWMssOS::_0/lib/xuartps_selftest.o ps7_cortexa9_0/lib/xuartps_sinit.o ps7_cortexa9_0/lib/xadcps.o ps7_cortexa9_0/lib/xuartps_g.o ps7_cor
-TRACE::2022-07-31.18:24:01::SCWMssOS::texa9_0/lib/kill.o ps7_cortexa9_0/lib/xil_printf.o ps7_cortexa9_0/lib/time.o ps7_cortexa9_0/lib/xgpio_sinit.o ps7_cortexa9_0/li
-TRACE::2022-07-31.18:24:01::SCWMssOS::b/xil_clocking.o ps7_cortexa9_0/lib/xscuwdt.o ps7_cortexa9_0/lib/xgpio_g.o ps7_cortexa9_0/lib/xgpiops_selftest.o ps7_cortexa9_0
-TRACE::2022-07-31.18:24:01::SCWMssOS::/lib/xgpiops_sinit.o ps7_cortexa9_0/lib/xemacps_g.o ps7_cortexa9_0/lib/close.o ps7_cortexa9_0/lib/xsdps.o ps7_cortexa9_0/lib/xu
-TRACE::2022-07-31.18:24:01::SCWMssOS::sbps_g.o ps7_cortexa9_0/lib/xadcps_intr.o ps7_cortexa9_0/lib/putnum.o ps7_cortexa9_0/lib/xscutimer_selftest.o ps7_cortexa9_0/li
-TRACE::2022-07-31.18:24:01::SCWMssOS::b/xdmaps_selftest.o ps7_cortexa9_0/lib/inbyte.o ps7_cortexa9_0/lib/xscutimer_sinit.o ps7_cortexa9_0/lib/xdmaps_sinit.o ps7_cort
-TRACE::2022-07-31.18:24:01::SCWMssOS::exa9_0/lib/xil_misc_psreset_api.o ps7_cortexa9_0/lib/xsdps_options.o ps7_cortexa9_0/lib/xscutimer_g.o ps7_cortexa9_0/lib/xdmaps
-TRACE::2022-07-31.18:24:01::SCWMssOS::_g.o ps7_cortexa9_0/lib/xqspips_options.o ps7_cortexa9_0/lib/xil_sleeptimer.o ps7_cortexa9_0/lib/xdevcfg_hw.o ps7_cortexa9_0/li
-TRACE::2022-07-31.18:24:01::SCWMssOS::b/unlink.o ps7_cortexa9_0/lib/xusbps_sinit.o ps7_cortexa9_0/lib/sleep.o ps7_cortexa9_0/lib/xil_mem.o ps7_cortexa9_0/lib/xplatfo
-TRACE::2022-07-31.18:24:01::SCWMssOS::rm_info.o ps7_cortexa9_0/lib/xadcps_selftest.o ps7_cortexa9_0/lib/xil_testcache.o ps7_cortexa9_0/lib/xgpio_selftest.o ps7_corte
-TRACE::2022-07-31.18:24:01::SCWMssOS::xa9_0/lib/xil_mmu.o ps7_cortexa9_0/lib/xadcps_sinit.o ps7_cortexa9_0/lib/xqspips_sinit.o ps7_cortexa9_0/lib/xgpiops_g.o ps7_cor
-TRACE::2022-07-31.18:24:01::SCWMssOS::texa9_0/lib/xadcps_g.o ps7_cortexa9_0/lib/xscugic.o ps7_cortexa9_0/lib/xil-crt0.o ps7_cortexa9_0/lib/isatty.o ps7_cortexa9_0/li
-TRACE::2022-07-31.18:24:01::SCWMssOS::b/xgpio_extra.o ps7_cortexa9_0/lib/xscuwdt_selftest.o ps7_cortexa9_0/lib/xemacps_intr.o ps7_cortexa9_0/lib/_exit.o ps7_cortexa9
-TRACE::2022-07-31.18:24:01::SCWMssOS::_0/lib/xscuwdt_g.o ps7_cortexa9_0/lib/vectors.o ps7_cortexa9_0/lib/xsdps_g.o ps7_cortexa9_0/lib/xuartps_options.o ps7_cortexa9_
-TRACE::2022-07-31.18:24:01::SCWMssOS::0/lib/xdevcfg_intr.o ps7_cortexa9_0/lib/errno.o ps7_cortexa9_0/lib/xqspips_hw.o ps7_cortexa9_0/lib/fstat.o ps7_cortexa9_0/lib/x
-TRACE::2022-07-31.18:24:01::SCWMssOS::usbps_hw.o ps7_cortexa9_0/lib/sbrk.o ps7_cortexa9_0/lib/xdmaps_hw.o ps7_cortexa9_0/lib/xsdps_card.o ps7_cortexa9_0/lib/xuartps_
-TRACE::2022-07-31.18:24:01::SCWMssOS::intr.o ps7_cortexa9_0/lib/xil_util.o ps7_cortexa9_0/lib/xscugic_selftest.o ps7_cortexa9_0/lib/xdmaps.o ps7_cortexa9_0/lib/xtime
-TRACE::2022-07-31.18:24:01::SCWMssOS::_l.o ps7_cortexa9_0/lib/read.o ps7_cortexa9_0/lib/xgpio_intr.o ps7_cortexa9_0/lib/xscuwdt_sinit.o ps7_cortexa9_0/lib/outbyte.o
-TRACE::2022-07-31.18:24:01::SCWMssOS::ps7_cortexa9_0/lib/xdevcfg_g.o ps7_cortexa9_0/lib/xscugic_sinit.o ps7_cortexa9_0/lib/xgpiops_intr.o ps7_cortexa9_0/lib/xscugic_
-TRACE::2022-07-31.18:24:01::SCWMssOS::g.o ps7_cortexa9_0/lib/xil_sleepcommon.o ps7_cortexa9_0/lib/cpu_init.o ps7_cortexa9_0/lib/xemacps_bdring.o ps7_cortexa9_0/lib/b
-TRACE::2022-07-31.18:24:01::SCWMssOS::oot.o ps7_cortexa9_0/lib/write.o ps7_cortexa9_0/lib/translation_table.o ps7_cortexa9_0/lib/xil_spinlock.o ps7_cortexa9_0/lib/xq
-TRACE::2022-07-31.18:24:01::SCWMssOS::spips.o ps7_cortexa9_0/lib/xil_testio.o ps7_cortexa9_0/lib/xil_cache.o ps7_cortexa9_0/lib/xemacps.o ps7_cortexa9_0/lib/xdevcfg_
-TRACE::2022-07-31.18:24:01::SCWMssOS::selftest.o ps7_cortexa9_0/lib/xdevcfg.o ps7_cortexa9_0/lib/xuartps_hw.o ps7_cortexa9_0/lib/print.o ps7_cortexa9_0/lib/fcntl.o p
-TRACE::2022-07-31.18:24:01::SCWMssOS::s7_cortexa9_0/lib/_open.o ps7_cortexa9_0/lib/cpputest_time.o ps7_cortexa9_0/lib/xuartps.o ps7_cortexa9_0/lib/xscugic_hw.o ps7_c
-TRACE::2022-07-31.18:24:01::SCWMssOS::ortexa9_0/lib/xsdps_host.o ps7_cortexa9_0/lib/xusbps_intr.o ps7_cortexa9_0/lib/xil_assert.o
-
-TRACE::2022-07-31.18:24:01::SCWMssOS::Finished building libraries
-
-TRACE::2022-07-31.18:24:01::SCWMssOS::Copying to export directory.
-TRACE::2022-07-31.18:24:01::SCWMssOS:: Checking if to create the Supporting Applications
-TRACE::2022-07-31.18:24:01::SCWMssOS:: No Linux domain exists, trying to generate FSBL
-LOG::2022-07-31.18:24:01::SCWSystem::Completed Processing the domain standalone_domain
-LOG::2022-07-31.18:24:01::SCWSystem::Completed Processing the sysconfig phased_array_platform
-LOG::2022-07-31.18:24:01::SCWPlatform::Completed generating the artifacts for system configuration phased_array_platform
-TRACE::2022-07-31.18:24:01::SCWPlatform::Started preparing the platform
-TRACE::2022-07-31.18:24:01::SCWSystem::Writing the bif file for system config phased_array_platform
-TRACE::2022-07-31.18:24:01::SCWSystem::dir created
-TRACE::2022-07-31.18:24:01::SCWSystem::Writing the bif
-TRACE::2022-07-31.18:24:01::SCWPlatform::Started writing the spfm file
-TRACE::2022-07-31.18:24:01::SCWPlatform::Started writing the xpfm file
-TRACE::2022-07-31.18:24:01::SCWPlatform::Completed generating the platform
-TRACE::2022-07-31.18:24:01::SCWMssOS::Saving the mss changes /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-31.18:24:01::SCWMssOS::Found a swdesign opened with the mssfile.
-TRACE::2022-07-31.18:24:01::SCWMssOS::Completed writemss as part of save.
-TRACE::2022-07-31.18:24:01::SCWMssOS::Commit changes completed.
-TRACE::2022-07-31.18:24:01::SCWMssOS::Saving the mss changes /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-31.18:24:01::SCWMssOS::Found a swdesign opened with the mssfile.
-TRACE::2022-07-31.18:24:01::SCWMssOS::Completed writemss as part of save.
-TRACE::2022-07-31.18:24:01::SCWMssOS::Commit changes completed.
-TRACE::2022-07-31.18:24:01::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:24:01::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:24:01::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:24:01::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-31.18:24:01::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:24:01::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-31.18:24:01::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-31.18:24:01::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-31.18:24:01::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-31.18:24:01::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-31.18:24:01::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-31.18:24:01::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss
-TRACE::2022-07-31.18:24:01::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:24:01::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:24:01::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:24:01::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-31.18:24:01::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:24:01::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-31.18:24:01::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-31.18:24:01::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-31.18:24:01::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-31.18:24:01::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-31.18:24:01::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-31.18:24:01::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-31.18:24:01::SCWWriter::formatted JSON is {
- "platformName": "phased_array_platform",
- "sprVersion": "2.0",
- "mode": "gui",
- "dsaType": "Fixed",
- "platformDesc": "phased_array_platform",
- "platHandOff": "/home/dylan/Documents/FPGA/phased_array/design_1_wrapper.xsa",
- "platIntHandOff": "/hw/design_1_wrapper.xsa",
- "deviceType": "zynq",
- "platIsPrebuiltAutogen": "false",
- "platIsNoBootBsp": "false",
- "hasFsblMakeHasChanges": "false",
- "hasPmufwMakeHasChanges": "false",
- "fsblExtraCompilerFlags": "-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ",
- "platPreBuiltFlag": false,
- "platformSamplesDir": "",
- "platActiveSys": "phased_array_platform",
- "systems": [{
- "systemName": "phased_array_platform",
- "systemDesc": "phased_array_platform",
- "sysIsBootAutoGen": "true",
- "systemDispName": "phased_array_platform",
- "sysActiveDom": "standalone_domain",
- "sysDefaultDom": "standalone_domain",
- "domains": [{
- "domainName": "zynq_fsbl",
- "domainDispName": "zynq_fsbl",
- "domainDesc": "FSBL Application BSP - Auto Generated.",
- "processors": "ps7_cortexa9_0",
- "os": "standalone",
- "sdxOs": "standalone",
- "debugEnable": "",
- "domRuntimes": ["cpp"],
- "swRepo": "",
- "mssOsVer": "7.6",
- "mssFile": "",
- "md5Digest": "3ad66e6342e47cdeb46ebdacd606f8ba",
- "compatibleApp": "zynq_fsbl",
- "domType": "bootDomain",
- "arch": "32-bit",
- "appSettings": {
- "appCompilerFlags": "",
- "appLinkerFlags": ""
- },
- "addedLibs": ["xilffs:4.6", "xilrsa:1.6"],
- "libOptions": {
- "libsContainingOptions": []
- },
- "prebuiltLibs": {
- "prebuiltIncPath": [],
- "prebuiltLibPath": []
- },
- "isolation": {
- }
- }, {
- "domainName": "standalone_domain",
- "domainDispName": "standalone on ps7_cortexa9_0",
- "domainDesc": "standalone_domain",
- "processors": "ps7_cortexa9_0",
- "os": "standalone",
- "sdxOs": "standalone",
- "qemuArgs": "/hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt",
- "qemuData": "/hddisk/Xilinx/Vitis/2021.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/",
- "debugEnable": "False",
- "domRuntimes": ["cpp"],
- "swRepo": "",
- "mssOsVer": "7.6",
- "mssFile": "",
- "md5Digest": "8f4cd5b2e4c0f3d4481583b0fc9b267f",
- "compatibleApp": "",
- "domType": "mssDomain",
- "appSettings": {
- "appCompilerFlags": "",
- "appLinkerFlags": ""
- },
- "addedLibs": [],
- "libOptions": {
- "libsContainingOptions": []
- },
- "prebuiltLibs": {
- "prebuiltIncPath": [],
- "prebuiltLibPath": []
- },
- "isolation": {
- }
- }]
- }]
-}
-KEYINFO::2022-07-31.18:24:01::SCWPlatform::updated the xpfm file.
-TRACE::2022-07-31.18:24:01::SCWPlatform::Trying to open the hw design at /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:24:01::SCWPlatform::DSA given /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:24:01::SCWPlatform::DSA absoulate path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:24:01::SCWPlatform::DSA directory /home/dylan/workspace/phased_array_platform/hw
-TRACE::2022-07-31.18:24:01::SCWPlatform:: Platform Path /home/dylan/workspace/phased_array_platform/hw/design_1_wrapper.xsa
-TRACE::2022-07-31.18:24:01::SCWPlatform:: Unique name xilinx:zybo-z7-20::0.0
-TRACE::2022-07-31.18:24:01::SCWPlatform::Trying to set the existing hwdb with name design_1_wrapper_0
-TRACE::2022-07-31.18:24:01::SCWPlatform::Opened existing hwdb design_1_wrapper_0
-TRACE::2022-07-31.18:24:01::SCWPlatform::Found the Hw Db part of the input DSA
-TRACE::2022-07-31.18:24:01::SCWMssOS::Checking the sw design at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
-TRACE::2022-07-31.18:24:01::SCWMssOS::DEBUG: swdes dump /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0||
-/home/dylan/workspace/phased_array_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss|system||
-
-TRACE::2022-07-31.18:24:01::SCWMssOS::Sw design exists and opened at /home/dylan/workspace/phased_array_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ce/005fa1525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ce/005fa1525243001d18b399c1eb9b3628
deleted file mode 100644
index 9794da0..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ce/005fa1525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,350 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xenv_standalone.h
-*
-* Defines common services specified by xenv.h.
-*
-* @note
-* This file is not intended to be included directly by driver code.
-* Instead, the generic xenv.h file is intended to be included by driver
-* code.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a wgr 02/28/07 Added cache handling macros.
-* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
-* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
-* used under Xilinx standalone BSP.
-* 1.00a xd 11/03/04 Improved support for doxygen.
-* 1.00a rmm 03/21/02 First release
-* 1.00a wgr 03/22/07 Converted to new coding style.
-* 1.00a rpm 06/29/07 Added udelay macro for standalone
-* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
-* to in MICROBLAZE section
-* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
-*
-*
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XENV_STANDALONE_H
-#define XENV_STANDALONE_H
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-/******************************************************************************
- *
- * Get the processor dependent includes
- *
- ******************************************************************************/
-
-#include
-
-#if defined __MICROBLAZE__
-# include "mb_interface.h"
-# include "xparameters.h" /* XPAR constants used below in MB section */
-
-#elif defined __PPC__
-# include "sleep.h"
-# include "xcache_l.h" /* also include xcache_l.h for caching macros */
-#endif
-
-/******************************************************************************
- *
- * MEMCPY / MEMSET related macros.
- *
- * The following are straight forward implementations of memset and memcpy.
- *
- * NOTE: memcpy may not work if source and target memory area are overlapping.
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
- *
- * Copies a non-overlapping block of memory.
- *
- * @param DestPtr
- * Destination address to copy data to.
- *
- * @param SrcPtr
- * Source address to copy data from.
- *
- * @param Bytes
- * Number of bytes to copy.
- *
- * @return None.
- *
- * @note
- * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
- *
- * @note
- * This implementation MAY BREAK work if source and target memory
- * area are overlapping.
- *
- *****************************************************************************/
-
-#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
- memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
-
-
-
-/*****************************************************************************/
-/**
- *
- * Fills an area of memory with constant data.
- *
- * @param DestPtr
- * Destination address to copy data to.
- *
- * @param Data
- * Value to set.
- *
- * @param Bytes
- * Number of bytes to copy.
- *
- * @return None.
- *
- * @note
- * The use of XENV_MEM_FILL is deprecated. Use memset() instead.
- *
- *****************************************************************************/
-
-#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
- memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
-
-
-
-/******************************************************************************
- *
- * TIME related macros
- *
- ******************************************************************************/
-
-/**
- * A structure that contains a time stamp used by other time stamp macros
- * defined below. This structure is processor dependent.
- */
-typedef s32 XENV_TIME_STAMP;
-
-/*****************************************************************************/
-/**
- *
- * Time is derived from the 64 bit PPC timebase register
- *
- * @param StampPtr is the storage for the retrieved time stamp.
- *
- * @return None.
- *
- * @note
- *
- * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_GET(StampPtr)
-
-/*****************************************************************************/
-/**
- *
- * This macro is not yet implemented and always returns 0.
- *
- * @param Stamp1Ptr is the first sampled time stamp.
- * @param Stamp2Ptr is the second sampled time stamp.
- *
- * @return 0
- *
- * @note
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
-
-/*****************************************************************************/
-/**
- *
- * This macro is not yet implemented and always returns 0.
- *
- * @param Stamp1Ptr is the first sampled time stamp.
- * @param Stamp2Ptr is the second sampled time stamp.
- *
- * @return 0
- *
- * @note
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
-
-/*****************************************************************************/
-/**
- * XENV_USLEEP(unsigned delay)
- *
- * Delay the specified number of microseconds. Not implemented without OS
- * support.
- *
- * @param delay
- * Number of microseconds to delay.
- *
- * @return None.
- *
- *****************************************************************************/
-
-#ifdef __PPC__
-#define XENV_USLEEP(delay) usleep(delay)
-#define udelay(delay) usleep(delay)
-#else
-#define XENV_USLEEP(delay)
-#define udelay(delay)
-#endif
-
-
-/******************************************************************************
- *
- * CACHE handling macros / mappings
- *
- ******************************************************************************/
-/******************************************************************************
- *
- * Processor independent macros
- *
- ******************************************************************************/
-
-#define XCACHE_ENABLE_CACHE() \
- { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
-
-#define XCACHE_DISABLE_CACHE() \
- { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
-
-
-/******************************************************************************
- *
- * MicroBlaze case
- *
- * NOTE: Currently the following macros will only work on systems that contain
- * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
- * system is built using a xparameters.h file.
- *
- ******************************************************************************/
-
-#if defined __MICROBLAZE__
-
-/* Check if MicroBlaze data cache was built into the core.
- */
-#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
-# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
-# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
-# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
-
-# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
- microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
-
-#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
-# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
-#else
-# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
-#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
-
-#else
-# define XCACHE_ENABLE_DCACHE()
-# define XCACHE_DISABLE_DCACHE()
-# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
-#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
-
-
-/* Check if MicroBlaze instruction cache was built into the core.
- */
-#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
-# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
-# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
-
-# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
-
-# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
- microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
-
-#else
-# define XCACHE_ENABLE_ICACHE()
-# define XCACHE_DISABLE_ICACHE()
-#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
-
-
-/******************************************************************************
- *
- * PowerPC case
- *
- * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
- * specific memory region (0x80000001). Each bit (0-30) in the regions
- * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
- * range.
- *
- * regions --> cached address range
- * ------------|--------------------------------------------------
- * 0x80000000 | [0, 0x7FFFFFF]
- * 0x00000001 | [0xF8000000, 0xFFFFFFFF]
- * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
- *
- ******************************************************************************/
-
-#elif defined __PPC__
-
-#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
-#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
-#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
-#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
-
-#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
- XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
-
-#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
-
-#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
-
-
-/******************************************************************************
- *
- * Unknown processor / architecture
- *
- ******************************************************************************/
-
-#else
-/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* #ifndef XENV_STANDALONE_H */
-
- /**
- *@endcond
- */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ce/139ef6585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ce/139ef6585243001d18b399c1eb9b3628
deleted file mode 100644
index 31156ee..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ce/139ef6585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,96 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xl2cc_counter.h
-*
-* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions
-*
-* xl2cc_counter.h contains APIs for configuring and controlling the event
-* counters in PL310 L2 cache controller.
-* PL310 has two event counters which can be used to count variety of events
-* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions
-* for different configurations which can be used for the event counters to
-* count a set of events.
-*
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
-* inside the APIs
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-*
-******************************************************************************/
-
-/**
-*@cond nocomments
-*/
-
-#ifndef L2CCCOUNTER_H /* prevent circular inclusions */
-#define L2CCCOUNTER_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/************************** Constant Definitions ****************************/
-
-/*
- * The following constants define the event codes for the event counters.
- */
-#define XL2CC_CO 0x1
-#define XL2CC_DRHIT 0x2
-#define XL2CC_DRREQ 0x3
-#define XL2CC_DWHIT 0x4
-#define XL2CC_DWREQ 0x5
-#define XL2CC_DWTREQ 0x6
-#define XL2CC_IRHIT 0x7
-#define XL2CC_IRREQ 0x8
-#define XL2CC_WA 0x9
-#define XL2CC_IPFALLOC 0xa
-#define XL2CC_EPFHIT 0xb
-#define XL2CC_EPFALLOC 0xc
-#define XL2CC_SRRCVD 0xd
-#define XL2CC_SRCONF 0xe
-#define XL2CC_EPFRCVD 0xf
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/**
-*@endcond
-*/
-
-/************************** Function Prototypes *****************************/
-
-void XL2cc_EventCtrInit(s32 Event0, s32 Event1);
-void XL2cc_EventCtrStart(void);
-void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* L2CCCOUNTER_H */
-/**
-* @} End of "addtogroup l2_event_counter_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ce/20c4b2525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ce/20c4b2525243001d18b399c1eb9b3628
deleted file mode 100644
index e48c5f3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ce/20c4b2525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,111 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_errata.h
-*
-* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
-* @{
-* Various ARM errata are handled in the standalone BSP. The implementation for
-* errata handling follows ARM guidelines and is based on the open source Linux
-* support for these errata.
-*
-* @note The errata handling is enabled by default. To disable handling of all the
-* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
-* disable errata on a per-erratum basis, un-define relevant macros in
-* xil_errata.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a srt 04/18/13 First release
-* 6.6 mus 12/07/17 Removed errata 753970, It fixes CR#989132.
-*
-*
-******************************************************************************/
-#ifndef XIL_ERRATA_H
-#define XIL_ERRATA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *@cond nocomments
- */
-/**
- * @name errata_definitions
- *
- * The errata conditions handled in the standalone BSP are listed below
- * @{
- */
-
-#define ENABLE_ARM_ERRATA 1
-
-/**
- *@endcond
- */
-
-#ifdef ENABLE_ARM_ERRATA
-
-/**
- * Errata No: 742230
- * Description: DMB operation may be faulty
- */
-#define CONFIG_ARM_ERRATA_742230 1
-
-/**
- * Errata No: 743622
- * Description: Faulty hazard checking in the Store Buffer may lead
- * to data corruption.
- */
-#define CONFIG_ARM_ERRATA_743622 1
-
-/**
- * Errata No: 775420
- * Description: A data cache maintenance operation which aborts,
- * might lead to deadlock
- */
-#define CONFIG_ARM_ERRATA_775420 1
-
-/**
- * Errata No: 794073
- * Description: Speculative instruction fetches with MMU disabled
- * might not comply with architectural requirements
- */
-#define CONFIG_ARM_ERRATA_794073 1
-
-
-/** PL310 L2 Cache Errata */
-
-/**
- * Errata No: 588369
- * Description: Clean & Invalidate maintenance operations do not
- * invalidate clean lines
- */
-#define CONFIG_PL310_ERRATA_588369 1
-
-/**
- * Errata No: 727915
- * Description: Background Clean and Invalidate by Way operation
- * can cause data corruption
- */
-#define CONFIG_PL310_ERRATA_727915 1
-
-/*@}*/
-#endif /* ENABLE_ARM_ERRATA */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_ERRATA_H */
-/**
-* @} End of "addtogroup a9_errata".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ce/702aef555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ce/702aef555243001d18b399c1eb9b3628
deleted file mode 100644
index 8dae55e..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ce/702aef555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,451 +0,0 @@
-;******************************************************************************
-; Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-; SPDX-License-Identifier: MIT
-;*****************************************************************************
-;****************************************************************************
-;**
-; @file boot.s
-;
-; This file contains the initial vector table for the Cortex A9 processor
-;
-;
-; MODIFICATION HISTORY:
-;
-; Ver Who Date Changes
-; ----- ------- -------- ---------------------------------------------------
-; 1.00a Initial version
-; 4.2 pkp 08/04/14 Removed PEEP board related code which contained
-; initialization of uart smc nor and sram
-; 5.0 pkp 16/12/14 Modified initialization code to enable scu after
-; MMU is enabled and removed incorrect initialization
-; of TLB lockdown register to fix CR#830580
-; 5.1 pkp 05/13/15 Changed the initialization order so to first invalidate
-; caches and TLB, enable MMU and caches, then enable SMP
-; bit in ACTLR. L2Cache invalidation and enabling of L2Cache
-; is done later.
-; 6.0 mus 08/04/16 Added code to detect zynq-7000 base silicon configuration and
-; attempt to enable dual core behavior on single cpu zynq-7000s devices
-; is prevented from corrupting system behavior.
-; 6.6 srm 10/25/17 Added timer configuration using XTime_StartTTCTimer API.
-; Now the TTC instance as specified by the user will be
-; started.
-;
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.00a wgr 10/10/10 First release
- * 1.04a nm 10/23/12 Fixed CR# 679106.
- * 1.05a kpc 07/03/13 Added XUsbPs_ResetHw function prototype
- * 2.00a kpc 04/03/14 Fixed CR#777764. Corrected max endpoint vale and masks
- * 2.5 pm 02/20/20 Added Endpoint Control Register bit positions for Rx & Tx
- *
- *
- ******************************************************************************/
-#ifndef XUSBPS_HW_H
-#define XUSBPS_HW_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-
-#define XUSBPS_REG_SPACING 4
-
-/** @name Timer 0 Register offsets
- *
- * @{
- */
-#define XUSBPS_TIMER0_LD_OFFSET 0x00000080
-#define XUSBPS_TIMER0_CTL_OFFSET 0x00000084
-/* @} */
-
-/** @name Timer Control Register bit mask
- *
- * @{
- */
-#define XUSBPS_TIMER_RUN_MASK 0x80000000
-#define XUSBPS_TIMER_STOP_MASK 0x80000000
-#define XUSBPS_TIMER_RESET_MASK 0x40000000
-#define XUSBPS_TIMER_REPEAT_MASK 0x01000000
-/* @} */
-
-/** @name Timer Control Register bit mask
- *
- * @{
- */
-#define XUSBPS_TIMER_COUNTER_MASK 0x00FFFFFF
-/* @} */
-
-/** @name Device Hardware Parameters
- *
- * @{
- */
-#define XUSBPS_HWDEVICE_OFFSET 0x0000000C
-
-#define XUSBPS_EP_NUM_MASK 0x3E
-#define XUSBPS_EP_NUM_SHIFT 1
-/* @} */
-
-/** @name Capability Register offsets
- */
-#define XUSBPS_HCSPARAMS_OFFSET 0x00000104
-
-/** @name Operational Register offsets.
- * Register comments are tagged with "H:" and "D:" for Host and Device modes,
- * respectively.
- * Tags are only present for registers that have a different meaning DEVICE and
- * HOST modes. Most registers are only valid for either DEVICE or HOST mode.
- * Those registers don't have tags.
- * @{
- */
-#define XUSBPS_CMD_OFFSET 0x00000140 /**< Configuration */
-#define XUSBPS_ISR_OFFSET 0x00000144 /**< Interrupt Status */
-#define XUSBPS_IER_OFFSET 0x00000148 /**< Interrupt Enable */
-#define XUSBPS_FRAME_OFFSET 0x0000014C /**< USB Frame Index */
-#define XUSBPS_LISTBASE_OFFSET 0x00000154 /**< H: Periodic List Base Address */
-#define XUSBPS_DEVICEADDR_OFFSET 0x00000154 /**< D: Device Address */
-#define XUSBPS_ASYNCLISTADDR_OFFSET 0x00000158 /**< H: Async List Address */
-#define XUSBPS_EPLISTADDR_OFFSET 0x00000158 /**< D: Endpoint List Addr */
-#define XUSBPS_TTCTRL_OFFSET 0x0000015C /**< TT Control */
-#define XUSBPS_BURSTSIZE_OFFSET 0x00000160 /**< Burst Size */
-#define XUSBPS_TXFILL_OFFSET 0x00000164 /**< Tx Fill Tuning */
-#define XUSBPS_ULPIVIEW_OFFSET 0x00000170 /**< ULPI Viewport */
-#define XUSBPS_EPNAKISR_OFFSET 0x00000178 /**< Endpoint NAK IRQ Status */
-#define XUSBPS_EPNAKIER_OFFSET 0x0000017C /**< Endpoint NAK IRQ Enable */
-#define XUSBPS_PORTSCR1_OFFSET 0x00000184 /**< Port Control/Status 1 */
-
-/* NOTE: The Port Control / Status Register index is 1-based. */
-#define XUSBPS_PORTSCRn_OFFSET(n) \
- (XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING))
-
-
-#define XUSBPS_OTGCSR_OFFSET 0x000001A4 /**< OTG Status and Control */
-#define XUSBPS_MODE_OFFSET 0x000001A8 /**< USB Mode */
-#define XUSBPS_EPSTAT_OFFSET 0x000001AC /**< Endpoint Setup Status */
-#define XUSBPS_EPPRIME_OFFSET 0x000001B0 /**< Endpoint Prime */
-#define XUSBPS_EPFLUSH_OFFSET 0x000001B4 /**< Endpoint Flush */
-#define XUSBPS_EPRDY_OFFSET 0x000001B8 /**< Endpoint Ready */
-#define XUSBPS_EPCOMPL_OFFSET 0x000001BC /**< Endpoint Complete */
-#define XUSBPS_EPCR0_OFFSET 0x000001C0 /**< Endpoint Control 0 */
-#define XUSBPS_EPCR1_OFFSET 0x000001C4 /**< Endpoint Control 1 */
-#define XUSBPS_EPCR2_OFFSET 0x000001C8 /**< Endpoint Control 2 */
-#define XUSBPS_EPCR3_OFFSET 0x000001CC /**< Endpoint Control 3 */
-#define XUSBPS_EPCR4_OFFSET 0x000001D0 /**< Endpoint Control 4 */
-
-#define XUSBPS_MAX_ENDPOINTS 12 /**< Number of supported Endpoints in
- * this core. */
-#define XUSBPS_EP_OUT_MASK 0x00000FFF /**< OUR (RX) endpoint mask */
-#define XUSBPS_EP_IN_MASK 0x0FFF0000 /**< IN (TX) endpoint mask */
-#define XUSBPS_EP_ALL_MASK 0x0FFF0FFF /**< Mask used for endpoint control
- * registers */
-#define XUSBPS_EPCRn_OFFSET(n) \
- (XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING))
-
-#define XUSBPS_EPFLUSH_RX_SHIFT 0
-#define XUSBPS_EPFLUSH_TX_SHIFT 16
-
-/* @} */
-
-
-
-/** @name Endpoint Control Register (EPCR) bit positions.
- * @{
- */
-
-/* Definitions for TX Endpoint bits */
-#define XUSBPS_EPCR_TXT_TYPE_SHIFT 18 /* < Endpoint Type - TX bit shift*/
-#define XUSBPS_EPCR_TXT_TYPE_MASK 0x000C0000 /* < Endpoint Type - TX read only*/
-#define XUSBPS_EPCR_TXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - TX */
-#define XUSBPS_EPCR_TXT_ISO_MASK 0x00040000 /**< Isochronous. Endpoint */
-#define XUSBPS_EPCR_TXT_BULK_MASK 0x00080000 /**< Bulk Endpoint - TX */
-#define XUSBPS_EPCR_TXT_INTR_MASK 0x000C0000 /**< Interrupt Endpoint */
-#define XUSBPS_EPCR_TXS_MASK 0x00010000 /**< Stall TX endpoint */
-#define XUSBPS_EPCR_TXE_MASK 0x00800000 /**< Transmit enable - TX */
-#define XUSBPS_EPCR_TXR_MASK 0x00400000 /**< Data Toggle Reset Bit */
-
-
-/* Definitions for RX Endpoint bits */
-#define XUSBPS_EPCR_RXT_TYPE_SHIFT 2 /* < Endpoint Type - RX bit shift*/
-#define XUSBPS_EPCR_RXT_TYPE_MASK 0x0000000C /**< Endpoint Type - RX read only*/
-#define XUSBPS_EPCR_RXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - RX */
-#define XUSBPS_EPCR_RXT_ISO_MASK 0x00000004 /**< Isochronous Endpoint */
-#define XUSBPS_EPCR_RXT_BULK_MASK 0x00000008 /**< Bulk Endpoint - RX */
-#define XUSBPS_EPCR_RXT_INTR_MASK 0x0000000C /**< Interrupt Endpoint */
-#define XUSBPS_EPCR_RXS_MASK 0x00000001 /**< Stall RX endpoint. */
-#define XUSBPS_EPCR_RXE_MASK 0x00000080 /**< Transmit enable. - RX */
-#define XUSBPS_EPCR_RXR_MASK 0x00000040 /**< Data Toggle Reset Bit */
-/* @} */
-
-
-/** @name USB Command Register (CR) bit positions.
- * @{
- */
-#define XUSBPS_CMD_RS_MASK 0x00000001 /**< Run/Stop */
-#define XUSBPS_CMD_RST_MASK 0x00000002 /**< Controller RESET */
-#define XUSBPS_CMD_FS01_MASK 0x0000000C /**< Frame List Size bit 0,1 */
-#define XUSBPS_CMD_PSE_MASK 0x00000010 /**< Periodic Sched Enable */
-#define XUSBPS_CMD_ASE_MASK 0x00000020 /**< Async Sched Enable */
-#define XUSBPS_CMD_IAA_MASK 0x00000040 /**< IRQ Async Advance Doorbell */
-#define XUSBPS_CMD_ASP_MASK 0x00000300 /**< Async Sched Park Mode Cnt */
-#define XUSBPS_CMD_ASPE_MASK 0x00000800 /**< Async Sched Park Mode Enbl */
-#define XUSBPS_CMD_SUTW_MASK 0x00002000 /**< Setup TripWire */
-#define XUSBPS_CMD_ATDTW_MASK 0x00004000 /**< Add dTD TripWire */
-#define XUSBPS_CMD_FS2_MASK 0x00008000 /**< Frame List Size bit 2 */
-#define XUSBPS_CMD_ITC_MASK 0x00FF0000 /**< IRQ Threshold Control */
-/* @} */
-
-
-/**
- * @name Interrupt Threshold
- * These definitions are used by software to set the maximum rate at which the
- * USB controller will generate interrupt requests. The interrupt interval is
- * given in number of micro-frames.
- *
- * USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF)
- * packet each and every 1ms. USB also defines a high-speed micro-frame with a
- * 125us frame time. For each micro-frame a SOF (Start Of Frame) packet is
- * generated. Data is sent in between the SOF packets. The interrupt threshold
- * defines how many micro-frames the controller waits before issuing an
- * interrupt after data has been received.
- *
- * For a threshold of 0 the controller will issue an interrupt immediately
- * after the last byte of the data has been received. For a threshold n>0 the
- * controller will wait for n micro-frames before issuing an interrupt.
- *
- * Therefore, a setting of 8 micro-frames (default) means that the controller
- * will issue at most 1 interrupt per millisecond.
- *
- * @{
- */
-#define XUSBPS_CMD_ITHRESHOLD_0 0x00 /**< Immediate interrupt. */
-#define XUSBPS_CMD_ITHRESHOLD_1 0x01 /**< 1 micro-frame */
-#define XUSBPS_CMD_ITHRESHOLD_2 0x02 /**< 2 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_4 0x04 /**< 4 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_8 0x08 /**< 8 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_16 0x10 /**< 16 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_32 0x20 /**< 32 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_64 0x40 /**< 64 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_MAX XUSBPS_CMD_ITHRESHOLD_64
-#define XUSBPS_CMD_ITHRESHOLD_DEFAULT XUSBPS_CMD_ITHRESHOLD_8
-/* @} */
-
-
-
-/** @name USB Interrupt Status Register (ISR) / Interrupt Enable Register (IER)
- * bit positions.
- * @{
- */
-#define XUSBPS_IXR_UI_MASK 0x00000001 /**< USB Transaction Complete */
-#define XUSBPS_IXR_UE_MASK 0x00000002 /**< Transaction Error */
-#define XUSBPS_IXR_PC_MASK 0x00000004 /**< Port Change Detect */
-#define XUSBPS_IXR_FRE_MASK 0x00000008 /**< Frame List Rollover */
-#define XUSBPS_IXR_AA_MASK 0x00000020 /**< Async Advance */
-#define XUSBPS_IXR_UR_MASK 0x00000040 /**< RESET Received */
-#define XUSBPS_IXR_SR_MASK 0x00000080 /**< Start of Frame */
-#define XUSBPS_IXR_SLE_MASK 0x00000100 /**< Device Controller Suspend */
-#define XUSBPS_IXR_ULPI_MASK 0x00000400 /**< ULPI IRQ */
-#define XUSBPS_IXR_HCH_MASK 0x00001000 /**< Host Controller Halted
- * Read Only */
-#define XUSBPS_IXR_RCL_MASK 0x00002000 /**< USB Reclamation Read Only */
-#define XUSBPS_IXR_PS_MASK 0x00004000 /**< Periodic Sched Status
- * Read Only */
-#define XUSBPS_IXR_AS_MASK 0x00008000 /**< Async Sched Status Read only */
-#define XUSBPS_IXR_NAK_MASK 0x00010000 /**< NAK IRQ */
-#define XUSBPS_IXR_UA_MASK 0x00040000 /**< USB Host Async IRQ */
-#define XUSBPS_IXR_UP_MASK 0x00080000 /**< USB Host Periodic IRQ */
-#define XUSBPS_IXR_TI0_MASK 0x01000000 /**< Timer 0 Interrupt */
-#define XUSBPS_IXR_TI1_MASK 0x02000000 /**< Timer 1 Interrupt */
-
-#define XUSBPS_IXR_ALL (XUSBPS_IXR_UI_MASK | \
- XUSBPS_IXR_UE_MASK | \
- XUSBPS_IXR_PC_MASK | \
- XUSBPS_IXR_FRE_MASK | \
- XUSBPS_IXR_AA_MASK | \
- XUSBPS_IXR_UR_MASK | \
- XUSBPS_IXR_SR_MASK | \
- XUSBPS_IXR_SLE_MASK | \
- XUSBPS_IXR_ULPI_MASK | \
- XUSBPS_IXR_HCH_MASK | \
- XUSBPS_IXR_RCL_MASK | \
- XUSBPS_IXR_PS_MASK | \
- XUSBPS_IXR_AS_MASK | \
- XUSBPS_IXR_NAK_MASK | \
- XUSBPS_IXR_UA_MASK | \
- XUSBPS_IXR_UP_MASK | \
- XUSBPS_IXR_TI0_MASK | \
- XUSBPS_IXR_TI1_MASK)
- /**< Mask for ALL IRQ types */
-/* @} */
-
-
-/** @name USB Mode Register (MODE) bit positions.
- * @{
- */
-#define XUSBPS_MODE_CM_MASK 0x00000003 /**< Controller Mode Select */
-#define XUSBPS_MODE_CM_IDLE_MASK 0x00000000
-#define XUSBPS_MODE_CM_DEVICE_MASK 0x00000002
-#define XUSBPS_MODE_CM_HOST_MASK 0x00000003
-#define XUSBPS_MODE_ES_MASK 0x00000004 /**< USB Endian Select */
-#define XUSBPS_MODE_SLOM_MASK 0x00000008 /**< USB Setup Lockout Mode Disable */
-#define XUSBPS_MODE_SDIS_MASK 0x00000010
-#define XUSBPS_MODE_VALID_MASK 0x0000001F
-
-/* @} */
-
-
-/** @name USB Device Address Register (DEVICEADDR) bit positions.
- * @{
- */
-#define XUSBPS_DEVICEADDR_DEVICEAADV_MASK 0x01000000
- /**< Device Addr Auto Advance */
-#define XUSBPS_DEVICEADDR_ADDR_MASK 0xFE000000
- /**< Device Address */
-#define XUSBPS_DEVICEADDR_ADDR_SHIFT 25
- /**< Address shift */
-#define XUSBPS_DEVICEADDR_MAX 127
- /**< Biggest allowed address */
-/* @} */
-
-/** @name USB TT Control Register (TTCTRL) bit positions.
- * @{
- */
-#define XUSBPS_TTCTRL_HUBADDR_MASK 0x7F000000 /**< TT Hub Address */
-/* @} */
-
-
-/** @name USB Burst Size Register (BURSTSIZE) bit posisions.
- * @{
- */
-#define XUSBPS_BURSTSIZE_RX_MASK 0x000000FF /**< RX Burst Length */
-#define XUSBPS_BURSTSIZE_TX_MASK 0x0000FF00 /**< TX Burst Length */
-/* @} */
-
-
-/** @name USB Tx Fill Tuning Register (TXFILL) bit positions.
- * @{
- */
-#define XUSBPS_TXFILL_OVERHEAD_MASK 0x000000FF
- /**< Scheduler Overhead */
-#define XUSBPS_TXFILL_HEALTH_MASK 0x00001F00
- /**< Scheduler Health Cntr */
-#define XUSBPS_TXFILL_BURST_MASK 0x003F0000
- /**< FIFO Burst Threshold */
-/* @} */
-
-
-/** @name USB ULPI Viewport Register (ULPIVIEW) bit positions.
- * @{
- */
-#define XUSBPS_ULPIVIEW_DATWR_MASK 0x000000FF /**< ULPI Data Write */
-#define XUSBPS_ULPIVIEW_DATRD_MASK 0x0000FF00 /**< ULPI Data Read */
-#define XUSBPS_ULPIVIEW_ADDR_MASK 0x00FF0000 /**< ULPI Data Address */
-#define XUSBPS_ULPIVIEW_PORT_MASK 0x07000000 /**< ULPI Port Number */
-#define XUSBPS_ULPIVIEW_SS_MASK 0x08000000 /**< ULPI Synchronous State */
-#define XUSBPS_ULPIVIEW_RW_MASK 0x20000000 /**< ULPI Read/Write Control */
-#define XUSBPS_ULPIVIEW_RUN_MASK 0x40000000 /**< ULPI Run */
-#define XUSBPS_ULPIVIEW_WU_MASK 0x80000000 /**< ULPI Wakeup */
-/* @} */
-
-
-/** @name Port Status Control Register bit positions.
- * @{
- */
-#define XUSBPS_PORTSCR_CCS_MASK 0x00000001 /**< Current Connect Status */
-#define XUSBPS_PORTSCR_CSC_MASK 0x00000002 /**< Connect Status Change */
-#define XUSBPS_PORTSCR_PE_MASK 0x00000004 /**< Port Enable/Disable */
-#define XUSBPS_PORTSCR_PEC_MASK 0x00000008 /**< Port Enable/Disable Change */
-#define XUSBPS_PORTSCR_OCA_MASK 0x00000010 /**< Over-current Active */
-#define XUSBPS_PORTSCR_OCC_MASK 0x00000020 /**< Over-current Change */
-#define XUSBPS_PORTSCR_FPR_MASK 0x00000040 /**< Force Port Resume */
-#define XUSBPS_PORTSCR_SUSP_MASK 0x00000080 /**< Suspend */
-#define XUSBPS_PORTSCR_PR_MASK 0x00000100 /**< Port Reset */
-#define XUSBPS_PORTSCR_HSP_MASK 0x00000200 /**< High Speed Port */
-#define XUSBPS_PORTSCR_LS_MASK 0x00000C00 /**< Line Status */
-#define XUSBPS_PORTSCR_PP_MASK 0x00001000 /**< Port Power */
-#define XUSBPS_PORTSCR_PO_MASK 0x00002000 /**< Port Owner */
-#define XUSBPS_PORTSCR_PIC_MASK 0x0000C000 /**< Port Indicator Control */
-#define XUSBPS_PORTSCR_PTC_MASK 0x000F0000 /**< Port Test Control */
-#define XUSBPS_PORTSCR_WKCN_MASK 0x00100000 /**< Wake on Connect Enable */
-#define XUSBPS_PORTSCR_WKDS_MASK 0x00200000 /**< Wake on Disconnect Enable */
-#define XUSBPS_PORTSCR_WKOC_MASK 0x00400000 /**< Wake on Over-current Enable */
-#define XUSBPS_PORTSCR_PHCD_MASK 0x00800000 /**< PHY Low Power Suspend -
- * Clock Disable */
-#define XUSBPS_PORTSCR_PFSC_MASK 0x01000000 /**< Port Force Full Speed
- * Connect */
-#define XUSBPS_PORTSCR_PSPD_MASK 0x0C000000 /**< Port Speed */
-/* @} */
-
-
-/** @name On-The-Go Status Control Register (OTGCSR) bit positions.
- * @{
- */
-#define XUSBPS_OTGSC_VD_MASK 0x00000001 /**< VBus Discharge Bit */
-#define XUSBPS_OTGSC_VC_MASK 0x00000002 /**< VBus Charge Bit */
-#define XUSBPS_OTGSC_HAAR_MASK 0x00000004 /**< HW Assist Auto Reset
- * Enable Bit */
-#define XUSBPS_OTGSC_OT_MASK 0x00000008 /**< OTG Termination Bit */
-#define XUSBPS_OTGSC_DP_MASK 0x00000010 /**< Data Pulsing Pull-up
- * Enable Bit */
-#define XUSBPS_OTGSC_IDPU_MASK 0x00000020 /**< ID Pull-up Enable Bit */
-#define XUSBPS_OTGSC_HADP_MASK 0x00000040 /**< HW Assist Data Pulse
- * Enable Bit */
-#define XUSBPS_OTGSC_HABA_MASK 0x00000080 /**< USB Hardware Assist
- * B Disconnect to A
- * Connect Enable Bit */
-#define XUSBPS_OTGSC_ID_MASK 0x00000100 /**< ID Status Flag */
-#define XUSBPS_OTGSC_AVV_MASK 0x00000200 /**< USB A VBus Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_ASV_MASK 0x00000400 /**< USB A Session Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_BSV_MASK 0x00000800 /**< USB B Session Valid Status Flag */
-#define XUSBPS_OTGSC_BSE_MASK 0x00001000 /**< USB B Session End Status Flag */
-#define XUSBPS_OTGSC_1MST_MASK 0x00002000 /**< USB 1 Millisecond Timer Status Flag */
-#define XUSBPS_OTGSC_DPS_MASK 0x00004000 /**< Data Pulse Status Flag */
-#define XUSBPS_OTGSC_IDIS_MASK 0x00010000 /**< USB ID Interrupt Status Flag */
-#define XUSBPS_OTGSC_AVVIS_MASK 0x00020000 /**< USB A VBus Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_ASVIS_MASK 0x00040000 /**< USB A Session Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_BSVIS_MASK 0x00080000 /**< USB B Session Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_BSEIS_MASK 0x00100000 /**< USB B Session End Interrupt Status Flag */
-#define XUSBPS_OTGSC_1MSS_MASK 0x00200000 /**< 1 Millisecond Timer Interrupt Status Flag */
-#define XUSBPS_OTGSC_DPIS_MASK 0x00400000 /**< Data Pulse Interrupt Status Flag */
-#define XUSBPS_OTGSC_IDIE_MASK 0x01000000 /**< ID Interrupt Enable Bit */
-#define XUSBPS_OTGSC_AVVIE_MASK 0x02000000 /**< USB A VBus Valid Interrupt Enable Bit */
-#define XUSBPS_OTGSC_ASVIE_MASK 0x04000000 /**< USB A Session Valid Interrupt Enable Bit */
-#define XUSBPS_OTGSC_BSVIE_MASK 0x08000000 /**< USB B Session Valid Interrupt Enable Bit */
-#define XUSBPS_OTGSC_BSEE_MASK 0x10000000 /**< USB B Session End Interrupt Enable Bit */
-#define XUSBPS_OTGSC_1MSE_MASK 0x20000000 /**< 1 Millisecond Timer
- * Interrupt Enable Bit */
-#define XUSBPS_OTGSC_DPIE_MASK 0x40000000 /**< Data Pulse Interrupt
- * Enable Bit */
-
-#define XUSBPS_OTG_ISB_ALL (XUSBPS_OTGSC_IDIS_MASK |\
- XUSBPS_OTGSC_AVVIS_MASK | \
- XUSBPS_OTGSC_ASVIS_MASK | \
- XUSBPS_OTGSC_BSVIS_MASK | \
- XUSBPS_OTGSC_BSEIS_MASK | \
- XUSBPS_OTGSC_1MSS_MASK | \
- XUSBPS_OTGSC_DPIS_MASK)
- /** Mask for All IRQ status masks */
-
-#define XUSBPS_OTG_IEB_ALL (XUSBPS_OTGSC_IDIE_MASK |\
- XUSBPS_OTGSC_AVVIE_MASK | \
- XUSBPS_OTGSC_ASVIE_MASK | \
- XUSBPS_OTGSC_BSVIE_MASK | \
- XUSBPS_OTGSC_BSEE_IEB_MASK | \
- XUSBPS_OTGSC_1MSE_MASK | \
- XUSBPS_OTGSC_DPIE_MASK)
- /** Mask for All IRQ Enable masks */
-/* @} */
-
-
-/**< Alignment of the Device Queue Head List BASE. */
-#define XUSBPS_dQH_BASE_ALIGN 2048
-
-/**< Alignment of a Device Queue Head structure. */
-#define XUSBPS_dQH_ALIGN 64
-
-/**< Alignment of a Device Transfer Descriptor structure. */
-#define XUSBPS_dTD_ALIGN 32
-
-/**< Size of one RX buffer for a OUT Transfer Descriptor. */
-#define XUSBPS_dTD_BUF_SIZE 4096
-
-/**< Maximum size of one RX/TX buffer. */
-#define XUSBPS_dTD_BUF_MAX_SIZE 16*1024
-
-/**< Alignment requirement for Transfer Descriptor buffers. */
-#define XUSBPS_dTD_BUF_ALIGN 4096
-
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* This macro reads the given register.
-*
-* @param BaseAddress is the base address for the USB registers.
-* @param RegOffset is the register offset to be read.
-*
-* @return The 32-bit value of the register.
-*
-* @note C-style signature:
-* u32 XUsbPs_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XUsbPs_ReadReg(BaseAddress, RegOffset) \
- Xil_In32(BaseAddress + (RegOffset))
-
-
-/****************************************************************************/
-/**
-*
-* This macro writes the given register.
-*
-* @param BaseAddress is the the base address for the USB registers.
-* @param RegOffset is the register offset to be written.
-* @param Data is the the 32-bit value to write to the register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XUsbPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
- *****************************************************************************/
-#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data) \
- Xil_Out32(BaseAddress + (RegOffset), (Data))
-
-
-/************************** Function Prototypes ******************************/
-/*
- * Perform reset operation to the USB PS interface
- */
-void XUsbPs_ResetHw(u32 BaseAddress);
-/************************** Variable Definitions ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XUSBPS_L_H */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cf/d0291f585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cf/d0291f585243001d18b399c1eb9b3628
deleted file mode 100644
index 4b6d75a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cf/d0291f585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,261 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xscutimer_hw.h
-* @addtogroup scutimer_v2_3
-* @{
-*
-* This file contains the hardware interface to the Timer.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm 03/10/10 First release
-* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
-* and interrupt registers
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-#ifndef XSCUTIMER_HW_H /* prevent circular inclusions */
-#define XSCUTIMER_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- * Offsets of registers from the start of the device
- * @{
- */
-
-#define XSCUTIMER_LOAD_OFFSET 0x00U /**< Timer Load Register */
-#define XSCUTIMER_COUNTER_OFFSET 0x04U /**< Timer Counter Register */
-#define XSCUTIMER_CONTROL_OFFSET 0x08U /**< Timer Control Register */
-#define XSCUTIMER_ISR_OFFSET 0x0CU /**< Timer Interrupt
- Status Register */
-/* @} */
-
-/** @name Timer Control register
- * This register bits control the prescaler, Intr enable,
- * auto-reload and timer enable.
- * @{
- */
-
-#define XSCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
-#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8U
-#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004U /**< Intr enable */
-#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload */
-#define XSCUTIMER_CONTROL_ENABLE_MASK 0x00000001U /**< Timer enable */
-/* @} */
-
-/** @name Interrupt Status register
- * This register indicates the Timer counter register has reached zero.
- * @{
- */
-
-#define XSCUTIMER_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Write to the timer load register. This will also update the
-* timer counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetLoadReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer load register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer load register.
-*
-* @note C-style signature:
-* u32 XScuTimer_GetLoadReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetLoadReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the timer counter register.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the counter register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetCounterReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer counter register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer counter register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetCounterReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetCounterReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the timer load register. This will also update the
-* timer counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetControlReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer load register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer load register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetControlReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetControlReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the timer counter register.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the counter register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetIntrReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer counter register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer counter register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetIntrReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetIntrReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Read from the given Timer register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note C-style signature:
-* u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuTimer_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + (RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write to the given Timer register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + (RegOffset), (Data))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cf/d2ba6f585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cf/d2ba6f585243001d18b399c1eb9b3628
deleted file mode 100644
index cbec306..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/cf/d2ba6f585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,420 +0,0 @@
-/*
- ****************************************************************************
- * (C) 2006 - Grzegorz Milos - Cambridge University
- ****************************************************************************
- *
- * File: console.h
- * Author: Grzegorz Milos
- * Changes:
- *
- * Date: Mar 2006
- *
- * Environment: Xen Minimal OS
- * Description: Console interface.
- *
- * Handles console I/O. Defines printk.
- *
- ****************************************************************************
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-/*
-Copyright DornerWorks 2016
-
-Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-following conditions are met:
-1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
-following disclaimer.
-
-THIS SOFTWARE IS PROVIDED BY DORNERWORKS FOR USE ON THE CONTRACTED PROJECT, AND ANY EXPRESS OR IMPLIED WARRANTY
-IS LIMITED TO THIS USE. FOR ALL OTHER USES THIS SOFTWARE IS PROVIDED ''AS IS'' AND ANY EXPRESS OR IMPLIED
-WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL DORNERWORKS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-#include
-#include
-#include
-#include
-#include "hypercall.h"
-#include "arm64_ops.h"
-#include "xen.h"
-#include "xen_console.h"
-#include "xen_events.h"
-
-#define ECHO_TO_UART 1
-#define SUCCESS 0
-#define ARG_NULL -1
-#define INIT_FAILED -2
-#define INIT_NOT_DONE -3
-#define BUFFER_OVERFLOW -4
-#define PRINT_FAILED -5
-
-#define PAGE_TO_ADDR(x) ((void*)((u64)(x)<out_cons;
- prod = intf->out_prod;
- mb();
- BUG_ON((prod - cons) > sizeof(intf->out));
-
- while ((sent < len) && ((prod - cons) < sizeof(intf->out)))
- {
- intf->out[MASK_XENCONS_IDX(prod++, intf->out)] = data[sent++];
- }
- wmb();
- intf->out_prod = prod;
-
- return sent;
-}
-
-// Copies the characters then raises an event to Xen
-static int xencons_ring_send(const u8 *data, unsigned len)
-{
- int sent;
-
- sent = xencons_ring_send_no_notify(data, len);
- notify_evtch(cons_evtch);
-
- return sent;
-}
-
-// Does some data reformatting to handle newline
-static void console_print(char *data, int length)
-{
- u8 *curr_char, saved_char;
- u8 copied_str[length+1];
- u8 *copied_ptr;
- int part_len;
- int (*ring_send_fn)(const u8 *data, unsigned length);
-
- if(!console_initialised)
- ring_send_fn = xencons_ring_send_no_notify;
- else
- ring_send_fn = xencons_ring_send;
-
- copied_ptr = copied_str;
- memcpy(copied_ptr, data, length);
-
- for(curr_char = copied_ptr; curr_char < copied_ptr+length-1; curr_char++)
- {
- if(*curr_char == '\n')
- {
- *curr_char = '\r';
- saved_char = *(curr_char+1);
- *(curr_char+1) = '\n';
- part_len = curr_char - copied_ptr + 2;
- ring_send_fn(copied_ptr, part_len);
- *(curr_char+1) = saved_char;
- copied_ptr = curr_char+1;
- length -= part_len - 1;
- }
- }
-
- if (copied_ptr[length-1] == '\n') {
- copied_ptr[length-1] = '\r';
- copied_ptr[length] = '\n';
- length++;
- }
-
- ring_send_fn(copied_ptr, length);
-}
-
-// This function will print to Xen's console one way or another
-static void pvc_print(int direct, const char *fmt, va_list args)
-{
- static char buf[1024];
-
- (void)vsnprintf(buf, sizeof(buf), fmt, args);
-
- if(direct)
- {
- // if console ring buffer/event not ready, use the Xen console IO hypercall
- (void)HYPERVISOR_console_io(CONSOLEIO_write, strlen(buf), buf);
- }
- else
- {
- console_print(buf, strlen(buf));
- }
-}
-
-// Use this function to print to the Xen console
-void printk(const char *fmt, ...)
-{
- va_list args;
- va_start(args, fmt);
- pvc_print(console_initialised!=1, fmt, args);
- va_end(args);
-}
-
-
-// Register this function with event handler to take care of console events
-static void console_handle_input(void)
-{
- struct xencons_interface *intf = mfn_to_virt(guest_phys_page);
- u32 cons, prod;
- u8 byte;
- static int cr = 0;
- char data[sizeof(intf->in)+1] = {0};
- int i;
-
-
- cons = intf->in_cons;
- prod = intf->in_prod;
- mb();
- BUG_ON((prod - cons) > sizeof(intf->in));
-
- i = 0;
- while (cons != prod)
- {
- byte = *(intf->in+MASK_XENCONS_IDX(cons,intf->in));
- cons++;
- data[i++] = byte;
- }
-
- mb();
- intf->in_cons = cons;
- notify_evtch(cons_evtch);
- console_input_callback(data, i);
-}
-
-// Initializes the Xen virtual console
-void init_console(void)
-{
- u64 val;
- int rv;
-
- init_events();
-
- // get the page where the console ring buffer is
- if(0 == get_hv_param(HVM_PARAM_CONSOLE_PFN, &val))
- {
- guest_phys_page = val;
- }
-
- // get event channel info necessary to do the things
- if(0 == get_hv_param(HVM_PARAM_CONSOLE_EVTCHN, &val))
- {
- cons_evtch = val;
- register_event_handler(cons_evtch, console_handle_input);
- }
- else
- {
- printk("error getting console event channel ID\r\n");
- }
-
- unmask_evtchn(cons_evtch);
- console_initialised = 1;
-}
-void XPVXenConsole_Init()
-{
- init_console();
-}
-/*****************************************************************************/
-/**
- *
- * @brief This function writes data to xen console output ring buffer &
- * sends event notification to xen
- *
- * @param BufferPtr: Pointer to buffer data to be written/copied to xen
- * console output ring buffer
- *
- * @return
- * Length: if data written to xen console output buffer successfully
- * BUFFER_OVERFLOW: if xen console output buffer overflow
- *
- ******************************************************************************/
- int XPVXenConsole_Write(const char *BufferPtr) {
- u32 Length = 0;
- u32 RingIndex = 0;
- struct xencons_interface *ConsoleInterfacePtr = mfn_to_virt(guest_phys_page);
- u32 Cons = ConsoleInterfacePtr->out_cons;
- u32 Prod = ConsoleInterfacePtr->out_prod;
-
- /*
- * It guarantees that any memory access initiated before the memory
- * barrier will be complete before passing the barrier, and all
- * subsequent memory accesses will be executed after the barrier
- */
- mb();
- if ((Prod - Cons) > sizeof(ConsoleInterfacePtr->out)) {
- notify_evtch(cons_evtch);
- return BUFFER_OVERFLOW;
- }
- /*
- * write buffer data into xen console output ring buffer,
- * taking care not to overflow the console output ring buffer
- */
- while ((*BufferPtr != '\0') &&
- ((Prod - Cons) < sizeof(ConsoleInterfacePtr->out))) {
- RingIndex = MASK_XENCONS_IDX(Prod, ConsoleInterfacePtr->out);
- ConsoleInterfacePtr->out[RingIndex] = *BufferPtr++;
- Prod++;
- Length++;
- }
- /*
- * make sure that data written into xen console output ring buffer
- * before updating the pointer
- */
- wmb();
- ConsoleInterfacePtr->out_prod = Prod;
- notify_evtch(cons_evtch);
-
- return Length;
-}
-/*****************************************************************************/
-/**
- *
- * @brief This API is used to print data on xen console
- *
- * @param FormatPtr: Pointer to format/string to be printed on xen console
- *
- * @return
- * SUCCESS: if xen console printed data successfully
- * INIT_NOT_DONE: if xen console initialization not done
- * ARG_NULL: if null argument passed to function
- * BUFFER_OVERFLOW: if print buffer overflow
- * PRINT_FAILED: if xen console printed data failed
- *
- ******************************************************************************/
-int XPVXenConsole_Printf(const char *FormatPtr, ...) {
- va_list Args;
- struct xencons_interface *ConsoleInterfacePtr = mfn_to_virt(guest_phys_page);
- static char Buf[sizeof(ConsoleInterfacePtr->out) + 1] = { 0 };
- u32 Ret = 0;
- int Length = 0;
-
- if (ConsoleInterfacePtr == NULL) {
- return INIT_NOT_DONE;
- }
- if (FormatPtr == NULL) {
- return ARG_NULL;
- }
-
- va_start(Args, FormatPtr);
- Ret = vsnprintf(Buf, sizeof(Buf), FormatPtr, Args);
- va_end(Args);
- if (Ret > (u32) sizeof(Buf)) {
- return BUFFER_OVERFLOW;
- }
-
- Length = XPVXenConsole_Write(Buf);
- if (Length < 0) {
- return PRINT_FAILED;
- }
-
- return SUCCESS;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d/407acb595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d/407acb595243001d18b399c1eb9b3628
deleted file mode 100644
index 27a10ad..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d/407acb595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,425 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xuartps_hw.h
-* @addtogroup uartps_v3_11
-* @{
-*
-* This header file contains the hardware interface of an XUartPs device.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00 drg/jz 01/12/10 First Release
-* 1.03a sg 09/04/12 Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
-* and XUARTPS_IXR_TTRIG.
-* Modified the names of these defines
-* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
-* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
-* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
-* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
-* 1.05a hk 08/22/13 Added prototype for uart reset and related
-* constant definitions.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
-* 3.6 ms 02/16/18 Updates flow control mode offset value in
-* modem control register.
-*
-*
-*
-******************************************************************************/
-#ifndef XUARTPS_HW_H /* prevent circular inclusions */
-#define XUARTPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets for the UART.
- * @{
- */
-#define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */
-#define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */
-#define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */
-#define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */
-#define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */
-#define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/
-#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */
-#define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */
-#define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */
-#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */
-#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */
-#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */
-#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */
-#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */
-#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */
-#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */
-#define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */
-/* @} */
-
-/** @name Control Register
- *
- * The Control register (CR) controls the major functions of the device.
- *
- * Control Register Bit Definition
- */
-
-#define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */
-#define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */
-#define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */
-#define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */
-#define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */
-#define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */
-#define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */
-#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */
-#define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */
-#define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */
-/* @}*/
-
-
-/** @name Mode Register
- *
- * The mode register (MR) defines the mode of transfer as well as the data
- * format. If this register is modified during transmission or reception,
- * data validity cannot be guaranteed.
- *
- * Mode Register Bit Definition
- * @{
- */
-#define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */
-#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */
-#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */
-#define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */
-#define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */
-#define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */
-#define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */
-#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */
-#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */
-#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */
-#define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */
-#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */
-#define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */
-#define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */
-#define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */
-#define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */
-#define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */
-#define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */
-#define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */
-#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */
-#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */
-#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */
-#define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */
-#define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */
-#define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */
-/* @} */
-
-
-/** @name Interrupt Registers
- *
- * Interrupt control logic uses the interrupt enable register (IER) and the
- * interrupt disable register (IDR) to set the value of the bits in the
- * interrupt mask register (IMR). The IMR determines whether to pass an
- * interrupt to the interrupt status register (ISR).
- * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
- * interrupt. IMR and ISR are read only, and IER and IDR are write only.
- * Reading either IER or IDR returns 0x00.
- *
- * All four registers have the same bit definitions.
- *
- * @{
- */
-#define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */
-#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */
-#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */
-#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */
-#define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */
-#define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */
-#define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */
-#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */
-#define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */
-#define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */
-#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */
-#define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */
-#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */
-#define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */
-#define XUARTPS_IXR_MASK 0x00003FFFU /**< Valid bit mask */
-/* @} */
-
-
-/** @name Baud Rate Generator Register
- *
- * The baud rate generator control register (BRGR) is a 16 bit register that
- * controls the receiver bit sample clock and baud rate.
- * Valid values are 1 - 65535.
- *
- * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
- * in the MR register.
- * @{
- */
-#define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */
-#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */
-#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */
-
-/** @name Baud Divisor Rate register
- *
- * The baud rate divider register (BDIV) controls how much the bit sample
- * rate is divided by. It sets the baud rate.
- * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
- *
- * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
- * the MR_CCLK bit in the MR register.
- * @{
- */
-#define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */
-#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */
-/* @} */
-
-
-/** @name Receiver Timeout Register
- *
- * Use the receiver timeout register (RTR) to detect an idle condition on
- * the receiver data line.
- *
- * @{
- */
-#define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */
-#define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */
-
-/** @name Receiver FIFO Trigger Level Register
- *
- * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
- * which the RX FIFO triggers an interrupt event.
- * @{
- */
-
-#define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */
-#define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */
-#define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */
-/* @} */
-
-/** @name Transmit FIFO Trigger Level Register
- *
- * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
- * which the TX FIFO triggers an interrupt event.
- * @{
- */
-
-#define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */
-#define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */
-/* @} */
-
-/** @name Modem Control Register
- *
- * This register (MODEMCR) controls the interface with the modem or data set,
- * or a peripheral device emulating a modem.
- *
- * @{
- */
-#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */
-#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */
-#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */
-/* @} */
-
-/** @name Modem Status Register
- *
- * This register (MODEMSR) indicates the current state of the control lines
- * from a modem, or another peripheral device, to the CPU. In addition, four
- * bits of the modem status register provide change information. These bits
- * are set to a logic 1 whenever a control input from the modem changes state.
- *
- * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
- * status interrupt is generated and this is reflected in the modem status
- * register.
- *
- * @{
- */
-#define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */
-#define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */
-#define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */
-#define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */
-#define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */
-#define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */
-#define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */
-#define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */
-#define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */
-/* @} */
-
-/** @name Channel Status Register
- *
- * The channel status register (CSR) is provided to enable the control logic
- * to monitor the status of bits in the channel interrupt status register,
- * even if these are masked out by the interrupt mask register.
- *
- * @{
- */
-#define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */
-#define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */
-#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */
-#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */
-#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */
-#define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */
-#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */
-#define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */
-#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */
-#define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */
-/* @} */
-
-/** @name Flow Delay Register
- *
- * Operation of the flow delay register (FLOWDEL) is very similar to the
- * receive FIFO trigger register. An internal trigger signal activates when the
- * FIFO is filled to the level set by this register. This trigger will not
- * cause an interrupt, although it can be read through the channel status
- * register. In hardware flow control mode, RTS is deactivated when the trigger
- * becomes active. RTS only resets when the FIFO level is four less than the
- * level of the flow delay trigger and the flow delay trigger is not activated.
- * A value less than 4 disables the flow delay.
- * @{
- */
-#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */
-/* @} */
-
-/** @name Receiver FIFO Byte Status Register
- *
- * The Receiver FIFO Status register is used to have a continuous
- * monitoring of the raw unmasked byte status information. The register
- * contains frame, parity and break status information for the top
- * four bytes in the RX FIFO.
- *
- * Receiver FIFO Byte Status Register Bit Definition
- * @{
- */
-#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /**< Byte3 Break Error */
-#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /**< Byte3 Frame Error */
-#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /**< Byte3 Parity Error */
-#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /**< Byte2 Break Error */
-#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /**< Byte2 Frame Error */
-#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /**< Byte2 Parity Error */
-#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /**< Byte1 Break Error */
-#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /**< Byte1 Frame Error */
-#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /**< Byte1 Parity Error */
-#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /**< Byte0 Break Error */
-#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /**< Byte0 Frame Error */
-#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /**< Byte0 Parity Error */
-#define XUARTPS_RXBS_MASK 0x00000007U /**< 3 bit RX byte status mask */
-/* @} */
-
-
-/*
- * Defines for backwards compatibility, will be removed
- * in the next version of the driver
- */
-#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD
-#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI
-#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR
-#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS
-
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-* Read a UART register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the base address of the
-* device.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
-*
-******************************************************************************/
-#define XUartPs_ReadReg(BaseAddress, RegOffset) \
- Xil_In32((BaseAddress) + (u32)(RegOffset))
-
-/***************************************************************************/
-/**
-* Write a UART register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the base address of the
-* device.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u16 RegisterValue)
-*
-******************************************************************************/
-#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
-
-/****************************************************************************/
-/**
-* Determine if there is receive data in the receiver and/or FIFO.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return TRUE if there is receive data, FALSE otherwise.
-*
-* @note C-Style signature:
-* u32 XUartPs_IsReceiveData(u32 BaseAddress)
-*
-******************************************************************************/
-#define XUartPs_IsReceiveData(BaseAddress) \
- !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
- (u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
-
-/****************************************************************************/
-/**
-* Determine if a byte of data can be sent with the transmitter.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the
-* FIFO.
-*
-* @note C-Style signature:
-* u32 XUartPs_IsTransmitFull(u32 BaseAddress)
-*
-******************************************************************************/
-#define XUartPs_IsTransmitFull(BaseAddress) \
- ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \
- (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
-
-/************************** Function Prototypes ******************************/
-
-void XUartPs_SendByte(u32 BaseAddress, u8 Data);
-
-u8 XUartPs_RecvByte(u32 BaseAddress);
-
-void XUartPs_ResetHw(u32 BaseAddress);
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d/90528a595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d/90528a595243001d18b399c1eb9b3628
deleted file mode 100644
index 4e3a872..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d/90528a595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,145 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include "profile.h"
-#include "_profile_timer_hw.h"
-#ifdef PROC_MICROBLAZE
-#include "mblaze_nt_types.h"
-#endif
-
-/*
- * The mcount function is excluded from the library, if the user defines
- * PROFILE_NO_GRAPH.
- */
-#ifndef PROFILE_NO_GRAPH
-
-#include
-#include
-#include
-
-#ifdef PROFILE_NO_FUNCPTR
-s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc );
-#else
-s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc );
-#endif
-
-/*extern struct gmonparam *_gmonparam, */
-
-#ifdef PROFILE_NO_FUNCPTR
-s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc )
-{
- s32 index = 0 ;
-
- while( (index < cgtable_size) && (cgtable[index].frompc != frompc) ){
- index++ ;
- }
- if( index == cgtable_size ) {
- return -1 ;
- } else {
- return index ;
- }
-}
-#else
-s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc )
-{
- s32 index = 0 ;
- s32 Status;
-
- while( (index < fromssize) && (froms[index].frompc != frompc) ){
- index++ ;
- }
- if( index == fromssize ) {
- Status = -1 ;
- } else {
- Status = index ;
- }
- return Status;
-}
-#endif /* PROFILE_NO_FUNCPTR */
-
-
-void mcount( u32 frompc, u32 selfpc )
-{
- register struct gmonparam *p = NULL;
- register s32 toindex, fromindex;
- s32 j;
-
- disable_timer();
-
- /*print("CG: "), putnum(frompc), print("->"), putnum(selfpc), print("\r\n") ,
- * check that frompcindex is a reasonable pc value.
- * for example: signal catchers get called from the stack,
- * not from text space. too bad.
- */
- for(j = 0; j < n_gmon_sections; j++ ){
- if((frompc >= _gmonparam[j].lowpc) && (frompc < _gmonparam[j].highpc)) {
- p = &_gmonparam[j];
- break;
- }
- }
- if( j == n_gmon_sections ) {
- goto done;
- }
-
-#ifdef PROFILE_NO_FUNCPTR
- fromindex = searchpc( p->cgtable, p->cgtable_size, frompc ) ;
- if( fromindex == -1 ) {
- fromindex = p->cgtable_size ;
- p->cgtable_size++ ;
- p->cgtable[fromindex].frompc = frompc ;
- p->cgtable[fromindex].selfpc = selfpc ;
- p->cgtable[fromindex].count = 1 ;
- goto done ;
- }
- p->cgtable[fromindex].count++ ;
-#else
- fromindex = (s32)searchpc( p->froms, ((s32)p->fromssize), frompc ) ;
- if( fromindex == -1 ) {
- fromindex = (s32)p->fromssize ;
- p->fromssize++ ;
- /*if( fromindex >= N_FROMS ) {
- * print("Error : From PC table overflow\r\n")
- * goto overflow
- *}*/
- p->froms[fromindex].frompc = frompc ;
- p->froms[fromindex].link = -1 ;
- }else {
- toindex = ((s32)(p->froms[fromindex].link));
- while(toindex != -1) {
- toindex = (((s32)p->tossize) - toindex)-1 ;
- if( p->tos[toindex].selfpc == selfpc ) {
- p->tos[toindex].count++ ;
- goto done ;
- }
- toindex = ((s32)(p->tos[toindex].link)) ;
- }
- }
-
- /*if( toindex == -1 ) { */
- p->tos-- ;
- p->tossize++ ;
- /* if( toindex >= N_TOS ) {
- * print("Error : To PC table overflow\r\n")
- * goto overflow
- *} */
- p->tos[0].selfpc = selfpc ;
- p->tos[0].count = 1 ;
- p->tos[0].link = p->froms[fromindex].link ;
- p->froms[fromindex].link = ((s32)(p->tossize))-((s32)1);
-#endif
-
- done:
- p->state = GMON_PROF_ON;
- goto enable_timer_label ;
- /* overflow: */
- /*p->state = GMON_PROF_ERROR */
- enable_timer_label:
- enable_timer();
- return ;
-}
-
-
-#endif /* PROFILE_NO_GRAPH */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d/90974c575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d/90974c575243001d18b399c1eb9b3628
deleted file mode 100644
index 7cc34bb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d/90974c575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,643 +0,0 @@
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diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d/b1282d575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d/b1282d575243001d18b399c1eb9b3628
deleted file mode 100644
index e06988a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d/b1282d575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,78 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xadcps_sinit.c
-* @addtogroup xadcps_v2_6
-* @{
-*
-* This file contains the implementation of the XAdcPs driver's static
-* initialization functionality.
-*
-* @note None.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a ssb 12/22/11 First release based on the XPS/AXI XADC driver
-* 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xparameters.h"
-#include "xadcps.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-extern XAdcPs_Config XAdcPs_ConfigTable[];
-
-/*****************************************************************************/
-/**
-*
-* This function looks up the device configuration based on the unique device ID.
-* The table XAdcPs_ConfigTable contains the configuration info for each device
-* in the system.
-*
-* @param DeviceId contains the ID of the device for which the
-* device configuration pointer is to be returned.
-*
-* @return
-* - A pointer to the configuration found.
-* - NULL if the specified device ID was not found.
-*
-* @note None.
-*
-******************************************************************************/
-XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId)
-{
- XAdcPs_Config *CfgPtr = NULL;
- u32 Index;
-
- for (Index = 0U; Index < 1U; Index++) {
- if (XAdcPs_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XAdcPs_ConfigTable[Index];
- break;
- }
- }
-
- return CfgPtr;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d/e15abe595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d/e15abe595243001d18b399c1eb9b3628
deleted file mode 100644
index b3cd2ea..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d/e15abe595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,113 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xplatform_info.h
-*
-*
-* @addtogroup common_platform_info APIs to Get Platform Information
-*
-*
-* The xplatform_info.h file contains definitions for various available Xilinx®
-* platforms. Also, it contains prototype of APIs, which can be used to get the
-* platform information.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- --------- -------------------------------------------------------
-* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
-* function for PMUFW.
-* 7.2 adk 08/01/20 Added versal support for the XGetPSVersion_Info function.
-* 7.6 mus 08/23/21 Updated prototypes for functions which are not taking any
-* arguments with void keyword. This has been done to fix
-* compilation warnings with "-Wstrict-prototypes" flag.
-* It fixes CR#1108601.
-* 7.6 mus 08/30/21 Updated flag checking to fix compilation warnings
-* reported with "-Wundef" flag.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 11/03/09 Initial release.
-* 4.2 pkp 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
-* as smc.c is removed
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 01/10/10 Initial release
-* 3.00a mb 25/06/12 InitQspi, data is read first and required config bits
-* are set
-* 4.00a sg 02/28/13 Cleanup
-* Removed LPBK_DLY_ADJ register setting code as we use
-* divisor 8
-* 5.00a sgd 05/17/13 Added Flash Size > 128Mbit support
-* Dual Stack support
-* Fix for CR:721674 - FSBL- Failed to boot from Dual
-* stacked QSPI
-* 6.00a kc 08/30/13 Fix for CR#722979 - Provide customer-friendly
-* changelogs in FSBL
-* Fix for CR#739711 - FSBL not able to read Large QSPI
-* (512M) in IO Mode
-* 7.00a kc 10/25/13 Fix for CR#739968 - FSBL should do the QSPI config
-* settings for Dual parallel
-* configuration in IO mode
-* 14.0 gan 01/13/16 Fix for CR#869081 - (2016.1)FSBL picks the qspi read
-* command from LQSPI_CFG register
-* instead of hard coded read
-* command (0x6B).
-* 15.0 bsv 09/04/20 Add support for 2Gb flash parts
-*
-*
-* @note
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "qspi.h"
-#include "image_mover.h"
-
-#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
-#include "xqspips_hw.h"
-#include "xqspips.h"
-
-/************************** Constant Definitions *****************************/
-
-/*
- * The following constants map to the XPAR parameters created in the
- * xparameters.h file. They are defined here such that a user can easily
- * change all the needed parameters in one place.
- */
-#define QSPI_DEVICE_ID XPAR_XQSPIPS_0_DEVICE_ID
-
-/*
- * The following constants define the commands which may be sent to the FLASH
- * device.
- */
-#define QUAD_READ_CMD 0x6B
-#define READ_ID_CMD 0x9F
-
-#define WRITE_ENABLE_CMD 0x06
-#define BANK_REG_RD 0x16
-#define BANK_REG_WR 0x17
-/* Bank register is called Extended Address Reg in Micron */
-#define EXTADD_REG_RD 0xC8
-#define EXTADD_REG_WR 0xC5
-
-#define COMMAND_OFFSET 0 /* FLASH instruction */
-#define ADDRESS_1_OFFSET 1 /* MSB byte of address to read or write */
-#define ADDRESS_2_OFFSET 2 /* Middle byte of address to read or write */
-#define ADDRESS_3_OFFSET 3 /* LSB byte of address to read or write */
-#define DATA_OFFSET 4 /* Start of Data for Read/Write */
-#define DUMMY_OFFSET 4 /* Dummy byte offset for fast, dual and quad
- reads */
-#define DUMMY_SIZE 1 /* Number of dummy bytes for fast, dual and
- quad reads */
-#define RD_ID_SIZE 4 /* Read ID command + 3 bytes ID response */
-#define BANK_SEL_SIZE 2 /* BRWR or EARWR command + 1 byte bank value */
-#define WRITE_ENABLE_CMD_SIZE 1 /* WE command */
-/*
- * The following constants specify the extra bytes which are sent to the
- * FLASH on the QSPI interface, that are not data, but control information
- * which includes the command and address
- */
-#define OVERHEAD_SIZE 4
-
-/*
- * The following constants specify the max amount of data and the size of the
- * the buffer required to hold the data and overhead to transfer the data to
- * and from the FLASH.
- */
-#define DATA_SIZE 4096
-
-/*
- * The following defines are for dual flash interface.
- */
-#define LQSPI_CR_FAST_READ 0x0000000B
-#define LQSPI_CR_FAST_DUAL_READ 0x0000003B
-#define LQSPI_CR_FAST_QUAD_READ 0x0000006B /* Fast Quad Read output */
-#define LQSPI_CR_1_DUMMY_BYTE 0x00000100 /* 1 Dummy Byte between
- address and return data */
-
-#define SINGLE_QSPI_CONFIG_FAST_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
- LQSPI_CR_1_DUMMY_BYTE | \
- LQSPI_CR_FAST_READ)
-
-#define SINGLE_QSPI_CONFIG_FAST_DUAL_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
- LQSPI_CR_1_DUMMY_BYTE | \
- LQSPI_CR_FAST_DUAL_READ)
-
-#define SINGLE_QSPI_CONFIG_FAST_QUAD_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
- LQSPI_CR_1_DUMMY_BYTE | \
- LQSPI_CR_FAST_QUAD_READ)
-
-#define DUAL_QSPI_CONFIG_FAST_QUAD_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
- XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
- XQSPIPS_LQSPI_CR_SEP_BUS_MASK | \
- LQSPI_CR_1_DUMMY_BYTE | \
- LQSPI_CR_FAST_QUAD_READ)
-
-#define DUAL_STACK_CONFIG_FAST_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
- LQSPI_CR_1_DUMMY_BYTE | \
- LQSPI_CR_FAST_READ)
-
-#define DUAL_STACK_CONFIG_FAST_DUAL_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
- LQSPI_CR_1_DUMMY_BYTE | \
- LQSPI_CR_FAST_DUAL_READ)
-
-#define DUAL_STACK_CONFIG_FAST_QUAD_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
- LQSPI_CR_1_DUMMY_BYTE | \
- LQSPI_CR_FAST_QUAD_READ)
-
-#define SINGLE_QSPI_IO_CONFIG_FAST_READ (LQSPI_CR_1_DUMMY_BYTE | \
- LQSPI_CR_FAST_READ)
-
-#define SINGLE_QSPI_IO_CONFIG_FAST_DUAL_READ (LQSPI_CR_1_DUMMY_BYTE | \
- LQSPI_CR_FAST_DUAL_READ)
-
-#define SINGLE_QSPI_IO_CONFIG_FAST_QUAD_READ (LQSPI_CR_1_DUMMY_BYTE | \
- LQSPI_CR_FAST_QUAD_READ)
-
-#define DUAL_QSPI_IO_CONFIG_FAST_QUAD_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
- XQSPIPS_LQSPI_CR_SEP_BUS_MASK | \
- LQSPI_CR_1_DUMMY_BYTE | \
- LQSPI_CR_FAST_QUAD_READ)
-
-#define QSPI_BUSWIDTH_ONE 0U
-#define QSPI_BUSWIDTH_TWO 1U
-#define QSPI_BUSWIDTH_FOUR 2U
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-XQspiPs QspiInstance;
-XQspiPs *QspiInstancePtr;
-u32 QspiFlashSize;
-u32 QspiFlashMake;
-extern u32 FlashReadBaseAddress;
-extern u8 LinearBootDeviceFlag;
-
-/*
- * The following variables are used to read and write to the eeprom and they
- * are global to avoid having large buffers on the stack
- */
-u8 ReadBuffer[DATA_SIZE + DATA_OFFSET + DUMMY_SIZE];
-u8 WriteBuffer[DATA_OFFSET + DUMMY_SIZE];
-
-/******************************************************************************/
-/**
-*
-* This function initializes the controller for the QSPI interface.
-*
-* @param None
-*
-* @return None
-*
-* @note None
-*
-****************************************************************************/
-u32 InitQspi(void)
-{
- XQspiPs_Config *QspiConfig;
- int Status;
- u32 ConfigCmd;
-
- QspiInstancePtr = &QspiInstance;
-
- /*
- * Set up the base address for access
- */
- FlashReadBaseAddress = XPS_QSPI_LINEAR_BASEADDR;
-
- /*
- * Initialize the QSPI driver so that it's ready to use
- */
- QspiConfig = XQspiPs_LookupConfig(QSPI_DEVICE_ID);
- if (NULL == QspiConfig) {
- return XST_FAILURE;
- }
-
- Status = XQspiPs_CfgInitialize(QspiInstancePtr, QspiConfig,
- QspiConfig->BaseAddress);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- /*
- * Set Manual Chip select options and drive HOLD_B pin high.
- */
- XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_FORCE_SSELECT_OPTION |
- XQSPIPS_HOLD_B_DRIVE_OPTION);
-
- /*
- * Set the prescaler for QSPI clock
- */
- XQspiPs_SetClkPrescaler(QspiInstancePtr, XQSPIPS_CLK_PRESCALE_8);
-
- /*
- * Assert the FLASH chip select.
- */
- XQspiPs_SetSlaveSelect(QspiInstancePtr);
-
- /*
- * Read Flash ID and extract Manufacture and Size information
- */
- Status = FlashReadID();
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- if (XPAR_XQSPIPS_0_QSPI_MODE == SINGLE_FLASH_CONNECTION) {
-
- fsbl_printf(DEBUG_INFO,"QSPI is in single flash connection\r\n");
- /*
- * For Flash size <128Mbit controller configured in linear mode
- */
- if (QspiFlashSize <= FLASH_SIZE_16MB) {
- LinearBootDeviceFlag = 1;
-
- /*
- * Enable linear mode
- */
- XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_LQSPI_MODE_OPTION |
- XQSPIPS_HOLD_B_DRIVE_OPTION);
-
- switch (XPAR_XQSPIPS_0_QSPI_BUS_WIDTH) {
-
- case QSPI_BUSWIDTH_ONE:
- {
- fsbl_printf(DEBUG_INFO,"QSPI is in 1-bit mode\r\n");
- ConfigCmd = SINGLE_QSPI_CONFIG_FAST_READ;
- }
- break;
-
- case QSPI_BUSWIDTH_TWO:
- {
- fsbl_printf(DEBUG_INFO,"QSPI is in 2-bit mode\r\n");
- ConfigCmd = SINGLE_QSPI_CONFIG_FAST_DUAL_READ;
- }
- break;
-
- case QSPI_BUSWIDTH_FOUR:
- {
- fsbl_printf(DEBUG_INFO,"QSPI is in 4-bit mode\r\n");
- ConfigCmd = SINGLE_QSPI_CONFIG_FAST_QUAD_READ;
- }
- break;
-
- }
-
- /*
- * Single linear read
- */
- XQspiPs_SetLqspiConfigReg(QspiInstancePtr, ConfigCmd);
-
- /*
- * Enable the controller
- */
- XQspiPs_Enable(QspiInstancePtr);
- } else {
-
- switch (XPAR_XQSPIPS_0_QSPI_BUS_WIDTH) {
-
- case QSPI_BUSWIDTH_ONE:
- {
- fsbl_printf(DEBUG_INFO,"QSPI is in 1-bit mode\r\n");
- ConfigCmd = SINGLE_QSPI_IO_CONFIG_FAST_READ;
- }
- break;
-
- case QSPI_BUSWIDTH_TWO:
- {
- fsbl_printf(DEBUG_INFO,"QSPI is in 2-bit mode\r\n");
- ConfigCmd = SINGLE_QSPI_IO_CONFIG_FAST_DUAL_READ;
- }
- break;
-
- case QSPI_BUSWIDTH_FOUR:
- {
- fsbl_printf(DEBUG_INFO,"QSPI is in 4-bit mode\r\n");
- ConfigCmd = SINGLE_QSPI_IO_CONFIG_FAST_QUAD_READ;
- }
- break;
-
- }
- /*
- * Single flash IO read
- */
- XQspiPs_SetLqspiConfigReg(QspiInstancePtr, ConfigCmd);
-
- /*
- * Enable the controller
- */
- XQspiPs_Enable(QspiInstancePtr);
- }
- }
-
- if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) {
-
- fsbl_printf(DEBUG_INFO,"QSPI is in Dual Parallel connection\r\n");
- /*
- * For Single Flash size <128Mbit controller configured in linear mode
- */
- if (QspiFlashSize <= FLASH_SIZE_16MB) {
- /*
- * Setting linear access flag
- */
- LinearBootDeviceFlag = 1;
-
- /*
- * Enable linear mode
- */
- XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_LQSPI_MODE_OPTION |
- XQSPIPS_HOLD_B_DRIVE_OPTION);
-
- /*
- * Dual linear read
- */
- XQspiPs_SetLqspiConfigReg(QspiInstancePtr, DUAL_QSPI_CONFIG_FAST_QUAD_READ);
-
- /*
- * Enable the controller
- */
- XQspiPs_Enable(QspiInstancePtr);
- } else {
- /*
- * Dual flash IO read
- */
- XQspiPs_SetLqspiConfigReg(QspiInstancePtr, DUAL_QSPI_IO_CONFIG_FAST_QUAD_READ);
-
- /*
- * Enable the controller
- */
- XQspiPs_Enable(QspiInstancePtr);
-
- }
-
- /*
- * Total flash size is two time of single flash size
- */
- QspiFlashSize = 2 * QspiFlashSize;
- }
-
- /*
- * It is expected to same flash size for both chip selection
- */
- if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_STACK_CONNECTION) {
-
- fsbl_printf(DEBUG_INFO,"QSPI is in Dual Stack connection\r\n");
-
- QspiFlashSize = 2 * QspiFlashSize;
-
- /*
- * Enable two flash memories on separate buses
- */
- switch (XPAR_XQSPIPS_0_QSPI_BUS_WIDTH) {
-
- case QSPI_BUSWIDTH_ONE:
- {
- fsbl_printf(DEBUG_INFO,"QSPI is in 1-bit mode\r\n");
- ConfigCmd = DUAL_STACK_CONFIG_FAST_READ;
- }
- break;
-
- case QSPI_BUSWIDTH_TWO:
- {
- fsbl_printf(DEBUG_INFO,"QSPI is in 2-bit mode\r\n");
- ConfigCmd = DUAL_STACK_CONFIG_FAST_DUAL_READ;
- }
- break;
-
- case QSPI_BUSWIDTH_FOUR:
- {
- fsbl_printf(DEBUG_INFO,"QSPI is in 4-bit mode\r\n");
- ConfigCmd = DUAL_STACK_CONFIG_FAST_QUAD_READ;
- }
- break;
-
- }
- XQspiPs_SetLqspiConfigReg(QspiInstancePtr, ConfigCmd);
- }
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* This function reads serial FLASH ID connected to the SPI interface.
-* It then deduces the make and size of the flash and obtains the
-* connection mode to point to corresponding parameters in the flash
-* configuration table. The flash driver will function based on this and
-* it presently supports Micron and Spansion - 128, 256 and 512Mbit and
-* Winbond 128Mbit
-*
-* @param none
-*
-* @return XST_SUCCESS if read id, otherwise XST_FAILURE.
-*
-* @note None.
-*
-******************************************************************************/
-u32 FlashReadID(void)
-{
- u32 Status;
-
- /*
- * Read ID in Auto mode.
- */
- WriteBuffer[COMMAND_OFFSET] = READ_ID_CMD;
- WriteBuffer[ADDRESS_1_OFFSET] = 0x00; /* 3 dummy bytes */
- WriteBuffer[ADDRESS_2_OFFSET] = 0x00;
- WriteBuffer[ADDRESS_3_OFFSET] = 0x00;
-
- Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
- RD_ID_SIZE);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- fsbl_printf(DEBUG_INFO,"Single Flash Information\r\n");
-
- fsbl_printf(DEBUG_INFO,"FlashID=0x%x 0x%x 0x%x\r\n", ReadBuffer[1],
- ReadBuffer[2],
- ReadBuffer[3]);
-
- /*
- * Deduce flash make
- */
- if (ReadBuffer[1] == MICRON_ID) {
- QspiFlashMake = MICRON_ID;
- fsbl_printf(DEBUG_INFO, "MICRON ");
- } else if(ReadBuffer[1] == SPANSION_ID) {
- QspiFlashMake = SPANSION_ID;
- fsbl_printf(DEBUG_INFO, "SPANSION ");
- } else if(ReadBuffer[1] == WINBOND_ID) {
- QspiFlashMake = WINBOND_ID;
- fsbl_printf(DEBUG_INFO, "WINBOND ");
- } else if(ReadBuffer[1] == MACRONIX_ID) {
- QspiFlashMake = MACRONIX_ID;
- fsbl_printf(DEBUG_INFO, "MACRONIX ");
- } else if(ReadBuffer[1] == ISSI_ID) {
- QspiFlashMake = ISSI_ID;
- fsbl_printf(DEBUG_INFO, "ISSI ");
- }
-
- /*
- * Deduce flash Size
- */
- if (ReadBuffer[3] == FLASH_SIZE_ID_8M) {
- QspiFlashSize = FLASH_SIZE_8M;
- fsbl_printf(DEBUG_INFO, "8M Bits\r\n");
- } else if (ReadBuffer[3] == FLASH_SIZE_ID_16M) {
- QspiFlashSize = FLASH_SIZE_16M;
- fsbl_printf(DEBUG_INFO, "16M Bits\r\n");
- } else if (ReadBuffer[3] == FLASH_SIZE_ID_32M) {
- QspiFlashSize = FLASH_SIZE_32M;
- fsbl_printf(DEBUG_INFO, "32M Bits\r\n");
- } else if (ReadBuffer[3] == FLASH_SIZE_ID_64M) {
- QspiFlashSize = FLASH_SIZE_64M;
- fsbl_printf(DEBUG_INFO, "64M Bits\r\n");
- } else if (ReadBuffer[3] == FLASH_SIZE_ID_128M) {
- QspiFlashSize = FLASH_SIZE_128M;
- fsbl_printf(DEBUG_INFO, "128M Bits\r\n");
- } else if (ReadBuffer[3] == FLASH_SIZE_ID_256M) {
- QspiFlashSize = FLASH_SIZE_256M;
- fsbl_printf(DEBUG_INFO, "256M Bits\r\n");
- } else if ((ReadBuffer[3] == FLASH_SIZE_ID_512M)
- || (ReadBuffer[3] == MACRONIX_FLASH_1_8_V_MX66_ID_512)
- || (ReadBuffer[3] == MACRONIX_FLASH_SIZE_ID_512M)) {
- QspiFlashSize = FLASH_SIZE_512M;
- fsbl_printf(DEBUG_INFO, "512M Bits\r\n");
- } else if ((ReadBuffer[3] == FLASH_SIZE_ID_1G)
- || (ReadBuffer[3] == MACRONIX_FLASH_SIZE_ID_1G)) {
- QspiFlashSize = FLASH_SIZE_1G;
- fsbl_printf(DEBUG_INFO, "1G Bits\r\n");
- } else if ((ReadBuffer[3] == FLASH_SIZE_ID_2G)
- || (ReadBuffer[3] == MACRONIX_FLASH_SIZE_ID_2G)) {
- QspiFlashSize = FLASH_SIZE_2G;
- fsbl_printf(DEBUG_INFO, "2G Bits\r\n");
- }
- return XST_SUCCESS;
-}
-
-
-/******************************************************************************
-*
-* This function reads from the serial FLASH connected to the
-* QSPI interface.
-*
-* @param Address contains the address to read data from in the FLASH.
-* @param ByteCount contains the number of bytes to read.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void FlashRead(u32 Address, u32 ByteCount)
-{
- /*
- * Setup the write command with the specified address and data for the
- * FLASH
- */
- u32 LqspiCrReg;
- u8 ReadCommand;
-
- LqspiCrReg = XQspiPs_GetLqspiConfigReg(QspiInstancePtr);
- ReadCommand = (u8) (LqspiCrReg & XQSPIPS_LQSPI_CR_INST_MASK);
- WriteBuffer[COMMAND_OFFSET] = ReadCommand;
- WriteBuffer[ADDRESS_1_OFFSET] = (u8)((Address & 0xFF0000) >> 16);
- WriteBuffer[ADDRESS_2_OFFSET] = (u8)((Address & 0xFF00) >> 8);
- WriteBuffer[ADDRESS_3_OFFSET] = (u8)(Address & 0xFF);
-
- ByteCount += DUMMY_SIZE;
-
- /*
- * Send the read command to the FLASH to read the specified number
- * of bytes from the FLASH, send the read command and address and
- * receive the specified number of bytes of data in the data buffer
- */
- XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
- ByteCount + OVERHEAD_SIZE);
-}
-
-/******************************************************************************/
-/**
-*
-* This function provides the QSPI FLASH interface for the Simplified header
-* functionality.
-*
-* @param SourceAddress is address in FLASH data space
-* @param DestinationAddress is address in DDR data space
-* @param LengthBytes is the length of the data in Bytes
-*
-* @return
-* - XST_SUCCESS if the write completes correctly
-* - XST_FAILURE if the write fails to completes correctly
-*
-* @note none.
-*
-****************************************************************************/
-u32 QspiAccess( u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
-{
- u8 *BufferPtr;
- u32 Length = 0;
- u32 BankSel = 0;
- u32 LqspiCrReg;
- u32 Status;
- u8 BankSwitchFlag = 1;
-
- /*
- * Linear access check
- */
- if (LinearBootDeviceFlag == 1) {
- /*
- * Check for non-word tail, add bytes to cover the end
- */
- if ((LengthBytes%4) != 0){
- LengthBytes += (4 - (LengthBytes & 0x00000003));
- }
-
- memcpy((void*)DestinationAddress,
- (const void*)(SourceAddress + FlashReadBaseAddress),
- (size_t)LengthBytes);
- } else {
- /*
- * Non Linear access
- */
- BufferPtr = (u8*)DestinationAddress;
-
- /*
- * Dual parallel connection actual flash is half
- */
- if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) {
- SourceAddress = SourceAddress/2;
- }
-
- while(LengthBytes > 0) {
- /*
- * Local of DATA_SIZE size used for read/write buffer
- */
- if(LengthBytes > DATA_SIZE) {
- Length = DATA_SIZE;
- } else {
- Length = LengthBytes;
- }
-
- /*
- * Dual stack connection
- */
- if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_STACK_CONNECTION) {
- /*
- * Get the current LQSPI configuration value
- */
- LqspiCrReg = XQspiPs_GetLqspiConfigReg(QspiInstancePtr);
-
- /*
- * Select lower or upper Flash based on sector address
- */
- if (SourceAddress >= (QspiFlashSize/2)) {
- /*
- * Set selection to U_PAGE
- */
- XQspiPs_SetLqspiConfigReg(QspiInstancePtr,
- LqspiCrReg | XQSPIPS_LQSPI_CR_U_PAGE_MASK);
-
- /*
- * Subtract first flash size when accessing second flash
- */
- SourceAddress = SourceAddress - (QspiFlashSize/2);
-
- fsbl_printf(DEBUG_INFO, "stacked - upper CS \n\r");
-
- /*
- * Assert the FLASH chip select.
- */
- XQspiPs_SetSlaveSelect(QspiInstancePtr);
- }
- }
-
- /*
- * Select bank
- */
- if ((SourceAddress >= FLASH_SIZE_16MB) && (BankSwitchFlag == 1)) {
- BankSel = SourceAddress/FLASH_SIZE_16MB;
-
- fsbl_printf(DEBUG_INFO, "Bank Selection %lu\n\r", BankSel);
-
- Status = SendBankSelect(BankSel);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO, "Bank Selection Failed\n\r");
- return XST_FAILURE;
- }
-
- BankSwitchFlag = 0;
- }
-
- /*
- * If data to be read spans beyond the current bank, then
- * calculate length in current bank else no change in length
- */
- if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) {
- /*
- * In dual parallel mode, check should be for half
- * the length.
- */
- if((SourceAddress & BANKMASK) != ((SourceAddress + (Length/2)) & BANKMASK))
- {
- Length = (SourceAddress & BANKMASK) + FLASH_SIZE_16MB - SourceAddress;
- /*
- * Above length calculated is for single flash
- * Length should be doubled since dual parallel
- */
- Length = Length * 2;
- BankSwitchFlag = 1;
- }
- } else {
- if((SourceAddress & BANKMASK) != ((SourceAddress + Length) & BANKMASK))
- {
- Length = (SourceAddress & BANKMASK) + FLASH_SIZE_16MB - SourceAddress;
- BankSwitchFlag = 1;
- }
- }
-
- /*
- * Copying the image to local buffer
- */
- FlashRead(SourceAddress, Length);
-
- /*
- * Moving the data from local buffer to DDR destination address
- */
- memcpy(BufferPtr, &ReadBuffer[DATA_OFFSET + DUMMY_SIZE], Length);
-
- /*
- * Updated the variables
- */
- LengthBytes -= Length;
-
- /*
- * For Dual parallel connection address increment should be half
- */
- if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) {
- SourceAddress += Length/2;
- } else {
- SourceAddress += Length;
- }
-
- BufferPtr = (u8*)((u32)BufferPtr + Length);
- }
-
- /*
- * Reset Bank selection to zero
- */
- Status = SendBankSelect(0);
- if (Status != XST_SUCCESS) {
- fsbl_printf(DEBUG_INFO, "Bank Selection Reset Failed\n\r");
- return XST_FAILURE;
- }
-
- if (XPAR_XQSPIPS_0_QSPI_MODE == DUAL_STACK_CONNECTION) {
-
- /*
- * Reset selection to L_PAGE
- */
- XQspiPs_SetLqspiConfigReg(QspiInstancePtr,
- LqspiCrReg & (~XQSPIPS_LQSPI_CR_U_PAGE_MASK));
-
- fsbl_printf(DEBUG_INFO, "stacked - lower CS \n\r");
-
- /*
- * Assert the FLASH chip select.
- */
- XQspiPs_SetSlaveSelect(QspiInstancePtr);
- }
- }
-
- return XST_SUCCESS;
-}
-
-
-
-/******************************************************************************
-*
-* This functions selects the current bank
-*
-* @param BankSel is the bank to be selected in the flash device(s).
-*
-* @return XST_SUCCESS if bank selected
-* XST_FAILURE if selection failed
-* @note None.
-*
-******************************************************************************/
-u32 SendBankSelect(u8 BankSel)
-{
- u32 Status;
-
- /*
- * bank select commands for Micron and Spansion are different
- * Macronix bank select is same as Micron
- */
- if (QspiFlashMake == MICRON_ID || QspiFlashMake == MACRONIX_ID) {
- /*
- * For micron command WREN should be sent first
- * except for some specific feature set
- */
- WriteBuffer[COMMAND_OFFSET] = WRITE_ENABLE_CMD;
- Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL,
- WRITE_ENABLE_CMD_SIZE);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
-
- /*
- * Send the Extended address register write command
- * written, no receive buffer required
- */
- WriteBuffer[COMMAND_OFFSET] = EXTADD_REG_WR;
- WriteBuffer[ADDRESS_1_OFFSET] = BankSel;
- Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL,
- BANK_SEL_SIZE);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
- }
-
- if (QspiFlashMake == SPANSION_ID) {
- WriteBuffer[COMMAND_OFFSET] = BANK_REG_WR;
- WriteBuffer[ADDRESS_1_OFFSET] = BankSel;
-
- /*
- * Send the Extended address register write command
- * written, no receive buffer required
- */
- Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL,
- BANK_SEL_SIZE);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
- }
-
- /*
- * For testing - Read bank to verify
- */
- if (QspiFlashMake == SPANSION_ID) {
- WriteBuffer[COMMAND_OFFSET] = BANK_REG_RD;
- WriteBuffer[ADDRESS_1_OFFSET] = 0x00;
-
- /*
- * Send the Extended address register write command
- * written, no receive buffer required
- */
- Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
- BANK_SEL_SIZE);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
- }
-
- if (QspiFlashMake == MICRON_ID || QspiFlashMake == MACRONIX_ID) {
- WriteBuffer[COMMAND_OFFSET] = EXTADD_REG_RD;
- WriteBuffer[ADDRESS_1_OFFSET] = 0x00;
-
- /*
- * Send the Extended address register write command
- * written, no receive buffer required
- */
- Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
- BANK_SEL_SIZE);
- if (Status != XST_SUCCESS) {
- return XST_FAILURE;
- }
- }
-
- if (ReadBuffer[1] != BankSel) {
- fsbl_printf(DEBUG_INFO, "BankSel %d != Register Read %d\n\r", BankSel,
- ReadBuffer[1]);
- return XST_FAILURE;
- }
-
- return XST_SUCCESS;
-}
-#endif
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d0/937ab3585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d0/937ab3585243001d18b399c1eb9b3628
deleted file mode 100644
index 90efcf4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d0/937ab3585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,23 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#include
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) clock_t clock(void);
-}
-#endif
-/*
- * clock -- It supposed to return processor time. We are not implementing
- * this function, as timekeeping is tightly coupled with system, hence
- * always returning 0. Users can override this with their system
- * specific implementation.
- *
- */
-__attribute__((weak)) clock_t clock(void)
-{
- return (0);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d0/a0c09f575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d0/a0c09f575243001d18b399c1eb9b3628
deleted file mode 100644
index de98c61..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d0/a0c09f575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,345 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xscutimer.h
-* @addtogroup scutimer_v2_3
-* @{
-* @details
-*
-* The timer driver supports the Cortex A9 private timer.
-*
-* The timer driver supports the following features:
-* - Normal mode and Auto reload mode
-* - Interrupts (Interrupt handler is not provided in this driver. Application
-* has to register it's own handler)
-*
-* Initialization and Configuration
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate with the Timer.
-*
-* XScuTimer_CfgInitialize() API is used to initialize the Timer. The
-* user needs to first call the XScuTimer_LookupConfig() API which returns
-* the Configuration structure pointer which is passed as a parameter to
-* the XScuTimer_CfgInitialize() API.
-*
-* Interrupts
-*
-* The Timer hardware supports interrupts.
-*
-* This driver does not provide a Interrupt Service Routine (ISR) for the device.
-* It is the responsibility of the application to provide one if needed. Refer to
-* the interrupt example provided with this driver for details on using the
-* Timer in interrupt mode.
-*
-* Virtual Memory
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-* Threads
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* Asserts
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* Building the driver
-*
-* The XScuTimer driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-*
-*
-* NOTE:
-* The timer is not a part of the snoop control unit as indicated by the
-* prefix "scu" in the name of the driver.
-* It is an independent module in APU.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm 03/10/10 First release
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 2.3 mus 08/31/20 Updated makefile to support parallel make and
-* incremental builds, it would help to reduce compilation
-* time.
-*
-*
-******************************************************************************/
-#ifndef XSCUTIMER_H /* prevent circular inclusions */
-#define XSCUTIMER_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xscutimer_hw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddr; /**< Base address of the device */
-} XScuTimer_Config;
-
-/**
- * The XScuTimer driver instance data. The user is required to allocate a
- * variable of this type for every timer device in the system.
- * A pointer to a variable of this type is then passed to the driver API
- * functions.
- */
-typedef struct {
- XScuTimer_Config Config; /**< Hardware Configuration */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStarted; /**< Device timer is running */
-} XScuTimer;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Check if the timer has expired.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return
-* - TRUE if the timer has expired.
-* - FALSE if the timer has not expired.
-*
-* @note C-style signature:
-* int XScuTimer_IsExpired(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_IsExpired(InstancePtr) \
- ((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_ISR_OFFSET) & \
- XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
- XSCUTIMER_ISR_EVENT_FLAG_MASK)
-
-/****************************************************************************/
-/**
-*
-* Re-start the timer. This macro will read the timer load register
-* and writes the same value to load register to update the counter register.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_RestartTimer(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_RestartTimer(InstancePtr) \
- XScuTimer_LoadTimer((InstancePtr), \
- XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_LOAD_OFFSET))
-
-/****************************************************************************/
-/**
-*
-* Write to the timer load register. This will also update the
-* timer counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-* @param Value is the count to be loaded in to the load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_LoadTimer(InstancePtr, Value) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_LOAD_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer counter register value. It can be called at any
-* time.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return Contents of the timer counter register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_GetCounterValue(InstancePtr) \
- XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_COUNTER_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Enable auto-reload mode.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_EnableAutoReload(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) | \
- XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
-
-/****************************************************************************/
-/**
-*
-* Disable auto-reload mode.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_DisableAutoReload(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) & \
- ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Enable the Timer interrupt.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_EnableInterrupt(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) | \
- XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
-
-/****************************************************************************/
-/**
-*
-* Disable the Timer interrupt.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_DisableInterrupt(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET, \
- (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_CONTROL_OFFSET) & \
- ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
-
-/*****************************************************************************/
-/**
-*
-* This function reads the interrupt status.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_GetInterruptStatus(InstancePtr) \
- XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_ISR_OFFSET)
-
-/*****************************************************************************/
-/**
-*
-* This function clears the interrupt status.
-*
-* @param InstancePtr is a pointer to the XScuTimer instance.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr)
-*
-******************************************************************************/
-#define XScuTimer_ClearInterruptStatus(InstancePtr) \
- XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \
- XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Lookup configuration in xscutimer_sinit.c
- */
-XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId);
-
-/*
- * Selftest function in xscutimer_selftest.c
- */
-s32 XScuTimer_SelfTest(XScuTimer *InstancePtr);
-
-/*
- * Interface functions in xscutimer.c
- */
-s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
- XScuTimer_Config *ConfigPtr, u32 EffectiveAddress);
-void XScuTimer_Start(XScuTimer *InstancePtr);
-void XScuTimer_Stop(XScuTimer *InstancePtr);
-void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue);
-u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d1/10cefa565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d1/10cefa565243001d18b399c1eb9b3628
deleted file mode 100644
index d986349..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d1/10cefa565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,240 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm_gcc.h
-*
-* This header file contains macros for using inline assembler code. It is
-* written specifically for the GNU compiler.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/21/14 First release
-* 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors
-* 7.2 asa 04/03/20 Renamed the str macro to strw.
-* 7.2 dp 04/30/20 Added clobber "cc" to mtcpsr for aarch32 processors
-*
-;* MODIFICATION HISTORY:
-;*
-;* Ver Who Date Changes
-;* ----- ------- -------- ---------------------------------------------------
-;* 7.0 cjp 02/26/19 First release
-;*
-;*
-;* @note
-;*
-;* None.
-;*
-;******************************************************************************/
-
-#include "bspconfig.h"
-
- EXPORT _vector_table
- EXPORT FPUStatus
-
- IMPORT _boot
- IMPORT FIQInterrupt
- IMPORT IRQInterrupt
- IMPORT SErrorInterrupt
- IMPORT SynchronousInterrupt
-
-;
-; FPUContextSize is the size of the array where floating point registers are
-; stored when required. The default size corresponds to the case when there is
-; no nested interrupt. If there are nested interrupts in application which are
-; using floating point operation, the size of FPUContextSize need to be
-; increased as per requirement
-;
-FPUContextSize EQU 528
-
- MACRO
- saveregister
- stp X0, X1, [sp,#-0x10]!
- stp X2, X3, [sp,#-0x10]!
- stp X4, X5, [sp,#-0x10]!
- stp X6, X7, [sp,#-0x10]!
- stp X8, X9, [sp,#-0x10]!
- stp X10, X11, [sp,#-0x10]!
- stp X12, X13, [sp,#-0x10]!
- stp X14, X15, [sp,#-0x10]!
- stp X16, X17, [sp,#-0x10]!
- stp X18, X19, [sp,#-0x10]!
- stp X29, X30, [sp,#-0x10]!
- MEND
-
- MACRO
- restoreregister
- ldp X29, X30, [sp], #0x10
- ldp X18, X19, [sp], #0x10
- ldp X16, X17, [sp], #0x10
- ldp X14, X15, [sp], #0x10
- ldp X12, X13, [sp], #0x10
- ldp X10, X11, [sp], #0x10
- ldp X8, X9, [sp], #0x10
- ldp X6, X7, [sp], #0x10
- ldp X4, X5, [sp], #0x10
- ldp X2, X3, [sp], #0x10
- ldp X0, X1, [sp], #0x10
- MEND
-
- MACRO
- savefloatregister
- ldr x1, =FPUContextBase ; Load the floating point context array address from FPUContextBase
- ldr x0, [x1]
- stp q0, q1, [x0], #0x20 ; Save all the floating point register to the array
- stp q2, q3, [x0], #0x20
- stp q4, q5, [x0], #0x20
- stp q6, q7, [x0], #0x20
- stp q8, q9, [x0], #0x20
- stp q10, q11, [x0], #0x20
- stp q12, q13, [x0], #0x20
- stp q14, q15, [x0], #0x20
- stp q16, q17, [x0], #0x20
- stp q18, q19, [x0], #0x20
- stp q20, q21, [x0], #0x20
- stp q22, q23, [x0], #0x20
- stp q24, q25, [x0], #0x20
- stp q26, q27, [x0], #0x20
- stp q28, q29, [x0], #0x20
- stp q30, q31, [x0], #0x20
- mrs x2, FPCR
- mrs x3, FPSR
- stp x2, x3, [x0], #0x10
- str x0, [x1] ; Save current address of floating point context array to FPUContextBase
- MEND
-
- MACRO
- restorefloatregister
- ldr x1, =FPUContextBase ; Restore the address of floating point context array from FPUContextBase
- ldr x0, [x1]
- ldp x2, x3, [x0,#-0x10]! ; Restore all the floating point register from the array
- msr FPCR, x2
- msr FPSR, x3
- ldp q30, q31, [x0,#-0x20]!
- ldp q28, q29, [x0,#-0x20]!
- ldp q26, q27, [x0,#-0x20]!
- ldp q24, q25, [x0,#-0x20]!
- ldp q22, q23, [x0,#-0x20]!
- ldp q20, q21, [x0,#-0x20]!
- ldp q18, q19, [x0,#-0x20]!
- ldp q16, q17, [x0,#-0x20]!
- ldp q14, q15, [x0,#-0x20]!
- ldp q12, q13, [x0,#-0x20]!
- ldp q10, q11, [x0,#-0x20]!
- ldp q8, q9, [x0,#-0x20]!
- ldp q6, q7, [x0,#-0x20]!
- ldp q4, q5, [x0,#-0x20]!
- ldp q2, q3, [x0,#-0x20]!
- ldp q0, q1, [x0,#-0x20]!
- str x0, [x1] ; Save current address of floating point context array to FPUContextBase
- MEND
-
- AREA |.vectors|, CODE
- REQUIRE8 {TRUE}
- PRESERVE8 {TRUE}
- ENTRY ; Define this as an entry point
-
-_vector_table
-
-;
-; If application is built for XEN GUEST as EL1 Non-secure following image
-; header is required by XEN.
-;
-#if (HYP_GUEST == 1)
- ldr x16, =_boot ; Valid Image header
- br x16 ; HW reset vector
- DCD 0 ; Text offset
- DCD 0 ; Image size
- DCD 8 ; Flags
- DCD 0 ; RES0
- DCD 0
- DCD 0
- DCD 0x644d5241 ; Magic
- DCD 0 ; RES0
-#endif
-
- B _boot
- ALIGN 512
- B SynchronousInterruptHandler
- ALIGN 128
- B IRQInterruptHandler
- ALIGN 128
- B FIQInterruptHandler
- ALIGN 128
- B SErrorInterruptHandler
-
-SynchronousInterruptHandler
- saveregister
-
-; Check if the Synchronous abort is occurred due to floating point access
-#if (EL3 == 1)
- mrs x0, ESR_EL3
-#else
- mrs x0, ESR_EL1
-#endif
- and x0, x0, #(0x3F << 26)
- mov x1, #(0x7 << 26)
- cmp x0, x1
-
-;
-; If exception is not due to floating point access go to synchronous
-; handler
-;
- bne synchronoushandler
-
-;
-; If exception occurred due to floating point access, Enable the floating point
-; access i.e. do not trap floating point instruction
-;
-#if (EL3 == 1)
- mrs x1, CPTR_EL3
- mov x2, #(0x1<<10)
- bic x1, x1, x2
- msr CPTR_EL3, x1
-#else
- mrs x1, CPACR_EL1
- orr x1, x1, #(0x1<<20)
- msr CPACR_EL1, x1
-#endif
- isb
-
-;
-; If the floating point access was previously enabled, store FPU context
-; registers(storefloat)
-;
- ldr x0, =FPUStatus
- ldrb w1, [x0]
- cbnz w1, storefloat
-
-;
-; If the floating point access was not enabled previously, save the status of
-; floating point accessibility i.e. enabled and store floating point context
-; array address(FPUContext) to FPUContextBase
-;
- mov w1, #0x1
- strb w1, [x0]
- ldr x0, =FPUContext
- ldr x1, =FPUContextBase
- str x0, [x1]
- b restorecontext
-
-storefloat
- savefloatregister
- b restorecontext
-
-synchronoushandler
- bl SynchronousInterrupt
-
-restorecontext
- restoreregister
- eret
-
-IRQInterruptHandler
- saveregister
-
-; Save the status of SPSR, ELR and CPTR to stack
-#if (EL3 == 1)
- mrs x0, CPTR_EL3
- mrs x1, ELR_EL3
- mrs x2, SPSR_EL3
-#else
- mrs x0, CPACR_EL1
- mrs x1, ELR_EL1
- mrs x2, SPSR_EL1
-#endif
- stp x0, x1, [sp,#-0x10]!
- str x2, [sp,#-0x10]!
-
-
-; Trap floating point access
-#if (EL3 == 1)
- mrs x1, CPTR_EL3
- orr x1, x1, #(0x1<<10)
- msr CPTR_EL3, x1
-#else
- mrs x1, CPACR_EL1
- mov x2, #(0x1<<20)
- bic x1, x1, x2
- msr CPACR_EL1, x1
-#endif
- isb
- bl IRQInterrupt
-;
-; If floating point access is enabled during interrupt handling, restore
-; floating point registers
-;
-#if (EL3 == 1)
- mrs x0, CPTR_EL3
- ands x0, x0, #(0x1<<10)
- bne RestorePrevState
-#else
- mrs x0, CPACR_EL1
- ands x0, x0, #(0x1<<20)
- beq RestorePrevState
-#endif
- restorefloatregister
-
-
-; Restore the status of SPSR, ELR and CPTR from stack
-RestorePrevState
- ldr x2, [sp], #0x10
- ldp x0, x1, [sp],#0x10
-#if (EL3 == 1)
- msr CPTR_EL3, x0
- msr ELR_EL3, x1
- msr SPSR_EL3, x2
-#else
- msr CPACR_EL1, x0
- msr ELR_EL1, x1
- msr SPSR_EL1, x2
-#endif
- restoreregister
- eret
-
-FIQInterruptHandler
- saveregister
- bl FIQInterrupt
- restoreregister
- eret
-
-SErrorInterruptHandler
- saveregister
- bl SErrorInterrupt
- restoreregister
- eret
-
- ALIGN 8
-
-; Array to store floating point registers
-FPUContext
- SPACE FPUContextSize
-
-; Stores address for floating point context array
-FPUContextBase
- SPACE 8
-
-FPUStatus
- SPACE 4
-
- END
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d1/9136e2595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d1/9136e2595243001d18b399c1eb9b3628
deleted file mode 100644
index b144c7a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d1/9136e2595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,116 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xadcps_selftest.c
-* @addtogroup xadcps_v2_6
-* @{
-*
-* This file contains a diagnostic self test function for the XAdcPs driver.
-* The self test function does a simple read/write test of the Alarm Threshold
-* Register.
-*
-* See xadcps.h for more information.
-*
-* @note None.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
-* 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors.
-*
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xadcps.h"
-
-/************************** Constant Definitions ****************************/
-
-/*
- * The following constant defines the test value to be written
- * to the Alarm Threshold Register
- */
-#define XADCPS_ATR_TEST_VALUE 0x55U
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-/*****************************************************************************/
-/**
-*
-* Run a self-test on the driver/device. The test
-* - Resets the device,
-* - Writes a value into the Alarm Threshold register and reads it back
-* for comparison.
-* - Resets the device again.
-*
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return
-* - XST_SUCCESS if the value read from the Alarm Threshold
-* register is the same as the value written.
-* - XST_FAILURE Otherwise
-*
-* @note This is a destructive test in that resets of the device are
-* performed. Refer to the device specification for the
-* device status after the reset operation.
-*
-******************************************************************************/
-int XAdcPs_SelfTest(XAdcPs *InstancePtr)
-{
- int Status;
- u32 RegValue;
-
- /*
- * Assert the argument
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- /*
- * Reset the device to get it back to its default state
- */
- XAdcPs_Reset(InstancePtr);
-
- /*
- * Write a value into the Alarm Threshold registers, read it back, and
- * do the comparison
- */
- XAdcPs_SetAlarmThreshold(InstancePtr, XADCPS_ATR_VCCINT_UPPER,
- XADCPS_ATR_TEST_VALUE);
- RegValue = XAdcPs_GetAlarmThreshold(InstancePtr, XADCPS_ATR_VCCINT_UPPER);
-
- if (RegValue == XADCPS_ATR_TEST_VALUE) {
- Status = XST_SUCCESS;
- } else {
- Status = XST_FAILURE;
- }
-
- /*
- * Reset the device again to its default state.
- */
- XAdcPs_Reset(InstancePtr);
- /*
- * Return the test result.
- */
- return Status;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d1/a07482575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d1/a07482575243001d18b399c1eb9b3628
deleted file mode 100644
index d6bc637..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d1/a07482575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,47 +0,0 @@
-/******************************************************************************/
-/**
-* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-* @file xil_mem.h
-*
-* @addtogroup common_mem_operation_api Customized APIs for Memory Operations
-*
-* The xil_mem.h file contains prototype for functions related
-* to memory operations. These APIs are applicable for all processors supported
-* by Xilinx.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.1 nsk 11/07/16 First release.
-* 7.0 mus 01/07/19 Add cpp extern macro
-*
-*
-*
-*****************************************************************************/
-#ifndef XIL_MEM_H /* prevent circular inclusions */
-#define XIL_MEM_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Function Prototypes *****************************/
-
-void Xil_MemCpy(void* dst, const void* src, u32 cnt);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_MEM_H */
-/**
-* @} End of "addtogroup common_mem_operation_api".
-*/
\ No newline at end of file
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d1/a1d0c6575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d1/a1d0c6575243001d18b399c1eb9b3628
deleted file mode 100644
index f1fa391..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d1/a1d0c6575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,88 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xdevcfg_selftest.c
-* @addtogroup devcfg_v3_7
-* @{
-*
-* Contains diagnostic self-test functions for the XDcfg driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.02a nm 02/27/13 Fixed CR# 701348.
-* Peripheral test fails with Running
-* DcfgSelfTestExample() in SECURE bootmode.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xdevcfg.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/****************************************************************************/
-/**
-*
-* Run a self-test on the Device Configuration Interface. This test does a
-* control register write and reads back the same value.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return
-* - XST_SUCCESS if self-test was successful.
-* - XST_FAILURE if fails.
-*
-* @note None.
-*
-******************************************************************************/
-int XDcfg_SelfTest(XDcfg *InstancePtr)
-{
- u32 OldCfgReg;
- u32 CfgReg;
- int Status = XST_SUCCESS;
-
- /*
- * Assert to ensure the inputs are valid and the instance has been
- * initialized.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- OldCfgReg = XDcfg_GetControlRegister(InstancePtr);
-
- XDcfg_SetControlRegister(InstancePtr, XDCFG_CTRL_NIDEN_MASK);
-
- CfgReg = XDcfg_GetControlRegister(InstancePtr);
-
- if ((CfgReg & XDCFG_CTRL_NIDEN_MASK) != XDCFG_CTRL_NIDEN_MASK) {
-
- Status = XST_FAILURE;
- }
-
- /*
- * Restore the original values of the register
- */
- XDcfg_SetControlRegister(InstancePtr, OldCfgReg);
-
- return Status;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d1/b0e0b5575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d1/b0e0b5575243001d18b399c1eb9b3628
deleted file mode 100644
index 991d295..0000000
Binary files a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d1/b0e0b5575243001d18b399c1eb9b3628 and /dev/null differ
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d1/b2ee89575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d1/b2ee89575243001d18b399c1eb9b3628
deleted file mode 100644
index e22e04d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d1/b2ee89575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,181 +0,0 @@
-/******************************************************************************/
-/**
-* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-* @file xil_util.h
-* @addtogroup common_utilities Common Utility APIs
-* @{
-* @details
-*
-* This file contains xil utility functions declaration
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.4 mmd 04/21/19 First release.
-* 6.5 kal 02/29/20 Added Xil_ConvertStringToHexBE API
-* 7.3 kal 06/30/20 Converted Xil_Ceil macro to API
-* rpo 08/19/20 Added function for read, modify and write
-* bsv 08/21/20 Added XSECURE_TEMPORAL_CHECK macro to add
-* redundancy in security critical functions, to avoid
-* glitches from altering the return values of security
-* critical functions. The macro requires a label to be
-* passed to "go to" in case of error.
-* kpt 09/03/20 Added XSECURE_TEMPORAL_IMPL macro for redundancy
-* kal 09/22/20 Changed the param type from const char to const char*
-* to avoid copying key onto stack
-* td 10/16/20 Added Xil_Strcpy, Xil_Strcat, Xil_SecureMemCpy and
-* Xil_MemCmp functions
-* am 10/13/20 Resolved Coverity warning
-* td 11/19/20 Updated XSECURE_TEMPORAL_CHECK and
-* XSECURE_TEMPORAL_IMPL to fix MISRA C Rule 15.3
-* 7.4 am 11/26/20 Added Xil_StrCpyRange function
-* 7.6 kpt 07/15/21 Added Xil_SecureZeroize function
-*
-*
-*
-*****************************************************************************/
-
-#ifndef XIL_UTIL_H_
-#define XIL_UTIL_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xstatus.h"
-
-/*************************** Constant Definitions *****************************/
-#define XIL_SIZE_OF_NIBBLE_IN_BITS 4U
-#define XIL_SIZE_OF_BYTE_IN_BITS 8U
-
-/* Maximum string length handled by Xil_ValidateHexStr function */
-#define XIL_MAX_HEX_STR_LEN 512U
-
-
-/****************** Macros (Inline Functions) Definitions *********************/
-#ifdef __GNUC__
-/******************************************************************************/
-/**
- *
- * Updates the return value of the called function into Var and VarTmp variables
- * for redundancy. This is to avoid glitches from altering the return values of
- * security critical functions.
- *
- * @param Var is the variable which holds the return value of function
- * executed
- * @param VarTmp is the variable which holds the value stored in Var
- * @param Function is the function to be executed
- * @param Other params are arguments to the called function
- *
- * @return None
- *
- ******************************************************************************/
-#define XSECURE_TEMPORAL_IMPL(Var, VarTmp, Function, ...) \
- { \
- Var = XST_FAILURE; \
- VarTmp = XST_FAILURE; \
- Var = Function(__VA_ARGS__); \
- VarTmp = Var; \
- }
-
-/******************************************************************************/
-/**
- *
- * Adds redundancy while checking the status of the called function.
- * This is to avoid glitches from altering the return values of security
- * critical functions. The macro requires a label to be passed to "go to"
- * in case of error.
- *
- * @param Label is the label defined in function and the control
- * will jump to the label in case of XST_FAILURE
- * @param Status is the variable which holds the return value of
- * function executed
- * @param Function is the function to be executed
- * @param Other params are arguments to the called function
- *
- * @return None
- *
- ******************************************************************************/
-#define XSECURE_TEMPORAL_CHECK(Label, Status, Function, ...) \
- { \
- volatile int StatusTmp = XST_FAILURE; \
- XSECURE_TEMPORAL_IMPL(Status, StatusTmp, Function, __VA_ARGS__); \
- if ((Status != XST_SUCCESS) || \
- (StatusTmp != XST_SUCCESS)) { \
- Status |= StatusTmp;\
- goto Label; \
- } \
- }
-#endif
-
-/*************************** Function Prototypes ******************************/
-/* Ceils the provided float value */
-int Xil_Ceil(float Value);
-
-/* Converts input character to nibble */
-u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num);
-
-/* Convert input hex string to array of 32-bits integers */
-u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len);
-
-/* Waits for specified event */
-u32 Xil_WaitForEvent(u32 RegAddr, u32 EventMask, u32 Event, u32 Timeout);
-
-/* Waits for specified events */
-u32 Xil_WaitForEvents(u32 EventsRegAddr, u32 EventsMask, u32 WaitEvents,
- u32 Timeout, u32* Events);
-
-/* Validate input hex character */
-u32 Xil_IsValidHexChar(const char *Ch);
-
-/* Validate the input string contains only hexadecimal characters */
-u32 Xil_ValidateHexStr(const char *HexStr);
-
-/* Convert string to hex numbers in little enidian format */
-u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len);
-
-/* Returns length of the input string */
-u32 Xil_Strnlen(const char *Str, u32 MaxLen);
-
-/* Convert string to hex numbers in big endian format */
-u32 Xil_ConvertStringToHexBE(const char * Str, u8 * Buf, u32 Len);
-
-/*Read, Modify and Write to an address*/
-void Xil_UtilRMW32(u32 Addr, u32 Mask, u32 Value);
-
-/* Copies source string to destination string */
-int Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size);
-
-/* Copies specified range from source string to destination string */
-int Xil_StrCpyRange(const u8 *Src, u8 *Dst, u32 From, u32 To, u32 MaxSrcLen,
- u32 MaxDstLen);
-
-/* Appends string2 to string1 */
-int Xil_Strcat(char* Str1Ptr, const char* Str2Ptr, const u32 Size);
-
-/* Copies Len bytes from source memory to destination memory */
-int Xil_SecureMemCpy(void * DestPtr, u32 DestPtrLen, const void * SrcPtr, u32 Len);
-
-/* Compares Len bytes from memory1 and memory2 */
-int Xil_MemCmp(const void * Buf1Ptr, const void * Buf2Ptr, u32 Len);
-
-/* Zeroizes the memory of given length */
-int Xil_SecureZeroize(u8 *DataPtr, const u32 Length);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_UTIL_H_ */
-/**
-* @} End of "addtogroup common_utilities".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d2/7054dc575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d2/7054dc575243001d18b399c1eb9b3628
deleted file mode 100644
index 9698ed3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d2/7054dc575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,1133 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
- *
- * @file xemacps_control.c
-* @addtogroup emacps_v3_15
-* @{
- *
- * Functions in this file implement general purpose command and control related
- * functionality. See xemacps.h for a detailed description of the driver.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -------------------------------------------------------
- * 1.00a wsy 01/10/10 First release
- * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
- * register. Added a new API for setting the BURST length
- * in DMACR register.
- * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
- * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
- * 3.0 hk 02/20/15 Added support for jumbo frames.
- * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
- *
- *****************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xemacps.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
- * Set the MAC address for this driver/device. The address is a 48-bit value.
- * The device must be stopped before calling this function.
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param AddressPtr is a pointer to a 6-byte MAC address.
- * @param Index is a index to which MAC (1-4) address.
- *
- * @return
- * - XST_SUCCESS if the MAC address was set successfully
- * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
- *
- *****************************************************************************/
-LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
-{
- u32 MacAddr;
- u8 *Aptr = (u8 *)(void *)AddressPtr;
- u8 IndexLoc = Index;
- LONG Status;
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(Aptr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
-
- /* Be sure device has been stopped */
- if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
- Status = (LONG)(XST_DEVICE_IS_STARTED);
- }
- else{
- /* Index ranges 1 to 4, for offset calculation is 0 to 3. */
- IndexLoc--;
-
- /* Set the MAC bits [31:0] in BOT */
- MacAddr = *(Aptr);
- MacAddr |= ((u32)(*(Aptr+1)) << 8U);
- MacAddr |= ((u32)(*(Aptr+2)) << 16U);
- MacAddr |= ((u32)(*(Aptr+3)) << 24U);
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- ((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
-
- /* There are reserved bits in TOP so don't affect them */
- MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
-
- MacAddr &= (u32)(~XEMACPS_LADDR_MACH_MASK);
-
- /* Set MAC bits [47:32] in TOP */
- MacAddr |= (u32)(*(Aptr+4));
- MacAddr |= (u32)(*(Aptr+5)) << 8U;
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
-
- Status = (LONG)(XST_SUCCESS);
- }
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
- * Get the MAC address for this driver/device.
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param AddressPtr is an output parameter, and is a pointer to a buffer into
- * which the current MAC address will be copied.
- * @param Index is a index to which MAC (1-4) address.
- *
- *****************************************************************************/
-void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
-{
- u32 MacAddr;
- u8 *Aptr = (u8 *)(void *)AddressPtr;
- u8 IndexLoc = Index;
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(Aptr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
-
- /* Index ranges 1 to 4, for offset calculation is 0 to 3. */
- IndexLoc--;
-
- MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- ((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)));
- *Aptr = (u8) MacAddr;
- *(Aptr+1) = (u8) (MacAddr >> 8U);
- *(Aptr+2) = (u8) (MacAddr >> 16U);
- *(Aptr+3) = (u8) (MacAddr >> 24U);
-
- /* Read MAC bits [47:32] in TOP */
- MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
- *(Aptr+4) = (u8) MacAddr;
- *(Aptr+5) = (u8) (MacAddr >> 8U);
-}
-
-
-/*****************************************************************************/
-/**
- * Set 48-bit MAC addresses in hash table.
- * The device must be stopped before calling this function.
- *
- * The hash address register is 64 bits long and takes up two locations in
- * the memory map. The least significant bits are stored in hash register
- * bottom and the most significant bits in hash register top.
- *
- * The unicast hash enable and the multicast hash enable bits in the network
- * configuration register enable the reception of hash matched frames. The
- * destination address is reduced to a 6 bit index into the 64 bit hash
- * register using the following hash function. The hash function is an XOR
- * of every sixth bit of the destination address.
- *
- *
- *
- * where f[HOSTCLK] is the bus clock frequency in MHz, and f[MDC] is the
- * MDIO clock frequency in MHz to the PHY. Typically, f[MDC] should not
- * exceed 2.5 MHz. Some PHYs can tolerate faster speeds which means faster
- * access. Here is the table to show values to generate MDC,
- *
- *
- * 000 : divide pclk by 8 (pclk up to 20 MHz)
- * 001 : divide pclk by 16 (pclk up to 40 MHz)
- * 010 : divide pclk by 32 (pclk up to 80 MHz)
- * 011 : divide pclk by 48 (pclk up to 120 MHz)
- * 100 : divide pclk by 64 (pclk up to 160 MHz)
- * 101 : divide pclk by 96 (pclk up to 240 MHz)
- * 110 : divide pclk by 128 (pclk up to 320 MHz)
- * 111 : divide pclk by 224 (pclk up to 540 MHz)
- *
- *
- * @param InstancePtr is a pointer to the instance to be worked on.
- * @param Divisor is the divisor to set. Range is 0b000 to 0b111.
- *
- *****************************************************************************/
-void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor)
-{
- u32 Reg;
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(Divisor <= (XEmacPs_MdcDiv)0x7); /* only last three bits are valid */
-
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCFG_OFFSET);
- /* clear these three bits, could be done with mask */
- Reg &= (u32)(~XEMACPS_NWCFG_MDCCLKDIV_MASK);
-
- Reg |= ((u32)Divisor << XEMACPS_NWCFG_MDC_SHIFT_MASK);
-
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWCFG_OFFSET, Reg);
-}
-
-
-/*****************************************************************************/
-/**
-* Read the current value of the PHY register indicated by the PhyAddress and
-* the RegisterNum parameters. The MAC provides the driver with the ability to
-* talk to a PHY that adheres to the Media Independent Interface (MII) as
-* defined in the IEEE 802.3 standard.
-*
-* Prior to PHY access with this function, the user should have setup the MDIO
-* clock with XEmacPs_SetMdioDivisor().
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-* @param PhyAddress is the address of the PHY to be read (supports multiple
-* PHYs)
-* @param RegisterNum is the register number, 0-31, of the specific PHY register
-* to read
-* @param PhyDataPtr is an output parameter, and points to a 16-bit buffer into
-* which the current value of the register will be copied.
-*
-* @return
-*
-* - XST_SUCCESS if the PHY was read from successfully
-* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
-*
-* @note
-*
-* This function is not thread-safe. The user must provide mutually exclusive
-* access to this function if there are to be multiple threads that can call it.
-*
-* There is the possibility that this function will not return if the hardware
-* is broken (i.e., it never sets the status bit indicating that the read is
-* done). If this is of concern to the user, the user should provide a mechanism
-* suitable to their needs for recovery.
-*
-* For the duration of this function, all host interface reads and writes are
-* blocked to the current XEmacPs instance.
-*
-******************************************************************************/
-LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
- u32 RegisterNum, u16 *PhyDataPtr)
-{
- u32 Mgtcr;
- volatile u32 Ipisr;
- u32 IpReadTemp;
- LONG Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /* Make sure no other PHY operation is currently in progress */
- if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWSR_OFFSET) &
- XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
- Status = (LONG)(XST_EMAC_MII_BUSY);
- } else {
-
- /* Construct Mgtcr mask for the operation */
- Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_R_MASK |
- (PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
- (RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK);
-
- /* Write Mgtcr and wait for completion */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
-
- do {
- Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWSR_OFFSET);
- IpReadTemp = Ipisr;
- } while ((IpReadTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
-
- /* Read data */
- *PhyDataPtr = (u16)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_PHYMNTNC_OFFSET);
- Status = (LONG)(XST_SUCCESS);
- }
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
-* Write data to the specified PHY register. The Ethernet driver does not
-* require the device to be stopped before writing to the PHY. Although it is
-* probably a good idea to stop the device, it is the responsibility of the
-* application to deem this necessary. The MAC provides the driver with the
-* ability to talk to a PHY that adheres to the Media Independent Interface
-* (MII) as defined in the IEEE 802.3 standard.
-*
-* Prior to PHY access with this function, the user should have setup the MDIO
-* clock with XEmacPs_SetMdioDivisor().
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-* @param PhyAddress is the address of the PHY to be written (supports multiple
-* PHYs)
-* @param RegisterNum is the register number, 0-31, of the specific PHY register
-* to write
-* @param PhyData is the 16-bit value that will be written to the register
-*
-* @return
-*
-* - XST_SUCCESS if the PHY was written to successfully. Since there is no error
-* status from the MAC on a write, the user should read the PHY to verify the
-* write was successful.
-* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
-*
-* @note
-*
-* This function is not thread-safe. The user must provide mutually exclusive
-* access to this function if there are to be multiple threads that can call it.
-*
-* There is the possibility that this function will not return if the hardware
-* is broken (i.e., it never sets the status bit indicating that the write is
-* done). If this is of concern to the user, the user should provide a mechanism
-* suitable to their needs for recovery.
-*
-* For the duration of this function, all host interface reads and writes are
-* blocked to the current XEmacPs instance.
-*
-******************************************************************************/
-LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
- u32 RegisterNum, u16 PhyData)
-{
- u32 Mgtcr;
- volatile u32 Ipisr;
- u32 IpWriteTemp;
- LONG Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /* Make sure no other PHY operation is currently in progress */
- if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWSR_OFFSET) &
- XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
- Status = (LONG)(XST_EMAC_MII_BUSY);
- } else {
- /* Construct Mgtcr mask for the operation */
- Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_W_MASK |
- (PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
- (RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK) | (u32)PhyData;
-
- /* Write Mgtcr and wait for completion */
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
- XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
-
- do {
- Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_NWSR_OFFSET);
- IpWriteTemp = Ipisr;
- } while ((IpWriteTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
-
- Status = (LONG)(XST_SUCCESS);
- }
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* API to update the Burst length in the DMACR register.
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-* @param BLength is the length in bytes for the dma burst.
-*
-* @return None
-*
-******************************************************************************/
-void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength)
-{
- u32 Reg;
- u32 RegUpdateVal = 0;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid((BLength == XEMACPS_SINGLE_BURST) ||
- (BLength == XEMACPS_4BYTE_BURST) ||
- (BLength == XEMACPS_8BYTE_BURST) ||
- (BLength == XEMACPS_16BYTE_BURST));
-
- switch (BLength) {
- case XEMACPS_SINGLE_BURST:
- RegUpdateVal = XEMACPS_DMACR_SINGLE_AHB_BURST;
- break;
-
- case XEMACPS_4BYTE_BURST:
- RegUpdateVal = XEMACPS_DMACR_INCR4_AHB_BURST;
- break;
-
- case XEMACPS_8BYTE_BURST:
- RegUpdateVal = XEMACPS_DMACR_INCR8_AHB_BURST;
- break;
-
- case XEMACPS_16BYTE_BURST:
- RegUpdateVal = XEMACPS_DMACR_INCR16_AHB_BURST;
- break;
- }
- Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
- XEMACPS_DMACR_OFFSET);
-
- Reg &= (u32)(~XEMACPS_DMACR_BLENGTH_MASK);
- Reg |= RegUpdateVal;
- XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
- Reg);
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d2/908978575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d2/908978575243001d18b399c1eb9b3628
deleted file mode 100644
index 9397afc..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d2/908978575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,61 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/******************************************************************************/
-/**
-* @file xgpio_i.h
-* @addtogroup gpio_v4_8
-* @{
-*
-* This header file contains internal identifiers, which are those shared
-* between the files of the driver. It is intended for internal use only.
-*
-* NOTES:
-*
-* None.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 03/13/02 First release
-* 2.11a mta 03/21/07 Updated to new coding style
-*
-******************************************************************************/
-
-#ifndef XGPIO_I_H /* prevent circular inclusions */
-#define XGPIO_I_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xgpio.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions ****************************/
-
-extern XGpio_Config XGpio_ConfigTable[];
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d2/a0dffc585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d2/a0dffc585243001d18b399c1eb9b3628
deleted file mode 100644
index 2a4fff2..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d2/a0dffc585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,573 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xreg_cortexa9.h
-*
-* This header file contains definitions for using inline assembler code. It is
-* written specifically for the GNU, ARMCC compiler.
-*
-* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
-* with the positions of the bits within the registers.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm 10/20/09 First release
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------------
-* 1.00a drg 01/19/00 First release
-* 1.01a sdm 11/09/11 The XScuGic and XScuGic_Config structures have changed.
-* The HandlerTable (of type XScuGic_VectorTableEntry) is
-* moved to XScuGic_Config structure from XScuGic structure.
-*
-* The "Config" entry in XScuGic structure is made as
-* pointer for better efficiency.
-*
-* A new file named as xscugic_hw.c is now added. It is
-* to implement low level driver routines without using
-* any xscugic instance pointer. They are useful when the
-* user wants to use xscugic through device id or
-* base address. The driver routines provided are explained
-* below.
-* XScuGic_DeviceInitialize that takes device id as
-* argument and initializes the device (without calling
-* XScuGic_CfgInitialize).
-* XScuGic_DeviceInterruptHandler that takes device id
-* as argument and calls appropriate handlers from the
-* HandlerTable.
-* XScuGic_RegisterHandler that registers a new handler
-* by taking xscugic hardware base address as argument.
-* LookupConfigByBaseAddress is used to return the
-* corresponding config structure from XScuGic_ConfigTable
-* based on the scugic base address passed.
-* 1.02a sdm 12/20/11 Removed AckBeforeService from the XScuGic_Config
-* structure.
-* 1.03a srt 02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
-* *_hw.h
-* Added APIs
-* - XScuGic_SetPriTrigTypeByDistAddr()
-* - XScuGic_GetPriTrigTypeByDistAddr()
-* (CR 702687)
-* Added support to direct interrupts to the appropriate CPU. Earlier
-* interrupts were directed to CPU1 (hard coded). Now depending
-* upon the CPU selected by the user (xparameters.h), interrupts
-* will be directed to the relevant CPU. This fixes CR 699688.
-* 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
-* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
-* Moved functions XScuGic_SetPriTrigTypeByDistAddr and
-* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
-* This is fix for CR#705621.
-* 1.05a hk 06/26/13 Modified tcl to export external interrupts correctly to
-* xparameters.h. Fix for CR's 690505, 708928 & 719359.
-* 2.0 adk 12/10/13 Updated as per the New Tcl API's
-* 2.1 adk 25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.2 asa 02/29/16 Modified DistributorInit function for Zynq AMP case. The
-* distributor is left uninitialized for Zynq AMP. It is assumed
-* that the distributor will be initialized by Linux master. However
-* for CortexR5 case, the earlier code is left unchanged where the
-* the interrupt processor target registers in the distributor is
-* initialized with the corresponding CPU ID on which the application
-* built over the scugic driver runs.
-* These changes fix CR#937243.
-*
-* 3.4 asa 04/07/16 Created a new static function DoDistributorInit to simplify
-* the flow and avoid code duplication. Changes are made for
-* USE_AMP use case for R5. In a scenario (in R5 split mode) when
-* one R5 is operating with A53 in open amp config and other
-* R5 running baremetal app, the existing code
-* had the potential to stop the whole AMP solution to work (if
-* for some reason the R5 running the baremetal app tasked to
-* initialize the Distributor hangs or crashes before initializing).
-* Changes are made so that the R5 under AMP first checks if
-* the distributor is enabled or not and if not, it does the
-* standard Distributor initialization.
-* This fixes the CR#952962.
-* 3.6 ms 01/23/17 Modified xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* kvn 02/17/17 Add support for changing GIC CPU master at run time.
-* kvn 02/28/17 Make the CpuId as static variable and Added new
-* XScugiC_GetCpuId to access CpuId.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 3.7 ms 04/11/17 Modified tcl file to add suffix U for all macro
-* definitions of scugic in xparameters.h
-* 3.8 mus 07/05/17 Updated scugic.tcl to add support for interrupts connected
-* through util_reduced_vector IP(OR gate)
-* mus 07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize
-* the HandlerTable in XScuGic_ConfigTable to 0, it removes
-* the compilation warning in xscugic_g.c. Fix for CR#978736.
-* mus 07/25/17 Updated xdefine_gic_params proc to export correct canonical
-* definitions for pl to ps interrupts.Fix for CR#980534
-* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
-* XScuGic_InterruptUnmapFromCpu, These API's can be used
-* by applications to unmap specific/all interrupts from
-* target CPU.
-* 3.10 aru 08/23/18 Resolved MISRA-C:2012 compliance mandatory violations
-* 4.0 mus 11/22/18 Fixed bugs in software interrupt generation through
-* XScuGic_SoftwareIntr API
-* 4.1 asa 03/30/19 Made changes not to direct each interrupt to all
-* available CPUs by default. This was breaking AMP
-* behavior. Instead every time an interrupt enable
-* request is received, the interrupt was mapped to
-* the respective CPU. There were several other changes
-* made to implement this. This set of changes was to
-* fix CR-1024716.
-* 4.1 mus 06/19/19 Added API's XScuGic_MarkCoreAsleep and
-* XScuGic_MarkCoreAwake to mark processor core as
-* asleep or awake. Fix for CR#1027220.
-* 4.5 asa 03/07/21 Included a header file xil_spinlock.h to ensure that
-* GIC driver can use newly introduced spinlock
-* functionality.
-* 4.6 sk 08/05/21 Fix scugic misrac violations.
-*
-*
-*
-******************************************************************************/
-
-#ifndef XSCUGIC_H /* prevent circular inclusions */
-#define XSCUGIC_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xil_io.h"
-#include "xscugic_hw.h"
-#include "xil_exception.h"
-#include "xil_spinlock.h"
-
-/************************** Constant Definitions *****************************/
-
-#define EFUSE_STATUS_OFFSET 0x10
-#define EFUSE_STATUS_CPU_MASK 0x80
-
-#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
-#define ARMA9
-#endif
-
-#define XSCUGIC500_DCTLR_ARE_NS_ENABLE 0x20
-#define XSCUGIC500_DCTLR_ARE_S_ENABLE 0x10
-/**************************** Type Definitions *******************************/
-
-/* The following data type defines each entry in an interrupt vector table.
- * The callback reference is the base address of the interrupting device
- * for the low level driver and an instance pointer for the high level driver.
- */
-typedef struct
-{
- Xil_InterruptHandler Handler;
- void *CallBackRef;
-} XScuGic_VectorTableEntry;
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct
-{
- u16 DeviceId; /**< Unique ID of device */
- u32 CpuBaseAddress; /**< CPU Interface Register base address */
- u32 DistBaseAddress; /**< Distributor Register base address */
- XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
- Vector table of interrupt handlers */
-} XScuGic_Config;
-
-/**
- * The XScuGic driver instance data. The user is required to allocate a
- * variable of this type for every intc device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct
-{
- XScuGic_Config *Config; /**< Configuration table entry */
- u32 IsReady; /**< Device is initialized and ready */
- u32 UnhandledInterrupts; /**< Intc Statistics */
-} XScuGic;
-
-/************************** Variable Definitions *****************************/
-
-extern XScuGic_Config XScuGic_ConfigTable[]; /**< Config table */
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Write the given CPU Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
- ((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given CPU Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
- (XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given Distributor Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
- ((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given Distributor Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
-(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given ReDistributor Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_ReDistWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress)+ \
- XSCUGIC_RDIST_OFFSET, (RegOffset), ((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given ReDistributor Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_ReDistReadReg(InstancePtr, RegOffset) \
-(XScuGic_ReadReg((((InstancePtr)->Config->DistBaseAddress)+ \
-XSCUGIC_RDIST_OFFSET), (RegOffset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given ReDistributor SGI PPI Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuGic_ReDistSGIPPIWriteReg(InstancePtr, RegOffset, Data) \
-(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress)+ \
- XSCUGIC_RDIST_SGI_PPI_OFFSET, (RegOffset), ((u32)(Data))))
-
-/****************************************************************************/
-/**
-*
-* Read the given ReDistributor SGI PPI Interface register
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note
-* C-style signature:
-* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuGic_ReDistSGIPPIReadReg(InstancePtr, RegOffset) \
-(XScuGic_ReadReg((((InstancePtr)->Config->DistBaseAddress)+ \
- XSCUGIC_RDIST_SGI_PPI_OFFSET), (RegOffset)))
-
-/****************************************************************************/
-/**
-* This function enables system register interface for GIC CPU Interface
-*
-* @param value to be written
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_Enable_SystemReg_CPU_Interface_EL3() mtcp(S3_6_C12_C12_5, 0xF);
-#define XScuGic_Enable_SystemReg_CPU_Interface_EL1() mtcp(S3_0_C12_C12_5, 0xF);
-/****************************************************************************/
-/**
-* This function enables Grou0 interrupts
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_Enable_Group0_Interrupts() mtcp(S3_0_C12_C12_6,0x1);
-/****************************************************************************/
-/**
-* This function enables Group1 interrupts
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#if defined (__aarch64__)
-#if EL1_NONSECURE
-#define XScuGic_Enable_Group1_Interrupts() \
- mtcp (S3_0_C12_C12_7, 0x1 | mfcp(S3_0_C12_C12_7) );
-#else
-#define XScuGic_Enable_Group1_Interrupts() \
- mtcp (S3_6_C12_C12_7, 0x1 | mfcp(S3_6_C12_C12_7) );
-#endif
-#endif
-/****************************************************************************/
-/**
-* This function writes to ICC_SGI0R_EL1
-*
-* @param value to be written
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_WriteICC_SGI0R_EL1(val) mtcp(S3_0_C12_C11_7,val)
-
-/****************************************************************************/
-/**
-* This function writes to ICC_SGI1R_EL1
-*
-* @param value to be written
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_WriteICC_SGI1R_EL1(val) mtcp(S3_0_C12_C11_5,val)
-
-/****************************************************************************/
-/**
-* This function reads ICC_SGI1R_EL1 register
-*
-* @param None
-*
-* @return Value of ICC_SGI1R_EL1 register
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_ReadICC_SGI1R_EL1() mfcp(S3_0_C12_C11_5)
-/****************************************************************************/
-/**
-* This function sets interrupt priority filter
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_set_priority_filter(val) __asm__ __volatile__("msr S3_0_C4_C6_0,%0" : : "r" (val))
-/****************************************************************************/
-/**
-* This function returns interrupt id of highest priority pending interrupt
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#if defined (__aarch64__)
-#if EL3
-#define XScuGic_get_IntID() mfcp(S3_0_C12_C8_0)
-#else
-#define XScuGic_get_IntID() mfcp(S3_0_C12_C12_0)
-#endif
-#endif
-/****************************************************************************/
-/**
-* This function acks the interrupt
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#if defined (__aarch64__)
-#if EL3
-#define XScuGic_ack_Int(val) mtcp(S3_0_C12_C8_1,val)
-#else
-#define XScuGic_ack_Int(val) mtcp(S3_0_C12_C12_1,val)
-#endif
-#endif
-/****************************************************************************/
-/**
-* This macro returns bit position for the specific interrupt's trigger type
-* configuration within GICR_ICFGR0/GICR_ICFGR1 register
-*
-* @param None.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XScuGic_Get_Rdist_Int_Trigger_Index(IntrId) (((Int_Id%16) & 0x1f) << 2) +1
-/************************** Function Prototypes ******************************/
-
-/*
- * Required functions in xscugic.c
- */
-
-s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
- Xil_InterruptHandler Handler, void *CallBackRef);
-void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id);
-
-void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id);
-void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id);
-
-s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr,
- u32 EffectiveAddr);
-
-s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Identifier);
-
-void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
- u8 *Priority, u8 *Trigger);
-void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
- u8 Priority, u8 Trigger);
-void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Identifier, u32 Int_Id);
-void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Identifier, u32 Int_Id);
-void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Identifier);
-void XScuGic_Stop(XScuGic *InstancePtr);
-void XScuGic_SetCpuID(u32 CpuCoreId);
-u32 XScuGic_GetCpuID(void);
-/*
- * Initialization functions in xscugic_sinit.c
- */
-XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
-
-/*
- * Interrupt functions in xscugic_intr.c
- */
-void XScuGic_InterruptHandler(XScuGic *InstancePtr);
-
-/*
- * Self-test functions in xscugic_selftest.c
- */
-s32 XScuGic_SelfTest(XScuGic *InstancePtr);
-
-#if defined (GICv3)
-void XScuGic_MarkCoreAsleep(XScuGic *InstancePtr);
-void XScuGic_MarkCoreAwake(XScuGic *InstancePtr);
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d3/02024e585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d3/02024e585243001d18b399c1eb9b3628
deleted file mode 100644
index 62a929e..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d3/02024e585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,124 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xil_mmu.c
-*
-* This file provides APIs for enabling/disabling MMU and setting the memory
-* attributes for sections, in the MMU translation table.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.2 pkp 28/05/15 First release
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-#include "xil_mmu.h"
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-extern u32 MMUTable;
-
-/************************** Function Prototypes ******************************/
-/*****************************************************************************/
-/**
-* @brief This function sets the memory attributes for a section covering 1MB
-* of memory in the translation table.
-*
-* @param Addr: 32-bit address for which the attributes need to be set.
-* @param attrib: Attributes for the specified memory region. xil_mmu.h
-* contains commonly used memory attributes definitions which can be
-* utilized for this function.
-*
-*
-* @return None.
-*
-* @note The MMU or D-cache does not need to be disabled before changing a
-* translation table entry.
-*
-******************************************************************************/
-void Xil_SetTlbAttributes(UINTPTR Addr, u32 attrib)
-{
- u32 *ptr;
- u32 section;
-
- section = Addr / 0x100000U;
- ptr = &MMUTable;
- ptr += section;
- if(ptr != NULL) {
- *ptr = (Addr & 0xFFF00000U) | attrib;
- }
-
- Xil_DCacheFlush();
-
- mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
- /* Invalidate all branch predictors */
- mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
-
- dsb(); /* ensure completion of the BP and TLB invalidation */
- isb(); /* synchronize context on this processor */
-}
-
-/*****************************************************************************/
-/**
-* @brief Enable MMU for Cortex-A53 processor in 32bit mode. This function
-* invalidates the instruction and data caches before enabling MMU.
-*
-* @return None.
-*
-******************************************************************************/
-void Xil_EnableMMU(void)
-{
- u32 Reg;
- Xil_DCacheInvalidate();
- Xil_ICacheInvalidate();
-
- Reg = mfcp(XREG_CP15_SYS_CONTROL);
- Reg |= (u32)0x05U;
- mtcp(XREG_CP15_SYS_CONTROL, Reg);
-
- dsb();
- isb();
-}
-
-/*****************************************************************************/
-/**
-* @brief Disable MMU for Cortex A53 processors in 32bit mode. This function
-* invalidates the TLBs, Branch Predictor Array and flushed the data
-* cache before disabling the MMU.
-*
-* @return None.
-*
-* @note When the MMU is disabled, all the memory accesses are treated as
-* strongly ordered.
-******************************************************************************/
-void Xil_DisableMMU(void)
-{
- u32 Reg;
-
- mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
- mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
- Xil_DCacheFlush();
- Reg = mfcp(XREG_CP15_SYS_CONTROL);
- Reg &= (u32)(~0x05U);
- mtcp(XREG_CP15_SYS_CONTROL, Reg);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d3/6192ec555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d3/6192ec555243001d18b399c1eb9b3628
deleted file mode 100644
index 1c41991..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d3/6192ec555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,134 +0,0 @@
-;******************************************************************************
-; Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-; SPDX-License-Identifier: MIT
-;*****************************************************************************
-;****************************************************************************
-;**
-; @file asm_vectors.s
-;
-; This file contains the initial vector table for the Cortex A9 processor
-;
-;
-; MODIFICATION HISTORY:
-;
-; Ver Who Date Changes
-; ----- ------- -------- ---------------------------------------------------
-; 1.00a Initial version
-; 4.2 pkp 06/27/14 Modified return addresses for interrupt
-; handlers
-; 5.1 pkp 05/13/15 Saved the addresses of instruction causing data
-; abort and prefetch abort into DataAbortAddr and
-; PrefetchAbortAddr for further use to fix CR#854523
-;
-;
-; @note
-;
-; None.
-;
-;****************************************************************************
-
- MODULE ?asm_vectors
-
- ;; Forward declaration of sections.
- SECTION IRQ_STACK:DATA:NOROOT(3)
- SECTION FIQ_STACK:DATA:NOROOT(3)
- SECTION SVC_STACK:DATA:NOROOT(3)
- SECTION ABT_STACK:DATA:NOROOT(3)
- SECTION UND_STACK:DATA:NOROOT(3)
- SECTION CSTACK:DATA:NOROOT(3)
-
-#include "xparameters.h"
-;#include "xtime_l.h"
-
-#define UART_BAUDRATE 115200
-
- IMPORT _prestart
- IMPORT __iar_program_start
-
-
-
- SECTION .intvec:CODE:NOROOT(2)
-
- PUBLIC _vector_table
-
- IMPORT IRQInterrupt
- IMPORT FIQInterrupt
- IMPORT SWInterrupt
- IMPORT DataAbortInterrupt
- IMPORT PrefetchAbortInterrupt
- IMPORT DataAbortAddr
- IMPORT PrefetchAbortAddr
-
-_vector_table
- ARM
-
- B __iar_program_start
- B Undefined
- B SVCHandler
- B PrefetchAbortHandler
- B DataAbortHandler
- NOP ; Placeholder for address exception vector
- B IRQHandler
- B FIQHandler
-
-
- SECTION .text:CODE:NOROOT(2)
- REQUIRE _vector_table
-
- ARM
-IRQHandler ; IRQ vector handler
-
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- bl IRQInterrupt ; IRQ vector
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- subs pc, lr, #4 ; adjust return
-
-
-FIQHandler ; FIQ vector handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
-
-FIQLoop
- bl FIQInterrupt ; FIQ vector
-
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- subs pc, lr, #4 ; adjust return
-
-
-Undefined ; Undefined handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- b _prestart
-
- movs pc, lr
-
-
-SVCHandler ; SWI handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- tst r0, #0x20 ; check the T bit
- ldrneh r0, [lr,#-2] ; Thumb mode
- bicne r0, r0, #0xff00 ; Thumb mode
- ldreq r0, [lr,#-4] ; ARM mode
- biceq r0, r0, #0xff000000 ; ARM mode
- bl SWInterrupt ; SWInterrupt: call C function here
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- movs pc, lr ; adjust return
-
-DataAbortHandler ; Data Abort handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- ldr r0, =DataAbortAddr
- sub r1, lr,#8
- str r1, [r0] ;Address of instruction causing data abort
- bl DataAbortInterrupt ;DataAbortInterrupt :call C function here
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- subs pc, lr, #8 ; adjust return
-
-PrefetchAbortHandler ; Prefetch Abort handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- ldr r0, =PrefetchAbortAddr
- sub r1, lr,#4
- str r1, [r0] ;Address of instruction causing prefetch abort
- bl PrefetchAbortInterrupt ; PrefetchAbortInterrupt: call C function here
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- subs pc, lr, #4 ; adjust return
-
- END
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d3/808a30545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d3/808a30545243001d18b399c1eb9b3628
deleted file mode 100644
index 9397afc..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d3/808a30545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,61 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/******************************************************************************/
-/**
-* @file xgpio_i.h
-* @addtogroup gpio_v4_8
-* @{
-*
-* This header file contains internal identifiers, which are those shared
-* between the files of the driver. It is intended for internal use only.
-*
-* NOTES:
-*
-* None.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 03/13/02 First release
-* 2.11a mta 03/21/07 Updated to new coding style
-*
-******************************************************************************/
-
-#ifndef XGPIO_I_H /* prevent circular inclusions */
-#define XGPIO_I_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xgpio.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions ****************************/
-
-extern XGpio_Config XGpio_ConfigTable[];
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d3/c2bdeb575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d3/c2bdeb575243001d18b399c1eb9b3628
deleted file mode 100644
index bee1d41..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d3/c2bdeb575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,133 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2003 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xgpio_sinit.c
-* @addtogroup gpio_v4_8
-* @{
-*
-* The implementation of the XGpio driver's static initialization
-* functionality.
-*
-* @note
-*
-* None
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 2.01a jvb 10/13/05 First release
-* 2.11a mta 03/21/07 Updated to new coding style
-* 4.0 sha 07/15/15 Defined macro XPAR_XGPIO_NUM_INSTANCES if not
-* defined in xparameters.h
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xstatus.h"
-#include "xparameters.h"
-#include "xgpio_i.h"
-
-/************************** Constant Definitions ****************************/
-
-#ifndef XPAR_XGPIO_NUM_INSTANCES
-#define XPAR_XGPIO_NUM_INSTANCES 0 /**< GPIO instances */
-#endif
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-
-/************************** Function Prototypes *****************************/
-
-
-/******************************************************************************/
-/**
-* Lookup the device configuration based on the unique device ID. The table
-* ConfigTable contains the configuration info for each device in the system.
-*
-* @param DeviceId is the device identifier to lookup.
-*
-* @return
-* - A pointer of data type XGpio_Config which points to the
-* device configuration if DeviceID is found.
-* - NULL if DeviceID is not found.
-*
-* @note None.
-*
-******************************************************************************/
-XGpio_Config *XGpio_LookupConfig(u16 DeviceId)
-{
- XGpio_Config *CfgPtr = NULL;
-
- int Index;
-
- for (Index = 0; Index < XPAR_XGPIO_NUM_INSTANCES; Index++) {
- if (XGpio_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XGpio_ConfigTable[Index];
- break;
- }
- }
-
- return CfgPtr;
-}
-
-
-/****************************************************************************/
-/**
-* Initialize the XGpio instance provided by the caller based on the
-* given DeviceID.
-*
-* Nothing is done except to initialize the InstancePtr.
-*
-* @param InstancePtr is a pointer to an XGpio instance. The memory the
-* pointer references must be pre-allocated by the caller. Further
-* calls to manipulate the instance/driver through the XGpio API
-* must be made with this pointer.
-* @param DeviceId is the unique id of the device controlled by this XGpio
-* instance. Passing in a device id associates the generic XGpio
-* instance to a specific device, as chosen by the caller or
-* application developer.
-*
-* @return
-* - XST_SUCCESS if the initialization was successful.
-* - XST_DEVICE_NOT_FOUND if the device configuration data was not
-* found for a device with the supplied device ID.
-*
-* @note None.
-*
-*****************************************************************************/
-int XGpio_Initialize(XGpio * InstancePtr, u16 DeviceId)
-{
- XGpio_Config *ConfigPtr;
-
- /*
- * Assert arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
-
- /*
- * Lookup configuration data in the device configuration table.
- * Use this configuration info down below when initializing this
- * driver.
- */
- ConfigPtr = XGpio_LookupConfig(DeviceId);
- if (ConfigPtr == (XGpio_Config *) NULL) {
- InstancePtr->IsReady = 0;
- return (XST_DEVICE_NOT_FOUND);
- }
-
- return XGpio_CfgInitialize(InstancePtr, ConfigPtr,
- ConfigPtr->BaseAddress);
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d4/01024e585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d4/01024e585243001d18b399c1eb9b3628
deleted file mode 100644
index 3eee8cc..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d4/01024e585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,41 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache_l.h
-*
-* Contains L1 and L2 specific functions for the ARM cache functionality
-* used by xcache.c. This functionality is being made available here for
-* more sophisticated users.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 01/24/10 First release
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00 hbm 08/19/10 First Release
-* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
-* the maximum number of channels.
-* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
-* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
-* Added the tcl file to automatically generate the
-* xparameters.h
-* 1.02a sg 05/16/12 Made changes for doxygen and moved some function
-* header from the xdmaps.h file to xdmaps.c file
-* Other cleanup for coding guidelines and CR 657109
-* and CR 657898
-* The xdmaps_example_no_intr.c example is removed
-* as it is using interrupts and is similar to
-* the interrupt example - CR 652477
-* 1.03a sg 07/16/2012 changed inline to __inline for CR665681
-* 1.04a nm 10/22/2012 Fixed CR# 681671.
-* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled
-* with -Wall and -Wextra option in bsp.
-* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
-* function description.
-* Fixed CR# 704396. Removed unused variables
-* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
-* function.
-* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc.
-* Removed the PDBG prints. By default they were always
-* defined out and never used. The PDBG is non-standard for
-* Xilinx drivers and no other driver does something similar.
-* Since there is no easy way to fix compilation issues with
-* the IARCC compiler around PDBG, it is better to remove it.
-* Users can always use xil_printfs if they want to debug.
-* 2.0 adk 10/12/13 Updated as per the New Tcl API's
-* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
-* 2.2 mus 08/12/16 Declared all inline functions in xdmaps.c as extern, to avoid
-* linker error for IAR compiler
-* 2.3 ms 01/23/17 Modified xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 2.4 adk 13/08/18 Fixed armcc compiler warnings in the driver CR-1008310.
-* 2.8 sk 05/18/21 Modify all inline functions declarations from extern inline
-* to static inline to avoid the linkage conflict for IAR compiler.
-*
-*
-*****************************************************************************/
-
-#ifndef XDMAPS_H /* prevent circular inclusions */
-#define XDMAPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xparameters.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-
-#include "xdmaps_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of device (IPIF) */
-} XDmaPs_Config;
-
-
-/** DMA channle control structure. It's for AXI bus transaction.
- * This struct will be translated into a 32-bit channel control register value.
- */
-typedef struct {
- unsigned int EndianSwapSize; /**< Endian swap size. */
- unsigned int DstCacheCtrl; /**< Destination cache control */
- unsigned int DstProtCtrl; /**< Destination protection control */
- unsigned int DstBurstLen; /**< Destination burst length */
- unsigned int DstBurstSize; /**< Destination burst size */
- unsigned int DstInc; /**< Destination incrementing or fixed
- * address */
- unsigned int SrcCacheCtrl; /**< Source cache control */
- unsigned int SrcProtCtrl; /**< Source protection control */
- unsigned int SrcBurstLen; /**< Source burst length */
- unsigned int SrcBurstSize; /**< Source burst size */
- unsigned int SrcInc; /**< Source incrementing or fixed
- * address */
-} XDmaPs_ChanCtrl;
-
-/** DMA block descriptor stucture.
- */
-typedef struct {
- u32 SrcAddr; /**< Source starting address */
- u32 DstAddr; /**< Destination starting address */
- unsigned int Length; /**< Number of bytes for the block */
-} XDmaPs_BD;
-
-/**
- * A DMA command consisits of a channel control struct, a block descriptor,
- * a user defined program, a pointer pointing to generated DMA program, and
- * execution result.
- *
- */
-typedef struct {
- XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */
- XDmaPs_BD BD; /**< Together with SgLength field,
- * it's a scatter-gather list.
- */
- void *UserDmaProg; /**< If user wants the driver to
- * execute their own DMA program,
- * this field points to the DMA
- * program.
- */
- int UserDmaProgLength; /**< The length of user defined
- * DMA program.
- */
-
- void *GeneratedDmaProg; /**< The DMA program genreated
- * by the driver. This field will be
- * set if a user invokes the DMA
- * program generation function. Or
- * the DMA command is finished and
- * a user informs the driver not to
- * release the program buffer.
- * This field has two purposes, one
- * is to ask the driver to generate
- * a DMA program while the DMAC is
- * performaning DMA transactions. The
- * other purpose is to debug the
- * driver.
- */
- int GeneratedDmaProgLength; /**< The length of the DMA program
- * generated by the driver
- */
- int DmaStatus; /**< 0 on success, otherwise error code
- */
- u32 ChanFaultType; /**< Channel fault type in case of fault
- */
- u32 ChanFaultPCAddr; /**< Channel fault PC address
- */
-} XDmaPs_Cmd;
-
-/**
- * It's the done handler a user can set for a channel
- */
-typedef void (*XDmaPsDoneHandler) (unsigned int Channel,
- XDmaPs_Cmd *DmaCmd,
- void *CallbackRef);
-
-/**
- * It's the fault handler a user can set for a channel
- */
-typedef void (*XDmaPsFaultHandler) (unsigned int Channel,
- XDmaPs_Cmd *DmaCmd,
- void *CallbackRef);
-
-#define XDMAPS_MAX_CHAN_BUFS 2
-#define XDMAPS_CHAN_BUF_LEN 128
-
-/**
- * The XDmaPs_ProgBuf is the struct for a DMA program buffer.
- */
-typedef struct {
- char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the
- * content */
- unsigned Len; /**< The actual length of the DMA
- * program in bytes. */
- int Allocated; /**< A tag indicating whether the
- * buffer is allocated or not */
-} XDmaPs_ProgBuf;
-
-/**
- * The XDmaPs_ChannelData is a struct to book keep individual channel of
- * the DMAC.
- */
-typedef struct {
- unsigned DevId; /**< Device id indicating which DMAC */
- unsigned ChanId; /**< Channel number of the DMAC */
- XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of
- program buffers*/
- XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */
- void *DoneRef; /**< Done interrupt callback data */
- XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */
- XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished.
- * This field is for debugging purpose
- */
- int HoldDmaProg; /**< A tag indicating whether to hold the
- * DMA program after the DMA is done.
- */
-
-} XDmaPs_ChannelData;
-
-/**
- * The XDmaPs driver instance data structure. A pointer to an instance data
- * structure is passed around by functions to refer to a specific driver
- * instance.
- */
-typedef struct {
- XDmaPs_Config Config; /**< Configuration data structure */
- int IsReady; /**< Device is Ready */
- int CacheLength; /**< icache length */
- XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */
- void *FaultRef; /**< fault call back data */
- XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV];
- /**<
- * channel data
- */
-} XDmaPs;
-
-/*
- * Functions implemented in xdmaps.c
- */
-int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
- XDmaPs_Config *Config,
- u32 EffectiveAddr);
-
-int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
- XDmaPs_Cmd *Cmd,
- int HoldDmaProg);
-
-int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel);
-int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel,
- XDmaPs_Cmd *Cmd);
-int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel,
- XDmaPs_Cmd *Cmd);
-void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
-
-
-int XDmaPs_ResetManager(XDmaPs *InstPtr);
-int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel);
-
-
-int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
- unsigned Channel,
- XDmaPsDoneHandler DoneHandler,
- void *CallbackRef);
-
-int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
- XDmaPsFaultHandler FaultHandler,
- void *CallbackRef);
-
-void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
-int XDmaPs_Instr_DMARMB(char *DmaProg);
-int XDmaPs_Instr_DMAWMB(char *DmaProg);
-
-/**
- * To avoid linkage error,modify all inline functions from extern
- * inline to static inline for IAR compiler
- */
-#ifdef __ICCARM__
-static INLINE int XDmaPs_Instr_DMAEND(char *DmaProg);
-static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src);
-static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
- u32 Imm, unsigned int Ns);
-static INLINE int XDmaPs_Instr_DMALD(char *DmaProg);
-static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
- unsigned LoopIterations);
-static INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc);
-static INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm);
-static INLINE int XDmaPs_Instr_DMANOP(char *DmaProg);
-static INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber);
-static INLINE int XDmaPs_Instr_DMAST(char *DmaProg);
-static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize);
-static INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize);
-#endif
-
-/**
- * Driver done interrupt service routines for the channels.
- * We need this done ISR mainly because the driver needs to release the
- * DMA program buffer. This is the one that connects the GIC
- */
-void XDmaPs_DoneISR_0(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_1(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_2(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_3(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_4(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_5(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_6(XDmaPs *InstPtr);
-void XDmaPs_DoneISR_7(XDmaPs *InstPtr);
-
-/**
- * Driver fault interrupt service routine
- */
-void XDmaPs_FaultISR(XDmaPs *InstPtr);
-
-
-/*
- * Static loopup function implemented in xdmaps_sinit.c
- */
-XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId);
-
-
-/*
- * self-test functions in xdmaps_selftest.c
- */
-int XDmaPs_SelfTest(XDmaPs *InstPtr);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d4/520cd5585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d4/520cd5585243001d18b399c1eb9b3628
deleted file mode 100644
index 7281ac4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d4/520cd5585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,17 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-#include
-
-/*
- * clock -- It supposed to return processor time. We are not implementing
- * this function, as timekeeping is tightly coupled with system, hence
- * always returning 0. Users can override this with their system
- * specific implementation.
- *
- */
-__weak clock_t clock(void)
-{
- return (0);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d4/62882f595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d4/62882f595243001d18b399c1eb9b3628
deleted file mode 100644
index 99b1375..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d4/62882f595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,113 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xbasic_types.h
-*
-*
-* @note Dummy File for backwards compatibility
-*
-
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
-* 7.0 aru 01/21/19 Modified the typedef of u32,u16,u8
-* 7.0 aru 02/06/19 Included stdint.h and stddef.h
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
-#define XBASIC_TYPES_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include
-#include
-
-/** @name Legacy types
- * Deprecated legacy types.
- * @{
- */
-typedef uint8_t Xuint8; /**< unsigned 8-bit */
-typedef char Xint8; /**< signed 8-bit */
-typedef uint16_t Xuint16; /**< unsigned 16-bit */
-typedef short Xint16; /**< signed 16-bit */
-typedef uint32_t Xuint32; /**< unsigned 32-bit */
-typedef long Xint32; /**< signed 32-bit */
-typedef float Xfloat32; /**< 32-bit floating point */
-typedef double Xfloat64; /**< 64-bit double precision FP */
-typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
-
-#if !defined __XUINT64__
-typedef struct
-{
- Xuint32 Upper;
- Xuint32 Lower;
-} Xuint64;
-#endif
-
-/** @name New types
- * New simple types.
- * @{
- */
-#ifndef __KERNEL__
-#ifndef XIL_TYPES_H
-typedef Xuint32 u32;
-typedef Xuint16 u16;
-typedef Xuint8 u8;
-#endif
-#else
-#include
-#endif
-
-#ifndef TRUE
-# define TRUE 1U
-#endif
-
-#ifndef FALSE
-# define FALSE 0U
-#endif
-
-#ifndef NULL
-#define NULL 0U
-#endif
-
-/*
- * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
- * Please use NULL, TRUE and FALSE
- */
-#define XNULL NULL
-#define XTRUE TRUE
-#define XFALSE FALSE
-
-/*
- * This file is deprecated and users
- * should use xil_types.h and xil_assert.h\n\r
- */
-#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
-#warning Please refer the Standalone BSP UG647 for further details
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d4/7157af545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d4/7157af545243001d18b399c1eb9b3628
deleted file mode 100644
index 9397afc..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d4/7157af545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,61 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/******************************************************************************/
-/**
-* @file xgpio_i.h
-* @addtogroup gpio_v4_8
-* @{
-*
-* This header file contains internal identifiers, which are those shared
-* between the files of the driver. It is intended for internal use only.
-*
-* NOTES:
-*
-* None.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 03/13/02 First release
-* 2.11a mta 03/21/07 Updated to new coding style
-*
-******************************************************************************/
-
-#ifndef XGPIO_I_H /* prevent circular inclusions */
-#define XGPIO_I_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xgpio.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions ****************************/
-
-extern XGpio_Config XGpio_ConfigTable[];
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d4/a184a9575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d4/a184a9575243001d18b399c1eb9b3628
deleted file mode 100644
index bb3765d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d4/a184a9575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,504 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xuartps.h
-* @addtogroup uartps_v3_11
-* @{
-* @details
-*
-* This driver supports the following features:
-*
-* - Dynamic data format (baud rate, data bits, stop bits, parity)
-* - Polled mode
-* - Interrupt driven mode
-* - Transmit and receive FIFOs (32 byte FIFO depth)
-* - Access to the external modem control lines
-*
-* Initialization & Configuration
-*
-* The XUartPs_Config structure is used by the driver to configure itself.
-* Fields inside this structure are properties of XUartPs based on its hardware
-* build.
-*
-* To support multiple runtime loading and initialization strategies employed
-* by various operating systems, the driver instance can be initialized in the
-* following way:
-*
-* - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-* configuration structure provided by the caller. If running in a system
-* with address translation, the parameter EffectiveAddr should be the
-* virtual address.
-*
-* Baud Rate
-*
-* The UART has an internal baud rate generator, which furnishes the baud rate
-* clock for both the receiver and the transmitter. The input clock frequency
-* can be either the master clock or the master clock divided by 8, configured
-* through the mode register.
-*
-* Accompanied with the baud rate divider register, the baud rate is determined
-* by:
-*
-* where bgen is the value of the baud rate generator, and bdiv is the value of
-* baud rate divider.
-*
-* Interrupts
-*
-* The FIFOs are not flushed when the driver is initialized, but a function is
-* provided to allow the user to reset the FIFOs if desired.
-*
-* The driver defaults to no interrupts at initialization such that interrupts
-* must be enabled if desired. An interrupt is generated for one of the
-* following conditions.
-*
-* - A change in the modem signals
-* - Data in the receive FIFO for a configuable time without receiver activity
-* - A parity error
-* - A framing error
-* - An overrun error
-* - Transmit FIFO is full
-* - Transmit FIFO is empty
-* - Receive FIFO is full
-* - Receive FIFO is empty
-* - Data in the receive FIFO equal to the receive threshold
-*
-* The application can control which interrupts are enabled using the
-* XUartPs_SetInterruptMask() function.
-*
-* In order to use interrupts, it is necessary for the user to connect the
-* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
-* system of the application. A separate handler should be provided by the
-* application to communicate with the interrupt system, and conduct
-* application specific interrupt handling. An application registers its own
-* handler through the XUartPs_SetHandler() function.
-*
-* Data Transfer
-*
-* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
-* driver to allow data to be sent and received. They can be used in either
-* polled or interrupt mode.
-*
-* @note
-*
-* The default configuration for the UART after initialization is:
-*
-* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
-* - 8 data bits
-* - 1 stop bit
-* - no parity
-* - FIFO's are enabled with a receive threshold of 8 bytes
-* - The RX timeout is enabled with a timeout of 1 (4 char times)
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00a drg/jz 01/12/10 First Release
-* 1.00a sdm 09/27/11 Fixed compiler warnings and also a bug
-* in XUartPs_SetFlowDelay where the value was not
-* being written to the register.
-* 1.01a sdm 12/20/11 Removed the InputClockHz parameter from the XUartPs
-* instance structure and the driver is updated to use
-* InputClockHz parameter from the XUartPs_Config config
-* structure.
-* Added a parameter to XUartPs_Config structure which
-* specifies whether the user has selected Modem pins
-* to be connected to MIO or FMIO.
-* Added the tcl file to generate the xparameters.h
-* 1.02a sg 05/16/12 Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
-* 1.03a sg 07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
-* with the correct values for CR 666724
-* Added defines for XUARTPS_IXR_TOVR, XUARTPS_IXR_TNFUL
-* and XUARTPS_IXR_TTRIG.
-* Modified the name of these defines
-* XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
-* XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
-* XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
-* XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
-* 1.05a hk 08/22/13 Added API for uart reset and related
-* constant definitions.
-* 2.0 hk 03/07/14 Version number revised.
-* 2.1 hk 04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
-* 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing
-* baud rate. CR# 804281.
-* 3.0 vm 12/09/14 Modified source code according to misrac guideline.
-* Support for Zynq Ultrascale Mp added.
-* 3.1 kvn 04/10/15 Modified code for latest RTL changes. Also added
-* platform variable in driver instance structure.
-* 3.1 adk 14/03/16 Include interrupt examples in the peripheral test when
-* uart is connected to a valid interrupt controller CR#946803.
-* 3.2 rk 07/20/16 Modified the logic for transmission break bit set
-* 3.4 ms 01/23/17 Added xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 3.6 ms 02/16/18 Updates the flow control mode offset value in modem
-* control register.
-* 3.7 aru 08/17/18 Resolved MISRA-C:2012 compliance mandatory violations.
-* 3.9 rna 12/03/19 Modified the XUARTPS_MAX_RATE macro.
-* 3.9 sd 02/06/20 Added clock support
-*
-*
-*
-*****************************************************************************/
-
-#ifndef XUARTPS_H /* prevent circular inclusions */
-#define XUARTPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xuartps_hw.h"
-#include "xplatform_info.h"
-#if defined (XCLOCKING)
-#include "xil_clocking.h"
-#endif
-
-/************************** Constant Definitions ****************************/
-
-/*
- * The following constants indicate the max and min baud rates and these
- * numbers are based only on the testing that has been done. The hardware
- * is capable of other baud rates.
- */
-#define XUARTPS_MAX_RATE 6240000U
-#define XUARTPS_MIN_RATE 110U
-
-#define XUARTPS_DFT_BAUDRATE 115200U /* Default baud rate */
-
-/** @name Configuration options
- * @{
- */
-/**
- * These constants specify the options that may be set or retrieved
- * with the driver, each is a unique bit mask such that multiple options
- * may be specified. These constants indicate the available options
- * in active state.
- *
- */
-
-#define XUARTPS_OPTION_SET_BREAK 0x0080U /**< Starts break transmission */
-#define XUARTPS_OPTION_STOP_BREAK 0x0040U /**< Stops break transmission */
-#define XUARTPS_OPTION_RESET_TMOUT 0x0020U /**< Reset the receive timeout */
-#define XUARTPS_OPTION_RESET_TX 0x0010U /**< Reset the transmitter */
-#define XUARTPS_OPTION_RESET_RX 0x0008U /**< Reset the receiver */
-#define XUARTPS_OPTION_ASSERT_RTS 0x0004U /**< Assert the RTS bit */
-#define XUARTPS_OPTION_ASSERT_DTR 0x0002U /**< Assert the DTR bit */
-#define XUARTPS_OPTION_SET_FCM 0x0001U /**< Turn on flow control mode */
-/*@}*/
-
-
-/** @name Channel Operational Mode
- *
- * The UART can operate in one of four modes: Normal, Local Loopback, Remote
- * Loopback, or automatic echo.
- *
- * @{
- */
-
-#define XUARTPS_OPER_MODE_NORMAL (u8)0x00U /**< Normal Mode */
-#define XUARTPS_OPER_MODE_AUTO_ECHO (u8)0x01U /**< Auto Echo Mode */
-#define XUARTPS_OPER_MODE_LOCAL_LOOP (u8)0x02U /**< Local Loopback Mode */
-#define XUARTPS_OPER_MODE_REMOTE_LOOP (u8)0x03U /**< Remote Loopback Mode */
-
-/* @} */
-
-/** @name Data format values
- *
- * These constants specify the data format that the driver supports.
- * The data format includes the number of data bits, the number of stop
- * bits and parity.
- *
- * @{
- */
-#define XUARTPS_FORMAT_8_BITS 0U /**< 8 data bits */
-#define XUARTPS_FORMAT_7_BITS 2U /**< 7 data bits */
-#define XUARTPS_FORMAT_6_BITS 3U /**< 6 data bits */
-
-#define XUARTPS_FORMAT_NO_PARITY 4U /**< No parity */
-#define XUARTPS_FORMAT_MARK_PARITY 3U /**< Mark parity */
-#define XUARTPS_FORMAT_SPACE_PARITY 2U /**< parity */
-#define XUARTPS_FORMAT_ODD_PARITY 1U /**< Odd parity */
-#define XUARTPS_FORMAT_EVEN_PARITY 0U /**< Even parity */
-
-#define XUARTPS_FORMAT_2_STOP_BIT 2U /**< 2 stop bits */
-#define XUARTPS_FORMAT_1_5_STOP_BIT 1U /**< 1.5 stop bits */
-#define XUARTPS_FORMAT_1_STOP_BIT 0U /**< 1 stop bit */
-/*@}*/
-
-/** @name Callback events
- *
- * These constants specify the handler events that an application can handle
- * using its specific handler function. Note that these constants are not bit
- * mask, so only one event can be passed to an application at a time.
- *
- * @{
- */
-#define XUARTPS_EVENT_RECV_DATA 1U /**< Data receiving done */
-#define XUARTPS_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */
-#define XUARTPS_EVENT_SENT_DATA 3U /**< Data transmission done */
-#define XUARTPS_EVENT_RECV_ERROR 4U /**< A receive error detected */
-#define XUARTPS_EVENT_MODEM 5U /**< Modem status changed */
-#define XUARTPS_EVENT_PARE_FRAME_BRKE 6U /**< A receive parity, frame, break
- * error detected */
-#define XUARTPS_EVENT_RECV_ORERR 7U /**< A receive overrun error detected */
-
-/*@}*/
-
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of device (IPIF) */
- u32 InputClockHz;/**< Input clock frequency */
- s32 ModemPinsConnected; /** Specifies whether modem pins are connected
- * to MIO or FMIO */
-#if defined (XCLOCKING)
- u32 RefClk; /**< Input clock frequency */
-#endif
-} XUartPs_Config;
-
-/* Keep track of state information about a data buffer in the interrupt mode. */
-typedef struct {
- u8 *NextBytePtr;
- u32 RequestedBytes;
- u32 RemainingBytes;
-} XUartPsBuffer;
-
-/**
- * Keep track of data format setting of a device.
- */
-typedef struct {
- u32 BaudRate; /**< In bps, ie 1200 */
- u32 DataBits; /**< Number of data bits */
- u32 Parity; /**< Parity */
- u8 StopBits; /**< Number of stop bits */
-} XUartPsFormat;
-
-/******************************************************************************/
-/**
- * This data type defines a handler that an application defines to communicate
- * with interrupt system to retrieve state information about an application.
- *
- * @param CallBackRef is a callback reference passed in by the upper layer
- * when setting the handler, and is passed back to the upper layer
- * when the handler is called. It is used to find the device driver
- * instance.
- * @param Event contains one of the event constants indicating events that
- * have occurred.
- * @param EventData contains the number of bytes sent or received at the
- * time of the call for send and receive events and contains the
- * modem status for modem events.
- *
- ******************************************************************************/
-typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
- u32 EventData);
-
-/**
- * The XUartPs driver instance data structure. A pointer to an instance data
- * structure is passed around by functions to refer to a specific driver
- * instance.
- */
-typedef struct {
- XUartPs_Config Config; /* Configuration data structure */
- u32 InputClockHz; /* Input clock frequency */
- u32 IsReady; /* Device is initialized and ready */
- u32 BaudRate; /* Current baud rate */
-
- XUartPsBuffer SendBuffer;
- XUartPsBuffer ReceiveBuffer;
-
- XUartPs_Handler Handler;
- void *CallBackRef; /* Callback reference for event handler */
- u32 Platform;
- u8 is_rxbs_error;
-} XUartPs;
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* Get the UART Channel Status Register.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_GetChannelStatus(InstancePtr) \
- Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
-
-/****************************************************************************/
-/**
-* Get the UART Mode Control Register.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return The value read from the register.
-*
-* @note C-Style signature:
-* u32 XUartPs_GetControl(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_GetModeControl(InstancePtr) \
- Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
-
-/****************************************************************************/
-/**
-* Set the UART Mode Control Register.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
-*
-******************************************************************************/
-#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
- Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
- (u32)(RegisterValue))
-
-/****************************************************************************/
-/**
-* Enable the transmitter and receiver of the UART.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_EnableUart(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_EnableUart(InstancePtr) \
- Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
- ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
- (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
-
-/****************************************************************************/
-/**
-* Disable the transmitter and receiver of the UART.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XUartPs_DisableUart(XUartPs *InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_DisableUart(InstancePtr) \
- Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
- (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
- (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
-
-/****************************************************************************/
-/**
-* Determine if the transmitter FIFO is empty.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-*
-* @return
-* - TRUE if a byte can be sent
-* - FALSE if the Transmitter Fifo is not empty
-*
-* @note C-Style signature:
-* u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
-*
-******************************************************************************/
-#define XUartPs_IsTransmitEmpty(InstancePtr) \
- ((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
- (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
-
-
-/************************** Function Prototypes *****************************/
-
-/* Static lookup function implemented in xuartps_sinit.c */
-XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
-
-/* Interface functions implemented in xuartps.c */
-s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
- XUartPs_Config * Config, u32 EffectiveAddr);
-
-u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
- u32 NumBytes);
-
-u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
- u32 NumBytes);
-
-s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
-
-/* Options functions in xuartps_options.c */
-void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
-
-u16 XUartPs_GetOptions(XUartPs *InstancePtr);
-
-void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
-
-u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
-
-u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
-
-u32 XUartPs_IsSending(XUartPs *InstancePtr);
-
-u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
-
-void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
-
-u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
-
-void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
-
-u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
-
-void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
-
-s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
-
-void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
-
-/* interrupt functions in xuartps_intr.c */
-u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
-
-void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
-
-void XUartPs_InterruptHandler(XUartPs *InstancePtr);
-
-void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
- void *CallBackRef);
-
-/* self-test functions in xuartps_selftest.c */
-s32 XUartPs_SelfTest(XUartPs *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d5/110cb5595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d5/110cb5595243001d18b399c1eb9b3628
deleted file mode 100644
index 5a1bda3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d5/110cb5595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,76 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_testio.h
-*
-* @addtogroup common_test_utils Test Utilities for Memory and Caches
-*
I/O test
-* The xil_testio.h file contains utility functions to test endian related memory
-* IO functions.
-*
-* A subset of the memory tests can be selected or all of the tests can be run
-* in order. If there is an error detected by a subtest, the test stops and the
-* failure code is returned. Further tests are not run even if all of the tests
-* are selected.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00 hbm 08/05/09 First release
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_TESTIO_H /* prevent circular inclusions */
-#define XIL_TESTIO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-
-
-#define XIL_TESTIO_DEFAULT 0
-#define XIL_TESTIO_LE 1
-#define XIL_TESTIO_BE 2
-
-/**
- *@endcond
- */
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
-extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
-extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_test_utils".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d5/146bcc565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d5/146bcc565243001d18b399c1eb9b3628
deleted file mode 100644
index 26966bf..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d5/146bcc565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,81 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file usleep.c
-*
-* This function provides a microsecond delay using the Global Timer register in
-* the ARM Cortex A9 MP core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm 11/11/09 First release
-* 3.07a sgd 07/05/12 Updated micro sleep function to make use Global Timer
-* 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine as it is not
-* possible to generate timer in nanosecond due to
-* limited cpu frequency
-* 6.0 asa 08/15/16 Updated the usleep signature. Fix for CR#956899.
-* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
-* implementation. Now sleep routines will use Timer
-* specified by the user (i.e. Global timer/TTC timer)
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "sleep.h"
-#include "xtime_l.h"
-#include "xparameters.h"
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#include "xreg_cortexa9.h"
-
-#if defined (SLEEP_TIMER_BASEADDR)
-#include "xil_sleeptimer.h"
-#endif
-
-/**************************** Constant Definitions ************************/
-#if defined (SLEEP_TIMER_BASEADDR)
-#define COUNTS_PER_USECOND (SLEEP_TIMER_FREQUENCY / 1000000)
-#else
-/* Global Timer is always clocked at half of the CPU frequency */
-#define COUNTS_PER_USECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / (2U*1000000U))
-#endif
-
-/*****************************************************************************/
-/**
-*
-* This API gives a delay in microseconds
-*
-* @param useconds requested
-*
-* @return 0 if the delay can be achieved, -1 if the requested delay
-* is out of range
-*
-* @note None.
-*
-****************************************************************************/
-int usleep_A9(unsigned long useconds)
-{
-#if defined (SLEEP_TIMER_BASEADDR)
- Xil_SleepTTCCommon(useconds, COUNTS_PER_USECOND);
-#else
- XTime tEnd, tCur;
-
- XTime_GetTime(&tCur);
- tEnd = tCur + (((XTime) useconds) * COUNTS_PER_USECOND);
- do
- {
- XTime_GetTime(&tCur);
- } while (tCur < tEnd);
-#endif
-
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d5/257695595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d5/257695595243001d18b399c1eb9b3628
deleted file mode 100644
index 9794da0..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d5/257695595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,350 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xenv_standalone.h
-*
-* Defines common services specified by xenv.h.
-*
-* @note
-* This file is not intended to be included directly by driver code.
-* Instead, the generic xenv.h file is intended to be included by driver
-* code.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a wgr 02/28/07 Added cache handling macros.
-* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
-* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
-* used under Xilinx standalone BSP.
-* 1.00a xd 11/03/04 Improved support for doxygen.
-* 1.00a rmm 03/21/02 First release
-* 1.00a wgr 03/22/07 Converted to new coding style.
-* 1.00a rpm 06/29/07 Added udelay macro for standalone
-* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
-* to in MICROBLAZE section
-* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
-*
-*
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XENV_STANDALONE_H
-#define XENV_STANDALONE_H
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-/******************************************************************************
- *
- * Get the processor dependent includes
- *
- ******************************************************************************/
-
-#include
-
-#if defined __MICROBLAZE__
-# include "mb_interface.h"
-# include "xparameters.h" /* XPAR constants used below in MB section */
-
-#elif defined __PPC__
-# include "sleep.h"
-# include "xcache_l.h" /* also include xcache_l.h for caching macros */
-#endif
-
-/******************************************************************************
- *
- * MEMCPY / MEMSET related macros.
- *
- * The following are straight forward implementations of memset and memcpy.
- *
- * NOTE: memcpy may not work if source and target memory area are overlapping.
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
- *
- * Copies a non-overlapping block of memory.
- *
- * @param DestPtr
- * Destination address to copy data to.
- *
- * @param SrcPtr
- * Source address to copy data from.
- *
- * @param Bytes
- * Number of bytes to copy.
- *
- * @return None.
- *
- * @note
- * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
- *
- * @note
- * This implementation MAY BREAK work if source and target memory
- * area are overlapping.
- *
- *****************************************************************************/
-
-#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
- memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
-
-
-
-/*****************************************************************************/
-/**
- *
- * Fills an area of memory with constant data.
- *
- * @param DestPtr
- * Destination address to copy data to.
- *
- * @param Data
- * Value to set.
- *
- * @param Bytes
- * Number of bytes to copy.
- *
- * @return None.
- *
- * @note
- * The use of XENV_MEM_FILL is deprecated. Use memset() instead.
- *
- *****************************************************************************/
-
-#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
- memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
-
-
-
-/******************************************************************************
- *
- * TIME related macros
- *
- ******************************************************************************/
-
-/**
- * A structure that contains a time stamp used by other time stamp macros
- * defined below. This structure is processor dependent.
- */
-typedef s32 XENV_TIME_STAMP;
-
-/*****************************************************************************/
-/**
- *
- * Time is derived from the 64 bit PPC timebase register
- *
- * @param StampPtr is the storage for the retrieved time stamp.
- *
- * @return None.
- *
- * @note
- *
- * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_GET(StampPtr)
-
-/*****************************************************************************/
-/**
- *
- * This macro is not yet implemented and always returns 0.
- *
- * @param Stamp1Ptr is the first sampled time stamp.
- * @param Stamp2Ptr is the second sampled time stamp.
- *
- * @return 0
- *
- * @note
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
-
-/*****************************************************************************/
-/**
- *
- * This macro is not yet implemented and always returns 0.
- *
- * @param Stamp1Ptr is the first sampled time stamp.
- * @param Stamp2Ptr is the second sampled time stamp.
- *
- * @return 0
- *
- * @note
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
-
-/*****************************************************************************/
-/**
- * XENV_USLEEP(unsigned delay)
- *
- * Delay the specified number of microseconds. Not implemented without OS
- * support.
- *
- * @param delay
- * Number of microseconds to delay.
- *
- * @return None.
- *
- *****************************************************************************/
-
-#ifdef __PPC__
-#define XENV_USLEEP(delay) usleep(delay)
-#define udelay(delay) usleep(delay)
-#else
-#define XENV_USLEEP(delay)
-#define udelay(delay)
-#endif
-
-
-/******************************************************************************
- *
- * CACHE handling macros / mappings
- *
- ******************************************************************************/
-/******************************************************************************
- *
- * Processor independent macros
- *
- ******************************************************************************/
-
-#define XCACHE_ENABLE_CACHE() \
- { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
-
-#define XCACHE_DISABLE_CACHE() \
- { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
-
-
-/******************************************************************************
- *
- * MicroBlaze case
- *
- * NOTE: Currently the following macros will only work on systems that contain
- * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
- * system is built using a xparameters.h file.
- *
- ******************************************************************************/
-
-#if defined __MICROBLAZE__
-
-/* Check if MicroBlaze data cache was built into the core.
- */
-#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
-# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
-# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
-# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
-
-# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
- microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
-
-#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
-# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
-#else
-# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
-#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
-
-#else
-# define XCACHE_ENABLE_DCACHE()
-# define XCACHE_DISABLE_DCACHE()
-# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
-#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
-
-
-/* Check if MicroBlaze instruction cache was built into the core.
- */
-#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
-# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
-# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
-
-# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
-
-# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
- microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
-
-#else
-# define XCACHE_ENABLE_ICACHE()
-# define XCACHE_DISABLE_ICACHE()
-#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
-
-
-/******************************************************************************
- *
- * PowerPC case
- *
- * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
- * specific memory region (0x80000001). Each bit (0-30) in the regions
- * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
- * range.
- *
- * regions --> cached address range
- * ------------|--------------------------------------------------
- * 0x80000000 | [0, 0x7FFFFFF]
- * 0x00000001 | [0xF8000000, 0xFFFFFFFF]
- * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
- *
- ******************************************************************************/
-
-#elif defined __PPC__
-
-#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
-#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
-#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
-#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
-
-#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
- XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
-
-#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
-
-#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
-
-
-/******************************************************************************
- *
- * Unknown processor / architecture
- *
- ******************************************************************************/
-
-#else
-/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* #ifndef XENV_STANDALONE_H */
-
- /**
- *@endcond
- */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d5/40c677575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d5/40c677575243001d18b399c1eb9b3628
deleted file mode 100644
index 9d33a6c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d5/40c677575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,193 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xgpio.h
-* @addtogroup gpio_v4_8
-* @{
-* @details
-*
-* This file contains the software API definition of the Xilinx General Purpose
-* I/O (XGpio) device driver.
-*
-* The Xilinx GPIO controller is a soft IP core designed for Xilinx FPGAs and
-* contains the following general features:
-* - Support for up to 32 I/O discretes for each channel (64 bits total).
-* - Each of the discretes can be configured for input or output.
-* - Configurable support for dual channels and interrupt generation.
-*
-* The driver provides interrupt management functions. Implementation of
-* interrupt handlers is left to the user. Refer to the provided interrupt
-* example in the examples directory for details.
-*
-* This driver is intended to be RTOS and processor independent. Any needs for
-* dynamic memory management, threads or thread mutual exclusion, virtual
-* memory, or cache control must be satisfied by the layer above this driver.
-*
-* Initialization & Configuration
-*
-* The XGpio_Config structure is used by the driver to configure itself. This
-* configuration structure is typically created by the tool-chain based on HW
-* build properties.
-*
-* To support multiple runtime loading and initialization strategies employed
-* by various operating systems, the driver instance can be initialized in one
-* of the following ways:
-*
-* - XGpio_Initialize(InstancePtr, DeviceId) - The driver looks up its own
-* configuration structure created by the tool-chain based on an ID provided
-* by the tool-chain.
-*
-* - XGpio_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-* configuration structure provided by the caller. If running in a system
-* with address translation, the provided virtual memory base address
-* replaces the physical address present in the configuration structure.
-*
-* @note
-*
-* This API utilizes 32 bit I/O to the GPIO registers. With less than 32 bits,
-* the unused bits from registers are read as zero and written as don't cares.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 03/13/02 First release
-* 2.00a jhl 11/26/03 Added support for dual channels and interrupts
-* 2.01a jvb 12/14/05 I separated dependency on the static config table and
-* xparameters.h from the driver initialization by moving
-* _Initialize and _LookupConfig to _sinit.c. I also added
-* the new _CfgInitialize routine.
-* 2.11a mta 03/21/07 Updated to new coding style, added GetDataDirection
-* 2.12a sv 11/21/07 Updated driver to support access through DCR bus
-* 2.12a sv 06/05/08 Updated driver to fix the XGpio_InterruptDisable function
-* to properly update the Interrupt Enable register
-* 2.13a sdm 08/22/08 Removed support for static interrupt handlers from the MDD
-* file
-* 3.00a sv 11/21/09 Updated to use HAL Processor APIs.
-* Renamed the macros XGpio_mWriteReg to XGpio_WriteReg and
-* XGpio_mReadReg to XGpio_ReadReg. Removed the macros
-* XGpio_mSetDataDirection, XGpio_mGetDataReg and
-* XGpio_mSetDataReg. Users should use XGpio_WriteReg and
-* XGpio_ReadReg to achieve the same functionality.
-* 3.01a bss 04/18/13 Updated driver tcl to generate Canonical params in
-* xparameters.h. CR#698589
-* 4.0 adk 19/12/13 Updated as per the New Tcl API's
-* 4.1 lks 11/18/15 Updated to use canonical xparameters in examples and
-* clean up of the comments, removed support for DCR bridge
-* and removed xgpio_intr_example for CR 900381
-* 4.2 sk 08/16/16 Used UINTPTR instead of u32 for Baseaddress as part of
-* adding 64 bit support. CR# 867425.
-* Changed the prototype of XGpio_CfgInitialize API.
-* 4.3 sk 09/29/16 Modified the example to make it work when LED_bits are
-* configured as an output. CR# 958644
-* ms 01/23/17 Added xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 4.4 sne 04/25/19 Updated Makefile for IAR compier (CR-1029421).
-* 4.5 sne 06/14/19 Fixed IAR compiler warnings on example files.
-* 4.6 sne 08/11/19 Fixed compilation error of armcc compiler.
-* 4.7 sne 08/28/20 Modify Makefile to support parallel make execution.
-* 4.8 sne 02/10/21 Fixed doxygen warnings.
-*
-*
-*****************************************************************************/
-
-#ifndef XGPIO_H /* prevent circular inclusions */
-#define XGPIO_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xgpio_l.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- UINTPTR BaseAddress; /**< Device base address */
- int InterruptPresent; /**< Are interrupts supported in h/w */
- int IsDual; /**< Are 2 channels supported in h/w */
-} XGpio_Config;
-
-/**
- * The XGpio driver instance data. The user is required to allocate a
- * variable of this type for every GPIO device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- UINTPTR BaseAddress; /**< Device base address */
- u32 IsReady; /**< Device is initialized and ready */
- int InterruptPresent; /**< Are interrupts supported in h/w */
- int IsDual; /**< Are 2 channels supported in h/w */
-} XGpio;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Function Prototypes *****************************/
-
-/*
- * Initialization functions in xgpio_sinit.c
- */
-int XGpio_Initialize(XGpio *InstancePtr, u16 DeviceId);
-XGpio_Config *XGpio_LookupConfig(u16 DeviceId);
-
-/*
- * API Basic functions implemented in xgpio.c
- */
-int XGpio_CfgInitialize(XGpio *InstancePtr, XGpio_Config * Config,
- UINTPTR EffectiveAddr);
-void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
- u32 DirectionMask);
-u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel);
-u32 XGpio_DiscreteRead(XGpio *InstancePtr, unsigned Channel);
-void XGpio_DiscreteWrite(XGpio *InstancePtr, unsigned Channel, u32 Mask);
-
-
-/*
- * API Functions implemented in xgpio_extra.c
- */
-void XGpio_DiscreteSet(XGpio *InstancePtr, unsigned Channel, u32 Mask);
-void XGpio_DiscreteClear(XGpio *InstancePtr, unsigned Channel, u32 Mask);
-
-/*
- * API Functions implemented in xgpio_selftest.c
- */
-int XGpio_SelfTest(XGpio *InstancePtr);
-
-/*
- * API Functions implemented in xgpio_intr.c
- */
-void XGpio_InterruptGlobalEnable(XGpio *InstancePtr);
-void XGpio_InterruptGlobalDisable(XGpio *InstancePtr);
-void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask);
-void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask);
-void XGpio_InterruptClear(XGpio *InstancePtr, u32 Mask);
-u32 XGpio_InterruptGetEnabled(XGpio *InstancePtr);
-u32 XGpio_InterruptGetStatus(XGpio *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d5/615667585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d5/615667585243001d18b399c1eb9b3628
deleted file mode 100644
index 01b5ba6..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d5/615667585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,732 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.c
-*
-* Contains required functions for the ARM cache functionality.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.0 pkp 05/29/14 First release
-* 5.5 pkp 04/15/16 Updated the Xil_DCacheInvalidate,
-* Xil_DCacheInvalidateLine and Xil_DCacheInvalidateRange
-* functions description for proper explanation
-* 6.2 pkp 01/22/17 Added support for EL1 non-secure
-* 6.2 asa 01/31/17 The existing Xil_DCacheDisable API first flushes the
-* D caches and then disables it. The problem with that is,
-* potentially there will be a small window after the cache
-* flush operation and before the we disable D caches where
-* we might have valid data in cache lines. In such a
-* scenario disabling the D cache can lead to unknown behavior.
-* The ideal solution to this is to use assembly code for
-* the complete API and avoid any memory accesses. But with
-* that we will end up having a huge amount on assembly code
-* which is not maintainable. Changes are done to use a mix
-* of assembly and C code. All local variables are put in
-* registers. Also function calls are avoided in the API to
-* avoid using stack memory.
-* These changes fix CR#966220.
-* 6.2 mus 02/13/17 The new api Xil_ConfigureL1Prefetch is added to disable pre-fetching/configure
-* the maximum number of outstanding data prefetches allowed in
-* L1 cache system.It fixes CR#967864.
-* 6.6 mus 02/27/18 Updated Xil_DCacheInvalidateRange and
-* Xil_ICacheInvalidateRange APIs to change the data type of
-* "cacheline" variable as "INTPTR", This change has been done
-* to avoid the truncation of upper DDR addresses to 32 bit.It
-* fixes CR#995581.
-* 6.6 mus 03/15/18 By default CPUACTLR_EL1 is accessible only from EL3, it
-* results into abort if accessed from EL1 non secure privilege
-* level. Updated Xil_ConfigureL1Prefetch function to access
-* CPUACTLR_EL1 only for EL3.
-* 6.8 mn 08/01/18 Optimize the Xil_DCacheInvalidateRange() function to remove
-* redundant operations
-* 6.8 asa 09/15/18 Fix bug in the Xil_DCacheInvalidateRange API introduced while
-* making optimizations in the previous patch. This change fixes
-* CR-1008926.
-* 7.0 mus 10/12/18 Updated Xil_DCacheInvalidateLine and Xil_DCacheInvalidateRange
-* APIs to replace IVAC instruction with CIVAC. So that, these
-* APIs will always do flush + invalidate in case of Cortexa53 as
-* well as Cortexa72 processor.
-* 7.1 mus 09/17/19 Xil_DCacheFlushRange and Xil_DCacheInvalidateRange are executing
-* same functionality (clean + validate). Removed
-* Xil_DCacheFlushRange function implementation and defined it as
-* macro. Xil_DCacheFlushRange macro points to the
-* Xil_DCacheInvalidateRange API to avoid code duplication.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xil_io.h"
-#include "xpseudo_asm.h"
-#include "xparameters.h"
-#include "xreg_cortexa53.h"
-#include "xil_exception.h"
-#include "bspconfig.h"
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-#define IRQ_FIQ_MASK 0xC0U /* Mask IRQ and FIQ interrupts in cpsr */
-
-/****************************************************************************/
-/**
-* @brief Enable the Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheEnable(void)
-{
- u32 CtrlReg;
-
- if (EL3 == 1) {
- CtrlReg = mfcp(SCTLR_EL3);
- } else if (EL1_NONSECURE == 1) {
- CtrlReg = mfcp(SCTLR_EL1);
- } else {
- CtrlReg = 0U;
- }
-
- /* enable caches only if they are disabled */
- if((CtrlReg & XREG_CONTROL_DCACHE_BIT) == 0X00000000U){
-
- /* invalidate the Data cache */
- Xil_DCacheInvalidate();
-
- CtrlReg |= XREG_CONTROL_DCACHE_BIT;
-
- if (EL3 == 1) {
- /* enable the Data cache for el3*/
- mtcp(SCTLR_EL3,CtrlReg);
- } else if (EL1_NONSECURE == 1) {
- /* enable the Data cache for el1*/
- mtcp(SCTLR_EL1,CtrlReg);
- }
- }
-}
-
-/****************************************************************************/
-/**
-* @brief Disable the Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheDisable(void)
-{
- register u32 CsidReg;
- register u32 C7Reg;
- register u32 LineSize;
- register u32 NumWays;
- register u32 Way;
- register u32 WayIndex;
- register u32 WayAdjust;
- register u32 Set;
- register u32 SetIndex;
- register u32 NumSet;
- register u32 CacheLevel;
-
- dsb();
- asm(
- "mov x0, #0\n\t"
-#if EL3==1
- "mrs x0, sctlr_el3 \n\t"
- "and w0, w0, #0xfffffffb\n\t"
- "msr sctlr_el3, x0\n\t"
-#elif EL1_NONSECURE==1
- "mrs x0, sctlr_el1 \n\t"
- "and w0, w0, #0xfffffffb\n\t"
- "msr sctlr_el1, x0\n\t"
-#endif
- "dsb sy\n\t"
- );
-
- /* Number of level of cache*/
- CacheLevel = 0U;
- /* Select cache level 0 and D cache in CSSR */
- mtcp(CSSELR_EL1,CacheLevel);
- isb();
-
- CsidReg = mfcp(CCSIDR_EL1);
-
- /* Get the cacheline size, way size, index size from csidr */
- LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
-
- /* Number of Ways */
- NumWays = (CsidReg & 0x00001FFFU) >> 3U;
- NumWays += 0x00000001U;
-
- /*Number of Set*/
- NumSet = (CsidReg >> 13U) & 0x00007FFFU;
- NumSet += 0x00000001U;
-
- WayAdjust = clz(NumWays) - (u32)0x0000001FU;
-
- Way = 0U;
- Set = 0U;
-
- /* Flush all the cachelines */
- for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set | CacheLevel;
- mtcpdc(CISW,C7Reg);
- Set += (0x00000001U << LineSize);
- }
- Set = 0U;
- Way += (0x00000001U << WayAdjust);
- }
-
- /* Wait for Flush to complete */
- dsb();
-
- /* Select cache level 1 and D cache in CSSR */
- CacheLevel += (0x00000001U << 1U);
- mtcp(CSSELR_EL1,CacheLevel);
- isb();
-
- CsidReg = mfcp(CCSIDR_EL1);
-
- /* Get the cacheline size, way size, index size from csidr */
- LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
-
- /* Number of Ways */
- NumWays = (CsidReg & 0x00001FFFU) >> 3U;
- NumWays += 0x00000001U;
-
- /* Number of Sets */
- NumSet = (CsidReg >> 13U) & 0x00007FFFU;
- NumSet += 0x00000001U;
-
- WayAdjust=clz(NumWays) - (u32)0x0000001FU;
-
- Way = 0U;
- Set = 0U;
-
- /* Flush all the cachelines */
- for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set | CacheLevel;
- mtcpdc(CISW,C7Reg);
- Set += (0x00000001U << LineSize);
- }
- Set=0U;
- Way += (0x00000001U<> 3U;
- NumWays += 0X00000001U;
-
- /*Number of Set*/
- NumSet = (CsidReg >> 13U) & 0x00007FFFU;
- NumSet += 0X00000001U;
-
- WayAdjust = clz(NumWays) - (u32)0x0000001FU;
-
- Way = 0U;
- Set = 0U;
-
- /* Invalidate all the cachelines */
- for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set | CacheLevel;
- mtcpdc(ISW,C7Reg);
- Set += (0x00000001U << LineSize);
- }
- Set = 0U;
- Way += (0x00000001U << WayAdjust);
- }
-
- /* Wait for invalidate to complete */
- dsb();
-
- /* Select cache level 1 and D cache in CSSR */
- CacheLevel += (0x00000001U<<1U) ;
- mtcp(CSSELR_EL1,CacheLevel);
- isb();
-
- CsidReg = mfcp(CCSIDR_EL1);
-
- /* Get the cacheline size, way size, index size from csidr */
- LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
-
- /* Number of Ways */
- NumWays = (CsidReg & 0x00001FFFU) >> 3U;
- NumWays += 0x00000001U;
-
- /* Number of Sets */
- NumSet = (CsidReg >> 13U) & 0x00007FFFU;
- NumSet += 0x00000001U;
-
- WayAdjust = clz(NumWays) - (u32)0x0000001FU;
-
- Way = 0U;
- Set = 0U;
-
- /* Invalidate all the cachelines */
- for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set | CacheLevel;
- mtcpdc(ISW,C7Reg);
- Set += (0x00000001U << LineSize);
- }
- Set = 0U;
- Way += (0x00000001U << WayAdjust);
- }
- /* Wait for invalidate to complete */
- dsb();
-
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate a Data cache line. The cacheline is cleaned and
-* invalidated.
-*
-* @param adr: 64bit address of the data to be flushed.
-*
-* @return None.
-*
-* @note In Cortex-A53, functionality to simply invalid the cachelines
-* is not present. Such operations are a problem for an environment
-* that supports virtualisation. It would allow one OS to invalidate
-* a line belonging to another OS. This could lead to the other OS
-* crashing because of the loss of essential data. Hence, such
-* operations are promoted to clean and invalidate which avoids such
-* corruption.
-*
-****************************************************************************/
-void Xil_DCacheInvalidateLine(INTPTR adr)
-{
-
- u32 currmask;
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
- /* Select cache level 0 and D cache in CSSR */
- mtcp(CSSELR_EL1,0x0);
- mtcpdc(CIVAC,(adr & (~0x3F)));
- /* Wait for invalidate to complete */
- dsb();
- /* Select cache level 1 and D cache in CSSR */
- mtcp(CSSELR_EL1,0x2);
- mtcpdc(IVAC,(adr & (~0x3F)));
- /* Wait for invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Invalidate the Data cache for the given address range.
-* The cachelines present in the adderss range are cleaned and
-* invalidated
-*
-* @param adr: 64bit start address of the range to be invalidated.
-* @param len: Length of the range to be invalidated in bytes.
-*
-* @return None.
-*
-* @note In Cortex-A53, functionality to simply invalid the cachelines
-* is not present. Such operations are a problem for an environment
-* that supports virtualisation. It would allow one OS to invalidate
-* a line belonging to another OS. This could lead to the other OS
-* crashing because of the loss of essential data. Hence, such
-* operations are promoted to clean and invalidate which avoids such
-* corruption.
-*
-****************************************************************************/
-void Xil_DCacheInvalidateRange(INTPTR adr, INTPTR len)
-{
- const INTPTR cacheline = 64U;
- INTPTR end = adr + len;
- adr = adr & (~0x3F);
- u32 currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
- if (len != 0U) {
- while (adr < end) {
- mtcpdc(CIVAC,adr);
- adr += cacheline;
- }
- }
- /* Wait for invalidate to complete */
- dsb();
- mtcpsr(currmask);
-}
-
-/****************************************************************************/
-/**
-* @brief Flush the Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_DCacheFlush(void)
-{
- register u32 CsidReg, C7Reg;
- u32 LineSize, NumWays;
- u32 Way, WayIndex,WayAdjust, Set, SetIndex, NumSet, CacheLevel;
- u32 currmask;
-
- currmask = mfcpsr();
- mtcpsr(currmask | IRQ_FIQ_MASK);
-
-
- /* Number of level of cache*/
-
- CacheLevel = 0U;
- /* Select cache level 0 and D cache in CSSR */
- mtcp(CSSELR_EL1,CacheLevel);
- isb();
-
- CsidReg = mfcp(CCSIDR_EL1);
-
- /* Get the cacheline size, way size, index size from csidr */
- LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
-
- /* Number of Ways */
- NumWays = (CsidReg & 0x00001FFFU) >> 3U;
- NumWays += 0x00000001U;
-
- /*Number of Set*/
- NumSet = (CsidReg >> 13U) & 0x00007FFFU;
- NumSet += 0x00000001U;
-
- WayAdjust = clz(NumWays) - (u32)0x0000001FU;
-
- Way = 0U;
- Set = 0U;
-
- /* Flush all the cachelines */
- for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set | CacheLevel;
- mtcpdc(CISW,C7Reg);
- Set += (0x00000001U << LineSize);
- }
- Set = 0U;
- Way += (0x00000001U << WayAdjust);
- }
-
- /* Wait for Flush to complete */
- dsb();
-
- /* Select cache level 1 and D cache in CSSR */
- CacheLevel += (0x00000001U << 1U);
- mtcp(CSSELR_EL1,CacheLevel);
- isb();
-
- CsidReg = mfcp(CCSIDR_EL1);
-
- /* Get the cacheline size, way size, index size from csidr */
- LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
-
- /* Number of Ways */
- NumWays = (CsidReg & 0x00001FFFU) >> 3U;
- NumWays += 0x00000001U;
-
- /* Number of Sets */
- NumSet = (CsidReg >> 13U) & 0x00007FFFU;
- NumSet += 0x00000001U;
-
- WayAdjust=clz(NumWays) - (u32)0x0000001FU;
-
- Way = 0U;
- Set = 0U;
-
- /* Flush all the cachelines */
- for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
- for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
- C7Reg = Way | Set | CacheLevel;
- mtcpdc(CISW,C7Reg);
- Set += (0x00000001U << LineSize);
- }
- Set=0U;
- Way += (0x00000001U<
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.6 srm 11/02/17 First release
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm 03/10/10 First release
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a wgr 02/28/07 Added cache handling macros.
-* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
-* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
-* used under Xilinx standalone BSP.
-* 1.00a xd 11/03/04 Improved support for doxygen.
-* 1.00a rmm 03/21/02 First release
-* 1.00a wgr 03/22/07 Converted to new coding style.
-* 1.00a rpm 06/29/07 Added udelay macro for standalone
-* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
-* to in MICROBLAZE section
-* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
-*
-*
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XENV_STANDALONE_H
-#define XENV_STANDALONE_H
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-/******************************************************************************
- *
- * Get the processor dependent includes
- *
- ******************************************************************************/
-
-#include
-
-#if defined __MICROBLAZE__
-# include "mb_interface.h"
-# include "xparameters.h" /* XPAR constants used below in MB section */
-
-#elif defined __PPC__
-# include "sleep.h"
-# include "xcache_l.h" /* also include xcache_l.h for caching macros */
-#endif
-
-/******************************************************************************
- *
- * MEMCPY / MEMSET related macros.
- *
- * The following are straight forward implementations of memset and memcpy.
- *
- * NOTE: memcpy may not work if source and target memory area are overlapping.
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
- *
- * Copies a non-overlapping block of memory.
- *
- * @param DestPtr
- * Destination address to copy data to.
- *
- * @param SrcPtr
- * Source address to copy data from.
- *
- * @param Bytes
- * Number of bytes to copy.
- *
- * @return None.
- *
- * @note
- * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
- *
- * @note
- * This implementation MAY BREAK work if source and target memory
- * area are overlapping.
- *
- *****************************************************************************/
-
-#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
- memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
-
-
-
-/*****************************************************************************/
-/**
- *
- * Fills an area of memory with constant data.
- *
- * @param DestPtr
- * Destination address to copy data to.
- *
- * @param Data
- * Value to set.
- *
- * @param Bytes
- * Number of bytes to copy.
- *
- * @return None.
- *
- * @note
- * The use of XENV_MEM_FILL is deprecated. Use memset() instead.
- *
- *****************************************************************************/
-
-#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
- memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
-
-
-
-/******************************************************************************
- *
- * TIME related macros
- *
- ******************************************************************************/
-
-/**
- * A structure that contains a time stamp used by other time stamp macros
- * defined below. This structure is processor dependent.
- */
-typedef s32 XENV_TIME_STAMP;
-
-/*****************************************************************************/
-/**
- *
- * Time is derived from the 64 bit PPC timebase register
- *
- * @param StampPtr is the storage for the retrieved time stamp.
- *
- * @return None.
- *
- * @note
- *
- * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_GET(StampPtr)
-
-/*****************************************************************************/
-/**
- *
- * This macro is not yet implemented and always returns 0.
- *
- * @param Stamp1Ptr is the first sampled time stamp.
- * @param Stamp2Ptr is the second sampled time stamp.
- *
- * @return 0
- *
- * @note
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
-
-/*****************************************************************************/
-/**
- *
- * This macro is not yet implemented and always returns 0.
- *
- * @param Stamp1Ptr is the first sampled time stamp.
- * @param Stamp2Ptr is the second sampled time stamp.
- *
- * @return 0
- *
- * @note
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
-
-/*****************************************************************************/
-/**
- * XENV_USLEEP(unsigned delay)
- *
- * Delay the specified number of microseconds. Not implemented without OS
- * support.
- *
- * @param delay
- * Number of microseconds to delay.
- *
- * @return None.
- *
- *****************************************************************************/
-
-#ifdef __PPC__
-#define XENV_USLEEP(delay) usleep(delay)
-#define udelay(delay) usleep(delay)
-#else
-#define XENV_USLEEP(delay)
-#define udelay(delay)
-#endif
-
-
-/******************************************************************************
- *
- * CACHE handling macros / mappings
- *
- ******************************************************************************/
-/******************************************************************************
- *
- * Processor independent macros
- *
- ******************************************************************************/
-
-#define XCACHE_ENABLE_CACHE() \
- { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
-
-#define XCACHE_DISABLE_CACHE() \
- { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
-
-
-/******************************************************************************
- *
- * MicroBlaze case
- *
- * NOTE: Currently the following macros will only work on systems that contain
- * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
- * system is built using a xparameters.h file.
- *
- ******************************************************************************/
-
-#if defined __MICROBLAZE__
-
-/* Check if MicroBlaze data cache was built into the core.
- */
-#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
-# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
-# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
-# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
-
-# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
- microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
-
-#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
-# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
-#else
-# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
-#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
-
-#else
-# define XCACHE_ENABLE_DCACHE()
-# define XCACHE_DISABLE_DCACHE()
-# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
-#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
-
-
-/* Check if MicroBlaze instruction cache was built into the core.
- */
-#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
-# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
-# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
-
-# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
-
-# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
- microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
-
-#else
-# define XCACHE_ENABLE_ICACHE()
-# define XCACHE_DISABLE_ICACHE()
-#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
-
-
-/******************************************************************************
- *
- * PowerPC case
- *
- * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
- * specific memory region (0x80000001). Each bit (0-30) in the regions
- * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
- * range.
- *
- * regions --> cached address range
- * ------------|--------------------------------------------------
- * 0x80000000 | [0, 0x7FFFFFF]
- * 0x00000001 | [0xF8000000, 0xFFFFFFFF]
- * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
- *
- ******************************************************************************/
-
-#elif defined __PPC__
-
-#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
-#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
-#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
-#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
-
-#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
- XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
-
-#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
-
-#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
-
-
-/******************************************************************************
- *
- * Unknown processor / architecture
- *
- ******************************************************************************/
-
-#else
-/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* #ifndef XENV_STANDALONE_H */
-
- /**
- *@endcond
- */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d6/504d62585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d6/504d62585243001d18b399c1eb9b3628
deleted file mode 100644
index 9db4610..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d6/504d62585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,529 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file translation_table.s
-*
-* @addtogroup a72_64_boot_code
-* @{
-*
translation_table.S
-* translation_table.S contains a static page table required by MMU for
-* cortex-A72. This translation table is flat mapped (input address = output
-* address) with default memory attributes defined for versal
-* architecture. It utilizes translation granual size of 4KB with 2MB section
-* size for initial 5GB memory and 1GB section size for memory after 5GB.
-* The overview of translation table memory attributes is described below.
-*
-*| Name | Memory Range | Def. in Translation Table |
-*|-----------------------|-----------------------------------|-----------------------------|
-*| DDR | 0x000_0000_0000 - 0x000_7FFF_FFFF | Normal WB Cacheable |
-*| LPD_AFI_FS | 0x000_8000_0000 - 0x000_9FFF_FFFF | Strongly Ordered |
-*| Reserved | 0x000_A000_0000 - 0x000_A3FF_FFFF | Unassigned |
-*| FPD_AFI_0 | 0x000_A400_0000 - 0x000_AFFF_FFFF | Strongly Ordered |
-*| FPD_AFI_1 | 0x000_B000_0000 - 0x000_BFFF_FFFF | Strongly Ordered |
-*| QSPI | 0x000_C000_0000 - 0x000_DFFF_FFFF | Strongly Ordered |
-*| PCIE region 0 | 0x000_E000_0000 - 0x000_EFFF_FFFF | Strongly Ordered |
-*| PMC | 0x000_F000_0000 - 0x000_F7FF_FFFF | Strongly Ordered |
-*| STM_CORESIGHT | 0x000_F800_0000 - 0x000_F8FF_FFFF | Strongly Ordered |
-*| GIC | 0x000_F900_0000 - 0x000_F90F_FFFF | Strongly Ordered |
-*| Reserved | 0x000_F910_0000 - 0x000_FBFF_FFFF | Unassigned |
-*| CPM | 0x000_FC00_0000 - 0x000_FCFF_FFFF | Strongly Ordered |
-*| FPD slaves | 0x000_FD00_0000 - 0x000_FDFF_FFFF | Strongly Ordered |
-*| LPD slaves | 0x000_FE00_0000 - 0x000_FFDF_FFFF | Strongly Ordered |
-*| OCM | 0x000_FFE0_0000 - 0xFFF_FFFF_FFFF | Normal WB Cacheable |
-*| PMC region 0-3 | 0x001_0000_0000 - 0x001_1FFF_FFFF | Strongly Ordered |
-*| Reserved | 0x001_2000_0000 - 0x001_FFFF_FFFF | Unassigned |
-*| ME Array 0-3 | 0x002_0000_0000 - 0x002_FFFF_FFFF | Strongly Ordered |
-*| Reserved | 0x003_0000_0000 - 0x003_FFFF_FFFF | Unassigned |
-*| PL- via PS | 0x004_0000_0000 - 0x005_FFFF_FFFF | Strongly Ordered |
-*| PCIe region 1 | 0x006_0000_0000 - 0x007_FFFF_FFFF | Strongly Ordered |
-*| DDR | 0x008_0000_0000 - 0x00F_FFFF_FFFF | Normal WB Cacheable |
-*| Reserved | 0x010_0000_0000 - 0x03F_FFFF_FFFF | Unassigned |
-*| HBM 0-3 | 0x040_0000_0000 - 0x07F_FFFF_FFFF | Strongly Ordered |
-*| PCIe region 2 | 0x080_0000_0000 - 0x0BF_FFFF_FFFF | Strongly Ordered |
-*| DDR | 0x0C0_0000_0000 - 0x1B7_7FFF_FFFF | Normal WB Cacheable |
-*| Reserved | 0x1B7_8000_0000 - 0x1FF_FFFF_FFFF | Unassigned |
-*| PL- Via NoC | 0x200_0000_0000 - 0x3FF_FFFF_FFFF | Strongly Ordered |
-*| PL- Via PS | 0x400_0000_0000 - 0x4FF_FFFF_FFFF | Strongly Ordered |
-*| DDR CH1-CH3 | 0x500_0000_0000 - 0x7FF_FFFF_FFFF | Normal WB Cacheable |
-*| PL- Via NoC | 0x800_0000_0000 - 0xFFF_FFFF_FFFF | Strongly Ordered |
-*
-* @note
-*
-* For DDR region 0x0000000000 - 0x007FFFFFFF, a system where DDR is less than
-* 2GB, region after DDR and before PL is marked as undefined/reserved in
-* translation table. Region 0xF9100000 - 0xF91FFFFF is reserved memory in
-* 0x00F9000000 - 0x00F91FFFFF range, but it is marked as strongly ordered
-* because minimum section size in translation table section is 2MB.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 7.2 mus 01/09/20 Initial version
-*
-*
-******************************************************************************/
-#include "xparameters.h"
-#include "bspconfig.h"
-
- EXPORT MMUTableL0
- EXPORT MMUTableL1
- EXPORT MMUTableL2
-
- GBLA abscnt
- GBLA count
- GBLA sect
-
-Reserved EQU 0x0 ; Fault
-#if EL1_NONSECURE
-Memory EQU 0x405:OR:(2:SHL:8):OR:0x0 ; normal writeback write allocate outer shared read write */
-#else
-Memory EQU 0x405:OR:(3:SHL:8):OR:0x0 ; normal writeback write allocate inner shared read write */
-#endif
-Device EQU 0x409:OR:(1:SHL:53):OR:(1:SHL:54):OR:0x0 ; strongly ordered read write non executable
-
- AREA |.mmu_tbl0|, CODE, ALIGN=12
-
-MMUTableL0
-
-count SETA 0
- WHILE count<0x1f
- DCQU MMUTableL1+count*0x1000+0x3 ; 0x0000_0000 - 0x7F_FFFF_FFFF
-count SETA count+1
- WEND
-
-count SETA 1
- WHILE count<0x20
- DCQ MMUTableL1+count*0x1000+0x3 ; 0x80_0000_0000 - 0xFFF_FFFF_FFFF
-count SETA count+1
- WEND
-
- AREA |.mmu_tbl1|, CODE, ALIGN=12
-
-MMUTableL1
-
- DCQU MMUTableL2+0x3 ; 0x0000_0000 - 0x3FFF_FFFF
-count SETA 1 ; 0x4000_0000 - 0x1_3FFF_FFFF
- WHILE count<5
- DCQ MMUTableL2+count*0x1000+0x3 ; 1GB DDR, 512MB LPD_AFI_FS, 448MB FPD_AFI_0, 512MB QSPI,
- ; 256MB PCIe region 0, PMC 128MB, GIC 1 MB, reserved 47MB,
- ; 2GB other devices and memory, 512 MB PMC
-count SETA count+1
- WEND
-
-Fixlocl1 EQU 0x140000000
-abscnt SETA 0
-
-count SETA 0
- WHILE count<0x3
- DCQU Fixlocl1+abscnt*0x40000000+Reserved ; 0x1_4000_0000 - 0x1_FFFF_FFFF
- ; 3GB Reserved
-count SETA count+1
-abscnt SETA abscnt+1
- WEND
-count SETA 0
- WHILE count<0x4
- DCQU Fixlocl1+abscnt*0x40000000+Device ; 0x2_0000_0000 - 0x2_FFFF_FFFF
- ; 4GB ME Array 0-3
-count SETA count+1
-abscnt SETA abscnt+1
- WEND
-count SETA 0
- WHILE count<0x4
- DCQU Fixlocl1+abscnt*0x40000000+Reserved ; 0x3_0000_0000 - 0x3_FFFF_FFFF
- ; 4GB Reserved
-count SETA count+1
-abscnt SETA abscnt+1
- WEND
-
-count SETA 0
- WHILE count<0x10
- DCQU Fixlocl1+abscnt*0x40000000+Device ; 0x4_0000_0000 - 0x7_FFFF_FFFF
- ; 8GB PL - via PS, 8GB PCIe region1
-count SETA count+1
-abscnt SETA abscnt+1
- WEND
-
-#ifdef XPAR_AXI_NOC_DDR_LOW_1_BASEADDR
-DDR_1_START EQU XPAR_AXI_NOC_DDR_LOW_1_BASEADDR
-DDR_1_END EQU XPAR_AXI_NOC_DDR_LOW_1_HIGHADDR
-DDR_1_SIZE EQU (DDR_1_END - DDR_1_START+1)
-#if DDR_1_SIZE > 0x800000000
-; If DDR size is larger than 32GB, truncate to 32GB
-DDR_1_REG EQU 0x20
-#else
-DDR_1_REG EQU DDR_1_SIZE/0x40000000
-#endif
-#else
-DDR_1_REG EQU 0
-#endif
-
-UNDEF_1_REG EQU (0x20 - DDR_1_REG)
-
-; DDR based on size in hw design
-count SETA 0
- WHILE count 0x4000000000
-; If DDR size is larger than 256 GB, truncate to 256GB
-DDR_2_REG EQU 0x100
-#else
-DDR_2_REG EQU DDR_2_SIZE/0x40000000
-#endif
-#else
-DDR_2_REG EQU 0
-#endif
-
-UNDEF_2_REG EQU (0x100 - DDR_2_REG)
-
-; DDR based on size in hw design
-count SETA 0
- WHILE count 0xB780000000
-; If DDR size is larger than 734 GB, truncate to 734GB
-DDR_3_REG EQU 0x2de
-#else
-DDR_3_REG EQU DDR_3_SIZE/0x40000000
-#endif
-#else
-DDR_3_REG EQU 0
-#endif
-
-UNDEF_3_REG EQU (0x2de - DDR_3_REG)
-
-; DDR based on size in hw design
-count SETA 0
- WHILE count 0x010000000000
-; If DDR size is larger than 1TB, truncate to 1 TB
-DDR_CH_1_REG EQU 0x400 ; 0x500_0000_0000 - 0x5FF_FFFF_FFFF
-#else
-DDR_CH_1_REG EQU DDR_CH_1_SIZE/0x40000000
-#endif
-#else
-DDR_CH_1_REG EQU 0
-#endif
-
-UNDEF_CH_1_REG EQU (0x400 - DDR_CH_1_REG)
-
-; DDR based on size in hw design, Max size 1 TB
-count SETA 0
- WHILE count 0x010000000000
-; If DDR_CH_2 size is larger than 1TB, truncate to 1 TB
-DDR_CH_2_REG EQU 0x400 ; 0x600_0000_0000 - 0x6FF_FFFF_FFFF
-#else
-DDR_CH_2_REG EQU DDR_CH_2_SIZE/0x40000000
-#endif
-#else
-DDR_CH_2_REG EQU 0
-#endif
-
-UNDEF_CH_2_REG EQU (0x400 - DDR_CH_2_REG)
-
-; DDR based on size in hw design, Max size 1 TB
-count SETA 0
- WHILE count 0x010000000000
-; If DDR_CH_3 size is larger than 1TB, truncate to 1 TB */
-DDR_CH_3_REG EQU 0x400 ; 0x700_0000_0000 - 0x7FF_FFFF_FFFF
-#else
-DDR_CH_3_REG EQU DDR_CH_3_SIZE/0x40000000
-#endif
-#else
-DDR_CH_3_REG EQU 0
-#endif
-
-UNDEF_CH_3_REG EQU (0x400 - DDR_CH_3_REG)
-
-; DDR based on size in hw design, Max size 1 TB
-count SETA 0
- WHILE count 0x80000000
-; If DDR size is larger than 2GB, truncate to 2GB
-.set DDR_0_REG, 0x400
-#else
-DDR_0_REG EQU DDR_0_SIZE/0x200000
-#endif
-#else
-DDR_0_REG EQU 0
-#endif
-
-UNDEF_0_REG EQU (0x400 - DDR_0_REG)
-
-; DDR based on size in hw design
-count SETA 0
- WHILE count
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 7.5 asa 02/16/21 First release
-* 7.6 sk 08/05/21 Add Boolean check and braces for Xil_IsSpinLockEnabled
-* if condition to fix misrac violations.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 01/24/10 First release
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-*
-******************************************************************************/
-#ifndef XIL_CACHE_MACH_H
-#define XIL_CACHE_MACH_H
-
-#include "xil_types.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Function Prototypes ******************************/
-
-void Xil_DCacheInvalidateLine(u32 adr);
-void Xil_DCacheFlushLine(u32 adr);
-void Xil_DCacheStoreLine(u32 adr);
-void Xil_ICacheInvalidateLine(u32 adr);
-
-void Xil_L1DCacheEnable(void);
-void Xil_L1DCacheDisable(void);
-void Xil_L1DCacheInvalidate(void);
-void Xil_L1DCacheInvalidateLine(u32 adr);
-void Xil_L1DCacheInvalidateRange(u32 adr, u32 len);
-void Xil_L1DCacheFlush(void);
-void Xil_L1DCacheFlushLine(u32 adr);
-void Xil_L1DCacheFlushRange(u32 adr, u32 len);
-void Xil_L1DCacheStoreLine(u32 adr);
-
-void Xil_L1ICacheEnable(void);
-void Xil_L1ICacheDisable(void);
-void Xil_L1ICacheInvalidate(void);
-void Xil_L1ICacheInvalidateLine(u32 adr);
-void Xil_L1ICacheInvalidateRange(u32 adr, u32 len);
-
-void Xil_L2CacheEnable(void);
-void Xil_L2CacheDisable(void);
-void Xil_L2CacheInvalidate(void);
-void Xil_L2CacheInvalidateLine(u32 adr);
-void Xil_L2CacheInvalidateRange(u32 adr, u32 len);
-void Xil_L2CacheFlush(void);
-void Xil_L2CacheFlushLine(u32 adr);
-void Xil_L2CacheFlushRange(u32 adr, u32 len);
-void Xil_L2CacheStoreLine(u32 adr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-* @} End of "addtogroup a9_cache_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d7/018559565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d7/018559565243001d18b399c1eb9b3628
deleted file mode 100644
index 1f57654..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d7/018559565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,64 +0,0 @@
-/******************************************************************************/
-/**
-* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-* @file xil_mem.c
-*
-* This file contains xil mem copy function to use in case of word aligned
-* data copies.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.1 nsk 11/07/16 First release.
-*
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-
-/***************** Inline Functions Definitions ********************/
-/*****************************************************************************/
-/**
-* @brief This function copies memory from once location to other.
-*
-* @param dst: pointer pointing to destination memory
-*
-* @param src: pointer pointing to source memory
-*
-* @param cnt: 32 bit length of bytes to be copied
-*
-*****************************************************************************/
-void Xil_MemCpy(void* dst, const void* src, u32 cnt)
-{
- char *d = (char*)(void *)dst;
- const char *s = src;
-
- while (cnt >= sizeof (int)) {
- *(int*)d = *(int*)s;
- d += sizeof (int);
- s += sizeof (int);
- cnt -= sizeof (int);
- }
- while (cnt >= sizeof (u16)) {
- *(u16*)d = *(u16*)s;
- d += sizeof (u16);
- s += sizeof (u16);
- cnt -= sizeof (u16);
- }
- while ((cnt) > 0U){
- *d = *s;
- d += 1U;
- s += 1U;
- cnt -= 1U;
- }
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d7/4094af565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d7/4094af565243001d18b399c1eb9b3628
deleted file mode 100644
index f6678a8..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d7/4094af565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,62 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.c
-*
-* @addtogroup microblaze_cache_apis Microblaze Cache APIs
-* @{
-*
-* This contains implementation of cache related driver functions.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00 hbm 07/28/09 Initial release
-* 3.10 asa 05/04/13 This version of MicroBlaze BSP adds support for system
-* cache/L2 cache. Existing APIs in this file are modified
-* to add support for L2 cache.
-* These changes are done for implementing PR #697214.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
-* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
-* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
-* in xadcps.c to fix CR #693371
-* 1.03a bss 11/01/13 Modified xadcps_hw.h to use correct Register offsets
-* CR#749687
-* 2.1 bss 08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
-* XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
-* XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
-* functions.
-* Modified Assert for XAdcPs_SetSingleChParams in
-* xadcps.c to fix CR #807563.
-* 2.2 bss 04/27/14 Modified to use correct Device Config base address in
-* xadcps.c (CR#854437).
-* ms 01/23/17 Added xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/05/17 Modified Comment lines in functions of xadcps
-* examples to recognize it as documentation block
-* for doxygen generation.
-* 2.3 mn 07/09/18 Fix Doxygen warning
-* 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors.
-* aad 12/17/20 Added missing function declarations and removed
-* functions with no definitions.
-*
-*
-*
-*****************************************************************************/
-#ifndef XADCPS_H /* Prevent circular inclusions */
-#define XADCPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xadcps_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**
- * @name Indexes for the different channels.
- * @{
- */
-#define XADCPS_CH_TEMP 0x0U /**< On Chip Temperature */
-#define XADCPS_CH_VCCINT 0x1U /**< VCCINT */
-#define XADCPS_CH_VCCAUX 0x2U /**< VCCAUX */
-#define XADCPS_CH_VPVN 0x3U /**< VP/VN Dedicated analog inputs */
-#define XADCPS_CH_VREFP 0x4U /**< VREFP */
-#define XADCPS_CH_VREFN 0x5U /**< VREFN */
-#define XADCPS_CH_VBRAM 0x6U /**< On-chip VBRAM Data Reg, 7 series */
-#define XADCPS_CH_SUPPLY_CALIB 0x07U /**< Supply Calib Data Reg */
-#define XADCPS_CH_ADC_CALIB 0x08U /**< ADC Offset Channel Reg */
-#define XADCPS_CH_GAINERR_CALIB 0x09U /**< Gain Error Channel Reg */
-#define XADCPS_CH_VCCPINT 0x0DU /**< On-chip PS VCCPINT Channel , Zynq */
-#define XADCPS_CH_VCCPAUX 0x0EU /**< On-chip PS VCCPAUX Channel , Zynq */
-#define XADCPS_CH_VCCPDRO 0x0FU /**< On-chip PS VCCPDRO Channel , Zynq */
-#define XADCPS_CH_AUX_MIN 16U /**< Channel number for 1st Aux Channel */
-#define XADCPS_CH_AUX_MAX 31U /**< Channel number for Last Aux channel */
-
-/*@}*/
-
-
-/**
- * @name Indexes for reading the Calibration Coefficient Data.
- * @{
- */
-#define XADCPS_CALIB_SUPPLY_COEFF 0U /**< Supply Offset Calib Coefficient */
-#define XADCPS_CALIB_ADC_COEFF 1U /**< ADC Offset Calib Coefficient */
-#define XADCPS_CALIB_GAIN_ERROR_COEFF 2U /**< Gain Error Calib Coefficient*/
-/*@}*/
-
-
-/**
- * @name Indexes for reading the Minimum/Maximum Measurement Data.
- * @{
- */
-#define XADCPS_MAX_TEMP 0U /**< Maximum Temperature Data */
-#define XADCPS_MAX_VCCINT 1U /**< Maximum VCCINT Data */
-#define XADCPS_MAX_VCCAUX 2U /**< Maximum VCCAUX Data */
-#define XADCPS_MAX_VBRAM 3U /**< Maximum VBRAM Data */
-#define XADCPS_MIN_TEMP 4U /**< Minimum Temperature Data */
-#define XADCPS_MIN_VCCINT 5U /**< Minimum VCCINT Data */
-#define XADCPS_MIN_VCCAUX 6U /**< Minimum VCCAUX Data */
-#define XADCPS_MIN_VBRAM 7U /**< Minimum VBRAM Data */
-#define XADCPS_MAX_VCCPINT 8U /**< Maximum VCCPINT Register , Zynq */
-#define XADCPS_MAX_VCCPAUX 9U /**< Maximum VCCPAUX Register , Zynq */
-#define XADCPS_MAX_VCCPDRO 0xAU /**< Maximum VCCPDRO Register , Zynq */
-#define XADCPS_MIN_VCCPINT 0xCU /**< Minimum VCCPINT Register , Zynq */
-#define XADCPS_MIN_VCCPAUX 0xDU /**< Minimum VCCPAUX Register , Zynq */
-#define XADCPS_MIN_VCCPDRO 0xEU /**< Minimum VCCPDRO Register , Zynq */
-
-/*@}*/
-
-
-/**
- * @name Alarm Threshold(Limit) Register (ATR) indexes.
- * @{
- */
-#define XADCPS_ATR_TEMP_UPPER 0U /**< High user Temperature */
-#define XADCPS_ATR_VCCINT_UPPER 1U /**< VCCINT high voltage limit register */
-#define XADCPS_ATR_VCCAUX_UPPER 2U /**< VCCAUX high voltage limit register */
-#define XADCPS_ATR_OT_UPPER 3U /**< VCCAUX high voltage limit register */
-#define XADCPS_ATR_TEMP_LOWER 4U /**< Upper Over Temperature limit Reg */
-#define XADCPS_ATR_VCCINT_LOWER 5U /**< VCCINT high voltage limit register */
-#define XADCPS_ATR_VCCAUX_LOWER 6U /**< VCCAUX low voltage limit register */
-#define XADCPS_ATR_OT_LOWER 7U /**< Lower Over Temperature limit */
-#define XADCPS_ATR_VBRAM_UPPER_ 8U /**< VRBAM Upper Alarm Reg, 7 Series */
-#define XADCPS_ATR_VCCPINT_UPPER 9U /**< VCCPINT Upper Alarm Reg, Zynq */
-#define XADCPS_ATR_VCCPAUX_UPPER 0xAU /**< VCCPAUX Upper Alarm Reg, Zynq */
-#define XADCPS_ATR_VCCPDRO_UPPER 0xBU /**< VCCPDRO Upper Alarm Reg, Zynq */
-#define XADCPS_ATR_VBRAM_LOWER 0xCU /**< VRBAM Lower Alarm Reg, 7 Series */
-#define XADCPS_ATR_VCCPINT_LOWER 0xDU /**< VCCPINT Lower Alarm Reg , Zynq */
-#define XADCPS_ATR_VCCPAUX_LOWER 0xEU /**< VCCPAUX Lower Alarm Reg , Zynq */
-#define XADCPS_ATR_VCCPDRO_LOWER 0xFU /**< VCCPDRO Lower Alarm Reg , Zynq */
-
-/*@}*/
-
-
-/**
- * @name Averaging to be done for the channels.
- * @{
- */
-#define XADCPS_AVG_0_SAMPLES 0U /**< No Averaging */
-#define XADCPS_AVG_16_SAMPLES 1U /**< Average 16 samples */
-#define XADCPS_AVG_64_SAMPLES 2U /**< Average 64 samples */
-#define XADCPS_AVG_256_SAMPLES 3U /**< Average 256 samples */
-
-/*@}*/
-
-
-/**
- * @name Channel Sequencer Modes of operation
- * @{
- */
-#define XADCPS_SEQ_MODE_SAFE 0U /**< Default Safe Mode */
-#define XADCPS_SEQ_MODE_ONEPASS 1U /**< Onepass through Sequencer */
-#define XADCPS_SEQ_MODE_CONTINPASS 2U /**< Continuous Cycling Sequencer */
-#define XADCPS_SEQ_MODE_SINGCHAN 3U /**< Single channel -No Sequencing */
-#define XADCPS_SEQ_MODE_SIMUL_SAMPLING 4U /**< Simultaneous sampling */
-#define XADCPS_SEQ_MODE_INDEPENDENT 8U /**< Independent mode */
-
-/*@}*/
-
-
-
-/**
- * @name Power Down Modes
- * @{
- */
-#define XADCPS_PD_MODE_NONE 0U /**< No Power Down */
-#define XADCPS_PD_MODE_ADCB 1U /**< Power Down ADC B */
-#define XADCPS_PD_MODE_XADC 2U /**< Power Down ADC A and ADC B */
-/*@}*/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the XADC/ADC
- * device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Device base address */
-} XAdcPs_Config;
-
-
-/**
- * The driver's instance data. The user is required to allocate a variable
- * of this type for every XADC/ADC device in the system. A pointer to
- * a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XAdcPs_Config Config; /**< XAdcPs_Config of current device */
- u32 IsReady; /**< Device is initialized and ready */
-
-} XAdcPs;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-*
-* This macro checks if the XADC device is in Event Sampling mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return
-* - TRUE if the device is in Event Sampling Mode.
-* - FALSE if the device is in Continuous Sampling Mode.
-*
-* @note C-Style signature:
-* int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);
-*
-*****************************************************************************/
-#define XAdcPs_IsEventSamplingModeSet(InstancePtr) \
- (((XAdcPs_ReadInternalReg(InstancePtr, \
- XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ? \
- TRUE : FALSE))
-
-
-/****************************************************************************/
-/**
-*
-* This macro checks if the XADC device is in External Mux mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return
-* - TRUE if the device is in External Mux Mode.
-* - FALSE if the device is NOT in External Mux Mode.
-*
-* @note C-Style signature:
-* int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);
-*
-*****************************************************************************/
-#define XAdcPs_IsExternalMuxModeSet(InstancePtr) \
- (((XAdcPs_ReadInternalReg(InstancePtr, \
- XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ? \
- TRUE : FALSE))
-
-/****************************************************************************/
-/**
-*
-* This macro converts XADC Raw Data to Temperature(centigrades).
-*
-* @param AdcData is the Raw ADC Data from XADC.
-*
-* @return The Temperature in centigrades.
-*
-* @note C-Style signature:
-* float XAdcPs_RawToTemperature(u32 AdcData);
-*
-*****************************************************************************/
-#define XAdcPs_RawToTemperature(AdcData) \
- ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
-
-/****************************************************************************/
-/**
-*
-* This macro converts XADC/ADC Raw Data to Voltage(volts).
-*
-* @param AdcData is the XADC/ADC Raw Data.
-*
-* @return The Voltage in volts.
-*
-* @note C-Style signature:
-* float XAdcPs_RawToVoltage(u32 AdcData);
-*
-*****************************************************************************/
-#define XAdcPs_RawToVoltage(AdcData) \
- ((((float)(AdcData))* (3.0f))/65536.0f)
-
-/****************************************************************************/
-/**
-*
-* This macro converts Temperature in centigrades to XADC/ADC Raw Data.
-*
-* @param Temperature is the Temperature in centigrades to be
-* converted to XADC/ADC Raw Data.
-*
-* @return The XADC/ADC Raw Data.
-*
-* @note C-Style signature:
-* int XAdcPs_TemperatureToRaw(float Temperature);
-*
-*****************************************************************************/
-#define XAdcPs_TemperatureToRaw(Temperature) \
- ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
-
-/****************************************************************************/
-/**
-*
-* This macro converts Voltage in Volts to XADC/ADC Raw Data.
-*
-* @param Voltage is the Voltage in volts to be converted to
-* XADC/ADC Raw Data.
-*
-* @return The XADC/ADC Raw Data.
-*
-* @note C-Style signature:
-* int XAdcPs_VoltageToRaw(float Voltage);
-*
-*****************************************************************************/
-#define XAdcPs_VoltageToRaw(Voltage) \
- ((int)((Voltage)*65536.0f/3.0f))
-
-
-/****************************************************************************/
-/**
-*
-* This macro is used for writing to the XADC Registers using the
-* command FIFO.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Data is the value to be written to XADC register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);
-*
-*****************************************************************************/
-#define XAdcPs_WriteFifo(InstancePtr, Data) \
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XADCPS_CMDFIFO_OFFSET, Data);
-
-
-/****************************************************************************/
-/**
-*
-* This macro is used for reading from the XADC Registers using the
-* data FIFO.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return Data read from the FIFO
-*
-* @note C-Style signature:
-* u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);
-*
-*****************************************************************************/
-#define XAdcPs_ReadFifo(InstancePtr) \
- XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XADCPS_RDFIFO_OFFSET);
-
-
-/************************** Function Prototypes *****************************/
-
-
-
-/**
- * Functions in xadcps_sinit.c
- */
-XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
-
-/**
- * Functions in xadcps.c
- */
-int XAdcPs_CfgInitialize(XAdcPs *InstancePtr,
- XAdcPs_Config *ConfigPtr,
- u32 EffectiveAddr);
-
-void XAdcPs_SetConfigRegister(XAdcPs *InstancePtr, u32 Data);
-u32 XAdcPs_GetConfigRegister(XAdcPs *InstancePtr);
-
-u32 XAdcPs_GetMiscStatus(XAdcPs *InstancePtr);
-
-void XAdcPs_SetMiscCtrlRegister(XAdcPs *InstancePtr, u32 Data);
-u32 XAdcPs_GetMiscCtrlRegister(XAdcPs *InstancePtr);
-
-void XAdcPs_Reset(XAdcPs *InstancePtr);
-
-u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel);
-
-u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType);
-
-u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType);
-
-void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average);
-u8 XAdcPs_GetAvg(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
- u8 Channel,
- int IncreaseAcqCycles,
- int IsEventMode,
- int IsDifferentialMode);
-
-
-void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask);
-u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr);
-
-void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration);
-u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr);
-
-void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode);
-u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr);
-
-void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor);
-u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask);
-u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask);
-u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask);
-u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask);
-u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr);
-
-void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value);
-u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg);
-
-void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr);
-void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr);
-
-void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode);
-
-int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr);
-
-void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel);
-
-void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode);
-
-u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr);
-
-/**
- * Functions in xadcps_selftest.c
- */
-int XAdcPs_SelfTest(XAdcPs *InstancePtr);
-
-/**
- * Functions in xadcps_intr.c
- */
-void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask);
-void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask);
-u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr);
-
-u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr);
-void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* End of protection macro. */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d8/61c7f8555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d8/61c7f8555243001d18b399c1eb9b3628
deleted file mode 100644
index e48c5f3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d8/61c7f8555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,111 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_errata.h
-*
-* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
-* @{
-* Various ARM errata are handled in the standalone BSP. The implementation for
-* errata handling follows ARM guidelines and is based on the open source Linux
-* support for these errata.
-*
-* @note The errata handling is enabled by default. To disable handling of all the
-* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
-* disable errata on a per-erratum basis, un-define relevant macros in
-* xil_errata.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a srt 04/18/13 First release
-* 6.6 mus 12/07/17 Removed errata 753970, It fixes CR#989132.
-*
-*
-******************************************************************************/
-#ifndef XIL_ERRATA_H
-#define XIL_ERRATA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *@cond nocomments
- */
-/**
- * @name errata_definitions
- *
- * The errata conditions handled in the standalone BSP are listed below
- * @{
- */
-
-#define ENABLE_ARM_ERRATA 1
-
-/**
- *@endcond
- */
-
-#ifdef ENABLE_ARM_ERRATA
-
-/**
- * Errata No: 742230
- * Description: DMB operation may be faulty
- */
-#define CONFIG_ARM_ERRATA_742230 1
-
-/**
- * Errata No: 743622
- * Description: Faulty hazard checking in the Store Buffer may lead
- * to data corruption.
- */
-#define CONFIG_ARM_ERRATA_743622 1
-
-/**
- * Errata No: 775420
- * Description: A data cache maintenance operation which aborts,
- * might lead to deadlock
- */
-#define CONFIG_ARM_ERRATA_775420 1
-
-/**
- * Errata No: 794073
- * Description: Speculative instruction fetches with MMU disabled
- * might not comply with architectural requirements
- */
-#define CONFIG_ARM_ERRATA_794073 1
-
-
-/** PL310 L2 Cache Errata */
-
-/**
- * Errata No: 588369
- * Description: Clean & Invalidate maintenance operations do not
- * invalidate clean lines
- */
-#define CONFIG_PL310_ERRATA_588369 1
-
-/**
- * Errata No: 727915
- * Description: Background Clean and Invalidate by Way operation
- * can cause data corruption
- */
-#define CONFIG_PL310_ERRATA_727915 1
-
-/*@}*/
-#endif /* ENABLE_ARM_ERRATA */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_ERRATA_H */
-/**
-* @} End of "addtogroup a9_errata".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d8/83c4b5585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d8/83c4b5585243001d18b399c1eb9b3628
deleted file mode 100644
index b42e351..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d8/83c4b5585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,14 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include
-
-
-void abort(void)
-{
- __exit(1);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d8/9026d9545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d8/9026d9545243001d18b399c1eb9b3628
deleted file mode 100644
index eb496ea..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d8/9026d9545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,39 +0,0 @@
-DRIVER_LIB_VERSION = 1.0
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I$(INCLUDEDIR)
-
-SRCFILES:=$(wildcard *.c)
-
-OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
-
-libs: $(OBJECTS)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf ${DEPFILES}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d8/a10817575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d8/a10817575243001d18b399c1eb9b3628
deleted file mode 100644
index b924726..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d8/a10817575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,507 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
- *
- * @file xusbps_endpoint.h
-* @addtogroup usbps_v2_7
-* @{
- *
- * This is an internal file containung the definitions for endpoints. It is
- * included by the xusbps_endpoint.c which is implementing the endpoint
- * functions and by xusbps_intr.c.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- --------------------------------------------------------
- * 1.00a wgr 10/10/10 First release
- * 2.5 pm 02/20/20 Added multiplier bit for ISO frame handling.
- *
- *
- ******************************************************************************/
-#ifndef XUSBPS_ENDPOINT_H
-#define XUSBPS_ENDPOINT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_cache.h"
-#include "xusbps.h"
-#include "xil_types.h"
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-
-/**
- * Endpoint Device Transfer Descriptor
- *
- * The dTD describes to the device controller the location and quantity of data
- * to be sent/received for given transfer. The driver does not attempt to
- * modify any field in an active dTD except the Next Link Pointer.
- */
-#define XUSBPS_dTDNLP 0x00 /**< Pointer to the next descriptor */
-#define XUSBPS_dTDTOKEN 0x04 /**< Descriptor Token */
-#define XUSBPS_dTDBPTR0 0x08 /**< Buffer Pointer 0 */
-#define XUSBPS_dTDBPTR1 0x0C /**< Buffer Pointer 1 */
-#define XUSBPS_dTDBPTR2 0x10 /**< Buffer Pointer 2 */
-#define XUSBPS_dTDBPTR3 0x14 /**< Buffer Pointer 3 */
-#define XUSBPS_dTDBPTR4 0x18 /**< Buffer Pointer 4 */
-#define XUSBPS_dTDBPTR(n) (XUSBPS_dTDBPTR0 + (n) * 0x04)
-#define XUSBPS_dTDRSRVD 0x1C /**< Reserved field */
-
-/* We use the reserved field in the dTD to store user data. */
-#define XUSBPS_dTDUSERDATA XUSBPS_dTDRSRVD /**< Reserved field */
-
-
-/** @name dTD Next Link Pointer (dTDNLP) bit positions.
- * @{
- */
-#define XUSBPS_dTDNLP_T_MASK 0x00000001
- /**< USB dTD Next Link Pointer Terminate Bit */
-#define XUSBPS_dTDNLP_ADDR_MASK 0xFFFFFFE0
- /**< USB dTD Next Link Pointer Address [31:5] */
-/* @} */
-
-
-/** @name dTD Token (dTDTOKEN) bit positions.
- * @{
- */
-#define XUSBPS_dTDTOKEN_XERR_MASK 0x00000008 /**< dTD Transaction Error */
-#define XUSBPS_dTDTOKEN_BUFERR_MASK 0x00000020 /**< dTD Data Buffer Error */
-#define XUSBPS_dTDTOKEN_HALT_MASK 0x00000040 /**< dTD Halted Flag */
-#define XUSBPS_dTDTOKEN_ACTIVE_MASK 0x00000080 /**< dTD Active Bit */
-#define XUSBPS_dTDTOKEN_MULTO_MASK 0x00000C00 /**< Multiplier Override Field [1:0] */
-#define XUSBPS_dTDTOKEN_IOC_MASK 0x00008000 /**< Interrupt on Complete Bit */
-#define XUSBPS_dTDTOKEN_LEN_MASK 0x7FFF0000 /**< Transfer Length Field */
-/* @} */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- *
- * IMPORTANT NOTE:
- * ===============
- *
- * Many of the following macros modify Device Queue Head (dQH) data structures
- * and Device Transfer Descriptor (dTD) data structures. Those structures can
- * potentially reside in CACHED memory. Therefore, it's the callers
- * responsibility to ensure cache coherency by using provided
- *
- * XUsbPs_dQHInvalidateCache()
- * XUsbPs_dQHFlushCache()
- * XUsbPs_dTDInvalidateCache()
- * XUsbPs_dTDFlushCache()
- *
- * function calls.
- *
- ******************************************************************************/
-#define XUsbPs_dTDInvalidateCache(dTDPtr) \
- Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
-
-#define XUsbPs_dTDFlushCache(dTDPtr) \
- Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
-
-#define XUsbPs_dQHInvalidateCache(dQHPtr) \
- Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
-
-#define XUsbPs_dQHFlushCache(dQHPtr) \
- Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Transfer Length for the given Transfer Descriptor.
- *
- * @param dTDPtr is pointer to the dTD element.
- * @param Len is the length to be set. Range: 0..16384
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetTransferLen(dTDPtr, Len) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
- ~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16))
-
-
-/*****************************************************************************/
-/**
- *
- * This macro gets the Next Link pointer of the given Transfer Descriptor.
- *
- * @param dTDPtr is pointer to the dTD element.
- *
- * @return TransferLength field of the descriptor.
- *
- * @note C-style signature:
- * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDGetNLP(dTDPtr) \
- (XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\
- & XUSBPS_dTDNLP_ADDR_MASK))
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Next Link pointer of the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- * @param NLP is the Next Link Pointer
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetNLP(dTDPtr, NLP) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
- (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
- ~XUSBPS_dTDNLP_ADDR_MASK) | \
- ((NLP) & XUSBPS_dTDNLP_ADDR_MASK))
-
-
-/*****************************************************************************/
-/**
- *
- * This macro gets the Transfer Length for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @return TransferLength field of the descriptor.
- *
- * @note C-style signature:
- * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDGetTransferLen(dTDPtr) \
- (u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) \
- & XUSBPS_dTDTOKEN_LEN_MASK) >> 16)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Interrupt On Complete (IOC) bit for the given Transfer
- * Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetIOC(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetIOC(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
- XUSBPS_dTDTOKEN_IOC_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Terminate bit for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetTerminate(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetTerminate(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) | \
- XUSBPS_dTDNLP_T_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro clears the Terminate bit for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDClrTerminate(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDClrTerminate(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \
- ~XUSBPS_dTDNLP_T_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro checks if the given descriptor is active.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @return
- * - TRUE: The buffer is active.
- * - FALSE: The buffer is not active.
- *
- * @note C-style signature:
- * int XUsbPs_dTDIsActive(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDIsActive(dTDPtr) \
- ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
- XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Active bit for the given Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetActive(u32 dTDPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetActive(dTDPtr) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \
- XUSBPS_dTDTOKEN_ACTIVE_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the multiplier bit for the Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- * @param val is the multiplier value.
- *
- * @note C-style signature:
- * void XUsbPs_dTDSetMultO(u32 dTDPtr, u32 val)
- *
- ******************************************************************************/
-#define XUsbPs_dTDSetMultO(dTDPtr, val) \
- XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \
- (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \
- (~XUSBPS_dTDTOKEN_MULTO_MASK)) | val)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro reads the content of a field in a Transfer Descriptor.
- *
- * @param dTDPtr is a pointer to the dTD element.
- * @param Id is the field ID inside the dTD element to read.
- *
- * @note C-style signature:
- * u32 XUsbPs_ReaddTD(u32 dTDPtr, u32 Id)
- *
- ******************************************************************************/
-#define XUsbPs_ReaddTD(dTDPtr, Id) (*(u32 *)((u32)(dTDPtr) + (u32)(Id)))
-
-/*****************************************************************************/
-/**
- *
- * This macro writes a value to a field in a Transfer Descriptor.
- *
- * @param dTDPtr is pointer to the dTD element.
- * @param Id is the field ID inside the dTD element to read.
- * @param Val is the value to write to the field.
- *
- * @note C-style signature:
- * u32 XUsbPs_WritedTD(u32 dTDPtr, u32 Id, u32 Val)
- *
- ******************************************************************************/
-#define XUsbPs_WritedTD(dTDPtr, Id, Val) \
- (*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val))
-
-
-/******************************************************************************/
-/**
- * Endpoint Device Queue Head
- *
- * Device queue heads are arranged in an array in a continuous area of memory
- * pointed to by the ENDPOINTLISTADDR pointer. The device controller will index
- * into this array based upon the endpoint number received from the USB bus.
- * All information necessary to respond to transactions for all primed
- * transfers is contained in this list so the Device Controller can readily
- * respond to incoming requests without having to traverse a linked list.
- *
- * The device Endpoint Queue Head (dQH) is where all transfers are managed. The
- * dQH is a 48-byte data structure, but must be aligned on a 64-byte boundary.
- * During priming of an endpoint, the dTD (device transfer descriptor) is
- * copied into the overlay area of the dQH, which starts at the nextTD pointer
- * DWord and continues through the end of the buffer pointers DWords. After a
- * transfer is complete, the dTD status DWord is updated in the dTD pointed to
- * by the currentTD pointer. While a packet is in progress, the overlay area of
- * the dQH is used as a staging area for the dTD so that the Device Controller
- * can access needed information with little minimal latency.
- *
- * @note
- * Software must ensure that no interface data structure reachable by the
- * Device Controller spans a 4K-page boundary. The first element of the
- * Endpoint Queue Head List must be aligned on a 4K boundary.
- */
-#define XUSBPS_dQHCFG 0x00 /**< dQH Configuration */
-#define XUSBPS_dQHCPTR 0x04 /**< dQH Current dTD Pointer */
-#define XUSBPS_dQHdTDNLP 0x08 /**< dTD Next Link Ptr in dQH
- overlay */
-#define XUSBPS_dQHdTDTOKEN 0x0C /**< dTD Token in dQH overlay */
-#define XUSBPS_dQHSUB0 0x28 /**< USB dQH Setup Buffer 0 */
-#define XUSBPS_dQHSUB1 0x2C /**< USB dQH Setup Buffer 1 */
-
-
-/** @name dQH Configuration (dQHCFG) bit positions.
- * @{
- */
-#define XUSBPS_dQHCFG_IOS_MASK 0x00008000
- /**< USB dQH Interrupt on Setup Bit */
-#define XUSBPS_dQHCFG_MPL_MASK 0x07FF0000
- /**< USB dQH Maximum Packet Length
- * Field [10:0] */
-#define XUSBPS_dQHCFG_MPL_SHIFT 16
-#define XUSBPS_dQHCFG_ZLT_MASK 0x20000000
- /**< USB dQH Zero Length Termination
- * Select Bit */
-#define XUSBPS_dQHCFG_MULT_MASK 0xC0000000
- /* USB dQH Number of Transactions Field
- * [1:0] */
-#define XUSBPS_dQHCFG_MULT_SHIFT 30
-/* @} */
-
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Maximum Packet Length field of the give Queue Head.
- *
- * @param dQHPtr is a pointer to the dQH element.
- * @param Len is the length to be set.
- *
- * @note C-style signature:
- * void XUsbPs_dQHSetMaxPacketLen(u32 dQHPtr, u32 Len)
- *
- ******************************************************************************/
-#define XUsbPs_dQHSetMaxPacketLen(dQHPtr, Len) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
- ~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16))
-
-/*****************************************************************************/
-/**
- *
- * This macro sets the Interrupt On Setup (IOS) bit for an endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHSetIOS(u32 dQHPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dQHSetIOS(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
- XUSBPS_dQHCFG_IOS_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro clears the Interrupt On Setup (IOS) bit for an endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHClrIOS(u32 dQHPtr)
- *
- ******************************************************************************/
-#define XUsbPs_dQHClrIOS(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
- ~XUSBPS_dQHCFG_IOS_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro enables Zero Length Termination for the endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHEnableZLT(u32 dQHPtr)
- *
- *
- ******************************************************************************/
-#define XUsbPs_dQHEnableZLT(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \
- ~XUSBPS_dQHCFG_ZLT_MASK)
-
-
-/*****************************************************************************/
-/**
- *
- * This macro disables Zero Length Termination for the endpoint.
- *
- * @param dQHPtr is a pointer to the dQH element.
- *
- * @note C-style signature:
- * void XUsbPs_dQHDisableZLT(u32 dQHPtr)
- *
- *
- ******************************************************************************/
-#define XUsbPs_dQHDisableZLT(dQHPtr) \
- XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \
- XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \
- XUSBPS_dQHCFG_ZLT_MASK)
-
-/*****************************************************************************/
-/**
- *
- * This macro reads the content of a field in a Queue Head.
- *
- * @param dQHPtr is a pointer to the dQH element.
- * @param Id is the Field ID inside the dQH element to read.
- *
- * @note C-style signature:
- * u32 XUsbPs_ReaddQH(u32 dQHPtr, u32 Id)
- *
- ******************************************************************************/
-#define XUsbPs_ReaddQH(dQHPtr, Id) (*(u32 *)((u32)(dQHPtr) + (u32) (Id)))
-
-/*****************************************************************************/
-/**
- *
- * This macro writes a value to a field in a Queue Head.
- *
- * @param dQHPtr is a pointer to the dQH element.
- * @param Id is the Field ID inside the dQH element to read.
- * @param Val is the Value to write to the field.
- *
- * @note C-style signature:
- * u32 XUsbPs_WritedQH(u32 dQHPtr, u32 Id, u32 Val)
- *
- ******************************************************************************/
-#define XUsbPs_WritedQH(dQHPtr, Id, Val) \
- (*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val))
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XUSBPS_ENDPOINT_H */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d8/b03deb565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d8/b03deb565243001d18b399c1eb9b3628
deleted file mode 100644
index 5798c21..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d8/b03deb565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,54 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_testcache.h
-*
-* @addtogroup common_test_utils
-*
Cache test
-* The xil_testcache.h file contains utility functions to test cache.
-*
-* @{
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 07/29/09 First release
-*
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.0 nsk 08/06/15 First Release
- * 1.0 nsk 08/20/15 Updated define_addr_params in ddrps.tcl
- * to support PBD Designs (CR #876857)
- *
- *
- *
-*******************************************************************************/
-
-#ifndef XDDRPS_H_
-/* Prevent circular inclusions by using protection macros. */
-#define XDDRPS_H_
-
-/******************************* Include Files ********************************/
-
-
-#endif /* XDDRPS_H_ */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d8/c0e45ab75243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d8/c0e45ab75243001d18b399c1eb9b3628
deleted file mode 100644
index c63db8f..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d8/c0e45ab75243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,11 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d9/10765c575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d9/10765c575243001d18b399c1eb9b3628
deleted file mode 100644
index 6f009c6..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d9/10765c575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,24 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by HSI.
-* Version: 2021.2
-* DO NOT EDIT.
-*
-* Copyright (C) 2010-2022 Xilinx, Inc. All Rights Reserved.
-* SPDX-License-Identifier: MIT
-
-*
-* Description: Configurations for Standalone BSP
-*
-*******************************************************************/
-
-#ifndef BSPCONFIG_H /* prevent circular inclusions */
-#define BSPCONFIG_H /* by using protection macros */
-
-#define MICROBLAZE_PVR_NONE
-
-/* Definition for hard-float ABI */
-#define FPU_HARD_FLOAT_ABI_ENABLED 1
-
-#endif /*end of __BSPCONFIG_H_*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d9/40af84525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d9/40af84525243001d18b399c1eb9b3628
deleted file mode 100644
index 6719ab0..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d9/40af84525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,62 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file vectors.h
-*
-* This file contains the C level vector prototypes for the ARM Cortex A9 core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 10/20/10 Initial version, moved over from bsp area
-* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
-* of 0x20 as the base address obtained from the tools
-* starts at 0x20.
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-#ifndef XSCUWDT_HW_H /**< prevent circular inclusions */
-#define XSCUWDT_HW_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- * Offsets of registers from the start of the device. The WDT registers start at
- * an offset 0x20
- * @{
- */
-
-#define XSCUWDT_LOAD_OFFSET 0x00U /**< Watchdog Load Register */
-#define XSCUWDT_COUNTER_OFFSET 0x04U /**< Watchdog Counter Register */
-#define XSCUWDT_CONTROL_OFFSET 0x08U /**< Watchdog Control Register */
-#define XSCUWDT_ISR_OFFSET 0x0CU /**< Watchdog Interrupt Status Register */
-#define XSCUWDT_RST_STS_OFFSET 0x10U /**< Watchdog Reset Status Register */
-#define XSCUWDT_DISABLE_OFFSET 0x14U /**< Watchdog Disable Register */
-/* @} */
-
-/** @name Watchdog Control register
- * This register bits control the prescaler, WD/Timer mode, Intr enable,
- * auto-reload, watchdog enable.
- * @{
- */
-
-#define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
-#define XSCUWDT_CONTROL_PRESCALER_SHIFT 8U
-#define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008U /**< Watchdog/Timer mode */
-#define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004U /**< Intr enable (in
- timer mode) */
-#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload (in
- timer mode) */
-#define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001U /**< Watchdog enable */
-/* @} */
-
-/** @name Interrupt Status register
- * This register indicates the Counter register has reached zero in Counter
- * mode.
- * @{
- */
-
-#define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
-/*@}*/
-
-/** @name Reset Status register
- * This register indicates the Counter register has reached zero in Watchdog
- * mode and a reset request is sent.
- * @{
- */
-
-#define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001U /**< Time out occurred */
-/*@}*/
-
-/** @name Disable register
- * This register is used to switch from watchdog mode to timer mode.
- * The software must write 0x12345678 and 0x87654321 successively to the
- * Watchdog Disable Register so that the watchdog mode bit in the Watchdog
- * Control Register is set to zero.
- * @{
- */
-#define XSCUWDT_DISABLE_VALUE1 0x12345678U /**< Watchdog mode disable
- value 1 */
-#define XSCUWDT_DISABLE_VALUE2 0x87654321U /**< Watchdog mode disable
- value 2 */
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note C-style signature:
-* u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuWdt_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + ((u32)RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d9/f1b060565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d9/f1b060565243001d18b399c1eb9b3628
deleted file mode 100644
index 5798c21..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/d9/f1b060565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,54 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_testcache.h
-*
-* @addtogroup common_test_utils
-*
Cache test
-* The xil_testcache.h file contains utility functions to test cache.
-*
-* @{
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 07/29/09 First release
-*
-*
-******************************************************************************/
-
-/**
-*@cond nocomments
-*/
-
-#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */
-#define XIL_TESTCACHE_H /* by using protection macros */
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern s32 Xil_TestDCacheRange(void);
-extern s32 Xil_TestDCacheAll(void);
-extern s32 Xil_TestICacheRange(void);
-extern s32 Xil_TestICacheAll(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
-
-/**
-* @} End of "addtogroup common_test_utils".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/da/01914b585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/da/01914b585243001d18b399c1eb9b3628
deleted file mode 100644
index c1258fb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/da/01914b585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,588 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
- *
- * @file xil_cache.c
- *
- * Contains required functions for the ARM cache functionality.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -----------------------------------------------
- * 5.2 pkp 28/05/15 First release
- * 5.5 pkp 04/15/16 Updated the Xil_DCacheInvalidate,
- * Xil_DCacheInvalidateLine and Xil_DCacheInvalidateRange
- * functions description for proper explanation
- * 6.8 aru 06/15/18 Removed unused variables.
- * 6.8 aru 07/04/18 Optimized code in Xil_DCacheInvalidate and
- * Xil_DCacheFlush
- * 6.8 asa 11/10/18 Fix issues in cache Xil_DCacheInvalidate and
- * Xil_DCacheFlush that got introduced in the optimization
- * changes done in the previous patch for this file.
- *
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 Initial release
-* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/**
- * @brief This variable allows testing to be done easier with asserts. An assert
- * sets this variable such that a driver can evaluate this variable
- * to determine if an assert occurred.
- */
-u32 Xil_AssertStatus;
-
-/**
- * @brief This variable allows the assert functionality to be changed for testing
- * such that it does not wait infinitely. Use the debugger to disable the
- * waiting during testing of asserts.
- */
-s32 Xil_AssertWait = 1;
-
-/* The callback function to be invoked when an assert is taken */
-static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* @brief Implement assert. Currently, it calls a user-defined callback
-* function if one has been set. Then, it potentially enters an
-* infinite loop depending on the value of the Xil_AssertWait
-* variable.
-*
-* @param File: filename of the source
-* @param Line: linenumber within File
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void Xil_Assert(const char8 *File, s32 Line)
-{
- /* if the callback has been set then invoke it */
- if (Xil_AssertCallbackRoutine != 0) {
- (*Xil_AssertCallbackRoutine)(File, Line);
- }
-
- /* if specified, wait indefinitely such that the assert will show up
- * in testing
- */
- while (Xil_AssertWait != 0) {
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Set up a callback function to be invoked when an assert occurs.
-* If a callback is already installed, then it will be replaced.
-*
-* @param Routine: callback to be invoked when an assert is taken
-*
-* @return None.
-*
-* @note This function has no effect if NDEBUG is set
-*
-******************************************************************************/
-void Xil_AssertSetCallback(Xil_AssertCallback Routine)
-{
- Xil_AssertCallbackRoutine = Routine;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Null handler function. This follows the XInterruptHandler
-* signature for interrupt handlers. It can be used to assign a null
-* handler (a stub) to an interrupt controller vector table.
-*
-* @param NullParameter: arbitrary void pointer and not used.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XNullHandler(void *NullParameter)
-{
- (void) NullParameter;
-}
-/**
-* @} End of "addtogroup common_assert_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/da/50f47f525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/da/50f47f525243001d18b399c1eb9b3628
deleted file mode 100644
index 08af00b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/da/50f47f525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,93 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/*****************************************************************************/
-/**
-* @file sleep.h
-*
-* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep
-* related APIs.
-*
-*
-* MODIFICATION HISTORY :
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 6.6 srm 11/02/17 Added processor specific sleep routines
-* function prototypes.
-*
-*
-*
-******************************************************************************/
-
-#ifndef SLEEP_H
-#define SLEEP_H
-
-#include "xil_types.h"
-#include "xil_io.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*****************************************************************************/
-/**
-*
-* This macro polls an address periodically until a condition is met or till the
-* timeout occurs.
-* The minimum timeout for calling this macro is 100us. If the timeout is less
-* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
-* If the timeout is not a multiple of 100us, it waits for a timeout of
-* the next usec value which is a multiple of 100us.
-*
-* @param IO_func - accessor function to read the register contents.
-* Depends on the register width.
-* @param ADDR - Address to be polled
-* @param VALUE - variable to read the value
-* @param COND - Condition to checked (usually involves VALUE)
-* @param TIMEOUT_US - timeout in micro seconds
-*
-* @return 0 - when the condition is met
-* -1 - when the condition is not met till the timeout period
-*
-* @note none
-*
-*****************************************************************************/
-#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
- ( { \
- u64 timeout = TIMEOUT_US/100; \
- if(TIMEOUT_US%100!=0) \
- timeout++; \
- for(;;) { \
- VALUE = IO_func(ADDR); \
- if(COND) \
- break; \
- else { \
- usleep(100); \
- timeout--; \
- if(timeout==0) \
- break; \
- } \
- } \
- (timeout>0) ? 0 : -1; \
- } )
-
-void usleep(unsigned long useconds);
-void sleep(unsigned int seconds);
-int usleep_R5(unsigned long useconds);
-unsigned sleep_R5(unsigned int seconds);
-int usleep_MB(unsigned long useconds);
-unsigned sleep_MB(unsigned int seconds);
-int usleep_A53(unsigned long useconds);
-unsigned sleep_A53(unsigned int seconds);
-int usleep_A9(unsigned long useconds);
-unsigned sleep_A9(unsigned int seconds);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/da/907ee8565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/da/907ee8565243001d18b399c1eb9b3628
deleted file mode 100644
index 5007212..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/da/907ee8565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,111 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2017 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_sleeptimer.h
-*
-* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs.
-* For sleep related functions that can be used across all Xilinx supported
-* processors, please use xil_sleeptimer.h.
-*
-*
-*
-* MODIFICATION HISTORY :
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 6.6 srm 10/18/17 First Release.
-* 7.0 mus 01/07/19 Add cpp extern macro
-*
-*
-*****************************************************************************/
-
-/**
- *@cond nocomments
- */
-#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */
-#define XIL_SLEEPTIMER_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**************************** Include Files ********************************/
-
-#include "xil_io.h"
-#include "xparameters.h"
-#include "bspconfig.h"
-
-/************************** Constant Definitions *****************************/
-
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
-#define XSLEEP_TIMER_REG_SHIFT 32U
-#define XSleep_ReadCounterVal Xil_In32
-#define XCntrVal u32
-#else
-#define XSLEEP_TIMER_REG_SHIFT 16U
-#define XSleep_ReadCounterVal Xil_In16
-#define XCntrVal u16
-#endif
-
-#if defined(ARMR5) || (defined (__aarch64__) && EL3==1) || defined (ARMA53_32)
-#if defined (versal)
-#define CRL_TTC_RST 0xFF5E0344U
-#define CRL_TTC_BASE_RST_MASK 0x1U
-#else
-#define RST_LPD_IOU2 0xFF5E0238U
-#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U
-#endif
-#endif
-
-#if defined (SLEEP_TIMER_BASEADDR)
-/** @name Register Map
-*
-* Register offsets from the base address of the TTC device
-*
-* @{
-*/
- #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U
- /**< Clock Control Register */
- #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU
- /**< Counter Control Register*/
- #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U
- /**< Current Counter Value */
-/* @} */
-/** @name Clock Control Register
-* Clock Control Register definitions of TTC
-* @{
-*/
- #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U
- /**< Prescale enable */
-/* @} */
-/** @name Counter Control Register
-* Counter Control Register definitions of TTC
-* @{
-*/
-#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U
- /**< Disable the counter */
-#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U
- /**< Reset counter */
-/* @} */
-
-/**************************** Type Definitions *******************************/
-/**
- *@endcond
- */
-/************************** Function Prototypes ******************************/
-
-void Xil_SleepTTCCommon(u32 delay, u64 frequency);
-void XTime_StartTTCTimer();
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_SLEEPTIMER_H */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/da/b04ace575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/da/b04ace575243001d18b399c1eb9b3628
deleted file mode 100644
index cb45d29..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/da/b04ace575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,90 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xdmaps_hw.c
-* @addtogroup dmaps_v2_8
-* @{
-*
-* This file contains the implementation of the interface reset functionality
-* for XDmaPs driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.06a kpc 10/07/13 First release
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xdmaps_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-#ifndef XDMAPS_MAX_WAIT
-#define XDMAPS_MAX_WAIT 4000
-#endif
-/************************** Function Prototypes *****************************/
-
-/************************** Variable Definitions ****************************/
-
-/*****************************************************************************/
-/**
-* This function perform the reset sequence to the given dmaps interface by
-* configuring the appropriate control bits in the dmaps specifc registers
-* the dmaps reset squence involves the following steps
-* Disable all the interuupts
-* Clear the pending interrupts
-* Kill all the active channel threads
-* Kill the manager thread
-*
-* @param BaseAddress of the interface
-*
-* @return N/A
-*
-* @note
-* This function will not modify the slcr registers that are relavant for
-* dmaps controller
-******************************************************************************/
-void XDmaPs_ResetHw(u32 BaseAddress)
-{
- u32 DbgInst;
- u32 WaitCount = 0;
- u32 ChanIndex;
-
- /* Disable all the interrupts */
- XDmaPs_WriteReg(BaseAddress, XDMAPS_INTEN_OFFSET, 0x00);
- /* Clear the interrupts */
- XDmaPs_WriteReg(BaseAddress, XDMAPS_INTCLR_OFFSET, XDMAPS_INTCLR_ALL_MASK);
- /* Kill the dma channel threads */
- for (ChanIndex=0; ChanIndex < XDMAPS_CHANNELS_PER_DEV; ChanIndex++) {
- while ((XDmaPs_ReadReg(BaseAddress, XDMAPS_DBGSTATUS_OFFSET)
- & XDMAPS_DBGSTATUS_BUSY)
- && (WaitCount < XDMAPS_MAX_WAIT))
- WaitCount++;
-
- DbgInst = XDmaPs_DBGINST0(0, 0x01, ChanIndex, 1);
- XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
- XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);
- XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
- }
- /* Kill the manager thread */
- DbgInst = XDmaPs_DBGINST0(0, 0x01, 0, 0);
- XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst);
- XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0);
- XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0);
-}
-
-
-
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/da/d0d86a585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/da/d0d86a585243001d18b399c1eb9b3628
deleted file mode 100644
index 97070df..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/da/d0d86a585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,67 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2017 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_errata.h
-*
-* @addtogroup a53_errata Cortex A53 64 bit Processor Errata Support
-* @{
-* Various ARM errata are handled in the standalone BSP. The implementation for
-* errata handling follows ARM guidelines and is based on the open source Linux
-* support for these errata.
-*
-* @note
-* The errata handling is enabled by default. To disable handling of all the
-* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
-* disable errata on a per-erratum basis, un-define relevant macros in
-* xil_errata.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 6.4 mus 08/11/17 First release
-*
-*
-******************************************************************************/
-#ifndef XIL_ERRATA_H
-#define XIL_ERRATA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @name errata_definitions
- *
- * The errata conditions handled in the standalone BSP are listed below
- * @{
- */
-
-#define ENABLE_ARM_ERRATA 1
-
-#ifdef ENABLE_ARM_ERRATA
-
-/**
- * Errata No: 855873
- * Description: An eviction might overtake a cache clean operation
- */
-#define CONFIG_ARM_ERRATA_855873 1
-
-
-/*@}*/
-#endif /* ENABLE_ARM_ERRATA */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_ERRATA_H */
-/**
-* @} End of "addtogroup a53_errata".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/da/d0ed28585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/da/d0ed28585243001d18b399c1eb9b3628
deleted file mode 100644
index 0cdfc1e..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/da/d0ed28585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,156 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xscuwdt_hw.h
-* @addtogroup scuwdt_v2_4
-* @{
-*
-* This file contains the hardware interface to the Xilinx SCU private Watch Dog
-* Timer (XSCUWDT).
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
-* of 0x20 as the base address obtained from the tools
-* starts at 0x20.
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-#ifndef XSCUWDT_HW_H /**< prevent circular inclusions */
-#define XSCUWDT_HW_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- * Offsets of registers from the start of the device. The WDT registers start at
- * an offset 0x20
- * @{
- */
-
-#define XSCUWDT_LOAD_OFFSET 0x00U /**< Watchdog Load Register */
-#define XSCUWDT_COUNTER_OFFSET 0x04U /**< Watchdog Counter Register */
-#define XSCUWDT_CONTROL_OFFSET 0x08U /**< Watchdog Control Register */
-#define XSCUWDT_ISR_OFFSET 0x0CU /**< Watchdog Interrupt Status Register */
-#define XSCUWDT_RST_STS_OFFSET 0x10U /**< Watchdog Reset Status Register */
-#define XSCUWDT_DISABLE_OFFSET 0x14U /**< Watchdog Disable Register */
-/* @} */
-
-/** @name Watchdog Control register
- * This register bits control the prescaler, WD/Timer mode, Intr enable,
- * auto-reload, watchdog enable.
- * @{
- */
-
-#define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
-#define XSCUWDT_CONTROL_PRESCALER_SHIFT 8U
-#define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008U /**< Watchdog/Timer mode */
-#define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004U /**< Intr enable (in
- timer mode) */
-#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload (in
- timer mode) */
-#define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001U /**< Watchdog enable */
-/* @} */
-
-/** @name Interrupt Status register
- * This register indicates the Counter register has reached zero in Counter
- * mode.
- * @{
- */
-
-#define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
-/*@}*/
-
-/** @name Reset Status register
- * This register indicates the Counter register has reached zero in Watchdog
- * mode and a reset request is sent.
- * @{
- */
-
-#define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001U /**< Time out occurred */
-/*@}*/
-
-/** @name Disable register
- * This register is used to switch from watchdog mode to timer mode.
- * The software must write 0x12345678 and 0x87654321 successively to the
- * Watchdog Disable Register so that the watchdog mode bit in the Watchdog
- * Control Register is set to zero.
- * @{
- */
-#define XSCUWDT_DISABLE_VALUE1 0x12345678U /**< Watchdog mode disable
- value 1 */
-#define XSCUWDT_DISABLE_VALUE2 0x87654321U /**< Watchdog mode disable
- value 2 */
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note C-style signature:
-* u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuWdt_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + ((u32)RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/da/e054c5585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/da/e054c5585243001d18b399c1eb9b3628
deleted file mode 100644
index becf67e..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/da/e054c5585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,169 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file vectors.c
-*
-* This file contains the C level vectors for the ARM Cortex A9 core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 10/20/09 Initial version, moved over from bsp area
-* 6.0 mus 27/07/16 Consolidated vectors for a53,a9 and r5 processor
-* and added UndefinedException for a53 32 bit and r5
-* processor
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "xil_exception.h"
-#include "vectors.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-typedef struct {
- Xil_ExceptionHandler Handler;
- void *Data;
-} XExc_VectorTableEntry;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-extern XExc_VectorTableEntry XExc_VectorTable[];
-
-/************************** Function Prototypes ******************************/
-
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the FIQ interrupt called from the vectors.s
-* file.
-*
-* @return None.
-*
-******************************************************************************/
-void FIQInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[
- XIL_EXCEPTION_ID_FIQ_INT].Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the IRQ interrupt called from the vectors.s
-* file.
-*
-* @return None.
-*
-******************************************************************************/
-void IRQInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[
- XIL_EXCEPTION_ID_IRQ_INT].Data);
-}
-
-#if !defined (__aarch64__)
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the Undefined exception called from the
-* vectors.s file.
-*
-* @return None.
-*
-******************************************************************************/
-void UndefinedException(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_UNDEFINED_INT].Handler(XExc_VectorTable[
- XIL_EXCEPTION_ID_UNDEFINED_INT].Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the SW Interrupt called from the vectors.s
-* file.
-*
-* @return None.
-*
-******************************************************************************/
-void SWInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_SWI_INT].Handler(XExc_VectorTable[
- XIL_EXCEPTION_ID_SWI_INT].Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the DataAbort Interrupt called from the
-* vectors.s file.
-*
-* @return None.
-*
-******************************************************************************/
-void DataAbortInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Handler(
- XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the PrefetchAbort Interrupt called from the
-* vectors.s file.
-*
-* @return None.
-*
-******************************************************************************/
-void PrefetchAbortInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler(
- XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data);
-}
-#else
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the Synchronous Interrupt called from the vectors.s
-* file.
-*
-* @return None.
-*
-******************************************************************************/
-void SynchronousInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_SYNC_INT].Handler(XExc_VectorTable[
- XIL_EXCEPTION_ID_SYNC_INT].Data);
-}
-
-/*****************************************************************************/
-/**
-*
-* This is the C level wrapper for the SError Interrupt called from the
-* vectors.s file.
-*
-* @return None.
-*
-******************************************************************************/
-void SErrorInterrupt(void)
-{
- XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Handler(
- XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Data);
-}
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/db/103975585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/db/103975585243001d18b399c1eb9b3628
deleted file mode 100644
index b8ea1ea..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/db/103975585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,163 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xreg_cortexa53.h
-*
-* This header file contains definitions for using inline assembler code. It is
-* written specifically for the GNU compiler.
-*
-* All of the ARM Cortex A53 GPRs, SPRs, and Debug Registers are defined along
-* with the positions of the bits within the registers.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/29/14 First release
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
-* inside the APIs
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep
-* implementation
-* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
-* displaying same warnings multiple times. It fixes CR#1090562.
-*
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XTIME_H /* prevent circular inclusions */
-#define XTIME_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xparameters.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-static inline u64 arch_counter_get_cntvct(void)
- {
- u64 cval;
- __asm__ __volatile__("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
- return cval;
- }
-/**************************** Type Definitions *******************************/
-
-typedef u64 XTime;
-
-/************************** Constant Definitions *****************************/
-#if defined (SLEEP_TIMER_BASEADDR)
-#define COUNTS_PER_SECOND SLEEP_TIMER_FREQUENCY
-#else
-#define COUNTS_PER_SECOND XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ
-#endif
-
-#define XIOU_SCNTRS_BASEADDR 0xFF260000U
-#define XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET 0x00000000U
-#define XIOU_SCNTRS_FREQ_REG_OFFSET 0x00000020U
-#define XIOU_SCNTRS_FREQ XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ
-#define XIOU_SCNTRS_CNT_CNTRL_REG_EN 0x00000001U
-#define XIOU_SCNTRS_CNT_CNTRL_REG_EN_MASK 0x00000001U
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void XTime_StartTimer(void);
-/**
- *@endcond
- */
-
-void XTime_SetTime(XTime Xtime_Global);
-void XTime_GetTime(XTime *Xtime_Global);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XTIME_H */
-/**
-* @} End of "addtogroup a53_32_time_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dc/50332b545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dc/50332b545243001d18b399c1eb9b3628
deleted file mode 100644
index e1bcd93..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dc/50332b545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,762 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
- *
- * @file xemacps_bd.h
-* @addtogroup emacps_v3_15
-* @{
- *
- * This header provides operations to manage buffer descriptors in support
- * of scatter-gather DMA.
- *
- * The API exported by this header defines abstracted macros that allow the
- * user to read/write specific BD fields.
- *
- * Buffer Descriptors
- *
- * A buffer descriptor (BD) defines a DMA transaction. The macros defined by
- * this header file allow access to most fields within a BD to tailor a DMA
- * transaction according to user and hardware requirements. See the hardware
- * IP DMA spec for more information on BD fields and how they affect transfers.
- *
- * The XEmacPs_Bd structure defines a BD. The organization of this structure
- * is driven mainly by the hardware for use in scatter-gather DMA transfers.
- *
- * Performance
- *
- * Limiting I/O to BDs can improve overall performance of the DMA channel.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -------------------------------------------------------
- * 1.00a wsy 01/10/10 First release
- * 2.1 srt 07/15/14 Add support for Zynq Ultrascale MP GEM specification
- * and 64-bit changes.
- * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
- * 3.0 hk 02/20/15 Added support for jumbo frames.
- * Disable extended mode. Perform all 64 bit changes under
- * check for arch64.
- * 3.2 hk 11/18/15 Change BD typedef and number of words.
- * 3.8 hk 08/18/18 Remove duplicate definition of XEmacPs_BdSetLength
- * 3.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
- *
- *
- *
- * ***************************************************************************
- */
-
-#ifndef XEMACPS_BD_H /* prevent circular inclusions */
-#define XEMACPS_BD_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-#ifdef __aarch64__
-/* Minimum BD alignment */
-#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U
-#define XEMACPS_BD_NUM_WORDS 4U
-#else
-/* Minimum BD alignment */
-#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U
-#define XEMACPS_BD_NUM_WORDS 2U
-#endif
-
-/**
- * The XEmacPs_Bd is the type for buffer descriptors (BDs).
- */
-typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- * Zero out BD fields
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Nothing
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClear(BdPtr) \
- memset((BdPtr), 0, sizeof(XEmacPs_Bd))
-
-/****************************************************************************/
-/**
-*
-* Read the given Buffer Descriptor word.
-*
-* @param BaseAddress is the base address of the BD to read
-* @param Offset is the word offset to be read
-*
-* @return The 32-bit value of the field
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)
-*
-*****************************************************************************/
-#define XEmacPs_BdRead(BaseAddress, Offset) \
- (*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
-
-/****************************************************************************/
-/**
-*
-* Write the given Buffer Descriptor word.
-*
-* @param BaseAddress is the base address of the BD to write
-* @param Offset is the word offset to be written
-* @param Data is the 32-bit value to write to the field
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)
-*
-*****************************************************************************/
-#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \
- (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
-
-/*****************************************************************************/
-/**
- * Set the BD's Address field (word 0).
- *
- * @param BdPtr is the BD pointer to operate on
- * @param Addr is the value to write to BD's status field.
- *
- * @note :
- *
- * C-style signature:
- * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
- *
- *****************************************************************************/
-#if defined(__aarch64__) || defined(__arch64__)
-#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- (u32)((Addr) & ULONG64_LO_MASK)); \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
- (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
-#else
-#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
-#endif
-
-/*****************************************************************************/
-/**
- * Set the BD's Address field (word 0).
- *
- * @param BdPtr is the BD pointer to operate on
- * @param Addr is the value to write to BD's status field.
- *
- * @note : Due to some bits are mixed within receive BD's address field,
- * read-modify-write is performed.
- *
- * C-style signature:
- * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
- *
- *****************************************************************************/
-#ifdef __aarch64__
-#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- ~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
- (u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
-#else
-#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))
-#endif
-
-/*****************************************************************************/
-/**
- * Set the BD's Status field (word 1).
- *
- * @param BdPtr is the BD pointer to operate on
- * @param Data is the value to write to BD's status field.
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetStatus(BdPtr, Data) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))
-
-
-/*****************************************************************************/
-/**
- * Retrieve the BD's Packet DMA transfer status word (word 1).
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Status word
- *
- * @note
- * C-style signature:
- * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)
- *
- * Due to the BD bit layout differences in transmit and receive. User's
- * caution is required.
- *****************************************************************************/
-#define XEmacPs_BdGetStatus(BdPtr) \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
-
-
-/*****************************************************************************/
-/**
- * Get the address (bits 0..31) of the BD's buffer address (word 0)
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#if defined(__aarch64__) || defined(__arch64__)
-#define XEmacPs_BdGetBufAddr(BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
-#else
-#define XEmacPs_BdGetBufAddr(BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
-#endif
-
-/*****************************************************************************/
-/**
- * Set transfer length in bytes for the given BD. The length must be set each
- * time a BD is submitted to hardware.
- *
- * @param BdPtr is the BD pointer to operate on
- * @param LenBytes is the number of bytes to transfer.
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
- XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
-
-
-/*****************************************************************************/
-/**
- * Retrieve the BD length field.
- *
- * For Tx channels, the returned value is the same as that written with
- * XEmacPs_BdSetLength().
- *
- * For Rx channels, the returned value is the size of the received packet.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Length field processed by hardware or set by
- * XEmacPs_BdSetLength().
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
- * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
- *
- *****************************************************************************/
-#define XEmacPs_BdGetLength(BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_LEN_MASK)
-
-/*****************************************************************************/
-/**
- * Retrieve the RX frame size.
- *
- * The returned value is the size of the received packet.
- * This API supports jumbo frame sizes if enabled.
- *
- * @param InstancePtr is the pointer to XEmacps instance
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return Length field processed by hardware or set by
- * XEmacPs_BdSetLength().
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr)
- * RxBufMask is dependent on whether jumbo is enabled or not.
- *
- *****************************************************************************/
-#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \
- (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- (InstancePtr)->RxBufMask)
-
-/*****************************************************************************/
-/**
- * Test whether the given BD has been marked as the last BD of a packet.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsLast(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Tell the DMA engine that the given transmit BD marks the end of the current
- * packet to be processed.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetLast(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_LAST_MASK))
-
-
-/*****************************************************************************/
-/**
- * Tell the DMA engine that the current packet does not end with the given
- * BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearLast(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_LAST_MASK))
-
-
-/*****************************************************************************/
-/**
- * Set this bit to mark the last descriptor in the receive buffer descriptor
- * list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-/*#define XEmacPs_BdSetRxWrap(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
- XEMACPS_RXBUF_WRAP_MASK))
-*/
-
-/*****************************************************************************/
-/**
- * Determine the wrap bit of the receive BD which indicates end of the
- * BD list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxWrap(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Sets this bit to mark the last descriptor in the transmit buffer
- * descriptor list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-/*#define XEmacPs_BdSetTxWrap(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_WRAP_MASK))
-*/
-
-/*****************************************************************************/
-/**
- * Determine the wrap bit of the transmit BD which indicates end of the
- * BD list.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxWrap(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/*
- * Must clear this bit to enable the MAC to write data to the receive
- * buffer. Hardware sets this bit once it has successfully written a frame to
- * memory. Once set, software has to clear the bit before the buffer can be
- * used again. This macro clear the new bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearRxNew(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- ~XEMACPS_RXBUF_NEW_MASK))
-
-
-/*****************************************************************************/
-/**
- * Determine the new bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxNew(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
- XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Software sets this bit to disable the buffer to be read by the hardware.
- * Hardware sets this bit for the first buffer of a frame once it has been
- * successfully transmitted. This macro sets this bit of transmit BD to avoid
- * confusion.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetTxUsed(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_USED_MASK))
-
-
-/*****************************************************************************/
-/**
- * Software clears this bit to enable the buffer to be read by the hardware.
- * Hardware sets this bit for the first buffer of a frame once it has been
- * successfully transmitted. This macro clears this bit of transmit BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearTxUsed(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_USED_MASK))
-
-
-/*****************************************************************************/
-/**
- * Determine the used bit of the transmit BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxUsed(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if a frame fails to be transmitted due to too many retries.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxRetry(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if a frame fails to be transmitted due to data can not be
- * feteched in time or buffers are exhausted.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxUrun(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if a frame fails to be transmitted due to buffer is exhausted
- * mid-frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsTxExh(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Sets this bit, no CRC will be appended to the current frame. This control
- * bit must be set for the first buffer in a frame and will be ignored for
- * the subsequent buffers of a frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * This bit must be clear when using the transmit checksum generation offload,
- * otherwise checksum generation and substitution will not occur.
- *
- * C-style signature:
- * UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdSetTxNoCRC(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
- XEMACPS_TXBUF_NOCRC_MASK))
-
-
-/*****************************************************************************/
-/**
- * Clear this bit, CRC will be appended to the current frame. This control
- * bit must be set for the first buffer in a frame and will be ignored for
- * the subsequent buffers of a frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * This bit must be clear when using the transmit checksum generation offload,
- * otherwise checksum generation and substitution will not occur.
- *
- * C-style signature:
- * UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdClearTxNoCRC(BdPtr) \
- (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
- XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- ~XEMACPS_TXBUF_NOCRC_MASK))
-
-
-/*****************************************************************************/
-/**
- * Determine the broadcast bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxBcast(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the multicast hash bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxMultiHash(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the unicast hash bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxUniHash(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if the received frame is a VLAN Tagged frame.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxVlan(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if the received frame has Type ID of 8100h and null VLAN
- * identifier(Priority tag).
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxPri(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine if the received frame's Concatenation Format Indicator (CFI) of
- * the frames VLANTCI field was set.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxCFI(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the End Of Frame (EOF) bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxEOF(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
-
-
-/*****************************************************************************/
-/**
- * Determine the Start Of Frame (SOF) bit of the receive BD.
- *
- * @param BdPtr is the BD pointer to operate on
- *
- * @note
- * C-style signature:
- * UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
- *
- *****************************************************************************/
-#define XEmacPs_BdIsRxSOF(BdPtr) \
- ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
- XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
-
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dc/513cf7515243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dc/513cf7515243001d18b399c1eb9b3628
deleted file mode 100644
index ac01e66..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dc/513cf7515243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,2 +0,0 @@
-/Debug/
-/Release/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dc/909ec5545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dc/909ec5545243001d18b399c1eb9b3628
deleted file mode 100644
index a3e2069..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dc/909ec5545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,198 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xqspips_hw.c
-* @addtogroup qspips_v3_9
-* @{
-*
-* Contains low level functions, primarily reset related.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 2.03a hk 09/17/13 First release
-* 3.1 hk 06/19/14 When writing to the configuration register, set/reset
-* required bits leaving reserved bits untouched. CR# 796813.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xqspips_hw.h"
-#include "xqspips.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Pre-scaler value for divided by 4
- *
- * Pre-scaler value for divided by 4
- *
- * @{
- */
-#define XQSPIPS_CR_PRESC_DIV_BY_4 0x01
-/* @} */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-
-/*****************************************************************************/
-/**
-*
-* Resets QSPI by disabling the device and bringing it to reset state through
-* register writes.
-*
-* @param BaseAddress
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XQspiPs_ResetHw(u32 BaseAddress)
-{
- u32 ConfigReg;
-
- /*
- * Disable interrupts
- */
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_IDR_OFFSET,
- XQSPIPS_IXR_DISABLE_ALL);
-
- /*
- * Disable device
- */
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
- 0);
-
- /*
- * De-assert slave select lines.
- */
- ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
- ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
-
- /*
- * Write default value to RX and TX threshold registers
- * RX threshold should be set to 1 here because the corresponding
- * status bit is used next to clear the RXFIFO
- */
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_TXWR_OFFSET,
- (XQSPIPS_TXWR_RESET_VALUE & XQSPIPS_TXWR_MASK));
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_RXWR_OFFSET,
- (XQSPIPS_RXWR_RESET_VALUE & XQSPIPS_RXWR_MASK));
-
- /*
- * Clear RXFIFO
- */
- while ((XQspiPs_ReadReg(BaseAddress,XQSPIPS_SR_OFFSET) &
- XQSPIPS_IXR_RXNEMPTY_MASK) != 0) {
- XQspiPs_ReadReg(BaseAddress, XQSPIPS_RXD_OFFSET);
- }
-
- /*
- * Clear status register by reading register and
- * writing 1 to clear the write to clear bits
- */
- XQspiPs_ReadReg(BaseAddress, XQSPIPS_SR_OFFSET);
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_SR_OFFSET,
- XQSPIPS_IXR_WR_TO_CLR_MASK);
-
- /*
- * Write default value to configuration register
- */
- ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
- ConfigReg |= XQSPIPS_CR_RESET_MASK_SET;
- ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR;
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
-
- /*
- * De-select linear mode
- */
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
- 0x0);
-
-}
-
-/*****************************************************************************/
-/**
-*
-* Initializes QSPI to Linear mode with default QSPI boot settings.
-*
-* @param BaseAddress
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XQspiPs_LinearInit(u32 BaseAddress)
-{
- u32 BaudRateDiv;
- u32 LinearCfg;
- u32 ConfigReg;
-
- /*
- * Baud rate divisor for dividing by 4. Value of CR bits [5:3]
- * should be set to 0x001; hence shift the value and use the mask.
- */
- BaudRateDiv = ( (XQSPIPS_CR_PRESC_DIV_BY_4) <<
- XQSPIPS_CR_PRESC_SHIFT) & XQSPIPS_CR_PRESC_MASK;
- /*
- * Write configuration register with default values, slave selected &
- * pre-scaler value for divide by 4
- */
- ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
- ConfigReg |= (XQSPIPS_CR_RESET_MASK_SET | BaudRateDiv);
- ConfigReg &= ~(XQSPIPS_CR_RESET_MASK_CLR | XQSPIPS_CR_SSCTRL_MASK);
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
-
- /*
- * Write linear configuration register with default value -
- * enable linear mode and use fast read.
- */
-
- if(XPAR_XQSPIPS_0_QSPI_MODE == XQSPIPS_CONNECTION_MODE_SINGLE){
-
- LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE;
-
- }else if(XPAR_XQSPIPS_0_QSPI_MODE ==
- XQSPIPS_CONNECTION_MODE_STACKED){
-
- LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
- XQSPIPS_LQSPI_CR_TWO_MEM_MASK;
-
- }else if(XPAR_XQSPIPS_0_QSPI_MODE ==
- XQSPIPS_CONNECTION_MODE_PARALLEL){
-
- LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
- XQSPIPS_LQSPI_CR_TWO_MEM_MASK |
- XQSPIPS_LQSPI_CR_SEP_BUS_MASK;
-
- }
-
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
- LinearCfg);
-
- /*
- * Enable device
- */
- XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
- XQSPIPS_ER_ENABLE_MASK);
-
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dc/b1b548595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dc/b1b548595243001d18b399c1eb9b3628
deleted file mode 100644
index b00e96a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dc/b1b548595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,27 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#ifndef UNDEFINE_FILE_OPS
-#include
-#include "xil_types.h"
-#include
-struct tms* tms;
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) clock_t _times(struct tms* tms);
-}
-#endif
-
-__attribute__((weak)) clock_t _times(struct tms* tms)
-{
- (void)tms;
-
- errno = EIO;
- return (-1);
-}
-
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dc/e05abe595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dc/e05abe595243001d18b399c1eb9b3628
deleted file mode 100644
index 14446f4..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dc/e05abe595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,143 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xplatform_info.c
-* @addtogroup common_platform_info Hardware Platform Information
-* @{
-* This file contains information about hardware for which the code is built
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 5.00 pkp 12/15/14 Initial release
-* 5.04 pkp 01/12/16 Added platform information support for Cortex-A53 32bit
-* mode
-* 6.00 mus 17/08/16 Removed unused variable from XGetPlatform_Info
-* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
-* function for PMUFW.
-* ms 06/13/17 Added PSU_PMU macro to provide support of
-* XGetPlatform_Info function for PMUFW.
-* mus 08/17/17 Add EL1 NS mode support for
-* XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info
-* APIs.
-* 7.0 aru 03/15/19 Check for versal before aarch64 and armr5
-* in XGetPlatform_Info()
-* 7.2 adk 08/01/20 Added versal support for the XGetPSVersion_Info function.
-* 7.6 mus 08/23/21 Updated prototypes for functions which are not taking any
-* arguments with void keyword. This has been done to fix
-* compilation warnings with "-Wstrict-prototypes" flag.
-* It fixes CR#1108601.
-* 7.6 mus 08/30/21 Updated flag checking to fix compilation warnings
-* reported with "-Wundef" flag. It fixes CR#1108601.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xplatform_info.h"
-#if defined (__aarch64__)
-#include "bspconfig.h"
-#include "xil_smc.h"
-#endif
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* @brief This API is used to provide information about platform
-*
-* @return The information about platform defined in xplatform_info.h
-*
-******************************************************************************/
-u32 XGetPlatform_Info(void)
-{
-#if defined (versal)
- return XPLAT_VERSAL;
-#elif defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU)
- return XPLAT_ZYNQ_ULTRA_MP;
-#elif defined (__microblaze__)
- return XPLAT_MICROBLAZE;
-#else
- return XPLAT_ZYNQ;
-#endif
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief This API is used to provide information about zynq ultrascale MP platform
-*
-* @return The information about zynq ultrascale MP platform defined in
-* xplatform_info.h
-*
-******************************************************************************/
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
-u32 XGet_Zynq_UltraMp_Platform_info(void)
-{
-#if EL1_NONSECURE
- XSmc_OutVar reg;
- /*
- * This SMC call will return,
- * idcode - upper 32 bits of reg.Arg0
- * version - lower 32 bits of reg.Arg1
- */
- reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
- return (u32)((reg.Arg1 >> XPLAT_INFO_SHIFT) & XPLAT_INFO_MASK);
-#else
- u32 reg;
- reg = ((Xil_In32(XPLAT_PS_VERSION_ADDRESS) >> XPLAT_INFO_SHIFT )
- & XPLAT_INFO_MASK);
- return reg;
-#endif
-}
-#endif
-
-/*****************************************************************************/
-/**
-*
-* @brief This API is used to provide information about PS Silicon version
-*
-* @return The information about PS Silicon version.
-*
-******************************************************************************/
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU) || defined (versal)
-u32 XGetPSVersion_Info(void)
-{
-#if EL1_NONSECURE
- /*
- * This SMC call will return,
- * idcode - upper 32 bits of reg.Arg0
- * version - lower 32 bits of reg.Arg1
- */
- XSmc_OutVar reg;
- reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
- return (u32)((reg.Arg1 & XPS_VERSION_INFO_MASK) >>
- XPS_VERSION_INFO_SHIFT);
-#else
- u32 reg;
- reg = (Xil_In32(XPLAT_PS_VERSION_ADDRESS)
- & XPS_VERSION_INFO_MASK);
- return (reg >> XPS_VERSION_INFO_SHIFT);
-#endif
-}
-#endif
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dd/30df13585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dd/30df13585243001d18b399c1eb9b3628
deleted file mode 100644
index 6d1f418..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dd/30df13585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,163 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xscugic_intr.c
-* @addtogroup scugic_v4_6
-* @{
-*
-* This file contains the interrupt processing for the driver for the Xilinx
-* Interrupt Controller. The interrupt processing is partitioned separately such
-* that users are not required to use the provided interrupt processing. This
-* file requires other files of the driver to be linked in also.
-*
-* The interrupt handler, XScuGic_InterruptHandler, uses an input argument which
-* is an instance pointer to an interrupt controller driver such that multiple
-* interrupt controllers can be supported. This handler requires the calling
-* function to pass it the appropriate argument, so another level of indirection
-* may be required.
-*
-* The interrupt processing may be used by connecting the interrupt handler to
-* the interrupt system. The handler does not save and restore the processor
-* context but only handles the processing of the Interrupt Controller. The user
-* is encouraged to supply their own interrupt handler when performance tuning is
-* deemed necessary.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------------
-* 1.00a drg 01/19/10 First release
-* 1.01a sdm 11/09/11 XScuGic_InterruptHandler has changed correspondingly
-* since the HandlerTable has now moved to XScuGic_Config.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.10 mus 07/17/18 Updated XScuGic_InterruptHandler to fix array overrun
-* reported by coverity tool. It fixes CR#1006344.
-* 3.10 mus 07/17/18 Updated file to fix the various coding style issues
-* reported by checkpatch. It fixes CR#1006344.
-*
-*
-*
-* @internal
-*
-* This driver assumes that the context of the processor has been saved prior to
-* the calling of the Interrupt Controller interrupt handler and then restored
-* after the handler returns. This requires either the running RTOS to save the
-* state of the machine or that a wrapper be used as the destination of the
-* interrupt vector to save the state of the processor and restore the state
-* after the interrupt handler returns.
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xscugic.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-* This function is the primary interrupt handler for the driver. It must be
-* connected to the interrupt source such that it is called when an interrupt of
-* the interrupt controller is active. It will resolve which interrupts are
-* active and enabled and call the appropriate interrupt handler. It uses
-* the Interrupt Type information to determine when to acknowledge the interrupt.
-* Highest priority interrupts are serviced first.
-*
-* This function assumes that an interrupt vector table has been previously
-* initialized. It does not verify that entries in the table are valid before
-* calling an interrupt handler.
-*
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XScuGic_InterruptHandler(XScuGic *InstancePtr)
-{
-
- u32 InterruptID;
-#if !defined (GICv3)
- u32 IntIDFull;
-#endif
- XScuGic_VectorTableEntry *TablePtr;
-
- /* Assert that the pointer to the instance is valid
- */
- Xil_AssertVoid(InstancePtr != NULL);
-
- /*
- * Read the int_ack register to identify the highest priority
- * interrupt ID and make sure it is valid. Reading Int_Ack will
- * clear the interrupt in the GIC.
- */
-#if defined (GICv3)
- InterruptID = XScuGic_get_IntID();
-#else
- IntIDFull = XScuGic_CPUReadReg(InstancePtr, XSCUGIC_INT_ACK_OFFSET);
- InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
-#endif
- if (XSCUGIC_MAX_NUM_INTR_INPUTS <= InterruptID) {
- goto IntrExit;
- }
-
- /*
- * If the interrupt is shared, do some locking here if
- * there are multiple processors.
- */
- /*
- * If pre-eption is required:
- * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
- * interrupts or the F bit for secure interrupts
- */
-
- /*
- * If we need to change security domains, issue a SMC
- * instruction here.
- */
-
- /*
- * Execute the ISR. Jump into the Interrupt service routine
- * based on the IRQSource. A software trigger is cleared by
- *.the ACK.
- */
- TablePtr = &(InstancePtr->Config->HandlerTable[InterruptID]);
- if (TablePtr != NULL) {
- TablePtr->Handler(TablePtr->CallBackRef);
- }
-
-IntrExit:
- /*
- * Write to the EOI register, we are all done here.
- * Let this function return, the boot code will restore the stack.
- */
-#if defined (GICv3)
- XScuGic_ack_Int(InterruptID);
-
-#else
- XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_EOI_OFFSET, IntIDFull);
-#endif
- /*
- * Return from the interrupt. Change security domains
- * could happen here.
- */
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dd/40907a585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dd/40907a585243001d18b399c1eb9b3628
deleted file mode 100644
index aa29487..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dd/40907a585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,197 +0,0 @@
-/*******************************************************************************
-* Copyright (c) 2018 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-*******************************************************************************/
-
-
-#ifndef __XFPD_SLCR_SECURE_H__
-#define __XFPD_SLCR_SECURE_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *@cond nocomments
- */
-
-/**
- * XfpdSlcrSecure Base Address
- */
-#define XFPD_SLCR_SECURE_BASEADDR 0xFD690000UL
-
-/**
- * Register: XfpdSlcrSecureCtrl
- */
-#define XFPD_SLCR_SECURE_CTRL ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL )
-#define XFPD_SLCR_SECURE_CTRL_RSTVAL 0x00000000UL
-
-#define XFPD_SLCR_SECURE_CTRL_SLVERR_EN_SHIFT 0UL
-#define XFPD_SLCR_SECURE_CTRL_SLVERR_EN_WIDTH 1UL
-#define XFPD_SLCR_SECURE_CTRL_SLVERR_EN_MASK 0x00000001UL
-#define XFPD_SLCR_SECURE_CTRL_SLVERR_EN_DEFVAL 0x0UL
-
-/**
- * Register: XfpdSlcrSecureIsr
- */
-#define XFPD_SLCR_SECURE_ISR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL )
-#define XFPD_SLCR_SECURE_ISR_RSTVAL 0x00000000UL
-
-#define XFPD_SLCR_SECURE_ISR_ADDR_DECODE_ERR_SHIFT 0UL
-#define XFPD_SLCR_SECURE_ISR_ADDR_DECODE_ERR_WIDTH 1UL
-#define XFPD_SLCR_SECURE_ISR_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XFPD_SLCR_SECURE_ISR_ADDR_DECODE_ERR_DEFVAL 0x0UL
-
-/**
- * Register: XfpdSlcrSecureImr
- */
-#define XFPD_SLCR_SECURE_IMR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL )
-#define XFPD_SLCR_SECURE_IMR_RSTVAL 0x00000001UL
-
-#define XFPD_SLCR_SECURE_IMR_ADDR_DECODE_ERR_SHIFT 0UL
-#define XFPD_SLCR_SECURE_IMR_ADDR_DECODE_ERR_WIDTH 1UL
-#define XFPD_SLCR_SECURE_IMR_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XFPD_SLCR_SECURE_IMR_ADDR_DECODE_ERR_DEFVAL 0x1UL
-
-/**
- * Register: XfpdSlcrSecureIer
- */
-#define XFPD_SLCR_SECURE_IER ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL )
-#define XFPD_SLCR_SECURE_IER_RSTVAL 0x00000000UL
-
-#define XFPD_SLCR_SECURE_IER_ADDR_DECODE_ERR_SHIFT 0UL
-#define XFPD_SLCR_SECURE_IER_ADDR_DECODE_ERR_WIDTH 1UL
-#define XFPD_SLCR_SECURE_IER_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XFPD_SLCR_SECURE_IER_ADDR_DECODE_ERR_DEFVAL 0x0UL
-
-/**
- * Register: XfpdSlcrSecureIdr
- */
-#define XFPD_SLCR_SECURE_IDR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL )
-#define XFPD_SLCR_SECURE_IDR_RSTVAL 0x00000000UL
-
-#define XFPD_SLCR_SECURE_IDR_ADDR_DECODE_ERR_SHIFT 0UL
-#define XFPD_SLCR_SECURE_IDR_ADDR_DECODE_ERR_WIDTH 1UL
-#define XFPD_SLCR_SECURE_IDR_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XFPD_SLCR_SECURE_IDR_ADDR_DECODE_ERR_DEFVAL 0x0UL
-
-/**
- * Register: XfpdSlcrSecureItr
- */
-#define XFPD_SLCR_SECURE_ITR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL )
-#define XFPD_SLCR_SECURE_ITR_RSTVAL 0x00000000UL
-
-#define XFPD_SLCR_SECURE_ITR_ADDR_DECODE_ERR_SHIFT 0UL
-#define XFPD_SLCR_SECURE_ITR_ADDR_DECODE_ERR_WIDTH 1UL
-#define XFPD_SLCR_SECURE_ITR_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XFPD_SLCR_SECURE_ITR_ADDR_DECODE_ERR_DEFVAL 0x0UL
-
-/**
- * Register: XfpdSlcrSecureTzCtrlApuDual
- */
-#define XFPD_SLCR_SECURE_TZ_CTRL_APU_DUAL ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000104UL )
-#define XFPD_SLCR_SECURE_TZ_CTRL_APU_DUAL_RSTVAL 0x00000001UL
-
-#define XFPD_SLCR_SECURE_TZ_CTRL_APU_DUAL_N_SHIFT 0UL
-#define XFPD_SLCR_SECURE_TZ_CTRL_APU_DUAL_N_WIDTH 1UL
-#define XFPD_SLCR_SECURE_TZ_CTRL_APU_DUAL_N_MASK 0x00000001UL
-#define XFPD_SLCR_SECURE_TZ_CTRL_APU_DUAL_N_DEFVAL 0x1UL
-
-/**
- * Register: XfpdSlcrSecureTzCtrlXmpu
- */
-#define XFPD_SLCR_SECURE_TZ_CTRL_XMPU ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000108UL )
-#define XFPD_SLCR_SECURE_TZ_CTRL_XMPU_RSTVAL 0x00000001UL
-
-#define XFPD_SLCR_SECURE_TZ_CTRL_XMPU_N_SHIFT 0UL
-#define XFPD_SLCR_SECURE_TZ_CTRL_XMPU_N_WIDTH 1UL
-#define XFPD_SLCR_SECURE_TZ_CTRL_XMPU_N_MASK 0x00000001UL
-#define XFPD_SLCR_SECURE_TZ_CTRL_XMPU_N_DEFVAL 0x1UL
-
-/**
- * Register: XfpdSlcrSecureTzCtrl
- */
-#define XFPD_SLCR_SECURE_TZ_CTRL ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x0000010CUL )
-#define XFPD_SLCR_SECURE_TZ_CTRL_RSTVAL 0x00000001UL
-
-#define XFPD_SLCR_SECURE_TZ_CTRL_N_SHIFT 0UL
-#define XFPD_SLCR_SECURE_TZ_CTRL_N_WIDTH 1UL
-#define XFPD_SLCR_SECURE_TZ_CTRL_N_MASK 0x00000001UL
-#define XFPD_SLCR_SECURE_TZ_CTRL_N_DEFVAL 0x1UL
-
-/**
- * Register: XfpdSlcrSecureTzCtrlCrf
- */
-#define XFPD_SLCR_SECURE_TZ_CTRL_CRF ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000110UL )
-#define XFPD_SLCR_SECURE_TZ_CTRL_CRF_RSTVAL 0x00000001UL
-
-#define XFPD_SLCR_SECURE_TZ_CTRL_CRF_N_SHIFT 0UL
-#define XFPD_SLCR_SECURE_TZ_CTRL_CRF_N_WIDTH 1UL
-#define XFPD_SLCR_SECURE_TZ_CTRL_CRF_N_MASK 0x00000001UL
-#define XFPD_SLCR_SECURE_TZ_CTRL_CRF_N_DEFVAL 0x1UL
-
-/**
- * Register: XfpdSlcrSecureTzCtrlAfifm0
- */
-#define XFPD_SLCR_SECURE_TZ_CTRL_AFIFM0 ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000114UL )
-#define XFPD_SLCR_SECURE_TZ_CTRL_AFIFM0_RSTVAL 0x00000001UL
-
-#define XFPD_SLCR_SECURE_TZ_CTRL_AFIFM0_AXI_N_SHIFT 0UL
-#define XFPD_SLCR_SECURE_TZ_CTRL_AFIFM0_AXI_N_WIDTH 1UL
-#define XFPD_SLCR_SECURE_TZ_CTRL_AFIFM0_AXI_N_MASK 0x00000001UL
-#define XFPD_SLCR_SECURE_TZ_CTRL_AFIFM0_AXI_N_DEFVAL 0x1UL
-
-/**
- * Register: XfpdSlcrSecureTzCtrlAfifm2
- */
-#define XFPD_SLCR_SECURE_TZ_CTRL_AFIFM2 ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000118UL )
-#define XFPD_SLCR_SECURE_TZ_CTRL_AFIFM2_RSTVAL 0x00000001UL
-
-#define XFPD_SLCR_SECURE_TZ_CTRL_AFIFM2_AXI_N_SHIFT 0UL
-#define XFPD_SLCR_SECURE_TZ_CTRL_AFIFM2_AXI_N_WIDTH 1UL
-#define XFPD_SLCR_SECURE_TZ_CTRL_AFIFM2_AXI_N_MASK 0x00000001UL
-#define XFPD_SLCR_SECURE_TZ_CTRL_AFIFM2_AXI_N_DEFVAL 0x1UL
-
-/**
- * Register: XfpdSlcrSecureTzCtrlCci
- */
-#define XFPD_SLCR_SECURE_TZ_CTRL_CCI ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x0000011CUL )
-#define XFPD_SLCR_SECURE_TZ_CTRL_CCI_RSTVAL 0x00000001UL
-
-#define XFPD_SLCR_SECURE_TZ_CTRL_CCI_N_SHIFT 0UL
-#define XFPD_SLCR_SECURE_TZ_CTRL_CCI_N_WIDTH 1UL
-#define XFPD_SLCR_SECURE_TZ_CTRL_CCI_N_MASK 0x00000001UL
-#define XFPD_SLCR_SECURE_TZ_CTRL_CCI_N_DEFVAL 0x1UL
-
-/**
- * Register: XfpdSlcrSecureTzCtrlSmmu
- */
-#define XFPD_SLCR_SECURE_TZ_CTRL_SMMU ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000120UL )
-#define XFPD_SLCR_SECURE_TZ_CTRL_SMMU_RSTVAL 0x00000001UL
-
-#define XFPD_SLCR_SECURE_TZ_CTRL_SMMU_N_SHIFT 0UL
-#define XFPD_SLCR_SECURE_TZ_CTRL_SMMU_N_WIDTH 1UL
-#define XFPD_SLCR_SECURE_TZ_CTRL_SMMU_N_MASK 0x00000001UL
-#define XFPD_SLCR_SECURE_TZ_CTRL_SMMU_N_DEFVAL 0x1UL
-
-/**
- * Register: XfpdSlcrSecureTzprot
- */
-#define XFPD_SLCR_SECURE_TZPROT ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000FF8UL )
-#define XFPD_SLCR_SECURE_TZPROT_RSTVAL 0x00000000UL
-
-#define XFPD_SLCR_SECURE_TZPROT_ACT_SHIFT 0UL
-#define XFPD_SLCR_SECURE_TZPROT_ACT_WIDTH 1UL
-#define XFPD_SLCR_SECURE_TZPROT_ACT_MASK 0x00000001UL
-#define XFPD_SLCR_SECURE_TZPROT_ACT_DEFVAL 0x0UL
-
-/**
- *@endcond
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XFPD_SLCR_SECURE_H__ */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dd/63882f595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dd/63882f595243001d18b399c1eb9b3628
deleted file mode 100644
index 29be8d2..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dd/63882f595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,73 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#ifndef XDEBUG
-#define XDEBUG
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(DEBUG) && !defined(NDEBUG)
-
-#ifndef XDEBUG_WARNING
-#define XDEBUG_WARNING
-#warning DEBUG is enabled
-#endif
-
-int printf(const char *format, ...);
-
-#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */
-#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */
-#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */
-
-#define XDBG_DEBUG_FIFO_REG 0x00000100U /* display register reads/writes */
-#define XDBG_DEBUG_FIFO_RX 0x00000101U /* receive debug messages */
-#define XDBG_DEBUG_FIFO_TX 0x00000102U /* transmit debug messages */
-#define XDBG_DEBUG_FIFO_ALL 0x0000010FU /* all fifo debug messages */
-
-#define XDBG_DEBUG_TEMAC_REG 0x00000400U /* display register reads/writes */
-#define XDBG_DEBUG_TEMAC_RX 0x00000401U /* receive debug messages */
-#define XDBG_DEBUG_TEMAC_TX 0x00000402U /* transmit debug messages */
-#define XDBG_DEBUG_TEMAC_ALL 0x0000040FU /* all temac debug messages */
-
-#define XDBG_DEBUG_TEMAC_ADPT_RX 0x00000800U /* receive debug messages */
-#define XDBG_DEBUG_TEMAC_ADPT_TX 0x00000801U /* transmit debug messages */
-#define XDBG_DEBUG_TEMAC_ADPT_IOCTL 0x00000802U /* ioctl debug messages */
-#define XDBG_DEBUG_TEMAC_ADPT_MISC 0x00000803U /* debug msg for other routines */
-#define XDBG_DEBUG_TEMAC_ADPT_ALL 0x0000080FU /* all temac adapter debug messages */
-
-
-#define xdbg_current_types (XDBG_DEBUG_GENERAL | XDBG_DEBUG_ERROR | XDBG_DEBUG_TEMAC_REG | XDBG_DEBUG_FIFO_RX | XDBG_DEBUG_FIFO_TX | XDBG_DEBUG_FIFO_REG)
-
-#define xdbg_stmnt(x) x
-
-/* In VxWorks, if _WRS_GNU_VAR_MACROS is defined, special syntax is needed for
- * macros that accept variable number of arguments
- */
-#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
-#define xdbg_printf(type, args...) (((type) & xdbg_current_types) ? printf (## args) : 0)
-#else /* ANSI Syntax */
-#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
-#endif
-
-#else /* defined(DEBUG) && !defined(NDEBUG) */
-
-#define xdbg_stmnt(x)
-
-/* See VxWorks comments above */
-#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
-#define xdbg_printf(type, args...)
-#else /* ANSI Syntax */
-#define xdbg_printf(...)
-#endif
-#endif /* defined(DEBUG) && !defined(NDEBUG) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XDEBUG */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dd/a2e14f595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dd/a2e14f595243001d18b399c1eb9b3628
deleted file mode 100644
index bb50751..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/dd/a2e14f595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,86 +0,0 @@
-###############################################################################
-# Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
-# SPDX-License-Identifier: MIT
-###############################################################################
-DRIVER_LIB_VERSION = v1.0
-
-# The following are defined in config.make
-# LIBSOURCES - Based on if MicroBlaze support Exceptions
-# LIBS - Do Build Profile Libraries
-include config.make
-
-AS=$(ASSEMBLER)
-CC=$(COMPILER)
-AR=$(ARCHIVER)
-CP=cp
-COMPILER_FLAGS=-O2 -c
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(subst -pg, , $(COMPILER_FLAGS))
-ECC_FLAGS = $(subst -pg, , $(EXTRA_COMPILER_FLAGS))
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-SRCFILES:=$(wildcard *.c)
-
-ASSEMBLY_SRCFILES:=$(wildcard *.S)
-
-OBJECTS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(filter-out $(wildcard microblaze_interrupt_handler.c), $(wildcard *.c)))))
-
-ASSEMBLY_OBJECTS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(wildcard *.S))))
-
-NON_LTO_OBJECTS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(wildcard microblaze_interrupt_handler.c))))
-
-NON_LTO_FILES = $(wildcard microblaze_interrupt_handler.c)
-INCLUDEFILES=*.h
-
-ECC_FLAGS_NO_FLTO1 = $(subst -flto,,$(ECC_FLAGS))
-ECC_FLAGS_NO_FLTO = $(subst -ffat-lto-objects,,$(ECC_FLAGS_NO_FLTO1))
-
-libs: $(LIBS)
-
-standalone_libs: $(OBJECTS) $(ASSEMBLY_OBJECTS) $(NON_LTO_OBJECTS)
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-ASSEMBLY_DEPFILES := $(ASSEMBLY_SRCFILES:%.S=$(RELEASEDIR)%.d)
-
-include $(wildcard $(ASSEMBLY_DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(NON_LTO_OBJECTS): $(NON_LTO_FILES)
- echo "DEBUG NON_LTO_OBJECTS is $(NON_LTO_OBJECTS)"
- $(CC) $(CC_FLAGS) $(ECC_FLAGS_NO_FLTO) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $<
-
-$(RELEASEDIR)%.o: %.S
- $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $<
-
-$(RELEASEDIR)%.o: %.c
- $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $<
-
-profile_libs:
- $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" AS="$(AS)" libs
-
-include: standalone_includes profile_includes
-
-standalone_includes: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-
-profile_includes:
- $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" AS="$(AS)" include
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf ${ASSEMBLY_OBJECTS}
- rm -rf ${NON_LTO_OBJECTS}
- rm -rf $(DEPFILES)
- rm -rf $(ASSEMBLY_DEPFILES)
- $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" AS="$(AS)" clean
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/de/503cd9565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/de/503cd9565243001d18b399c1eb9b3628
deleted file mode 100644
index fd80a0d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/de/503cd9565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,62 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_clocking.h
-*
-* The xil_clocking.h file contains clocking related functions and macros.
-* certain conditions.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 7.2 sd 12/11/19 First release
-* 7.2 sd 03/20/20 Added checking for isolation case
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ---------------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 6.6 srm 10/23/17 Updated the macros to support user configurable sleep
-* implementation
-* 7.5 mus 04/30/21 Moved pragma message from xtime_l.h to xtime_l.c, to avoid
-* displaying same warnings multiple times. It fixes CR#1090562.
-*
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XTIME_H /* prevent circular inclusions */
-#define XTIME_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xparameters.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-static inline u64 arch_counter_get_cntvct(void)
- {
- u64 cval;
- __asm__ __volatile__("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
- return cval;
- }
-/**************************** Type Definitions *******************************/
-
-typedef u64 XTime;
-
-/************************** Constant Definitions *****************************/
-#if defined (SLEEP_TIMER_BASEADDR)
-#define COUNTS_PER_SECOND SLEEP_TIMER_FREQUENCY
-#else
-#define COUNTS_PER_SECOND XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ
-#endif
-
-#define XIOU_SCNTRS_BASEADDR 0xFF260000U
-#define XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET 0x00000000U
-#define XIOU_SCNTRS_FREQ_REG_OFFSET 0x00000020U
-#define XIOU_SCNTRS_FREQ XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ
-#define XIOU_SCNTRS_CNT_CNTRL_REG_EN 0x00000001U
-#define XIOU_SCNTRS_CNT_CNTRL_REG_EN_MASK 0x00000001U
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-void XTime_StartTimer(void);
-/**
- *@endcond
- */
-
-void XTime_SetTime(XTime Xtime_Global);
-void XTime_GetTime(XTime *Xtime_Global);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XTIME_H */
-/**
-* @} End of "addtogroup a53_32_time_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/de/928978575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/de/928978575243001d18b399c1eb9b3628
deleted file mode 100644
index fd7f472..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/de/928978575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,273 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xgpiops.h
-* @addtogroup gpiops_v3_9
-* @{
-* @details
-*
-* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
-* Controller.
-*
-* The GPIO Controller supports the following features:
-* - 4 banks
-* - Masked writes (There are no masked reads)
-* - Bypass mode
-* - Configurable Interrupts (Level/Edge)
-*
-* This driver is intended to be RTOS and processor independent. Any needs for
-* dynamic memory management, threads or thread mutual exclusion, virtual
-* memory, or cache control must be satisfied by the layer above this driver.
-
-* This driver supports all the features listed above, if applicable.
-*
-* Driver Description
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate to the GPIO.
-*
-* Interrupts
-*
-* The driver provides interrupt management functions and an interrupt handler.
-* Users of this driver need to provide callback functions. An interrupt handler
-* example is available with the driver.
-*
-* Threads
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* Asserts
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* Building the driver
-*
-* The XGpioPs driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sv 01/15/10 First Release
-* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
-* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
-* relevant to Zynq device.The interrupts are disabled
-* for output pins on all banks during initialization.
-* 1.02a hk 08/22/13 Added low level reset API
-* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
-* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
-* passed to APIs. CR# 822636
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/05/17 Added tabspace for return statements in functions of
-* gpiops examples for proper documentation while
-* generating doxygen.
-* 3.3 ms 04/17/17 Added notes about gpio input and output pin description
-* for zcu102 and zc702 boards in polled and interrupt
-* example, configured Interrupt pin to input pin for
-* proper functioning of interrupt example.
-* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
-* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
-* in safety mode and modified the code such as
-* Use of mixed mode arithmetic,Declared the pointer param
-* as Pointer to const,Casting operation to a pointer,
-* Literal value requires a U suffix.
-* 3.5 sne 03/14/19 Added Versal support.
-* 3.6 mus 04/05/19 Replaced XPLAT_versal macro with XPLAT_VERSAL, to be in
-* sync with standalone BSP
-* 3.6 sne 06/12/19 Fixed IAR compiler warning.
-* 3.6 sne 08/14/19 Added interrupt handler support on versal.
-* 3.7 sne 12/04/19 Reverted versal examples support.
-* 3.8 sne 08/28/20 Modify Makefile to support parallel make execution.
-* 3.8 sne 09/17/20 Added description for Versal PS and PMC GPIO pins.
-* 3.9 sne 03/15/21 Fixed MISRA-C violations.
-*
-*
-*
-******************************************************************************/
-#ifndef XGPIOPS_H /* prevent circular inclusions */
-#define XGPIOPS_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xgpiops_hw.h"
-#include "xplatform_info.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Interrupt types
- * @{
- * The following constants define the interrupt types that can be set for each
- * GPIO pin.
- */
-#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */
-#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */
-#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */
-#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */
-#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
-/** @}*/
-
-#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
-#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
-#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
-#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
-#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
-
-#ifdef XPAR_PSU_GPIO_0_BASEADDR
-#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */
-#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */
-#endif
-
-#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a
- * Zynq Ultrascale+ MP GPIO device
- */
-#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
-
-#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
- * Zynq Ultrascale+ MP GPIO device
- * 0 - 25, Bank 0
- * 26 - 51, Bank 1
- * 52 - 77, Bank 2
- * 78 - 109, Bank 3
- * 110 - 141, Bank 4
- * 142 - 173, Bank 5
- */
-#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device
- * 0 - 31, Bank 0
- * 32 - 53, Bank 1
- * 54 - 85, Bank 2
- * 86 - 117, Bank 3
- */
-
-/**************************** Type Definitions *******************************/
-
-/****************************************************************************/
-/**
- * This handler data type allows the user to define a callback function to
- * handle the interrupts for the GPIO device. The application using this
- * driver is expected to define a handler of this type, to support interrupt
- * driven mode. The handler executes in an interrupt context such that minimal
- * processing should be performed.
- *
- * @param CallBackRef is a callback reference passed in by the upper layer
- * when setting the callback functions for a GPIO bank. It is
- * passed back to the upper layer when the callback is invoked. Its
- * type is not important to the driver component, so it is a void
- * pointer.
- * @param Bank is the bank for which the interrupt status has changed.
- * @param Status is the Interrupt status of the GPIO bank.
- *
- *****************************************************************************/
-typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
-
-/**
- * This typedef contains configuration information for a device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- UINTPTR BaseAddr; /**< Register base address */
-} XGpioPs_Config;
-
-/**
- * The XGpioPs driver instance data. The user is required to allocate a
- * variable of this type for the GPIO device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XGpioPs_Config GpioConfig; /**< Device configuration */
- u32 IsReady; /**< Device is initialized and ready */
- XGpioPs_Handler Handler; /**< Status handlers for all banks */
- void *CallBackRef; /**< Callback ref for bank handlers */
- u32 Platform; /**< Platform data */
- u32 MaxPinNum; /**< Max pins in the GPIO device */
- u8 MaxBanks; /**< Max banks in a GPIO device */
- u32 PmcGpio; /**< Flag for accessing PS GPIO for versal*/
-} XGpioPs;
-
-/************************** Variable Definitions *****************************/
-extern XGpioPs_Config XGpioPs_ConfigTable[];
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/* Functions in xgpiops.c */
-s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
- u32 EffectiveAddr);
-
-/* Bank APIs in xgpiops.c */
-u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data);
-void XGpioPs_SetDirection(const XGpioPs *InstancePtr, u8 Bank, u32 Direction);
-u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_SetOutputEnable(const XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
-u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank);
-#ifdef versal
-void XGpioPs_GetBankPin(const XGpioPs *InstancePtr,u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank);
-#else
-void XGpioPs_GetBankPin(u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank);
-#endif
-
-/* Pin APIs in xgpiops.c */
-u32 XGpioPs_ReadPin(const XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_WritePin(const XGpioPs *InstancePtr, u32 Pin, u32 Data);
-void XGpioPs_SetDirectionPin(const XGpioPs *InstancePtr, u32 Pin, u32 Direction);
-u32 XGpioPs_GetDirectionPin(const XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
-u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin);
-
-/* Diagnostic functions in xgpiops_selftest.c */
-s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr);
-
-/* Functions in xgpiops_intr.c */
-/* Bank APIs in xgpiops_intr.c */
-void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
-void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
-u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank);
-u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank);
-void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
-void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
- u32 IntrPolarity, u32 IntrOnAny);
-void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
- u32 *IntrPolarity, u32 *IntrOnAny);
-void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
- XGpioPs_Handler FuncPointer);
-void XGpioPs_IntrHandler(const XGpioPs *InstancePtr);
-
-/* Pin APIs in xgpiops_intr.c */
-void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
-u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin);
-
-void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin);
-u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin);
-u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin);
-void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin);
-
-/* Functions in xgpiops_sinit.c */
-XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/de/a02019565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/de/a02019565243001d18b399c1eb9b3628
deleted file mode 100644
index 9425ff3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/de/a02019565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,48 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file cpu_init.S
-*
-* This file contains CPU specific initialization. Invoked from main CRT
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 5.00 pkp 02/10/14 Initial version
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------
-* 1.00a sv 01/15/10 First Release
-* 1.02a hk 08/22/13 Added low level reset API function prototype and
-* related constant definitions
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/13/15 Corrected reset values of banks.
-* 3.5 sne 03/14/19 Added versal support.
-*
-*
-******************************************************************************/
-#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
-#define XGPIOPS_HW_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register offsets for the GPIO. Each register is 32 bits.
- * @{
- */
-#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /**< Mask and Data Register LSW, WO */
-#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /**< Mask and Data Register MSW, WO */
-#define XGPIOPS_DATA_OFFSET 0x00000040U /**< Data Register, RW */
-#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /**< Data Register - Input, RO */
-#define XGPIOPS_DIRM_OFFSET 0x00000204U /**< Direction Mode Register, RW */
-#define XGPIOPS_OUTEN_OFFSET 0x00000208U /**< Output Enable Register, RW */
-#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /**< Interrupt Mask Register, RO */
-#define XGPIOPS_INTEN_OFFSET 0x00000210U /**< Interrupt Enable Register, WO */
-#define XGPIOPS_INTDIS_OFFSET 0x00000214U /**< Interrupt Disable Register, WO*/
-#define XGPIOPS_INTSTS_OFFSET 0x00000218U /**< Interrupt Status Register, RO */
-#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /**< Interrupt Type Register, RW */
-#define XGPIOPS_INTPOL_OFFSET 0x00000220U /**< Interrupt Polarity Register, RW */
-#define XGPIOPS_INTANY_OFFSET 0x00000224U /**< Interrupt On Any Register, RW */
-/** @} */
-
-/** @name Register offsets for each Bank.
- * @{
- */
-#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /**< Data/Mask Registers offset */
-#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /**< Data Registers offset */
-#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /**< Registers offset */
-/** @} */
-
-/* For backwards compatibility */
-#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40 /**< Mask for backward support */
-
-/** @name Interrupt type reset values for each bank
- * @{
- */
-#ifdef XPAR_PSU_GPIO_0_BASEADDR
-#define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-#define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-#define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-#else
-#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /**< Resets specific to Zynq */
-#define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU /**< Resets specific to Zynq */
-#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU /**< Resets specific to Zynq */
-#endif
-
-#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /**< Reset common to both platforms */
-#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
-/** @} */
-#define XGPIOPS_PS_GPIO_BASEADDR 0xFF0B0000U /**< Flag for Base Address for PS_GPIO in Versal */
-#define XGPIOPS_ZERO 0U /**< Flag for 0 Value */
-#define XGPIOPS_ONE 1U /**< Flag for 1 Value */
-#define XGPIOPS_TWO 2U /**< Flag for 2 Value */
-#define XGPIOPS_THREE 3U /**< Flag for 3 Value */
-#define XGPIOPS_FOUR 4U /**< Flag for 4 Value */
-#define XGPIOPS_SIX 6U /**< Flag for 6 Value */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* This macro reads the given register.
-*
-* @param BaseAddr is the base address of the device.
-* @param RegOffset is the register offset to be read.
-*
-* @return The 32-bit value of the register
-*
-* @note None.
-*
-*****************************************************************************/
-#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + (u32)(RegOffset))
-
-/****************************************************************************/
-/**
-*
-* This macro writes to the given register.
-*
-* @param BaseAddr is the base address of the device.
-* @param RegOffset is the offset of the register to be written.
-* @param Data is the 32-bit value to write to the register.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
-
-/************************** Function Prototypes ******************************/
-
-void XGpioPs_ResetHw(UINTPTR BaseAddress);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XGPIOPS_HW_H */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/df/01ca1b545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/df/01ca1b545243001d18b399c1eb9b3628
deleted file mode 100644
index 6719ab0..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/df/01ca1b545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,62 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file vectors.h
-*
-* This file contains the C level vector prototypes for the ARM Cortex A9 core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a ecm 10/20/10 Initial version, moved over from bsp area
-* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 First release
-* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_ASSERT_H /* prevent circular inclusions */
-#define XIL_ASSERT_H /* by using protection macros */
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-
-
-/************************** Constant Definitions *****************************/
-
-#define XIL_ASSERT_NONE 0U
-#define XIL_ASSERT_OCCURRED 1U
-#define XNULL NULL
-
-extern u32 Xil_AssertStatus;
-extern s32 Xil_AssertWait;
-extern void Xil_Assert(const char8 *File, s32 Line);
-/**
- *@endcond
- */
-void XNullHandler(void *NullParameter);
-
-/**
- * This data type defines a callback to be invoked when an
- * assert occurs. The callback is invoked only when asserts are enabled
- */
-typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#ifndef NDEBUG
-
-/*****************************************************************************/
-/**
-* @brief This assert macro is to be used for void functions. This in
-* conjunction with the Xil_AssertWait boolean can be used to
-* accommodate tests so that asserts which fail allow execution to
-* continue.
-*
-* @param Expression: expression to be evaluated. If it evaluates to
-* false, the assert occurs.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertVoid(Expression) \
-{ \
- if (Expression) { \
- Xil_AssertStatus = XIL_ASSERT_NONE; \
- } else { \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* @brief This assert macro is to be used for functions that do return a
-* value. This in conjunction with the Xil_AssertWait boolean can be
-* used to accommodate tests so that asserts which fail allow execution
-* to continue.
-*
-* @param Expression: expression to be evaluated. If it evaluates to false,
-* the assert occurs.
-*
-* @return Returns 0 unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertNonvoid(Expression) \
-{ \
- if (Expression) { \
- Xil_AssertStatus = XIL_ASSERT_NONE; \
- } else { \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return 0; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* @brief Always assert. This assert macro is to be used for void functions.
-* Use for instances where an assert should always occur.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertVoidAlways() \
-{ \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return; \
-}
-
-/*****************************************************************************/
-/**
-* @brief Always assert. This assert macro is to be used for functions that
-* do return a value. Use for instances where an assert should always
-* occur.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertNonvoidAlways() \
-{ \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return 0; \
-}
-
-
-#else
-
-#define Xil_AssertVoid(Expression)
-#define Xil_AssertVoidAlways()
-#define Xil_AssertNonvoid(Expression)
-#define Xil_AssertNonvoidAlways()
-
-#endif
-
-/************************** Function Prototypes ******************************/
-
-void Xil_AssertSetCallback(Xil_AssertCallback Routine);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_assert_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e/00905a595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e/00905a595243001d18b399c1eb9b3628
deleted file mode 100644
index ab0423e..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e/00905a595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,53 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-* @file microblaze_disable_interrupts.S
-*
-* @addtogroup microblaze_pseudo_asm_macro
-* @{
-*
microblaze_disable_interrupts.S
-* - API to disable Interrupts: void microblaze_disable_interrupts(void)
-*
-* This API Disables interrupts on the MicroBlaze processor. It can be
-* called when entering a critical section of code where a context switch is
-* undesirable.
-*
-*
-* File : microblaze_disable_interrupts.s
-* Date : 2002, March 20.
-* Company: Xilinx
-* Group : Emerging Software Technologies
-*
-* Summary:
-* Disable interrupts on the microblaze.
-*
-*
-******************************************************************************/
-
-#include "xparameters.h"
-
- .text
- .globl microblaze_disable_interrupts
- .ent microblaze_disable_interrupts
- .align 2
-microblaze_disable_interrupts:
-#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
- rtsd r15, 8
- msrclr r0, 0x2
-#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- #Read the MSR register
- mfs r12, rmsr
- #Clear the interrupt enable bit
- andi r12, r12, ~(0x2)
- #Save the MSR register
- mts rmsr, r12
- #Return
- rtsd r15, 8
- nop
-#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- .end microblaze_disable_interrupts
-/**
-* @} End of "addtogroup microblaze_pseudo_asm_macro".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e/10492b565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e/10492b565243001d18b399c1eb9b3628
deleted file mode 100644
index fcc7450..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e/10492b565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,95 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.h
-*
-* @addtogroup r5_cache_apis Cortex R5 Processor Cache Functions
-*
-* Cache functions provide access to cache related operations such as flush
-* and invalidate for instruction and data caches. It gives option to perform
-* the cache operations on a single cacheline, a range of memory and an entire
-* cache.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.00 pkp 02/20/14 First release
-* 6.2 mus 01/27/17 Updated to support IAR compiler
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a wgr 02/28/07 Added cache handling macros.
-* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
-* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
-* used under Xilinx standalone BSP.
-* 1.00a xd 11/03/04 Improved support for doxygen.
-* 1.00a rmm 03/21/02 First release
-* 1.00a wgr 03/22/07 Converted to new coding style.
-* 1.00a rpm 06/29/07 Added udelay macro for standalone
-* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
-* to in MICROBLAZE section
-* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
-*
-*
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XENV_STANDALONE_H
-#define XENV_STANDALONE_H
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-/******************************************************************************
- *
- * Get the processor dependent includes
- *
- ******************************************************************************/
-
-#include
-
-#if defined __MICROBLAZE__
-# include "mb_interface.h"
-# include "xparameters.h" /* XPAR constants used below in MB section */
-
-#elif defined __PPC__
-# include "sleep.h"
-# include "xcache_l.h" /* also include xcache_l.h for caching macros */
-#endif
-
-/******************************************************************************
- *
- * MEMCPY / MEMSET related macros.
- *
- * The following are straight forward implementations of memset and memcpy.
- *
- * NOTE: memcpy may not work if source and target memory area are overlapping.
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
- *
- * Copies a non-overlapping block of memory.
- *
- * @param DestPtr
- * Destination address to copy data to.
- *
- * @param SrcPtr
- * Source address to copy data from.
- *
- * @param Bytes
- * Number of bytes to copy.
- *
- * @return None.
- *
- * @note
- * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
- *
- * @note
- * This implementation MAY BREAK work if source and target memory
- * area are overlapping.
- *
- *****************************************************************************/
-
-#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
- memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
-
-
-
-/*****************************************************************************/
-/**
- *
- * Fills an area of memory with constant data.
- *
- * @param DestPtr
- * Destination address to copy data to.
- *
- * @param Data
- * Value to set.
- *
- * @param Bytes
- * Number of bytes to copy.
- *
- * @return None.
- *
- * @note
- * The use of XENV_MEM_FILL is deprecated. Use memset() instead.
- *
- *****************************************************************************/
-
-#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
- memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
-
-
-
-/******************************************************************************
- *
- * TIME related macros
- *
- ******************************************************************************/
-
-/**
- * A structure that contains a time stamp used by other time stamp macros
- * defined below. This structure is processor dependent.
- */
-typedef s32 XENV_TIME_STAMP;
-
-/*****************************************************************************/
-/**
- *
- * Time is derived from the 64 bit PPC timebase register
- *
- * @param StampPtr is the storage for the retrieved time stamp.
- *
- * @return None.
- *
- * @note
- *
- * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_GET(StampPtr)
-
-/*****************************************************************************/
-/**
- *
- * This macro is not yet implemented and always returns 0.
- *
- * @param Stamp1Ptr is the first sampled time stamp.
- * @param Stamp2Ptr is the second sampled time stamp.
- *
- * @return 0
- *
- * @note
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
-
-/*****************************************************************************/
-/**
- *
- * This macro is not yet implemented and always returns 0.
- *
- * @param Stamp1Ptr is the first sampled time stamp.
- * @param Stamp2Ptr is the second sampled time stamp.
- *
- * @return 0
- *
- * @note
- *
- * This macro must be implemented by the user.
- *
- *****************************************************************************/
-#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
-
-/*****************************************************************************/
-/**
- * XENV_USLEEP(unsigned delay)
- *
- * Delay the specified number of microseconds. Not implemented without OS
- * support.
- *
- * @param delay
- * Number of microseconds to delay.
- *
- * @return None.
- *
- *****************************************************************************/
-
-#ifdef __PPC__
-#define XENV_USLEEP(delay) usleep(delay)
-#define udelay(delay) usleep(delay)
-#else
-#define XENV_USLEEP(delay)
-#define udelay(delay)
-#endif
-
-
-/******************************************************************************
- *
- * CACHE handling macros / mappings
- *
- ******************************************************************************/
-/******************************************************************************
- *
- * Processor independent macros
- *
- ******************************************************************************/
-
-#define XCACHE_ENABLE_CACHE() \
- { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
-
-#define XCACHE_DISABLE_CACHE() \
- { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
-
-
-/******************************************************************************
- *
- * MicroBlaze case
- *
- * NOTE: Currently the following macros will only work on systems that contain
- * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
- * system is built using a xparameters.h file.
- *
- ******************************************************************************/
-
-#if defined __MICROBLAZE__
-
-/* Check if MicroBlaze data cache was built into the core.
- */
-#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
-# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
-# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
-# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
-
-# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
- microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
-
-#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
-# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
-#else
-# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
-#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
-
-#else
-# define XCACHE_ENABLE_DCACHE()
-# define XCACHE_DISABLE_DCACHE()
-# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
-# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
-#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
-
-
-/* Check if MicroBlaze instruction cache was built into the core.
- */
-#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
-# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
-# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
-
-# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
-
-# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
- microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
-
-#else
-# define XCACHE_ENABLE_ICACHE()
-# define XCACHE_DISABLE_ICACHE()
-#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
-
-
-/******************************************************************************
- *
- * PowerPC case
- *
- * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
- * specific memory region (0x80000001). Each bit (0-30) in the regions
- * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
- * range.
- *
- * regions --> cached address range
- * ------------|--------------------------------------------------
- * 0x80000000 | [0, 0x7FFFFFF]
- * 0x00000001 | [0xF8000000, 0xFFFFFFFF]
- * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
- *
- ******************************************************************************/
-
-#elif defined __PPC__
-
-#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
-#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
-#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
-#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
-
-#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
- XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
-
-#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
- XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
-
-#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
-
-
-/******************************************************************************
- *
- * Unknown processor / architecture
- *
- ******************************************************************************/
-
-#else
-/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* #ifndef XENV_STANDALONE_H */
-
- /**
- *@endcond
- */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e0/712305565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e0/712305565243001d18b399c1eb9b3628
deleted file mode 100644
index edf6684..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e0/712305565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,558 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpm_counter.h
-*
-* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions
-*
-* Cortex A9 event counter functions can be utilized to configure and control
-* the Cortex-A9 performance monitor events.
-*
-* Cortex-A9 performance monitor has six event counters which can be used to
-* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines
-* configurations XPM_CNTRCFGx which can be used to program the event counters
-* to count a set of events.
-*
-* @note
-* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
-* being used for time keeping.
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-*
-******************************************************************************/
-
-/**
-*@cond nocomments
-*/
-
-#ifndef XPMCOUNTER_H /* prevent circular inclusions */
-#define XPMCOUNTER_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/************************** Constant Definitions ****************************/
-
-/* Number of performance counters */
-#define XPM_CTRCOUNT 6U
-
-/* The following constants define the Cortex-A9 Performance Monitor Events */
-
-/*
- * Software increment. The register is incremented only on writes to the
- * Software Increment Register
- */
-#define XPM_EVENT_SOFTINCR 0x00U
-
-/*
- * Instruction fetch that causes a refill at (at least) the lowest level(s) of
- * instruction or unified cache. Includes the speculative linefills in the
- * count
- */
-#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
-
-/*
- * Instruction fetch that causes a TLB refill at (at least) the lowest level of
- * TLB. Includes the speculative requests in the count
- */
-#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
-
-/*
- * Data read or write operation that causes a refill at (at least) the lowest
- * level(s)of data or unified cache. Counts the number of allocations performed
- * in the Data Cache due to a read or a write
- */
-#define XPM_EVENT_DATA_CACHEREFILL 0x03U
-
-/*
- * Data read or write operation that causes a cache access at (at least) the
- * lowest level(s) of data or unified cache. This includes speculative reads
- */
-#define XPM_EVENT_DATA_CACHEACCESS 0x04U
-
-/*
- * Data read or write operation that causes a TLB refill at (at least) the
- * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
- * CP15 Cache operation by MVA and CP15 VA to PA operations
- */
-#define XPM_EVENT_DATA_TLBREFILL 0x05U
-
-/*
- * Data read architecturally executed. Counts the number of data read
- * instructions accepted by the Load Store Unit. This includes counting the
- * speculative and aborted LDR/LDM, as well as the reads due to the SWP
- * instructions
- */
-#define XPM_EVENT_DATA_READS 0x06U
-
-/*
- * Data write architecturally executed. Counts the number of data write
- * instructions accepted by the Load Store Unit. This includes counting the
- * speculative and aborted STR/STM, as well as the writes due to the SWP
- * instructions
- */
-#define XPM_EVENT_DATA_WRITE 0x07U
-
-/* Exception taken. Counts the number of exceptions architecturally taken.*/
-#define XPM_EVENT_EXCEPTION 0x09U
-
-/* Exception return architecturally executed.*/
-#define XPM_EVENT_EXCEPRETURN 0x0AU
-
-/*
- * Change to ContextID retired. Counts the number of instructions
- * architecturally executed writing into the ContextID Register
- */
-#define XPM_EVENT_CHANGECONTEXT 0x0BU
-
-/*
- * Software change of PC, except by an exception, architecturally executed.
- * Count the number of PC changes architecturally executed, excluding the PC
- * changes due to taken exceptions
- */
-#define XPM_EVENT_SW_CHANGEPC 0x0CU
-
-/*
- * Immediate branch architecturally executed (taken or not taken). This includes
- * the branches which are flushed due to a previous load/store which aborts
- * late
- */
-#define XPM_EVENT_IMMEDBRANCH 0x0DU
-
-/*
- * Unaligned access architecturally executed. Counts the number of aborted
- * unaligned accessed architecturally executed, and the number of not-aborted
- * unaligned accesses, including the speculative ones
- */
-#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
-
-/*
- * Branch mispredicted/not predicted. Counts the number of mispredicted or
- * not-predicted branches executed. This includes the branches which are flushed
- * due to a previous load/store which aborts late
- */
-#define XPM_EVENT_BRANCHMISS 0x10U
-
-/*
- * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
- * event is not exported on the PMUEVENT bus
- */
-#define XPM_EVENT_CLOCKCYCLES 0x11U
-
-/*
- * Branches or other change in program flow that could have been predicted by
- * the branch prediction resources of the processor. This includes the branches
- * which are flushed due to a previous load/store which aborts late
- */
-#define XPM_EVENT_BRANCHPREDICT 0x12U
-
-/*
- * Java bytecode execute. Counts the number of Java bytecodes being decoded,
- * including speculative ones
- */
-#define XPM_EVENT_JAVABYTECODE 0x40U
-
-/*
- * Software Java bytecode executed. Counts the number of software java bytecodes
- * being decoded, including speculative ones
- */
-#define XPM_EVENT_SWJAVABYTECODE 0x41U
-
-/*
- * Jazelle backward branches executed. Counts the number of Jazelle taken
- * branches being executed. This includes the branches which are flushed due
- * to a previous load/store which aborts late
- */
-#define XPM_EVENT_JAVABACKBRANCH 0x42U
-
-/*
- * Coherent linefill miss Counts the number of coherent linefill requests
- * performed by the Cortex-A9 processor which also miss in all the other
- * Cortex-A9 processors, meaning that the request is sent to the external
- * memory
- */
-#define XPM_EVENT_COHERLINEMISS 0x50U
-
-/*
- * Coherent linefill hit. Counts the number of coherent linefill requests
- * performed by the Cortex-A9 processor which hit in another Cortex-A9
- * processor, meaning that the linefill data is fetched directly from the
- * relevant Cortex-A9 cache
- */
-#define XPM_EVENT_COHERLINEHIT 0x51U
-
-/*
- * Instruction cache dependent stall cycles. Counts the number of cycles where
- * the processor is ready to accept new instructions, but does not receive any
- * due to the instruction side not being able to provide any and the
- * instruction cache is currently performing at least one linefill
- */
-#define XPM_EVENT_INSTRSTALL 0x60U
-
-/*
- * Data cache dependent stall cycles. Counts the number of cycles where the core
- * has some instructions that it cannot issue to any pipeline, and the Load
- * Store unit has at least one pending linefill request, and no pending
- */
-#define XPM_EVENT_DATASTALL 0x61U
-
-/*
- * Main TLB miss stall cycles. Counts the number of cycles where the processor
- * is stalled waiting for the completion of translation table walks from the
- * main TLB. The processor stalls can be due to the instruction side not being
- * able to provide the instructions, or to the data side not being able to
- * provide the necessary data, due to them waiting for the main TLB translation
- * table walk to complete
- */
-#define XPM_EVENT_MAINTLBSTALL 0x62U
-
-/*
- * Counts the number of STREX instructions architecturally executed and
- * passed
- */
-#define XPM_EVENT_STREXPASS 0x63U
-
-/*
- * Counts the number of STREX instructions architecturally executed and
- * failed
- */
-#define XPM_EVENT_STREXFAIL 0x64U
-
-/*
- * Data eviction. Counts the number of eviction requests due to a linefill in
- * the data cache
- */
-#define XPM_EVENT_DATAEVICT 0x65U
-
-/*
- * Counts the number of cycles where the issue stage does not dispatch any
- * instruction because it is empty or cannot dispatch any instructions
- */
-#define XPM_EVENT_NODISPATCH 0x66U
-
-/*
- * Counts the number of cycles where the issue stage is empty
- */
-#define XPM_EVENT_ISSUEEMPTY 0x67U
-
-/*
- * Counts the number of instructions going through the Register Renaming stage.
- * This number is an approximate number of the total number of instructions
- * speculatively executed, and even more approximate of the total number of
- * instructions architecturally executed. The approximation depends mainly on
- * the branch misprediction rate.
- * The renaming stage can handle two instructions in the same cycle so the event
- * is two bits long:
- * - b00 no instructions renamed
- * - b01 one instruction renamed
- * - b10 two instructions renamed
- */
-#define XPM_EVENT_INSTRRENAME 0x68U
-
-/*
- * Counts the number of procedure returns whose condition codes do not fail,
- * excluding all returns from exception. This count includes procedure returns
- * which are flushed due to a previous load/store which aborts late.
- * Only the following instructions are reported:
- * - BX R14
- * - MOV PC LR
- * - POP {..,pc}
- * - LDR pc,[sp],#offset
- * The following instructions are not reported:
- * - LDMIA R9!,{..,PC} (ThumbEE state only)
- * - LDR PC,[R9],#offset (ThumbEE state only)
- * - BX R0 (Rm != R14)
- * - MOV PC,R0 (Rm != R14)
- * - LDM SP,{...,PC} (writeback not specified)
- * - LDR PC,[SP,#offset] (wrong addressing mode)
- */
-#define XPM_EVENT_PREDICTFUNCRET 0x6EU
-
-/*
- * Counts the number of instructions being executed in the main execution
- * pipeline of the processor, the multiply pipeline and arithmetic logic unit
- * pipeline. The counted instructions are still speculative
- */
-#define XPM_EVENT_MAINEXEC 0x70U
-
-/*
- * Counts the number of instructions being executed in the processor second
- * execution pipeline (ALU). The counted instructions are still speculative
- */
-#define XPM_EVENT_SECEXEC 0x71U
-
-/*
- * Counts the number of instructions being executed in the Load/Store unit. The
- * counted instructions are still speculative
- */
-#define XPM_EVENT_LDRSTR 0x72U
-
-/*
- * Counts the number of Floating-point instructions going through the Register
- * Rename stage. Instructions are still speculative in this stage.
- *Two floating-point instructions can be renamed in the same cycle so the event
- * is two bitslong:
- *0b00 no floating-point instruction renamed
- *0b01 one floating-point instruction renamed
- *0b10 two floating-point instructions renamed
- */
-#define XPM_EVENT_FLOATRENAME 0x73U
-
-/*
- * Counts the number of Neon instructions going through the Register Rename
- * stage.Instructions are still speculative in this stage.
- * Two NEON instructions can be renamed in the same cycle so the event is two
- * bits long:
- *0b00 no NEON instruction renamed
- *0b01 one NEON instruction renamed
- *0b10 two NEON instructions renamed
- */
-#define XPM_EVENT_NEONRENAME 0x74U
-
-/*
- * Counts the number of cycles where the processor is stalled because PLD slots
- * are all full
- */
-#define XPM_EVENT_PLDSTALL 0x80U
-
-/*
- * Counts the number of cycles when the processor is stalled and the data side
- * is stalled too because it is full and executing writes to the external
- * memory
- */
-#define XPM_EVENT_WRITESTALL 0x81U
-
-/*
- * Counts the number of stall cycles due to main TLB misses on requests issued
- * by the instruction side
- */
-#define XPM_EVENT_INSTRTLBSTALL 0x82U
-
-/*
- * Counts the number of stall cycles due to main TLB misses on requests issued
- * by the data side
- */
-#define XPM_EVENT_DATATLBSTALL 0x83U
-
-/*
- * Counts the number of stall cycles due to micro TLB misses on the instruction
- * side. This event does not include main TLB miss stall cycles that are already
- * counted in the corresponding main TLB event
- */
-#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
-
-/*
- * Counts the number of stall cycles due to micro TLB misses on the data side.
- * This event does not include main TLB miss stall cycles that are already
- * counted in the corresponding main TLB event
- */
-#define XPM_EVENT_DATA_uTLBSTALL 0x85U
-
-/*
- * Counts the number of stall cycles because of the execution of a DMB memory
- * barrier. This includes all DMB instructions being executed, even
- * speculatively
- */
-#define XPM_EVENT_DMB_STALL 0x86U
-
-/*
- * Counts the number of cycles during which the integer core clock is enabled
- */
-#define XPM_EVENT_INT_CLKEN 0x8AU
-
-/*
- * Counts the number of cycles during which the Data Engine clock is enabled
- */
-#define XPM_EVENT_DE_CLKEN 0x8BU
-
-/*
- * Counts the number of ISB instructions architecturally executed
- */
-#define XPM_EVENT_INSTRISB 0x90U
-
-/*
- * Counts the number of DSB instructions architecturally executed
- */
-#define XPM_EVENT_INSTRDSB 0x91U
-
-/*
- * Counts the number of DMB instructions speculatively executed
- */
-#define XPM_EVENT_INSTRDMB 0x92U
-
-/*
- * Counts the number of external interrupts executed by the processor
- */
-#define XPM_EVENT_EXTINT 0x93U
-
-/*
- * PLE cache line request completed
- */
-#define XPM_EVENT_PLE_LRC 0xA0U
-
-/*
- * PLE cache line request skipped
- */
-#define XPM_EVENT_PLE_LRS 0xA1U
-
-/*
- * PLE FIFO flush
- */
-#define XPM_EVENT_PLE_FLUSH 0xA2U
-
-/*
- * PLE request complete
- */
-#define XPM_EVENT_PLE_CMPL 0xA3U
-
-/*
- * PLE FIFO overflow
- */
-#define XPM_EVENT_PLE_OVFL 0xA4U
-
-/*
- * PLE request programmed
- */
-#define XPM_EVENT_PLE_PROG 0xA5U
-
-/*
- * The following constants define the configurations for Cortex-A9 Performance
- * Monitor Events. Each configuration configures the event counters for a set
- * of events.
- * -----------------------------------------------
- * Config PmCtr0... PmCtr5
- * -----------------------------------------------
- * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR,
- * XPM_EVENT_INSRFETCH_CACHEREFILL,
- * XPM_EVENT_INSTRFECT_TLBREFILL,
- * XPM_EVENT_DATA_CACHEREFILL,
- * XPM_EVENT_DATA_CACHEACCESS,
- * XPM_EVENT_DATA_TLBREFILL }
- *
- * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS,
- * XPM_EVENT_DATA_WRITE,
- * XPM_EVENT_EXCEPTION,
- * XPM_EVENT_EXCEPRETURN,
- * XPM_EVENT_CHANGECONTEXT,
- * XPM_EVENT_SW_CHANGEPC }
- *
- * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH,
- * XPM_EVENT_UNALIGNEDACCESS,
- * XPM_EVENT_BRANCHMISS,
- * XPM_EVENT_CLOCKCYCLES,
- * XPM_EVENT_BRANCHPREDICT,
- * XPM_EVENT_JAVABYTECODE }
- *
- * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE,
- * XPM_EVENT_JAVABACKBRANCH,
- * XPM_EVENT_COHERLINEMISS,
- * XPM_EVENT_COHERLINEHIT,
- * XPM_EVENT_INSTRSTALL,
- * XPM_EVENT_DATASTALL }
- *
- * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL,
- * XPM_EVENT_STREXPASS,
- * XPM_EVENT_STREXFAIL,
- * XPM_EVENT_DATAEVICT,
- * XPM_EVENT_NODISPATCH,
- * XPM_EVENT_ISSUEEMPTY }
- *
- * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME,
- * XPM_EVENT_PREDICTFUNCRET,
- * XPM_EVENT_MAINEXEC,
- * XPM_EVENT_SECEXEC,
- * XPM_EVENT_LDRSTR,
- * XPM_EVENT_FLOATRENAME }
- *
- * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME,
- * XPM_EVENT_PLDSTALL,
- * XPM_EVENT_WRITESTALL,
- * XPM_EVENT_INSTRTLBSTALL,
- * XPM_EVENT_DATATLBSTALL,
- * XPM_EVENT_INSTR_uTLBSTALL }
- *
- * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL,
- * XPM_EVENT_DMB_STALL,
- * XPM_EVENT_INT_CLKEN,
- * XPM_EVENT_DE_CLKEN,
- * XPM_EVENT_INSTRISB,
- * XPM_EVENT_INSTRDSB }
- *
- * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB,
- * XPM_EVENT_EXTINT,
- * XPM_EVENT_PLE_LRC,
- * XPM_EVENT_PLE_LRS,
- * XPM_EVENT_PLE_FLUSH,
- * XPM_EVENT_PLE_CMPL }
- *
- * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL,
- * XPM_EVENT_PLE_PROG,
- * XPM_EVENT_PLE_LRC,
- * XPM_EVENT_PLE_LRS,
- * XPM_EVENT_PLE_FLUSH,
- * XPM_EVENT_PLE_CMPL }
- *
- * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL,
- * XPM_EVENT_INSRFETCH_CACHEREFILL,
- * XPM_EVENT_INSTRFECT_TLBREFILL,
- * XPM_EVENT_DATA_CACHEREFILL,
- * XPM_EVENT_DATA_CACHEACCESS,
- * XPM_EVENT_DATA_TLBREFILL }
- */
-#define XPM_CNTRCFG1 0
-#define XPM_CNTRCFG2 1
-#define XPM_CNTRCFG3 2
-#define XPM_CNTRCFG4 3
-#define XPM_CNTRCFG5 4
-#define XPM_CNTRCFG6 5
-#define XPM_CNTRCFG7 6
-#define XPM_CNTRCFG8 7
-#define XPM_CNTRCFG9 8
-#define XPM_CNTRCFG10 9
-#define XPM_CNTRCFG11 10
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/**
-*@endcond
-*/
-
-/************************** Function Prototypes *****************************/
-
-/* Interface functions to access performance counters from abstraction layer */
-void Xpm_SetEvents(s32 PmcrCfg);
-void Xpm_GetEventCounters(u32 *PmCtrValue);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-* @} End of "addtogroup a9_event_counter_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e0/80aa60595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e0/80aa60595243001d18b399c1eb9b3628
deleted file mode 100644
index 59db30b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e0/80aa60595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,47 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2008 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-* microblaze_flush_cache_ext()
-*
-* Flush the entire L2 Cache
-*
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-#include "microblaze_instructions.h"
-
-#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
-
-#define CACHEABLE_REGION_SIZE (XPAR_MICROBLAZE_DCACHE_HIGHADDR - XPAR_MICROBLAZE_DCACHE_BASEADDR)
-
-
- .text
- .globl microblaze_flush_cache_ext
- .ent microblaze_flush_cache_ext
- .align 2
-
-microblaze_flush_cache_ext:
-
-#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
- ADDIK r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_DCACHE_LINE_LEN))
-
- ADDIK r6, r0, CACHEABLE_REGION_SIZE-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
- ANDI r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
-
-Loop_start:
- wdc.ext.flush r5, r6
-#if defined (__arch64__)
- addlik r6, r6,-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
- beagei r6, Loop_start
-#else
- bgtid r6,Loop_start
- addik r6, r6,-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
-#endif
-#endif
- rtsd r15, 8
- nop
- .end microblaze_flush_cache_ext
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e0/a28de6575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e0/a28de6575243001d18b399c1eb9b3628
deleted file mode 100644
index 9d33a6c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e0/a28de6575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,193 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xgpio.h
-* @addtogroup gpio_v4_8
-* @{
-* @details
-*
-* This file contains the software API definition of the Xilinx General Purpose
-* I/O (XGpio) device driver.
-*
-* The Xilinx GPIO controller is a soft IP core designed for Xilinx FPGAs and
-* contains the following general features:
-* - Support for up to 32 I/O discretes for each channel (64 bits total).
-* - Each of the discretes can be configured for input or output.
-* - Configurable support for dual channels and interrupt generation.
-*
-* The driver provides interrupt management functions. Implementation of
-* interrupt handlers is left to the user. Refer to the provided interrupt
-* example in the examples directory for details.
-*
-* This driver is intended to be RTOS and processor independent. Any needs for
-* dynamic memory management, threads or thread mutual exclusion, virtual
-* memory, or cache control must be satisfied by the layer above this driver.
-*
-* Initialization & Configuration
-*
-* The XGpio_Config structure is used by the driver to configure itself. This
-* configuration structure is typically created by the tool-chain based on HW
-* build properties.
-*
-* To support multiple runtime loading and initialization strategies employed
-* by various operating systems, the driver instance can be initialized in one
-* of the following ways:
-*
-* - XGpio_Initialize(InstancePtr, DeviceId) - The driver looks up its own
-* configuration structure created by the tool-chain based on an ID provided
-* by the tool-chain.
-*
-* - XGpio_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-* configuration structure provided by the caller. If running in a system
-* with address translation, the provided virtual memory base address
-* replaces the physical address present in the configuration structure.
-*
-* @note
-*
-* This API utilizes 32 bit I/O to the GPIO registers. With less than 32 bits,
-* the unused bits from registers are read as zero and written as don't cares.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 03/13/02 First release
-* 2.00a jhl 11/26/03 Added support for dual channels and interrupts
-* 2.01a jvb 12/14/05 I separated dependency on the static config table and
-* xparameters.h from the driver initialization by moving
-* _Initialize and _LookupConfig to _sinit.c. I also added
-* the new _CfgInitialize routine.
-* 2.11a mta 03/21/07 Updated to new coding style, added GetDataDirection
-* 2.12a sv 11/21/07 Updated driver to support access through DCR bus
-* 2.12a sv 06/05/08 Updated driver to fix the XGpio_InterruptDisable function
-* to properly update the Interrupt Enable register
-* 2.13a sdm 08/22/08 Removed support for static interrupt handlers from the MDD
-* file
-* 3.00a sv 11/21/09 Updated to use HAL Processor APIs.
-* Renamed the macros XGpio_mWriteReg to XGpio_WriteReg and
-* XGpio_mReadReg to XGpio_ReadReg. Removed the macros
-* XGpio_mSetDataDirection, XGpio_mGetDataReg and
-* XGpio_mSetDataReg. Users should use XGpio_WriteReg and
-* XGpio_ReadReg to achieve the same functionality.
-* 3.01a bss 04/18/13 Updated driver tcl to generate Canonical params in
-* xparameters.h. CR#698589
-* 4.0 adk 19/12/13 Updated as per the New Tcl API's
-* 4.1 lks 11/18/15 Updated to use canonical xparameters in examples and
-* clean up of the comments, removed support for DCR bridge
-* and removed xgpio_intr_example for CR 900381
-* 4.2 sk 08/16/16 Used UINTPTR instead of u32 for Baseaddress as part of
-* adding 64 bit support. CR# 867425.
-* Changed the prototype of XGpio_CfgInitialize API.
-* 4.3 sk 09/29/16 Modified the example to make it work when LED_bits are
-* configured as an output. CR# 958644
-* ms 01/23/17 Added xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* 4.4 sne 04/25/19 Updated Makefile for IAR compier (CR-1029421).
-* 4.5 sne 06/14/19 Fixed IAR compiler warnings on example files.
-* 4.6 sne 08/11/19 Fixed compilation error of armcc compiler.
-* 4.7 sne 08/28/20 Modify Makefile to support parallel make execution.
-* 4.8 sne 02/10/21 Fixed doxygen warnings.
-*
-*
-*****************************************************************************/
-
-#ifndef XGPIO_H /* prevent circular inclusions */
-#define XGPIO_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xgpio_l.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- UINTPTR BaseAddress; /**< Device base address */
- int InterruptPresent; /**< Are interrupts supported in h/w */
- int IsDual; /**< Are 2 channels supported in h/w */
-} XGpio_Config;
-
-/**
- * The XGpio driver instance data. The user is required to allocate a
- * variable of this type for every GPIO device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- UINTPTR BaseAddress; /**< Device base address */
- u32 IsReady; /**< Device is initialized and ready */
- int InterruptPresent; /**< Are interrupts supported in h/w */
- int IsDual; /**< Are 2 channels supported in h/w */
-} XGpio;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Function Prototypes *****************************/
-
-/*
- * Initialization functions in xgpio_sinit.c
- */
-int XGpio_Initialize(XGpio *InstancePtr, u16 DeviceId);
-XGpio_Config *XGpio_LookupConfig(u16 DeviceId);
-
-/*
- * API Basic functions implemented in xgpio.c
- */
-int XGpio_CfgInitialize(XGpio *InstancePtr, XGpio_Config * Config,
- UINTPTR EffectiveAddr);
-void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
- u32 DirectionMask);
-u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel);
-u32 XGpio_DiscreteRead(XGpio *InstancePtr, unsigned Channel);
-void XGpio_DiscreteWrite(XGpio *InstancePtr, unsigned Channel, u32 Mask);
-
-
-/*
- * API Functions implemented in xgpio_extra.c
- */
-void XGpio_DiscreteSet(XGpio *InstancePtr, unsigned Channel, u32 Mask);
-void XGpio_DiscreteClear(XGpio *InstancePtr, unsigned Channel, u32 Mask);
-
-/*
- * API Functions implemented in xgpio_selftest.c
- */
-int XGpio_SelfTest(XGpio *InstancePtr);
-
-/*
- * API Functions implemented in xgpio_intr.c
- */
-void XGpio_InterruptGlobalEnable(XGpio *InstancePtr);
-void XGpio_InterruptGlobalDisable(XGpio *InstancePtr);
-void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask);
-void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask);
-void XGpio_InterruptClear(XGpio *InstancePtr, u32 Mask);
-u32 XGpio_InterruptGetEnabled(XGpio *InstancePtr);
-u32 XGpio_InterruptGetStatus(XGpio *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e0/d097dd585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e0/d097dd585243001d18b399c1eb9b3628
deleted file mode 100644
index e5a1efd..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e0/d097dd585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,122 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm_rvct.c
-*
-* This header file contains functions for using assembler code. It is
-* written specifically for RVCT.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 11/18/09 First Release
-* 7.2 asa 04/04/20 Renamed the str macro to strw.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xpseudo_asm_rvct.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-/* embedded assembler instructions */
-__asm void cpsiei(void)
-{
- cpsie i
- bx lr
-}
-__asm void cpsidi(void)
-{
- cpsid i
- bx lr
-}
-
-__asm void cpsief(void)
-{
- cpsie f
- bx lr
-}
-
-__asm void cpsidf(void)
-{
- cpsid f
- bx lr
-}
-
-/* memory synchronization operations */
-
-/* Instruction Synchronization Barrier */
-__asm void isb(void)
-{
- isb
- bx lr
-}
-
-/* Data Synchronization Barrier */
-__asm void dsb(void)
-{
- dsb
- bx lr
-}
-
-/* Data Memory Barrier */
-__asm void dmb(void)
-{
- dmb
- bx lr
-}
-
-/* Memory Operations */
-__asm u32 ldr(u32 adr)
-{
- ldr r0, [r0]
- bx lr
-}
-
-__asm u32 ldrb(u32 adr)
-{
- ldrb r0, [r0]
- bx lr
-}
-
-__asm void strw(u32 adr, u32 val)
-{
- str r1, [r0]
- bx lr
-}
-
-__asm void strb(u32 adr, u32 val)
-{
- strb r1, [r0]
- bx lr
-}
-
-/* Count leading zeroes (clz) */
-__asm u32 clz(u32 arg)
-{
- clz r0, r0
- bx lr
-}
-
-__asm u32 mfcpsr(void)
-{
- mrs r0, cpsr
- bx lr
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e1/31f29c525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e1/31f29c525243001d18b399c1eb9b3628
deleted file mode 100644
index b733141..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e1/31f29c525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,215 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xemacps_bdring.h
-* @addtogroup emacps_v3_15
-* @{
-*
-* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
-* DMA functionalities.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a wsy 01/10/10 First release
-* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
-* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
-* changed to volatile.
-*
-*
-*
-******************************************************************************/
-
-#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */
-#define XEMACPS_BDRING_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/**************************** Type Definitions *******************************/
-
-/** This is an internal structure used to maintain the DMA list */
-typedef struct {
- UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
- UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */
- UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */
- u32 Length; /**< Total size of ring in bytes */
- u32 RunState; /**< Flag to indicate DMA is started */
- u32 Separation; /**< Number of bytes between the starting address
- of adjacent BDs */
- XEmacPs_Bd *FreeHead;
- /**< First BD in the free group */
- XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
- XEmacPs_Bd *HwHead; /**< First BD in the work group */
- XEmacPs_Bd *HwTail; /**< Last BD in the work group */
- XEmacPs_Bd *PostHead;
- /**< First BD in the post-work group */
- XEmacPs_Bd *BdaRestart;
- /**< BDA to load when channel is started */
-
- volatile u32 HwCnt; /**< Number of BDs in work group */
- u32 PreCnt; /**< Number of BDs in pre-work group */
- u32 FreeCnt; /**< Number of allocatable BDs in the free group */
- u32 PostCnt; /**< Number of BDs in post-work group */
- u32 AllCnt; /**< Total Number of BDs for channel */
-} XEmacPs_BdRing;
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
-* Use this macro at initialization time to determine how many BDs will fit
-* in a BD list within the given memory constraints.
-*
-* The results of this macro can be provided to XEmacPs_BdRingCreate().
-*
-* @param Alignment specifies what byte alignment the BDs must fall on and
-* must be a power of 2 to get an accurate calculation (32, 64, 128,...)
-* @param Bytes is the number of bytes to be used to store BDs.
-*
-* @return Number of BDs that can fit in the given memory area
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
-*
-******************************************************************************/
-#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \
- (u32)((Bytes) / (sizeof(XEmacPs_Bd)))
-
-/*****************************************************************************/
-/**
-* Use this macro at initialization time to determine how many bytes of memory
-* is required to contain a given number of BDs at a given alignment.
-*
-* @param Alignment specifies what byte alignment the BDs must fall on. This
-* parameter must be a power of 2 to get an accurate calculation (32, 64,
-* 128,...)
-* @param NumBd is the number of BDs to calculate memory size requirements for
-*
-* @return The number of bytes of memory required to create a BD list with the
-* given memory constraints.
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
-*
-******************************************************************************/
-#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \
- (u32)(sizeof(XEmacPs_Bd) * (NumBd))
-
-/****************************************************************************/
-/**
-* Return the total number of BDs allocated by this channel with
-* XEmacPs_BdRingCreate().
-*
-* @param RingPtr is the DMA channel to operate on.
-*
-* @return The total number of BDs allocated for this channel.
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
-
-/****************************************************************************/
-/**
-* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
-* processing.
-*
-* @param RingPtr is the DMA channel to operate on.
-*
-* @return The number of BDs currently allocatable.
-*
-* @note
-* C-style signature:
-* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt)
-
-/****************************************************************************/
-/**
-* Return the next BD from BdPtr in a list.
-*
-* @param RingPtr is the DMA channel to operate on.
-* @param BdPtr is the BD to operate on.
-*
-* @return The next BD in the list relative to the BdPtr parameter.
-*
-* @note
-* C-style signature:
-* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
-* XEmacPs_Bd *BdPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingNext(RingPtr, BdPtr) \
- (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ? \
- (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) : \
- (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
-
-/****************************************************************************/
-/**
-* Return the previous BD from BdPtr in the list.
-*
-* @param RingPtr is the DMA channel to operate on.
-* @param BdPtr is the BD to operate on
-*
-* @return The previous BD in the list relative to the BdPtr parameter.
-*
-* @note
-* C-style signature:
-* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
-* XEmacPs_Bd *BdPtr)
-*
-*****************************************************************************/
-#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \
- (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \
- (XEmacPs_Bd*)(RingPtr)->HighBdAddr : \
- (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Scatter gather DMA related functions in xemacps_bdring.c
- */
-LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
- UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
-LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
- u8 Direction);
-LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd ** BdSetPtr);
-LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr);
-LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr);
-LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
- XEmacPs_Bd * BdSetPtr);
-u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
- XEmacPs_Bd ** BdSetPtr);
-u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
- XEmacPs_Bd ** BdSetPtr);
-LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
-
-void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* end of protection macros */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e1/6094b0585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e1/6094b0585243001d18b399c1eb9b3628
deleted file mode 100644
index 00b233a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e1/6094b0585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,20 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include "xil_types.h"
-
-/*
- * fcntl -- Manipulate a file descriptor.
- * We don't have a filesystem, so we do nothing.
- */
-__attribute__((weak)) sint32 fcntl (sint32 fd, sint32 cmd, long arg)
-{
- (void)fd;
- (void)cmd;
- (void)arg;
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e1/7091c3565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e1/7091c3565243001d18b399c1eb9b3628
deleted file mode 100644
index 4e3a872..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e1/7091c3565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,145 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include "profile.h"
-#include "_profile_timer_hw.h"
-#ifdef PROC_MICROBLAZE
-#include "mblaze_nt_types.h"
-#endif
-
-/*
- * The mcount function is excluded from the library, if the user defines
- * PROFILE_NO_GRAPH.
- */
-#ifndef PROFILE_NO_GRAPH
-
-#include
-#include
-#include
-
-#ifdef PROFILE_NO_FUNCPTR
-s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc );
-#else
-s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc );
-#endif
-
-/*extern struct gmonparam *_gmonparam, */
-
-#ifdef PROFILE_NO_FUNCPTR
-s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc )
-{
- s32 index = 0 ;
-
- while( (index < cgtable_size) && (cgtable[index].frompc != frompc) ){
- index++ ;
- }
- if( index == cgtable_size ) {
- return -1 ;
- } else {
- return index ;
- }
-}
-#else
-s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc )
-{
- s32 index = 0 ;
- s32 Status;
-
- while( (index < fromssize) && (froms[index].frompc != frompc) ){
- index++ ;
- }
- if( index == fromssize ) {
- Status = -1 ;
- } else {
- Status = index ;
- }
- return Status;
-}
-#endif /* PROFILE_NO_FUNCPTR */
-
-
-void mcount( u32 frompc, u32 selfpc )
-{
- register struct gmonparam *p = NULL;
- register s32 toindex, fromindex;
- s32 j;
-
- disable_timer();
-
- /*print("CG: "), putnum(frompc), print("->"), putnum(selfpc), print("\r\n") ,
- * check that frompcindex is a reasonable pc value.
- * for example: signal catchers get called from the stack,
- * not from text space. too bad.
- */
- for(j = 0; j < n_gmon_sections; j++ ){
- if((frompc >= _gmonparam[j].lowpc) && (frompc < _gmonparam[j].highpc)) {
- p = &_gmonparam[j];
- break;
- }
- }
- if( j == n_gmon_sections ) {
- goto done;
- }
-
-#ifdef PROFILE_NO_FUNCPTR
- fromindex = searchpc( p->cgtable, p->cgtable_size, frompc ) ;
- if( fromindex == -1 ) {
- fromindex = p->cgtable_size ;
- p->cgtable_size++ ;
- p->cgtable[fromindex].frompc = frompc ;
- p->cgtable[fromindex].selfpc = selfpc ;
- p->cgtable[fromindex].count = 1 ;
- goto done ;
- }
- p->cgtable[fromindex].count++ ;
-#else
- fromindex = (s32)searchpc( p->froms, ((s32)p->fromssize), frompc ) ;
- if( fromindex == -1 ) {
- fromindex = (s32)p->fromssize ;
- p->fromssize++ ;
- /*if( fromindex >= N_FROMS ) {
- * print("Error : From PC table overflow\r\n")
- * goto overflow
- *}*/
- p->froms[fromindex].frompc = frompc ;
- p->froms[fromindex].link = -1 ;
- }else {
- toindex = ((s32)(p->froms[fromindex].link));
- while(toindex != -1) {
- toindex = (((s32)p->tossize) - toindex)-1 ;
- if( p->tos[toindex].selfpc == selfpc ) {
- p->tos[toindex].count++ ;
- goto done ;
- }
- toindex = ((s32)(p->tos[toindex].link)) ;
- }
- }
-
- /*if( toindex == -1 ) { */
- p->tos-- ;
- p->tossize++ ;
- /* if( toindex >= N_TOS ) {
- * print("Error : To PC table overflow\r\n")
- * goto overflow
- *} */
- p->tos[0].selfpc = selfpc ;
- p->tos[0].count = 1 ;
- p->tos[0].link = p->froms[fromindex].link ;
- p->froms[fromindex].link = ((s32)(p->tossize))-((s32)1);
-#endif
-
- done:
- p->state = GMON_PROF_ON;
- goto enable_timer_label ;
- /* overflow: */
- /*p->state = GMON_PROF_ERROR */
- enable_timer_label:
- enable_timer();
- return ;
-}
-
-
-#endif /* PROFILE_NO_GRAPH */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e1/818a30545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e1/818a30545243001d18b399c1eb9b3628
deleted file mode 100644
index 33b33eb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e1/818a30545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,167 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xgpio_l.h
-* @addtogroup gpio_v4_8
-* @{
-*
-* This header file contains identifiers and driver functions (or
-* macros) that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-*
-* The macros that are available in this file use a multiply to calculate the
-* addresses of registers. The user can control whether that multiply is done
-* at run time or at compile time. A constant passed as the channel parameter
-* will cause the multiply to be done at compile time. A variable passed as the
-* channel parameter will cause it to occur at run time.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a jhl 04/24/02 First release of low level driver
-* 2.00a jhl 11/26/03 Added support for dual channels and interrupts. This
-* change required the functions to be changed such that
-* the interface is not compatible with previous versions.
-* See the examples in the example directory for macros
-* to help compile an application that was designed for
-* previous versions of the driver. The interrupt registers
-* are accessible using the ReadReg and WriteReg macros and
-* a channel parameter was added to the other macros.
-* 2.11a mta 03/21/07 Updated to new coding style
-* 2.12a sv 11/21/07 Updated driver to support access through DCR bus.
-* 3.00a sv 11/21/09 Renamed the macros XGpio_mWriteReg to XGpio_WriteReg
-* XGpio_mReadReg to XGpio_ReadReg.
-* Removed the macros XGpio_mSetDataDirection,
-* XGpio_mGetDataReg and XGpio_mSetDataReg. Users
-* should use XGpio_WriteReg/XGpio_ReadReg to achieve the
-* same functionality.
-* 4.1 lks 11/18/15 Removed support for DCR bridge
-*
-*
-******************************************************************************/
-
-#ifndef XGPIO_L_H /* prevent circular inclusions */
-#define XGPIO_L_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-
-/************************** Constant Definitions *****************************/
-
-/** @name Registers
- *
- * Register offsets for this device.
- * @{
- */
-#define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */
-#define XGPIO_TRI_OFFSET 0x4 /**< I/O direction reg for 1st channel */
-#define XGPIO_DATA2_OFFSET 0x8 /**< Data register for 2nd channel */
-#define XGPIO_TRI2_OFFSET 0xC /**< I/O direction reg for 2nd channel */
-
-#define XGPIO_GIE_OFFSET 0x11C /**< Glogal interrupt enable register */
-#define XGPIO_ISR_OFFSET 0x120 /**< Interrupt status register */
-#define XGPIO_IER_OFFSET 0x128 /**< Interrupt enable register */
-
-/** @} */
-
-/* The following constant describes the offset of each channels data and
- * tristate register from the base address.
- */
-#define XGPIO_CHAN_OFFSET 8 /**< Channel offeset */
-
-/** @name Interrupt Status and Enable Register bitmaps and masks
- *
- * Bit definitions for the interrupt status register and interrupt enable
- * registers.
- * @{
- */
-#define XGPIO_IR_MASK 0x3 /**< Mask of all bits */
-#define XGPIO_IR_CH1_MASK 0x1 /**< Mask for the 1st channel */
-#define XGPIO_IR_CH2_MASK 0x2 /**< Mask for the 2nd channel */
-/** @}*/
-
-
-/** @name Global Interrupt Enable Register bitmaps and masks
- *
- * Bit definitions for the Global Interrupt Enable register
- * @{
- */
-#define XGPIO_GIE_GINTR_ENABLE_MASK 0x80000000 /**< Mask for Global Interrupt */
-/** @}*/
-
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XGpio_In32 Xil_In32 /**< Input Operations */
-#define XGpio_Out32 Xil_Out32 /**< Output Operations */
-
-
-/****************************************************************************/
-/**
-*
-* Write a value to a GPIO register. A 32 bit write is performed. If the
-* GPIO core is implemented in a smaller width, only the least significant data
-* is written.
-*
-* @param BaseAddress is the base address of the GPIO device.
-* @param RegOffset is the register offset from the base to write to.
-* @param Data is the data written to the register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XGpio_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
-****************************************************************************/
-#define XGpio_WriteReg(BaseAddress, RegOffset, Data) \
- XGpio_Out32((BaseAddress) + (RegOffset), (u32)(Data))
-
-/****************************************************************************/
-/**
-*
-* Read a value from a GPIO register. A 32 bit read is performed. If the
-* GPIO core is implemented in a smaller width, only the least
-* significant data is read from the register. The most significant data
-* will be read as 0.
-*
-* @param BaseAddress is the base address of the GPIO device.
-* @param RegOffset is the register offset from the base to read from.
-*
-* @return Data read from the register.
-*
-* @note C-style signature:
-* u32 XGpio_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-****************************************************************************/
-#define XGpio_ReadReg(BaseAddress, RegOffset) \
- XGpio_In32((BaseAddress) + (RegOffset))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e1/b08a6a585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e1/b08a6a585243001d18b399c1eb9b3628
deleted file mode 100644
index b878d05..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e1/b08a6a585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,75 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.h
-*
-* @addtogroup a53_64_cache_apis Cortex A53 64bit Processor Cache Functions
-*
-* Cache functions provide access to cache related operations such as flush
-* and invalidate for instruction and data caches. It gives option to perform
-* the cache operations on a single cacheline, a range of memory and an entire
-* cache.
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.00 pkp 05/29/14 First release
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00 hbm 07/28/09 Initial release
-* 6.2 ms 02/20/17 Fixed compilation warning. This is a fix for CR-969126.
-*
-*
-*
-******************************************************************************/
-
-#include "xil_types.h"
-#include "xil_exception.h"
-
-#include "microblaze_exceptions_g.h"
-#include "microblaze_interrupts_i.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *@cond nocomments
- */
-extern void microblaze_enable_exceptions(void);
-extern void microblaze_disable_exceptions(void);
-extern void microblaze_enable_interrupts(void);
-extern void microblaze_disable_interrupts(void);
-
-/**
-* Currently HAL is an augmented part of standalone BSP, so the old definition
-* of MB_ExceptionVectorTableEntry is used here.
-*/
-
-typedef struct {
- Xil_ExceptionHandler Handler;
- void *CallBackRef;
-} MB_ExceptionVectorTableEntry;
-
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * @endcond
- */
-
-/************************** Variable Definitions *****************************/
-extern MB_ExceptionVectorTableEntry MB_ExceptionVectorTable[XIL_EXCEPTION_ID_INT];
-extern MB_InterruptVectorTableEntry MB_InterruptVectorTable[MB_INTERRUPT_VECTOR_TABLE_ENTRIES];
-
-/****************************************************************************/
-/**
- * @brief This function is a stub handler that is the default handler that gets
- * called if the application has not setup a handler for a specific
- * exception. The function interface has to match the interface
- * specified for a handler even though none of the arguments are used.
- *
- * @param Data: unused by this function.
- *
- *****************************************************************************/
-static void Xil_ExceptionNullHandler(void *Data)
-{
- (void) Data;
-}
-
-/****************************************************************************/
-/**
-* @brief Initialize exception handling for the processor. The exception
-* vector table is setup with the stub handler for all exceptions.
-*
-*****************************************************************************/
-void Xil_ExceptionInit(void)
-{
- /*
- * there is no need to setup the exception table here
- */
-
-}
-
-/****************************************************************************/
-/**
-* @brief Enable Exceptions.
-*
-******************************************************************************/
-void Xil_ExceptionEnable(void)
-{
-#ifdef MICROBLAZE_EXCEPTIONS_ENABLED
- microblaze_enable_exceptions();
-#endif
- microblaze_enable_interrupts();
-}
-
-/****************************************************************************/
-/**
-* @brief Disable Exceptions.
-*
-******************************************************************************/
-void Xil_ExceptionDisable(void)
-{
-#ifdef MICROBLAZE_EXCEPTIONS_ENABLED
- microblaze_disable_exceptions();
-#endif
- microblaze_disable_interrupts();
-}
-
-/*****************************************************************************/
-/**
-*@brief Makes the connection between the Id of the exception source and the
-* associated handler that is to run when the exception is recognized.
-* The argument provided in this call as the DataPtr is used as the
-* argument for the handler when it is called.
-*
-* @param Id: contains the 32 bit ID of the exception source and should
-* be XIL_EXCEPTION_INT or be in the range of 0 to XIL_EXCEPTION_LAST.
-* See xil_mach_exception.h for further information.
-* @param Handler: handler function to be registered for exception
-* @param Data: a reference to data that will be passed to the handler
-* when it gets called.
-*
-****************************************************************************/
-void Xil_ExceptionRegisterHandler(u32 Id, Xil_ExceptionHandler Handler,
- void *Data)
-{
- if (Id == XIL_EXCEPTION_ID_INT) {
- MB_InterruptVectorTable[0].Handler = Handler;
- MB_InterruptVectorTable[0].CallBackRef = Data;
- }
- else {
-#ifdef MICROBLAZE_EXCEPTIONS_ENABLED
- MB_ExceptionVectorTable[Id].Handler = Handler;
- MB_ExceptionVectorTable[Id].CallBackRef = Data;
-#endif
- }
-}
-
-
-/*****************************************************************************/
-/**
-* @brief Removes the handler for a specific exception Id. The stub handler
-* is then registered for this exception Id.
-*
-* @param Id: contains the 32 bit ID of the exception source and should
-* be XIL_EXCEPTION_INT or in the range of 0 to XIL_EXCEPTION_LAST.
-* See xexception_l.h for further information.
-*
-****************************************************************************/
-void Xil_ExceptionRemoveHandler(u32 Id)
-{
- if (Id == XIL_EXCEPTION_ID_INT) {
- MB_InterruptVectorTable[0].Handler = Xil_ExceptionNullHandler;
- MB_InterruptVectorTable[0].CallBackRef = NULL;
- }
- else {
-
-#ifdef MICROBLAZE_EXCEPTIONS_ENABLED
- MB_ExceptionVectorTable[Id].Handler =
- Xil_ExceptionNullHandler;
- MB_ExceptionVectorTable[Id].CallBackRef = NULL;
-#endif
- }
-}
-/**
-* @} End of "addtogroup microblaze_exception_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e3/00fe36555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e3/00fe36555243001d18b399c1eb9b3628
deleted file mode 100644
index c4789b8..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e3/00fe36555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,316 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2018 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xparameters_ps.h
-*
-* This file contains the address definitions for the hard peripherals
-* attached to the ARM Cortex A72 core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 7.00 mus 01/11/18 First release
-* mn 03/26/18 Change Interrupt IDs for versal
-* mn 03/26/18 Update SLCR base address
-* ap 02/14/19 Add Interrupt Id for usbpsu controller
-* sne 03/26/20 Add Interrupt Id's for WWDT.
-* 7.2 pm 03/24/20 Add wakeup Interrupt Id for usbpsu controller
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.0 hk 27/01/14 First release
-* 1.4 vns 07/06/17 Added dooxygen tags.
-*
-*
-*
-* @note
-*
-******************************************************************************/
-#ifndef ___XIL_RSA_H___
-#define ___XIL_RSA_H___
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/***************************** Include Files *********************************/
-
-/*
- * Digit size selection (32 or 16-bit). If supported by the CPU/compiler,
- * 32-bit digits are approximately 4 times faster
- */
-
-//#define RSA_DIGIT_16
-#define RSA_DIGIT_32
-
-/*
- * RSA loop unrolling selection
- * RSA main loop can be unrolled 2, 4 or 8 ways
- */
-#define RSA_UNROLL 1
-
-/*
- * Select if ARM-optimized code is to be used. Only GCC for ARM is supported
- */
-//#define RSA_ARM_OPTIMIZED
-
-/*
- * Check the compatibility of the selection
- */
-#if defined(RSA_DIGIT_16) && defined(RSA_DIGIT_32)
- #error Please select a digit size
-#endif
-#if !defined(RSA_DIGIT_16) && !defined(RSA_DIGIT_32)
- #error Please select just one digit size
-#endif
-#if (!defined(__GNUC__) || !defined(__arm__)) && defined(RSA_ARM_OPTIMIZED)
- #error Assembly level code is only supported for the GCC/ARM combination
-#endif
-#if (RSA_UNROLL != 1) && (RSA_UNROLL != 2) && (RSA_UNROLL != 4) && (RSA_UNROLL != 8)
- #error Only 1, 2, 4, and 8 unrolling are supported
-#endif
-
-#ifdef RSA_DIGIT_16
-#define RSA_DIGIT unsigned short
-#define RSA_SDIGIT short
-#define RSA_DDIGIT unsigned long
-#endif
-#ifdef RSA_DIGIT_32
-#define RSA_DIGIT unsigned long
-#define RSA_SDIGIT long
-#define RSA_DDIGIT unsigned long long
-#endif
-
-#define RSA_NUMBER RSA_DIGIT *
-#define RSA_NBITS 2048
-#define RSA_NDIGITS (RSA_NBITS/(sizeof(RSA_DIGIT)*8))
-#define RSA_NBYTES (RSA_NDIGITS*sizeof(RSA_DIGIT))
-
-/*
- * Double-digit to single digit conversion
- */
-#define RSA_MSB(x) (x >> (sizeof(RSA_DIGIT)*8))
-#define RSA_LSB(x) (x & (RSA_DIGIT)~0)
-
-#define SHA_BLKSIZE 512
-#define SHA_BLKBYTES (SHA_BLKSIZE/8)
-#define SHA_BLKWORDS (SHA_BLKBYTES/4)
-
-#define SHA_VALSIZE 256
-#define SHA_VALBYTES (SHA_VALSIZE/8)
-#define SHA_VALWORDS (SHA_VALBYTES/4)
-
-/*
- * SHA-256 context structure
- * Includes SHA-256 state, coalescing buffer to collect the processed strings, and
- * total byte length counter (used both to manage the buffer and for padding)
- */
- //! [sha2_context]
-typedef struct
-{
- unsigned int state[8];
- unsigned char buffer[SHA_BLKBYTES];
- unsigned long long bytes;
-} sha2_context;
-//! [sha2_context]
-/** @}
-@endcond */
-
-/*
- * RSA-2048 user interfaces
- */
-/*****************************************************************************/
-/**
- * @brief
- * This function is used to encrypt the data using 2048 bit private key.
- *
- * @param modular A char pointer which contains the key modulus
- * @param modular_ext A char pointer which contains the key modulus
- * extension
- * @param exponent A char pointer which contains the private key
- * exponent
- * @param result A char pointer which contains the encrypted data
- *
- * @return None
- *
- ******************************************************************************/
-void rsa2048_exp(const unsigned char *base, const unsigned char * modular,
- const unsigned char *modular_ext, const unsigned char *exponent,
- unsigned char *result);
-/*****************************************************************************/
-/**
- * @brief
- * This function is used to decrypt the data using 2048 bit public key
- *
- * @param a RSA_NUMBER containing the decrypted data.
- * @param x RSA_NUMBER containing the input data
- * @param e Unsigned number containing the public key exponent
- * @param m RSA_NUMBER containing the public key modulus
- * @param rrm RSA_NUMBER containing the public key modulus extension.
- *
- * @return None
- *
- ******************************************************************************/
-void rsa2048_pubexp(RSA_NUMBER a, RSA_NUMBER x,
- unsigned long e, RSA_NUMBER m, RSA_NUMBER rrm);
-
-/*
- * SHA-256 user interfaces
- */
-/*****************************************************************************/
-/**
- * @brief
- * This function calculates the hash for the input data using SHA-256
- * algorithm. This function internally calls the sha2_init, updates and
- * finishes functions and updates the result.
- *
- * @param In Char pointer which contains the input data.
- * @param Size Length of the input data
- * @param Out Pointer to location where resulting hash will be
- * written.
- *
- * @return None
- *
- ******************************************************************************/
-void sha_256(const unsigned char *in, const unsigned int size, unsigned char *out);
-/*****************************************************************************/
-/**
- * @brief
- * This function initializes the SHA2 context.
- *
- * @param ctx Pointer to sha2_context structure that stores status and
- * buffer.
- *
- * @return None
- *
- ******************************************************************************/
-void sha2_starts(sha2_context *ctx);
-/*****************************************************************************/
-/**
- * @brief
- * This function adds the input data to SHA256 calculation.
- *
- * @param ctx Pointer to sha2_context structure that stores status and
- * buffer.
- * @param input Pointer to the data to add.
- * @param Out Length of the input data.
- *
- * @return None
- *
- ******************************************************************************/
-void sha2_update(sha2_context *ctx, unsigned char* input, unsigned int ilen);
-/*****************************************************************************/
-/**
- * @brief
- * This function finishes the SHA calculation.
- *
- * @param ctx Pointer to sha2_context structure that stores status and
- * buffer.
- * @param output Pointer to the calculated hash data.
- *
- * @return None
- *
- *
- ******************************************************************************/
-void sha2_finish(sha2_context *ctx, unsigned char* output);
-
-/*
- * Preprocessing interface (pre-computation of R*R mod M)
- */
-/**@cond xilrsa_internal */
-void modular_ext(const unsigned char *modular, unsigned char *res);
-/** @}
-@endcond */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ___XIL_RSA_H___ */
-/** @} */
-
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e3/402844565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e3/402844565243001d18b399c1eb9b3628
deleted file mode 100644
index fd80a0d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e3/402844565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,62 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_clocking.h
-*
-* The xil_clocking.h file contains clocking related functions and macros.
-* certain conditions.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 7.2 sd 12/11/19 First release
-* 7.2 sd 03/20/20 Added checking for isolation case
-*
-*
-******************************************************************************/
-
-#ifndef XIL_CLOCKING_H /* prevent circular inclusions */
-#define XIL_CLOCKING_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xdebug.h"
-#include "xil_printf.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xparameters.h"
-#include "xstatus.h"
-#if defined (XPAR_XCRPSU_0_DEVICE_ID)
-#include "xclockps.h"
-#else
-typedef u32 XClock_OutputClks;
-typedef u64 XClockRate;
-#endif
-
-/***************************** Include Files *********************************/
-
-
-/************************** Constant Definitions *****************************/
-
-
-XStatus Xil_ClockDisable(XClock_OutputClks ClockId);
-XStatus Xil_ClockEnable(XClock_OutputClks ClockId);
-XStatus Xil_ClockInit(void);
-XStatus Xil_ClockGet(void);
-XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate, XClockRate *SetRate);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e3/b2b548595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e3/b2b548595243001d18b399c1eb9b3628
deleted file mode 100644
index 48dcec3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e3/b2b548595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,53 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file cpu_init.S
-*
-* This file contains CPU specific initialization. Invoked from main CRT
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 1.00a ecm/sdm 10/20/09 Initial version
-* 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
-* 5.0 pkp 12/16/14 removed incorrect initialization of TLB lockdown
-* register to fix CR#830580
-*
-* - API to Enable Interrupts: void microblaze_enable_interrupts(void)
-*
-* This API Enables interrupts on the MicroBlaze processor. When the MicroBlaze
-* processor starts up, interrupts are disabled. Interrupts must be explicitly
-* turned on using this function.
-*
-*
-*
-* File : microblaze_enable_interrupts.s
-* Date : 2002, March 20.
-* Company: Xilinx
-* Group : Emerging Software Technologies
-*
-* Summary:
-* Enable interrupts on the microblaze.
-*
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.00a wgr 10/10/10 First release
- * 1.04a nm 10/23/12 Fixed CR# 679106.
- * 1.05a kpc 07/03/13 Added XUsbPs_ResetHw function prototype
- * 2.00a kpc 04/03/14 Fixed CR#777764. Corrected max endpoint vale and masks
- * 2.5 pm 02/20/20 Added Endpoint Control Register bit positions for Rx & Tx
- *
- *
- ******************************************************************************/
-#ifndef XUSBPS_HW_H
-#define XUSBPS_HW_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-
-#define XUSBPS_REG_SPACING 4
-
-/** @name Timer 0 Register offsets
- *
- * @{
- */
-#define XUSBPS_TIMER0_LD_OFFSET 0x00000080
-#define XUSBPS_TIMER0_CTL_OFFSET 0x00000084
-/* @} */
-
-/** @name Timer Control Register bit mask
- *
- * @{
- */
-#define XUSBPS_TIMER_RUN_MASK 0x80000000
-#define XUSBPS_TIMER_STOP_MASK 0x80000000
-#define XUSBPS_TIMER_RESET_MASK 0x40000000
-#define XUSBPS_TIMER_REPEAT_MASK 0x01000000
-/* @} */
-
-/** @name Timer Control Register bit mask
- *
- * @{
- */
-#define XUSBPS_TIMER_COUNTER_MASK 0x00FFFFFF
-/* @} */
-
-/** @name Device Hardware Parameters
- *
- * @{
- */
-#define XUSBPS_HWDEVICE_OFFSET 0x0000000C
-
-#define XUSBPS_EP_NUM_MASK 0x3E
-#define XUSBPS_EP_NUM_SHIFT 1
-/* @} */
-
-/** @name Capability Register offsets
- */
-#define XUSBPS_HCSPARAMS_OFFSET 0x00000104
-
-/** @name Operational Register offsets.
- * Register comments are tagged with "H:" and "D:" for Host and Device modes,
- * respectively.
- * Tags are only present for registers that have a different meaning DEVICE and
- * HOST modes. Most registers are only valid for either DEVICE or HOST mode.
- * Those registers don't have tags.
- * @{
- */
-#define XUSBPS_CMD_OFFSET 0x00000140 /**< Configuration */
-#define XUSBPS_ISR_OFFSET 0x00000144 /**< Interrupt Status */
-#define XUSBPS_IER_OFFSET 0x00000148 /**< Interrupt Enable */
-#define XUSBPS_FRAME_OFFSET 0x0000014C /**< USB Frame Index */
-#define XUSBPS_LISTBASE_OFFSET 0x00000154 /**< H: Periodic List Base Address */
-#define XUSBPS_DEVICEADDR_OFFSET 0x00000154 /**< D: Device Address */
-#define XUSBPS_ASYNCLISTADDR_OFFSET 0x00000158 /**< H: Async List Address */
-#define XUSBPS_EPLISTADDR_OFFSET 0x00000158 /**< D: Endpoint List Addr */
-#define XUSBPS_TTCTRL_OFFSET 0x0000015C /**< TT Control */
-#define XUSBPS_BURSTSIZE_OFFSET 0x00000160 /**< Burst Size */
-#define XUSBPS_TXFILL_OFFSET 0x00000164 /**< Tx Fill Tuning */
-#define XUSBPS_ULPIVIEW_OFFSET 0x00000170 /**< ULPI Viewport */
-#define XUSBPS_EPNAKISR_OFFSET 0x00000178 /**< Endpoint NAK IRQ Status */
-#define XUSBPS_EPNAKIER_OFFSET 0x0000017C /**< Endpoint NAK IRQ Enable */
-#define XUSBPS_PORTSCR1_OFFSET 0x00000184 /**< Port Control/Status 1 */
-
-/* NOTE: The Port Control / Status Register index is 1-based. */
-#define XUSBPS_PORTSCRn_OFFSET(n) \
- (XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING))
-
-
-#define XUSBPS_OTGCSR_OFFSET 0x000001A4 /**< OTG Status and Control */
-#define XUSBPS_MODE_OFFSET 0x000001A8 /**< USB Mode */
-#define XUSBPS_EPSTAT_OFFSET 0x000001AC /**< Endpoint Setup Status */
-#define XUSBPS_EPPRIME_OFFSET 0x000001B0 /**< Endpoint Prime */
-#define XUSBPS_EPFLUSH_OFFSET 0x000001B4 /**< Endpoint Flush */
-#define XUSBPS_EPRDY_OFFSET 0x000001B8 /**< Endpoint Ready */
-#define XUSBPS_EPCOMPL_OFFSET 0x000001BC /**< Endpoint Complete */
-#define XUSBPS_EPCR0_OFFSET 0x000001C0 /**< Endpoint Control 0 */
-#define XUSBPS_EPCR1_OFFSET 0x000001C4 /**< Endpoint Control 1 */
-#define XUSBPS_EPCR2_OFFSET 0x000001C8 /**< Endpoint Control 2 */
-#define XUSBPS_EPCR3_OFFSET 0x000001CC /**< Endpoint Control 3 */
-#define XUSBPS_EPCR4_OFFSET 0x000001D0 /**< Endpoint Control 4 */
-
-#define XUSBPS_MAX_ENDPOINTS 12 /**< Number of supported Endpoints in
- * this core. */
-#define XUSBPS_EP_OUT_MASK 0x00000FFF /**< OUR (RX) endpoint mask */
-#define XUSBPS_EP_IN_MASK 0x0FFF0000 /**< IN (TX) endpoint mask */
-#define XUSBPS_EP_ALL_MASK 0x0FFF0FFF /**< Mask used for endpoint control
- * registers */
-#define XUSBPS_EPCRn_OFFSET(n) \
- (XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING))
-
-#define XUSBPS_EPFLUSH_RX_SHIFT 0
-#define XUSBPS_EPFLUSH_TX_SHIFT 16
-
-/* @} */
-
-
-
-/** @name Endpoint Control Register (EPCR) bit positions.
- * @{
- */
-
-/* Definitions for TX Endpoint bits */
-#define XUSBPS_EPCR_TXT_TYPE_SHIFT 18 /* < Endpoint Type - TX bit shift*/
-#define XUSBPS_EPCR_TXT_TYPE_MASK 0x000C0000 /* < Endpoint Type - TX read only*/
-#define XUSBPS_EPCR_TXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - TX */
-#define XUSBPS_EPCR_TXT_ISO_MASK 0x00040000 /**< Isochronous. Endpoint */
-#define XUSBPS_EPCR_TXT_BULK_MASK 0x00080000 /**< Bulk Endpoint - TX */
-#define XUSBPS_EPCR_TXT_INTR_MASK 0x000C0000 /**< Interrupt Endpoint */
-#define XUSBPS_EPCR_TXS_MASK 0x00010000 /**< Stall TX endpoint */
-#define XUSBPS_EPCR_TXE_MASK 0x00800000 /**< Transmit enable - TX */
-#define XUSBPS_EPCR_TXR_MASK 0x00400000 /**< Data Toggle Reset Bit */
-
-
-/* Definitions for RX Endpoint bits */
-#define XUSBPS_EPCR_RXT_TYPE_SHIFT 2 /* < Endpoint Type - RX bit shift*/
-#define XUSBPS_EPCR_RXT_TYPE_MASK 0x0000000C /**< Endpoint Type - RX read only*/
-#define XUSBPS_EPCR_RXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - RX */
-#define XUSBPS_EPCR_RXT_ISO_MASK 0x00000004 /**< Isochronous Endpoint */
-#define XUSBPS_EPCR_RXT_BULK_MASK 0x00000008 /**< Bulk Endpoint - RX */
-#define XUSBPS_EPCR_RXT_INTR_MASK 0x0000000C /**< Interrupt Endpoint */
-#define XUSBPS_EPCR_RXS_MASK 0x00000001 /**< Stall RX endpoint. */
-#define XUSBPS_EPCR_RXE_MASK 0x00000080 /**< Transmit enable. - RX */
-#define XUSBPS_EPCR_RXR_MASK 0x00000040 /**< Data Toggle Reset Bit */
-/* @} */
-
-
-/** @name USB Command Register (CR) bit positions.
- * @{
- */
-#define XUSBPS_CMD_RS_MASK 0x00000001 /**< Run/Stop */
-#define XUSBPS_CMD_RST_MASK 0x00000002 /**< Controller RESET */
-#define XUSBPS_CMD_FS01_MASK 0x0000000C /**< Frame List Size bit 0,1 */
-#define XUSBPS_CMD_PSE_MASK 0x00000010 /**< Periodic Sched Enable */
-#define XUSBPS_CMD_ASE_MASK 0x00000020 /**< Async Sched Enable */
-#define XUSBPS_CMD_IAA_MASK 0x00000040 /**< IRQ Async Advance Doorbell */
-#define XUSBPS_CMD_ASP_MASK 0x00000300 /**< Async Sched Park Mode Cnt */
-#define XUSBPS_CMD_ASPE_MASK 0x00000800 /**< Async Sched Park Mode Enbl */
-#define XUSBPS_CMD_SUTW_MASK 0x00002000 /**< Setup TripWire */
-#define XUSBPS_CMD_ATDTW_MASK 0x00004000 /**< Add dTD TripWire */
-#define XUSBPS_CMD_FS2_MASK 0x00008000 /**< Frame List Size bit 2 */
-#define XUSBPS_CMD_ITC_MASK 0x00FF0000 /**< IRQ Threshold Control */
-/* @} */
-
-
-/**
- * @name Interrupt Threshold
- * These definitions are used by software to set the maximum rate at which the
- * USB controller will generate interrupt requests. The interrupt interval is
- * given in number of micro-frames.
- *
- * USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF)
- * packet each and every 1ms. USB also defines a high-speed micro-frame with a
- * 125us frame time. For each micro-frame a SOF (Start Of Frame) packet is
- * generated. Data is sent in between the SOF packets. The interrupt threshold
- * defines how many micro-frames the controller waits before issuing an
- * interrupt after data has been received.
- *
- * For a threshold of 0 the controller will issue an interrupt immediately
- * after the last byte of the data has been received. For a threshold n>0 the
- * controller will wait for n micro-frames before issuing an interrupt.
- *
- * Therefore, a setting of 8 micro-frames (default) means that the controller
- * will issue at most 1 interrupt per millisecond.
- *
- * @{
- */
-#define XUSBPS_CMD_ITHRESHOLD_0 0x00 /**< Immediate interrupt. */
-#define XUSBPS_CMD_ITHRESHOLD_1 0x01 /**< 1 micro-frame */
-#define XUSBPS_CMD_ITHRESHOLD_2 0x02 /**< 2 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_4 0x04 /**< 4 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_8 0x08 /**< 8 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_16 0x10 /**< 16 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_32 0x20 /**< 32 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_64 0x40 /**< 64 micro-frames */
-#define XUSBPS_CMD_ITHRESHOLD_MAX XUSBPS_CMD_ITHRESHOLD_64
-#define XUSBPS_CMD_ITHRESHOLD_DEFAULT XUSBPS_CMD_ITHRESHOLD_8
-/* @} */
-
-
-
-/** @name USB Interrupt Status Register (ISR) / Interrupt Enable Register (IER)
- * bit positions.
- * @{
- */
-#define XUSBPS_IXR_UI_MASK 0x00000001 /**< USB Transaction Complete */
-#define XUSBPS_IXR_UE_MASK 0x00000002 /**< Transaction Error */
-#define XUSBPS_IXR_PC_MASK 0x00000004 /**< Port Change Detect */
-#define XUSBPS_IXR_FRE_MASK 0x00000008 /**< Frame List Rollover */
-#define XUSBPS_IXR_AA_MASK 0x00000020 /**< Async Advance */
-#define XUSBPS_IXR_UR_MASK 0x00000040 /**< RESET Received */
-#define XUSBPS_IXR_SR_MASK 0x00000080 /**< Start of Frame */
-#define XUSBPS_IXR_SLE_MASK 0x00000100 /**< Device Controller Suspend */
-#define XUSBPS_IXR_ULPI_MASK 0x00000400 /**< ULPI IRQ */
-#define XUSBPS_IXR_HCH_MASK 0x00001000 /**< Host Controller Halted
- * Read Only */
-#define XUSBPS_IXR_RCL_MASK 0x00002000 /**< USB Reclamation Read Only */
-#define XUSBPS_IXR_PS_MASK 0x00004000 /**< Periodic Sched Status
- * Read Only */
-#define XUSBPS_IXR_AS_MASK 0x00008000 /**< Async Sched Status Read only */
-#define XUSBPS_IXR_NAK_MASK 0x00010000 /**< NAK IRQ */
-#define XUSBPS_IXR_UA_MASK 0x00040000 /**< USB Host Async IRQ */
-#define XUSBPS_IXR_UP_MASK 0x00080000 /**< USB Host Periodic IRQ */
-#define XUSBPS_IXR_TI0_MASK 0x01000000 /**< Timer 0 Interrupt */
-#define XUSBPS_IXR_TI1_MASK 0x02000000 /**< Timer 1 Interrupt */
-
-#define XUSBPS_IXR_ALL (XUSBPS_IXR_UI_MASK | \
- XUSBPS_IXR_UE_MASK | \
- XUSBPS_IXR_PC_MASK | \
- XUSBPS_IXR_FRE_MASK | \
- XUSBPS_IXR_AA_MASK | \
- XUSBPS_IXR_UR_MASK | \
- XUSBPS_IXR_SR_MASK | \
- XUSBPS_IXR_SLE_MASK | \
- XUSBPS_IXR_ULPI_MASK | \
- XUSBPS_IXR_HCH_MASK | \
- XUSBPS_IXR_RCL_MASK | \
- XUSBPS_IXR_PS_MASK | \
- XUSBPS_IXR_AS_MASK | \
- XUSBPS_IXR_NAK_MASK | \
- XUSBPS_IXR_UA_MASK | \
- XUSBPS_IXR_UP_MASK | \
- XUSBPS_IXR_TI0_MASK | \
- XUSBPS_IXR_TI1_MASK)
- /**< Mask for ALL IRQ types */
-/* @} */
-
-
-/** @name USB Mode Register (MODE) bit positions.
- * @{
- */
-#define XUSBPS_MODE_CM_MASK 0x00000003 /**< Controller Mode Select */
-#define XUSBPS_MODE_CM_IDLE_MASK 0x00000000
-#define XUSBPS_MODE_CM_DEVICE_MASK 0x00000002
-#define XUSBPS_MODE_CM_HOST_MASK 0x00000003
-#define XUSBPS_MODE_ES_MASK 0x00000004 /**< USB Endian Select */
-#define XUSBPS_MODE_SLOM_MASK 0x00000008 /**< USB Setup Lockout Mode Disable */
-#define XUSBPS_MODE_SDIS_MASK 0x00000010
-#define XUSBPS_MODE_VALID_MASK 0x0000001F
-
-/* @} */
-
-
-/** @name USB Device Address Register (DEVICEADDR) bit positions.
- * @{
- */
-#define XUSBPS_DEVICEADDR_DEVICEAADV_MASK 0x01000000
- /**< Device Addr Auto Advance */
-#define XUSBPS_DEVICEADDR_ADDR_MASK 0xFE000000
- /**< Device Address */
-#define XUSBPS_DEVICEADDR_ADDR_SHIFT 25
- /**< Address shift */
-#define XUSBPS_DEVICEADDR_MAX 127
- /**< Biggest allowed address */
-/* @} */
-
-/** @name USB TT Control Register (TTCTRL) bit positions.
- * @{
- */
-#define XUSBPS_TTCTRL_HUBADDR_MASK 0x7F000000 /**< TT Hub Address */
-/* @} */
-
-
-/** @name USB Burst Size Register (BURSTSIZE) bit posisions.
- * @{
- */
-#define XUSBPS_BURSTSIZE_RX_MASK 0x000000FF /**< RX Burst Length */
-#define XUSBPS_BURSTSIZE_TX_MASK 0x0000FF00 /**< TX Burst Length */
-/* @} */
-
-
-/** @name USB Tx Fill Tuning Register (TXFILL) bit positions.
- * @{
- */
-#define XUSBPS_TXFILL_OVERHEAD_MASK 0x000000FF
- /**< Scheduler Overhead */
-#define XUSBPS_TXFILL_HEALTH_MASK 0x00001F00
- /**< Scheduler Health Cntr */
-#define XUSBPS_TXFILL_BURST_MASK 0x003F0000
- /**< FIFO Burst Threshold */
-/* @} */
-
-
-/** @name USB ULPI Viewport Register (ULPIVIEW) bit positions.
- * @{
- */
-#define XUSBPS_ULPIVIEW_DATWR_MASK 0x000000FF /**< ULPI Data Write */
-#define XUSBPS_ULPIVIEW_DATRD_MASK 0x0000FF00 /**< ULPI Data Read */
-#define XUSBPS_ULPIVIEW_ADDR_MASK 0x00FF0000 /**< ULPI Data Address */
-#define XUSBPS_ULPIVIEW_PORT_MASK 0x07000000 /**< ULPI Port Number */
-#define XUSBPS_ULPIVIEW_SS_MASK 0x08000000 /**< ULPI Synchronous State */
-#define XUSBPS_ULPIVIEW_RW_MASK 0x20000000 /**< ULPI Read/Write Control */
-#define XUSBPS_ULPIVIEW_RUN_MASK 0x40000000 /**< ULPI Run */
-#define XUSBPS_ULPIVIEW_WU_MASK 0x80000000 /**< ULPI Wakeup */
-/* @} */
-
-
-/** @name Port Status Control Register bit positions.
- * @{
- */
-#define XUSBPS_PORTSCR_CCS_MASK 0x00000001 /**< Current Connect Status */
-#define XUSBPS_PORTSCR_CSC_MASK 0x00000002 /**< Connect Status Change */
-#define XUSBPS_PORTSCR_PE_MASK 0x00000004 /**< Port Enable/Disable */
-#define XUSBPS_PORTSCR_PEC_MASK 0x00000008 /**< Port Enable/Disable Change */
-#define XUSBPS_PORTSCR_OCA_MASK 0x00000010 /**< Over-current Active */
-#define XUSBPS_PORTSCR_OCC_MASK 0x00000020 /**< Over-current Change */
-#define XUSBPS_PORTSCR_FPR_MASK 0x00000040 /**< Force Port Resume */
-#define XUSBPS_PORTSCR_SUSP_MASK 0x00000080 /**< Suspend */
-#define XUSBPS_PORTSCR_PR_MASK 0x00000100 /**< Port Reset */
-#define XUSBPS_PORTSCR_HSP_MASK 0x00000200 /**< High Speed Port */
-#define XUSBPS_PORTSCR_LS_MASK 0x00000C00 /**< Line Status */
-#define XUSBPS_PORTSCR_PP_MASK 0x00001000 /**< Port Power */
-#define XUSBPS_PORTSCR_PO_MASK 0x00002000 /**< Port Owner */
-#define XUSBPS_PORTSCR_PIC_MASK 0x0000C000 /**< Port Indicator Control */
-#define XUSBPS_PORTSCR_PTC_MASK 0x000F0000 /**< Port Test Control */
-#define XUSBPS_PORTSCR_WKCN_MASK 0x00100000 /**< Wake on Connect Enable */
-#define XUSBPS_PORTSCR_WKDS_MASK 0x00200000 /**< Wake on Disconnect Enable */
-#define XUSBPS_PORTSCR_WKOC_MASK 0x00400000 /**< Wake on Over-current Enable */
-#define XUSBPS_PORTSCR_PHCD_MASK 0x00800000 /**< PHY Low Power Suspend -
- * Clock Disable */
-#define XUSBPS_PORTSCR_PFSC_MASK 0x01000000 /**< Port Force Full Speed
- * Connect */
-#define XUSBPS_PORTSCR_PSPD_MASK 0x0C000000 /**< Port Speed */
-/* @} */
-
-
-/** @name On-The-Go Status Control Register (OTGCSR) bit positions.
- * @{
- */
-#define XUSBPS_OTGSC_VD_MASK 0x00000001 /**< VBus Discharge Bit */
-#define XUSBPS_OTGSC_VC_MASK 0x00000002 /**< VBus Charge Bit */
-#define XUSBPS_OTGSC_HAAR_MASK 0x00000004 /**< HW Assist Auto Reset
- * Enable Bit */
-#define XUSBPS_OTGSC_OT_MASK 0x00000008 /**< OTG Termination Bit */
-#define XUSBPS_OTGSC_DP_MASK 0x00000010 /**< Data Pulsing Pull-up
- * Enable Bit */
-#define XUSBPS_OTGSC_IDPU_MASK 0x00000020 /**< ID Pull-up Enable Bit */
-#define XUSBPS_OTGSC_HADP_MASK 0x00000040 /**< HW Assist Data Pulse
- * Enable Bit */
-#define XUSBPS_OTGSC_HABA_MASK 0x00000080 /**< USB Hardware Assist
- * B Disconnect to A
- * Connect Enable Bit */
-#define XUSBPS_OTGSC_ID_MASK 0x00000100 /**< ID Status Flag */
-#define XUSBPS_OTGSC_AVV_MASK 0x00000200 /**< USB A VBus Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_ASV_MASK 0x00000400 /**< USB A Session Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_BSV_MASK 0x00000800 /**< USB B Session Valid Status Flag */
-#define XUSBPS_OTGSC_BSE_MASK 0x00001000 /**< USB B Session End Status Flag */
-#define XUSBPS_OTGSC_1MST_MASK 0x00002000 /**< USB 1 Millisecond Timer Status Flag */
-#define XUSBPS_OTGSC_DPS_MASK 0x00004000 /**< Data Pulse Status Flag */
-#define XUSBPS_OTGSC_IDIS_MASK 0x00010000 /**< USB ID Interrupt Status Flag */
-#define XUSBPS_OTGSC_AVVIS_MASK 0x00020000 /**< USB A VBus Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_ASVIS_MASK 0x00040000 /**< USB A Session Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_BSVIS_MASK 0x00080000 /**< USB B Session Valid Interrupt Status Flag */
-#define XUSBPS_OTGSC_BSEIS_MASK 0x00100000 /**< USB B Session End Interrupt Status Flag */
-#define XUSBPS_OTGSC_1MSS_MASK 0x00200000 /**< 1 Millisecond Timer Interrupt Status Flag */
-#define XUSBPS_OTGSC_DPIS_MASK 0x00400000 /**< Data Pulse Interrupt Status Flag */
-#define XUSBPS_OTGSC_IDIE_MASK 0x01000000 /**< ID Interrupt Enable Bit */
-#define XUSBPS_OTGSC_AVVIE_MASK 0x02000000 /**< USB A VBus Valid Interrupt Enable Bit */
-#define XUSBPS_OTGSC_ASVIE_MASK 0x04000000 /**< USB A Session Valid Interrupt Enable Bit */
-#define XUSBPS_OTGSC_BSVIE_MASK 0x08000000 /**< USB B Session Valid Interrupt Enable Bit */
-#define XUSBPS_OTGSC_BSEE_MASK 0x10000000 /**< USB B Session End Interrupt Enable Bit */
-#define XUSBPS_OTGSC_1MSE_MASK 0x20000000 /**< 1 Millisecond Timer
- * Interrupt Enable Bit */
-#define XUSBPS_OTGSC_DPIE_MASK 0x40000000 /**< Data Pulse Interrupt
- * Enable Bit */
-
-#define XUSBPS_OTG_ISB_ALL (XUSBPS_OTGSC_IDIS_MASK |\
- XUSBPS_OTGSC_AVVIS_MASK | \
- XUSBPS_OTGSC_ASVIS_MASK | \
- XUSBPS_OTGSC_BSVIS_MASK | \
- XUSBPS_OTGSC_BSEIS_MASK | \
- XUSBPS_OTGSC_1MSS_MASK | \
- XUSBPS_OTGSC_DPIS_MASK)
- /** Mask for All IRQ status masks */
-
-#define XUSBPS_OTG_IEB_ALL (XUSBPS_OTGSC_IDIE_MASK |\
- XUSBPS_OTGSC_AVVIE_MASK | \
- XUSBPS_OTGSC_ASVIE_MASK | \
- XUSBPS_OTGSC_BSVIE_MASK | \
- XUSBPS_OTGSC_BSEE_IEB_MASK | \
- XUSBPS_OTGSC_1MSE_MASK | \
- XUSBPS_OTGSC_DPIE_MASK)
- /** Mask for All IRQ Enable masks */
-/* @} */
-
-
-/**< Alignment of the Device Queue Head List BASE. */
-#define XUSBPS_dQH_BASE_ALIGN 2048
-
-/**< Alignment of a Device Queue Head structure. */
-#define XUSBPS_dQH_ALIGN 64
-
-/**< Alignment of a Device Transfer Descriptor structure. */
-#define XUSBPS_dTD_ALIGN 32
-
-/**< Size of one RX buffer for a OUT Transfer Descriptor. */
-#define XUSBPS_dTD_BUF_SIZE 4096
-
-/**< Maximum size of one RX/TX buffer. */
-#define XUSBPS_dTD_BUF_MAX_SIZE 16*1024
-
-/**< Alignment requirement for Transfer Descriptor buffers. */
-#define XUSBPS_dTD_BUF_ALIGN 4096
-
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* This macro reads the given register.
-*
-* @param BaseAddress is the base address for the USB registers.
-* @param RegOffset is the register offset to be read.
-*
-* @return The 32-bit value of the register.
-*
-* @note C-style signature:
-* u32 XUsbPs_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-*****************************************************************************/
-#define XUsbPs_ReadReg(BaseAddress, RegOffset) \
- Xil_In32(BaseAddress + (RegOffset))
-
-
-/****************************************************************************/
-/**
-*
-* This macro writes the given register.
-*
-* @param BaseAddress is the the base address for the USB registers.
-* @param RegOffset is the register offset to be written.
-* @param Data is the the 32-bit value to write to the register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XUsbPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
- *****************************************************************************/
-#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data) \
- Xil_Out32(BaseAddress + (RegOffset), (Data))
-
-
-/************************** Function Prototypes ******************************/
-/*
- * Perform reset operation to the USB PS interface
- */
-void XUsbPs_ResetHw(u32 BaseAddress);
-/************************** Variable Definitions ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XUSBPS_L_H */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e4/a0ba17595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e4/a0ba17595243001d18b399c1eb9b3628
deleted file mode 100644
index c73d6b2..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e4/a0ba17595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,344 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2018 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file mpu.c
-*
-* This file contains initial configuration of the MPU.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 7.00 mus 02/20/14 First release
-* 7.00 mus 03/16/19 Updated MPU region to mark DDR regions as
-* memory, based on the DDR size in hdf
-* 7.01 nis 09/02/19 Map AIE region if AIE instance is defined
-* 7.3 asa 09/25/20 Make changes to update the global array
-* Mpu_Config for the static regions created
-* during boot up.
-* 7.5 mus 01/13/21 Removed redundant declaration for Mpu_Config,
-* declaration is present in xil_mpu.h.
-* 7.5 asa 03/07/21 Ensure that Update_MpuConfig_Array stays in .boot section
-* as it is used only during bootup.
-* Add function header to Init_MPU function.
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xreg_cortexr5.h"
-#include "xil_mpu.h"
-#include "xpseudo_asm.h"
-#include "xparameters.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-static const struct {
- u64 size;
- unsigned int encoding;
-}region_size[] = {
- { 0x20, REGION_32B },
- { 0x40, REGION_64B },
- { 0x80, REGION_128B },
- { 0x100, REGION_256B },
- { 0x200, REGION_512B },
- { 0x400, REGION_1K },
- { 0x800, REGION_2K },
- { 0x1000, REGION_4K },
- { 0x2000, REGION_8K },
- { 0x4000, REGION_16K },
- { 0x8000, REGION_32K },
- { 0x10000, REGION_64K },
- { 0x20000, REGION_128K },
- { 0x40000, REGION_256K },
- { 0x80000, REGION_512K },
- { 0x100000, REGION_1M },
- { 0x200000, REGION_2M },
- { 0x400000, REGION_4M },
- { 0x800000, REGION_8M },
- { 0x1000000, REGION_16M },
- { 0x2000000, REGION_32M },
- { 0x4000000, REGION_64M },
- { 0x8000000, REGION_128M },
- { 0x10000000, REGION_256M },
- { 0x20000000, REGION_512M },
- { 0x40000000, REGION_1G },
- { 0x80000000, REGION_2G },
- { 0x100000000, REGION_4G },
-};
-
-/************************** Function Prototypes ******************************/
-#if defined (__GNUC__)
-void Init_MPU(void) __attribute__((__section__(".boot")));
-static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib) __attribute__((__section__(".boot")));
-static void Xil_DisableMPURegions(void) __attribute__((__section__(".boot")));
-static inline void Update_MpuConfig_Array(u32 Addr,u32 RegSize,u32 RegNum, u32 Attrib) __attribute__((__section__(".boot")));
-#elif defined (__ICCARM__)
-#pragma default_function_attributes = @ ".boot"
-void Init_MPU(void);
-static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib);
-static void Xil_DisableMPURegions(void);
-#endif
-/*****************************************************************************
-*
-* Initialize MPU for a given address map and Enabled the background Region in
-* MPU with default memory attributes for rest of address range for Cortex R5
-* processor.
-*
-* @param None.
-*
-* @return None.
-*
-*
-******************************************************************************/
-static inline void Update_MpuConfig_Array(u32 Addr,u32 RegSize,u32 RegNum,
- u32 Attrib)
-{
- Mpu_Config[RegNum].RegionStatus = MPU_REG_ENABLED;
- Mpu_Config[RegNum].BaseAddress = Addr;
- Mpu_Config[RegNum].Size = RegSize;
- Mpu_Config[RegNum].Attribute = Attrib;
-}
-
-/*****************************************************************************
-*
-* Initialize MPU for during bootup with predefined region attributes.
-*
-* @param None.
-*
-* @return None.
-*
-*
-******************************************************************************/
-void Init_MPU(void)
-{
- u32 Addr;
- u32 RegSize = 0U;
- u32 Attrib;
- u32 RegNum = 0, i;
- u64 size;
-
- Xil_DisableMPURegions();
-
- Addr = 0x00000000U;
-#ifdef XPAR_AXI_NOC_DDR_LOW_0_BASEADDR
- /* If the DDR is present, configure region as per DDR size */
- size = (XPAR_AXI_NOC_DDR_LOW_0_HIGHADDR - XPAR_AXI_NOC_DDR_LOW_0_BASEADDR) + 1;
- if (size < 0x80000000) {
- /* Lookup the size. */
- for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) {
- if (size <= region_size[i].size) {
- RegSize = region_size[i].encoding;
- break;
- }
- }
- } else {
-#ifdef XPAR_AIE_NUM_INSTANCES
- /* If AIE is mapped, DDR space is reduced to 1GB */
- RegSize = REGION_1G;
-#else
- /* if the DDR size is > 2GB, truncate it to 2GB */
- RegSize = REGION_2G;
-#endif
- }
-#else
- /* For DDRless system, configure region for TCM */
- RegSize = REGION_256K;
-#endif
-
- Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /*
- * 1G of strongly ordered memory from 0x80000000 to 0xBFFFFFFF for PL.
- * 256 MB - LPD-AFI
- * 64 MB - VCU controller
- * 192 MB - FPD-AFI-0
- * 256 MB - FPD-AFI-1
- *
- *
- */
- Addr = 0x80000000;
- RegSize = REGION_1G;
- Attrib = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 512M of device memory from 0xC0000000 to 0xDFFFFFFF for QSPI */
- Addr = 0xC0000000U;
- RegSize = REGION_512M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 256M of device memory from 0xE0000000 to 0xEFFFFFFF for PCIe Low */
- Addr = 0xE0000000U;
- RegSize = REGION_256M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 128M of device memory from 0xF0000000 to 0xF7FFFFFF for PMC */
- Addr = 0xF0000000U;
- RegSize = REGION_128M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 16M of device memory from 0xF8000000 to 0xF8FFFFFF for STM_CORESIGHT */
- Addr = 0xF8000000U;
- RegSize = REGION_16M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 1M of device memory from 0xF9000000 to 0xF90FFFFF for RPU_A53_GIC */
- Addr = 0xF9000000U;
- RegSize = REGION_1M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 16M of device memory from 0xFD000000 to 0xFDFFFFFF for FPS slaves */
- Addr = 0xFD000000U;
- RegSize = REGION_16M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 16M of device memory from 0xFE000000 to 0xFEFFFFFF for Upper LPS slaves */
- Addr = 0xFE000000U;
- RegSize = REGION_16M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /*
- * 16M of device memory from 0xFF000000 to 0xFFFFFFFF for Lower LPS slaves,
- * CSU, PMU, TCM, OCM
- */
- Addr = 0xFF000000U;
- RegSize = REGION_16M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /**
- * 1G of remapped adddress space from 0x40000000 to 0x7FFFFFFF for AIE.
- * The number of allocated MPU regions would be 12, 4 being free for
- * the user.
- * TODO: The value assigned to Addr must be parsed from XSA if the
- * remap address is part of it (currently we are not sure if that's
- * the case).
- */
-#ifdef XPAR_AIE_NUM_INSTANCES
- Addr = 0x40000000U;
- RegSize = REGION_1G;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-#endif
-
- /* 256K of OCM RAM from 0xFFFC0000 to 0xFFFFFFFF marked as normal memory */
- Addr = 0xFFFC0000U;
- RegSize = REGION_256K;
- Attrib = NORM_NSHARED_WB_WA| PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
-
- /* A total of 11 MPU regions are allocated with another 5 being free for users */
-
-}
-
-/*****************************************************************************
-*
-* Set the memory attributes for a section of memory with starting address addr
-* of the region size defined by reg_size having attributes attrib of region number
-* reg_num
-*
-* @param addr is the address for which attributes are to be set.
-* @param attrib specifies the attributes for that memory region.
-* @param reg_size specifies the size for that memory region.
-* @param reg_num specifies the number for that memory region.
-* @return None.
-*
-*
-******************************************************************************/
-static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib)
-{
- u32 Local_reg_size = reg_size;
-
- Local_reg_size = Local_reg_size<<1U;
- Local_reg_size |= REGION_EN;
- dsb();
- mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num);
- isb();
- mtcp(XREG_CP15_MPU_REG_BASEADDR,addr); /* Set base address of a region */
- mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL,attrib); /* Set the control attribute */
- mtcp(XREG_CP15_MPU_REG_SIZE_EN,Local_reg_size); /* set the region size and enable it*/
- dsb();
- isb(); /* synchronize context on this processor */
-}
-
-
-/*****************************************************************************
-*
-* Disable all the MPU regions if any of them is enabled
-*
-* @param None.
-*
-* @return None.
-*
-*
-******************************************************************************/
-static void Xil_DisableMPURegions(void)
-{
- u32 Temp = 0U;
- u32 Index = 0U;
- for (Index = 0; Index <= 15; Index++) {
- mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index);
-#if defined (__GNUC__)
- Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
-#endif
- Temp &= (~REGION_EN);
- dsb();
- mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
- dsb();
- isb();
- }
-
-}
-
-#if defined (__ICCARM__)
-#pragma default_function_attributes =
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e4/a5217b575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e4/a5217b575243001d18b399c1eb9b3628
deleted file mode 100644
index fd80a0d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e4/a5217b575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,62 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_clocking.h
-*
-* The xil_clocking.h file contains clocking related functions and macros.
-* certain conditions.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 7.2 sd 12/11/19 First release
-* 7.2 sd 03/20/20 Added checking for isolation case
-*
-*
-******************************************************************************/
-
-#ifndef XIL_CLOCKING_H /* prevent circular inclusions */
-#define XIL_CLOCKING_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xdebug.h"
-#include "xil_printf.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xparameters.h"
-#include "xstatus.h"
-#if defined (XPAR_XCRPSU_0_DEVICE_ID)
-#include "xclockps.h"
-#else
-typedef u32 XClock_OutputClks;
-typedef u64 XClockRate;
-#endif
-
-/***************************** Include Files *********************************/
-
-
-/************************** Constant Definitions *****************************/
-
-
-XStatus Xil_ClockDisable(XClock_OutputClks ClockId);
-XStatus Xil_ClockEnable(XClock_OutputClks ClockId);
-XStatus Xil_ClockInit(void);
-XStatus Xil_ClockGet(void);
-XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate, XClockRate *SetRate);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e4/b1c1e7535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e4/b1c1e7535243001d18b399c1eb9b3628
deleted file mode 100644
index 1e9e6fb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e4/b1c1e7535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,522 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xstatus.h
-*
-* @addtogroup common_status_codes Xilinx software status codes
-*
-* The xstatus.h file contains the Xilinx software status codes.These codes are
-* used throughout the Xilinx device drivers.
-*
-* @{
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XSTATUS_H /* prevent circular inclusions */
-#define XSTATUS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/*********************** Common statuses 0 - 500 *****************************/
-/**
-@name Common Status Codes for All Device Drivers
-@{
-*/
-#define XST_SUCCESS 0L
-#define XST_FAILURE 1L
-#define XST_DEVICE_NOT_FOUND 2L
-#define XST_DEVICE_BLOCK_NOT_FOUND 3L
-#define XST_INVALID_VERSION 4L
-#define XST_DEVICE_IS_STARTED 5L
-#define XST_DEVICE_IS_STOPPED 6L
-#define XST_FIFO_ERROR 7L /*!< An error occurred during an
- operation with a FIFO such as
- an underrun or overrun, this
- error requires the device to
- be reset */
-#define XST_RESET_ERROR 8L /*!< An error occurred which requires
- the device to be reset */
-#define XST_DMA_ERROR 9L /*!< A DMA error occurred, this error
- typically requires the device
- using the DMA to be reset */
-#define XST_NOT_POLLED 10L /*!< The device is not configured for
- polled mode operation */
-#define XST_FIFO_NO_ROOM 11L /*!< A FIFO did not have room to put
- the specified data into */
-#define XST_BUFFER_TOO_SMALL 12L /*!< The buffer is not large enough
- to hold the expected data */
-#define XST_NO_DATA 13L /*!< There was no data available */
-#define XST_REGISTER_ERROR 14L /*!< A register did not contain the
- expected value */
-#define XST_INVALID_PARAM 15L /*!< An invalid parameter was passed
- into the function */
-#define XST_NOT_SGDMA 16L /*!< The device is not configured for
- scatter-gather DMA operation */
-#define XST_LOOPBACK_ERROR 17L /*!< A loopback test failed */
-#define XST_NO_CALLBACK 18L /*!< A callback has not yet been
- registered */
-#define XST_NO_FEATURE 19L /*!< Device is not configured with
- the requested feature */
-#define XST_NOT_INTERRUPT 20L /*!< Device is not configured for
- interrupt mode operation */
-#define XST_DEVICE_BUSY 21L /*!< Device is busy */
-#define XST_ERROR_COUNT_MAX 22L /*!< The error counters of a device
- have maxed out */
-#define XST_IS_STARTED 23L /*!< Used when part of device is
- already started i.e.
- sub channel */
-#define XST_IS_STOPPED 24L /*!< Used when part of device is
- already stopped i.e.
- sub channel */
-#define XST_DATA_LOST 26L /*!< Driver defined error */
-#define XST_RECV_ERROR 27L /*!< Generic receive error */
-#define XST_SEND_ERROR 28L /*!< Generic transmit error */
-#define XST_NOT_ENABLED 29L /*!< A requested service is not
- available because it has not
- been enabled */
-#define XST_NO_ACCESS 30L /* Generic access error */
-#define XST_TIMEOUT 31L /*!< Event timeout occurred */
-
-/** @} */
-/***************** Utility Component statuses 401 - 500 *********************/
-/**
-@name Utility Component Status Codes 401 - 500
-@{
-*/
-#define XST_MEMTEST_FAILED 401L /*!< Memory test failed */
-
-/** @} */
-/***************** Common Components statuses 501 - 1000 *********************/
-/**
-@name Packet Fifo Status Codes 501 - 510
-@{
-*/
-/********************* Packet Fifo statuses 501 - 510 ************************/
-
-#define XST_PFIFO_LACK_OF_DATA 501L /*!< Not enough data in FIFO */
-#define XST_PFIFO_NO_ROOM 502L /*!< Not enough room in FIFO */
-#define XST_PFIFO_BAD_REG_VALUE 503L /*!< Self test, a register value
- was invalid after reset */
-#define XST_PFIFO_ERROR 504L /*!< Generic packet FIFO error */
-#define XST_PFIFO_DEADLOCK 505L /*!< Packet FIFO is reporting
- * empty and full simultaneously
- */
-/** @} */
-/**
-@name DMA Status Codes 511 - 530
-@{
-*/
-/************************** DMA statuses 511 - 530 ***************************/
-
-#define XST_DMA_TRANSFER_ERROR 511L /*!< Self test, DMA transfer
- failed */
-#define XST_DMA_RESET_REGISTER_ERROR 512L /*!< Self test, a register value
- was invalid after reset */
-#define XST_DMA_SG_LIST_EMPTY 513L /*!< Scatter gather list contains
- no buffer descriptors ready
- to be processed */
-#define XST_DMA_SG_IS_STARTED 514L /*!< Scatter gather not stopped */
-#define XST_DMA_SG_IS_STOPPED 515L /*!< Scatter gather not running */
-#define XST_DMA_SG_LIST_FULL 517L /*!< All the buffer descriptors of
- the scatter gather list are
- being used */
-#define XST_DMA_SG_BD_LOCKED 518L /*!< The scatter gather buffer
- descriptor which is to be
- copied over in the scatter
- list is locked */
-#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /*!< No buffer descriptors have been
- put into the scatter gather
- list to be committed */
-#define XST_DMA_SG_COUNT_EXCEEDED 521L /*!< The packet count threshold
- specified was larger than the
- total # of buffer descriptors
- in the scatter gather list */
-#define XST_DMA_SG_LIST_EXISTS 522L /*!< The scatter gather list has
- already been created */
-#define XST_DMA_SG_NO_LIST 523L /*!< No scatter gather list has
- been created */
-#define XST_DMA_SG_BD_NOT_COMMITTED 524L /*!< The buffer descriptor which was
- being started was not committed
- to the list */
-#define XST_DMA_SG_NO_DATA 525L /*!< The buffer descriptor to start
- has already been used by the
- hardware so it can't be reused
- */
-#define XST_DMA_SG_LIST_ERROR 526L /*!< General purpose list access
- error */
-#define XST_DMA_BD_ERROR 527L /*!< General buffer descriptor
- error */
-/** @} */
-/**
-@name IPIF Status Codes Codes 531 - 550
-@{
-*/
-/************************** IPIF statuses 531 - 550 ***************************/
-
-#define XST_IPIF_REG_WIDTH_ERROR 531L /*!< An invalid register width
- was passed into the function */
-#define XST_IPIF_RESET_REGISTER_ERROR 532L /*!< The value of a register at
- reset was not valid */
-#define XST_IPIF_DEVICE_STATUS_ERROR 533L /*!< A write to the device interrupt
- status register did not read
- back correctly */
-#define XST_IPIF_DEVICE_ACK_ERROR 534L /*!< The device interrupt status
- register did not reset when
- acked */
-#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /*!< The device interrupt enable
- register was not updated when
- other registers changed */
-#define XST_IPIF_IP_STATUS_ERROR 536L /*!< A write to the IP interrupt
- status register did not read
- back correctly */
-#define XST_IPIF_IP_ACK_ERROR 537L /*!< The IP interrupt status register
- did not reset when acked */
-#define XST_IPIF_IP_ENABLE_ERROR 538L /*!< IP interrupt enable register was
- not updated correctly when other
- registers changed */
-#define XST_IPIF_DEVICE_PENDING_ERROR 539L /*!< The device interrupt pending
- register did not indicate the
- expected value */
-#define XST_IPIF_DEVICE_ID_ERROR 540L /*!< The device interrupt ID register
- did not indicate the expected
- value */
-#define XST_IPIF_ERROR 541L /*!< Generic ipif error */
-/** @} */
-
-/****************** Device specific statuses 1001 - 4095 *********************/
-/**
-@name Ethernet Status Codes 1001 - 1050
-@{
-*/
-/********************* Ethernet statuses 1001 - 1050 *************************/
-
-#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /*!< Memory space is not big enough
- * to hold the minimum number of
- * buffers or descriptors */
-#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /*!< Memory allocation failed */
-#define XST_EMAC_MII_READ_ERROR 1003L /*!< MII read error */
-#define XST_EMAC_MII_BUSY 1004L /*!< An MII operation is in progress */
-#define XST_EMAC_OUT_OF_BUFFERS 1005L /*!< Driver is out of buffers */
-#define XST_EMAC_PARSE_ERROR 1006L /*!< Invalid driver init string */
-#define XST_EMAC_COLLISION_ERROR 1007L /*!< Excess deferral or late
- * collision on polled send */
-/** @} */
-/**
-@name UART Status Codes 1051 - 1075
-@{
-*/
-/*********************** UART statuses 1051 - 1075 ***************************/
-#define XST_UART
-
-#define XST_UART_INIT_ERROR 1051L
-#define XST_UART_START_ERROR 1052L
-#define XST_UART_CONFIG_ERROR 1053L
-#define XST_UART_TEST_FAIL 1054L
-#define XST_UART_BAUD_ERROR 1055L
-#define XST_UART_BAUD_RANGE 1056L
-
-/** @} */
-/**
-@name IIC Status Codes 1076 - 1100
-@{
-*/
-/************************ IIC statuses 1076 - 1100 ***************************/
-
-#define XST_IIC_SELFTEST_FAILED 1076 /*!< self test failed */
-#define XST_IIC_BUS_BUSY 1077 /*!< bus found busy */
-#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /*!< mastersend attempted with */
- /* general call address */
-#define XST_IIC_STAND_REG_RESET_ERROR 1079 /*!< A non parameterizable reg */
- /* value after reset not valid */
-#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /*!< Tx fifo included in design */
- /* value after reset not valid */
-#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /*!< Rx fifo included in design */
- /* value after reset not valid */
-#define XST_IIC_TBA_REG_RESET_ERROR 1082 /*!< 10 bit addr incl in design */
- /* value after reset not valid */
-#define XST_IIC_CR_READBACK_ERROR 1083 /*!< Read of the control register */
- /* didn't return value written */
-#define XST_IIC_DTR_READBACK_ERROR 1084 /*!< Read of the data Tx reg */
- /* didn't return value written */
-#define XST_IIC_DRR_READBACK_ERROR 1085 /*!< Read of the data Receive reg */
- /* didn't return value written */
-#define XST_IIC_ADR_READBACK_ERROR 1086 /*!< Read of the data Tx reg */
- /* didn't return value written */
-#define XST_IIC_TBA_READBACK_ERROR 1087 /*!< Read of the 10 bit addr reg */
- /* didn't return written value */
-#define XST_IIC_NOT_SLAVE 1088 /*!< The device isn't a slave */
-#define XST_IIC_ARB_LOST 1089 /*!< Arbitration lost for master */
-/** @} */
-/**
-@name ATMC Status Codes 1101 - 1125
-@{
-*/
-/*********************** ATMC statuses 1101 - 1125 ***************************/
-
-#define XST_ATMC_ERROR_COUNT_MAX 1101L /*!< the error counters in the ATM
- controller hit the max value
- which requires the statistics
- to be cleared */
-/** @} */
-/**
-@name Flash Status Codes 1126 - 1150
-@{
-*/
-/*********************** Flash statuses 1126 - 1150 **************************/
-
-#define XST_FLASH_BUSY 1126L /*!< Flash is erasing or programming
- */
-#define XST_FLASH_READY 1127L /*!< Flash is ready for commands */
-#define XST_FLASH_ERROR 1128L /*!< Flash had detected an internal
- error. Use XFlash_DeviceControl
- to retrieve device specific codes
- */
-#define XST_FLASH_ERASE_SUSPENDED 1129L /*!< Flash is in suspended erase state
- */
-#define XST_FLASH_WRITE_SUSPENDED 1130L /*!< Flash is in suspended write state
- */
-#define XST_FLASH_PART_NOT_SUPPORTED 1131L /*!< Flash type not supported by
- driver */
-#define XST_FLASH_NOT_SUPPORTED 1132L /*!< Operation not supported */
-#define XST_FLASH_TOO_MANY_REGIONS 1133L /*!< Too many erase regions */
-#define XST_FLASH_TIMEOUT_ERROR 1134L /*!< Programming or erase operation
- aborted due to a timeout */
-#define XST_FLASH_ADDRESS_ERROR 1135L /*!< Accessed flash outside its
- addressible range */
-#define XST_FLASH_ALIGNMENT_ERROR 1136L /*!< Write alignment error */
-#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /*!< Couldn't return immediately from
- write/erase function with
- XFL_NON_BLOCKING_WRITE/ERASE
- option cleared */
-#define XST_FLASH_CFI_QUERY_ERROR 1138L /*!< Failed to query the device */
-/** @} */
-/**
-@name SPI Status Codes 1151 - 1175
-@{
-*/
-/*********************** SPI statuses 1151 - 1175 ****************************/
-
-#define XST_SPI_MODE_FAULT 1151 /*!< master was selected as slave */
-#define XST_SPI_TRANSFER_DONE 1152 /*!< data transfer is complete */
-#define XST_SPI_TRANSMIT_UNDERRUN 1153 /*!< slave underruns transmit register */
-#define XST_SPI_RECEIVE_OVERRUN 1154 /*!< device overruns receive register */
-#define XST_SPI_NO_SLAVE 1155 /*!< no slave has been selected yet */
-#define XST_SPI_TOO_MANY_SLAVES 1156 /*!< more than one slave is being
- * selected */
-#define XST_SPI_NOT_MASTER 1157 /*!< operation is valid only as master */
-#define XST_SPI_SLAVE_ONLY 1158 /*!< device is configured as slave-only
- */
-#define XST_SPI_SLAVE_MODE_FAULT 1159 /*!< slave was selected while disabled */
-#define XST_SPI_SLAVE_MODE 1160 /*!< device has been addressed as slave */
-#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /*!< device received data in slave mode */
-
-#define XST_SPI_COMMAND_ERROR 1162 /*!< unrecognised command - qspi only */
-#define XST_SPI_POLL_DONE 1163 /*!< controller completed polling the
- device for status */
-/** @} */
-/**
-@name OPB Arbiter Status Codes 1176 - 1200
-@{
-*/
-/********************** OPB Arbiter statuses 1176 - 1200 *********************/
-
-#define XST_OPBARB_INVALID_PRIORITY 1176 /*!< the priority registers have either
- * one master assigned to two or more
- * priorities, or one master not
- * assigned to any priority
- */
-#define XST_OPBARB_NOT_SUSPENDED 1177 /*!< an attempt was made to modify the
- * priority levels without first
- * suspending the use of priority
- * levels
- */
-#define XST_OPBARB_PARK_NOT_ENABLED 1178 /*!< bus parking by id was enabled but
- * bus parking was not enabled
- */
-#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /*!< the arbiter must be in fixed
- * priority mode to allow the
- * priorities to be changed
- */
-/** @} */
-/**
-@name INTC Status Codes 1201 - 1225
-@{
-*/
-/************************ Intc statuses 1201 - 1225 **************************/
-
-#define XST_INTC_FAIL_SELFTEST 1201 /*!< self test failed */
-#define XST_INTC_CONNECT_ERROR 1202 /*!< interrupt already in use */
-/** @} */
-/**
-@name TmrCtr Status Codes 1226 - 1250
-@{
-*/
-/********************** TmrCtr statuses 1226 - 1250 **************************/
-
-#define XST_TMRCTR_TIMER_FAILED 1226 /*!< self test failed */
-/** @} */
-/**
-@name WdtTb Status Codes 1251 - 1275
-@{
-*/
-/********************** WdtTb statuses 1251 - 1275 ***************************/
-
-#define XST_WDTTB_TIMER_FAILED 1251L
-/** @} */
-/**
-@name PlbArb status Codes 1276 - 1300
-@{
-*/
-/********************** PlbArb statuses 1276 - 1300 **************************/
-
-#define XST_PLBARB_FAIL_SELFTEST 1276L
-/** @} */
-/**
-@name Plb2Opb Status Codes 1301 - 1325
-@{
-*/
-/********************** Plb2Opb statuses 1301 - 1325 *************************/
-
-#define XST_PLB2OPB_FAIL_SELFTEST 1301L
-/** @} */
-/**
-@name Opb2Plb Status 1326 - 1350
-@{
-*/
-/********************** Opb2Plb statuses 1326 - 1350 *************************/
-
-#define XST_OPB2PLB_FAIL_SELFTEST 1326L
-/** @} */
-/**
-@name SysAce Status Codes 1351 - 1360
-@{
-*/
-/********************** SysAce statuses 1351 - 1360 **************************/
-
-#define XST_SYSACE_NO_LOCK 1351L /*!< No MPU lock has been granted */
-/** @} */
-/**
-@name PCI Bridge Status Codes 1361 - 1375
-@{
-*/
-/********************** PCI Bridge statuses 1361 - 1375 **********************/
-
-#define XST_PCI_INVALID_ADDRESS 1361L
-/** @} */
-/**
-@name FlexRay Constants 1400 - 1409
-@{
-*/
-/********************** FlexRay constants 1400 - 1409 *************************/
-
-#define XST_FR_TX_ERROR 1400
-#define XST_FR_TX_BUSY 1401
-#define XST_FR_BUF_LOCKED 1402
-#define XST_FR_NO_BUF 1403
-/** @} */
-/**
-@name USB constants 1410 - 1420
-@{
-*/
-/****************** USB constants 1410 - 1420 *******************************/
-
-#define XST_USB_ALREADY_CONFIGURED 1410
-#define XST_USB_BUF_ALIGN_ERROR 1411
-#define XST_USB_NO_DESC_AVAILABLE 1412
-#define XST_USB_BUF_TOO_BIG 1413
-#define XST_USB_NO_BUF 1414
-/** @} */
-/**
-@name HWICAP constants 1421 - 1429
-@{
-*/
-/****************** HWICAP constants 1421 - 1429 *****************************/
-
-#define XST_HWICAP_WRITE_DONE 1421
-
-/** @} */
-/**
-@name AXI VDMA constants 1430 - 1440
-@{
-*/
-/****************** AXI VDMA constants 1430 - 1440 *****************************/
-
-#define XST_VDMA_MISMATCH_ERROR 1430
-/** @} */
-/**
-@name NAND Flash Status Codes 1441 - 1459
-@{
-*/
-/*********************** NAND Flash statuses 1441 - 1459 *********************/
-
-#define XST_NAND_BUSY 1441L /*!< Flash is erasing or
- * programming
- */
-#define XST_NAND_READY 1442L /*!< Flash is ready for commands
- */
-#define XST_NAND_ERROR 1443L /*!< Flash had detected an
- * internal error.
- */
-#define XST_NAND_PART_NOT_SUPPORTED 1444L /*!< Flash type not supported by
- * driver
- */
-#define XST_NAND_OPT_NOT_SUPPORTED 1445L /*!< Operation not supported
- */
-#define XST_NAND_TIMEOUT_ERROR 1446L /*!< Programming or erase
- * operation aborted due to a
- * timeout
- */
-#define XST_NAND_ADDRESS_ERROR 1447L /*!< Accessed flash outside its
- * addressible range
- */
-#define XST_NAND_ALIGNMENT_ERROR 1448L /*!< Write alignment error
- */
-#define XST_NAND_PARAM_PAGE_ERROR 1449L /*!< Failed to read parameter
- * page of the device
- */
-#define XST_NAND_CACHE_ERROR 1450L /*!< Flash page buffer error
- */
-
-#define XST_NAND_WRITE_PROTECTED 1451L /*!< Flash is write protected
- */
-/** @} */
-
-/**************************** Type Definitions *******************************/
-
-typedef s32 XStatus;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
-
-/**
-* @} End of "addtogroup common_status_codes".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e4/e033a4545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e4/e033a4545243001d18b399c1eb9b3628
deleted file mode 100644
index a4e6192..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e4/e033a4545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,97 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xemacps_hw.c
-* @addtogroup emacps_v3_15
-* @{
-*
-* This file contains the implementation of the ethernet interface reset sequence
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.05a kpc 28/06/13 First release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xemacps_hw.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-* This function perform the reset sequence to the given emacps interface by
-* configuring the appropriate control bits in the emacps specific registers.
-* the emacps reset sequence involves the following steps
-* Disable all the interuupts
-* Clear the status registers
-* Disable Rx and Tx engines
-* Update the Tx and Rx descriptor queue registers with reset values
-* Update the other relevant control registers with reset value
-*
-* @param BaseAddr of the interface
-*
-* @return N/A
-*
-* @note
-* This function will not modify the slcr registers that are relevant for
-* emacps controller
-******************************************************************************/
-void XEmacPs_ResetHw(u32 BaseAddr)
-{
- u32 RegVal;
-
- /* Disable the interrupts */
- XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0U);
-
- /* Stop transmission,disable loopback and Stop tx and Rx engines */
- RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET);
- RegVal &= ~((u32)XEMACPS_NWCTRL_TXEN_MASK|
- (u32)XEMACPS_NWCTRL_RXEN_MASK|
- (u32)XEMACPS_NWCTRL_HALTTX_MASK|
- (u32)XEMACPS_NWCTRL_LOOPEN_MASK);
- /* Clear the statistic registers, flush the packets in DPRAM*/
- RegVal |= (XEMACPS_NWCTRL_STATCLR_MASK|
- XEMACPS_NWCTRL_FLUSH_DPRAM_MASK);
- XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCTRL_OFFSET,RegVal);
- /* Clear the interrupt status */
- XEmacPs_WriteReg(BaseAddr,XEMACPS_ISR_OFFSET,XEMACPS_IXR_ALL_MASK);
- /* Clear the tx status */
- XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,(XEMACPS_TXSR_ERROR_MASK|
- (u32)XEMACPS_TXSR_TXCOMPL_MASK|
- (u32)XEMACPS_TXSR_TXGO_MASK));
- /* Clear the rx status */
- XEmacPs_WriteReg(BaseAddr,XEMACPS_RXSR_OFFSET,
- XEMACPS_RXSR_FRAMERX_MASK);
- /* Clear the tx base address */
- XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0U);
- /* Clear the rx base address */
- XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0U);
- /* Update the network config register with reset value */
- XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCFG_OFFSET,XEMACPS_NWCFG_RESET_MASK);
- /* Update the hash address registers with reset value */
- XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0U);
- XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHH_OFFSET,0x0U);
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e4/e1724f565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e4/e1724f565243001d18b399c1eb9b3628
deleted file mode 100644
index 99b1375..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e4/e1724f565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,113 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xbasic_types.h
-*
-*
-* @note Dummy File for backwards compatibility
-*
-
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
-* 7.0 aru 01/21/19 Modified the typedef of u32,u16,u8
-* 7.0 aru 02/06/19 Included stdint.h and stddef.h
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
-#define XBASIC_TYPES_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include
-#include
-
-/** @name Legacy types
- * Deprecated legacy types.
- * @{
- */
-typedef uint8_t Xuint8; /**< unsigned 8-bit */
-typedef char Xint8; /**< signed 8-bit */
-typedef uint16_t Xuint16; /**< unsigned 16-bit */
-typedef short Xint16; /**< signed 16-bit */
-typedef uint32_t Xuint32; /**< unsigned 32-bit */
-typedef long Xint32; /**< signed 32-bit */
-typedef float Xfloat32; /**< 32-bit floating point */
-typedef double Xfloat64; /**< 64-bit double precision FP */
-typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
-
-#if !defined __XUINT64__
-typedef struct
-{
- Xuint32 Upper;
- Xuint32 Lower;
-} Xuint64;
-#endif
-
-/** @name New types
- * New simple types.
- * @{
- */
-#ifndef __KERNEL__
-#ifndef XIL_TYPES_H
-typedef Xuint32 u32;
-typedef Xuint16 u16;
-typedef Xuint8 u8;
-#endif
-#else
-#include
-#endif
-
-#ifndef TRUE
-# define TRUE 1U
-#endif
-
-#ifndef FALSE
-# define FALSE 0U
-#endif
-
-#ifndef NULL
-#define NULL 0U
-#endif
-
-/*
- * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
- * Please use NULL, TRUE and FALSE
- */
-#define XNULL NULL
-#define XTRUE TRUE
-#define XFALSE FALSE
-
-/*
- * This file is deprecated and users
- * should use xil_types.h and xil_assert.h\n\r
- */
-#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
-#warning Please refer the Standalone BSP UG647 for further details
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e5/908ada585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e5/908ada585243001d18b399c1eb9b3628
deleted file mode 100644
index a224878..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e5/908ada585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,454 +0,0 @@
-;******************************************************************************
-; Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-; SPDX-License-Identifier: MIT
-;*****************************************************************************
-;****************************************************************************
-;**
-; @file boot.S
-;
-; This file contains the initial startup code for the Cortex A9 processor
-;
-;
-; MODIFICATION HISTORY:
-;
-; Ver Who Date Changes
-; ----- ------- -------- ---------------------------------------------------
-; 1.00a ecm/sdm 10/20/09 Initial version
-; 3.04a sdm 01/02/12 Updated to clear cp15 regs with unknown reset values
-; 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
-; register settings.
-; 3.06a asa 06/17/12 Modified the TTBR settings and L2 Cache auxiliary
-; register settings.
-; 3.07a sgd 07/05/12 Updated with reset and start Global Timer
-; 3.07a sgd 10/19/12 SMC NOR and SRAM initialization with build option
-; 4.2 pkp 06/19/14 Enabled asynchronous abort exception
-; 4.2 pkp 08/04/14 Removed PEEP board related code which contained
-; initialization of uart smc nor and sram
-; 5.0 pkp 16/12/14 Modified initialization code to enable scu after
-; MMU is enabled and removed incorrect initialization
-; of TLB lockdown register to fix CR#830580
-; 5.1 pkp 05/13/15 Changed the initialization order so to first invalidate
-; caches and TLB, enable MMU and caches, then enable SMP
-; bit in ACTLR. L2Cache invalidation and enabling of L2Cache
-; is done later.
-; 5.4 asa 12/06/15 Added code to initialize SPSR for all relevant modes.
-; 6.0 mus 04/08/16 Added code to detect zynq-7000 base silicon configuration and
-; attempt to enable dual core behavior on single cpu zynq-7000s devices
-; is prevented from corrupting system behavior.
-; 6.0 mus 24/08/16 Check CPU core before putting cpu1 to reset for single core
-; zynq-7000s devices
-; 6.6 srm 10/25/17 Added timer configuration using XTime_StartTTCTimer API.
-* Now the TTC instance as specified by the user will be
-* started.
-;
-;
-; @note
-;
-; None.
-;
-;****************************************************************************
-
-
-
-#include "xparameters.h"
-#include "xil_errata.h"
-
-#define UART_BAUDRATE 115200
-
- EXPORT _prestart
- EXPORT _boot
-
- IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
- IMPORT |Image$$IRQ_STACK$$ZI$$Limit|
- IMPORT |Image$$SPV_STACK$$ZI$$Limit|
- IMPORT |Image$$ABORT_STACK$$ZI$$Limit|
- IMPORT MMUTable
- IMPORT _vector_table
- IMPORT __main
- IMPORT Xil_ExceptionInit
- IMPORT XTime_SetTime
-#if defined SLEEP_TIMER_BASEADDR
- IMPORT XTime_StartTTCTimer
-#endif
-
-PSS_L2CC_BASE_ADDR EQU 0xF8F02000
-PSS_SLCR_BASE_ADDR EQU 0xF8000000
-
-L2CCWay EQU (PSS_L2CC_BASE_ADDR + 0x077C) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)
-L2CCSync EQU (PSS_L2CC_BASE_ADDR + 0x0730) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)
-L2CCCrtl EQU (PSS_L2CC_BASE_ADDR + 0x0100) ;(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)
-L2CCAuxCrtl EQU (PSS_L2CC_BASE_ADDR + 0x0104) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)
-L2CCTAGLatReg EQU (PSS_L2CC_BASE_ADDR + 0x0108) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)
-L2CCDataLatReg EQU (PSS_L2CC_BASE_ADDR + 0x010C) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)
-L2CCIntClear EQU (PSS_L2CC_BASE_ADDR + 0x0220) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)
-L2CCIntRaw EQU (PSS_L2CC_BASE_ADDR + 0x021C) ;(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)
-
-SLCRlockReg EQU (PSS_SLCR_BASE_ADDR + 0x04) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/
-SLCRUnlockReg EQU (PSS_SLCR_BASE_ADDR + 0x08) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/
-SLCRL2cRamReg EQU (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/
-SLCRCPURSTReg EQU (0xF8000000 + 0x244) ;(XPS_SYS_CTRL_BASEADDR + A9_CPU_RST_CTRL_OFFSET)
-EFUSEStaus EQU (0xF800D000 + 0x10) ;(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)
-
-SLCRlockKey EQU 0x767B /* SLCR lock key */
-SLCRUnlockKey EQU 0xDF0D /* SLCR unlock key */
-SLCRL2cRamConfig EQU 0x00020202 /* SLCR L2C ram configuration */
-
-CRValMmuCac EQU 2_01000000000101 ; Enable IDC, and MMU
-CRValHiVectorAddr EQU 2_10000000000000 ; Set the Vector address to high, 0xFFFF0000
-
-L2CCAuxControl EQU 0x72360000 ; Enable all prefetching, Way Size (16 KB) and High Priority for SO and Dev Reads Enable
-L2CCControl EQU 0x01 ; Enable L2CC
-L2CCTAGLatency EQU 0x0111 ; 7 Cycles of latency for TAG RAM
-L2CCDataLatency EQU 0x0121 ; 7 Cycles of latency for DATA RAM
-
-FPEXC_EN EQU 0x40000000 ; FPU enable bit, (1 << 30)
-
- AREA |.boot|, CODE
- PRESERVE8
-
-
-; this initializes the various processor modes
-
-_prestart
-_boot
-
-#if XPAR_CPU_ID==0
-; only allow cp0 through
- mrc p15,0,r1,c0,c0,5
- and r1, r1, #0xf
- cmp r1, #0
- beq CheckEFUSE
-EndlessLoop0
- wfe
- b EndlessLoop0
-
-CheckEFUSE
- ldr r0,=EFUSEStaus
- ldr r1,[r0] ; Read eFuse setting
- ands r1,r1,#0x80 ; Check whether device is having single core
- beq OKToRun
- ; Single core device, reset CPU1
- ldr r0,=SLCRUnlockReg ; Load SLCR base address base + unlock register
- ldr r1,=SLCRUnlockKey ; set unlock key
- str r1, [r0] ; Unlock SLCR
-
- ldr r0,=SLCRCPURSTReg
- ldr r1,[r0] ; Read CPU Software Reset Control register
- orr r1,r1,#0x22
- str r1,[r0] ; Reset CPU1
-
- ldr r0,=SLCRlockReg ; Load SLCR base address base + lock register
- ldr r1,=SLCRlockKey ; set lock key
- str r1, [r0] ; lock SLCR
-
-#elif XPAR_CPU_ID==1
-; only allow cpu1 through
- mrc p15,0,r1,c0,c0,5
- and r1, r1, #0xf
- cmp r1, #1
- beq CheckEFUSE1
- b EndlessLoop1
-
-CheckEFUSE1
- ldr r0,=EFUSEStaus
- ldr r1,[r0] ; Read eFuse setting
- ands r1,r1,#0x80 ; Check whether device is having single core
- beq OKToRun
-EndlessLoop1
- wfe
- b EndlessLoop1
-#endif
-
-OKToRun
- mrc p15, 0, r0, c0, c0, 0 /* Get the revision */
- and r5, r0, #0x00f00000
- and r6, r0, #0x0000000f
- orr r6, r6, r5, lsr #20-4
-
-#ifdef CONFIG_ARM_ERRATA_742230
- cmp r6, #0x22 /* only present up to r2p2 */
- mrcle p15, 0, r10, c15, c0, 1 /* read diagnostic register */
- orrle r10, r10, #1 << 4 /* set bit #4 */
- mcrle p15, 0, r10, c15, c0, 1 /* write diagnostic register */
-#endif
-
-#ifdef CONFIG_ARM_ERRATA_743622
- teq r5, #0x00200000 /* only present in r2p* */
- mrceq p15, 0, r10, c15, c0, 1 /* read diagnostic register */
- orreq r10, r10, #1 << 6 /* set bit #6 */
- mcreq p15, 0, r10, c15, c0, 1 /* write diagnostic register */
-#endif
-
- /* set VBAR to the _vector_table address in scatter file */
- ldr r0, =_vector_table
- mcr p15, 0, r0, c12, c0, 0
-
- ;invalidate scu
- ldr r7, =0xf8f0000c
- ldr r6, =0xffff
- str r6, [r7]
-
- ;Invalidate caches and TLBs
- mov r0,#0 ; r0 = 0
- mcr p15, 0, r0, c8, c7, 0 ; invalidate TLBs
- mcr p15, 0, r0, c7, c5, 0 ; invalidate icache
- mcr p15, 0, r0, c7, c5, 6 ; Invalidate branch predictor array
- bl invalidate_dcache ; invalidate dcache
-
- ; Disable MMU, if enabled
- mrc p15, 0, r0, c1, c0, 0 ; read CP15 register 1
- bic r0, r0, #0x1 ; clear bit 0
- mcr p15, 0, r0, c1, c0, 0 ; write value back
-
-#ifdef SHAREABLE_DDR
- ; Mark the entire DDR memory as shareable
- ldr r3, =0x3ff ; 1024 entries to cover 1G DDR
- ldr r0, =TblBase ; MMU Table address in memory
- ldr r2, =0x15de6 ; S=1, TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1
-shareable_loop:
- str r2, [r0] ; write the entry to MMU table
- add r0, r0, #0x4 ; next entry in the table
- add r2, r2, #0x100000 ; next section
- subs r3, r3, #1
- bge shareable_loop ; loop till 1G is covered
-#endif
-
- mrs r0, cpsr ; get the current PSR
- mvn r1, #0x1f ; set up the irq stack pointer
- and r2, r1, r0
- orr r2, r2, #0x12 ; IRQ mode
- msr apsr, r2 ; was cpsr, apsr is considered synonym
- ldr r13,=|Image$$IRQ_STACK$$ZI$$Limit| ; IRQ stack pointer
- bic r2, r2, #(0x1 << 9) ; Set EE bit to little-endian
- msr spsr_fsxc,r2
-
- mrs r0, cpsr ; get the current PSR
- mvn r1, #0x1f ; set up the supervisor stack pointer
- and r2, r1, r0
- orr r2, r2, #0x13 ; supervisor mode
- msr apsr, r2 ; was cpsr, apsr is considered synonym
- ldr r13,=|Image$$SPV_STACK$$ZI$$Limit| ; Supervisor stack pointer
- bic r2, r2, #(0x1 << 9) ; Set EE bit to little-endian
- msr spsr_fsxc,r2
-
- mrs r0, cpsr ; get the current PSR
- mvn r1, #0x1f ; set up the Abort stack pointer
- and r2, r1, r0
- orr r2, r2, #0x17 ; Abort mode
- msr apsr, r2 ; was cpsr, apsr is considered synonym
- ldr r13,=|Image$$ABORT_STACK$$ZI$$Limit| ; Abort stack pointer
- bic r2, r2, #(0x1 << 9) ; Set EE bit to little-endian
- msr spsr_fsxc,r2
-
- mrs r0, cpsr ; get the current PSR
- mvn r1, #0x1f ; set up the system stack pointer
- and r2, r1, r0
- orr r2, r2, #0x1f ; SYS mode
- msr apsr, r2 ; was cpsr, apsr is considered synonym
- ldr r13,=|Image$$ARM_LIB_STACK$$ZI$$Limit| ; SYS stack pointer
-
- ;set scu enable bit in scu
- ldr r7, =0xf8f00000
- ldr r0, [r7]
- orr r0, r0, #0x1
- str r0, [r7]
-
- ; enable MMU and cache
-
- ldr r0,=MMUTable ; Load MMU translation table base
- orr r0, r0, #0x5B ; Outer-cacheable, WB
- mcr p15, 0, r0, c2, c0, 0 ; TTB0
-
- mvn r0,#0
- mcr p15,0,r0,c3,c0,0
-
- ; Enable mmu, icahce and dcache
- ldr r0,=CRValMmuCac
-
- mcr p15,0,r0,c1,c0,0 ; Enable cache and MMU
- dsb ; dsb allow the MMU to start up
- isb ; isb flush prefetch buffer
-
-
- ; Write to ACTLR
- mrc p15, 0,r0, c1, c0, 1 ; Read ACTLR
- orr r0, r0, #(0x01 << 6) ; SMP bit
- orr r0, r0, #(0x01 ) ; Cache/TLB maintenance broadcast
- mcr p15, 0,r0, c1, c0, 1 ; Write ACTLR
-
-; Invalidate L2 Cache and initialize L2 Cache
-; For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux)
-#if USE_AMP!=1
- ldr r0,=L2CCCrtl ; Load L2CC base address base + control register
- mov r1, #0 ; force the disable bit
- str r1, [r0] ; disable the L2 Caches
-
- ldr r0,=L2CCAuxCrtl ; Load L2CC base address base + Aux control register
- ldr r1,[r0] ; read the register
- ldr r2,=L2CCAuxControl ; set the default bits
- orr r1,r1,r2
- str r1, [r0] ; store the Aux Control Register
-
- ldr r0,=L2CCTAGLatReg ; Load L2CC base address base + TAG Latency address
- ldr r1,=L2CCTAGLatency ; set the latencies for the TAG
- str r1, [r0] ; store the TAG Latency register Register
-
- ldr r0,=L2CCDataLatReg ; Load L2CC base address base + Data Latency address
- ldr r1,=L2CCDataLatency ; set the latencies for the Data
- str r1, [r0] ; store the Data Latency register Register
-
- ldr r0,=L2CCWay ; Load L2CC base address base + way register
- ldr r2, =0xFFFF
- str r2, [r0] ; force invalidate
-
- ldr r0,=L2CCSync ; need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET
- ; Load L2CC base address base + sync register
- ; poll for completion
-Sync
- ldr r1, [r0]
- cmp r1, #0
- bne Sync
-
- ldr r0,=L2CCIntRaw ; clear pending interrupts
- ldr r1,[r0]
- ldr r0,=L2CCIntClear
- str r1,[r0]
-
- ldr r0,=SLCRUnlockReg ;Load SLCR base address base + unlock register
- ldr r1,=SLCRUnlockKey ;set unlock key
- str r1, [r0] ;Unlock SLCR
-
- ldr r0,=SLCRL2cRamReg ;Load SLCR base address base + l2c Ram Control register
- ldr r1,=SLCRL2cRamConfig ;set the configuration value
- str r1, [r0] ;store the L2c Ram Control Register
-
- ldr r0,=SLCRlockReg ;Load SLCR base address base + lock register
- ldr r1,=SLCRlockKey ;set lock key
- str r1, [r0] ;lock SLCR
-
- ldr r0,=L2CCCrtl ; Load L2CC base address base + control register
- ldr r1,[r0] ; read the register
- mov r2, #L2CCControl ; set the enable bit
- orr r1,r1,r2
- str r1, [r0] ; enable the L2 Caches
-#endif
-
- mov r0, r0
- mrc p15, 0, r1, c1, c0, 2 ; read cp access control register (CACR) into r1
- orr r1, r1, #(0xf << 20) ; enable full access for p10 & p11
- mcr p15, 0, r1, c1, c0, 2 ; write back into CACR
-
- ; enable vfp
- fmrx r1, FPEXC ; read the exception register
- orr r1,r1, #FPEXC_EN ; set VFP enable bit, leave the others in orig state
- fmxr FPEXC, r1 ; write back the exception register
-
- mrc p15, 0, r0, c1, c0, 0 ; flow prediction enable
- orr r0, r0, #(0x01 << 11) ; #0x8000
- mcr p15,0,r0,c1,c0,0
-
- mrc p15, 0, r0, c1, c0, 1 ; read Auxiliary Control Register
- orr r0, r0, #(0x1 << 2) ; enable Dside prefetch
- orr r0, r0, #(0x1 << 1) ; enable L2 prefetch
- mcr p15, 0, r0, c1, c0, 1 ; write Auxiliary Control Register
-
- mrs r0, cpsr /* get the current PSR */
- bic r0, r0, #0x100 /* enable asynchronous abort exception */
- msr cpsr_xsf, r0
-
-; Clear cp15 regs with unknown reset values
- mov r0, #0x0
- mcr p15, 0, r0, c5, c0, 0 ; DFSR
- mcr p15, 0, r0, c5, c0, 1 ; IFSR
- mcr p15, 0, r0, c6, c0, 0 ; DFAR
- mcr p15, 0, r0, c6, c0, 2 ; IFAR
- mcr p15, 0, r0, c9, c13, 2 ; PMXEVCNTR
- mcr p15, 0, r0, c13, c0, 2 ; TPIDRURW
- mcr p15, 0, r0, c13, c0, 3 ; TPIDRURO
-
-; Reset and start Cycle Counter
- mov r2, #0x80000000 ; clear overflow
- mcr p15, 0, r2, c9, c12, 3
- mov r2, #0xd ; D, C, E
- mcr p15, 0, r2, c9, c12, 0
- mov r2, #0x80000000 ; enable cycle counter
- mcr p15, 0, r2, c9, c12, 1
-
-; Reset and start Global Timer
- mov r0, #0x0
- mov r1, #0x0
- bl XTime_SetTime
-
-; Reset and start Triple Timer counter
- #if defined SLEEP_TIMER_BASEADDR
- bl XTime_StartTTCTimer
- #endif
-
-#ifdef PROFILING /* defined in Makefile */
- /* Setup profiling stuff */
- bl _profile_init
-#endif /* PROFILING */
-
-; make sure argc and argv are valid
- mov r0, #0
- mov r1, #0
- b __main ; jump to C startup code
- and r0, r0, r0 ; no op
-
-Ldone b Ldone ; Paranoia: we should never get here
-
-
-; *************************************************************************
-; *
-; * invalidate_dcache - invalidate the entire d-cache by set/way
-; *
-; * Note: for Cortex-A9, there is no cp instruction for invalidating
-; * the whole D-cache. Need to invalidate each line.
-; *
-; *************************************************************************
-
-invalidate_dcache
- mrc p15, 1, r0, c0, c0, 1 ; read CLIDR
- ands r3, r0, #0x7000000
- mov r3, r3, lsr #23 ; cache level value (naturally aligned)
- beq finished
- mov r10, #0 ; start with level 0
-loop1
- add r2, r10, r10, lsr #1 ; work out 3xcachelevel
- mov r1, r0, lsr r2 ; bottom 3 bits are the Cache type for this level
- and r1, r1, #7 ; get those 3 bits alone
- cmp r1, #2
- blt skip ; no cache or only instruction cache at this level
- mcr p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register
- isb ; isb to sync the change to the CacheSizeID reg
- mrc p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register
- and r2, r1, #7 ; extract the line length field
- add r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
- ldr r4, =0x3ff
- ands r4, r4, r1, lsr #3 ; r4 is the max number on the way size (right aligned)
- clz r5, r4 ; r5 is the bit position of the way size increment
- ldr r7, =0x7fff
- ands r7, r7, r1, lsr #13 ; r7 is the max number of the index size (right aligned)
-loop2
- mov r9, r4 ; r9 working copy of the max way size (right aligned)
-loop3
- orr r11, r10, r9, lsl r5 ; factor in the way number and cache number into r11
- orr r11, r11, r7, lsl r2 ; factor in the index number
- mcr p15, 0, r11, c7, c6, 2 ; invalidate by set/way
- subs r9, r9, #1 ; decrement the way number
- bge loop3
- subs r7, r7, #1 ; decrement the index
- bge loop2
-skip
- add r10, r10, #2 ; increment the cache number
- cmp r3, r10
- bgt loop1
-
-finished
- mov r10, #0 ; switch back to cache level 0
- mcr p15, 2, r10, c0, c0, 0 ; select current cache level in cssr
- isb
-
- bx lr
-
- END
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e5/a1a2a4575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e5/a1a2a4575243001d18b399c1eb9b3628
deleted file mode 100644
index 2782826..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e5/a1a2a4575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,342 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xsdps.h
-* @addtogroup sdps_v3_13
-* @{
-* @details
-*
-* This file contains the implementation of XSdPs driver.
-* This driver is used initialize read from and write to the SD card.
-* Features such as switching bus width to 4-bit and switching to high speed,
-* changing clock frequency, block size etc. are supported.
-* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
-* is done using 1-bit bus width and 400KHz clock frequency.
-* SD commands are classified as broadcast and addressed. Commands can be
-* those with response only (using only command line) or
-* response + data (using command and data lines).
-* Only one command can be sent at a time. During a data transfer however,
-* when dsta lines are in use, certain commands (which use only the command
-* line) can be sent, most often to obtain status.
-* This driver does not support multi card slots at present.
-*
-* Initialization:
-* This includes initialization on the host controller side to select
-* clock frequency, bus power and default transfer related parameters.
-* The default voltage is 3.3V.
-* On the SD card side, the initialization and identification state diagram is
-* implemented. This resets the card, gives it a unique address/ID and
-* identifies key card related specifications.
-*
-* Data transfer:
-* The SD card is put in transfer state to read from or write to it.
-* The default block size is 512 bytes and if supported,
-* default bus width is 4-bit and bus speed is High speed.
-* The read and write functions are implemented in polled mode using ADMA2.
-*
-* At any point, when key parameters such as block size or
-* clock/speed or bus width are modified, this driver takes care of
-* maintaining the same selection on host and card.
-* All error bits in host controller are monitored by the driver and in the
-* event one of them is set, driver will clear the interrupt status and
-* communicate failure to the upper layer.
-*
-* File system use:
-* This driver can be used with xilffs library to read and write files to SD.
-* (Please refer to procedure in diskio.c). The file system read/write example
-* in polled mode can used for reference.
-*
-* There is no example for using SD driver without file system at present.
-* However, the driver can be used without the file system. The glue layer
-* in filesystem can be used as reference for the same. The block count
-* passed to the read/write function in one call is limited by the ADMA2
-* descriptor table and hence care will have to be taken to call read/write
-* API's in a loop for large file sizes.
-*
-* Interrupt mode is not supported because it offers no improvement when used
-* with file system.
-*
-* eMMC support:
-* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
-* The features of eMMC supported by the driver will depend on those supported
-* by the host controller. The current driver supports read/write on eMMC card
-* using 4-bit and high speed mode currently.
-*
-* Features not supported include - card write protect, password setting,
-* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
-* 64-bit addressed ADMA2, erase/pre-erase commands.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a hk/sg 10/17/13 Initial release
-* 2.0 hk 03/07/14 Version number revised.
-* 2.1 hk 04/18/14 Increase sleep for eMMC switch command.
-* Add sleep for microblaze designs. CR# 781117.
-* 2.2 hk 07/28/14 Make changes to enable use of data cache.
-* 2.3 sk 09/23/14 Send command for relative card address
-* when re-initialization is done.CR# 819614.
-* Use XSdPs_Change_ClkFreq API whenever changing
-* clock.CR# 816586.
-* 2.4 sk 12/04/14 Added support for micro SD without
-* WP/CD. CR# 810655.
-* Checked for DAT Inhibit mask instead of CMD
-* Inhibit mask in Cmd Transfer API.
-* Added Support for SD Card v1.0
-* 2.5 sg 07/09/15 Added SD 3.0 features
-* kvn 07/15/15 Modified the code according to MISRAC-2012.
-* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
-* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
-* sk 12/10/15 Added support for MMC cards.
-* 01/08/16 Added workaround for issue in auto tuning mode
-* of SDR50, SDR104 and HS200.
-* sk 02/16/16 Corrected the Tuning logic.
-* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
-* 2.8 sk 04/20/16 Added new workaround for auto tuning.
-* 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
-* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
-* sk 07/16/16 Added support for UHS modes.
-* sk 07/07/16 Used usleep API for both arm and microblaze.
-* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
-* operating modes.
-* sk 08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
-* CR#956899.
-* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
-* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
-* sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
-* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
-* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value.
-* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
-* sk 02/01/17 Added HSD and DDR mode support for eMMC.
-* sk 02/01/17 Consider bus width parameter from design for switching
-* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
-* sk 03/20/17 Add support for EL1 non-secure mode.
-* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
-* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
-* mn 08/17/17 Enabled CCI support for A53 by adding cache coherency
-* information.
-* mn 09/06/17 Resolved compilation errors with IAR toolchain
-* 3.6 mn 08/01/18 Add support for using 64Bit DMA with 32-Bit Processor
-* 3.7 mn 02/01/19 Add support for idling of SDIO
-* 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
-* mn 09/17/19 Modified ADMA handling API for 32bit and 64bit addresses
-* 3.9 mn 03/03/20 Restructured the code for more readability and modularity
-* mn 03/16/20 Move XSdPs_Select_Card API to User APIs
-* 3.10 mn 06/05/20 Check Transfer completion separately from XSdPs_Read and
-* XSdPs_Write APIs
-* mn 06/05/20 Modified code for SD Non-Blocking Read support
-* 3.11 sk 12/01/20 Tap programming sequence updates like disable OTAPEN
-* always, write zero to tap register for zero tap value.
-* sk 12/07/20 Fix eMMC DDR52 mode write/read issue.
-* sk 12/17/20 Removed checking platform specific SD macros and used
-* Baseaddress instead.
-* 3.12 sk 01/28/21 Added support for non-blocking write.
-* sk 02/12/21 Fix the issue in reading CID and CSD.
-* sk 04/08/21 Fixed doxygen warnings in all source files.
-* sk 05/25/21 Fix the compilation issue in Cortex-A72 + EL1_NS by
-* removing the DLL reset logic (Dead code for Versal).
-* 3.13 sk 08/10/21 Limit the SD operating frequency to 19MHz for Versal.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.4 mmd 04/21/19 First release.
-* 6.5 kal 02/29/20 Added Xil_ConvertStringToHexBE API
-* 7.3 kal 06/30/20 Converted Xil_Ceil macro to API
-* rpo 08/19/20 Added function for read, modify and write
-* bsv 08/21/20 Added XSECURE_TEMPORAL_CHECK macro to add
-* redundancy in security critical functions, to avoid
-* glitches from altering the return values of security
-* critical functions. The macro requires a label to be
-* passed to "go to" in case of error.
-* kpt 09/03/20 Added XSECURE_TEMPORAL_IMPL macro for redundancy
-* kal 09/22/20 Changed the param type from const char to const char*
-* to avoid copying key onto stack
-* td 10/16/20 Added Xil_Strcpy, Xil_Strcat, Xil_SecureMemCpy and
-* Xil_MemCmp functions
-* am 10/13/20 Resolved Coverity warning
-* td 11/19/20 Updated XSECURE_TEMPORAL_CHECK and
-* XSECURE_TEMPORAL_IMPL to fix MISRA C Rule 15.3
-* 7.4 am 11/26/20 Added Xil_StrCpyRange function
-* 7.6 kpt 07/15/21 Added Xil_SecureZeroize function
-*
-*
-*
-*****************************************************************************/
-
-#ifndef XIL_UTIL_H_
-#define XIL_UTIL_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xstatus.h"
-
-/*************************** Constant Definitions *****************************/
-#define XIL_SIZE_OF_NIBBLE_IN_BITS 4U
-#define XIL_SIZE_OF_BYTE_IN_BITS 8U
-
-/* Maximum string length handled by Xil_ValidateHexStr function */
-#define XIL_MAX_HEX_STR_LEN 512U
-
-
-/****************** Macros (Inline Functions) Definitions *********************/
-#ifdef __GNUC__
-/******************************************************************************/
-/**
- *
- * Updates the return value of the called function into Var and VarTmp variables
- * for redundancy. This is to avoid glitches from altering the return values of
- * security critical functions.
- *
- * @param Var is the variable which holds the return value of function
- * executed
- * @param VarTmp is the variable which holds the value stored in Var
- * @param Function is the function to be executed
- * @param Other params are arguments to the called function
- *
- * @return None
- *
- ******************************************************************************/
-#define XSECURE_TEMPORAL_IMPL(Var, VarTmp, Function, ...) \
- { \
- Var = XST_FAILURE; \
- VarTmp = XST_FAILURE; \
- Var = Function(__VA_ARGS__); \
- VarTmp = Var; \
- }
-
-/******************************************************************************/
-/**
- *
- * Adds redundancy while checking the status of the called function.
- * This is to avoid glitches from altering the return values of security
- * critical functions. The macro requires a label to be passed to "go to"
- * in case of error.
- *
- * @param Label is the label defined in function and the control
- * will jump to the label in case of XST_FAILURE
- * @param Status is the variable which holds the return value of
- * function executed
- * @param Function is the function to be executed
- * @param Other params are arguments to the called function
- *
- * @return None
- *
- ******************************************************************************/
-#define XSECURE_TEMPORAL_CHECK(Label, Status, Function, ...) \
- { \
- volatile int StatusTmp = XST_FAILURE; \
- XSECURE_TEMPORAL_IMPL(Status, StatusTmp, Function, __VA_ARGS__); \
- if ((Status != XST_SUCCESS) || \
- (StatusTmp != XST_SUCCESS)) { \
- Status |= StatusTmp;\
- goto Label; \
- } \
- }
-#endif
-
-/*************************** Function Prototypes ******************************/
-/* Ceils the provided float value */
-int Xil_Ceil(float Value);
-
-/* Converts input character to nibble */
-u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num);
-
-/* Convert input hex string to array of 32-bits integers */
-u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len);
-
-/* Waits for specified event */
-u32 Xil_WaitForEvent(u32 RegAddr, u32 EventMask, u32 Event, u32 Timeout);
-
-/* Waits for specified events */
-u32 Xil_WaitForEvents(u32 EventsRegAddr, u32 EventsMask, u32 WaitEvents,
- u32 Timeout, u32* Events);
-
-/* Validate input hex character */
-u32 Xil_IsValidHexChar(const char *Ch);
-
-/* Validate the input string contains only hexadecimal characters */
-u32 Xil_ValidateHexStr(const char *HexStr);
-
-/* Convert string to hex numbers in little enidian format */
-u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len);
-
-/* Returns length of the input string */
-u32 Xil_Strnlen(const char *Str, u32 MaxLen);
-
-/* Convert string to hex numbers in big endian format */
-u32 Xil_ConvertStringToHexBE(const char * Str, u8 * Buf, u32 Len);
-
-/*Read, Modify and Write to an address*/
-void Xil_UtilRMW32(u32 Addr, u32 Mask, u32 Value);
-
-/* Copies source string to destination string */
-int Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size);
-
-/* Copies specified range from source string to destination string */
-int Xil_StrCpyRange(const u8 *Src, u8 *Dst, u32 From, u32 To, u32 MaxSrcLen,
- u32 MaxDstLen);
-
-/* Appends string2 to string1 */
-int Xil_Strcat(char* Str1Ptr, const char* Str2Ptr, const u32 Size);
-
-/* Copies Len bytes from source memory to destination memory */
-int Xil_SecureMemCpy(void * DestPtr, u32 DestPtrLen, const void * SrcPtr, u32 Len);
-
-/* Compares Len bytes from memory1 and memory2 */
-int Xil_MemCmp(const void * Buf1Ptr, const void * Buf2Ptr, u32 Len);
-
-/* Zeroizes the memory of given length */
-int Xil_SecureZeroize(u8 *DataPtr, const u32 Length);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_UTIL_H_ */
-/**
-* @} End of "addtogroup common_utilities".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e5/f052c9555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e5/f052c9555243001d18b399c1eb9b3628
deleted file mode 100644
index fa58233..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e5/f052c9555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,78 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_spinlock.h
-*
-* This header file contains function prototypes to be used while using Xilinx
-* spinlocking mechanism.
-* Please refer to file header contents of xil_spinlock.c to understand in
-* detail the spinlocking mechanism.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 7.5 asa 02/16/21 First release
-* 7.6 sk 08/05/21 Add Boolean check and braces for Xil_IsSpinLockEnabled
-* if condition to fix misrac violations.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00 pkp 05/29/14 First release
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#ifndef XIL_MMU_H
-#define XIL_MMU_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/**
- *@cond nocomments
- */
-
-/* Memory type */
-#define NORM_NONCACHE 0x401UL /* Normal Non-cacheable*/
-#define STRONG_ORDERED 0x409UL /* Strongly ordered (Device-nGnRnE)*/
-#define DEVICE_MEMORY 0x40DUL /* Device memory (Device-nGnRE)*/
-#define RESERVED 0x0UL /* reserved memory*/
-
-/* Normal write-through cacheable inner shareable*/
-#define NORM_WT_CACHE 0x711UL
-
-/* Normal write back cacheable inner-shareable */
-#define NORM_WB_CACHE 0x705UL
-
-/*
- * shareability attribute only applicable to
- * normal cacheable memory
- */
-#define INNER_SHAREABLE (0x3 << 8)
-#define OUTER_SHAREABLE (0x2 << 8)
-#define NON_SHAREABLE (~(0x3 << 8))
-
-/* Execution type */
-#define EXECUTE_NEVER ((0x1 << 53) | (0x1 << 54))
-
-/* Security type */
-#define NON_SECURE (0x1 << 5)
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-/**
- *@endcond
- */
-
-void Xil_SetTlbAttributes(UINTPTR Addr, u64 attrib);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_MMU_H */
-/**
-* @} End of "addtogroup a53_64_mmu_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e7/304c70575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e7/304c70575243001d18b399c1eb9b3628
deleted file mode 100644
index 33822bf..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e7/304c70575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,843 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
- *
- * @file xemacps.h
-* @addtogroup emacps_v3_15
-* @{
-* @details
- *
- * The Xilinx Embedded Processor Block Ethernet driver.
- *
- * For a full description of XEMACPS features, please see the hardware spec.
- * This driver supports the following features:
- * - Memory mapped access to host interface registers
- * - Statistics counter registers for RMON/MIB
- * - API for interrupt driven frame transfers for hardware configured DMA
- * - Virtual memory support
- * - Unicast, broadcast, and multicast receive address filtering
- * - Full and half duplex operation
- * - Automatic PAD & FCS insertion and stripping
- * - Flow control
- * - Support up to four 48bit addresses
- * - Address checking for four specific 48bit addresses
- * - VLAN frame support
- * - Pause frame support
- * - Large frame support up to 1536 bytes
- * - Checksum offload
- *
- * Driver Description
- *
- * The device driver enables higher layer software (e.g., an application) to
- * communicate to the XEmacPs. The driver handles transmission and reception
- * of Ethernet frames, as well as configuration and control. No pre or post
- * processing of frame data is performed. The driver does not validate the
- * contents of an incoming frame in addition to what has already occurred in
- * hardware.
- * A single device driver can support multiple devices even when those devices
- * have significantly different configurations.
- *
- * Initialization & Configuration
- *
- * The XEmacPs_Config structure is used by the driver to configure itself.
- * This configuration structure is typically created by the tool-chain based
- * on hardware build properties.
- *
- * The driver instance can be initialized in
- *
- * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a
- * configuration structure provided by the caller. If running in a system
- * with address translation, the provided virtual memory base address
- * replaces the physical address present in the configuration structure.
- *
- * The device supports DMA only as current development plan. No FIFO mode is
- * supported. The driver expects to start the DMA channels and expects that
- * the user has set up the buffer descriptor lists.
- *
- * Interrupts and Asynchronous Callbacks
- *
- * The driver has no dependencies on the interrupt controller. When an
- * interrupt occurs, the handler will perform a small amount of
- * housekeeping work, determine the source of the interrupt, and call the
- * appropriate callback function. All callbacks are registered by the user
- * level application.
- *
- * Virtual Memory
- *
- * All virtual to physical memory mappings must occur prior to accessing the
- * driver API.
- *
- * For DMA transactions, user buffers supplied to the driver must be in terms
- * of their physical address.
- *
- * DMA
- *
- * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
- * These BDs are typically chained together into a list the hardware follows
- * when transferring data in and out of the packet buffers. Each BD describes
- * a memory region containing either a full or partial Ethernet packet.
- *
- * Interrupt coalescing is not supported from this built-in DMA engine.
- *
- * This API requires the user to understand how the DMA operates. The
- * following paragraphs provide some explanation, but the user is encouraged
- * to read documentation in xemacps_bdring.h as well as study example code
- * that accompanies this driver.
- *
- * The API is designed to get BDs to and from the DMA engine in the most
- * efficient means possible. The first step is to establish a memory region
- * to contain all BDs for a specific channel. This is done with
- * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
- * follow as BDs are processed. The ring will consist of a user defined number
- * of BDs which will all be partially initialized. For example on the transmit
- * channel, the driver will initialize all BDs' so that they are configured
- * for transmit. The more fields that can be permanently setup at
- * initialization, then the fewer accesses will be needed to each BD while
- * the DMA engine is in operation resulting in better throughput and CPU
- * utilization. The best case initialization would require the user to set
- * only a frame buffer address and length prior to submitting the BD to the
- * engine.
- *
- * BDs move through the engine with the help of functions
- * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
- * and XEmacPs_BdRingFree().
- * All these functions handle BDs that are in place. That is, there are no
- * copies of BDs kept anywhere and any BD the user interacts with is an actual
- * BD from the same ring hardware accesses.
- *
- * BDs in the ring go through a series of states as follows:
- * 1. Idle. The driver controls BDs in this state.
- * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
- * reserve BD(s). Once allocated, the user may setup the BD(s) with
- * frame buffer address, length, and other attributes. The user controls
- * BDs in this state.
- * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
- * in this state are either waiting to be processed by hardware, are in
- * process, or have been processed. The DMA engine controls BDs in this
- * state.
- * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
- * user. Once retrieved, the user can examine each BD for the outcome of
- * the DMA transfer. The user controls BDs in this state. After examining
- * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
- * into state 1.
- *
- * Each of the four BD accessor functions operate on a set of BDs. A set is
- * defined as a segment of the BD ring consisting of one or more BDs. The user
- * views the set as a pointer to the first BD along with the number of BDs for
- * that set. The set can be navigated by using macros XEmacPs_BdNext(). The
- * user must exercise extreme caution when changing BDs in a set as there is
- * nothing to prevent doing a mBdNext past the end of the set and modifying a
- * BD out of bounds.
- *
- * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
- * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
- * tandem. The same BD set retrieved with BdRingAlloc should be the same one
- * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
- * BdRIngFree.
- *
- * Alignment & Data Cache Restrictions
- *
- * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
- * aligned. Please reference xemacps_bd.h for cache related macros.
- *
- * DMA Tx:
- *
- * - If frame buffers exist in cached memory, then they must be flushed
- * prior to committing them to hardware.
- *
- * DMA Rx:
- *
- * - If frame buffers exist in cached memory, then the cache must be
- * invalidated for the memory region containing the frame prior to data
- * access
- *
- * Both cache invalidate/flush are taken care of in driver code.
- *
- * Buffer Copying
- *
- * The driver is designed for a zero-copy buffer scheme. That is, the driver
- * will not copy buffers. This avoids potential throughput bottlenecks within
- * the driver. If byte copying is required, then the transfer will take longer
- * to complete.
- *
- * Checksum Offloading
- *
- * The Embedded Processor Block Ethernet can be configured to perform IP, TCP
- * and UDP checksum offloading in both receive and transmit directions.
- *
- * IP packets contain a 16-bit checksum field, which is the 16-bit 1s
- * complement of the 1s complement sum of all 16-bit words in the header.
- * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
- * 1s complement of the 1s complement sum of all 16-bit words in the header,
- * the data and a conceptual pseudo header.
- *
- * To calculate these checksums in software requires each byte of the packet
- * to be read. For TCP and UDP this can use a large amount of processing power.
- * Offloading the checksum calculation to hardware can result in significant
- * performance improvements.
- *
- * The transmit checksum offload is only available to use DMA in packet buffer
- * mode. This is because the complete frame to be transmitted must be read
- * into the packet buffer memory before the checksum can be calculated and
- * written to the header at the beginning of the frame.
- *
- * For IP, TCP or UDP receive checksum offload to be useful, the operating
- * system containing the protocol stack must be aware that this offload is
- * available so that it can make use of the fact that the hardware has verified
- * the checksum.
- *
- * When receive checksum offloading is enabled in the hardware, the IP header
- * checksum is checked, where the packet meets the following criteria:
- *
- * 1. If present, the VLAN header must be four octets long and the CFI bit
- * must not be set.
- * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
- * encoding.
- * 3. IP v4 packet.
- * 4. IP header is of a valid length.
- * 5. Good IP header checksum.
- * 6. No IP fragmentation.
- * 7. TCP or UDP packet.
- *
- * When an IP, TCP or UDP frame is received, the receive buffer descriptor
- * gives an indication if the hardware was able to verify the checksums.
- * There is also an indication if the frame had SNAP encapsulation. These
- * indication bits will replace the type ID match indication bits when the
- * receive checksum offload is enabled.
- *
- * If any of the checksums are verified incorrect by the hardware, the packet
- * is discarded and the appropriate statistics counter incremented.
- *
- * PHY Interfaces
- *
- * RGMII 1.3 is the only interface supported.
- *
- * Asserts
- *
- * Asserts are used within all Xilinx drivers to enforce constraints on
- * parameters. Asserts can be turned off on a system-wide basis by defining,
- * at compile time, the NDEBUG identifier. By default, asserts are turned on
- * and it is recommended that users leave asserts on during development. For
- * deployment use -DNDEBUG compiler switch to remove assert code.
- *
- * @note
- *
- * Xilinx drivers are typically composed of two parts, one is the driver
- * and the other is the adapter. The driver is independent of OS and processor
- * and is intended to be highly portable. The adapter is OS-specific and
- * facilitates communication between the driver and an OS.
- * This driver is intended to be RTOS and processor independent. Any needs for
- * dynamic memory management, threads or thread mutual exclusion, or cache
- * control must be satisfied bythe layer above this driver.
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -------------------------------------------------------
- * 1.00a wsy 01/10/10 First release
- * 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file
- * xemacps_bdring.c is modified. Earlier it was checking for
- * "BdLimit"(passed argument) number of BDs for finding out
- * which BDs are successfully processed. Now one more check
- * is added. It looks for BDs till the current BD pointer
- * reaches HwTail. By doing this processing time is saved.
- * 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
- * xemacps_bdring.c is modified. Now start of packet is
- * searched for returning the number of BDs processed.
- * 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
- * registers. Added a new API to set the bust length.
- * Added some new hash-defines.
- * 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for
- * Rx errors. Under heavy Rx traffic, there will be a large
- * number of errors related to receive buffer not available.
- * Because of a HW bug (SI #692601), under such heavy errors,
- * the Rx data path can become unresponsive. To reduce the
- * probabilities for hitting this HW bug, the SW writes to
- * bit 18 to flush a packet from Rx DPRAM immediately. The
- * changes for it are done in the function
- * XEmacPs_IntrHandler.
- * 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
- * removed. It is expected that all BDs are allocated in
- * from uncached area.
- * 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
- * to 0x1fff. This fixes the CR#744902.
- * Made changes in example file xemacps_example.h to fix compilation
- * issues with iarcc compiler.
- * 2.0 adk 10/12/13 Updated as per the New Tcl API's
- * 2.1 adk 11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
- * 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy
- * address in xparameters.h when GMII to RGMII converter
- * is present in hw.
- * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
- * changes.
- * 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
- * 1000BASE-X mode export proper values to the xparameters.h
- * file. Changes are made in the driver tcl file.
- * 3.0 adk 08/1/15 Don't include gem in peripheral test when gem is
- * configured with PCS/PMA Core. Changes are made in the
- * test app tcl(CR:827686).
- * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
- * 3.0 hk 03/18/15 Added support for jumbo frames. Increase AHB burst.
- * Disable extended mode. Perform all 64 bit changes under
- * check for arch64.
- * Remove "used bit set" from TX error interrupt masks.
- * 3.1 hk 07/27/15 Do not call error handler with '0' error code when
- * there is no error. CR# 869403
- * 08/10/15 Update upper 32 bit tx and rx queue ptr registers.
- * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
- * 3.4 ms 01/23/17 Modified xil_printf statement in main function for all
- * examples to ensure that "Successfully ran" and "Failed"
- * strings are available in all examples. This is a fix
- * for CR-965028.
- * ms 03/17/17 Modified text file in examples folder for doxygen
- * generation.
- * ms 04/05/17 Added tabspace for return statements in functions of
- * xemacps_ieee1588_example.c for proper documentation
- * while generating doxygen.
- * 3.5 hk 08/14/17 Update cache coherency information of the interface in
- * its config structure.
- * 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
- * changed to volatile.
- * Add API XEmacPs_BdRingPtrReset() to reset pointers
- * 3.8 hk 07/19/18 Fixed CPP, GCC and doxygen warnings - CR-1006327
- * hk 09/17/18 Fix PTP interrupt masks and cleanup comments.
- * 3.9 hk 01/23/19 Add RX watermark support
- * 3.11 sd 02/14/20 Add clock support
- * 3.13 nsk 12/14/20 Updated the tcl to not to use the instance names.
- *
- *
- *
- ****************************************************************************/
-
-#ifndef XEMACPS_H /* prevent circular inclusions */
-#define XEMACPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xemacps_hw.h"
-#include "xemacps_bd.h"
-#include "xemacps_bdring.h"
-#if defined (XCLOCKING)
-#include "xil_clocking.h"
-#endif
-
-/************************** Constant Definitions ****************************/
-
-/*
- * Device information
- */
-#define XEMACPS_DEVICE_NAME "xemacps"
-#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC"
-
-
-/** @name Configuration options
- *
- * Device configuration options. See the XEmacPs_SetOptions(),
- * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
- * use options.
- *
- * The default state of the options are noted and are what the device and
- * driver will be set to after calling XEmacPs_Reset() or
- * XEmacPs_Initialize().
- *
- * @{
- */
-
-#define XEMACPS_PROMISC_OPTION 0x00000001U
-/**< Accept all incoming packets.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_FRAME1536_OPTION 0x00000002U
-/**< Frame larger than 1516 support for Tx & Rx.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_VLAN_OPTION 0x00000004U
-/**< VLAN Rx & Tx frame support.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U
-/**< Enable recognition of flow control frames on Rx
- * This option defaults to enabled (set) */
-
-#define XEMACPS_FCS_STRIP_OPTION 0x00000020U
-/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
- * stripped.
- * This option defaults to enabled (set) */
-
-#define XEMACPS_FCS_INSERT_OPTION 0x00000040U
-/**< Generate FCS field and add PAD automatically for outgoing frames.
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U
-/**< Enable Length/Type error checking for incoming frames. When this option is
- * set, the MAC will filter frames that have a mismatched type/length field
- * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
- * types of frames are encountered. When this option is cleared, the MAC will
- * allow these types of frames to be received.
- *
- * This option defaults to disabled (cleared) */
-
-#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U
-/**< Enable the transmitter.
- * This option defaults to enabled (set) */
-
-#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U
-/**< Enable the receiver
- * This option defaults to enabled (set) */
-
-#define XEMACPS_BROADCAST_OPTION 0x00000400U
-/**< Allow reception of the broadcast address
- * This option defaults to enabled (set) */
-
-#define XEMACPS_MULTICAST_OPTION 0x00000800U
-/**< Allows reception of multicast addresses programmed into hash
- * This option defaults to disabled (clear) */
-
-#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U
-/**< Enable the RX checksum offload
- * This option defaults to enabled (set) */
-
-#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U
-/**< Enable the TX checksum offload
- * This option defaults to enabled (set) */
-
-#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U
-#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U
-
-#define XEMACPS_DEFAULT_OPTIONS \
- ((u32)XEMACPS_FLOW_CONTROL_OPTION | \
- (u32)XEMACPS_FCS_INSERT_OPTION | \
- (u32)XEMACPS_FCS_STRIP_OPTION | \
- (u32)XEMACPS_BROADCAST_OPTION | \
- (u32)XEMACPS_LENTYPE_ERR_OPTION | \
- (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
- (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
- (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
- (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
-
-/**< Default options set when device is initialized or reset */
-/*@}*/
-
-/** @name Callback identifiers
- *
- * These constants are used as parameters to XEmacPs_SetHandler()
- * @{
- */
-#define XEMACPS_HANDLER_DMASEND 1U
-#define XEMACPS_HANDLER_DMARECV 2U
-#define XEMACPS_HANDLER_ERROR 3U
-/*@}*/
-
-/* Constants to determine the configuration of the hardware device. They are
- * used to allow the driver to verify it can operate with the hardware.
- */
-#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */
-
-/* The next few constants help upper layers determine the size of memory
- * pools used for Ethernet buffers and descriptor lists.
- */
-#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */
-
-#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */
-#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */
-#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */
-#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
-#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
-#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
- XEMACPS_TRL_SIZE)
-#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
- XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
-#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
- XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
-
-/* DMACR Bust length hash defines */
-
-#define XEMACPS_SINGLE_BURST 0x00000001
-#define XEMACPS_4BYTE_BURST 0x00000004
-#define XEMACPS_8BYTE_BURST 0x00000008
-#define XEMACPS_16BYTE_BURST 0x00000010
-
-
-/**************************** Type Definitions ******************************/
-/** @name Typedefs for callback functions
- *
- * These callbacks are invoked in interrupt context.
- * @{
- */
-/**
- * Callback invoked when frame(s) have been sent or received in interrupt
- * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
- *
- * @param CallBackRef is user data assigned when the callback was set.
- *
- * @note
- * See xemacps_hw.h for bitmasks definitions and the device hardware spec for
- * further information on their meaning.
- *
- */
-typedef void (*XEmacPs_Handler) (void *CallBackRef);
-
-/**
- * Callback when an asynchronous error occurs. To set this callback, invoke
- * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
- * parameter.
- *
- * @param CallBackRef is user data assigned when the callback was set.
- * @param Direction defines either receive or transmit error(s) has occurred.
- * @param ErrorWord definition varies with Direction
- *
- */
-typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
- u32 ErrorWord);
-
-/*@}*/
-
-/**
- * This typedef contains configuration information for a device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
- u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
- * describes whether Cache Coherent or not */
-#if defined (XCLOCKING)
- u32 RefClk; /**< Input clock */
-#endif
- u16 S1GDiv0; /**< 1Gbps Clock Divider 0 */
- u8 S1GDiv1; /**< 1Gbps Clock Divider 1 */
- u16 S100MDiv0; /**< 100Mbps Clock Divider 0 */
- u8 S100MDiv1; /**< 100Mbps Clock Divider 1 */
- u16 S10MDiv0; /**< 10Mbps Clock Divider 0 */
- u8 S10MDiv1; /**< 10Mbps Clock Divider 1 */
-} XEmacPs_Config;
-
-
-/**
- * The XEmacPs driver instance data. The user is required to allocate a
- * structure of this type for every XEmacPs device in the system. A pointer
- * to a structure of this type is then passed to the driver API functions.
- */
-typedef struct XEmacPs_Instance {
- XEmacPs_Config Config; /* Hardware configuration */
- u32 IsStarted; /* Device is currently started */
- u32 IsReady; /* Device is initialized and ready */
- u32 Options; /* Current options word */
-
- XEmacPs_BdRing TxBdRing; /* Transmit BD ring */
- XEmacPs_BdRing RxBdRing; /* Receive BD ring */
-
- XEmacPs_Handler SendHandler;
- XEmacPs_Handler RecvHandler;
- void *SendRef;
- void *RecvRef;
-
- XEmacPs_ErrHandler ErrorHandler;
- void *ErrorRef;
- u32 Version;
- u32 RxBufMask;
- u32 MaxMtuSize;
- u32 MaxFrameSize;
- u32 MaxVlanFrameSize;
-
-} XEmacPs;
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* Retrieve the Tx ring object. This object can be used in the various Ring
-* API functions.
-*
-* @param InstancePtr is the DMA channel to operate on.
-*
-* @return TxBdRing attribute
-*
-* @note
-* C-style signature:
-* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
-
-/****************************************************************************/
-/**
-* Retrieve the Rx ring object. This object can be used in the various Ring
-* API functions.
-*
-* @param InstancePtr is the DMA channel to operate on.
-*
-* @return RxBdRing attribute
-*
-* @note
-* C-style signature:
-* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
-
-/****************************************************************************/
-/**
-*
-* Enable interrupts specified in Mask. The corresponding interrupt for
-* each bit set to 1 in Mask, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to enable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntEnable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_IER_OFFSET, \
- ((Mask) & XEMACPS_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Disable interrupts specified in Mask. The corresponding interrupt for
-* each bit set to 1 in Mask, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to disable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntDisable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_IDR_OFFSET, \
- ((Mask) & XEMACPS_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Enable interrupts specified in Mask. The corresponding interrupt for
-* each bit set to 1 in Mask, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to enable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_INTQ1_IER_OFFSET, \
- ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* Disable interrupts specified in Mask. The corresponding interrupt for
-* each bit set to 1 in Mask, will be enabled.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Mask contains a bit mask of interrupts to disable. The mask can
-* be formed using a set of bitwise or'd values.
-*
-* @note
-* The state of the transmitter and receiver are not modified by this function.
-* C-style signature
-* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
-*
-*****************************************************************************/
-#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_INTQ1_IDR_OFFSET, \
- ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
-
-/****************************************************************************/
-/**
-*
-* This macro triggers trasmit circuit to send data currently in TX buffer(s).
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return
-*
-* @note
-*
-* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_Transmit(InstancePtr) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_NWCTRL_OFFSET, \
- (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
-
-/****************************************************************************/
-/**
-*
-* This macro determines if the device is configured with checksum offloading
-* on the receive channel
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return
-*
-* Boolean TRUE if the device is configured with checksum offloading, or
-* FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_IsRxCsum(InstancePtr) \
- ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
- ? TRUE : FALSE)
-
-/****************************************************************************/
-/**
-*
-* This macro determines if the device is configured with checksum offloading
-* on the transmit channel
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return
-*
-* Boolean TRUE if the device is configured with checksum offloading, or
-* FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_IsTxCsum(InstancePtr) \
- ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
- ? TRUE : FALSE)
-
-/************************** Function Prototypes *****************************/
-
-/****************************************************************************/
-/**
-*
-* This macro sets RX watermark register.
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-* @param High is the non-zero RX high watermark value. When SRAM fill level
-* is above this, a pause frame will be sent.
-* @param Low is the non-zero RX low watermark value. When SRAM fill level
-* is below this, a zero length pause frame will be sent IF the last
-* pause frame sent was non-zero.
-*
-* @return None
-*
-* @note
-*
-* Signature: void XEmacPs_SetRXWatermark(XEmacPs *InstancePtr, u16 High,
-* u16 Low)
-*
-*****************************************************************************/
-#define XEmacPs_SetRXWatermark(InstancePtr, High, Low) \
- XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_RXWATERMARK_OFFSET, \
- (High & XEMACPS_RXWM_HIGH_MASK) | \
- ((Low << XEMACPS_RXWM_LOW_SHFT_MSK) & XEMACPS_RXWM_LOW_MASK) |)
-
-/****************************************************************************/
-/**
-*
-* This macro gets RX watermark register.
-*
-* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
-*
-* @return RX watermark register value
-*
-* @note
-*
-* Signature: void XEmacPs_GetRXWatermark(XEmacPs *InstancePtr)
-*
-*****************************************************************************/
-#define XEmacPs_GetRXWatermark(InstancePtr) \
- XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XEMACPS_RXWATERMARK_OFFSET)
-/*
- * Initialization functions in xemacps.c
- */
-LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
- UINTPTR EffectiveAddress);
-void XEmacPs_Start(XEmacPs *InstancePtr);
-void XEmacPs_Stop(XEmacPs *InstancePtr);
-void XEmacPs_Reset(XEmacPs *InstancePtr);
-void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
- u16 Direction);
-
-/*
- * Lookup configuration in xemacps_sinit.c
- */
-XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
-
-/*
- * Interrupt-related functions in xemacps_intr.c
- * DMA only and FIFO is not supported. This DMA does not support coalescing.
- */
-LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
- void *FuncPointer, void *CallBackRef);
-void XEmacPs_IntrHandler(void *XEmacPsPtr);
-
-/*
- * MAC configuration/control functions in XEmacPs_control.c
- */
-LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
-LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
-u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
-
-LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
-LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
-void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
-
-LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
-void XEmacPs_ClearHash(XEmacPs *InstancePtr);
-void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
-
-void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
- XEmacPs_MdcDiv Divisor);
-void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
-u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
-LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
- u32 RegisterNum, u16 *PhyDataPtr);
-LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
- u32 RegisterNum, u16 PhyData);
-LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
-
-LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
-void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e7/30e77d545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e7/30e77d545243001d18b399c1eb9b3628
deleted file mode 100644
index 5bac22a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e7/30e77d545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,919 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xdevcfg.c
-* @addtogroup devcfg_v3_7
-* @{
-*
-* This file contains the implementation of the interface functions for XDcfg
-* driver. Refer to the header file xdevcfg.h for more detailed information.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
-* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
-* APIs is words (32 bit) and not bytes.
-* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
-* to add information that 2 LSBs of the Source/Destination
-* address when equal to 2�b01 indicate the last DMA command
-* of an overall transfer.
-* Updated the XDcfg_Transfer function to use the
-* Destination Address passed to this API for secure transfers
-* instead of using 0xFFFFFFFF for CR 662197. This issue was
-* resulting in the failure of secure transfers of
-* non-bitstream images.
-* 2.01a nm 08/27/12 Updated the XDcfg_Transfer API to clear the
-* QUARTER_PCAP_RATE_EN bit in the control register for
-* non secure writes for CR 675543.
-* 2.02a nm 01/31/13 Fixed CR# 679335.
-* Added Setting and Clearing the internal PCAP loopback.
-* Removed code for enabling/disabling AES engine as BootROM
-* locks down this setting.
-* Fixed CR# 681976.
-* Skip Checking the PCFG_INIT in case of non-secure DMA
-* loopback.
-* Fixed CR# 699558.
-* XDcfg_Transfer fails to transfer data in loopback mode.
-* 2.03a nm 04/19/13 Fixed CR# 703728.
-* Updated the register definitions as per the latest TRM
-* version UG585 (v1.4) November 16, 2012.
-* 3.0 kpc 21/02/14 Implemented new function XDcfg_ClearControlRegister
-* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
-* updated driver code with != instead of ==,
-* while checking for Interrupt Status with DMA and
-* PCAP Done Mask
-* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
-* XDCFG_INT_STS_OFFSET) &
-* XDCFG_IXR_D_P_DONE_MASK) !=
-* XDCFG_IXR_D_P_DONE_MASK);
-*
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xdevcfg.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/****************************************************************************/
-/**
-*
-* Initialize the Device Config Interface driver. This function
-* must be called before other functions of the driver are called.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param ConfigPtr is the config structure.
-* @param EffectiveAddress is the base address for the device. It could be
-* a virtual address if address translation is supported in the
-* system, otherwise it is the physical address.
-*
-* @return
-* - XST_SUCCESS if initialization was successful.
-* - XST_DEVICE_IS_STARTED if the device has already been started.
-*
-* @note The very first APB access to the Device Configuration Interface
-* block needs to be a write to the UNLOCK register with the value
-* of 0x757BDF0D. This step is to be done once after reset, any
-* other APB access has to come after this. The APB access is
-* considered illegal if the step is not done or if it is done
-* incorrectly. Furthermore, if any of efuse_sec_cfg[5:0] is high,
-* the following additional actions would be carried out.
-* In other words, if all bits are low, the following steps are not
-* done.
-* 1. AES is disabled
-* 2. All APB writes disabled
-* 3. SoC debug fully enabled
-*
-******************************************************************************/
-int XDcfg_CfgInitialize(XDcfg *InstancePtr,
- XDcfg_Config *ConfigPtr, u32 EffectiveAddress)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
-
- /*
- * If the device is started, disallow the initialize and return a
- * status indicating it is started. This allows the user to stop the
- * device and reinitialize, but prevents a user from inadvertently
- * initializing.
- */
- if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
- return XST_DEVICE_IS_STARTED;
- }
-
- /*
- * Copy configuration into instance.
- */
- InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
-
- /*
- * Save the base address pointer such that the registers of the block
- * can be accessed and indicate it has not been started yet.
- */
- InstancePtr->Config.BaseAddr = EffectiveAddress;
- InstancePtr->IsStarted = 0;
-
-
- /* Unlock the Device Configuration Interface */
- XDcfg_Unlock(InstancePtr);
-
- /*
- * Indicate the instance is ready to use, successfully initialized.
- */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- return XST_SUCCESS;
-}
-
-/****************************************************************************/
-/**
-*
-* The functions enables the PCAP interface by setting the PCAP mode bit in the
-* control register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return None.
-*
-* @note Enable FPGA programming from PCAP interface. Enabling this bit
-* disables all the external interfaces from programming of FPGA
-* except for ICAP. The user needs to ensure that the FPGA is
-* programmed through either PCAP or ICAP.
-*
-*****************************************************************************/
-void XDcfg_EnablePCAP(XDcfg *InstancePtr)
-{
- u32 CtrlReg;
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
- (CtrlReg | XDCFG_CTRL_PCAP_MODE_MASK));
-
-}
-
-/****************************************************************************/
-/**
-*
-* The functions disables the PCAP interface by clearing the PCAP mode bit in
-* the control register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_DisablePCAP(XDcfg *InstancePtr)
-{
- u32 CtrlReg;
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
- (CtrlReg & ( ~XDCFG_CTRL_PCAP_MODE_MASK)));
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the contents of the Control Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Mask is the 32 bit mask data to be written to the Register.
-* The mask definitions are defined in the xdevcfg_hw.h file.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask)
-{
- u32 CtrlReg;
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
- (CtrlReg | Mask));
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function Clears the specified bit positions of the Control Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Mask is the 32 bit value which holds the bit positions to be cleared.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask)
-{
- u32 CtrlReg;
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
- (CtrlReg & ~Mask));
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function reads the contents of the Control Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return A 32-bit value representing the contents of the Control
-* Register.
-* Use the XDCFG_CTRL_*_MASK constants defined in xdevcfg_hw.h to
-* interpret the returned value.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XDcfg_GetControlRegister(XDcfg *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Control Register and return the value.
- */
- return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the contents of the Lock Register. These bits
-* can only be set to a 1. They will be cleared after a Power On Reset.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Data is the 32 bit data to be written to the Register.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET, Data);
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function reads the contents of the Lock Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return A 32-bit value representing the contents of the Lock
-* Register.
-* Use the XDCFG_CR_*_MASK constants defined in xdevcfg_hw.h to
-* interpret the returned value.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XDcfg_GetLockRegister(XDcfg *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Lock Register and return the value.
- */
- return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the contents of the Configuration Register with the
-* given value.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Data is the 32 bit data to be written to the Register.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET, Data);
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function reads the contents of the Configuration Register with the
-* given value.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return A 32-bit value representing the contents of the Config
-* Register.
-* Use the XDCFG_CFG_*_MASK constants defined in xdevcfg_hw.h to
-* interpret the returned value.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET);
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the contents of the Status Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Data is the 32 bit data to be written to the Register.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET, Data);
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function reads the contents of the Status Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return A 32-bit value representing the contents of the Status
-* Register.
-* Use the XDCFG_STATUS_*_MASK constants defined in
-* xdevcfg_hw.h to interpret the returned value.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Status Register and return the value.
- */
- return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the contents of the ROM Shadow Control Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Data is the 32 bit data to be written to the Register.
-*
-* @return None.
-*
-* @note This register is can only be written and is used to control the
-* RAM shadow of 32 bit 4K page ROM pages in user mode
-*
-*****************************************************************************/
-void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_ROM_SHADOW_OFFSET,
- Data);
-
-}
-
-/****************************************************************************/
-/**
-*
-* The function reads the contents of the Software ID Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return 32 Bit boot software ID.
-*
-* @note This register is locked for write once the system enters
-* usermode. Hence API for reading the register only is provided.
-*
-*****************************************************************************/
-u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Software ID Register and return the value.
- */
- return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_SW_ID_OFFSET);
-}
-
-/****************************************************************************/
-/**
-*
-* The function sets the bit mask for the feature in Miscellaneous Control
-* Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param Mask is the bit-mask of the feature to be set.
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask)
-{
- u32 RegData;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET,
- (RegData | Mask));
-}
-
-/****************************************************************************/
-/**
-*
-* The function reads the contents of the Miscellaneous Control Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return 32 Bit boot software ID.
-*
-* @note This register is locked for write once the system enters
-* usermode. Hence API to reading the register only is provided.
-*
-*****************************************************************************/
-u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the Miscellaneous Control Register and return the value.
- */
- return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET);
-}
-
-/******************************************************************************/
-/**
-*
-* This function checks if DMA command queue is full.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-*
-* @return XST_SUCCESS is the DMA is busy
-* XST_FAILURE if the DMA is idle
-*
-* @note The DMA queue has a depth of two.
-*
-****************************************************************************/
-u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr)
-{
-
- u32 RegData;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Read the PCAP status register for DMA status */
- RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_STATUS_OFFSET);
-
- if ((RegData & XDCFG_STATUS_DMA_CMD_Q_F_MASK) ==
- XDCFG_STATUS_DMA_CMD_Q_F_MASK){
- return XST_SUCCESS;
- }
-
- return XST_FAILURE;
-}
-
-/******************************************************************************/
-/**
-*
-* This function initiates the DMA transfer.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param SourcePtr contains a pointer to the source memory where the data
-* is to be transferred from.
-* @param SrcWordLength is the number of words (32 bit) to be transferred
-* for the source transfer.
-* @param DestPtr contains a pointer to the destination memory
-* where the data is to be transferred to.
-* @param DestWordLength is the number of words (32 bit) to be transferred
-* for the Destination transfer.
-*
-* @return None.
-*
-* @note It is the responsibility of the caller function to ensure that
-* correct values are passed to this function.
-*
-* The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination)
-* address when equal to 2�b01 indicates the last DMA command of
-* an overall transfer.
-*
-****************************************************************************/
-void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
- u32 SrcWordLength, u32 DestWordLength)
-{
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_DMA_SRC_ADDR_OFFSET,
- SourcePtr);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_DMA_DEST_ADDR_OFFSET,
- DestPtr);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_DMA_SRC_LEN_OFFSET,
- SrcWordLength);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_DMA_DEST_LEN_OFFSET,
- DestWordLength);
-}
-
-/******************************************************************************/
-/**
-*
-* This function Implements the DMA Read Command. This command is used to
-* transfer the image data from FPGA to the external memory.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param SourcePtr contains a pointer to the source memory where the data
-* is to be transferred from.
-* @param SrcWordLength is the number of words (32 bit) to be transferred
-* for the source transfer.
-* @param DestPtr contains a pointer to the destination memory
-* where the data is to be transferred to.
-* @param DestWordLength is the number of words (32 bit) to be transferred
-* for the Destination transfer.
-*
-* @return - XST_INVALID_PARAM if source address/length is invalid.
-* - XST_SUCCESS if DMA transfer initiated properly.
-*
-* @note None.
-*
-****************************************************************************/
-static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr,
- u32 SrcWordLength, u32 DestPtr,
- u32 DestWordLength)
-{
- u32 IntrReg;
-
- /*
- * Send READ Frame command to FPGA
- */
- XDcfg_InitiateDma(InstancePtr, SourcePtr, XDCFG_DMA_INVALID_ADDRESS,
- SrcWordLength, 0);
-
- /*
- * Store the enabled interrupts to enable before the actual read
- * transfer is initiated and Disable all the interrupts temporarily.
- */
- IntrReg = XDcfg_IntrGetEnabled(InstancePtr);
- XDcfg_IntrDisable(InstancePtr, XDCFG_IXR_ALL_MASK);
-
- /*
- * Wait till you get the DMA done for the read command sent
- */
- while ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_INT_STS_OFFSET) &
- XDCFG_IXR_D_P_DONE_MASK) !=
- XDCFG_IXR_D_P_DONE_MASK);
- /*
- * Enable the previously stored Interrupts .
- */
- XDcfg_IntrEnable(InstancePtr, IntrReg);
-
- /*
- * Initiate the DMA write command.
- */
- XDcfg_InitiateDma(InstancePtr, XDCFG_DMA_INVALID_ADDRESS, (u32)DestPtr,
- 0, DestWordLength);
-
- return XST_SUCCESS;
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function starts the DMA transfer. This function only starts the
-* operation and returns before the operation may be completed.
-* If the interrupt is enabled, an interrupt will be generated when the
-* operation is completed, otherwise it is necessary to poll the Status register
-* to determine when it is completed. It is the responsibility of the caller to
-* determine when the operation is completed by handling the generated interrupt
-* or polling the Status Register.
-*
-* @param InstancePtr is a pointer to the XDcfg instance.
-* @param SourcePtr contains a pointer to the source memory where the data
-* is to be transferred from.
-* @param SrcWordLength is the number of words (32 bit) to be transferred
-* for the source transfer.
-* @param DestPtr contains a pointer to the destination memory
-* where the data is to be transferred to.
-* @param DestWordLength is the number of words (32 bit) to be transferred
-* for the Destination transfer.
-* @param TransferType contains the type of PCAP transfer being requested.
-* The definitions can be found in the xdevcfg.h file.
-* @return
-* - XST_SUCCESS.if DMA transfer initiated successfully
-* - XST_DEVICE_BUSY if DMA is busy
-* - XST_INVALID_PARAM if invalid Source / Destination address
-* is sent or an invalid Source / Destination length is
-* sent
-*
-* @note It is the responsibility of the caller to ensure that the cache
-* is flushed and invalidated both before the DMA operation is
-* started and after the DMA operation completes if the memory
-* pointed to is cached. The caller must also ensure that the
-* pointers contain physical address rather than a virtual address
-* if address translation is being used.
-*
-* The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination)
-* address when equal to 2�b01 indicates the last DMA command of
-* an overall transfer.
-*
-*****************************************************************************/
-u32 XDcfg_Transfer(XDcfg *InstancePtr,
- void *SourcePtr, u32 SrcWordLength,
- void *DestPtr, u32 DestWordLength,
- u32 TransferType)
-{
-
- u32 CtrlReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-
- if (XDcfg_IsDmaBusy(InstancePtr) == XST_SUCCESS) {
- return XST_DEVICE_BUSY;
- }
-
- /*
- * Check whether the fabric is in initialized state
- */
- if ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET)
- & XDCFG_STATUS_PCFG_INIT_MASK) == 0) {
- /*
- * We don't need to check PCFG_INIT to be high for
- * non-encrypted loopback transfers.
- */
- if (TransferType != XDCFG_CONCURRENT_NONSEC_READ_WRITE) {
- return XST_FAILURE;
- }
- }
-
- if ((TransferType == XDCFG_SECURE_PCAP_WRITE) ||
- (TransferType == XDCFG_NON_SECURE_PCAP_WRITE)) {
-
- /* Check for valid source pointer and length */
- if ((!SourcePtr) || (SrcWordLength == 0)) {
- return XST_INVALID_PARAM;
- }
-
- /* Clear internal PCAP loopback */
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET);
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET, (CtrlReg &
- ~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
-
- if (TransferType == XDCFG_NON_SECURE_PCAP_WRITE) {
- /*
- * Clear QUARTER_PCAP_RATE_EN bit
- * so that the PCAP data is transmitted every clock
- */
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET, (CtrlReg &
- ~XDCFG_CTRL_PCAP_RATE_EN_MASK));
-
- }
- if (TransferType == XDCFG_SECURE_PCAP_WRITE) {
- /*
- * AES engine handles only 8 bit data every clock cycle.
- * Hence, Encrypted PCAP data which is 32 bit data can
- * only be sent in every 4 clock cycles. Set the control
- * register QUARTER_PCAP_RATE_EN bit to achieve this
- * operation.
- */
- XDcfg_SetControlRegister(InstancePtr,
- XDCFG_CTRL_PCAP_RATE_EN_MASK);
- }
-
- XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr,
- (u32)DestPtr, SrcWordLength, DestWordLength);
-
- }
-
- if (TransferType == XDCFG_PCAP_READBACK) {
-
- if ((!DestPtr) || (DestWordLength == 0)) {
-
- return XST_INVALID_PARAM;
- }
-
- /* Clear internal PCAP loopback */
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET);
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET, (CtrlReg &
- ~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
-
- /*
- * For PCAP readback of FPGA configuration register or memory,
- * the read command is first sent (written) to the FPGA fabric
- * which responds by returning the required read data. Read data
- * from the FPGA is captured if pcap_radata_v is active.A DMA
- * read transfer is required to obtain the readback command,
- * which is then sent to the FPGA, followed by a DMA write
- * transfer to support this mode of operation.
- */
- return XDcfg_PcapReadback(InstancePtr,
- (u32)SourcePtr, SrcWordLength,
- (u32)DestPtr, DestWordLength);
- }
-
-
- if ((TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) ||
- (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE)) {
-
- if ((!SourcePtr) || (SrcWordLength == 0) ||
- (!DestPtr) || (DestWordLength == 0)) {
- return XST_INVALID_PARAM;
- }
-
- if (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE) {
- /* Enable internal PCAP loopback */
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET);
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET, (CtrlReg |
- XDCFG_MCTRL_PCAP_LPBK_MASK));
-
- /*
- * Clear QUARTER_PCAP_RATE_EN bit
- * so that the PCAP data is transmitted every clock
- */
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET);
-
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_CTRL_OFFSET, (CtrlReg &
- ~XDCFG_CTRL_PCAP_RATE_EN_MASK));
-
- }
- if (TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) {
- /* Clear internal PCAP loopback */
- CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET);
- XDcfg_WriteReg(InstancePtr->Config.BaseAddr,
- XDCFG_MCTRL_OFFSET, (CtrlReg &
- ~(XDCFG_MCTRL_PCAP_LPBK_MASK)));
-
- /*
- * Set the QUARTER_PCAP_RATE_EN bit
- * so that the PCAP data is transmitted every 4 clock
- * cycles, this is required for encrypted data.
- */
- XDcfg_SetControlRegister(InstancePtr,
- XDCFG_CTRL_PCAP_RATE_EN_MASK);
- }
-
- XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr,
- (u32)DestPtr, SrcWordLength, DestWordLength);
- }
-
- return XST_SUCCESS;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e7/91a7e4595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e7/91a7e4595243001d18b399c1eb9b3628
deleted file mode 100644
index 6f579ab..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e7/91a7e4595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,541 +0,0 @@
-/*-----------------------------------------------------------------------*/
-/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2016 */
-/*-----------------------------------------------------------------------*/
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file diskio.c
-* This file is the glue layer between file system and
-* driver.
-* Description related to SD driver:
-* Process to use file system with SD
-* Select xilffs in SDK when creating a BSP
-* In SDK, set "fs_interface" to 1 to select SD interface.
-* This glue layer can currently be used only with one
-* SD controller enabled.
-* In order to use eMMC, in SDK set "Enable MMC" to 1. If not,
-* SD support is enabled by default.
-*
-* Description:
-* This glue layer initializes the host controller and SD card
-* in disk_initialize. If SD card supports it, 4-bit mode and
-* high speed mode will be enabled.
-* The default block size is 512 bytes.
-* disk_read and disk_write functions are used to read and
-* write files using ADMA2 in polled mode.
-* The file system can be used to read from and write to an
-* SD card that is already formatted as FATFS.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hk 10/17/13 First release
-* 2.0 hk 02/12/14 Corrected status check in disk initialize. CR# 772072.
-* 2.1 hk 04/16/14 Move check for ExtCSD high speed bit set inside if
-* condition for high speed support.
-* Include xil_types.h irrespective of xsdps.h. CR# 797086.
-* 2.2 hk 07/28/14 Make changes to enable use of data cache.
-* 3.0 sk 12/04/14 Added support for micro SD without
-* WP/CD. CR# 810655.
-* Make changes for prototypes of disk_read and
-* disk_write according to latest version.
-* 12/15/14 Modified the code according to MISRAC 2012 Compliant.
-* Updated the FatFs to R0.10b
-* Removed alignment for local buffers as CacheInvalidate
-* will take care of it.
-* sg 03/03/15 Added card detection check logic
-* 04/28/15 Card detection only in case of card detection signal
-* 3.1 sk 06/04/15 Added support for SD1.
-* 3.2 sk 11/24/15 Considered the slot type before checking the CD/WP pins.
-* 3.3 sk 04/01/15 Added one second delay for checking CD pin.
-* 3.4 sk 06/09/16 Added support for mkfs.
-* 3.8 mj 07/31/17 Added support for RAM based FATfs.
-* mn 12/04/17 Resolve errors in XilFFS for ARMCC compiler
-* 3.9 mn 04/18/18 Resolve build warnings for xilffs library
-* mn 07/06/18 Fix Cppcheck and Doxygen warnings
-* 4.2 mn 08/16/19 Initialize Status variables with failure values
-* mn 09/25/19 Check if the SD is powered on or not in disk_status()
-* 4.3 mn 02/24/20 Remove unused macro defines
-* mn 04/08/20 Set IsReady to '0' before calling XSdPs_CfgInitialize
-* 4.5 sk 03/31/21 Maintain discrete global variables for each controller.
-* 4.6 sk 07/20/21 Fixed compilation warning in RAM interface.
-*
-*
-*
-* @note
-*
-******************************************************************************/
-#include "diskio.h"
-#include "ff.h"
-#include "xil_types.h"
-
-#ifdef FILE_SYSTEM_INTERFACE_SD
-#include "xsdps.h" /* SD device driver */
-#endif
-#include "sleep.h"
-#include "xil_printf.h"
-
-#define SD_CD_DELAY 10000U
-#define XSDPS_NUM_INSTANCES 2
-
-#ifdef FILE_SYSTEM_INTERFACE_RAM
-#include "xparameters.h"
-
-static char *dataramfs = NULL;
-
-#define BLOCKSIZE 1U
-#define SECTORSIZE 512U
-#define SECTORCNT (RAMFS_SIZE / SECTORSIZE)
-#endif
-
-/*--------------------------------------------------------------------------
-
- Public Functions
-
----------------------------------------------------------------------------*/
-
-/*
- * Global variables
- */
-static DSTATUS Stat[XSDPS_NUM_INSTANCES] = {STA_NOINIT, STA_NOINIT}; /* Disk status */
-
-#ifdef FILE_SYSTEM_INTERFACE_SD
-static XSdPs SdInstance[XSDPS_NUM_INSTANCES];
-static u32 BaseAddress[XSDPS_NUM_INSTANCES];
-static u32 CardDetect[XSDPS_NUM_INSTANCES];
-static u32 WriteProtect[XSDPS_NUM_INSTANCES];
-static u32 SlotType[XSDPS_NUM_INSTANCES];
-static u8 HostCntrlrVer[XSDPS_NUM_INSTANCES];
-#endif
-
-/*-----------------------------------------------------------------------*/
-/* Get Disk Status */
-/*-----------------------------------------------------------------------*/
-
-/*****************************************************************************/
-/**
-*
-* Gets the status of the disk.
-* In case of SD, it checks whether card is present or not.
-*
-* @param pdrv - Drive number
-*
-* @return
-* 0 Status ok
-* STA_NOINIT Drive not initialized
-* STA_NODISK No medium in the drive
-* STA_PROTECT Write protected
-*
-* @note In case Card detect signal is not connected,
-* this function will not be able to check if card is present.
-*
-******************************************************************************/
-DSTATUS disk_status (
- BYTE pdrv /* Drive number (0) */
-)
-{
- DSTATUS s = Stat[pdrv];
-#ifdef FILE_SYSTEM_INTERFACE_SD
- u32 StatusReg;
- u32 DelayCount = 0;
-
- if (SdInstance[pdrv].Config.BaseAddress == (u32)0) {
- XSdPs_Config *SdConfig;
-
- SdConfig = XSdPs_LookupConfig((u16)pdrv);
- if (NULL == SdConfig) {
- s |= STA_NOINIT;
- return s;
- }
-
- BaseAddress[pdrv] = SdConfig->BaseAddress;
- CardDetect[pdrv] = SdConfig->CardDetect;
- WriteProtect[pdrv] = SdConfig->WriteProtect;
-
- HostCntrlrVer[pdrv] = (u8)(XSdPs_ReadReg16(BaseAddress[pdrv],
- XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK);
- if (HostCntrlrVer[pdrv] == XSDPS_HC_SPEC_V3) {
- SlotType[pdrv] = XSdPs_ReadReg(BaseAddress[pdrv],
- XSDPS_CAPS_OFFSET) & XSDPS_CAPS_SLOT_TYPE_MASK;
- } else {
- SlotType[pdrv] = 0;
- }
- }
-
- /* If SD is not powered up then mark it as not initialized */
- if ((XSdPs_ReadReg8((u32)BaseAddress[pdrv], XSDPS_POWER_CTRL_OFFSET) &
- XSDPS_PC_BUS_PWR_MASK) == 0U) {
- s |= STA_NOINIT;
- }
-
- StatusReg = XSdPs_GetPresentStatusReg((u32)BaseAddress[pdrv]);
- if (SlotType[pdrv] != XSDPS_CAPS_EMB_SLOT) {
- if (CardDetect[pdrv]) {
- while ((StatusReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U) {
- if (DelayCount == 500U) {
- s = STA_NODISK | STA_NOINIT;
- goto Label;
- } else {
- /* Wait for 10 msec */
- usleep(SD_CD_DELAY);
- DelayCount++;
- StatusReg = XSdPs_GetPresentStatusReg((u32)BaseAddress[pdrv]);
- }
- }
- }
- s &= ~STA_NODISK;
- if (WriteProtect[pdrv]) {
- if ((StatusReg & XSDPS_PSR_WPS_PL_MASK) == 0U){
- s |= STA_PROTECT;
- goto Label;
- }
- }
- s &= ~STA_PROTECT;
- } else {
- s &= ~STA_NODISK & ~STA_PROTECT;
- }
-
-
-Label:
- Stat[pdrv] = s;
-#endif
-
- return s;
-}
-
-/*-----------------------------------------------------------------------*/
-/* Initialize Disk Drive */
-/*-----------------------------------------------------------------------*/
-/*****************************************************************************/
-/**
-*
-* Initializes the drive.
-* In case of SD, it initializes the host controller and the card.
-* This function also selects additional settings such as bus width,
-* speed and block size.
-*
-* @param pdrv - Drive number
-*
-* @return s - which contains an OR of the following information
-* STA_NODISK Disk is not present
-* STA_NOINIT Drive not initialized
-* STA_PROTECT Drive is write protected
-* 0 or only STA_PROTECT both indicate successful initialization.
-*
-* @note
-*
-******************************************************************************/
-DSTATUS disk_initialize (
- BYTE pdrv /* Physical drive number (0) */
-)
-{
- DSTATUS s;
-#ifdef FILE_SYSTEM_INTERFACE_SD
- s32 Status = XST_FAILURE;
- XSdPs_Config *SdConfig;
-#endif
-
- s = disk_status(pdrv);
- if ((s & STA_NODISK) != 0U) {
- return s;
- }
-
- /* If disk is already initialized */
- if ((s & STA_NOINIT) == 0U) {
- return s;
- }
-
-#ifdef FILE_SYSTEM_INTERFACE_SD
- if (CardDetect[pdrv]) {
- /*
- * Card detection check
- * If the HC detects the No Card State, power will be cleared
- */
- while(!((XSDPS_PSR_CARD_DPL_MASK |
- XSDPS_PSR_CARD_STABLE_MASK |
- XSDPS_PSR_CARD_INSRT_MASK) ==
- (XSdPs_GetPresentStatusReg((u32)BaseAddress[pdrv]) &
- (XSDPS_PSR_CARD_DPL_MASK |
- XSDPS_PSR_CARD_STABLE_MASK |
- XSDPS_PSR_CARD_INSRT_MASK))));
- }
-
- /*
- * Initialize the host controller
- */
- SdConfig = XSdPs_LookupConfig((u16)pdrv);
- if (NULL == SdConfig) {
- s |= STA_NOINIT;
- return s;
- }
-
- SdInstance[pdrv].IsReady = 0U;
-
- Status = XSdPs_CfgInitialize(&SdInstance[pdrv], SdConfig,
- SdConfig->BaseAddress);
- if (Status != XST_SUCCESS) {
- s |= STA_NOINIT;
- return s;
- }
-
- Status = XSdPs_CardInitialize(&SdInstance[pdrv]);
- if (Status != XST_SUCCESS) {
- s |= STA_NOINIT;
- return s;
- }
-
-
- /*
- * Disk is initialized.
- * Store the same in Stat.
- */
- s &= (~STA_NOINIT);
-
- Stat[pdrv] = s;
-#endif
-
-#ifdef FILE_SYSTEM_INTERFACE_RAM
- /* Assign RAMFS address value from xparameters.h */
- dataramfs = (char *)RAMFS_START_ADDR;
-
- /* Clearing No init Status for RAM */
- s &= (~STA_NOINIT);
- Stat[pdrv] = s;
-#endif
-
- return s;
-}
-
-
-/*-----------------------------------------------------------------------*/
-/* Read Sector(s) */
-/*-----------------------------------------------------------------------*/
-/*****************************************************************************/
-/**
-*
-* Reads the drive
-* In case of SD, it reads the SD card using ADMA2 in polled mode.
-*
-* @param pdrv - Drive number
-* @param *buff - Pointer to the data buffer to store read data
-* @param sector - Start sector number
-* @param count - Sector count
-*
-* @return
-* RES_OK Read successful
-* STA_NOINIT Drive not initialized
-* RES_ERROR Read not successful
-*
-* @note
-*
-******************************************************************************/
-DRESULT disk_read (
- BYTE pdrv, /* Physical drive number (0) */
- BYTE *buff, /* Pointer to the data buffer to store read data */
- DWORD sector, /* Start sector number (LBA) */
- UINT count /* Sector count (1..128) */
-)
-{
- DSTATUS s;
-#ifdef FILE_SYSTEM_INTERFACE_SD
- s32 Status = XST_FAILURE;
- DWORD LocSector = sector;
-#endif
-
- s = disk_status(pdrv);
-
- if ((s & STA_NOINIT) != 0U) {
- return RES_NOTRDY;
- }
- if (count == 0U) {
- return RES_PARERR;
- }
-
-#ifdef FILE_SYSTEM_INTERFACE_SD
- /* Convert LBA to byte address if needed */
- if ((SdInstance[pdrv].HCS) == 0U) {
- LocSector *= (DWORD)XSDPS_BLK_SIZE_512_MASK;
- }
-
- Status = XSdPs_ReadPolled(&SdInstance[pdrv], (u32)LocSector, count, buff);
- if (Status != XST_SUCCESS) {
- return RES_ERROR;
- }
-#endif
-
-#ifdef FILE_SYSTEM_INTERFACE_RAM
- memcpy(buff, dataramfs + (sector * SECTORSIZE), count * SECTORSIZE);
-#endif
-
-#if !defined(FILE_SYSTEM_INTERFACE_SD) && !defined(FILE_SYSTEM_INTERFACE_RAM)
- (void)buff;
- (void)sector;
-#endif
-
- return RES_OK;
-}
-
-/*-----------------------------------------------------------------------*/
-/* Miscellaneous Functions */
-/*-----------------------------------------------------------------------*/
-
-DRESULT disk_ioctl (
- BYTE pdrv, /* Physical drive number (0) */
- BYTE cmd, /* Control code */
- void *buff /* Buffer to send/receive control data */
-)
-{
- DRESULT res = RES_ERROR;
-
-#ifdef FILE_SYSTEM_INTERFACE_SD
- void *LocBuff = buff;
- if ((disk_status(pdrv) & STA_NOINIT) != 0U) { /* Check if card is in the socket */
- return RES_NOTRDY;
- }
-
- switch (cmd) {
- case (BYTE)CTRL_SYNC : /* Make sure that no pending write process */
- res = RES_OK;
- break;
-
- case (BYTE)GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */
- (*((DWORD *)(void *)LocBuff)) = (DWORD)SdInstance[pdrv].SectorCount;
- res = RES_OK;
- break;
-
- case (BYTE)GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */
- (*((DWORD *)((void *)LocBuff))) = ((DWORD)128);
- res = RES_OK;
- break;
-
- default:
- res = RES_PARERR;
- break;
- }
-#endif
-
-#ifdef FILE_SYSTEM_INTERFACE_RAM
- switch (cmd) {
- case (BYTE)CTRL_SYNC:
- res = RES_OK;
- break;
- case (BYTE)GET_BLOCK_SIZE:
- *(WORD *)buff = BLOCKSIZE;
- res = RES_OK;
- break;
- case (BYTE)GET_SECTOR_SIZE:
- *(WORD *)buff = SECTORSIZE;
- res = RES_OK;
- break;
- case (BYTE)GET_SECTOR_COUNT:
- *(DWORD *)buff = SECTORCNT;
- res = RES_OK;
- break;
- default:
- res = RES_PARERR;
- break;
- }
-
- (void)pdrv;
-#endif
-
-#if !defined(FILE_SYSTEM_INTERFACE_SD) && !defined(FILE_SYSTEM_INTERFACE_RAM)
- (void)pdrv;
- (void)cmd;
- (void)buff;
-#endif
-
- return res;
-}
-
-/******************************************************************************/
-/**
-*
-* This function is User Provided Timer Function for FatFs module
-*
-* @return DWORD
-*
-* @note None
-*
-****************************************************************************/
-
-DWORD get_fattime (void)
-{
- return ((DWORD)(2010U - 1980U) << 25U) /* Fixed to Jan. 1, 2010 */
- | ((DWORD)1 << 21)
- | ((DWORD)1 << 16)
- | ((DWORD)0 << 11)
- | ((DWORD)0 << 5)
- | ((DWORD)0 >> 1);
-}
-
-/*****************************************************************************/
-/**
-*
-* Reads the drive
-* In case of SD, it reads the SD card using ADMA2 in polled mode.
-*
-* @param pdrv - Drive number
-* @param *buff - Pointer to the data to be written
-* @param sector - Sector address
-* @param count - Sector count
-*
-* @return
-* RES_OK Read successful
-* STA_NOINIT Drive not initialized
-* RES_ERROR Read not successful
-*
-* @note
-*
-******************************************************************************/
-DRESULT disk_write (
- BYTE pdrv, /* Physical drive nmuber (0..) */
- const BYTE *buff, /* Data to be written */
- DWORD sector, /* Sector address (LBA) */
- UINT count /* Number of sectors to write (1..128) */
-)
-{
- DSTATUS s;
-#ifdef FILE_SYSTEM_INTERFACE_SD
- s32 Status = XST_FAILURE;
- DWORD LocSector = sector;
-#endif
-
- s = disk_status(pdrv);
- if ((s & STA_NOINIT) != 0U) {
- return RES_NOTRDY;
- }
- if (count == 0U) {
- return RES_PARERR;
- }
-
-#ifdef FILE_SYSTEM_INTERFACE_SD
- /* Convert LBA to byte address if needed */
- if ((SdInstance[pdrv].HCS) == 0U) {
- LocSector *= (DWORD)XSDPS_BLK_SIZE_512_MASK;
- }
-
- Status = XSdPs_WritePolled(&SdInstance[pdrv], (u32)LocSector, count, buff);
- if (Status != XST_SUCCESS) {
- return RES_ERROR;
- }
-
-#endif
-
-#ifdef FILE_SYSTEM_INTERFACE_RAM
- memcpy(dataramfs + (sector * SECTORSIZE), buff, count * SECTORSIZE);
-#endif
-
-#if !defined(FILE_SYSTEM_INTERFACE_SD) && !defined(FILE_SYSTEM_INTERFACE_RAM)
- (void)buff;
- (void)sector;
-#endif
-
- return RES_OK;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e7/b1c2ba575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e7/b1c2ba575243001d18b399c1eb9b3628
deleted file mode 100644
index 5feeb49..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e7/b1c2ba575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,39 +0,0 @@
-DRIVER_LIB_VERSION = 1.0
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I$(INCLUDEDIR)
-
-SRCFILES:=$(wildcard *.c)
-
-OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
-
-libs: $(OBJECTS)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf $(DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e8/11a13a585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e8/11a13a585243001d18b399c1eb9b3628
deleted file mode 100644
index f2d44ce..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e8/11a13a585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,28 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#ifndef UNDEFINE_FILE_OPS
-#include
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode);
-}
-#endif
-
-/*
- * _open -- open a file descriptor. We don't have a filesystem, so
- * we return an error.
- */
-__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode)
-{
- (void)buf;
- (void)flags;
- (void)mode;
- errno = EIO;
- return (-1);
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e8/529d25595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e8/529d25595243001d18b399c1eb9b3628
deleted file mode 100644
index 9be0b25..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e8/529d25595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,176 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file asm_vectors.S
-*
-* This file contains the initial vector table for the Cortex A9 processor
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 1.00a ecm/sdm 10/20/09 Initial version
-* 3.05a sdm 02/02/12 Save lr when profiling is enabled
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-* 4.00a pkp 22/01/14 Modified return addresses for interrupt
-* handlers (DataAbortHandler and SVCHandler)
-* to fix CR#767251
-* 5.1 pkp 05/13/15 Saved the addresses of instruction causing data
-* abort and prefetch abort into DataAbortAddr and
-* PrefetchAbortAddr for further use to fix CR#854523
-* 5.4 pkp 12/03/15 Added handler for undefined exception
-* 6.8 mus 04/27/18 Removed __ARM_NEON__ flag definition. Now,
-* saving/restoring of of HW floating point register
-* would be done through newly introduced flag
-* FPU_HARD_FLOAT_ABI_ENABLED. This new flag will be
-* configured based on the -mfpu-abi option in extra
-* compiler flags.
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#include "xil_errata.h"
-#include "bspconfig.h"
-
-.org 0
-.text
-
-.globl _vector_table
-
-.section .vectors
-_vector_table:
- B _boot
- B Undefined
- B SVCHandler
- B PrefetchAbortHandler
- B DataAbortHandler
- NOP /* Placeholder for address exception vector*/
- B IRQHandler
- B FIQHandler
-
-
-IRQHandler: /* IRQ vector handler */
-
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/
-#if FPU_HARD_FLOAT_ABI_ENABLED
- vpush {d0-d7}
- vpush {d16-d31}
- vmrs r1, FPSCR
- push {r1}
- vmrs r1, FPEXC
- push {r1}
-#endif
-
-#ifdef PROFILING
- ldr r2, =prof_pc
- subs r3, lr, #0
- str r3, [r2]
-#endif
-
- bl IRQInterrupt /* IRQ vector */
-
-#if FPU_HARD_FLOAT_ABI_ENABLED
- pop {r1}
- vmsr FPEXC, r1
- pop {r1}
- vmsr FPSCR, r1
- vpop {d16-d31}
- vpop {d0-d7}
-#endif
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
-
- subs pc, lr, #4 /* adjust return */
-
-
-FIQHandler: /* FIQ vector handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
-#if FPU_HARD_FLOAT_ABI_ENABLED
- vpush {d0-d7}
- vpush {d16-d31}
- vmrs r1, FPSCR
- push {r1}
- vmrs r1, FPEXC
- push {r1}
-#endif
-
-FIQLoop:
- bl FIQInterrupt /* FIQ vector */
-
-#if FPU_HARD_FLOAT_ABI_ENABLED
- pop {r1}
- vmsr FPEXC, r1
- pop {r1}
- vmsr FPSCR, r1
- vpop {d16-d31}
- vpop {d0-d7}
-#endif
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
- subs pc, lr, #4 /* adjust return */
-
-
-Undefined: /* Undefined handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- ldr r0, =UndefinedExceptionAddr
- sub r1, lr, #4
- str r1, [r0] /* Store address of instruction causing undefined exception */
-
- bl UndefinedException /* UndefinedException: call C function here */
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
- movs pc, lr
-
-SVCHandler: /* SWI handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
-
- tst r0, #0x20 /* check the T bit */
- ldrneh r0, [lr,#-2] /* Thumb mode */
- bicne r0, r0, #0xff00 /* Thumb mode */
- ldreq r0, [lr,#-4] /* ARM mode */
- biceq r0, r0, #0xff000000 /* ARM mode */
-
- bl SWInterrupt /* SWInterrupt: call C function here */
-
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
- movs pc, lr /*return to the next instruction after the SWI instruction */
-
-
-DataAbortHandler: /* Data Abort handler */
-#ifdef CONFIG_ARM_ERRATA_775420
- dsb
-#endif
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- ldr r0, =DataAbortAddr
- sub r1, lr, #8
- str r1, [r0] /* Stores instruction causing data abort */
-
- bl DataAbortInterrupt /*DataAbortInterrupt :call C function here */
-
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
- subs pc, lr, #8 /* points to the instruction that caused the Data Abort exception */
-
-PrefetchAbortHandler: /* Prefetch Abort handler */
-#ifdef CONFIG_ARM_ERRATA_775420
- dsb
-#endif
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- ldr r0, =PrefetchAbortAddr
- sub r1, lr, #4
- str r1, [r0] /* Stores instruction causing prefetch abort */
-
- bl PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */
-
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
- subs pc, lr, #4 /* points to the instruction that caused the Prefetch Abort exception */
-
-.end
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e8/90cd49565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e8/90cd49565243001d18b399c1eb9b3628
deleted file mode 100644
index 50df3c5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e8/90cd49565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,128 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_clocking.c
-*
-* The xil_clocking.c file contains clocking related functions and macros.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 7.2 sd 02/06/20 First release of clocking
-* 7.2 sd 03/20/20 Added checking for isolation case
-*
-*
-******************************************************************************/
-
-#include "xil_clocking.h"
-/************************** Variable Definitions *****************************/
-
-#if defined (XPAR_XCRPSU_0_DEVICE_ID) && defined (XCLOCKING)
-
-XClock ClockInstance; /* Instance of clock Controller */
-XClockPs_Config *ConfigPtr;
-
-
-XStatus Xil_ClockInit(void)
-{
- XStatus Status = XST_FAILURE;
-
- /* Lookup clock configurations */
- ConfigPtr = XClock_LookupConfig(XPAR_XCLOCKPS_DEVICE_ID);
-
- /* Initialize the Clock controller driver */
- Status = XClock_CfgInitialize(&ClockInstance, ConfigPtr);
- return Status;
-}
-
-XStatus Xil_ClockEnable(XClock_OutputClks ClockId)
-{
-
- XStatus Status = XST_FAILURE;
-
- Status = XClock_EnableClock(ClockId);
- return Status;
-}
-
-XStatus Xil_ClockDisable(XClock_OutputClks ClockId)
-{
- XStatus Status = XST_FAILURE;
-
- Status = XClock_DisableClock(ClockId);
- return Status;
-}
-
-XStatus Xil_ClockGetRate(XClock_OutputClks ClockId, XClockRate *Rate)
-{
- XStatus Status = XST_FAILURE;
-
- Xil_AssertNonvoid(Rate != NULL);
-
- Status = XClock_GetRate(ClockId, Rate);
- if (XST_SUCCESS == Status) {
- xdbg_printf(XDBG_DEBUG_GENERAL, "Operating rate = %lx\n",*Rate);
- } else {
- xdbg_printf(XDBG_DEBUG_ERROR, "Failed: Fetching rate\r\n");
- }
- return Status;
-}
-
-XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate,
- XClockRate *SetRate)
-{
- XStatus Status = XST_FAILURE;
-
- Xil_AssertNonvoid(SetRate != NULL);
-
- if (Rate == 0) {
- return XST_FAILURE;
- }
- Status = XClock_SetRate(ClockId, Rate, SetRate);
- if (XST_SUCCESS != Status) {
- xdbg_printf(XDBG_DEBUG_ERROR, "Failed Setting rate\n");
- }
- return Status;
-}
-
-#else
-XStatus Xil_ClockGetRate(XClock_OutputClks ClockId, XClockRate *Rate)
-{
- (void) ClockId;
- (void) Rate;
- return XST_FAILURE;
-}
-
-XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate,
- XClockRate *SetRate) {
- (void) ClockId;
- (void) Rate;
- (void) SetRate;
- return XST_FAILURE;
-}
-
-XStatus Xil_ClockInit(void)
-{
- return XST_SUCCESS;
-}
-
-XStatus Xil_ClockEnable(XClock_OutputClks ClockId)
-{
- (void) ClockId;
- return XST_SUCCESS;
-}
-
-XStatus Xil_ClockDisable(XClock_OutputClks ClockId)
-{
- (void) ClockId;
- return XST_SUCCESS;
-}
-
-#endif /* XCLOCKING */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e8/917085595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e8/917085595243001d18b399c1eb9b3628
deleted file mode 100644
index 92d7005..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e8/917085595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,356 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include "profile.h"
-#include "_profile_timer_hw.h"
-
-#include "xil_exception.h"
-
-#ifdef PROC_PPC
-#include "xtime_l.h"
-#include "xpseudo_asm.h"
-#endif
-
-#ifdef TIMER_CONNECT_INTC
-#include "xintc_l.h"
-#include "xintc.h"
-#endif /* TIMER_CONNECT_INTC */
-
-/* #ifndef PPC_PIT_INTERRUPT */
-#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
-#include "xtmrctr_l.h"
-#endif
-
-/* extern u32 timer_clk_ticks, */
-
-#ifdef PROC_PPC405
-#ifdef PPC_PIT_INTERRUPT
-s32 ppc_pit_init( void );
-#endif
-s32 powerpc405_init()
-#endif /* PROC_CORTEXA9 */
-
-#ifdef PROC_PPC440
-#ifdef PPC_PIT_INTERRUPT
-s32 ppc_dec_init( void );
-#endif
-s32 powerpc405_init(void);
-#endif /* PROC_PPC440 */
-
-#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
-s32 opb_timer_init( void );
-#endif
-
-#ifdef PROC_MICROBLAZE
-s32 microblaze_init(void);
-#endif /* PROC_MICROBLAZE */
-
-#ifdef PROC_CORTEXA9
-s32 scu_timer_init( void );
-s32 cortexa9_init(void);
-#endif /* PROC_CORTEXA9 */
-
-
-/*--------------------------------------------------------------------
- * PowerPC Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_PPC405
-
-
-/*--------------------------------------------------------------------
-* PowerPC PIT Timer Init.
-* Defined only if PIT Timer is used for Profiling
-*
-*-------------------------------------------------------------------- */
-#ifdef PPC_PIT_INTERRUPT
-int ppc_pit_init( void )
-{
- /* 1. Register Profile_intr_handler as Interrupt handler */
- /* 2. Set PIT Timer Interrupt and Enable it. */
- Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_PIT_INT,
- (Xil_ExceptionHandler)profile_intr_handler,NULL);
- XTime_PITSetInterval( timer_clk_ticks ) ;
- XTime_PITEnableAutoReload() ;
- return 0;
-}
-#endif
-
-
-/* --------------------------------------------------------------------
-* PowerPC Timer Initialization functions.
-* For PowerPC, PIT and opb_timer can be used for Profiling. This
-* is selected by the user in standalone BSP
-*
-*-------------------------------------------------------------------- */
-s32 powerpc405_init()
-{
- Xil_ExceptionInit() ;
- Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
-
- /* Initialize the Timer.
- * 1. If PowerPC PIT Timer has to be used, initialize PIT timer.
- * 2. Else use opb_timer. It can be directly connected or through intc to PowerPC */
-#ifdef PPC_PIT_INTERRUPT
- ppc_pit_init();
-#else
-#ifdef TIMER_CONNECT_INTC
- Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
- (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
- XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
- (XInterruptHandler)profile_intr_handler,NULL);
-#else
- Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
- (Xil_ExceptionHandler)profile_intr_handler,NULL);
-#endif
- /* Initialize the timer with Timer Ticks */
- opb_timer_init() ;
-#endif
-
- /* Enable Interrupts in the System, if Profile Timer is the only Interrupt
- * in the System. */
-#ifdef ENABLE_SYS_INTR
-#ifdef PPC_PIT_INTERRUPT
- XTime_PITEnableInterrupt() ;
-#elif TIMER_CONNECT_INTC
- XIntc_MasterEnable( INTC_BASEADDR );
- XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
- XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
-#endif
- Xil_ExceptionEnableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
-#endif
- return 0;
-}
-
-#endif /* PROC_PPC */
-
-
-
-/*--------------------------------------------------------------------
- * PowerPC440 Target - Timer related functions
- * -------------------------------------------------------------------- */
-#ifdef PROC_PPC440
-
-
-/*--------------------------------------------------------------------
- * PowerPC DEC Timer Init.
- * Defined only if DEC Timer is used for Profiling
- *
- *-------------------------------------------------------------------- */
-#ifdef PPC_PIT_INTERRUPT
-s32 ppc_dec_init( void )
-{
- /* 1. Register Profile_intr_handler as Interrupt handler */
- /* 2. Set DEC Timer Interrupt and Enable it. */
- Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_DEC_INT,
- (Xil_ExceptionHandler)profile_intr_handler,NULL);
- XTime_DECSetInterval( timer_clk_ticks ) ;
- XTime_DECEnableAutoReload() ;
- return 0;
-}
-#endif
-
-
-/*--------------------------------------------------------------------
- * PowerPC Timer Initialization functions.
- * For PowerPC, DEC and opb_timer can be used for Profiling. This
- * is selected by the user in standalone BSP
- *
- *-------------------------------------------------------------------- */
-s32 powerpc405_init(void)
-{
- Xil_ExceptionInit();
- Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
-
- /* Initialize the Timer.
- * 1. If PowerPC DEC Timer has to be used, initialize DEC timer.
- * 2. Else use opb_timer. It can be directly connected or through intc to PowerPC */
-#ifdef PPC_PIT_INTERRUPT
- ppc_dec_init();
-#else
-#ifdef TIMER_CONNECT_INTC
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT,
- (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
-
- XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
- (XInterruptHandler)profile_intr_handler,NULL);
-#else
- Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
- (Xil_ExceptionHandler)profile_intr_handler,NULL);
- Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
- (Xil_ExceptionHandler)profile_intr_handler,NULL);
-#endif
- /* Initialize the timer with Timer Ticks */
- opb_timer_init() ;
-#endif
-
- /* Enable Interrupts in the System, if Profile Timer is the only Interrupt
- * in the System. */
-#ifdef ENABLE_SYS_INTR
-#ifdef PPC_PIT_INTERRUPT
- XTime_DECEnableInterrupt() ;
-#elif TIMER_CONNECT_INTC
- XIntc_MasterEnable( INTC_BASEADDR );
- XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
- XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
-#endif
- Xil_ExceptionEnableMask( XEXC_NON_CRITICAL ) ;
-#endif
- return 0;
-}
-
-#endif /* PROC_PPC440 */
-
-/* --------------------------------------------------------------------
- * opb_timer Initialization for PowerPC and MicroBlaze. This function
- * is not needed if DEC timer is used in PowerPC
- *
- *-------------------------------------------------------------------- */
-/* #ifndef PPC_PIT_INTERRUPT */
-#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
-s32 opb_timer_init( void )
-{
- /* set the number of cycles the timer counts before interrupting */
- XTmrCtr_SetLoadReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)timer_clk_ticks);
-
- /* reset the timers, and clear interrupts */
- XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0,
- (u32)XTC_CSR_INT_OCCURED_MASK | (u32)XTC_CSR_LOAD_MASK );
-
- /* start the timers */
- XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)XTC_CSR_ENABLE_TMR_MASK
- | (u32)XTC_CSR_ENABLE_INT_MASK | (u32)XTC_CSR_AUTO_RELOAD_MASK | (u32)XTC_CSR_DOWN_COUNT_MASK);
- return 0;
-}
-#endif
-
-
-/*--------------------------------------------------------------------
- * MicroBlaze Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_MICROBLAZE
-
-/* --------------------------------------------------------------------
- * Initialize the Profile Timer for MicroBlaze Target.
- * For MicroBlaze, opb_timer is used. The opb_timer can be directly
- * connected to MicroBlaze or connected through Interrupt Controller.
- *
- *-------------------------------------------------------------------- */
-s32 microblaze_init(void)
-{
- /* Register profile_intr_handler
- * 1. If timer is connected to Interrupt Controller, register the handler
- * to Interrupt Controllers vector table.
- * 2. If timer is directly connected to MicroBlaze, register the handler
- * as Interrupt handler */
- Xil_ExceptionInit();
-
-#ifdef TIMER_CONNECT_INTC
- XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
- (XInterruptHandler)profile_intr_handler,NULL);
-#else
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
- (Xil_ExceptionHandler)profile_intr_handler,
- NULL) ;
-#endif
-
- /* Initialize the timer with Timer Ticks */
- (void)opb_timer_init() ;
-
- /* Enable Interrupts in the System, if Profile Timer is the only Interrupt
- * in the System. */
-#ifdef ENABLE_SYS_INTR
-#ifdef TIMER_CONNECT_INTC
- XIntc_MasterEnable((u32)INTC_BASEADDR );
- XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
- XIntc_EnableIntr( (u32)INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
- (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
-#endif
-
-#endif
-
- Xil_ExceptionEnable();
-
- return 0;
-
-}
-
-#endif /* PROC_MICROBLAZE */
-
-
-
-/* --------------------------------------------------------------------
- * Cortex A9 Target - Timer related functions
- *-------------------------------------------------------------------- */
-#ifdef PROC_CORTEXA9
-
-/* --------------------------------------------------------------------
- * Initialize the Profile Timer for Cortex A9 Target.
- * The scu private timer is connected to the Scu GIC controller.
- *
- *-------------------------------------------------------------------- */
-s32 scu_timer_init( void )
-{
- /* set the number of cycles the timer counts before interrupting
- * scu timer runs at half the cpu clock */
- XScuTimer_SetLoadReg(PROFILE_TIMER_BASEADDR, timer_clk_ticks/2U);
-
- /* clear any pending interrupts */
- XScuTimer_SetIntrReg(PROFILE_TIMER_BASEADDR, 1U);
-
- /* enable interrupts, auto-reload mode and start the timer */
- XScuTimer_SetControlReg(PROFILE_TIMER_BASEADDR, XSCUTIMER_CONTROL_IRQ_ENABLE_MASK |
- XSCUTIMER_CONTROL_AUTO_RELOAD_MASK | XSCUTIMER_CONTROL_ENABLE_MASK);
-
- return 0;
-}
-
-s32 cortexa9_init(void)
-{
-
- Xil_ExceptionInit();
-
- XScuGic_DeviceInitialize(0);
-
- /*
- * Connect the interrupt controller interrupt handler to the hardware
- * interrupt handling logic in the processor.
- */
- Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
- (Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler,
- NULL);
-
- /*
- * Connect the device driver handler that will be called when an
- * interrupt for the device occurs, the handler defined above performs
- * the specific interrupt processing for the device.
- */
- XScuGic_RegisterHandler(SCUGIC_CPU_BASEADDR,
- PROFILE_TIMER_INTR_ID,
- (Xil_ExceptionHandler)profile_intr_handler,
- NULL);
-
- /*
- * Enable the interrupt for scu timer.
- */
- XScuGic_EnableIntr(SCUGIC_DIST_BASEADDR, PROFILE_TIMER_INTR_ID);
-
- /*
- * Enable interrupts in the Processor.
- */
- Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
-
- /*
- * Initialize the timer with Timer Ticks
- */
- (void)scu_timer_init() ;
-
- Xil_ExceptionEnable();
-
- return 0;
-}
-
-#endif /* PROC_CORTEXA9 */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e9/303b58585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e9/303b58585243001d18b399c1eb9b3628
deleted file mode 100644
index 150a298..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e9/303b58585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,408 +0,0 @@
-;/******************************************************************************
-;* Copyright (c) 2019 - 2021 Xilinx, Inc. All rights reserved.
-;* SPDX-License-Identifier: MIT
-;******************************************************************************/
-;/*****************************************************************************/
-;/**
-;* @file boot.S
-;*
-;* @addtogroup a53_64_boot_code Cortex A53 64bit Processor Boot Code
-;* @{
-;*
boot.S
-;*
-;* The boot code performs minimum configuration which is required for an
-;* application. Cortex-A53 starts by checking current exception level. If the
-;* current exception level is EL3 and BSP is built for EL3, it will do
-;* initialization required for application execution at EL3. Below is a
-;* sequence illustrating what all configuration is performed before control
-;* reaches to main function for EL3 execution.
-;*
-;* 1. Program vector table base for exception handling
-;* 2. Set reset vector table base address
-;* 3. Program stack pointer for EL3
-;* 4. Routing of interrupts to EL3
-;* 5. Enable ECC protection
-;* 6. Program generic counter frequency
-;* 7. Invalidate instruction cache, data cache and TLBs
-;* 8. Configure MMU registers and program base address of translation table
-;* 9. Transfer control to _start which clears BSS sections and runs global
-;* constructor before jumping to main application
-;*
-;* If current exception level is EL1 and BSP is also built for EL1_NONSECURE
-;* it will perform initialization required for application execution at EL1
-;* non-secure. For all other combination, the execution will go into infinite
-;* loop. Below is a sequence illustrating what all configuration is performed
-;* before control reaches to main function for EL1 execution.
-;*
-;* 1. Program vector table base for exception handling
-;* 2. Program stack pointer for EL1
-;* 3. Invalidate instruction cache, data cache and TLBs
-;* 4. Configure MMU registers and program base address of translation table
-;* 5. Transfer control to _start which clears BSS sections and runs global
-;* constructor before jumping to main application
-;*
-;*
-;* MODIFICATION HISTORY:
-;*
-;* Ver Who Date Changes
-;* ----- ------- -------- ---------------------------------------------------
-;* 7.0 mus 02/26/19 First release
-;* 7.2 mus 01/08/19 Added support for versal
-;* sd 02/23/20 Clock Init is called
-;* sd 03/21/20 Added XCLOCKING flag
-;*
-;******************************************************************************/
-
-#include "xparameters.h"
-#include "bspconfig.h"
-#include "xil_errata.h"
-
- EXPORT _prestart
- EXPORT _boot
-
- IMPORT MMUTableL0
- IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base|
- IMPORT _vector_table
- IMPORT __main
-#ifdef XCLOCKING
- IMPORT Xil_ClockInit
-#endif
-
-#ifndef FREERTOS_BSP
- IMPORT FPUStatus
-#endif
-
-rvbar_base EQU 0xFD5C0040
-MODE_EL1 EQU 0x5
-DAIF_BIT EQU 0x1C0
-TT_S1_FAULT EQU 0x0
-TT_S1_TABLE EQU 0x3
-
- AREA |.boot|, CODE
-
-; This initializes the various processor modes
-
-_prestart
-_boot
- mov x0, #0
- mov x1, #0
- mov x2, #0
- mov x3, #0
- mov x4, #0
- mov x5, #0
- mov x6, #0
- mov x7, #0
- mov x8, #0
- mov x9, #0
- mov x10, #0
- mov x11, #0
- mov x12, #0
- mov x13, #0
- mov x14, #0
- mov x15, #0
- mov x16, #0
- mov x17, #0
- mov x18, #0
- mov x19, #0
- mov x20, #0
- mov x21, #0
- mov x22, #0
- mov x23, #0
- mov x24, #0
- mov x25, #0
- mov x26, #0
- mov x27, #0
- mov x28, #0
- mov x29, #0
- mov x30, #0
-
-OKToRun
- mrs x0, currentEL
- cmp x0, #0xC
- beq InitEL3
- cmp x0, #0x4
- beq InitEL1
- b error ; Go to error if current exception level is neither EL3 nor EL1
-
-
-InitEL3
-#if (EL3 == 1)
- ldr x1, =_vector_table ; Set vector table base address
- msr VBAR_EL3, x1
- mrs x0, MPIDR_EL1 ; Get the CPU ID
- and x0, x0, #0xFF
- mov w0, w0
- ldr w2, =rvbar_base ; Calculate the rvbar base address for particular CPU core
- mov w3, #0x8
- mul w0, w0, w3
- add w2, w2, w0
- str x1, [x2] ; Store vector base address to rvbar
- ldr x2, =|Image$$ARM_LIB_STACK$$ZI$$Base| ; Define stack pointer for current exception level
- mov sp, x2
-
- mov x0, #0 ; Enable Trapping of SIMD/FPU register for standalone BSP
-#ifndef FREERTOS_BSP
- orr x0, x0, #(0x1 << 10)
-#endif
- msr CPTR_EL3, x0
- isb
-
-;
-; Clear FPUStatus variable to make sure that it contains current
-; status of FPU i.e. disabled. In case of a warm restart execution
-; when bss sections are not cleared, it may contain previously updated
-; value which does not hold true now
-;
-#ifndef FREERTOS_BSP
- ldr x0, =FPUStatus
- str xzr, [x0]
-#endif
-
-; Configure SCR_EL3
- mov w1, #0 ; Initial value of register is unknown
- orr w1, w1, #(1 << 11) ; Set ST bit (Secure EL1 can access CNTPS_TVAL_EL1, CNTPS_CTL_EL1 & CNTPS_CVAL_EL1)
- orr w1, w1, #(1 << 10) ; Set RW bit (EL1 is AArch64, as this is the Secure world)
- orr w1, w1, #(1 << 3) ; Set EA bit (SError routed to EL3)
- orr w1, w1, #(1 << 2) ; Set FIQ bit (FIQs routed to EL3)
- orr w1, w1, #(1 << 1) ; Set IRQ bit (IRQs routed to EL3)
- msr SCR_EL3, x1
-
-; Configure cpu auxiliary control register EL1
- ldr x0, =0x80CA000 ; L1 Data prefetch control - 5, Enable device split throttle, 2 independent data prefetch streams
-#if (CONFIG_ARM_ERRATA_855873)
-;
-; Set ENDCCASCI bit in CPUACTLR_EL1 register, to execute data
-; cache clean operations as data cache clean and invalidate
-;
- orr x0, x0, #(1 << 44) ; Set ENDCCASCI bit
-#endif
- msr S3_1_C15_C2_0, x0 ; CPUACTLR_EL1
-
-; Program the counter frequency
-#if defined (versal)
- ldr x0, =XPAR_CPU_CORTEXA72_0_TIMESTAMP_CLK_FREQ
-#else
- ldr x0, =XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ
- msr CNTFRQ_EL0, x0
-#endif
-
-; Enable hardware coherency between cores
- mrs x0, S3_1_c15_c2_1 ; Read EL1 CPU Extended Control Register
- orr x0, x0, #(1 << 6) ; Set the SMPEN bit
- msr S3_1_c15_c2_1, x0 ; Write EL1 CPU Extended Control Register
- isb
-
- tlbi ALLE3
- ic IALLU ; Invalidate I cache to PoU
- bl invalidate_dcaches
- dsb sy
- isb
-
- ldr x1, =MMUTableL0 ; Get address of level 0 for TTBR0_EL3
- msr TTBR0_EL3, x1 ; Set TTBR0_EL3
-
-;
-; Set up memory attributes
-; This equates to:
-; 0 = b01000100 = Normal, Inner/Outer Non-Cacheable
-; 1 = b11111111 = Normal, Inner/Outer WB/WA/RA
-; 2 = b00000000 = Device-nGnRnE
-; 3 = b00000100 = Device-nGnRE
-; 4 = b10111011 = Normal, Inner/Outer WT/WA/RA
-;
- ldr x1, =0x000000BB0400FF44
- msr MAIR_EL3, x1
-#if defined (versal)
-; Set up TCR_EL3
-; Physical Address Size PS = 100 -> 44bits 16 TB
-; Granual Size TG0 = 00 -> 4KB
-; size offset of the memory region T0SZ = 20 -> (region size 2^(64-20) = 2^44)
- ldr x1,=0x80843514
-#else
-;
-; Set up TCR_EL3
-; Physical Address Size PS = 010 -> 40bits 1TB
-; Granule Size TG0 = 00 -> 4KB
-; Size offset of the memory region T0SZ = 24 -> (region size 2^(64-24) = 2^40)
-;
- ldr x1, =0x80823518
-#endif
- msr TCR_EL3, x1
- isb
-
-
-; Enable SError Exception for asynchronous abort
- mrs x1, DAIF
- mov x2, #(0x1<<8)
- bic x1, x1, x2
- msr DAIF, x1
-
-
-; Configure SCTLR_EL3
- mov x1, #0 ; Most of the SCTLR_EL3 bits are unknown at reset
- orr x1, x1, #(1 << 12) ; Enable I cache
- orr x1, x1, #(1 << 3) ; Enable SP alignment check
- orr x1, x1, #(1 << 2) ; Enable caches
- orr x1, x1, #(1 << 0) ; Enable MMU
- msr SCTLR_EL3, x1
- dsb sy
- isb
-
-#ifdef XCLOCKING
- b Xil_Clockinit
-#endif
- b __main ; Jump to start
-
-#else
- b error ; Present exception level and selected exception level mismatch
-
-#endif
-
-InitEL1
-#if (EL1_NONSECURE == 1)
- ldr x1, =_vector_table ; Set vector table base address
-
- msr VBAR_EL1, x1
- mrs x0, CPACR_EL1
- mov x2, #(0x3 << 0x20)
- bic x0, x0, x2
- msr CPACR_EL1, x0
- isb
-
-;
-; Clear FPUStatus variable to make sure that it contains current
-; status of FPU i.e. disabled. In case of a warm restart execution
-; when bss sections are not cleared, it may contain previously updated
-; value which does not hold true now
-;
-#ifndef FREERTOS_BSP
- ldr x0, =FPUStatus
- str xzr, [x0]
-#endif
- ldr x2, =|Image$$ARM_LIB_STACK$$ZI$$Base| ; Define stack pointer for current exception level
- mov sp, x2
-
-; Disable MMU
- mov x1, #0x0
- msr SCTLR_EL1, x1
- isb
-
- TLBI VMALLE1
- ic IALLU ; Invalidate I cache to PoU
- bl invalidate_dcaches
- dsb sy
- isb
-
- ldr x1, =MMUTableL0 ; Get address of level 0 for TTBR0_EL1
- msr TTBR0_EL1, x1 ; Set TTBR0_EL1
-
-;
-; Set up memory attributes
-; This equates to:
-; 0 = b01000100 = Normal, Inner/Outer Non-Cacheable
-; 1 = b11111111 = Normal, Inner/Outer WB/WA/RA
-; 2 = b00000000 = Device-nGnRnE
-; 3 = b00000100 = Device-nGnRE
-; 4 = b10111011 = Normal, Inner/Outer WT/WA/RA
-;
- ldr x1, =0x000000BB0400FF44
- msr MAIR_EL1, x1
-
-#if defined (versal)
-;
-; Set up TCR_EL1
-; Physical Address Size PS = 100 -> 44bits 16TB
-; Granual Size TG0 = 00 -> 4KB
-; size offset of the memory region T0SZ = 20 -> (region size 2^(64-20) = 2^44)
-;
- ldr x1,=0x485800514
-#else
-;
-; Set up TCR_EL1
-; Physical Address Size PS = 010 -> 40bits 1TB
-; Granule Size TG0 = 00 -> 4KB
-; Size offset of the memory region T0SZ = 24 -> (region size 2^(64-24) = 2^40)
-;
- ldr x1, =0x285800518
-#endif
- msr TCR_EL1, x1
- isb
-
-
-; Enable SError Exception for asynchronous abort
- mrs x1,DAIF
- mov x2, #(0x1<<8)
- bic x1,x1,x2
- msr DAIF,x1
-
-
-; Enable MMU
- mov x1,#0x0
- orr x1, x1, #(1 << 18) ; Set WFE non trapping
- orr x1, x1, #(1 << 17) ; Set WFI non trapping
- orr x1, x1, #(1 << 5) ; Set CP15 barrier enabled
- orr x1, x1, #(1 << 12) ; Set I bit
- orr x1, x1, #(1 << 2) ; Set C bit
- orr x1, x1, #(1 << 0) ; Set M bit
- msr SCTLR_EL1, x1
- isb
-
- bl __main ; Jump to start
-#else
- b error ; present exception level and selected exception level mismatch
-#endif
-
-error
- b error
-
-invalidate_dcaches
- dmb ISH
- mrs x0, CLIDR_EL1 ; x0 = CLIDR
- ubfx w2, w0, #24, #3 ; w2 = CLIDR>Loc
- cmp w2, #0 ; LoC is 0?
- b.eq invalidateCaches_end ; No cleaning required and enable MMU
- mov w1, #0 ; w1 = level iterator
-
-invalidateCaches_flush_level
- add w3, w1, w1, lsl #1 ; w3 = w1 * 3 (right-shift for cache type)
- lsr w3, w0, w3 ; w3 = w0 >> w3
- ubfx w3, w3, #0, #3 ; w3 = cache type of this level
- cmp w3, #2 ; No cache at this level?
- b.lt invalidateCaches_next_level
- lsl w4, w1, #1
- msr CSSELR_EL1, x4 ; Select current cache level in CSSELR
- isb ; ISB required to reflect new CSIDR
- mrs x4, CCSIDR_EL1 ; w4 = CSIDR
- ubfx w3, w4, #0, #3
- add w3, w3, #2 ; w3 = log2(line size)
- ubfx w5, w4, #13, #15
- ubfx w4, w4, #3, #10 ; w4 = Way number
- clz w6, w4 ; w6 = 32 - log2(number of ways)
-
-invalidateCaches_flush_set
- mov w8, w4 ; w8 = Way number
-
-invalidateCaches_flush_way
- lsl w7, w1, #1 ; Fill level field
- lsl w9, w5, w3
- orr w7, w7, w9 ; Fill index field
- lsl w9, w8, w6
- orr w7, w7, w9 ; Fill way field
- dc CISW, x7 ; Invalidate by set/way to point of coherency
- subs w8, w8, #1 ; Decrement way
- b.ge invalidateCaches_flush_way
- subs w5, w5, #1 ; Decrement set
- b.ge invalidateCaches_flush_set
-
-invalidateCaches_next_level
- add w1, w1, #1 ; Next level
- cmp w2, w1
- b.gt invalidateCaches_flush_level
-
-invalidateCaches_end
- ret
-
- END
-;
-; @} End of "addtogroup a53_64_boot_code"
-;
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e9/40e7b6565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e9/40e7b6565243001d18b399c1eb9b3628
deleted file mode 100644
index b248e6a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e9/40e7b6565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,27 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#ifndef UNDEFINE_FILE_OPS
-#include
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode);
-}
-#endif
-/*
- * open -- open a file descriptor. We don't have a filesystem, so
- * we return an error.
- */
-__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode)
-{
- (void)buf;
- (void)flags;
- (void)mode;
- errno = EIO;
- return (-1);
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e9/7106dd595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e9/7106dd595243001d18b399c1eb9b3628
deleted file mode 100644
index 980f394..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e9/7106dd595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,571 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xadcps.h
-* @addtogroup xadcps_v2_6
-* @{
-* @details
-*
-* The XAdcPs driver supports the Xilinx XADC/ADC device.
-*
-* The XADC/ADC device has the following features:
-* - 10-bit, 200-KSPS (kilo samples per second)
-* Analog-to-Digital Converter (ADC)
-* - Monitoring of on-chip supply voltages and temperature
-* - 1 dedicated differential analog-input pair and
-* 16 auxiliary differential analog-input pairs
-* - Automatic alarms based on user defined limits for the on-chip
-* supply voltages and temperature
-* - Automatic Channel Sequencer, programmable averaging, programmable
-* acquisition time for the external inputs, unipolar or differential
-* input selection for the external inputs
-* - Inbuilt Calibration
-* - Optional interrupt request generation
-*
-*
-* The user should refer to the hardware device specification for detailed
-* information about the device.
-*
-* This header file contains the prototypes of driver functions that can
-* be used to access the XADC/ADC device.
-*
-*
-* XADC Channel Sequencer Modes
-*
-* The XADC Channel Sequencer supports the following operating modes:
-*
-* - Default : This is the default mode after power up.
-* In this mode of operation the XADC operates in
-* a sequence mode, monitoring the on chip sensors:
-* Temperature, VCCINT, and VCCAUX.
-* - One pass through sequence : In this mode the XADC
-* converts the channels enabled in the Sequencer Channel Enable
-* registers for a single pass and then stops.
-* - Continuous cycling of sequence : In this mode the XADC
-* converts the channels enabled in the Sequencer Channel Enable
-* registers continuously.
-* - Single channel mode: In this mode the XADC Channel
-* Sequencer is disabled and the XADC operates in a
-* Single Channel Mode.
-* The XADC can operate either in a Continuous or Event
-* driven sampling mode in the single channel mode.
-* - Simultaneous Sampling Mode: In this mode the XADC Channel
-* Sequencer will automatically sequence through eight fixed pairs
-* of auxiliary analog input channels for simulataneous conversion.
-* - Independent ADC mode: In this mode the first ADC (A) is used to
-* is used to implement a fixed monitoring mode similar to the
-* default mode but the alarm fucntions ar eenabled.
-* The second ADC (B) is available to be used with external analog
-* input channels only.
-*
-* Read the XADC spec for more information about the sequencer modes.
-*
-* Initialization and Configuration
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate to the XADC/ADC device.
-*
-* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC
-* device. The user needs to first call the XAdcPs_LookupConfig() API which
-* returns the Configuration structure pointer which is passed as a parameter to
-* the XAdcPs_CfgInitialize() API.
-*
-*
-* Interrupts
-*
-* The XADC/ADC device supports interrupt driven mode and the default
-* operation mode is polling mode.
-*
-* The interrupt mode is available only if hardware is configured to support
-* interrupts.
-*
-* This driver does not provide a Interrupt Service Routine (ISR) for the device.
-* It is the responsibility of the application to provide one if needed. Refer to
-* the interrupt example provided with this driver for details on using the
-* device in interrupt mode.
-*
-*
-* Virtual Memory
-*
-* This driver supports Virtual Memory. The RTOS is responsible for calculating
-* the correct device base address in Virtual Memory space.
-*
-*
-* Threads
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-*
-* Asserts
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-*
-* Building the driver
-*
-* The XAdcPs driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-* Limitations of the driver
-*
-* XADC/ADC device can be accessed through the JTAG port and the PLB
-* interface. The driver implementation does not support the simultaneous access
-* of the device by both these interfaces. The user has to care of this situation
-* in the user application code.
-*
-*
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
-* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
-* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
-* in xadcps.c to fix CR #693371
-* 1.03a bss 11/01/13 Modified xadcps_hw.h to use correct Register offsets
-* CR#749687
-* 2.1 bss 08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
-* XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
-* XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
-* functions.
-* Modified Assert for XAdcPs_SetSingleChParams in
-* xadcps.c to fix CR #807563.
-* 2.2 bss 04/27/14 Modified to use correct Device Config base address in
-* xadcps.c (CR#854437).
-* ms 01/23/17 Added xil_printf statement in main function for all
-* examples to ensure that "Successfully ran" and "Failed"
-* strings are available in all examples. This is a fix
-* for CR-965028.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/05/17 Modified Comment lines in functions of xadcps
-* examples to recognize it as documentation block
-* for doxygen generation.
-* 2.3 mn 07/09/18 Fix Doxygen warning
-* 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors.
-* aad 12/17/20 Added missing function declarations and removed
-* functions with no definitions.
-*
-*
-*
-*****************************************************************************/
-#ifndef XADCPS_H /* Prevent circular inclusions */
-#define XADCPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xstatus.h"
-#include "xadcps_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/**
- * @name Indexes for the different channels.
- * @{
- */
-#define XADCPS_CH_TEMP 0x0U /**< On Chip Temperature */
-#define XADCPS_CH_VCCINT 0x1U /**< VCCINT */
-#define XADCPS_CH_VCCAUX 0x2U /**< VCCAUX */
-#define XADCPS_CH_VPVN 0x3U /**< VP/VN Dedicated analog inputs */
-#define XADCPS_CH_VREFP 0x4U /**< VREFP */
-#define XADCPS_CH_VREFN 0x5U /**< VREFN */
-#define XADCPS_CH_VBRAM 0x6U /**< On-chip VBRAM Data Reg, 7 series */
-#define XADCPS_CH_SUPPLY_CALIB 0x07U /**< Supply Calib Data Reg */
-#define XADCPS_CH_ADC_CALIB 0x08U /**< ADC Offset Channel Reg */
-#define XADCPS_CH_GAINERR_CALIB 0x09U /**< Gain Error Channel Reg */
-#define XADCPS_CH_VCCPINT 0x0DU /**< On-chip PS VCCPINT Channel , Zynq */
-#define XADCPS_CH_VCCPAUX 0x0EU /**< On-chip PS VCCPAUX Channel , Zynq */
-#define XADCPS_CH_VCCPDRO 0x0FU /**< On-chip PS VCCPDRO Channel , Zynq */
-#define XADCPS_CH_AUX_MIN 16U /**< Channel number for 1st Aux Channel */
-#define XADCPS_CH_AUX_MAX 31U /**< Channel number for Last Aux channel */
-
-/*@}*/
-
-
-/**
- * @name Indexes for reading the Calibration Coefficient Data.
- * @{
- */
-#define XADCPS_CALIB_SUPPLY_COEFF 0U /**< Supply Offset Calib Coefficient */
-#define XADCPS_CALIB_ADC_COEFF 1U /**< ADC Offset Calib Coefficient */
-#define XADCPS_CALIB_GAIN_ERROR_COEFF 2U /**< Gain Error Calib Coefficient*/
-/*@}*/
-
-
-/**
- * @name Indexes for reading the Minimum/Maximum Measurement Data.
- * @{
- */
-#define XADCPS_MAX_TEMP 0U /**< Maximum Temperature Data */
-#define XADCPS_MAX_VCCINT 1U /**< Maximum VCCINT Data */
-#define XADCPS_MAX_VCCAUX 2U /**< Maximum VCCAUX Data */
-#define XADCPS_MAX_VBRAM 3U /**< Maximum VBRAM Data */
-#define XADCPS_MIN_TEMP 4U /**< Minimum Temperature Data */
-#define XADCPS_MIN_VCCINT 5U /**< Minimum VCCINT Data */
-#define XADCPS_MIN_VCCAUX 6U /**< Minimum VCCAUX Data */
-#define XADCPS_MIN_VBRAM 7U /**< Minimum VBRAM Data */
-#define XADCPS_MAX_VCCPINT 8U /**< Maximum VCCPINT Register , Zynq */
-#define XADCPS_MAX_VCCPAUX 9U /**< Maximum VCCPAUX Register , Zynq */
-#define XADCPS_MAX_VCCPDRO 0xAU /**< Maximum VCCPDRO Register , Zynq */
-#define XADCPS_MIN_VCCPINT 0xCU /**< Minimum VCCPINT Register , Zynq */
-#define XADCPS_MIN_VCCPAUX 0xDU /**< Minimum VCCPAUX Register , Zynq */
-#define XADCPS_MIN_VCCPDRO 0xEU /**< Minimum VCCPDRO Register , Zynq */
-
-/*@}*/
-
-
-/**
- * @name Alarm Threshold(Limit) Register (ATR) indexes.
- * @{
- */
-#define XADCPS_ATR_TEMP_UPPER 0U /**< High user Temperature */
-#define XADCPS_ATR_VCCINT_UPPER 1U /**< VCCINT high voltage limit register */
-#define XADCPS_ATR_VCCAUX_UPPER 2U /**< VCCAUX high voltage limit register */
-#define XADCPS_ATR_OT_UPPER 3U /**< VCCAUX high voltage limit register */
-#define XADCPS_ATR_TEMP_LOWER 4U /**< Upper Over Temperature limit Reg */
-#define XADCPS_ATR_VCCINT_LOWER 5U /**< VCCINT high voltage limit register */
-#define XADCPS_ATR_VCCAUX_LOWER 6U /**< VCCAUX low voltage limit register */
-#define XADCPS_ATR_OT_LOWER 7U /**< Lower Over Temperature limit */
-#define XADCPS_ATR_VBRAM_UPPER_ 8U /**< VRBAM Upper Alarm Reg, 7 Series */
-#define XADCPS_ATR_VCCPINT_UPPER 9U /**< VCCPINT Upper Alarm Reg, Zynq */
-#define XADCPS_ATR_VCCPAUX_UPPER 0xAU /**< VCCPAUX Upper Alarm Reg, Zynq */
-#define XADCPS_ATR_VCCPDRO_UPPER 0xBU /**< VCCPDRO Upper Alarm Reg, Zynq */
-#define XADCPS_ATR_VBRAM_LOWER 0xCU /**< VRBAM Lower Alarm Reg, 7 Series */
-#define XADCPS_ATR_VCCPINT_LOWER 0xDU /**< VCCPINT Lower Alarm Reg , Zynq */
-#define XADCPS_ATR_VCCPAUX_LOWER 0xEU /**< VCCPAUX Lower Alarm Reg , Zynq */
-#define XADCPS_ATR_VCCPDRO_LOWER 0xFU /**< VCCPDRO Lower Alarm Reg , Zynq */
-
-/*@}*/
-
-
-/**
- * @name Averaging to be done for the channels.
- * @{
- */
-#define XADCPS_AVG_0_SAMPLES 0U /**< No Averaging */
-#define XADCPS_AVG_16_SAMPLES 1U /**< Average 16 samples */
-#define XADCPS_AVG_64_SAMPLES 2U /**< Average 64 samples */
-#define XADCPS_AVG_256_SAMPLES 3U /**< Average 256 samples */
-
-/*@}*/
-
-
-/**
- * @name Channel Sequencer Modes of operation
- * @{
- */
-#define XADCPS_SEQ_MODE_SAFE 0U /**< Default Safe Mode */
-#define XADCPS_SEQ_MODE_ONEPASS 1U /**< Onepass through Sequencer */
-#define XADCPS_SEQ_MODE_CONTINPASS 2U /**< Continuous Cycling Sequencer */
-#define XADCPS_SEQ_MODE_SINGCHAN 3U /**< Single channel -No Sequencing */
-#define XADCPS_SEQ_MODE_SIMUL_SAMPLING 4U /**< Simultaneous sampling */
-#define XADCPS_SEQ_MODE_INDEPENDENT 8U /**< Independent mode */
-
-/*@}*/
-
-
-
-/**
- * @name Power Down Modes
- * @{
- */
-#define XADCPS_PD_MODE_NONE 0U /**< No Power Down */
-#define XADCPS_PD_MODE_ADCB 1U /**< Power Down ADC B */
-#define XADCPS_PD_MODE_XADC 2U /**< Power Down ADC A and ADC B */
-/*@}*/
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef contains configuration information for the XADC/ADC
- * device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Device base address */
-} XAdcPs_Config;
-
-
-/**
- * The driver's instance data. The user is required to allocate a variable
- * of this type for every XADC/ADC device in the system. A pointer to
- * a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XAdcPs_Config Config; /**< XAdcPs_Config of current device */
- u32 IsReady; /**< Device is initialized and ready */
-
-} XAdcPs;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-*
-* This macro checks if the XADC device is in Event Sampling mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return
-* - TRUE if the device is in Event Sampling Mode.
-* - FALSE if the device is in Continuous Sampling Mode.
-*
-* @note C-Style signature:
-* int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);
-*
-*****************************************************************************/
-#define XAdcPs_IsEventSamplingModeSet(InstancePtr) \
- (((XAdcPs_ReadInternalReg(InstancePtr, \
- XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ? \
- TRUE : FALSE))
-
-
-/****************************************************************************/
-/**
-*
-* This macro checks if the XADC device is in External Mux mode.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return
-* - TRUE if the device is in External Mux Mode.
-* - FALSE if the device is NOT in External Mux Mode.
-*
-* @note C-Style signature:
-* int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);
-*
-*****************************************************************************/
-#define XAdcPs_IsExternalMuxModeSet(InstancePtr) \
- (((XAdcPs_ReadInternalReg(InstancePtr, \
- XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ? \
- TRUE : FALSE))
-
-/****************************************************************************/
-/**
-*
-* This macro converts XADC Raw Data to Temperature(centigrades).
-*
-* @param AdcData is the Raw ADC Data from XADC.
-*
-* @return The Temperature in centigrades.
-*
-* @note C-Style signature:
-* float XAdcPs_RawToTemperature(u32 AdcData);
-*
-*****************************************************************************/
-#define XAdcPs_RawToTemperature(AdcData) \
- ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
-
-/****************************************************************************/
-/**
-*
-* This macro converts XADC/ADC Raw Data to Voltage(volts).
-*
-* @param AdcData is the XADC/ADC Raw Data.
-*
-* @return The Voltage in volts.
-*
-* @note C-Style signature:
-* float XAdcPs_RawToVoltage(u32 AdcData);
-*
-*****************************************************************************/
-#define XAdcPs_RawToVoltage(AdcData) \
- ((((float)(AdcData))* (3.0f))/65536.0f)
-
-/****************************************************************************/
-/**
-*
-* This macro converts Temperature in centigrades to XADC/ADC Raw Data.
-*
-* @param Temperature is the Temperature in centigrades to be
-* converted to XADC/ADC Raw Data.
-*
-* @return The XADC/ADC Raw Data.
-*
-* @note C-Style signature:
-* int XAdcPs_TemperatureToRaw(float Temperature);
-*
-*****************************************************************************/
-#define XAdcPs_TemperatureToRaw(Temperature) \
- ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
-
-/****************************************************************************/
-/**
-*
-* This macro converts Voltage in Volts to XADC/ADC Raw Data.
-*
-* @param Voltage is the Voltage in volts to be converted to
-* XADC/ADC Raw Data.
-*
-* @return The XADC/ADC Raw Data.
-*
-* @note C-Style signature:
-* int XAdcPs_VoltageToRaw(float Voltage);
-*
-*****************************************************************************/
-#define XAdcPs_VoltageToRaw(Voltage) \
- ((int)((Voltage)*65536.0f/3.0f))
-
-
-/****************************************************************************/
-/**
-*
-* This macro is used for writing to the XADC Registers using the
-* command FIFO.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Data is the value to be written to XADC register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);
-*
-*****************************************************************************/
-#define XAdcPs_WriteFifo(InstancePtr, Data) \
- XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XADCPS_CMDFIFO_OFFSET, Data);
-
-
-/****************************************************************************/
-/**
-*
-* This macro is used for reading from the XADC Registers using the
-* data FIFO.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return Data read from the FIFO
-*
-* @note C-Style signature:
-* u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);
-*
-*****************************************************************************/
-#define XAdcPs_ReadFifo(InstancePtr) \
- XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XADCPS_RDFIFO_OFFSET);
-
-
-/************************** Function Prototypes *****************************/
-
-
-
-/**
- * Functions in xadcps_sinit.c
- */
-XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
-
-/**
- * Functions in xadcps.c
- */
-int XAdcPs_CfgInitialize(XAdcPs *InstancePtr,
- XAdcPs_Config *ConfigPtr,
- u32 EffectiveAddr);
-
-void XAdcPs_SetConfigRegister(XAdcPs *InstancePtr, u32 Data);
-u32 XAdcPs_GetConfigRegister(XAdcPs *InstancePtr);
-
-u32 XAdcPs_GetMiscStatus(XAdcPs *InstancePtr);
-
-void XAdcPs_SetMiscCtrlRegister(XAdcPs *InstancePtr, u32 Data);
-u32 XAdcPs_GetMiscCtrlRegister(XAdcPs *InstancePtr);
-
-void XAdcPs_Reset(XAdcPs *InstancePtr);
-
-u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel);
-
-u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType);
-
-u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType);
-
-void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average);
-u8 XAdcPs_GetAvg(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
- u8 Channel,
- int IncreaseAcqCycles,
- int IsEventMode,
- int IsDifferentialMode);
-
-
-void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask);
-u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr);
-
-void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration);
-u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr);
-
-void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode);
-u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr);
-
-void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor);
-u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask);
-u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask);
-u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask);
-u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr);
-
-int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask);
-u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr);
-
-void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value);
-u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg);
-
-void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr);
-void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr);
-
-void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode);
-
-int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr);
-
-void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel);
-
-void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode);
-
-u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr);
-
-/**
- * Functions in xadcps_selftest.c
- */
-int XAdcPs_SelfTest(XAdcPs *InstancePtr);
-
-/**
- * Functions in xadcps_intr.c
- */
-void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask);
-void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask);
-u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr);
-
-u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr);
-void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* End of protection macro. */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e9/a0aa7f565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e9/a0aa7f565243001d18b399c1eb9b3628
deleted file mode 100644
index 47ddf9b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e9/a0aa7f565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,712 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
- * Microblaze HW Exception Handler
- * - Non self-modifying exception handler for the following exception conditions
- * - Unalignment
- * - Instruction bus error
- * - Data bus error
- * - Illegal instruction opcode
- * - Divide-by-zero
- * - Stack protection violation
- *******************************************************************************/
-
-#include "microblaze_exceptions_g.h"
-#include "xparameters.h"
-#include "microblaze_instructions.h"
-
-/* 64-bit definitions */
-#if defined (__arch64__)
-#define INTPTR_DATAITEM .quad
-#define REGSIZE 8
-#define DATAALIGN 4
-#else
-#define INTPTR_DATAITEM .long
-#define REGSIZE 4
-#define DATAALIGN 2
-#endif /* 64-bit definitions */
-
-/* Helpful Macros */
-#define EX_HANDLER_STACK_SIZ (REGSIZE*21)
-#define RMSR_OFFSET (20 * REGSIZE)
-#define R17_OFFSET (0)
-#define REG_OFFSET(regnum) (REGSIZE * (regnum + 1))
-#define NUM_TO_REG(num) r ## num
-
-#define R3_TO_STACK(regnum) SI r3, r1, REG_OFFSET(regnum)
-#define R3_FROM_STACK(regnum) LI r3, r1, REG_OFFSET(regnum)
-
-#define PUSH_REG(regnum) SI NUM_TO_REG(regnum), r1, REG_OFFSET(regnum)
-#define POP_REG(regnum) LI NUM_TO_REG(regnum), r1, REG_OFFSET(regnum)
-
-/* Uses r5 */
-#define PUSH_MSR \
- mfs r5, rmsr; \
- swi r5, r1, RMSR_OFFSET;
-
-#define PUSH_MSR_AND_ENABLE_EXC \
- mfs r5, rmsr; \
- swi r5, r1, RMSR_OFFSET; \
- ori r5, r5, 0x100; /* Turn ON the EE bit*/ \
- mts rmsr, r5;
-
-/* Uses r5 */
-#define POP_MSR \
- lwi r5, r1, RMSR_OFFSET; \
- mts rmsr, r5;
-
-/* Push r17 */
-#define PUSH_R17 SI r17, r1, R17_OFFSET
-/* Pop r17 */
-#define POP_R17 LI r17, r1, R17_OFFSET
-
-#define LWREG_NOP \
- BRI ex_handler_unhandled; \
- nop;
-
-#define SWREG_NOP \
- BRI ex_handler_unhandled; \
- nop;
-
-/* r3 is the source */
-#define R3_TO_LWREG_V(regnum) \
- R3_TO_STACK (regnum); \
- BRI ex_handler_done;
-
-/* r3 is the source */
-#define R3_TO_LWREG(regnum) \
- OR NUM_TO_REG (regnum), r0, r3; \
- BRI ex_handler_done;
-
-/* r3 is the target */
-#define SWREG_TO_R3_V(regnum) \
- R3_FROM_STACK (regnum); \
- BRI ex_sw_tail;
-
-/* r3 is the target */
-#define SWREG_TO_R3(regnum) \
- OR r3, r0, NUM_TO_REG (regnum); \
- BRI ex_sw_tail;
-
-/* regnum is the source */
-#define FP_EX_OPB_SAVE(regnum) \
- SI NUM_TO_REG (regnum), r0, mb_fpex_op_b; \
- nop; \
- BRI handle_fp_ex_opa;
-
-/* regnum is the source */
-#define FP_EX_OPB_SAVE_V(regnum) \
- R3_FROM_STACK (regnum); \
- SI r3, r0, mb_fpex_op_b; \
- BRI handle_fp_ex_opa;
-
-/* regnum is the source */
-#define FP_EX_OPA_SAVE(regnum) \
- SI NUM_TO_REG (regnum), r0, mb_fpex_op_a; \
- nop; \
- BRI handle_fp_ex_done;
-
-/* regnum is the source */
-#define FP_EX_OPA_SAVE_V(regnum) \
- R3_FROM_STACK (regnum); \
- SI r3, r0, mb_fpex_op_a; \
- BRI handle_fp_ex_done;
-
-#define FP_EX_UNHANDLED \
- BRI fp_ex_unhandled; \
- nop; \
- nop;
-
-/* ESR masks */
-#define ESR_EXC_MASK 0x0000001F
-#define ESR_REG_MASK 0x000003E0
-#define ESR_LW_SW_MASK 0x00000400
-#define ESR_WORD_MASK 0x00000800
-#define ESR_DS_MASK 0x00001000
-#define ESR_LONG_MASK 0x00002000
-
-/* Extern declarations */
-.extern XNullHandler
-
-
-#ifdef MICROBLAZE_EXCEPTIONS_ENABLED /* If exceptions are enabled in the processor */
-
-/*
- * hw_exception_handler - Handler for unaligned exceptions
- * Exception handler notes:
- * - Does not handle exceptions other than unaligned exceptions
- * - Does not handle exceptions during load into r17, r1, r0.
- * - Does not handle exceptions during store from r17 (cannot be done) and r1 (slows down common case)
- *
- * Relevant register structures
- *
- * EAR - |----|----|----|----|----|----|----|----|
- * - < ## 32 or 64 bit faulting address ## >
- *
- * ESR - |----|----|----|----|----| - | - |-----|-----|
- * - W S REG EXC
- *
- *
- * STACK FRAME STRUCTURE
- * ---------------------
- *
- * +-------------+ + 0
- * | r17 |
- * +-------------+ + 4 (32-bit) + 8 (64-bit)
- * | Args for |
- * | next func |
- * +-------------+ + 8 (32-bit) + 16 (64-bit)
- * | r1 |
- * | . |
- * | . |
- * | . |
- * | . |
- * | r18 |
- * +-------------+ + 80 (32-bit) + 160 (64-bit)
- * | MSR |
- * +-------------+ + 84 (32-bit) + 168 (64-bit)
- * | . |
- * | . |
- */
-
-
-.global _hw_exception_handler
-.section .text
-.align 2
-.ent _hw_exception_handler
-.type _hw_exception_handler, @function
-_hw_exception_handler:
-
-#if defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1)
- /* Immediately halt for stack protection violation exception without using any stack */
- SI r3, r0, mb_sp_save_r3; /* Save temporary register */
- mfs r3, resr; /* Extract ESR[DS] */
- andi r3, r3, ESR_EXC_MASK;
- xori r3, r3, 0x7; /* Check for stack protection violation */
- BNEI r3, ex_handler_not_sp_violation;
-ex_handler_sp_violation:
- bri 0; /* Halt here if stack protection violation */
-ex_handler_not_sp_violation:
- LI r3, r0, mb_sp_save_r3; /* Restore temporary register */
-#endif /* defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1) */
-
- ADDIK r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */
- PUSH_REG(3);
- PUSH_REG(4);
- PUSH_REG(5);
- PUSH_REG(6);
-#ifdef MICROBLAZE_CAN_HANDLE_EXCEPTIONS_IN_DELAY_SLOTS
- mfs r6, resr;
- andi r6, r6, ESR_DS_MASK;
- BEQI r6, ex_handler_no_ds;
- mfs r17, rbtr;
-ex_handler_no_ds:
-#endif
- PUSH_R17;
- PUSH_MSR_AND_ENABLE_EXC; /* Exceptions enabled here. This will allow nested exceptions */
-
- mfs r3, resr;
- andi r5, r3, ESR_EXC_MASK; /* Extract ESR[EXC] */
-#ifndef NO_UNALIGNED_EXCEPTIONS
- xori r6, r5, 1; /* 00001 = Unaligned Exception */
- BNEI r6, handle_ex_regular;
-
- ADDIK r4, r0, MB_ExceptionVectorTable; /* Check if user has registered an unaligned exception handler */
-#if defined (__arch64__)
- LI r4, r4, 16;
-#else
- LI r4, r4, 8;
-#endif
- ADDIK r6, r0, XNullHandler; /* If exceptionvectortable entry is still XNullHandler, use */
- XOR r6, r4, r6; /* the default exception handler */
- BEQI r6, handle_unaligned_ex ;
-
-handle_ex_regular:
-#endif /* ! NO_UNALIGNED_EXCEPTIONS */
-
-#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE)
- xori r6, r5, 6; /* 00110 = FPU exception */
- BEQI r6, handle_fp_ex; /* Go and decode the FP exception */
-#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
-
-handle_other_ex: /* Handle Other exceptions here */
- ori r6, r0, 20;
- cmp r6, r5, r6; /* >= 20 are exceptions we do not handle. */
- BLEI r6, ex_handler_unhandled;
-
- ori r6, r0, 7;
- cmp r6, r5, r6; /* Convert MMU exception indices into an ordinal of 7 */
- BGTI r6, handle_other_ex_tail;
- ori r5, r0, 0x7;
-
-handle_other_ex_tail:
- PUSH_REG(7); /* Save other volatiles before we make procedure calls below */
- PUSH_REG(8);
- PUSH_REG(9);
- PUSH_REG(10);
- PUSH_REG(11);
- PUSH_REG(12);
- PUSH_REG(15);
- PUSH_REG(18);
-
- ADDIK r4, r0, MB_ExceptionVectorTable; /* Load the Exception vector table base address */
- ADDK r7, r5, r5; /* Calculate exception vector offset = r5 * 8 (32-bit) */
- ADDK r7, r7, r7;
- ADDK r7, r7, r7;
-#if defined (__arch64__)
- ADDK r7, r7, r7; /* or r5 * 16 (64-bit) */
-#endif
- ADDK r7, r7, r4; /* Get pointer to exception vector */
- LI r5, r7, REGSIZE; /* Load argument to exception handler from table */
- LOAD r7, r7, r0; /* Load vector itself here */
-
- brald r15, r7; /* Branch to handler */
- nop;
-
- POP_REG(7); /* Restore other volatiles */
- POP_REG(8);
- POP_REG(9);
- POP_REG(10);
- POP_REG(11);
- POP_REG(12);
- POP_REG(15);
- POP_REG(18);
-
- BRI ex_handler_done; /* Complete exception handling */
-
-#ifndef NO_UNALIGNED_EXCEPTIONS
-handle_unaligned_ex:
- andi r6, r3, ESR_REG_MASK; /* Mask and extract the register operand */
- srl r6, r6; /* r6 >> 5 */
- srl r6, r6;
- srl r6, r6;
- srl r6, r6;
- srl r6, r6;
- sbi r6, r0, ex_reg_op; /* Store the register operand in a temporary location */
- mfs r4, rear;
- andi r6, r3, ESR_LW_SW_MASK; /* Extract ESR[S] */
- BNEI r6, ex_sw;
-#if defined (__arch64__)
-ex_ll:
- andi r6, r3, ESR_LONG_MASK; /* Extract ESR[L] */
- BEQI r6, ex_lw;
- lbui r5, r4, 0; /* Exception address in r4 */
- sbi r5, r0, ex_tmp_data_loc_0; /* Load a long, byte-by-byte from destination address and save it in tmp space */
- lbui r5, r4, 1;
- sbi r5, r0, ex_tmp_data_loc_1;
- lbui r5, r4, 2;
- sbi r5, r0, ex_tmp_data_loc_2;
- lbui r5, r4, 3;
- sbi r5, r0, ex_tmp_data_loc_3;
- lbui r5, r4, 4;
- sbi r5, r0, ex_tmp_data_loc_4;
- lbui r5, r4, 5;
- sbi r5, r0, ex_tmp_data_loc_5;
- lbui r5, r4, 6;
- sbi r5, r0, ex_tmp_data_loc_6;
- lbui r5, r4, 7;
- sbi r5, r0, ex_tmp_data_loc_7;
- lli r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */
- BRI ex_lw_tail;
-#endif
-ex_lw:
- andi r6, r3, ESR_WORD_MASK; /* Extract ESR[W] */
- BEQI r6, ex_lhw;
- lbui r5, r4, 0; /* Exception address in r4 */
- sbi r5, r0, ex_tmp_data_loc_0; /* Load a word, byte-by-byte from destination address and save it in tmp space */
- lbui r5, r4, 1;
- sbi r5, r0, ex_tmp_data_loc_1;
- lbui r5, r4, 2;
- sbi r5, r0, ex_tmp_data_loc_2;
- lbui r5, r4, 3;
- sbi r5, r0, ex_tmp_data_loc_3;
- lwi r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */
- BRI ex_lw_tail;
-ex_lhw:
- lbui r5, r4, 0; /* Exception address in r4 */
- sbi r5, r0, ex_tmp_data_loc_0; /* Load a half-word, byte-by-byte from destination address and save it in tmp space */
- lbui r5, r4, 1;
- sbi r5, r0, ex_tmp_data_loc_1;
- lhui r3, r0, ex_tmp_data_loc_0; /* Get the destination register value into r3 */
-ex_lw_tail:
- lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */
- ADDIK r6, r0, lw_table; /* Form load_word jump table offset (lw_table + (8 * regnum)) */
- ADDK r5, r5, r5;
- ADDK r5, r5, r5;
- ADDK r5, r5, r5;
- ADDK r5, r5, r6;
- bra r5;
-ex_lw_end: /* Exception handling of load word, ends */
-ex_sw:
- lbui r5, r0, ex_reg_op; /* Get the destination register number into r5 */
- ADDIK r6, r0, sw_table; /* Form store_word jump table offset (sw_table + (8 * regnum)) */
- ADDK r5, r5, r5;
- ADDK r5, r5, r5;
- ADDK r5, r5, r5;
- ADDK r5, r5, r6;
- bra r5;
-ex_sw_tail:
-#if defined (__arch64__)
-ex_sl:
- mfs r6, resr;
- andi r6, r6, ESR_LONG_MASK; /* Extract ESR[L] */
- BEQI r6, ex_not_sl;
- sli r3, r0, ex_tmp_data_loc_0;
- lbui r3, r0, ex_tmp_data_loc_0; /* Store the long, byte-by-byte into destination address */
- sbi r3, r4, 0;
- lbui r3, r0, ex_tmp_data_loc_1;
- sbi r3, r4, 1;
- lbui r3, r0, ex_tmp_data_loc_2;
- sbi r3, r4, 2;
- lbui r3, r0, ex_tmp_data_loc_3;
- sbi r3, r4, 3;
- lbui r3, r0, ex_tmp_data_loc_4;
- sbi r3, r4, 4;
- lbui r3, r0, ex_tmp_data_loc_5;
- sbi r3, r4, 5;
- lbui r3, r0, ex_tmp_data_loc_6;
- sbi r3, r4, 6;
- lbui r3, r0, ex_tmp_data_loc_7;
- sbi r3, r4, 7;
- BRI ex_handler_done;
-ex_not_sl:
-#endif
- mfs r6, resr;
- andi r6, r6, ESR_WORD_MASK; /* Extract ESR[W] */
- BEQI r6, ex_shw;
- swi r3, r0, ex_tmp_data_loc_0;
- lbui r3, r0, ex_tmp_data_loc_0; /* Store the word, byte-by-byte into destination address */
- sbi r3, r4, 0;
- lbui r3, r0, ex_tmp_data_loc_1;
- sbi r3, r4, 1;
- lbui r3, r0, ex_tmp_data_loc_2;
- sbi r3, r4, 2;
- lbui r3, r0, ex_tmp_data_loc_3;
- sbi r3, r4, 3;
- BRI ex_handler_done;
-ex_shw:
- swi r3, r0, ex_tmp_data_loc_0; /* Store the lower half-word, byte-by-byte into destination address */
-
-#ifdef __LITTLE_ENDIAN__
- lbui r3, r0, ex_tmp_data_loc_0;
-#else
- lbui r3, r0, ex_tmp_data_loc_2;
-#endif
- sbi r3, r4, 0;
-#ifdef __LITTLE_ENDIAN__
- lbui r3, r0, ex_tmp_data_loc_1;
-#else
- lbui r3, r0, ex_tmp_data_loc_3;
-#endif
- sbi r3, r4, 1;
-ex_sw_end: /* Exception handling of store word, ends. */
- BRI ex_handler_done;
-#endif /* !NO_UNALIGNED_EXCEPTIONS */
-
-#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE)
-handle_fp_ex:
- ADDIK r3, r17, -4; /* r17 contains (addr of exception causing FP instruction + 4) */
- lw r4, r0, r3; /* We might find ourselves in a spot here. Unguaranteed load */
-
-handle_fp_ex_opb:
- ADDIK r6, r0, fp_table_opb; /* Decode opB and store its value in mb_fpex_op_b */
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- andi r3, r4, 0x1F;
- ADDK r3, r3, r3; /* Calculate (fp_table_opb + (regno * 12)) in r5 */
- ADDK r3, r3, r3;
- ADDK r5, r3, r3;
- ADDK r5, r5, r3;
- ADDK r5, r5, r6;
- bra r5;
-
-handle_fp_ex_opa:
- ADDIK r6, r0, fp_table_opa; /* Decode opA and store its value in mb_fpex_op_a */
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- srl r4, r4;
- andi r3, r4, 0x1F;
- ADDK r3, r3, r3; /* Calculate (fp_table_opb + (regno * 12)) in r5 */
- ADDK r3, r3, r3;
- ADDK r5, r3, r3;
- ADDK r5, r5, r3;
- ADDK r5, r5, r6;
- bra r5;
-
-handle_fp_ex_done:
- ori r5, r0, 6; /* Set exception number back to 6 */
- BRI handle_other_ex_tail;
-
-fp_ex_unhandled:
- bri 0;
-#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
-
-ex_handler_done:
- POP_R17;
- POP_MSR;
- POP_REG(3);
- POP_REG(4);
- POP_REG(5);
- POP_REG(6);
-
- ADDIK r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */
- rted r17, 0
- nop
-
-ex_handler_unhandled:
- bri 0 /* UNHANDLED. TRAP HERE */
-.end _hw_exception_handler
-
-#ifndef NO_UNALIGNED_EXCEPTIONS
-
-/*
- * hw_exception_handler Jump Table
- * - Contains code snippets for each register that caused the unaligned exception.
- * - Hence exception handler is NOT self-modifying
- * - Separate table for load exceptions and store exceptions.
- * - Each table is of size: (8 * 32) = 256 bytes
- */
-
-.section .text
-.align 4
-lw_table:
-lw_r0: R3_TO_LWREG (0);
-lw_r1: LWREG_NOP;
-lw_r2: R3_TO_LWREG (2);
-lw_r3: R3_TO_LWREG_V (3);
-lw_r4: R3_TO_LWREG_V (4);
-lw_r5: R3_TO_LWREG_V (5);
-lw_r6: R3_TO_LWREG_V (6);
-lw_r7: R3_TO_LWREG (7);
-lw_r8: R3_TO_LWREG (8);
-lw_r9: R3_TO_LWREG (9);
-lw_r10: R3_TO_LWREG (10);
-lw_r11: R3_TO_LWREG (11);
-lw_r12: R3_TO_LWREG (12);
-lw_r13: R3_TO_LWREG (13);
-lw_r14: R3_TO_LWREG (14);
-lw_r15: R3_TO_LWREG (15);
-lw_r16: R3_TO_LWREG (16);
-lw_r17: LWREG_NOP;
-lw_r18: R3_TO_LWREG (18);
-lw_r19: R3_TO_LWREG (19);
-lw_r20: R3_TO_LWREG (20);
-lw_r21: R3_TO_LWREG (21);
-lw_r22: R3_TO_LWREG (22);
-lw_r23: R3_TO_LWREG (23);
-lw_r24: R3_TO_LWREG (24);
-lw_r25: R3_TO_LWREG (25);
-lw_r26: R3_TO_LWREG (26);
-lw_r27: R3_TO_LWREG (27);
-lw_r28: R3_TO_LWREG (28);
-lw_r29: R3_TO_LWREG (29);
-lw_r30: R3_TO_LWREG (30);
-lw_r31: R3_TO_LWREG (31);
-
-sw_table:
-sw_r0: SWREG_TO_R3 (0);
-sw_r1: SWREG_NOP;
-sw_r2: SWREG_TO_R3 (2);
-sw_r3: SWREG_TO_R3_V (3);
-sw_r4: SWREG_TO_R3_V (4);
-sw_r5: SWREG_TO_R3_V (5);
-sw_r6: SWREG_TO_R3_V (6);
-sw_r7: SWREG_TO_R3 (7);
-sw_r8: SWREG_TO_R3 (8);
-sw_r9: SWREG_TO_R3 (9);
-sw_r10: SWREG_TO_R3 (10);
-sw_r11: SWREG_TO_R3 (11);
-sw_r12: SWREG_TO_R3 (12);
-sw_r13: SWREG_TO_R3 (13);
-sw_r14: SWREG_TO_R3 (14);
-sw_r15: SWREG_TO_R3 (15);
-sw_r16: SWREG_TO_R3 (16);
-sw_r17: SWREG_NOP;
-sw_r18: SWREG_TO_R3 (18);
-sw_r19: SWREG_TO_R3 (19);
-sw_r20: SWREG_TO_R3 (20);
-sw_r21: SWREG_TO_R3 (21);
-sw_r22: SWREG_TO_R3 (22);
-sw_r23: SWREG_TO_R3 (23);
-sw_r24: SWREG_TO_R3 (24);
-sw_r25: SWREG_TO_R3 (25);
-sw_r26: SWREG_TO_R3 (26);
-sw_r27: SWREG_TO_R3 (27);
-sw_r28: SWREG_TO_R3 (28);
-sw_r29: SWREG_TO_R3 (29);
-sw_r30: SWREG_TO_R3 (30);
-sw_r31: SWREG_TO_R3 (31);
-
-/* Temporary data structures used in the handler */
-.section .data
-.align DATAALIGN
-ex_tmp_data_loc_0:
- .byte 0
-ex_tmp_data_loc_1:
- .byte 0
-ex_tmp_data_loc_2:
- .byte 0
-ex_tmp_data_loc_3:
- .byte 0
-#if defined (__arch64__)
-ex_tmp_data_loc_4:
- .byte 0
-ex_tmp_data_loc_5:
- .byte 0
-ex_tmp_data_loc_6:
- .byte 0
-ex_tmp_data_loc_7:
- .byte 0
-#endif
-ex_reg_op:
- .byte 0
-
-#endif /* ! NO_UNALIGNED_EXCEPTIONS */
-
-#if defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE)
-/*
- * FP exception decode jump table.
- * - Contains code snippets for each register that could have been a source operand for an excepting FP instruction
- * - Hence exception handler is NOT self-modifying
- * - Separate table for opA and opB
- * - Each table is of size: (12 * 32) = 384 bytes
- */
-
-.section .text
-.align 4
-fp_table_opa:
-opa_r0: FP_EX_OPA_SAVE (0);
-opa_r1: FP_EX_UNHANDLED;
-opa_r2: FP_EX_OPA_SAVE (2);
-opa_r3: FP_EX_OPA_SAVE_V (3);
-opa_r4: FP_EX_OPA_SAVE_V (4);
-opa_r5: FP_EX_OPA_SAVE_V (5);
-opa_r6: FP_EX_OPA_SAVE_V (6);
-opa_r7: FP_EX_OPA_SAVE (7);
-opa_r8: FP_EX_OPA_SAVE (8);
-opa_r9: FP_EX_OPA_SAVE (9);
-opa_r10: FP_EX_OPA_SAVE (10);
-opa_r11: FP_EX_OPA_SAVE (11);
-opa_r12: FP_EX_OPA_SAVE (12);
-opa_r13: FP_EX_OPA_SAVE (13);
-opa_r14: FP_EX_UNHANDLED;
-opa_r15: FP_EX_UNHANDLED;
-opa_r16: FP_EX_UNHANDLED;
-opa_r17: FP_EX_UNHANDLED;
-opa_r18: FP_EX_OPA_SAVE (18);
-opa_r19: FP_EX_OPA_SAVE (19);
-opa_r20: FP_EX_OPA_SAVE (20);
-opa_r21: FP_EX_OPA_SAVE (21);
-opa_r22: FP_EX_OPA_SAVE (22);
-opa_r23: FP_EX_OPA_SAVE (23);
-opa_r24: FP_EX_OPA_SAVE (24);
-opa_r25: FP_EX_OPA_SAVE (25);
-opa_r26: FP_EX_OPA_SAVE (26);
-opa_r27: FP_EX_OPA_SAVE (27);
-opa_r28: FP_EX_OPA_SAVE (28);
-opa_r29: FP_EX_OPA_SAVE (29);
-opa_r30: FP_EX_OPA_SAVE (30);
-opa_r31: FP_EX_OPA_SAVE (31);
-
-fp_table_opb:
-opb_r0: FP_EX_OPB_SAVE (0);
-opb_r1: FP_EX_UNHANDLED;
-opb_r2: FP_EX_OPB_SAVE (2);
-opb_r3: FP_EX_OPB_SAVE_V (3);
-opb_r4: FP_EX_OPB_SAVE_V (4);
-opb_r5: FP_EX_OPB_SAVE_V (5);
-opb_r6: FP_EX_OPB_SAVE_V (6);
-opb_r7: FP_EX_OPB_SAVE (7);
-opb_r8: FP_EX_OPB_SAVE (8);
-opb_r9: FP_EX_OPB_SAVE (9);
-opb_r10: FP_EX_OPB_SAVE (10);
-opb_r11: FP_EX_OPB_SAVE (11);
-opb_r12: FP_EX_OPB_SAVE (12);
-opb_r13: FP_EX_OPB_SAVE (13);
-opb_r14: FP_EX_UNHANDLED;
-opb_r15: FP_EX_UNHANDLED;
-opb_r16: FP_EX_UNHANDLED;
-opb_r17: FP_EX_UNHANDLED;
-opb_r18: FP_EX_OPB_SAVE (18);
-opb_r19: FP_EX_OPB_SAVE (19);
-opb_r20: FP_EX_OPB_SAVE (20);
-opb_r21: FP_EX_OPB_SAVE (21);
-opb_r22: FP_EX_OPB_SAVE (22);
-opb_r23: FP_EX_OPB_SAVE (23);
-opb_r24: FP_EX_OPB_SAVE (24);
-opb_r25: FP_EX_OPB_SAVE (25);
-opb_r26: FP_EX_OPB_SAVE (26);
-opb_r27: FP_EX_OPB_SAVE (27);
-opb_r28: FP_EX_OPB_SAVE (28);
-opb_r29: FP_EX_OPB_SAVE (29);
-opb_r30: FP_EX_OPB_SAVE (30);
-opb_r31: FP_EX_OPB_SAVE (31);
-
-#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
-
-#if defined(MICROBLAZE_FP_EXCEPTION_ENABLED) && defined(MICROBLAZE_FP_EXCEPTION_DECODE)
-/* This is where we store the opA and opB of the last excepting FP instruction */
-.section .data
-.align DATAALIGN
-.global mb_fpex_op_a
-.global mb_fpex_op_b
-mb_fpex_op_a:
- INTPTR_DATAITEM 0
-mb_fpex_op_b:
- INTPTR_DATAITEM 0
-#endif /* defined (MICROBLAZE_FP_EXCEPTION_ENABLED) && defined (MICROBLAZE_FP_EXCEPTION_DECODE) */
-
-#if defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1)
-/* This is where we store the register used to check which exception occurred */
- .section .data
- .align DATAALIGN
-mb_sp_save_r3:
- INTPTR_DATAITEM 0
-#endif /* defined(XPAR_MICROBLAZE_USE_STACK_PROTECTION) && (XPAR_MICROBLAZE_USE_STACK_PROTECTION == 1) */
-
-/* The exception vector table */
-.section .data
-.align DATAALIGN
-.global MB_ExceptionVectorTable
-MB_ExceptionVectorTable:
- INTPTR_DATAITEM XNullHandler
- INTPTR_DATAITEM 0 /* -- FSL Exception -- */
- INTPTR_DATAITEM XNullHandler
- INTPTR_DATAITEM 1 /* -- Unaligned Access Exception -- */
- INTPTR_DATAITEM XNullHandler
- INTPTR_DATAITEM 2 /* -- Illegal Opcode Exception -- */
- INTPTR_DATAITEM XNullHandler
- INTPTR_DATAITEM 3 /* -- Instruction Bus Exception -- */
- INTPTR_DATAITEM XNullHandler
- INTPTR_DATAITEM 4 /* -- Data Bus Exception -- */
- INTPTR_DATAITEM XNullHandler
- INTPTR_DATAITEM 5 /* -- Div-by-0 Exception -- */
- INTPTR_DATAITEM XNullHandler
- INTPTR_DATAITEM 6 /* -- FPU Exception -- */
- INTPTR_DATAITEM XNullHandler
- INTPTR_DATAITEM 7 /* -- MMU Exceptions -- */
-
-#else /* Dummy exception handler, in case exceptions are not present in the processor */
-
-.global _hw_exception_handler
-.section .text
-.align 2
-.ent _hw_exception_handler
-_hw_exception_handler:
- bri 0;
-.end _hw_exception_handler
-
-#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e9/a24a95555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e9/a24a95555243001d18b399c1eb9b3628
deleted file mode 100644
index 8eb4638..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e9/a24a95555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,24 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf);
-}
-#endif
-/*
- * fstat -- Since we have no file system, we just return an error.
- */
-__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf)
-{
- (void)fd;
- buf->st_mode = S_IFCHR; /* Always pretend to be a tty */
-
- return (0);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e9/e0d1d7555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e9/e0d1d7555243001d18b399c1eb9b3628
deleted file mode 100644
index 243c109..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/e9/e0d1d7555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,12 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#include "xil_types.h"
-/* Stub for read() sys-call */
-__weak s32 _sys_read(u32 fh, u8 *buf, u32 len, s32 mode)
-{
- /* Return the number of character NOT read */
- return len;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ea/319223545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ea/319223545243001d18b399c1eb9b3628
deleted file mode 100644
index 1b7d881..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ea/319223545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,369 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xdevcfg_hw.h
-* @addtogroup devcfg_v3_7
-* @{
-*
-* This file contains the hardware interface to the Device Config Interface.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.01a nm 08/01/12 Added defines for the PS Version bits,
-* removed the FIFO Flush bits from the
-* Miscellaneous Control Reg
-* 2.03a nm 04/19/13 Fixed CR# 703728.
-* Updated the register definitions as per the latest TRM
-* version UG585 (v1.4) November 16, 2012.
-* 2.04a kpc 10/07/13 Added function prototype.
-* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
-*
-*
-******************************************************************************/
-#ifndef XDCFG_HW_H /* prevent circular inclusions */
-#define XDCFG_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- * Offsets of registers from the start of the device
- * @{
- */
-
-#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */
-#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */
-#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */
-#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */
-#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */
-#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */
-#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */
-#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */
-#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */
-#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */
-#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */
-#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */
-#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */
-#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */
-#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */
-
-/* @} */
-
-/** @name Control Register Bit definitions
- * @{
- */
-
-#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into
- * Secure Reset
- */
-#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to
- * Reset FPGA
- */
-#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */
-#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */
-#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */
-#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data
- * to FPGA every 4 PCAP
- * cycles
- */
-#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */
-#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */
-#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */
-#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */
-#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */
-#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */
-#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure
- * Status mask
- */
-#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive
- * Debug Enable
- */
-#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive
- * Debug Enable
- */
-#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug
- * Enable
- */
-#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug
- * Enable
- */
-#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */
-
-/* @} */
-
-/** @name Lock register bit definitions
- * @{
- */
-
-#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */
-#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */
-#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */
-#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and
- * USER_MODE
- */
-#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks
- * security config
- * including: DAP_En,
- * DBGEN,,
- * NIDEN, SPNIEN
- */
-/*@}*/
-
-
-
-/** @name Config Register Bit definitions
- * @{
- */
-#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO
- * Threshold Mask
- */
-#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold
- * Mask
- */
-#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active
- * clock edge
- */
-#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active
- * clock edge
- */
-#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address
- * increment mask
- */
-#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination
- * address increment
- * mask
- */
-/* @} */
-
-
-/** @name Interrupt Status/Mask Register Bit definitions
- * @{
- */
-#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during
- * HIZ
- */
-#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration
- * done
- */
-#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */
-#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during
- * configuration
- */
-#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration
- * reset
- */
-#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address
- * or Data or response
- * timeout
- */
-#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response
- * error
- */
-#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or
- * response timeout
- */
-#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response
- * error
- */
-#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */
-#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than
- * threshold */
-#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than
- * threshold */
-#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */
-#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue
- * overflow
- */
-#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */
-#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP
- * transfers Done
- */
-#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer
- * length error
- */
-#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */
-#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */
-#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */
-#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */
-#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */
-#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge
- * of Init Signal
- */
-#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge
- * of Init Signal
- */
-#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \
- XDCFG_IXR_AXI_WERR_MASK | \
- XDCFG_IXR_AXI_RTO_MASK | \
- XDCFG_IXR_AXI_RERR_MASK | \
- XDCFG_IXR_RX_FIFO_OV_MASK | \
- XDCFG_IXR_DMA_CMD_ERR_MASK |\
- XDCFG_IXR_DMA_Q_OV_MASK | \
- XDCFG_IXR_P2D_LEN_ERR_MASK |\
- XDCFG_IXR_PCFG_HMAC_ERR_MASK)
-
-
-#define XDCFG_IXR_ALL_MASK 0x00F7F8EF
-
-
-
-/* @} */
-
-
-/** @name Status Register Bit definitions
- * @{
- */
-#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command
- * Queue full
- */
-#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command
- * Queue empty
- */
-#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of
- * completed DMA
- * transfers
- */
-#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */
-#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */
-
-#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO
- * during HIZ
- */
-#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config
- * done
- */
-#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */
-#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during
- * config
- */
-#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset
- * POR Status
- */
-#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB
- * access
- */
-#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config
- * reset status
- */
-#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init
- * Status
- */
-#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008
- /**< BBRAM key
- * disable
- */
-#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security
- * Enable Status
- */
-#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG
- * Disable
- * status
- */
-/* @} */
-
-
-/** @name DMA Source/Destination Transfer Length Register Bit definitions
- * @{
- */
-#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */
-/*@}*/
-
-
-
-
-/** @name Miscellaneous Control Register Bit definitions
- * @{
- */
-#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */
-#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */
-#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */
-/* @} */
-
-/** @name FIFO Threshold Bit definitions
- * @{
- */
-
-#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */
-#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */
-#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */
-#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */
-/* @}*/
-
-
-/* Miscellaneous constant values */
-#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */
-#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/
-#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base
- * address
- */
-#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Read the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note C-style signature:
-* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XDcfg_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + (RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write to the given register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + (RegOffset), (Data))
-
-/************************** Function Prototypes ******************************/
-/*
- * Perform reset operation to the devcfg interface
- */
-void XDcfg_ResetHw(u32 BaseAddr);
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ea/91bf75565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ea/91bf75565243001d18b399c1eb9b3628
deleted file mode 100644
index f673ff3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ea/91bf75565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,34 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#include
-#include
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) int _kill(pid_t pid, int sig);
-}
-#endif
-
-/*
- * kill -- go out via exit...
- */
-
-__attribute__((weak)) int kill(pid_t pid, int sig)
-{
- if(pid == 1) {
- _exit(sig);
- }
- return 0;
-}
-
-__attribute__((weak)) int _kill(pid_t pid, int sig)
-{
- if(pid == 1) {
- _exit(sig);
- }
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ea/a18e66545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ea/a18e66545243001d18b399c1eb9b3628
deleted file mode 100644
index 2782826..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ea/a18e66545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,342 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xsdps.h
-* @addtogroup sdps_v3_13
-* @{
-* @details
-*
-* This file contains the implementation of XSdPs driver.
-* This driver is used initialize read from and write to the SD card.
-* Features such as switching bus width to 4-bit and switching to high speed,
-* changing clock frequency, block size etc. are supported.
-* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
-* is done using 1-bit bus width and 400KHz clock frequency.
-* SD commands are classified as broadcast and addressed. Commands can be
-* those with response only (using only command line) or
-* response + data (using command and data lines).
-* Only one command can be sent at a time. During a data transfer however,
-* when dsta lines are in use, certain commands (which use only the command
-* line) can be sent, most often to obtain status.
-* This driver does not support multi card slots at present.
-*
-* Initialization:
-* This includes initialization on the host controller side to select
-* clock frequency, bus power and default transfer related parameters.
-* The default voltage is 3.3V.
-* On the SD card side, the initialization and identification state diagram is
-* implemented. This resets the card, gives it a unique address/ID and
-* identifies key card related specifications.
-*
-* Data transfer:
-* The SD card is put in transfer state to read from or write to it.
-* The default block size is 512 bytes and if supported,
-* default bus width is 4-bit and bus speed is High speed.
-* The read and write functions are implemented in polled mode using ADMA2.
-*
-* At any point, when key parameters such as block size or
-* clock/speed or bus width are modified, this driver takes care of
-* maintaining the same selection on host and card.
-* All error bits in host controller are monitored by the driver and in the
-* event one of them is set, driver will clear the interrupt status and
-* communicate failure to the upper layer.
-*
-* File system use:
-* This driver can be used with xilffs library to read and write files to SD.
-* (Please refer to procedure in diskio.c). The file system read/write example
-* in polled mode can used for reference.
-*
-* There is no example for using SD driver without file system at present.
-* However, the driver can be used without the file system. The glue layer
-* in filesystem can be used as reference for the same. The block count
-* passed to the read/write function in one call is limited by the ADMA2
-* descriptor table and hence care will have to be taken to call read/write
-* API's in a loop for large file sizes.
-*
-* Interrupt mode is not supported because it offers no improvement when used
-* with file system.
-*
-* eMMC support:
-* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
-* The features of eMMC supported by the driver will depend on those supported
-* by the host controller. The current driver supports read/write on eMMC card
-* using 4-bit and high speed mode currently.
-*
-* Features not supported include - card write protect, password setting,
-* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
-* 64-bit addressed ADMA2, erase/pre-erase commands.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a hk/sg 10/17/13 Initial release
-* 2.0 hk 03/07/14 Version number revised.
-* 2.1 hk 04/18/14 Increase sleep for eMMC switch command.
-* Add sleep for microblaze designs. CR# 781117.
-* 2.2 hk 07/28/14 Make changes to enable use of data cache.
-* 2.3 sk 09/23/14 Send command for relative card address
-* when re-initialization is done.CR# 819614.
-* Use XSdPs_Change_ClkFreq API whenever changing
-* clock.CR# 816586.
-* 2.4 sk 12/04/14 Added support for micro SD without
-* WP/CD. CR# 810655.
-* Checked for DAT Inhibit mask instead of CMD
-* Inhibit mask in Cmd Transfer API.
-* Added Support for SD Card v1.0
-* 2.5 sg 07/09/15 Added SD 3.0 features
-* kvn 07/15/15 Modified the code according to MISRAC-2012.
-* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
-* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
-* sk 12/10/15 Added support for MMC cards.
-* 01/08/16 Added workaround for issue in auto tuning mode
-* of SDR50, SDR104 and HS200.
-* sk 02/16/16 Corrected the Tuning logic.
-* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
-* 2.8 sk 04/20/16 Added new workaround for auto tuning.
-* 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
-* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
-* sk 07/16/16 Added support for UHS modes.
-* sk 07/07/16 Used usleep API for both arm and microblaze.
-* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
-* operating modes.
-* sk 08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
-* CR#956899.
-* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
-* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
-* sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
-* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
-* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value.
-* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
-* sk 02/01/17 Added HSD and DDR mode support for eMMC.
-* sk 02/01/17 Consider bus width parameter from design for switching
-* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
-* sk 03/20/17 Add support for EL1 non-secure mode.
-* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
-* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
-* mn 08/17/17 Enabled CCI support for A53 by adding cache coherency
-* information.
-* mn 09/06/17 Resolved compilation errors with IAR toolchain
-* 3.6 mn 08/01/18 Add support for using 64Bit DMA with 32-Bit Processor
-* 3.7 mn 02/01/19 Add support for idling of SDIO
-* 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
-* mn 09/17/19 Modified ADMA handling API for 32bit and 64bit addresses
-* 3.9 mn 03/03/20 Restructured the code for more readability and modularity
-* mn 03/16/20 Move XSdPs_Select_Card API to User APIs
-* 3.10 mn 06/05/20 Check Transfer completion separately from XSdPs_Read and
-* XSdPs_Write APIs
-* mn 06/05/20 Modified code for SD Non-Blocking Read support
-* 3.11 sk 12/01/20 Tap programming sequence updates like disable OTAPEN
-* always, write zero to tap register for zero tap value.
-* sk 12/07/20 Fix eMMC DDR52 mode write/read issue.
-* sk 12/17/20 Removed checking platform specific SD macros and used
-* Baseaddress instead.
-* 3.12 sk 01/28/21 Added support for non-blocking write.
-* sk 02/12/21 Fix the issue in reading CID and CSD.
-* sk 04/08/21 Fixed doxygen warnings in all source files.
-* sk 05/25/21 Fix the compilation issue in Cortex-A72 + EL1_NS by
-* removing the DLL reset logic (Dead code for Versal).
-* 3.13 sk 08/10/21 Limit the SD operating frequency to 19MHz for Versal.
-*
-*
-*
-******************************************************************************/
-
-
-#ifndef SDPS_H_
-#define SDPS_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xil_printf.h"
-#include "xil_cache.h"
-#include "xstatus.h"
-#include "xsdps_hw.h"
-#include "xplatform_info.h"
-#include "sleep.h"
-#include
-#if defined (XCLOCKING)
-#include "xil_clocking.h"
-#endif
-
-/************************** Constant Definitions *****************************/
-
-#define XSDPS_CT_ERROR 0x2L /**< Command timeout flag */
-#define MAX_TUNING_COUNT 40U /**< Maximum Tuning count */
-#define MAX_TIMEOUT 0x1FFFFFFFU /**< Maximum Timeout */
-#define XSDPS_CMD8_VOL_PATTERN 0x1AAU /**< CMD8 voltage pattern */
-#define XSDPS_RESPOCR_READY 0x80000000U /**< Ready response */
-#define XSDPS_ACMD41_HCS 0x40000000U /**< High Capacity Support */
-#define XSDPS_ACMD41_3V3 0x00300000U /**< 3.3 voltage support */
-#define XSDPS_CMD1_HIGH_VOL 0x00FF8000U /**< CMD1 for High voltage */
-#define XSDPS_CMD1_DUAL_VOL 0x00FF8010U /**< CMD1 for Dual voltage */
-#define HIGH_SPEED_SUPPORT 0x2U /**< High Speed support */
-#define UHS_SDR12_SUPPORT 0x1U /**< SDR12 support */
-#define UHS_SDR25_SUPPORT 0x2U /**< SDR25 support */
-#define UHS_SDR50_SUPPORT 0x4U /**< SDR50 support */
-#define UHS_SDR104_SUPPORT 0x8U /**< SDR104 support */
-#define UHS_DDR50_SUPPORT 0x10U /**< DDR50 support */
-#define WIDTH_4_BIT_SUPPORT 0x4U /**< 4-bit width support */
-#define SD_CLK_25_MHZ 25000000U /**< 25MHz clock */
-#define SD_CLK_19_MHZ 19000000U /**< 19MHz clock */
-#define SD_CLK_26_MHZ 26000000U /**< 26MHz clock */
-#define EXT_CSD_DEVICE_TYPE_BYTE 196U /**< CSD Device Type byte number */
-#define EXT_CSD_SEC_COUNT_BYTE1 212U /**< CSD Sector count byte 1 */
-#define EXT_CSD_SEC_COUNT_BYTE2 213U /**< CSD Sector count byte 2 */
-#define EXT_CSD_SEC_COUNT_BYTE3 214U /**< CSD Sector count byte 3 */
-#define EXT_CSD_SEC_COUNT_BYTE4 215U /**< CSD Sector count byte 4 */
-#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED 0x2U /**< CSD Device type HS */
-#define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED 0x4U /**< CSD Dev type DDR 1.8v speed */
-#define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED 0x8U /**< CSD Dev type DDR 1.2v speed */
-#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 0x10U /**< CSD SDR 1.8v HS200 */
-#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200 0x20U /**< CSD SDR 1.2v HS200 */
-#define CSD_SPEC_VER_3 0x3U /**< CSD card spec ver 3 */
-#define SCR_SPEC_VER_3 0x80U /**< SCR spec ver 3 */
-#define ADDRESS_BEYOND_32BIT 0x100000000U /**< Macro used for beyond 32-bit addr */
-
-#define XSDPS_ZYNQMP_SD0_BASE 0xFF160000U /**< ZynqMP SD0 Baseaddress */
-#define XSDPS_ZYNQMP_SD1_BASE 0xFF170000U /**< ZynqMP SD1 Baseaddress */
-#define XSDPS_VERSAL_SD0_BASE 0xF1040000U /**< Versal SD0 Baseaddress */
-#define XSDPS_VERSAL_SD1_BASE 0xF1050000U /**< Versal SD1 Baseaddress */
-
-/**************************** Type Definitions *******************************/
-
-/**
- * Function pointer for configuring the Tap delays.
- */
-typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of the device */
- u32 InputClockHz; /**< Input clock frequency */
- u32 CardDetect; /**< Card Detect */
- u32 WriteProtect; /**< Write Protect */
- u32 BusWidth; /**< Bus Width */
- u32 BankNumber; /**< MIO Bank selection for SD */
- u32 HasEMIO; /**< If SD is connected to EMIO */
- u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */
-#if defined (XCLOCKING)
- u32 RefClk; /**< Input clocks */
-#endif
-} XSdPs_Config;
-
-/**
- * ADMA2 32-Bit descriptor table
- */
-typedef struct {
- u16 Attribute; /**< Attributes of descriptor */
- u16 Length; /**< Length of current dma transfer */
- u32 Address; /**< Address of current dma transfer */
-#ifdef __ICCARM__
-#pragma data_alignment = 32
-} XSdPs_Adma2Descriptor32;
-#else
-} __attribute__((__packed__))XSdPs_Adma2Descriptor32;
-#endif
-
-/**
- * ADMA2 64-Bit descriptor table
- */
-typedef struct {
- u16 Attribute; /**< Attributes of descriptor */
- u16 Length; /**< Length of current dma transfer */
- u64 Address; /**< Address of current dma transfer */
-#ifdef __ICCARM__
-#pragma data_alignment = 32
-} XSdPs_Adma2Descriptor64;
-#else
-} __attribute__((__packed__))XSdPs_Adma2Descriptor64;
-#endif
-
-/**
- * The XSdPs driver instance data. The user is required to allocate a
- * variable of this type for every SD device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XSdPs_Config Config; /**< Configuration structure */
- u32 IsReady; /**< Device is initialized and ready */
- u32 Host_Caps; /**< Capabilities of host controller */
- u32 Host_CapsExt; /**< Extended Capabilities */
- u32 HCS; /**< High capacity support in card */
- u8 CardType; /**< Type of card - SD/MMC/eMMC */
- u8 Card_Version; /**< Card version */
- u8 HC_Version; /**< Host controller version */
- u8 BusWidth; /**< Current operating bus width */
- u32 BusSpeed; /**< Current operating bus speed */
- u8 Switch1v8; /**< 1.8V Switch support */
- u32 CardID[4]; /**< Card ID Register */
- u32 RelCardAddr; /**< Relative Card Address */
- u32 CardSpecData[4]; /**< Card Specific Data Register */
- u32 SectorCount; /**< Sector Count */
- u32 SdCardConfig; /**< Sd Card Configuration Register */
- u32 Mode; /**< Bus Speed Mode */
- u32 OTapDelay; /**< Output Tap Delay */
- u32 ITapDelay; /**< Input Tap Delay */
- u64 Dma64BitAddr; /**< 64 Bit DMA Address */
- u16 TransferMode; /**< Transfer Mode */
- u32 SlcrBaseAddr; /**< SLCR base address*/
- u8 IsBusy; /**< Busy Flag*/
- u32 BlkSize; /**< Block Size*/
-} XSdPs;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-/**
- * @name SD High Speed mode configuration options
- * @{
- */
-/**
- * User configuration option to enable or disable SD HS mode.
- * By default SD HS mode is disabled for Versal and enabled for
- * other platforms.
- */
-#ifdef versal
-#define SD_HS_MODE_ENABLE 0
-#else
-#define SD_HS_MODE_ENABLE 1
-#endif
-/** @} */
-
-/************************** Function Prototypes ******************************/
-XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
-s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
- u32 EffectiveAddr);
-s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
-s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
-s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
-s32 XSdPs_Idle(XSdPs *InstancePtr);
-
-s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr);
-s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq);
-s32 XSdPs_Pullup(XSdPs *InstancePtr);
-s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *ReadBuff);
-s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr);
-s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff);
-s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
-s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg);
-s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize);
-s32 XSdPs_Get_Status(XSdPs *InstancePtr, u8 *SdStatReg);
-s32 XSdPs_Select_Card(XSdPs *InstancePtr);
-s32 XSdPs_StartReadTransfer(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
-s32 XSdPs_CheckReadTransfer(XSdPs *InstancePtr);
-s32 XSdPs_StartWriteTransfer(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
-s32 XSdPs_CheckWriteTransfer(XSdPs *InstancePtr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SD_H_ */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ea/c08b23575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ea/c08b23575243001d18b399c1eb9b3628
deleted file mode 100644
index 5feeb49..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ea/c08b23575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,39 +0,0 @@
-DRIVER_LIB_VERSION = 1.0
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I$(INCLUDEDIR)
-
-SRCFILES:=$(wildcard *.c)
-
-OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
-
-libs: $(OBJECTS)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf $(DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ea/c0d993575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ea/c0d993575243001d18b399c1eb9b3628
deleted file mode 100644
index d986349..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ea/c0d993575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,240 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm_gcc.h
-*
-* This header file contains macros for using inline assembler code. It is
-* written specifically for the GNU compiler.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 05/21/14 First release
-* 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors
-* 7.2 asa 04/03/20 Renamed the str macro to strw.
-* 7.2 dp 04/30/20 Added clobber "cc" to mtcpsr for aarch32 processors
-*
- *
- * The Spartan-3AF Embedded Peripheral Block contains a USB controller for
- * communication with serial peripherals or hosts. The USB controller supports
- * Host, Device and On the Go (OTG) applications.
- *
- *
USB Controller Features
- *
- * - Supports Low Speed USB 1.1 (1.5Mbps), Full Speed USB 1.1 (12Mbps), and
- * High Speed USB 2.0 (480Mbps) data speeds
- * - Supports Device, Host and OTG operational modes
- * - ULPI transceiver interface for USB 2.0 operation
- * - Integrated USB Full and Low speed serial transceiver interfaces for lowest
- * cost connections
- *
- *
Initialization & Configuration
- *
- * The configuration of the USB driver happens in multiple stages:
- *
- * - (a) Configuration of the basic parameters:
- * In this stage the basic parameters for the driver are configured,
- * including the base address and the controller ID.
- *
- * - (b) Configuration of the DEVICE endpoints (if applicable):
- * If DEVICE mode is desired, the endpoints of the controller need to be
- * configured using the XUsbPs_DeviceConfig data structure. Once the
- * endpoint configuration is set up in the data structure, The user then
- * needs to allocate the required amount of DMAable memory and
- * finalize the configuration of the XUsbPs_DeviceConfig data structure,
- * e.g. setting the DMAMemVirt and DMAMemPhys members.
- *
- * - (c) Configuration of the DEVICE modes:
- * In the second stage the parameters for DEVICE are configured.
- * The caller only needs to configure the modes that are
- * actually used. Configuration is done with the:
- * XUsbPs_ConfigureDevice()
- * Configuration parameters are defined and passed
- * into these functions using the:
- * XUsbPs_DeviceConfig data structures.
- *
- *
- *
USB Device Endpoints
- *
- * The USB core supports up to 4 endpoints. Each endpoint has two directions,
- * an OUT (RX) and an IN (TX) direction. Note that the direction is viewed from
- * the host's perspective. Endpoint 0 defaults to be the control endpoint and
- * does not need to be set up. Other endpoints need to be configured and set up
- * depending on the application. Only endpoints that are actuelly used by the
- * application need to be initialized.
- * See the example code (xusbps_intr_example.c) for more information.
- *
- *
- *
Interrupt Handling
- *
- * The USB core uses one interrupt line to report interrupts to the CPU.
- * Interrupts are handled by the driver's interrupt handler function
- * XUsbPs_IntrHandler().
- * It has to be registered with the OS's interrupt subsystem. The driver's
- * interrupt handler divides incoming interrupts into two categories:
- *
- * - General device interrupts
- * - Endopint related interrupts
- *
- * The user (typically the adapter layer) can register general interrupt
- * handler functions and endpoint specific interrupt handler functions with the
- * driver to receive those interrupts by calling the
- * XUsbPs_IntrSetHandler()
- * and
- * XUsbPs_EpSetHandler()
- * functions respectively. Calling these functions with a NULL pointer as the
- * argument for the function pointer will "clear" the handler function.
- *
- * The user can register one handler function for the generic interrupts and
- * two handler functions for each endpoint, one for the RX (OUT) and one for
- * the TX (IN) direction. For some applications it may be useful to register a
- * single endpoint handler function for muliple endpoints/directions.
- *
- * When a callback function is called by the driver, parameters identifying the
- * type of the interrupt will be passed into the handler functions. For general
- * interrupts the interrupt mask will be passed into the handler function. For
- * endpoint interrupts the parameters include the number of the endpoint, the
- * direction (OUT/IN) and the type of the interrupt.
- *
- *
- *
Data buffer handling
- *
- * Data buffers are sent to and received from endpoint using the
- * XUsbPs_EpBufferSend(), XUsbPs_EpBufferSendWithZLT()
- * and
- * XUsbPs_EpBufferReceive()
- * functions.
- *
- * User data buffer size is limited to 16 Kbytes. If the user wants to send a
- * data buffer that is bigger than this limit it needs to break down the data
- * buffer into multiple fragments and send the fragments individually.
- *
- * From the controller perspective Data buffers can be aligned at any boundary.
- * if the buffers are from cache region then the buffer and buffer size should
- * be aligned to cache line aligned
- *
- *
- *
Zero copy
- *
- * The driver uses a zero copy mechanism which imposes certain restrictions to
- * the way the user can handle the data buffers.
- *
- * One restriction is that the user needs to release a buffer after it is done
- * processing the data in the buffer.
- *
- * Similarly, when the user sends a data buffer it MUST not re-use the buffer
- * until it is notified by the driver that the buffer has been transmitted. The
- * driver will notify the user via the registered endpoint interrupt handling
- * function by sending a XUSBPS_EP_EVENT_DATA_TX event.
- *
- *
- *
DMA
- *
- * The driver uses DMA internally to move data from/to memory. This behaviour
- * is transparent to the user. Keeping the DMA handling hidden from the user
- * has the advantage that the same API can be used with USB cores that do not
- * support DMA.
- *
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- ----------------------------------------------------------
- * 1.00a wgr 10/10/10 First release
- * 1.02a wgr 05/16/12 Removed comments as they are showing up in SDK
- * Tabs for CR 657898
- * 1.03a nm 09/21/12 Fixed CR#678977. Added proper sequence for setup packet
- * handling.
- * 1.04a nm 10/23/12 Fixed CR# 679106.
- * 11/02/12 Fixed CR# 683931. Mult bits are set properly in dQH.
- * 2.00a kpc 04/03/14 Fixed CR#777763. Corrected the setup tripwire macro val.
- * 2.1 kpc 04/28/14 Removed unused function prototypes
- * 2.2 kpc 08/23/14 Exported XUsbPs_DeviceReset API as global for calling in
- * code coverage tests.
- * 2.3 kpc 02/19/14 Fixed CR#873972, CR#873974. Corrected the logic for proper
- * moving of dTD Head/Tail Pointers. Invalidate the cache
- * after buffer receive in Endpoint Buffer Handler.
- * 2.4 sg 04/26/16 Fixed CR#949693, Corrected the logic for EP flush
- * ms 03/17/17 Added readme.txt file in examples folder for doxygen
- * generation.
- * ms 04/10/17 Modified filename tag to include the file in doxygen
- * examples.
- * 2.5 pm 02/20/20 Added ISO support for usb 2.0 and ch9 common framework
- * calls.
- *
- *
- ******************************************************************************/
-
-#ifndef XUSBPS_H
-#define XUSBPS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xusbps_hw.h"
-#include "xil_types.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions *****************************/
-
-/**
- * @name System hang prevention Timeout counter value.
- *
- * This value is used throughout the code to initialize a Timeout counter that
- * is used when hard polling a register. The ides is to initialize the Timeout
- * counter to a value that is longer than any expected Timeout but short enough
- * so the system will continue to work and report an error while the user is
- * still paying attention. A reasonable Timeout time would be about 10 seconds.
- * The XUSBPS_TIMEOUT_COUNTER value should be chosen so a polling loop would
- * run about 10 seconds before a Timeout is detected. For example:
- *
- * int Timeout = XUSBPS_TIMEOUT_COUNTER;
- * while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
- * XUSBPS_CMD_OFFSET) &
- * XUSBPS_CMD_RST_MASK) && --Timeout) {
- * ;
- * }
- * if (0 == Timeout) {
- * return XST_FAILURE;
- * }
- *
- */
-#define XUSBPS_TIMEOUT_COUNTER 1000000
-
-
-/**
- * @name Endpoint Direction (bitmask)
- * Definitions to be used with Endpoint related function that require a
- * 'Direction' parameter.
- *
- * NOTE:
- * The direction is always defined from the perspective of the HOST! This
- * means that an IN endpoint on the controller is used for sending data while
- * the OUT endpoint on the controller is used for receiving data.
- * @{
- */
-#define XUSBPS_EP_DIRECTION_IN 0x01 /**< Endpoint direction IN. */
-#define XUSBPS_EP_DIRECTION_OUT 0x02 /**< Endpoint direction OUT. */
-/* @} */
-
-
-/**
- * @name Endpoint Type
- * Definitions to be used with Endpoint related functions that require a 'Type'
- * parameter.
- * @{
- */
-#define XUSBPS_EP_TYPE_NONE 0 /**< Endpoint is not used. */
-#define XUSBPS_EP_TYPE_CONTROL 1 /**< Endpoint for Control Transfers */
-#define XUSBPS_EP_TYPE_ISOCHRONOUS 2 /**< Endpoint for isochronous data */
-#define XUSBPS_EP_TYPE_BULK 3 /**< Endpoint for BULK Transfers. */
-#define XUSBPS_EP_TYPE_INTERRUPT 4 /**< Endpoint for interrupt Transfers */
-/* @} */
-
-/**
- * Endpoint Max Packet Length in DeviceConfig is a coded value, ch9.6.6.
- *
- * @{
- */
-#define ENDPOINT_MAXP_LENGTH 0x400
-#define ENDPOINT_MAXP_MULT_MASK 0xC00
-#define ENDPOINT_MAXP_MULT_SHIFT 10
-/* @} */
-
-/**
- * @name Field names for status retrieval
- * Definitions for the XUsbPs_GetStatus() function call 'StatusType'
- * parameter.
- * @{
- */
-#define XUSBPS_EP_STS_ADDRESS 1 /**< Address of controller. */
-#define XUSBPS_EP_STS_CONTROLLER_STATE 2 /**< Current controller state. */
-/* @} */
-
- /*
- * Device Speeds
- */
- #define XUSBPS_SPEED_UNKNOWN 0U
- #define XUSBPS_SPEED_LOW 1U
- #define XUSBPS_SPEED_FULL 2U
- #define XUSBPS_SPEED_HIGH 3U
-
-/**
- * @name USB Default alternate setting
- *
- * @{
- */
-#define XUSBPS_DEFAULT_ALT_SETTING 0 /**< The default alternate setting is 0 */
-/* @} */
-
- /*
- * Device States
- */
- #define XUSBPS_STATE_ATTACHED 0U
- #define XUSBPS_STATE_POWERED 1U
- #define XUSBPS_STATE_DEFAULT 2U
- #define XUSBPS_STATE_ADDRESS 3U
- #define XUSBPS_STATE_CONFIGURED 4U
- #define XUSBPS_STATE_SUSPENDED 5U
-
-/**
- * @name Endpoint event types
- * Definitions that are used to identify events that occur on endpoints. Passed
- * to the endpoint event handler functions registered with
- * XUsbPs_EpSetHandler().
- * @{
- */
-#define XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED 0x01
- /**< Setup data has been received on the endpoint. */
-#define XUSBPS_EP_EVENT_DATA_RX 0x02
- /**< Data frame has been received on the endpoint. */
-#define XUSBPS_EP_EVENT_DATA_TX 0x03
- /**< Data frame has been sent on the endpoint. */
-/* @} */
-
-
-/*
- * Maximum packet size for endpoint, 1024
- * @{
- */
-#define XUSBPS_MAX_PACKET_SIZE 1024
- /**< Maximum value can be put into the queue head */
-/* @} */
-/**************************** Type Definitions *******************************/
-
-/******************************************************************************
- * This data type defines the callback function to be used for Endpoint
- * handlers.
- *
- * @param CallBackRef is the Callback reference passed in by the upper
- * layer when setting the handler, and is passed back to the upper
- * layer when the handler is called.
- * @param EpNum is the Number of the endpoint that caused the event.
- * @param EventType is the type of the event that occurred on the endpoint.
- * @param Data is a pointer to user data pointer specified when callback
- * was registered.
- */
-typedef void (*XUsbPs_EpHandlerFunc)(void *CallBackRef,
- u8 EpNum, u8 EventType, void *Data);
-
-/******************************************************************************
- * This data type defines the callback function to be used for Endpoint
- * handlers.
- *
- * @param CallBackRef is the Callback reference passed in by the upper
- * layer when setting the handler, and is passed back to the upper
- * layer when the handler is called.
- * @param RequestedBytes is the number of bytes requested to transfer.
- * @param BytesTxed is the actual number of bytes to be transfer.
- */
-typedef void (*XUsbPs_EpIsoHandlerFunc)(void *CallBackRef,
- u32 RequestedBytes, u32 BytesTxed);
-
-/******************************************************************************
- * This data type defines the callback function to be used for the general
- * interrupt handler.
- *
- * @param CallBackRef is the Callback reference passed in by the upper
- * layer when setting the handler, and is passed back to the upper
- * layer when the handler is called.
- * @param IrqMask is the Content of the interrupt status register. This
- * value can be used by the callback function to distinguish the
- * individual interrupt types.
- */
-typedef void (*XUsbPs_IntrHandlerFunc)(void *CallBackRef, u32 IrqMask);
-
-
-/******************************************************************************/
-
-/* The following type definitions are used for referencing Queue Heads and
- * Transfer Descriptors. The structures themselves are not used, however, the
- * types are used in the API to avoid using (void *) pointers.
- */
-typedef u8 XUsbPs_dQH[XUSBPS_dQH_ALIGN];
-typedef u8 XUsbPs_dTD[XUSBPS_dTD_ALIGN];
-
-
-/**
- * The following data structures are used internally by the L0/L1 driver.
- * Their contents MUST NOT be changed by the upper layers.
- */
-
-/**
- * The following data structure represents OUT endpoint.
- */
-typedef struct {
- XUsbPs_dQH *dQH;
- /**< Pointer to the Queue Head structure of the endpoint. */
-
- XUsbPs_dTD *dTDs;
- /**< Pointer to the first dTD of the dTD list for this
- * endpoint. */
-
- XUsbPs_dTD *dTDCurr;
- /**< Buffer to the currently processed descriptor. */
-
- u8 *dTDBufs;
- /**< Pointer to the first buffer of the buffer list for this
- * endpoint. */
-
- XUsbPs_EpHandlerFunc HandlerFunc;
- XUsbPs_EpIsoHandlerFunc HandlerIsoFunc;
- /**< Handler function for this endpoint. */
- void *HandlerRef;
- /**< User data reference for the handler. */
- u32 RequestedBytes; /**< RequestedBytes for transfer */
- u32 BytesTxed; /**< Actual Bytes transferred */
- u8 *BufferPtr; /**< Buffer location */
- u8 MemAlloted; /**< Mem alloted and data is not received */
- u32 Interval; /**< Data transfer service interval */
-} XUsbPs_EpOut;
-
-
-/**
- * The following data structure represents IN endpoint.
- */
-typedef struct {
- XUsbPs_dQH *dQH;
- /**< Pointer to the Queue Head structure of the endpoint. */
-
- XUsbPs_dTD *dTDs;
- /**< List of pointers to the Transfer Descriptors of the
- * endpoint. */
-
- XUsbPs_dTD *dTDHead;
- /**< Buffer to the next available descriptor in the list. */
-
- XUsbPs_dTD *dTDTail;
- /**< Buffer to the last unsent descriptor in the list*/
-
- XUsbPs_EpHandlerFunc HandlerFunc;
- XUsbPs_EpIsoHandlerFunc HandlerIsoFunc;
- /**< Handler function for this endpoint. */
- void *HandlerRef;
- /**< User data reference for the handler. */
- u32 RequestedBytes; /**< RequestedBytes for transfer */
- u32 BytesTxed; /**< Actual Bytes transferred */
- u8 *BufferPtr; /**< Buffer location */
- u32 Interval; /**< Data transfer service interval */
-} XUsbPs_EpIn;
-
-
-/**
- * The following data structure represents an endpoint used internally
- * by the L0/L1 driver.
- */
-typedef struct {
- /* Each endpoint has an OUT and an IN component.
- */
- XUsbPs_EpOut Out; /**< OUT endpoint structure */
- XUsbPs_EpIn In; /**< IN endpoint structure */
-} XUsbPs_Endpoint;
-
-
-
-/**
- * The following structure is used by the user to receive Setup Data from an
- * endpoint. Using this structure simplifies the process of interpreting the
- * setup data in the core's data fields.
- *
- * The naming scheme for the members of this structure is different from the
- * naming scheme found elsewhere in the code. The members of this structure are
- * defined in the Chapter 9 USB reference guide. Using this naming scheme makes
- * it easier for people familiar with the standard to read the code.
- */
-typedef struct {
- u8 bmRequestType; /**< bmRequestType in setup data */
- u8 bRequest; /**< bRequest in setup data */
- u16 wValue; /**< wValue in setup data */
- u16 wIndex; /**< wIndex in setup data */
- u16 wLength; /**< wLength in setup data */
-}
-XUsbPs_SetupData;
-
-
-/**
- * Data structures used to configure endpoints.
- */
-typedef struct {
- u32 Type;
- /**< Endpoint type:
- - XUSBPS_EP_TYPE_CONTROL
- - XUSBPS_EP_TYPE_ISOCHRONOUS
- - XUSBPS_EP_TYPE_BULK
- - XUSBPS_EP_TYPE_INTERRUPT */
-
- u32 NumBufs;
- /**< Number of buffers to be handled by this endpoint. */
- u32 BufSize;
- /**< Buffer size. Only relevant for OUT (receive) Endpoints. */
-
- u16 MaxPacketSize;
- /**< Maximum packet size for this endpoint. This number will
- * define the maximum number of bytes sent on the wire per
- * transaction. Range: 0..1024 */
-} XUsbPs_EpSetup;
-
-
-/**
- * Endpoint configuration structure.
- */
-typedef struct {
- XUsbPs_EpSetup Out; /**< OUT component of endpoint. */
- XUsbPs_EpSetup In; /**< IN component of endpoint. */
-} XUsbPs_EpConfig;
-
-
-/**
- * The XUsbPs_DeviceConfig structure contains the configuration information to
- * configure the USB controller for DEVICE mode. This data structure is used
- * with the XUsbPs_ConfigureDevice() function call.
- */
-typedef struct {
- u8 NumEndpoints; /**< Number of Endpoints for the controller.
- This number depends on the runtime
- configuration of driver. The driver may
- configure fewer endpoints than are available
- in the core. */
-
- XUsbPs_EpConfig EpCfg[XUSBPS_MAX_ENDPOINTS];
- /**< List of endpoint configurations. */
-
-
- u32 DMAMemPhys; /**< Physical base address of DMAable memory
- allocated for the driver. */
-
- /* The following members are used internally by the L0/L1 driver. They
- * MUST NOT be accesses and/or modified in any way by the upper layers.
- *
- * The reason for having these members is that we generally try to
- * avoid allocating memory in the L0/L1 driver as we want to be OS
- * independent. In order to avoid allocating memory for this data
- * structure wihin L0/L1 we put it into the XUsbPs_DeviceConfig
- * structure which is allocated by the caller.
- */
- XUsbPs_Endpoint Ep[XUSBPS_MAX_ENDPOINTS];
- /**< List of endpoint metadata structures. */
-
- u32 PhysAligned; /**< 64 byte aligned base address of the DMA
- memory block. Will be computed and set by
- the L0/L1 driver. */
-} XUsbPs_DeviceConfig;
-
-
-/**
- * The XUsbPs_Config structure contains configuration information for the USB
- * controller.
- *
- * This structure only contains the basic configuration for the controller. The
- * caller also needs to initialize the controller for the DEVICE mode
- * using the XUsbPs_DeviceConfig data structures with the
- * XUsbPs_ConfigureDevice() function call
- */
-typedef struct {
- u16 DeviceID; /**< Unique ID of controller. */
- u32 BaseAddress; /**< Core register base address. */
-} XUsbPs_Config;
-
-typedef XUsbPs_Config Usb_Config;
-
-struct Usb_DevData {
- u8 Speed;
- u8 State;
-
- void *PrivateData;
-};
-
-/**
- * The XUsbPs driver instance data. The user is required to allocate a
- * variable of this type for every USB controller in the system. A pointer to a
- * variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XUsbPs_SetupData SetupData;
- /**< Setup Packet buffer */
- XUsbPs_Config Config; /**< Configuration structure */
-
- int CurrentAltSetting; /**< Current alternative setting of interface */
-
- void *UserDataPtr; /**< Data pointer to be used by upper layers to
- store application dependent data structures.
- The upper layers are responsible to allocated
- and free the memory. The driver will not
- mofidy this data pointer. */
-
- /**
- * The following structures hold the configuration for DEVICE mode
- * of the controller. They are initialized using the
- * XUsbPs_ConfigureDevice() function call.
- */
- XUsbPs_DeviceConfig DeviceConfig;
- /**< Configuration for the DEVICE mode. */
-
- XUsbPs_IntrHandlerFunc HandlerFunc;
- /**< Handler function for the controller. */
- void *HandlerRef;
- /**< User data reference for the handler. */
- u32 HandlerMask;
- /**< User interrupt mask. Defines which interrupts will cause
- * the callback to be called. */
- struct Usb_DevData *AppData;
- u8 IsConfigDone;
- void *data_ptr; /* pointer for storing applications data */
-} XUsbPs;
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/******************************************************************************
- *
- * USB CONTROLLER RELATED MACROS
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
- * This macro returns the current frame number.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @return The current frame number.
- *
- * @note C-style signature:
- * u32 XUsbPs_GetFrameNum(const XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_GetFrameNum(InstancePtr) \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, XUSBPS_FRAME_OFFSET)
-
-
-/*****************************************************************************/
-/**
- * This macro starts the USB engine.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @note C-style signature:
- * void XUsbPs_Start(XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_Start(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
-
-
-/*****************************************************************************/
-/**
- * This macro stops the USB engine.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @note C-style signature:
- * void XUsbPs_Stop(XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_Stop(InstancePtr) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
-
-
-/*****************************************************************************/
-/**
- * This macro forces the USB engine to be in Full Speed (FS) mode.
- *
- * @param InstancePtr is a pointer to the XUsbPs instance of the
- * controller.
- *
- * @note C-style signature:
- * void XUsbPs_ForceFS(XUsbPs *InstancePtr)
- *
- ******************************************************************************/
-#define XUsbPs_ForceFS(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
- XUSBPS_PORTSCR_PFSC_MASK)
-
-
-/*****************************************************************************/
-/**
- * This macro starts the USB Timer 0, with repeat option for period of
- * one second.
- *
- * @param InstancePtr is a pointer to XUsbPs instance of the controller.
- * @param Interval is the interval for Timer0 to generate an interrupt
- *
- * @note C-style signature:
- * void XUsbPs_StartTimer0(XUsbPs *InstancePtr, u32 Interval)
- *
- ******************************************************************************/
-#define XUsbPs_StartTimer0(InstancePtr, Interval) \
-{ \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_TIMER0_LD_OFFSET, (Interval)); \
- XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
- XUSBPS_TIMER_RUN_MASK | \
- XUSBPS_TIMER_RESET_MASK | \
- XUSBPS_TIMER_REPEAT_MASK); \
-} \
-
-
-/*****************************************************************************/
-/**
-* This macro stops Timer 0.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_StopTimer0(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_StopTimer0(InstancePtr) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \
- XUSBPS_TIMER_RUN_MASK)
-
-
-/*****************************************************************************/
-/**
-* This macro reads Timer 0.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_ReadTimer0(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_ReadTimer0(InstancePtr) \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_TIMER0_CTL_OFFSET) & \
- XUSBPS_TIMER_COUNTER_MASK
-
-
-/*****************************************************************************/
-/**
-* This macro force remote wakeup on host
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_RemoteWakeup(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_RemoteWakeup(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \
- XUSBPS_PORTSCR_FPR_MASK)
-
-
-/******************************************************************************
- *
- * ENDPOINT RELATED MACROS
- *
- ******************************************************************************/
-/*****************************************************************************/
-/**
-* This macro enables the given endpoint for the given direction.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is number of the endpoint to enable.
-* @param Dir is direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpEnable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpEnable(InstancePtr, EpNum, Dir) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro disables the given endpoint for the given direction.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is the number of the endpoint to disable.
-* @param Dir is the direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpDisable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpDisable(InstancePtr, EpNum, Dir) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro stalls the given endpoint for the given direction, and flush
-* the buffers.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is number of the endpoint to stall.
-* @param Dir is the direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpStall(InstancePtr, EpNum, Dir) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro unstalls the given endpoint for the given direction.
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is the Number of the endpoint to unstall.
-* @param Dir is the Direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpUnStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpUnStall(InstancePtr, EpNum, Dir) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \
- ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
- ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0))
-
-
-/*****************************************************************************/
-/**
-* This macro flush an endpoint upon interface disable
-*
-* @param InstancePtr is a pointer to the XUsbPs instance of the
-* controller.
-* @param EpNum is the number of the endpoint to flush.
-* @param Dir is the direction of the endpoint (bitfield):
-* - XUSBPS_EP_DIRECTION_OUT
-* - XUSBPS_EP_DIRECTION_IN
-*
-* @note C-style signature:
-* void XUsbPs_EpFlush(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
-*
-******************************************************************************/
-#define XUsbPs_EpFlush(InstancePtr, EpNum, Dir) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPFLUSH_OFFSET, \
- 1 << (EpNum + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? \
- XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT))) \
-
-/*****************************************************************************/
-/**
-* This macro enables the interrupts defined by the bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param IntrMask is the Bit mask of interrupts to be enabled.
-*
-* @note C-style signature:
-* void XUsbPs_IntrEnable(XUsbPs *InstancePtr, u32 IntrMask)
-*
-******************************************************************************/
-#define XUsbPs_IntrEnable(InstancePtr, IntrMask) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
-
-
-/*****************************************************************************/
-/**
-* This function disables the interrupts defined by the bit mask.
-*
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param IntrMask is a Bit mask of interrupts to be disabled.
-*
-* @note C-style signature:
-* void XUsbPs_IntrDisable(XUsbPs *InstancePtr, u32 IntrMask)
-*
-******************************************************************************/
-#define XUsbPs_IntrDisable(InstancePtr, IntrMask) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
-
-
-/*****************************************************************************/
-/**
-* This macro enables the endpoint NAK interrupts defined by the bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be
-* enabled.
-* @note C-style signature:
-* void XUsbPs_NakIntrEnable(XUsbPs *InstancePtr, u32 NakIntrMask)
-*
-******************************************************************************/
-#define XUsbPs_NakIntrEnable(InstancePtr, NakIntrMask) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
-
-
-/*****************************************************************************/
-/**
-* This macro disables the endpoint NAK interrupts defined by the bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param NakIntrMask is a Bit mask of endpoint NAK interrupts to be
-* disabled.
-*
-* @note
-* C-style signature:
-* void XUsbPs_NakIntrDisable(XUsbPs *InstancePtr, u32 NakIntrMask)
-*
-******************************************************************************/
-#define XUsbPs_NakIntrDisable(InstancePtr, NakIntrMask) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
-
-
-/*****************************************************************************/
-/**
-* This function clears the endpoint NAK interrupts status defined by the
-* bit mask.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be cleared.
-*
-* @note C-style signature:
-* void XUsbPs_NakIntrClear(XUsbPs *InstancePtr, u32 NakIntrMask)
-*
-******************************************************************************/
-#define XUsbPs_NakIntrClear(InstancePtr, NakIntrMask) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_EPNAKISR_OFFSET, NakIntrMask)
-
-
-
-/*****************************************************************************/
-/**
-* This macro sets the Interrupt Threshold value in the control register
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param Threshold is the Interrupt threshold to be set.
-* Allowed values:
-* - XUSBPS_CMD_ITHRESHOLD_0 - Immediate interrupt
-* - XUSBPS_CMD_ITHRESHOLD_1 - 1 Frame
-* - XUSBPS_CMD_ITHRESHOLD_2 - 2 Frames
-* - XUSBPS_CMD_ITHRESHOLD_4 - 4 Frames
-* - XUSBPS_CMD_ITHRESHOLD_8 - 8 Frames
-* - XUSBPS_CMD_ITHRESHOLD_16 - 16 Frames
-* - XUSBPS_CMD_ITHRESHOLD_32 - 32 Frames
-* - XUSBPS_CMD_ITHRESHOLD_64 - 64 Frames
-*
-* @note
-* C-style signature:
-* void XUsbPs_SetIntrThreshold(XUsbPs *InstancePtr, u8 Threshold)
-*
-******************************************************************************/
-#define XUsbPs_SetIntrThreshold(InstancePtr, Threshold) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_CMD_OFFSET, (Threshold))\
-
-
-/*****************************************************************************/
-/**
-* This macro sets the Tripwire bit in the USB command register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_SetTripwire(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_SetSetupTripwire(InstancePtr) \
- XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, \
- XUSBPS_CMD_SUTW_MASK)
-
-
-/*****************************************************************************/
-/**
-* This macro clears the Tripwire bit in the USB command register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @note C-style signature:
-* void XUsbPs_ClrTripwire(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_ClrSetupTripwire(InstancePtr) \
- XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, \
- XUSBPS_CMD_SUTW_MASK)
-
-
-/*****************************************************************************/
-/**
-* This macro checks if the Tripwire bit in the USB command register is set.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-*
-* @return
-* - TRUE: The tripwire bit is still set.
-* - FALSE: The tripwire bit has been cleared.
-*
-* @note C-style signature:
-* int XUsbPs_TripwireIsSet(XUsbPs *InstancePtr)
-*
-******************************************************************************/
-#define XUsbPs_SetupTripwireIsSet(InstancePtr) \
- (XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- XUSBPS_CMD_OFFSET) & \
- XUSBPS_CMD_SUTW_MASK ? TRUE : FALSE)
-
-
-/******************************************************************************
-*
-* GENERAL REGISTER / BIT MANIPULATION MACROS
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-* This macro sets the given bit mask in the register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param RegOffset is the register offset to be written.
-* @param Bits is the Bits to be set in the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XUsbPs_SetBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
-*
-*****************************************************************************/
-#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- RegOffset) | (Bits));
-
-
-/****************************************************************************/
-/**
-*
-* This macro clears the given bits in the register.
-*
-* @param InstancePtr is a pointer to XUsbPs instance of the controller.
-* @param RegOffset is the register offset to be written.
-* @param Bits are the bits to be cleared in the register
-*
-* @return None.
-*
-* @note
-* C-style signature:
-* void XUsbPs_ClrBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
-*
-*****************************************************************************/
-#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits) \
- XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \
- XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \
- RegOffset) & ~(Bits));
-
-
-/************************** Function Prototypes ******************************/
-
-/**
- * Setup / Initialize functions.
- *
- * Implemented in file xusbps.c
- */
-int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
- const XUsbPs_Config *ConfigPtr, u32 BaseAddress);
-
-int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr,
- const XUsbPs_DeviceConfig *CfgPtr);
-
-/**
- * Common functions used for DEVICE/HOST mode.
- */
-int XUsbPs_Reset(XUsbPs *InstancePtr);
-
-void XUsbPs_DeviceReset(XUsbPs *InstancePtr);
-
-/**
- * DEVICE mode specific functions.
- */
-int XUsbPs_BusReset(XUsbPs *InstancePtr);
-int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address);
-
-
-/**
- * Handling Suspend and Resume.
- *
- * Implemented in xusbps.c
- */
-int XUsbPs_Suspend(const XUsbPs *InstancePtr);
-int XUsbPs_Resume(const XUsbPs *InstancePtr);
-int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr);
-
-
-/*
- * Functions for managing Endpoints / Transfers
- *
- * Implemented in file xusbps_endpoint.c
- */
-int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum,
- const u8 *BufferPtr, u32 BufferLen);
-int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum,
- const u8 *BufferPtr, u32 BufferLen);
-int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
- u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle);
-void XUsbPs_EpBufferRelease(u32 Handle);
-
-int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
- XUsbPs_EpHandlerFunc CallBackFunc,
- void *CallBackRef);
-s32 XUsbPs_EpSetIsoHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
- XUsbPs_EpIsoHandlerFunc CallBackFunc);
-int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum,
- XUsbPs_SetupData *SetupDataPtr);
-
-int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction);
-
-int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr,
- int EpNum, unsigned short NewDirection, int DirectionChanged);
-
-/*
- * Interrupt handling functions
- *
- * Implemented in file xusbps_intr.c
- */
-void XUsbPs_IntrHandler(void *InstancePtr);
-
-int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
- XUsbPs_IntrHandlerFunc CallBackFunc,
- void *CallBackRef, u32 Mask);
-void XUsbPs_EpGetData(XUsbPs *InstancePtr, u8 EpNum, u32 BufferLen);
-
-s32 XUsbPs_EpDataBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
- u8 *BufferPtr, u32 BufferLen);
-/*
- * Helper functions for static configuration.
- * Implemented in xusbps_sinit.c
- */
-XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceId);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XUSBPS_H */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/eb/5089e7555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/eb/5089e7555243001d18b399c1eb9b3628
deleted file mode 100644
index 0c4863d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/eb/5089e7555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,473 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file boot.S
-*
-* @addtogroup a9_boot_code Cortex A9 Processor Boot Code
-* @{
-*
boot.S
-* The boot code performs minimum configuration which is required for an
-* application to run starting from processor reset state of the processor. Below is a
-* sequence illustrating what all configuration is performed before control
-* reaches to main function.
-*
-* 1. Program vector table base for exception handling
-* 2. Invalidate instruction cache, data cache and TLBs
-* 3. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine,
-* abort, system)
-* 4. Configure MMU with short descriptor translation table format and program
-* base address of translation table
-* 5. Enable data cache, instruction cache and MMU
-* 6. Enable Floating point unit
-* 7. Transfer control to _start which clears BSS sections, initializes
-* global timer and runs global constructor before jumping to main
-* application
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 1.00a ecm/sdm 10/20/09 Initial version
-* 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
-* register settings.
-* 3.06a asa 06/17/12 Modified the TTBR settings and L2 Cache auxiliary
-* register settings.
-* 3.07a asa 07/16/12 Modified the L2 Cache controller settings to improve
-* performance. Changed the property of the ".boot"
-* section.
-* 3.07a sgd 08/21/12 Modified the L2 Cache controller and cp15 Aux Control
-* Register settings
-* 3.09a sgd 02/06/13 Updated SLCR l2c Ram Control register to a
-* value of 0x00020202. Fix for CR 697094 (SI#687034).
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-* 4.2 pkp 06/19/14 Enabled asynchronous abort exception
-* 5.0 pkp 16/15/14 Modified initialization code to enable scu after
-* MMU is enabled
-* 5.1 pkp 05/13/15 Changed the initialization order so to first invalidate
-* caches and TLB, enable MMU and caches, then enable SMP
-* bit in ACTLR. L2Cache invalidation and enabling of L2Cache
-* is done later.
-* 5.4 asa 12/6/15 Added code to initialize SPSR for all relevant modes.
-* 6.0 mus 08/04/16 Added code to detect zynq-7000 base silicon configuration and
-* attempt to enable dual core behavior on single cpu zynq-7000s
-* devices is prevented from corrupting system behavior.
-* 6.0 mus 08/24/16 Check CPU core before putting cpu1 to reset for single core
-* zynq-7000s devices
-* 7.6 mus 09/02/21 SCU invalidation should be done only from primary CPU, so
-* skipping it when USE_AMP is set to 1. It fixes CR#1109723
-*
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#include "xparameters.h"
-#include "xil_errata.h"
-
-.globl MMUTable
-.global _prestart
-.global _boot
-.global __stack
-.global __irq_stack
-.global __supervisor_stack
-.global __abort_stack
-.global __fiq_stack
-.global __undef_stack
-.global _vector_table
-
-.set PSS_L2CC_BASE_ADDR, 0xF8F02000
-.set PSS_SLCR_BASE_ADDR, 0xF8000000
-
-.set RESERVED, 0x0fffff00
-.set TblBase , MMUTable
-.set LRemap, 0xFE00000F /* set the base address of the peripheral block as not shared */
-.set L2CCWay, (PSS_L2CC_BASE_ADDR + 0x077C) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)*/
-.set L2CCSync, (PSS_L2CC_BASE_ADDR + 0x0730) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)*/
-.set L2CCCrtl, (PSS_L2CC_BASE_ADDR + 0x0100) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)*/
-.set L2CCAuxCrtl, (PSS_L2CC_BASE_ADDR + 0x0104) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)*/
-.set L2CCTAGLatReg, (PSS_L2CC_BASE_ADDR + 0x0108) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)*/
-.set L2CCDataLatReg, (PSS_L2CC_BASE_ADDR + 0x010C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)*/
-.set L2CCIntClear, (PSS_L2CC_BASE_ADDR + 0x0220) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)*/
-.set L2CCIntRaw, (PSS_L2CC_BASE_ADDR + 0x021C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)*/
-
-.set SLCRlockReg, (PSS_SLCR_BASE_ADDR + 0x04) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/
-.set SLCRUnlockReg, (PSS_SLCR_BASE_ADDR + 0x08) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/
-.set SLCRL2cRamReg, (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/
-.set SLCRCPURSTReg, (0xF8000000 + 0x244) /*(XPS_SYS_CTRL_BASEADDR + A9_CPU_RST_CTRL_OFFSET)*/
-.set EFUSEStaus, (0xF800D000 + 0x10) /*(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)*/
-
-/* workaround for simulation not working when L1 D and I caches,MMU and L2 cache enabled - DT568997 */
-.if SIM_MODE == 1
-.set CRValMmuCac, 0b00000000000000 /* Disable IDC, and MMU */
-.else
-.set CRValMmuCac, 0b01000000000101 /* Enable IDC, and MMU */
-.endif
-
-.set CRValHiVectorAddr, 0b10000000000000 /* Set the Vector address to high, 0xFFFF0000 */
-
-.set L2CCAuxControl, 0x72360000 /* Enable all prefetching, Cache replacement policy, Parity enable,
- Event monitor bus enable and Way Size (64 KB) */
-.set L2CCControl, 0x01 /* Enable L2CC */
-.set L2CCTAGLatency, 0x0111 /* latency for TAG RAM */
-.set L2CCDataLatency, 0x0121 /* latency for DATA RAM */
-
-.set SLCRlockKey, 0x767B /* SLCR lock key */
-.set SLCRUnlockKey, 0xDF0D /* SLCR unlock key */
-.set SLCRL2cRamConfig, 0x00020202 /* SLCR L2C ram configuration */
-
-/* Stack Pointer locations for boot code */
-.set Undef_stack, __undef_stack
-.set FIQ_stack, __fiq_stack
-.set Abort_stack, __abort_stack
-.set SPV_stack, __supervisor_stack
-.set IRQ_stack, __irq_stack
-.set SYS_stack, __stack
-
-.set vector_base, _vector_table
-
-.set FPEXC_EN, 0x40000000 /* FPU enable bit, (1 << 30) */
-
-.section .boot,"ax"
-
-
-/* this initializes the various processor modes */
-
-_prestart:
-_boot:
-
-#if XPAR_CPU_ID==0
- /* only allow cpu0 through */
- mrc p15,0,r1,c0,c0,5
- and r1, r1, #0xf
- cmp r1, #0
- beq CheckEFUSE
- EndlessLoop0:
- wfe
- b EndlessLoop0
-
-CheckEFUSE:
- ldr r0,=EFUSEStaus
- ldr r1,[r0] /* Read eFuse setting */
- ands r1,r1,#0x80 /* Check whether device is having single core */
- beq OKToRun
-
- /* single core device, reset cpu1 */
- ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
- ldr r1,=SLCRUnlockKey /* set unlock key */
- str r1, [r0] /* Unlock SLCR */
-
- ldr r0,=SLCRCPURSTReg
- ldr r1,[r0] /* Read CPU Software Reset Control register */
- orr r1,r1,#0x22
- str r1,[r0] /* Reset CPU1 */
-
- ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
- ldr r1,=SLCRlockKey /* set lock key */
- str r1, [r0] /* lock SLCR */
-
-#elif XPAR_CPU_ID==1
- /* only allow cpu1 through */
- mrc p15,0,r1,c0,c0,5
- and r1, r1, #0xf
- cmp r1, #1
- beq CheckEFUSE1
- b EndlessLoop1
-
-CheckEFUSE1:
- ldr r0,=EFUSEStaus
- ldr r1,[r0] /* Read eFuse setting */
- ands r1,r1,#0x80 /* Check whether device is having single core */
- beq OKToRun
- EndlessLoop1:
- wfe
- b EndlessLoop1
-#endif
-
-OKToRun:
- mrc p15, 0, r0, c0, c0, 0 /* Get the revision */
- and r5, r0, #0x00f00000
- and r6, r0, #0x0000000f
- orr r6, r6, r5, lsr #20-4
-
-#ifdef CONFIG_ARM_ERRATA_742230
- cmp r6, #0x22 /* only present up to r2p2 */
- mrcle p15, 0, r10, c15, c0, 1 /* read diagnostic register */
- orrle r10, r10, #1 << 4 /* set bit #4 */
- mcrle p15, 0, r10, c15, c0, 1 /* write diagnostic register */
-#endif
-
-#ifdef CONFIG_ARM_ERRATA_743622
- teq r5, #0x00200000 /* only present in r2p* */
- mrceq p15, 0, r10, c15, c0, 1 /* read diagnostic register */
- orreq r10, r10, #1 << 6 /* set bit #6 */
- mcreq p15, 0, r10, c15, c0, 1 /* write diagnostic register */
-#endif
-
- /* set VBAR to the _vector_table address in linker script */
- ldr r0, =vector_base
- mcr p15, 0, r0, c12, c0, 0
-
- /*invalidate scu*/
-#if USE_AMP!=1
- ldr r7, =0xf8f0000c
- ldr r6, =0xffff
- str r6, [r7]
-#endif
-
- /* Invalidate caches and TLBs */
- mov r0,#0 /* r0 = 0 */
- mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
- mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
- mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */
- bl invalidate_dcache /* invalidate dcache */
-
- /* Disable MMU, if enabled */
- mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */
- bic r0, r0, #0x1 /* clear bit 0 */
- mcr p15, 0, r0, c1, c0, 0 /* write value back */
-
-#ifdef SHAREABLE_DDR
- /* Mark the entire DDR memory as shareable */
- ldr r3, =0x3ff /* 1024 entries to cover 1G DDR */
- ldr r0, =TblBase /* MMU Table address in memory */
- ldr r2, =0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
-shareable_loop:
- str r2, [r0] /* write the entry to MMU table */
- add r0, r0, #0x4 /* next entry in the table */
- add r2, r2, #0x100000 /* next section */
- subs r3, r3, #1
- bge shareable_loop /* loop till 1G is covered */
-#endif
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the irq stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x12 /* IRQ mode */
- msr cpsr, r2
- ldr r13,=IRQ_stack /* IRQ stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the supervisor stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x13 /* supervisor mode */
- msr cpsr, r2
- ldr r13,=SPV_stack /* Supervisor stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the Abort stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x17 /* Abort mode */
- msr cpsr, r2
- ldr r13,=Abort_stack /* Abort stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the FIQ stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x11 /* FIQ mode */
- msr cpsr, r2
- ldr r13,=FIQ_stack /* FIQ stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the Undefine stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x1b /* Undefine mode */
- msr cpsr, r2
- ldr r13,=Undef_stack /* Undefine stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the system stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x1F /* SYS mode */
- msr cpsr, r2
- ldr r13,=SYS_stack /* SYS stack pointer */
-
- /*set scu enable bit in scu*/
- ldr r7, =0xf8f00000
- ldr r0, [r7]
- orr r0, r0, #0x1
- str r0, [r7]
-
- /* enable MMU and cache */
-
- ldr r0,=TblBase /* Load MMU translation table base */
- orr r0, r0, #0x5B /* Outer-cacheable, WB */
- mcr 15, 0, r0, c2, c0, 0 /* TTB0 */
-
- mvn r0,#0 /* Load MMU domains -- all ones=manager */
- mcr p15,0,r0,c3,c0,0
-
- /* Enable mmu, icahce and dcache */
- ldr r0,=CRValMmuCac
- mcr p15,0,r0,c1,c0,0 /* Enable cache and MMU */
- dsb /* dsb allow the MMU to start up */
- isb /* isb flush prefetch buffer */
-
- /* Write to ACTLR */
- mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/
- orr r0, r0, #(0x01 << 6) /* set SMP bit */
- orr r0, r0, #(0x01 ) /* Cache/TLB maintenance broadcast */
- mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/
-
-/* Invalidate L2 Cache and enable L2 Cache*/
-/* For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) */
-#if USE_AMP!=1
- ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */
- mov r1, #0 /* force the disable bit */
- str r1, [r0] /* disable the L2 Caches */
-
- ldr r0,=L2CCAuxCrtl /* Load L2CC base address base + Aux control register */
- ldr r1,[r0] /* read the register */
- ldr r2,=L2CCAuxControl /* set the default bits */
- orr r1,r1,r2
- str r1, [r0] /* store the Aux Control Register */
-
- ldr r0,=L2CCTAGLatReg /* Load L2CC base address base + TAG Latency address */
- ldr r1,=L2CCTAGLatency /* set the latencies for the TAG*/
- str r1, [r0] /* store the TAG Latency register Register */
-
- ldr r0,=L2CCDataLatReg /* Load L2CC base address base + Data Latency address */
- ldr r1,=L2CCDataLatency /* set the latencies for the Data*/
- str r1, [r0] /* store the Data Latency register Register */
-
- ldr r0,=L2CCWay /* Load L2CC base address base + way register*/
- ldr r2, =0xFFFF
- str r2, [r0] /* force invalidate */
-
- ldr r0,=L2CCSync /* need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET */
- /* Load L2CC base address base + sync register*/
- /* poll for completion */
-Sync: ldr r1, [r0]
- cmp r1, #0
- bne Sync
-
- ldr r0,=L2CCIntRaw /* clear pending interrupts */
- ldr r1,[r0]
- ldr r0,=L2CCIntClear
- str r1,[r0]
-
- ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
- ldr r1,=SLCRUnlockKey /* set unlock key */
- str r1, [r0] /* Unlock SLCR */
-
- ldr r0,=SLCRL2cRamReg /* Load SLCR base address base + l2c Ram Control register */
- ldr r1,=SLCRL2cRamConfig /* set the configuration value */
- str r1, [r0] /* store the L2c Ram Control Register */
-
- ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
- ldr r1,=SLCRlockKey /* set lock key */
- str r1, [r0] /* lock SLCR */
-
- ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */
- ldr r1,[r0] /* read the register */
- mov r2, #L2CCControl /* set the enable bit */
- orr r1,r1,r2
- str r1, [r0] /* enable the L2 Caches */
-#endif
-
- mov r0, r0
- mrc p15, 0, r1, c1, c0, 2 /* read cp access control register (CACR) into r1 */
- orr r1, r1, #(0xf << 20) /* enable full access for p10 & p11 */
- mcr p15, 0, r1, c1, c0, 2 /* write back into CACR */
-
- /* enable vfp */
- fmrx r1, FPEXC /* read the exception register */
- orr r1,r1, #FPEXC_EN /* set VFP enable bit, leave the others in orig state */
- fmxr FPEXC, r1 /* write back the exception register */
-
- mrc p15,0,r0,c1,c0,0 /* flow prediction enable */
- orr r0, r0, #(0x01 << 11) /* #0x8000 */
- mcr p15,0,r0,c1,c0,0
-
- mrc p15,0,r0,c1,c0,1 /* read Auxiliary Control Register */
- orr r0, r0, #(0x1 << 2) /* enable Dside prefetch */
- orr r0, r0, #(0x1 << 1) /* enable L2 Prefetch hint */
- mcr p15,0,r0,c1,c0,1 /* write Auxiliary Control Register */
-
- mrs r0, cpsr /* get the current PSR */
- bic r0, r0, #0x100 /* enable asynchronous abort exception */
- msr cpsr_xsf, r0
-
-
- b _start /* jump to C startup code */
- and r0, r0, r0 /* no op */
-
-.Ldone: b .Ldone /* Paranoia: we should never get here */
-
-
-/*
- *************************************************************************
- *
- * invalidate_dcache - invalidate the entire d-cache by set/way
- *
- * Note: for Cortex-A9, there is no cp instruction for invalidating
- * the whole D-cache. Need to invalidate each line.
- *
- *************************************************************************
- */
-invalidate_dcache:
- mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */
- ands r3, r0, #0x7000000
- mov r3, r3, lsr #23 /* cache level value (naturally aligned) */
- beq finished
- mov r10, #0 /* start with level 0 */
-loop1:
- add r2, r10, r10, lsr #1 /* work out 3xcachelevel */
- mov r1, r0, lsr r2 /* bottom 3 bits are the Cache type for this level */
- and r1, r1, #7 /* get those 3 bits alone */
- cmp r1, #2
- blt skip /* no cache or only instruction cache at this level */
- mcr p15, 2, r10, c0, c0, 0 /* write the Cache Size selection register */
- isb /* isb to sync the change to the CacheSizeID reg */
- mrc p15, 1, r1, c0, c0, 0 /* reads current Cache Size ID register */
- and r2, r1, #7 /* extract the line length field */
- add r2, r2, #4 /* add 4 for the line length offset (log2 16 bytes) */
- ldr r4, =0x3ff
- ands r4, r4, r1, lsr #3 /* r4 is the max number on the way size (right aligned) */
- clz r5, r4 /* r5 is the bit position of the way size increment */
- ldr r7, =0x7fff
- ands r7, r7, r1, lsr #13 /* r7 is the max number of the index size (right aligned) */
-loop2:
- mov r9, r4 /* r9 working copy of the max way size (right aligned) */
-loop3:
- orr r11, r10, r9, lsl r5 /* factor in the way number and cache number into r11 */
- orr r11, r11, r7, lsl r2 /* factor in the index number */
- mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */
- subs r9, r9, #1 /* decrement the way number */
- bge loop3
- subs r7, r7, #1 /* decrement the index */
- bge loop2
-skip:
- add r10, r10, #2 /* increment the cache number */
- cmp r3, r10
- bgt loop1
-
-finished:
- mov r10, #0 /* switch back to cache level 0 */
- mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
- dsb
- isb
-
- bx lr
-
-.end
-/**
-* @} End of "addtogroup a9_boot_code".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/eb/70b86c595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/eb/70b86c595243001d18b399c1eb9b3628
deleted file mode 100644
index ec5f8b1..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/eb/70b86c595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,184 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-* microblaze_scrub ()
-*
-* Scrub LMB memory and all internal BRAMs (data cache, instruction cache,
-* MMU UTLB and branch target cache) in MicroBlaze to reduce the possibility
-* of an uncorrectable error when fault tolerance support is enabled.
-*
-* This routine assumes that the processor is in privileged mode when it is
-* called, if the MMU is enabled.
-*
-* Call this routine regularly from a timer interrupt.
-*
-* Parameters:
-* None
-*
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-
-/* Define if fault tolerance is used */
-#ifdef XPAR_MICROBLAZE_FAULT_TOLERANT
- #if XPAR_MICROBLAZE_FAULT_TOLERANT > 0
- #define FAULT_TOLERANT
- #endif
-#endif
-
-/* Define if LMB is used and can be scrubbed */
-#if defined(XPAR_MICROBLAZE_D_LMB) && \
- defined(XPAR_DLMB_CNTLR_BASEADDR) && \
- defined(XPAR_DLMB_CNTLR_HIGHADDR)
- #if XPAR_MICROBLAZE_D_LMB == 1
- #define HAS_SCRUBBABLE_LMB
- #define DLMB_MASK (XPAR_DLMB_CNTLR_HIGHADDR - XPAR_DLMB_CNTLR_BASEADDR)
- #endif
-#endif
-
-/* Set default cache line lengths */
-#ifndef XPAR_MICROBLAZE_DCACHE_LINE_LEN
- #define XPAR_MICROBLAZE_DCACHE_LINE_LEN 4
-#endif
-
-#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
- #define XPAR_MICROBLAZE_ICACHE_LINE_LEN 4
-#endif
-
-/* Define if internal Data Cache BRAMs are used */
-#if defined(XPAR_MICROBLAZE_USE_DCACHE) && defined(XPAR_MICROBLAZE_DCACHE_BYTE_SIZE)
- #if XPAR_MICROBLAZE_USE_DCACHE == 1 && XPAR_MICROBLAZE_DCACHE_BYTE_SIZE > 1024
- #define HAS_BRAM_DCACHE
- #define DCACHE_INCREMENT (XPAR_MICROBLAZE_DCACHE_LINE_LEN * 4)
- #define DCACHE_MASK (XPAR_MICROBLAZE_DCACHE_BYTE_SIZE - 1)
- #endif
-#endif
-
-/* Define if internal Instruction Cache BRAMs are used */
-#if defined(XPAR_MICROBLAZE_USE_ICACHE) && defined(XPAR_MICROBLAZE_CACHE_BYTE_SIZE)
- #if XPAR_MICROBLAZE_USE_ICACHE == 1 && XPAR_MICROBLAZE_CACHE_BYTE_SIZE > 1024
- #define HAS_BRAM_ICACHE
- #define ICACHE_INCREMENT (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4)
- #define ICACHE_MASK (XPAR_MICROBLAZE_CACHE_BYTE_SIZE - 1)
- #endif
-#endif
-
-/* Define if internal MMU UTLB BRAM is used */
-#ifdef XPAR_MICROBLAZE_USE_MMU
- #if XPAR_MICROBLAZE_USE_MMU > 1
- #define HAS_BRAM_MMU_UTLB
- #endif
-#endif
-
-/* Define if internal BTC BRAM is used, and match BTC clear to a complete cache scrub */
-#if defined(XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE) && \
- defined(XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE)
- #if XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE == 1
- #if XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE == 0 || \
- XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE > 4
- #define HAS_BRAM_BRANCH_TARGET_CACHE
- #ifdef HAS_BRAM_DCACHE
- #define BTC_MASK_D (XPAR_MICROBLAZE_DCACHE_BYTE_SIZE/DCACHE_INCREMENT-1)
- #else
- #define BTC_MASK_D 256
- #endif
- #ifdef HAS_BRAM_ICACHE
- #define BTC_MASK_I (XPAR_MICROBLAZE_CACHE_BYTE_SIZE/ICACHE_INCREMENT-1)
- #else
- #define BTC_MASK_I 256
- #endif
- #if BTC_MASK_D > BTC_MASK_I
- #define BTC_MASK BTC_MASK_D
- #else
- #define BTC_MASK BTC_MASK_I
- #endif
- #endif
- #endif
-#endif
-
-/* Define index offsets to persistent data used by this routine */
-#define DLMB_INDEX_OFFSET 0
-#define DCACHE_INDEX_OFFSET 4
-#define ICACHE_INDEX_OFFSET 8
-#define MMU_INDEX_OFFSET 12
-#define BTC_CALL_COUNT_OFFSET 16
-
- .text
- .globl microblaze_scrub
- .ent microblaze_scrub
- .align 2
-
-microblaze_scrub:
-#ifdef FAULT_TOLERANT
- la r6, r0, L_persistent_data /* Get pointer to data */
-
-#ifdef HAS_SCRUBBABLE_LMB
-L_dlmb:
- lwi r5, r6, DLMB_INDEX_OFFSET /* Get dlmb index */
- lw r7, r5, r0 /* Load and store */
- sw r7, r5, r0
- addik r5, r5, 4 /* Increment and save dlmb index */
- andi r5, r5, DLMB_MASK
- swi r5, r6, DLMB_INDEX_OFFSET
-#endif /* HAS_SCRUBBABLE_LMB */
-
-#ifdef HAS_BRAM_DCACHE
-L_dcache:
- lwi r5, r6, DCACHE_INDEX_OFFSET /* Get dcache line index */
- wdc r5, r0 /* Invalidate data cache line */
- addik r5, r5, DCACHE_INCREMENT /* Increment and save entry index */
- andi r5, r5, DCACHE_MASK
- swi r5, r6, DCACHE_INDEX_OFFSET
-#endif /* HAS_BRAM_DCACHE */
-
-#ifdef HAS_BRAM_ICACHE
-L_icache:
- lwi r5, r6, ICACHE_INDEX_OFFSET /* Get icache line index */
- wic r5, r0 /* Invalidate data cache line */
- addik r5, r5, ICACHE_INCREMENT /* Increment and save entry index */
- andi r5, r5, ICACHE_MASK
- swi r5, r6, ICACHE_INDEX_OFFSET
-#endif /* HAS_BRAM_ICACHE */
-
-#ifdef HAS_BRAM_MMU_UTLB
-L_mmu:
- lwi r5, r6, MMU_INDEX_OFFSET /* Get UTLB entry index */
- mts rtlbx, r5 /* Access next entry in UTLB */
- mts rtlbhi, r0 /* Clear the UTLB entry */
-
- addik r5, r5, 1 /* Increment and save entry index */
- andi r5, r5, 0x3F
- swi r5, r6, MMU_INDEX_OFFSET
-#endif /* HAS_BRAM_MMU_UTLB */
-
-#ifdef HAS_BRAM_BRANCH_TARGET_CACHE
-L_btc:
- lwi r5, r6, BTC_CALL_COUNT_OFFSET /* Get BTC call count offset */
- addik r5, r5, 1 /* Increment and save call count */
- andi r5, r5, BTC_MASK
- swi r5, r6, BTC_CALL_COUNT_OFFSET
-
- bnei r5, L_skip_btc_scrub /* Skip scrub unless count wrap */
- bri 4 /* Clear branch target cache */
-L_skip_btc_scrub:
-#endif /* HAS_BRAM_BRANCH_TARGET_CACHE */
-
-#endif /* FAULT_TOLERANT */
-L_done:
- rtsd r15, 8 /* Return */
- nop
- .end microblaze_scrub
-
- /* Persistent data used by this routine */
- .data
- .align 2
-L_persistent_data:
- .long 0 /* dlmb index */
- .long 0 /* dcache index */
- .long 0 /* icache index */
- .long 0 /* mmu entry index */
- .long 0 /* btc call count */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/eb/82bcda595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/eb/82bcda595243001d18b399c1eb9b3628
deleted file mode 100644
index 5feeb49..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/eb/82bcda595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,39 +0,0 @@
-DRIVER_LIB_VERSION = 1.0
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-
-CC_FLAGS = $(COMPILER_FLAGS)
-ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I$(INCLUDEDIR)
-
-SRCFILES:=$(wildcard *.c)
-
-OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
-
-libs: $(OBJECTS)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)%.o: %.c
- ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf $(DEPFILES)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ec/6015da585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ec/6015da585243001d18b399c1eb9b3628
deleted file mode 100644
index 98aa62a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ec/6015da585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,142 +0,0 @@
-;******************************************************************************
-; Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-; SPDX-License-Identifier: MIT
-;*****************************************************************************
-;****************************************************************************
-;**
-; @file asm_vectors.s
-;
-; This file contains the initial vector table for the Cortex A9 processor
-;
-;
-; MODIFICATION HISTORY:
-;
-; Ver Who Date Changes
-; ----- ------- -------- ---------------------------------------------------
-; 1.00a ecm/sdm 10/20/09 Initial version
-; 3.11a asa 9/17/13 Added support for neon.
-; 4.00 pkp 01/22/14 Modified return addresses for interrupt
-; handlers
-; 5.1 pkp 05/13/15 Saved the addresses of instruction causing data
-; abort and prefetch abort into DataAbortAddr and
-; PrefetchAbortAddr for further use to fix CR#854523
-; 5.4 pkp 12/03/15 Added handler for undefined exception
-;
-;
-; @note
-;
-; None.
-;
-;****************************************************************************
-
- EXPORT _vector_table
- EXPORT IRQHandler
-
- IMPORT _boot
- IMPORT _prestart
- IMPORT IRQInterrupt
- IMPORT FIQInterrupt
- IMPORT SWInterrupt
- IMPORT DataAbortInterrupt
- IMPORT PrefetchAbortInterrupt
- IMPORT UndefinedException
- IMPORT DataAbortAddr
- IMPORT PrefetchAbortAddr
- IMPORT UndefinedExceptionAddr
-
- AREA |.vectors|, CODE
- REQUIRE8 {TRUE}
- PRESERVE8 {TRUE}
- ENTRY ; define this as an entry point
-_vector_table
- B _boot
- B Undefined
- B SVCHandler
- B PrefetchAbortHandler
- B DataAbortHandler
- NOP ; Placeholder for address exception vector
- B IRQHandler
- B FIQHandler
-
-
-IRQHandler ; IRQ vector handler
-
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- vpush {d0-d7}
- vpush {d16-d31}
- vmrs r1, FPSCR
- push {r1}
- vmrs r1, FPEXC
- push {r1}
- bl IRQInterrupt ; IRQ vector
- pop {r1}
- vmsr FPEXC, r1
- pop {r1}
- vmsr FPSCR, r1
- vpop {d16-d31}
- vpop {d0-d7}
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- subs pc, lr, #4 ; adjust return
-
-
-FIQHandler ; FIQ vector handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- vpush {d0-d7}
- vpush {d16-d31}
- vmrs r1, FPSCR
- push {r1}
- vmrs r1, FPEXC
- push {r1}
-FIQLoop
- bl FIQInterrupt ; FIQ vector
- pop {r1}
- vmsr FPEXC, r1
- pop {r1}
- vmsr FPSCR, r1
- vpop {d16-d31}
- vpop {d0-d7}
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- subs pc, lr, #4 ; adjust return
-
-
-Undefined ; Undefined handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- ldr r0, =UndefinedExceptionAddr
- sub r1, lr,#4
- str r1, [r0] ; Address of instruction causing undefined exception
- bl UndefinedException ; UndefinedException: call C function here
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
-
- movs pc, lr
-
-
-SVCHandler ; SWI handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- tst r0, #0x20 ; check the T bit
- ldrneh r0, [lr,#-2] ; Thumb mode
- bicne r0, r0, #0xff00 ; Thumb mode
- ldreq r0, [lr,#-4] ; ARM mode
- biceq r0, r0, #0xff000000 ; ARM mode
- bl SWInterrupt ; SWInterrupt: call C function here
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- movs pc, lr ; adjust return
-
-DataAbortHandler ; Data Abort handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- ldr r0, =DataAbortAddr
- sub r1, lr,#8
- str r1, [r0] ;Address of instruction causing data abort
- bl DataAbortInterrupt ;DataAbortInterrupt :call C function here
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- subs pc, lr, #8 ; adjust return
-
-PrefetchAbortHandler ; Prefetch Abort handler
- stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
- ldr r0, =PrefetchAbortAddr
- sub r1, lr,#4
- str r1, [r0] ;Address of instruction causing prefetch abort
- bl PrefetchAbortInterrupt ; PrefetchAbortInterrupt: call C function here
- ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
- subs pc, lr, #4 ; adjust return
-
- END
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ec/b0974d595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ec/b0974d595243001d18b399c1eb9b3628
deleted file mode 100644
index 20b9f3c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ec/b0974d595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,25 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include "xil_types.h"
-/*
- * getpid -- only one process, so just return 1.
- */
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) s32 _getpid(void);
-}
-#endif
-
-__attribute__((weak)) s32 getpid(void)
-{
- return 1;
-}
-
-__attribute__((weak)) s32 _getpid(void)
-{
- return 1;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ed/20bdc8525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ed/20bdc8525243001d18b399c1eb9b3628
deleted file mode 100644
index 7e29233..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ed/20bdc8525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,165 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_testmem.h
-* @addtogroup common_test_utils Test Utilities for Memory and Caches
-*
-* - Cache test: xil_testcache.h contains utility functions to test cache.
-*
-* - I/O test: The Xil_testio.h file contains endian related memory IO functions. A
-* subset of the memory tests can be selected or all of the tests can be run in order.
-* If there is an error detected by a subtest, the test stops and the failure code is
-* returned. Further tests are not run even if all of the tests are selected.
-*
-* - Memory test: The xil_testmem.h file contains utility functions to test memory.
-* A subset of the memory tests can be selected or all of the tests can be run
-* in order. If there is an error detected by a subtest, the test stops and the
-* failure code is returned. Further tests are not run even if all of the tests are selected.
-*
-*
-* Following list describes the supported memory tests:
-*
-* - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
-*
-* - XIL_TESTMEM_INCREMENT: This test
-* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
-* test value for memory.
-*
-* - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
-* uses a walking '1' as the test value for memory.
-* @code
-* location 1 = 0x00000001
-* location 2 = 0x00000002
-* ...
-* @endcode
-*
-* - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
-* This test uses the inverse value of the walking ones test
-* as the test value for memory.
-* @code
-* location 1 = 0xFFFFFFFE
-* location 2 = 0xFFFFFFFD
-* ...
-*@endcode
-*
-* - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
-* This test uses the inverse of the address of the location under test
-* as the test value for memory.
-*
-* - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
-* This test uses the provided patters as the test value for memory.
-* If zero is provided as the pattern the test uses '0xDEADBEEF".
-*
-* @warning
-* The tests are DESTRUCTIVE. Run before any initialized memory spaces
-* have been set up.
-* The address provided to the memory tests is not checked for
-* validity except for the NULL case. It is possible to provide a code-space
-* pointer for this test to start with and ultimately destroy executable code
-* causing random failures.
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 08/25/09 First release
-* 7.5 mus 03/10/21 Added new set of Xil_TestMem32, Xil_TestMem16 and
-* Xil_TestMem8 APIs to support memory test for memory
-* regions mapped at extended addresses
-* (addresses > 4 GB). These new set of APIs would be
-* compiled only for 32 bit Microblaze processor, if
-* XPAR_MICROBLAZE_ADDR_SIZE is greater than 32.
-* It fixes CR#1089129.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a sdm 01/15/10 First release
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xscuwdt.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/****************************************************************************/
-/**
-*
-* Initialize a specific watchdog timer instance/driver. This function
-* must be called before other functions of the driver are called.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-* @param ConfigPtr is the config structure.
-* @param EffectiveAddress is the base address for the device. It could be
-* a virtual address if address translation is supported in the
-* system, otherwise it is the physical address.
-*
-* @return
-* - XST_SUCCESS if initialization was successful.
-* - XST_DEVICE_IS_STARTED if the device has already been started.
-*
-* @note This function enables the watchdog mode.
-*
-******************************************************************************/
-s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
- XScuWdt_Config *ConfigPtr, u32 EffectiveAddress)
-{
- s32 CfgStatus;
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
- Xil_AssertNonvoid(EffectiveAddress != 0x00U);
-
- /*
- * If the device is started, disallow the initialize and return a
- * status indicating it is started. This allows the user to stop the
- * device and reinitialize, but prevents a user from inadvertently
- * initializing.
- */
- if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
- CfgStatus = (s32)XST_DEVICE_IS_STARTED;
- }
- else {
- /*
- * Copy configuration into instance.
- */
- InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
-
- /*
- * Save the base address pointer such that the registers of the block
- * can be accessed and indicate it has not been started yet.
- */
- InstancePtr->Config.BaseAddr = EffectiveAddress;
- InstancePtr->IsStarted = 0U;
-
- /*
- * Put the watchdog timer in Watchdog mode.
- */
- XScuWdt_SetWdMode(InstancePtr);
-
- /*
- * Indicate the instance is ready to use, successfully initialized.
- */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- CfgStatus =(s32)XST_SUCCESS;
- }
- return CfgStatus;
-}
-
-/****************************************************************************/
-/**
-*
-* Start the watchdog counter of the device.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note User needs to select the appropriate mode (watchdog/timer)
-* before using this API.
-* See XScuWdt_SetWdMode/XScuWdt_SetTimerMode macros in
-* xscuwdt.h.
-*
-******************************************************************************/
-void XScuWdt_Start(XScuWdt *InstancePtr)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the contents of the Control register.
- */
- Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr,
- XSCUWDT_CONTROL_OFFSET);
-
- /*
- * Set the 'watchdog enable' bit in the register.
- */
- Register |= XSCUWDT_CONTROL_WD_ENABLE_MASK;
-
- /*
- * Update the Control register with the new value.
- */
- XScuWdt_WriteReg(InstancePtr->Config.BaseAddr,
- XSCUWDT_CONTROL_OFFSET, Register);
-
- /*
- * Indicate that the device is started.
- */
- InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
-}
-
-/****************************************************************************/
-/**
-*
-* Stop the watchdog timer.
-*
-* @param InstancePtr is a pointer to the XScuWdt instance.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XScuWdt_Stop(XScuWdt *InstancePtr)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the contents of the Control register.
- */
- Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr,
- XSCUWDT_CONTROL_OFFSET);
-
- /*
- * Clear the 'watchdog enable' bit in the register.
- */
- Register &= (~(u32)XSCUWDT_CONTROL_WD_ENABLE_MASK);
-
- /*
- * Update the Control register with the new value.
- */
- XScuWdt_WriteReg(InstancePtr->Config.BaseAddr,
- XSCUWDT_CONTROL_OFFSET, Register);
-
- /*
- * Indicate that the device is stopped.
- */
- InstancePtr->IsStarted = 0U;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ed/b19589565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ed/b19589565243001d18b399c1eb9b3628
deleted file mode 100644
index 62b8cf7..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ed/b19589565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,29 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-* Enable exceptions on microblaze.
-*
-*
-******************************************************************************/
-
-#include "xparameters.h"
-
- .text
- .globl microblaze_enable_exceptions
- .ent microblaze_enable_exceptions
- .align 2
-microblaze_enable_exceptions:
-#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
- rtsd r15, 8;
- msrset r0, 0x100
-#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- mfs r4, rmsr;
- ori r4, r4, 0x100; /* Turn ON the EE bit */
- mts rmsr, r4;
- rtsd r15, 8;
- nop;
-#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
-.end microblaze_enable_exceptions
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ed/f1054a545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ed/f1054a545243001d18b399c1eb9b3628
deleted file mode 100644
index 5a1bda3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ed/f1054a545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,76 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_testio.h
-*
-* @addtogroup common_test_utils Test Utilities for Memory and Caches
-*
I/O test
-* The xil_testio.h file contains utility functions to test endian related memory
-* IO functions.
-*
-* A subset of the memory tests can be selected or all of the tests can be run
-* in order. If there is an error detected by a subtest, the test stops and the
-* failure code is returned. Further tests are not run even if all of the tests
-* are selected.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00 hbm 08/05/09 First release
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm 03/10/10 First release
-* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
-* and interrupt registers
-* 1.02a sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
-* when the xstatus.h in the common driver overwrites
-* the xstatus.h of the standalone BSP during the
-* libgen.
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-#ifndef XSCUTIMER_HW_H /* prevent circular inclusions */
-#define XSCUTIMER_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- * Offsets of registers from the start of the device
- * @{
- */
-
-#define XSCUTIMER_LOAD_OFFSET 0x00U /**< Timer Load Register */
-#define XSCUTIMER_COUNTER_OFFSET 0x04U /**< Timer Counter Register */
-#define XSCUTIMER_CONTROL_OFFSET 0x08U /**< Timer Control Register */
-#define XSCUTIMER_ISR_OFFSET 0x0CU /**< Timer Interrupt
- Status Register */
-/* @} */
-
-/** @name Timer Control register
- * This register bits control the prescaler, Intr enable,
- * auto-reload and timer enable.
- * @{
- */
-
-#define XSCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */
-#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8U
-#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004U /**< Intr enable */
-#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload */
-#define XSCUTIMER_CONTROL_ENABLE_MASK 0x00000001U /**< Timer enable */
-/* @} */
-
-/** @name Interrupt Status register
- * This register indicates the Timer counter register has reached zero.
- * @{
- */
-
-#define XSCUTIMER_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/**
-*
-* Write to the timer load register. This will also update the
-* timer counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetLoadReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer load register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer load register.
-*
-* @note C-style signature:
-* u32 XScuTimer_GetLoadReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetLoadReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the timer counter register.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the counter register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetCounterReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer counter register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer counter register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetCounterReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetCounterReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the timer load register. This will also update the
-* timer counter register with the new value. This macro can be used to
-* change the time-out value.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the load register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetControlReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer load register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer load register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetControlReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetControlReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Write to the timer counter register.
-*
-* @param BaseAddr is the base address of the scu timer.
-* @param Value is the count to be loaded in to the counter register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value)
-*
-******************************************************************************/
-#define XScuTimer_SetIntrReg(BaseAddr, Value) \
- XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value))
-
-/****************************************************************************/
-/**
-*
-* Returns the current timer counter register value.
-*
-* @param BaseAddr is the base address of the scu timer.
-*
-* @return Contents of the timer counter register.
-*
-* @note C-style signature:
- u32 XScuTimer_GetIntrReg(u32 BaseAddr)
-*
-******************************************************************************/
-#define XScuTimer_GetIntrReg(BaseAddr) \
- XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Read from the given Timer register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be read
-*
-* @return The 32-bit value of the register
-*
-* @note C-style signature:
-* u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset)
-*
-*****************************************************************************/
-#define XScuTimer_ReadReg(BaseAddr, RegOffset) \
- Xil_In32((BaseAddr) + (RegOffset))
-
-/****************************************************************************/
-/**
-*
-* Write to the given Timer register.
-*
-* @param BaseAddr is the base address of the device
-* @param RegOffset is the register offset to be written
-* @param Data is the 32-bit value to write to the register
-*
-* @return None.
-*
-* @note C-style signature:
-* void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
-*
-*****************************************************************************/
-#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data) \
- Xil_Out32((BaseAddr) + (RegOffset), (Data))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ee/706492555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ee/706492555243001d18b399c1eb9b3628
deleted file mode 100644
index 105c913..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ee/706492555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,39 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include "xil_types.h"
-
-extern u8 _heap_start[];
-extern u8 _heap_end[];
-
-#ifdef __cplusplus
-extern "C" {
- __attribute__((weak)) caddr_t _sbrk ( s32 incr );
-}
-#endif
-
-__attribute__((weak)) caddr_t _sbrk ( s32 incr )
-{
- static u8 *heap = NULL;
- u8 *prev_heap;
- static u8 *HeapEndPtr = (u8 *)&_heap_end;
- caddr_t Status;
-
- if (heap == NULL) {
- heap = (u8 *)&_heap_start;
- }
- prev_heap = heap;
-
- if (((heap + incr) <= HeapEndPtr) && (prev_heap != NULL)) {
- heap += incr;
- Status = (caddr_t) ((void *)prev_heap);
- } else {
- Status = (caddr_t) -1;
- }
-
- return Status;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ee/839a39595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ee/839a39595243001d18b399c1eb9b3628
deleted file mode 100644
index 60f4ba3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ee/839a39595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,53 +0,0 @@
-/******************************************************************************
-* Copyright (c) 1995 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-*******************************************************************************/
- #ifndef XIL_PRINTF_H
- #define XIL_PRINTF_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include
-#include
-#include
-#include "xil_types.h"
-#include "xparameters.h"
-#include "bspconfig.h"
-#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
-#include "xen_console.h"
-#endif
-
-/*----------------------------------------------------*/
-/* Use the following parameter passing structure to */
-/* make xil_printf re-entrant. */
-/*----------------------------------------------------*/
-
-struct params_s;
-
-
-/*---------------------------------------------------*/
-/* The purpose of this routine is to output data the */
-/* same as the standard printf function without the */
-/* overhead most run-time libraries involve. Usually */
-/* the printf brings in many kilobytes of code and */
-/* that is unacceptable in most embedded systems. */
-/*---------------------------------------------------*/
-
-typedef char8* charptr;
-typedef s32 (*func_ptr)(int c);
-
-/* */
-
-void xil_printf( const char8 *ctrl1, ...);
-void xil_vprintf(const char8 *ctrl1, va_list argp);
-void print( const char8 *ptr);
-extern void outbyte (char8 c);
-extern char8 inbyte(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ee/b1ee89575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ee/b1ee89575243001d18b399c1eb9b3628
deleted file mode 100644
index 1d18bfb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ee/b1ee89575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,203 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_types.h
-*
-* @addtogroup common_types Basic Data types for Xilinx® Software IP
-*
-* The xil_types.h file contains basic types for Xilinx software IP. These data types
-* are applicable for all processors supported by Xilinx.
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 First release
-* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
-* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
-* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
-* Define LONG and ULONG datatypes and mask values
-* 7.00 mus 01/07/19 Add cpp extern macro
-* 7.1 aru 08/19/19 Shift the value in UPPER_32_BITS only if it
-* is 64-bit processor
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-#ifndef XIL_TYPES_H /* prevent circular inclusions */
-#define XIL_TYPES_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include
-#include
-
-/************************** Constant Definitions *****************************/
-
-#ifndef TRUE
-# define TRUE 1U
-#endif
-
-#ifndef FALSE
-# define FALSE 0U
-#endif
-
-#ifndef NULL
-#define NULL 0U
-#endif
-
-#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be
- assigend to "IsReady" member of driver
- instance to indicate that driver
- instance is initialized and ready to use. */
-#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to
- "IsStarted" member of driver instance
- to indicate that driver instance is
- started and it can be enabled. */
-
-/* @name New types
- * New simple types.
- * @{
- */
-#ifndef __KERNEL__
-#ifndef XBASIC_TYPES_H
-/*
- * guarded against xbasic_types.h.
- */
-typedef uint8_t u8;
-typedef uint16_t u16;
-typedef uint32_t u32;
-/** @}*/
-#define __XUINT64__
-typedef struct
-{
- u32 Upper;
- u32 Lower;
-} Xuint64;
-
-
-/*****************************************************************************/
-/**
-* @brief Return the most significant half of the 64 bit data type.
-*
-* @param x is the 64 bit word.
-*
-* @return The upper 32 bits of the 64 bit word.
-*
-******************************************************************************/
-#define XUINT64_MSW(x) ((x).Upper)
-
-/*****************************************************************************/
-/**
-* @brief Return the least significant half of the 64 bit data type.
-*
-* @param x is the 64 bit word.
-*
-* @return The lower 32 bits of the 64 bit word.
-*
-******************************************************************************/
-#define XUINT64_LSW(x) ((x).Lower)
-
-#endif /* XBASIC_TYPES_H */
-
-/*
- * xbasic_types.h does not typedef s* or u64
- */
-/** @{ */
-typedef char char8;
-typedef int8_t s8;
-typedef int16_t s16;
-typedef int32_t s32;
-typedef int64_t s64;
-typedef uint64_t u64;
-typedef int sint32;
-
-typedef intptr_t INTPTR;
-typedef uintptr_t UINTPTR;
-typedef ptrdiff_t PTRDIFF;
-/** @}*/
-#if !defined(LONG) || !defined(ULONG)
-typedef long LONG;
-typedef unsigned long ULONG;
-#endif
-
-#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
-#define ULONG64_LO_MASK ~ULONG64_HI_MASK
-
-#else
-#include
-#endif
-
-/** @{ */
-/**
- * This data type defines an interrupt handler for a device.
- * The argument points to the instance of the component
- */
-typedef void (*XInterruptHandler) (void *InstancePtr);
-
-/**
- * This data type defines an exception handler for a processor.
- * The argument points to the instance of the component
- */
-typedef void (*XExceptionHandler) (void *InstancePtr);
-
-/**
- * @brief Returns 32-63 bits of a number.
- * @param n : Number being accessed.
- * @return Bits 32-63 of number.
- *
- * @note A basic shift-right of a 64- or 32-bit quantity.
- * Use this to suppress the "right shift count >= width of type"
- * warning when that quantity is 32-bits.
- */
-#if defined (__aarch64__) || defined (__arch64__)
-#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
-#else
-#define UPPER_32_BITS(n) 0U
-#endif
-/**
- * @brief Returns 0-31 bits of a number
- * @param n : Number being accessed.
- * @return Bits 0-31 of number
- */
-#define LOWER_32_BITS(n) ((u32)(n))
-
-
-
-
-/************************** Constant Definitions *****************************/
-
-#ifndef TRUE
-#define TRUE 1U
-#endif
-
-#ifndef FALSE
-#define FALSE 0U
-#endif
-
-#ifndef NULL
-#define NULL 0U
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
- *@endcond
- */
-/**
-* @} End of "addtogroup common_types".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ef/110ff9585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ef/110ff9585243001d18b399c1eb9b3628
deleted file mode 100644
index edf6684..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ef/110ff9585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,558 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpm_counter.h
-*
-* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions
-*
-* Cortex A9 event counter functions can be utilized to configure and control
-* the Cortex-A9 performance monitor events.
-*
-* Cortex-A9 performance monitor has six event counters which can be used to
-* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines
-* configurations XPM_CNTRCFGx which can be used to program the event counters
-* to count a set of events.
-*
-* @note
-* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
-* being used for time keeping.
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-*
-******************************************************************************/
-
-/**
-*@cond nocomments
-*/
-
-#ifndef XPMCOUNTER_H /* prevent circular inclusions */
-#define XPMCOUNTER_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/************************** Constant Definitions ****************************/
-
-/* Number of performance counters */
-#define XPM_CTRCOUNT 6U
-
-/* The following constants define the Cortex-A9 Performance Monitor Events */
-
-/*
- * Software increment. The register is incremented only on writes to the
- * Software Increment Register
- */
-#define XPM_EVENT_SOFTINCR 0x00U
-
-/*
- * Instruction fetch that causes a refill at (at least) the lowest level(s) of
- * instruction or unified cache. Includes the speculative linefills in the
- * count
- */
-#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
-
-/*
- * Instruction fetch that causes a TLB refill at (at least) the lowest level of
- * TLB. Includes the speculative requests in the count
- */
-#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
-
-/*
- * Data read or write operation that causes a refill at (at least) the lowest
- * level(s)of data or unified cache. Counts the number of allocations performed
- * in the Data Cache due to a read or a write
- */
-#define XPM_EVENT_DATA_CACHEREFILL 0x03U
-
-/*
- * Data read or write operation that causes a cache access at (at least) the
- * lowest level(s) of data or unified cache. This includes speculative reads
- */
-#define XPM_EVENT_DATA_CACHEACCESS 0x04U
-
-/*
- * Data read or write operation that causes a TLB refill at (at least) the
- * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
- * CP15 Cache operation by MVA and CP15 VA to PA operations
- */
-#define XPM_EVENT_DATA_TLBREFILL 0x05U
-
-/*
- * Data read architecturally executed. Counts the number of data read
- * instructions accepted by the Load Store Unit. This includes counting the
- * speculative and aborted LDR/LDM, as well as the reads due to the SWP
- * instructions
- */
-#define XPM_EVENT_DATA_READS 0x06U
-
-/*
- * Data write architecturally executed. Counts the number of data write
- * instructions accepted by the Load Store Unit. This includes counting the
- * speculative and aborted STR/STM, as well as the writes due to the SWP
- * instructions
- */
-#define XPM_EVENT_DATA_WRITE 0x07U
-
-/* Exception taken. Counts the number of exceptions architecturally taken.*/
-#define XPM_EVENT_EXCEPTION 0x09U
-
-/* Exception return architecturally executed.*/
-#define XPM_EVENT_EXCEPRETURN 0x0AU
-
-/*
- * Change to ContextID retired. Counts the number of instructions
- * architecturally executed writing into the ContextID Register
- */
-#define XPM_EVENT_CHANGECONTEXT 0x0BU
-
-/*
- * Software change of PC, except by an exception, architecturally executed.
- * Count the number of PC changes architecturally executed, excluding the PC
- * changes due to taken exceptions
- */
-#define XPM_EVENT_SW_CHANGEPC 0x0CU
-
-/*
- * Immediate branch architecturally executed (taken or not taken). This includes
- * the branches which are flushed due to a previous load/store which aborts
- * late
- */
-#define XPM_EVENT_IMMEDBRANCH 0x0DU
-
-/*
- * Unaligned access architecturally executed. Counts the number of aborted
- * unaligned accessed architecturally executed, and the number of not-aborted
- * unaligned accesses, including the speculative ones
- */
-#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
-
-/*
- * Branch mispredicted/not predicted. Counts the number of mispredicted or
- * not-predicted branches executed. This includes the branches which are flushed
- * due to a previous load/store which aborts late
- */
-#define XPM_EVENT_BRANCHMISS 0x10U
-
-/*
- * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
- * event is not exported on the PMUEVENT bus
- */
-#define XPM_EVENT_CLOCKCYCLES 0x11U
-
-/*
- * Branches or other change in program flow that could have been predicted by
- * the branch prediction resources of the processor. This includes the branches
- * which are flushed due to a previous load/store which aborts late
- */
-#define XPM_EVENT_BRANCHPREDICT 0x12U
-
-/*
- * Java bytecode execute. Counts the number of Java bytecodes being decoded,
- * including speculative ones
- */
-#define XPM_EVENT_JAVABYTECODE 0x40U
-
-/*
- * Software Java bytecode executed. Counts the number of software java bytecodes
- * being decoded, including speculative ones
- */
-#define XPM_EVENT_SWJAVABYTECODE 0x41U
-
-/*
- * Jazelle backward branches executed. Counts the number of Jazelle taken
- * branches being executed. This includes the branches which are flushed due
- * to a previous load/store which aborts late
- */
-#define XPM_EVENT_JAVABACKBRANCH 0x42U
-
-/*
- * Coherent linefill miss Counts the number of coherent linefill requests
- * performed by the Cortex-A9 processor which also miss in all the other
- * Cortex-A9 processors, meaning that the request is sent to the external
- * memory
- */
-#define XPM_EVENT_COHERLINEMISS 0x50U
-
-/*
- * Coherent linefill hit. Counts the number of coherent linefill requests
- * performed by the Cortex-A9 processor which hit in another Cortex-A9
- * processor, meaning that the linefill data is fetched directly from the
- * relevant Cortex-A9 cache
- */
-#define XPM_EVENT_COHERLINEHIT 0x51U
-
-/*
- * Instruction cache dependent stall cycles. Counts the number of cycles where
- * the processor is ready to accept new instructions, but does not receive any
- * due to the instruction side not being able to provide any and the
- * instruction cache is currently performing at least one linefill
- */
-#define XPM_EVENT_INSTRSTALL 0x60U
-
-/*
- * Data cache dependent stall cycles. Counts the number of cycles where the core
- * has some instructions that it cannot issue to any pipeline, and the Load
- * Store unit has at least one pending linefill request, and no pending
- */
-#define XPM_EVENT_DATASTALL 0x61U
-
-/*
- * Main TLB miss stall cycles. Counts the number of cycles where the processor
- * is stalled waiting for the completion of translation table walks from the
- * main TLB. The processor stalls can be due to the instruction side not being
- * able to provide the instructions, or to the data side not being able to
- * provide the necessary data, due to them waiting for the main TLB translation
- * table walk to complete
- */
-#define XPM_EVENT_MAINTLBSTALL 0x62U
-
-/*
- * Counts the number of STREX instructions architecturally executed and
- * passed
- */
-#define XPM_EVENT_STREXPASS 0x63U
-
-/*
- * Counts the number of STREX instructions architecturally executed and
- * failed
- */
-#define XPM_EVENT_STREXFAIL 0x64U
-
-/*
- * Data eviction. Counts the number of eviction requests due to a linefill in
- * the data cache
- */
-#define XPM_EVENT_DATAEVICT 0x65U
-
-/*
- * Counts the number of cycles where the issue stage does not dispatch any
- * instruction because it is empty or cannot dispatch any instructions
- */
-#define XPM_EVENT_NODISPATCH 0x66U
-
-/*
- * Counts the number of cycles where the issue stage is empty
- */
-#define XPM_EVENT_ISSUEEMPTY 0x67U
-
-/*
- * Counts the number of instructions going through the Register Renaming stage.
- * This number is an approximate number of the total number of instructions
- * speculatively executed, and even more approximate of the total number of
- * instructions architecturally executed. The approximation depends mainly on
- * the branch misprediction rate.
- * The renaming stage can handle two instructions in the same cycle so the event
- * is two bits long:
- * - b00 no instructions renamed
- * - b01 one instruction renamed
- * - b10 two instructions renamed
- */
-#define XPM_EVENT_INSTRRENAME 0x68U
-
-/*
- * Counts the number of procedure returns whose condition codes do not fail,
- * excluding all returns from exception. This count includes procedure returns
- * which are flushed due to a previous load/store which aborts late.
- * Only the following instructions are reported:
- * - BX R14
- * - MOV PC LR
- * - POP {..,pc}
- * - LDR pc,[sp],#offset
- * The following instructions are not reported:
- * - LDMIA R9!,{..,PC} (ThumbEE state only)
- * - LDR PC,[R9],#offset (ThumbEE state only)
- * - BX R0 (Rm != R14)
- * - MOV PC,R0 (Rm != R14)
- * - LDM SP,{...,PC} (writeback not specified)
- * - LDR PC,[SP,#offset] (wrong addressing mode)
- */
-#define XPM_EVENT_PREDICTFUNCRET 0x6EU
-
-/*
- * Counts the number of instructions being executed in the main execution
- * pipeline of the processor, the multiply pipeline and arithmetic logic unit
- * pipeline. The counted instructions are still speculative
- */
-#define XPM_EVENT_MAINEXEC 0x70U
-
-/*
- * Counts the number of instructions being executed in the processor second
- * execution pipeline (ALU). The counted instructions are still speculative
- */
-#define XPM_EVENT_SECEXEC 0x71U
-
-/*
- * Counts the number of instructions being executed in the Load/Store unit. The
- * counted instructions are still speculative
- */
-#define XPM_EVENT_LDRSTR 0x72U
-
-/*
- * Counts the number of Floating-point instructions going through the Register
- * Rename stage. Instructions are still speculative in this stage.
- *Two floating-point instructions can be renamed in the same cycle so the event
- * is two bitslong:
- *0b00 no floating-point instruction renamed
- *0b01 one floating-point instruction renamed
- *0b10 two floating-point instructions renamed
- */
-#define XPM_EVENT_FLOATRENAME 0x73U
-
-/*
- * Counts the number of Neon instructions going through the Register Rename
- * stage.Instructions are still speculative in this stage.
- * Two NEON instructions can be renamed in the same cycle so the event is two
- * bits long:
- *0b00 no NEON instruction renamed
- *0b01 one NEON instruction renamed
- *0b10 two NEON instructions renamed
- */
-#define XPM_EVENT_NEONRENAME 0x74U
-
-/*
- * Counts the number of cycles where the processor is stalled because PLD slots
- * are all full
- */
-#define XPM_EVENT_PLDSTALL 0x80U
-
-/*
- * Counts the number of cycles when the processor is stalled and the data side
- * is stalled too because it is full and executing writes to the external
- * memory
- */
-#define XPM_EVENT_WRITESTALL 0x81U
-
-/*
- * Counts the number of stall cycles due to main TLB misses on requests issued
- * by the instruction side
- */
-#define XPM_EVENT_INSTRTLBSTALL 0x82U
-
-/*
- * Counts the number of stall cycles due to main TLB misses on requests issued
- * by the data side
- */
-#define XPM_EVENT_DATATLBSTALL 0x83U
-
-/*
- * Counts the number of stall cycles due to micro TLB misses on the instruction
- * side. This event does not include main TLB miss stall cycles that are already
- * counted in the corresponding main TLB event
- */
-#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
-
-/*
- * Counts the number of stall cycles due to micro TLB misses on the data side.
- * This event does not include main TLB miss stall cycles that are already
- * counted in the corresponding main TLB event
- */
-#define XPM_EVENT_DATA_uTLBSTALL 0x85U
-
-/*
- * Counts the number of stall cycles because of the execution of a DMB memory
- * barrier. This includes all DMB instructions being executed, even
- * speculatively
- */
-#define XPM_EVENT_DMB_STALL 0x86U
-
-/*
- * Counts the number of cycles during which the integer core clock is enabled
- */
-#define XPM_EVENT_INT_CLKEN 0x8AU
-
-/*
- * Counts the number of cycles during which the Data Engine clock is enabled
- */
-#define XPM_EVENT_DE_CLKEN 0x8BU
-
-/*
- * Counts the number of ISB instructions architecturally executed
- */
-#define XPM_EVENT_INSTRISB 0x90U
-
-/*
- * Counts the number of DSB instructions architecturally executed
- */
-#define XPM_EVENT_INSTRDSB 0x91U
-
-/*
- * Counts the number of DMB instructions speculatively executed
- */
-#define XPM_EVENT_INSTRDMB 0x92U
-
-/*
- * Counts the number of external interrupts executed by the processor
- */
-#define XPM_EVENT_EXTINT 0x93U
-
-/*
- * PLE cache line request completed
- */
-#define XPM_EVENT_PLE_LRC 0xA0U
-
-/*
- * PLE cache line request skipped
- */
-#define XPM_EVENT_PLE_LRS 0xA1U
-
-/*
- * PLE FIFO flush
- */
-#define XPM_EVENT_PLE_FLUSH 0xA2U
-
-/*
- * PLE request complete
- */
-#define XPM_EVENT_PLE_CMPL 0xA3U
-
-/*
- * PLE FIFO overflow
- */
-#define XPM_EVENT_PLE_OVFL 0xA4U
-
-/*
- * PLE request programmed
- */
-#define XPM_EVENT_PLE_PROG 0xA5U
-
-/*
- * The following constants define the configurations for Cortex-A9 Performance
- * Monitor Events. Each configuration configures the event counters for a set
- * of events.
- * -----------------------------------------------
- * Config PmCtr0... PmCtr5
- * -----------------------------------------------
- * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR,
- * XPM_EVENT_INSRFETCH_CACHEREFILL,
- * XPM_EVENT_INSTRFECT_TLBREFILL,
- * XPM_EVENT_DATA_CACHEREFILL,
- * XPM_EVENT_DATA_CACHEACCESS,
- * XPM_EVENT_DATA_TLBREFILL }
- *
- * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS,
- * XPM_EVENT_DATA_WRITE,
- * XPM_EVENT_EXCEPTION,
- * XPM_EVENT_EXCEPRETURN,
- * XPM_EVENT_CHANGECONTEXT,
- * XPM_EVENT_SW_CHANGEPC }
- *
- * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH,
- * XPM_EVENT_UNALIGNEDACCESS,
- * XPM_EVENT_BRANCHMISS,
- * XPM_EVENT_CLOCKCYCLES,
- * XPM_EVENT_BRANCHPREDICT,
- * XPM_EVENT_JAVABYTECODE }
- *
- * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE,
- * XPM_EVENT_JAVABACKBRANCH,
- * XPM_EVENT_COHERLINEMISS,
- * XPM_EVENT_COHERLINEHIT,
- * XPM_EVENT_INSTRSTALL,
- * XPM_EVENT_DATASTALL }
- *
- * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL,
- * XPM_EVENT_STREXPASS,
- * XPM_EVENT_STREXFAIL,
- * XPM_EVENT_DATAEVICT,
- * XPM_EVENT_NODISPATCH,
- * XPM_EVENT_ISSUEEMPTY }
- *
- * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME,
- * XPM_EVENT_PREDICTFUNCRET,
- * XPM_EVENT_MAINEXEC,
- * XPM_EVENT_SECEXEC,
- * XPM_EVENT_LDRSTR,
- * XPM_EVENT_FLOATRENAME }
- *
- * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME,
- * XPM_EVENT_PLDSTALL,
- * XPM_EVENT_WRITESTALL,
- * XPM_EVENT_INSTRTLBSTALL,
- * XPM_EVENT_DATATLBSTALL,
- * XPM_EVENT_INSTR_uTLBSTALL }
- *
- * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL,
- * XPM_EVENT_DMB_STALL,
- * XPM_EVENT_INT_CLKEN,
- * XPM_EVENT_DE_CLKEN,
- * XPM_EVENT_INSTRISB,
- * XPM_EVENT_INSTRDSB }
- *
- * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB,
- * XPM_EVENT_EXTINT,
- * XPM_EVENT_PLE_LRC,
- * XPM_EVENT_PLE_LRS,
- * XPM_EVENT_PLE_FLUSH,
- * XPM_EVENT_PLE_CMPL }
- *
- * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL,
- * XPM_EVENT_PLE_PROG,
- * XPM_EVENT_PLE_LRC,
- * XPM_EVENT_PLE_LRS,
- * XPM_EVENT_PLE_FLUSH,
- * XPM_EVENT_PLE_CMPL }
- *
- * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL,
- * XPM_EVENT_INSRFETCH_CACHEREFILL,
- * XPM_EVENT_INSTRFECT_TLBREFILL,
- * XPM_EVENT_DATA_CACHEREFILL,
- * XPM_EVENT_DATA_CACHEACCESS,
- * XPM_EVENT_DATA_TLBREFILL }
- */
-#define XPM_CNTRCFG1 0
-#define XPM_CNTRCFG2 1
-#define XPM_CNTRCFG3 2
-#define XPM_CNTRCFG4 3
-#define XPM_CNTRCFG5 4
-#define XPM_CNTRCFG6 5
-#define XPM_CNTRCFG7 6
-#define XPM_CNTRCFG8 7
-#define XPM_CNTRCFG9 8
-#define XPM_CNTRCFG10 9
-#define XPM_CNTRCFG11 10
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/**
-*@endcond
-*/
-
-/************************** Function Prototypes *****************************/
-
-/* Interface functions to access performance counters from abstraction layer */
-void Xpm_SetEvents(s32 PmcrCfg);
-void Xpm_GetEventCounters(u32 *PmCtrValue);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-* @} End of "addtogroup a9_event_counter_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ef/40d35a585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ef/40d35a585243001d18b399c1eb9b3628
deleted file mode 100644
index 9a87752..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ef/40d35a585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,361 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file asm_vectors.S
-*
-* This file contains the initial vector table for the Cortex A53 processor
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 5.00 pkp 05/21/14 Initial version
-* 6.02 pkp 12/21/16 Added support for floating point access
-* 6.02 pkp 01/22/17 Added support for EL1 non-secure and hypervisor
-* baremetal guest
-* 6.4 mus 06/14/17 Fixed bug in IRQInterruptHandler code snippet,
-* which checks for the FPEN bit of CPACR_EL1
-* 6.6 mus 01/19/18 Added isb after writing to the cpacr_el1/cptr_el3,
-* to ensure enabling/disabling of floating-point unit
-* is completed, before any subsequent instruction.
-* 7.5 mus 05/20/21 Fixed speculative execution past ERET and BR instructions.
-* As per CVE-2020-13844, Cortex-A72 is affected with
-* vulnearability, hence changes are targeted only for Cortex-A72.
-* It fixes CR#1083649.
-*
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#include "bspconfig.h"
-
-.org 0
-.text
-
-.globl _boot
-.globl _vector_table
-
-.globl FIQInterrupt
-.globl IRQInterrupt
-.globl SErrorInterrupt
-.globl SynchronousInterrupt
-.globl FPUStatus
-
-/*
- * FPUContextSize is the size of the array where floating point registers are
- * stored when required. The default size corresponds to the case when there is no
- * nested interrupt. If there are nested interrupts in application which are using
- * floating point operation, the size of FPUContextSize need to be increased as per
- * requirement
- */
-
-.set FPUContextSize, 528
-
-.macro saveregister
- stp X0,X1, [sp,#-0x10]!
- stp X2,X3, [sp,#-0x10]!
- stp X4,X5, [sp,#-0x10]!
- stp X6,X7, [sp,#-0x10]!
- stp X8,X9, [sp,#-0x10]!
- stp X10,X11, [sp,#-0x10]!
- stp X12,X13, [sp,#-0x10]!
- stp X14,X15, [sp,#-0x10]!
- stp X16,X17, [sp,#-0x10]!
- stp X18,X19, [sp,#-0x10]!
- stp X29,X30, [sp,#-0x10]!
-.endm
-
-.macro restoreregister
- ldp X29,X30, [sp], #0x10
- ldp X18,X19, [sp], #0x10
- ldp X16,X17, [sp], #0x10
- ldp X14,X15, [sp], #0x10
- ldp X12,X13, [sp], #0x10
- ldp X10,X11, [sp], #0x10
- ldp X8,X9, [sp], #0x10
- ldp X6,X7, [sp], #0x10
- ldp X4,X5, [sp], #0x10
- ldp X2,X3, [sp], #0x10
- ldp X0,X1, [sp], #0x10
-.endm
-
-.macro savefloatregister
-
-/* Load the floating point context array address from FPUContextBase */
- ldr x1,=FPUContextBase
- ldr x0, [x1]
-
-/* Save all the floating point register to the array */
- stp q0,q1, [x0], #0x20
- stp q2,q3, [x0], #0x20
- stp q4,q5, [x0], #0x20
- stp q6,q7, [x0], #0x20
- stp q8,q9, [x0], #0x20
- stp q10,q11, [x0], #0x20
- stp q12,q13, [x0], #0x20
- stp q14,q15, [x0], #0x20
- stp q16,q17, [x0], #0x20
- stp q18,q19, [x0], #0x20
- stp q20,q21, [x0], #0x20
- stp q22,q23, [x0], #0x20
- stp q24,q25, [x0], #0x20
- stp q26,q27, [x0], #0x20
- stp q28,q29, [x0], #0x20
- stp q30,q31, [x0], #0x20
- mrs x2, FPCR
- mrs x3, FPSR
- stp x2, x3, [x0], #0x10
-
-/* Save current address of floating point context array to FPUContextBase */
- str x0, [x1]
-.endm
-
-.macro restorefloatregister
-
-/* Restore the address of floating point context array from FPUContextBase */
- ldr x1,=FPUContextBase
- ldr x0, [x1]
-
-/* Restore all the floating point register from the array */
- ldp x2, x3, [x0,#-0x10]!
- msr FPCR, x2
- msr FPSR, x3
- ldp q30,q31, [x0,#-0x20]!
- ldp q28,q29, [x0,#-0x20]!
- ldp q26,q27, [x0,#-0x20]!
- ldp q24,q25, [x0,#-0x20]!
- ldp q22,q23, [x0,#-0x20]!
- ldp q20,q21, [x0,#-0x20]!
- ldp q18,q19, [x0,#-0x20]!
- ldp q16,q17, [x0,#-0x20]!
- ldp q14,q15, [x0,#-0x20]!
- ldp q12,q13, [x0,#-0x20]!
- ldp q10,q11, [x0,#-0x20]!
- ldp q8,q9, [x0,#-0x20]!
- ldp q6,q7, [x0,#-0x20]!
- ldp q4,q5, [x0,#-0x20]!
- ldp q2,q3, [x0,#-0x20]!
- ldp q0,q1, [x0,#-0x20]!
-
-/* Save current address of floating point context array to FPUContextBase */
- str x0, [x1]
-.endm
-
-.macro exception_return
- eret
-#if defined (versal)
- dsb nsh
- isb
-#endif
-.endm
-
-.org 0
-
-.section .vectors, "a"
-
-_vector_table:
-.set VBAR, _vector_table
-.org VBAR
-/*
- * if application is built for XEN GUEST as EL1 Non-secure following image
- * header is required by XEN.
- */
-.if (HYP_GUEST == 1)
-
- /* Valid Image header. */
- /* HW reset vector. */
- ldr x16, =_boot
- br x16
-#if defined (versal)
- dsb nsh
- isb
-#endif
- /* text offset. */
- .dword 0
- /* image size. */
- .dword 0
- /* flags. */
- .dword 8
- /* RES0 */
- .dword 0
- .dword 0
- .dword 0
-
- /* magic */
- .dword 0x644d5241
- /* RES0 */
- .dword 0
- /* End of Image header. */
-.endif
-
- b _boot
-.org (VBAR + 0x200)
- b SynchronousInterruptHandler
-
-.org (VBAR + 0x280)
- b IRQInterruptHandler
-
-.org (VBAR + 0x300)
- b FIQInterruptHandler
-
-.org (VBAR + 0x380)
- b SErrorInterruptHandler
-
-
-SynchronousInterruptHandler:
- saveregister
-
-/* Check if the Synchronous abort is occurred due to floating point access. */
-.if (EL3 == 1)
- mrs x0, ESR_EL3
-.else
- mrs x0, ESR_EL1
-.endif
- and x0, x0, #(0x3F << 26)
- mov x1, #(0x7 << 26)
- cmp x0, x1
-/* If exception is not due to floating point access go to synchronous handler */
- bne synchronoushandler
-
-/*
- * If excpetion occurred due to floating point access, Enable the floating point
- * access i.e. do not trap floating point instruction
- */
- .if (EL3 == 1)
- mrs x1,CPTR_EL3
- bic x1, x1, #(0x1<<10)
- msr CPTR_EL3, x1
-.else
- mrs x1,CPACR_EL1
- orr x1, x1, #(0x1<<20)
- msr CPACR_EL1, x1
-.endif
- isb
-
-/* If the floating point access was previously enabled, store FPU context
- * registers(storefloat).
- */
- ldr x0, =FPUStatus
- ldrb w1,[x0]
- cbnz w1, storefloat
-/*
- * If the floating point access was not enabled previously, save the status of
- * floating point accessibility i.e. enabled and store floating point context
- * array address(FPUContext) to FPUContextBase.
- */
- mov w1, #0x1
- strb w1, [x0]
- ldr x0, =FPUContext
- ldr x1, =FPUContextBase
- str x0,[x1]
- b restorecontext
-storefloat:
- savefloatregister
- b restorecontext
-synchronoushandler:
- bl SynchronousInterrupt
-restorecontext:
- restoreregister
- exception_return
-
-IRQInterruptHandler:
-
- saveregister
-/* Save the status of SPSR, ELR and CPTR to stack */
- .if (EL3 == 1)
- mrs x0, CPTR_EL3
- mrs x1, ELR_EL3
- mrs x2, SPSR_EL3
-.else
- mrs x0, CPACR_EL1
- mrs x1, ELR_EL1
- mrs x2, SPSR_EL1
-.endif
- stp x0, x1, [sp,#-0x10]!
- str x2, [sp,#-0x10]!
-
-/* Trap floating point access */
- .if (EL3 == 1)
- mrs x1,CPTR_EL3
- orr x1, x1, #(0x1<<10)
- msr CPTR_EL3, x1
-.else
- mrs x1,CPACR_EL1
- bic x1, x1, #(0x1<<20)
- msr CPACR_EL1, x1
-.endif
- isb
-
- bl IRQInterrupt
-/*
- * If floating point access is enabled during interrupt handling,
- * restore floating point registers.
- */
-
- .if (EL3 == 1)
- mrs x0, CPTR_EL3
- ands x0, x0, #(0x1<<10)
- bne RestorePrevState
-.else
- mrs x0,CPACR_EL1
- ands x0, x0, #(0x1<<20)
- beq RestorePrevState
-.endif
-
- restorefloatregister
-
-/* Restore the status of SPSR, ELR and CPTR from stack */
-RestorePrevState:
- ldr x2,[sp],0x10
- ldp x0, x1, [sp],0x10
- .if (EL3 == 1)
- msr CPTR_EL3, x0
- msr ELR_EL3, x1
- msr SPSR_EL3, x2
-.else
- msr CPACR_EL1, x0
- msr ELR_EL1, x1
- msr SPSR_EL1, x2
-.endif
- restoreregister
- exception_return
-
-FIQInterruptHandler:
-
- saveregister
-
- bl FIQInterrupt
-
- restoreregister
-
- exception_return
-
-SErrorInterruptHandler:
-
- saveregister
-
- bl SErrorInterrupt
-
- restoreregister
-
- exception_return
-
-
-.align 8
-/* Array to store floating point registers */
-FPUContext: .skip FPUContextSize
-
-/* Stores address for floating point context array */
-FPUContextBase: .skip 8
-
-FPUStatus: .skip 1
-
-.end
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ef/910fc8545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ef/910fc8545243001d18b399c1eb9b3628
deleted file mode 100644
index af11096..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ef/910fc8545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,404 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xqspips_options.c
-* @addtogroup qspips_v3_9
-* @{
-*
-* Contains functions for the configuration of the XQspiPs driver component.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00 sdm 11/25/10 First release
-* 2.00a kka 07/25/12 Removed the selection for the following options:
-* Master mode (XQSPIPS_MASTER_OPTION) and
-* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
-* as the QSPI driver supports the Master mode
-* and Flash Interface mode. The driver doesnot support
-* Slave mode or the legacy mode.
-* Added the option for setting the Holdb_dr bit in the
-* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
-* is the option to be used for setting this bit in the
-* configuration register.
-* 2.01a sg 02/03/13 SetDelays and GetDelays API's include DelayNss parameter.
-*
-* 2.02a hk 26/03/13 Removed XQspi_Reset() in Set_Options() function when
-* LQSPI_MODE_OPTION is set. Moved Enable() to XQpsiPs_LqspiRead().
-* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
-* to remove compilation warnings. CR# 868893.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xqspips.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/*
- * Create the table of options which are processed to get/set the device
- * options. These options are table driven to allow easy maintenance and
- * expansion of the options.
- */
-typedef struct {
- u32 Option;
- u32 Mask;
-} OptionsMap;
-
-static OptionsMap OptionsTable[] = {
- {XQSPIPS_CLK_ACTIVE_LOW_OPTION, XQSPIPS_CR_CPOL_MASK},
- {XQSPIPS_CLK_PHASE_1_OPTION, XQSPIPS_CR_CPHA_MASK},
- {XQSPIPS_FORCE_SSELECT_OPTION, XQSPIPS_CR_SSFORCE_MASK},
- {XQSPIPS_MANUAL_START_OPTION, XQSPIPS_CR_MANSTRTEN_MASK},
- {XQSPIPS_HOLD_B_DRIVE_OPTION, XQSPIPS_CR_HOLD_B_MASK},
-};
-
-#define XQSPIPS_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionsMap))
-
-/*****************************************************************************/
-/**
-*
-* This function sets the options for the QSPI device driver. The options control
-* how the device behaves relative to the QSPI bus. The device must be idle
-* rather than busy transferring data before setting these device options.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param Options contains the specified options to be set. This is a bit
-* mask where a 1 means to turn the option on, and a 0 means to
-* turn the option off. One or more bit values may be contained in
-* the mask. See the bit definitions named XQSPIPS_*_OPTIONS in
-* the file xqspips.h.
-*
-* @return
-* - XST_SUCCESS if options are successfully set.
-* - XST_DEVICE_BUSY if the device is currently transferring data.
-* The transfer must complete or be aborted before setting options.
-*
-* @note
-* This function is not thread-safe.
-*
-******************************************************************************/
-s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options)
-{
- u32 ConfigReg;
- unsigned int Index;
- u32 QspiOptions;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Do not allow to modify the Control Register while a transfer is in
- * progress. Not thread-safe.
- */
- if (InstancePtr->IsBusy) {
- return XST_DEVICE_BUSY;
- }
-
- QspiOptions = Options & XQSPIPS_LQSPI_MODE_OPTION;
- Options &= ~XQSPIPS_LQSPI_MODE_OPTION;
-
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
-
- /*
- * Loop through the options table, turning the option on or off
- * depending on whether the bit is set in the incoming options flag.
- */
- for (Index = 0; Index < XQSPIPS_NUM_OPTIONS; Index++) {
- if (Options & OptionsTable[Index].Option) {
- /* Turn it on */
- ConfigReg |= OptionsTable[Index].Mask;
- } else {
- /* Turn it off */
- ConfigReg &= ~(OptionsTable[Index].Mask);
- }
- }
-
- /*
- * Now write the control register. Leave it to the upper layers
- * to restart the device.
- */
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET,
- ConfigReg);
-
- /*
- * Check for the LQSPI configuration options.
- */
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_LQSPI_CR_OFFSET);
-
-
- if (QspiOptions & XQSPIPS_LQSPI_MODE_OPTION) {
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_LQSPI_CR_OFFSET,
- XQSPIPS_LQSPI_CR_RST_STATE);
- XQspiPs_SetSlaveSelect(InstancePtr);
- } else {
- ConfigReg &= ~XQSPIPS_LQSPI_CR_LINEAR_MASK;
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_LQSPI_CR_OFFSET, ConfigReg);
- }
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function gets the options for the QSPI device. The options control how
-* the device behaves relative to the QSPI bus.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return
-*
-* Options contains the specified options currently set. This is a bit value
-* where a 1 means the option is on, and a 0 means the option is off.
-* See the bit definitions named XQSPIPS_*_OPTIONS in file xqspips.h.
-*
-* @note None.
-*
-******************************************************************************/
-u32 XQspiPs_GetOptions(XQspiPs *InstancePtr)
-{
- u32 OptionsFlag = 0;
- u32 ConfigReg;
- unsigned int Index;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Get the current options from QSPI configuration register.
- */
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
-
- /*
- * Loop through the options table to grab options
- */
- for (Index = 0; Index < XQSPIPS_NUM_OPTIONS; Index++) {
- if (ConfigReg & OptionsTable[Index].Mask) {
- OptionsFlag |= OptionsTable[Index].Option;
- }
- }
-
- /*
- * Check for the LQSPI configuration options.
- */
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_LQSPI_CR_OFFSET);
-
- if ((ConfigReg & XQSPIPS_LQSPI_CR_LINEAR_MASK) != 0) {
- OptionsFlag |= XQSPIPS_LQSPI_MODE_OPTION;
- }
-
- return OptionsFlag;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets the clock prescaler for an QSPI device. The device
-* must be idle rather than busy transferring data before setting these device
-* options.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param Prescaler is the value that determine how much the clock should
-* be divided by. Use the XQSPIPS_CLK_PRESCALE_* constants defined
-* in xqspips.h for this setting.
-*
-* @return
-* - XST_SUCCESS if options are successfully set.
-* - XST_DEVICE_BUSY if the device is currently transferring data.
-* The transfer must complete or be aborted before setting options.
-*
-* @note
-* This function is not thread-safe.
-*
-******************************************************************************/
-s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler)
-{
- u32 ConfigReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(Prescaler <= XQSPIPS_CR_PRESC_MAXIMUM);
-
- /*
- * Do not allow the slave select to change while a transfer is in
- * progress. Not thread-safe.
- */
- if (InstancePtr->IsBusy) {
- return XST_DEVICE_BUSY;
- }
-
- /*
- * Read the configuration register, mask out the interesting bits, and set
- * them with the shifted value passed into the function. Write the
- * results back to the configuration register.
- */
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
-
- ConfigReg &= ~XQSPIPS_CR_PRESC_MASK;
- ConfigReg |= (u32) (Prescaler & XQSPIPS_CR_PRESC_MAXIMUM) <<
- XQSPIPS_CR_PRESC_SHIFT;
-
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET,
- ConfigReg);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function gets the clock prescaler of an QSPI device.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return The prescaler value.
-*
-* @note None.
-*
-*
-******************************************************************************/
-u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr)
-{
- u32 ConfigReg;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_CR_OFFSET);
-
- ConfigReg &= XQSPIPS_CR_PRESC_MASK;
-
- return (u8)(ConfigReg >> XQSPIPS_CR_PRESC_SHIFT);
-}
-
-/*****************************************************************************/
-/**
-*
-* This function sets the delay register for the QSPI device driver.
-* The delay register controls the Delay Between Transfers, Delay After
-* Transfers, and the Delay Initially. The default value is 0x0. The range of
-* each delay value is 0-255.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param DelayNss is the delay to de-assert slave select between
-* two word transfers.
-* @param DelayBtwn is the delay between one Slave Select being
-* de-activated and the activation of another slave. The delay is
-* the number of master clock periods given by DelayBtwn + 2.
-* @param DelayAfter define the delay between the last bit of the current
-* byte transfer and the first bit of the next byte transfer.
-* The delay in number of master clock periods is given as:
-* CHPA=0:DelayInit+DelayAfter+3
-* CHPA=1:DelayAfter+1
-* @param DelayInit is the delay between asserting the slave select signal
-* and the first bit transfer. The delay int number of master clock
-* periods is DelayInit+1.
-*
-* @return
-* - XST_SUCCESS if delays are successfully set.
-* - XST_DEVICE_BUSY if the device is currently transferring data.
-* The transfer must complete or be aborted before setting options.
-*
-* @note None.
-*
-******************************************************************************/
-int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
- u8 DelayAfter, u8 DelayInit)
-{
- u32 DelayRegister;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Do not allow the delays to change while a transfer is in
- * progress. Not thread-safe.
- */
- if (InstancePtr->IsBusy) {
- return XST_DEVICE_BUSY;
- }
-
- /* Shift, Mask and OR the values to build the register settings */
- DelayRegister = (u32) DelayNss << XQSPIPS_DR_NSS_SHIFT;
- DelayRegister |= (u32) DelayBtwn << XQSPIPS_DR_BTWN_SHIFT;
- DelayRegister |= (u32) DelayAfter << XQSPIPS_DR_AFTER_SHIFT;
- DelayRegister |= (u32) DelayInit;
-
- XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_DR_OFFSET, DelayRegister);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/**
-*
-* This function gets the delay settings for an QSPI device.
-* The delay register controls the Delay Between Transfers, Delay After
-* Transfers, and the Delay Initially. The default value is 0x0.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param DelayNss is a pointer to the Delay to de-assert slave select
-* between two word transfers.
-* @param DelayBtwn is a pointer to the Delay Between transfers value.
-* This is a return parameter.
-* @param DelayAfter is a pointer to the Delay After transfer value.
-* This is a return parameter.
-* @param DelayInit is a pointer to the Delay Initially value. This is
-* a return parameter.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
- u8 *DelayAfter, u8 *DelayInit)
-{
- u32 DelayRegister;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- DelayRegister = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
- XQSPIPS_DR_OFFSET);
-
- *DelayInit = (u8)(DelayRegister & XQSPIPS_DR_INIT_MASK);
-
- *DelayAfter = (u8)((DelayRegister & XQSPIPS_DR_AFTER_MASK) >>
- XQSPIPS_DR_AFTER_SHIFT);
-
- *DelayBtwn = (u8)((DelayRegister & XQSPIPS_DR_BTWN_MASK) >>
- XQSPIPS_DR_BTWN_SHIFT);
-
- *DelayNss = (u8)((DelayRegister & XQSPIPS_DR_NSS_MASK) >>
- XQSPIPS_DR_NSS_SHIFT);
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ef/a35252595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ef/a35252595243001d18b399c1eb9b3628
deleted file mode 100644
index 12fa312..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ef/a35252595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,125 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#ifndef FSL_H
-#define FSL_H
-/*****************************************************************************/
-/**
-*
-* @file fsl.h
-*
-* @addtogroup microblaze_fsl_macro MicroBlaze Processor FSL Macros
-*
-* Microblaze BSP includes macros to provide convenient access to accelerators
-* connected to the MicroBlaze Fast Simplex Link (FSL) Interfaces.To use these functions,
-* include the header file fsl.h in your source code
-*
-* @{
-*
-******************************************************************************/
-#include "mb_interface.h" /* Legacy reasons. We just have to include this guy who defines the FSL stuff */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *@cond nocomments
- */
-/* Extended FSL macros. These now replace all of the previous FSL macros */
-#define FSL_DEFAULT
-#define FSL_NONBLOCKING n
-#define FSL_EXCEPTION e
-#define FSL_CONTROL c
-#define FSL_ATOMIC a
-
-#define FSL_NONBLOCKING_EXCEPTION ne
-#define FSL_NONBLOCKING_CONTROL nc
-#define FSL_NONBLOCKING_ATOMIC na
-#define FSL_EXCEPTION_CONTROL ec
-#define FSL_EXCEPTION_ATOMIC ea
-#define FSL_CONTROL_ATOMIC ca
-
-#define FSL_NONBLOCKING_EXCEPTION_CONTROL nec
-#define FSL_NONBLOCKING_EXCEPTION_ATOMIC nea
-#define FSL_NONBLOCKING_CONTROL_ATOMIC nca
-#define FSL_EXCEPTION_CONTROL_ATOMIC eca
-
-#define FSL_NONBLOCKING_EXCEPTION_CONTROL_ATOMIC neca
-
- /**
- *@endcond
- */
-
-/**
-Performs a get function on an input FSL of the MicroBlaze processor
-@param val variable to sink data from get function
-@param id literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
-@param flags valid FSL macro flags
-*/
-#define getfslx(val, id, flags) asm volatile (stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
-
-/**
-Performs a put function on an input FSL of the MicroBlaze processor
-@param val variable to source data to put function
-@param id literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
-@param flags valid FSL macro flags
-*/
-#define putfslx(val, id, flags) asm volatile (stringify(flags) "put\t%0,rfsl" stringify(id) :: "d" (val))
-
-/**
-Performs a test get function on an input FSL of the MicroBlaze processor
-@param val variable to sink data from get function
-@param id literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
-@param flags valid FSL macro flags
-*/
-#define tgetfslx(val, id, flags) asm volatile ("t" stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
-
-/**
-Performs a put function on an input FSL of the MicroBlaze processor
-@param id FSL identifier
-@param flags valid FSL macro flags
-*/
-#define tputfslx(id, flags) asm volatile ("t" stringify(flags) "put\trfsl" stringify(id))
-
-/**
-Performs a getd function on an input FSL of the MicroBlaze processor
-@param val variable to sink data from getd function
-@param var literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
-@param flags valid FSL macro flags
-*/
-#define getdfslx(val, var, flags) asm volatile (stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
-
-/**
-Performs a putd function on an input FSL of the MicroBlaze processor
-@param val variable to source data to putd function
-@param var literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
-@param flags valid FSL macro flags
-*/
-#define putdfslx(val, var, flags) asm volatile (stringify(flags) "putd\t%0,%1" :: "d" (val), "d" (var))
-
-/**
-Performs a test getd function on an input FSL of the MicroBlaze processor;
-@param val variable to sink data from getd function
-@param var literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
-@param flags valid FSL macro flags
-*/
-#define tgetdfslx(val, var, flags) asm volatile ("t" stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
-
-/**
-Performs a put function on an input FSL of the MicroBlaze processor
-@param var FSL identifier
-@param flags valid FSL macro flags
-*/
-#define tputdfslx(var, flags) asm volatile ("t" stringify(flags) "putd\t%0" :: "d" (var))
-
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* FSL_H */
-/**
-* @} End of "addtogroup microblaze_fsl_macro".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ef/d19a21585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ef/d19a21585243001d18b399c1eb9b3628
deleted file mode 100644
index 4bf1905..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ef/d19a21585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,70 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xscutimer_sinit.c
-* @addtogroup scutimer_v2_3
-* @{
-*
-* This file contains method for static initialization (compile-time) of the
-* driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a nm 03/10/10 First release
-* 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance.
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xscutimer.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions ****************************/
-extern XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES];
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-* Lookup the device configuration based on the unique device ID. The table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId is the unique device ID of the device being looked up.
-*
-* @return A pointer to the configuration table entry corresponding to the
-* given device ID, or NULL if no match is found.
-*
-* @note None.
-*
-******************************************************************************/
-XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId)
-{
- XScuTimer_Config *CfgPtr = NULL;
- u32 Index;
-
- for (Index = 0U; Index < XPAR_XSCUTIMER_NUM_INSTANCES; Index++) {
- if (XScuTimer_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XScuTimer_ConfigTable[Index];
- break;
- }
- }
-
- return (XScuTimer_Config *)CfgPtr;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ef/f08420545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ef/f08420545243001d18b399c1eb9b3628
deleted file mode 100644
index 99b1375..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ef/f08420545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,113 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xbasic_types.h
-*
-*
-* @note Dummy File for backwards compatibility
-*
-
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
-* 7.0 aru 01/21/19 Modified the typedef of u32,u16,u8
-* 7.0 aru 02/06/19 Included stdint.h and stddef.h
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
-#define XBASIC_TYPES_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include
-#include
-
-/** @name Legacy types
- * Deprecated legacy types.
- * @{
- */
-typedef uint8_t Xuint8; /**< unsigned 8-bit */
-typedef char Xint8; /**< signed 8-bit */
-typedef uint16_t Xuint16; /**< unsigned 16-bit */
-typedef short Xint16; /**< signed 16-bit */
-typedef uint32_t Xuint32; /**< unsigned 32-bit */
-typedef long Xint32; /**< signed 32-bit */
-typedef float Xfloat32; /**< 32-bit floating point */
-typedef double Xfloat64; /**< 64-bit double precision FP */
-typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
-
-#if !defined __XUINT64__
-typedef struct
-{
- Xuint32 Upper;
- Xuint32 Lower;
-} Xuint64;
-#endif
-
-/** @name New types
- * New simple types.
- * @{
- */
-#ifndef __KERNEL__
-#ifndef XIL_TYPES_H
-typedef Xuint32 u32;
-typedef Xuint16 u16;
-typedef Xuint8 u8;
-#endif
-#else
-#include
-#endif
-
-#ifndef TRUE
-# define TRUE 1U
-#endif
-
-#ifndef FALSE
-# define FALSE 0U
-#endif
-
-#ifndef NULL
-#define NULL 0U
-#endif
-
-/*
- * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
- * Please use NULL, TRUE and FALSE
- */
-#define XNULL NULL
-#define XTRUE TRUE
-#define XFALSE FALSE
-
-/*
- * This file is deprecated and users
- * should use xil_types.h and xil_assert.h\n\r
- */
-#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
-#warning Please refer the Standalone BSP UG647 for further details
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f/001457565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f/001457565243001d18b399c1eb9b3628
deleted file mode 100644
index 77e1f3d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f/001457565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,74 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache_vxworks.h
-*
-* Contains the cache related functions for VxWorks that is wrapped by
-* xil_cache.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 12/11/09 Initial release
-*
-*
-*
-* @note
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_CACHE_VXWORKS_H
-#define XIL_CACHE_VXWORKS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "vxWorks.h"
-#include "vxLib.h"
-#include "sysLibExtra.h"
-#include "cacheLib.h"
-
-#if (CPU_FAMILY==PPC)
-
-#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
-
-#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
-
-#define Xil_DCacheInvalidateRange(Addr, Len) \
- cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
-
-#define Xil_DCacheFlushRange(Addr, Len) \
- cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
-
-#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
-
-#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
-
-#define Xil_ICacheInvalidateRange(Addr, Len) \
- cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
-
-
-#else
-#error "Unknown processor / architecture. Must be PPC for VxWorks."
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
- *@endcond
- */
\ No newline at end of file
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f/00d42b585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f/00d42b585243001d18b399c1eb9b3628
deleted file mode 100644
index ab2b506..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f/00d42b585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,454 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xsdps.c
-* @addtogroup sdps_v3_13
-* @{
-*
-* Contains the interface functions of the XSdPs driver.
-* See xsdps.h for a detailed description of the device and driver.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a hk/sg 10/17/13 Initial release
-* 2.0 hk 12/13/13 Added check for arm to use sleep.h and its API's
-* 2.1 hk 04/18/14 Add sleep for microblaze designs. CR# 781117.
-* 2.2 hk 07/28/14 Make changes to enable use of data cache.
-* 2.3 sk 09/23/14 Send command for relative card address
-* when re-initialization is done.CR# 819614.
-* Use XSdPs_Change_ClkFreq API whenever changing
-* clock.CR# 816586.
-* 2.4 sk 12/04/14 Added support for micro SD without
-* WP/CD. CR# 810655.
-* Checked for DAT Inhibit mask instead of CMD
-* Inhibit mask in Cmd Transfer API.
-* Added Support for SD Card v1.0
-* 2.5 sg 07/09/15 Added SD 3.0 features
-* kvn 07/15/15 Modified the code according to MISRAC-2012.
-* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
-* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
-* sk 12/10/15 Added support for MMC cards.
-* sk 02/16/16 Corrected the Tuning logic.
-* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
-* 2.8 sk 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
-* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
-* sk 07/16/16 Added support for UHS modes.
-* sk 07/07/16 Used usleep API for both arm and microblaze.
-* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
-* operating modes.
-* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
-* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
-* sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
-* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
-* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
-* sk 02/01/17 Added HSD and DDR mode support for eMMC.
-* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
-* sk 03/20/17 Add support for EL1 non-secure mode.
-* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
-* mn 07/17/17 Add support for running SD at 200MHz
-* mn 07/26/17 Fixed compilation warnings
-* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
-* mn 08/17/17 Added CCI support for A53 and disabled data cache
-* operations when it is enabled.
-* mn 08/22/17 Updated for Word Access System support
-* mn 09/06/17 Resolved compilation errors with IAR toolchain
-* mn 09/26/17 Added UHS_MODE_ENABLE macro to enable UHS mode
-* 3.4 mn 10/17/17 Use different commands for single and multi block
-* transfers
-* mn 03/02/18 Move UHS macro check to SD card initialization routine
-* 3.5 mn 04/18/18 Resolve compilation warnings for sdps driver
-* 3.6 mn 07/06/18 Fix Cppcheck and Doxygen warnings for sdps driver
-* mn 08/01/18 Add support for using 64Bit DMA with 32-Bit Processor
-* mn 08/01/18 Add cache invalidation call before returning from
-* ReadPolled API
-* mn 08/14/18 Resolve compilation warnings for ARMCC toolchain
-* mn 10/01/18 Change Expected Response for CMD3 to R1 for MMC
-* mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
-* 3.7 mn 02/01/19 Add support for idling of SDIO
-* aru 03/12/19 Modified the code according to MISRAC-2012.
-* 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
-* mn 09/17/19 Modified ADMA handling API for 32bit and 64bit addresses
-* 3.9 sd 02/07/20 Added clock support
-* mn 03/03/20 Restructured the code for more readability and modularity
-* mn 03/30/20 Return XST_DEVICE_IS_STARTED when host is already started
-* mn 03/30/20 Move Clock enabling before checking for Host already started
-* 3.10 mn 06/05/20 Check Transfer completion separately from XSdPs_Read and
-* XSdPs_Write APIs
-* mn 06/05/20 Modified code for SD Non-Blocking Read support
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-#include "xsdps_core.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-/*****************************************************************************/
-/**
-*
-* @brief
-* Initializes a specific XSdPs instance such that the driver is ready to use.
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-* @param ConfigPtr is a reference to a structure containing information
-* about a specific SD device. This function initializes an
-* InstancePtr object for a specific device specified by the
-* contents of Config.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. The caller is responsible for keeping the address
-* mapping from EffectiveAddr to the device physical base address
-* unchanged once this function is invoked. Unexpected errors may
-* occur if the address mapping changes after this function is
-* called. If address translation is not used, use
-* ConfigPtr->Config.BaseAddress for this device.
-*
-* @return
-* - XST_SUCCESS if successful.
-* - XST_DEVICE_IS_STARTED if the device is already started.
-* It must be stopped to re-initialize.
-*
-* @note This function initializes the host controller.
-* Initial clock of 400KHz is set.
-* Voltage of 3.3V is selected as that is supported by host.
-* Interrupts status is enabled and signal disabled by default.
-* Default data direction is card to host and
-* 32 bit ADMA2 is selected. Default Block size is 512 bytes.
-*
-******************************************************************************/
-s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
- u32 EffectiveAddr)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(ConfigPtr != NULL);
-
-#if defined (XCLOCKING)
- InstancePtr->Config.RefClk = ConfigPtr->RefClk;
- Xil_ClockEnable(InstancePtr->Config.RefClk);
-#endif
- /* If this API is getting called twice, return value accordingly */
- if (InstancePtr->IsReady == XIL_COMPONENT_IS_READY) {
- Status = (s32)XST_DEVICE_IS_STARTED;
- goto RETURN_PATH ;
- }
-
- /* Set some default values. */
- InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
- InstancePtr->Config.BaseAddress = EffectiveAddr;
- InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
- InstancePtr->Config.CardDetect = ConfigPtr->CardDetect;
- InstancePtr->Config.WriteProtect = ConfigPtr->WriteProtect;
- InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
- InstancePtr->Config.BankNumber = ConfigPtr->BankNumber;
- InstancePtr->Config.HasEMIO = ConfigPtr->HasEMIO;
- InstancePtr->Config.IsCacheCoherent = ConfigPtr->IsCacheCoherent;
- InstancePtr->SectorCount = 0U;
- InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
- InstancePtr->OTapDelay = 0U;
- InstancePtr->ITapDelay = 0U;
- InstancePtr->Dma64BitAddr = 0U;
- InstancePtr->SlcrBaseAddr = XPS_SYS_CTRL_BASEADDR;
- InstancePtr->IsBusy = FALSE;
- InstancePtr->BlkSize = 0U;
-
- /* Host Controller version is read. */
- InstancePtr->HC_Version =
- (u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
- XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK);
-
- /*
- * Read capabilities register and update it in Instance pointer.
- * It is sufficient to read this once on power on.
- */
- InstancePtr->Host_Caps = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
- XSDPS_CAPS_OFFSET);
-
- /* Reset the SD bus lines */
- Status = XSdPs_ResetConfig(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- /* Configure the SD Host Controller */
- XSdPs_HostConfig(InstancePtr);
-
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
-RETURN_PATH:
-#if defined (XCLOCKING)
- Xil_ClockDisable(InstancePtr->Config.RefClk);
-#endif
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* Initialize Card with Identification mode sequence
-*
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because
-* a) SD is already initialized
-* b) There is no card inserted
-* c) One of the steps (commands) in the
-* initialization cycle failed
-*
-*
-******************************************************************************/
-s32 XSdPs_CardInitialize(XSdPs *InstancePtr)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /* Default settings */
- InstancePtr->BusWidth = XSDPS_1_BIT_WIDTH;
- InstancePtr->CardType = XSDPS_CARD_SD;
- InstancePtr->Switch1v8 = 0U;
- InstancePtr->BusSpeed = XSDPS_CLK_400_KHZ;
-
-#if defined (XCLOCKING)
- Xil_ClockEnable(InstancePtr->Config.RefClk);
-#endif
-
- /* Change the clock frequency to 400 KHz */
- Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- /* Identify the Card whether it is SD, MMC or eMMC */
- Status = XSdPs_IdentifyCard(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Initialize the identified card */
- if (InstancePtr->CardType == XSDPS_CARD_SD) {
- Status = XSdPs_SdCardInitialize(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- } else {
- Status = XSdPs_MmcCardInitialize(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
- }
-
-RETURN_PATH:
-#if defined (XCLOCKING)
- Xil_ClockDisable(InstancePtr->Config.RefClk);
-#endif
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function performs SD read in polled mode.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Arg is the address passed by the user that is to be sent as
-* argument along with the command.
-* @param BlkCnt - Block count passed by the user.
-* @param Buff - Pointer to the data buffer for a DMA transfer.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because another transfer
-* is in progress or command or data inhibit is set
-*
-******************************************************************************/
-s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- if (InstancePtr->IsBusy == TRUE) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
-#if defined (XCLOCKING)
- Xil_ClockEnable(InstancePtr->Config.RefClk);
-#endif
-
- /* Setup the Read Transfer */
- Status = XSdPs_SetupTransfer(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Read from the card */
- Status = XSdPs_Read(InstancePtr, Arg, BlkCnt, Buff);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Check for transfer done */
- Status = XSdps_CheckTransferDone(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- if (InstancePtr->Config.IsCacheCoherent == 0U) {
- Xil_DCacheInvalidateRange((INTPTR)Buff,
- (INTPTR)BlkCnt * InstancePtr->BlkSize);
- }
-
-RETURN_PATH:
-#if defined (XCLOCKING)
- Xil_ClockDisable(InstancePtr->Config.RefClk);
-#endif
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief
-* This function performs SD write in polled mode.
-*
-* @param InstancePtr is a pointer to the instance to be worked on.
-* @param Arg is the address passed by the user that is to be sent as
-* argument along with the command.
-* @param BlkCnt - Block count passed by the user.
-* @param Buff - Pointer to the data buffer for a DMA transfer.
-*
-* @return
-* - XST_SUCCESS if initialization was successful
-* - XST_FAILURE if failure - could be because another transfer
-* is in progress or command or data inhibit is set
-*
-******************************************************************************/
-s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- if (InstancePtr->IsBusy == TRUE) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
-#if defined (XCLOCKING)
- Xil_ClockEnable(InstancePtr->Config.RefClk);
-#endif
-
- /* Setup the Write Transfer */
- Status = XSdPs_SetupTransfer(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Write to the card */
- Status = XSdPs_Write(InstancePtr, Arg, BlkCnt, Buff);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
- /* Check for transfer done */
- Status = XSdps_CheckTransferDone(InstancePtr);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH;
- }
-
-RETURN_PATH:
-#if defined (XCLOCKING)
- Xil_ClockDisable(InstancePtr->Config.RefClk);
-#endif
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief
-* API to idle the SDIO Interface
-*
-*
-* @param InstancePtr is a pointer to the XSdPs instance.
-*
-* @return None
-*
-* @note None.
-*
-******************************************************************************/
-s32 XSdPs_Idle(XSdPs *InstancePtr)
-{
- s32 Status;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-#if defined (XCLOCKING)
- Xil_ClockEnable(InstancePtr->Config.RefClk);
-#endif
-
- /* Check if the bus is idle */
- Status = XSdPs_CheckBusIdle(InstancePtr, XSDPS_PSR_INHIBIT_CMD_MASK
- | XSDPS_PSR_INHIBIT_DAT_MASK
- | XSDPS_PSR_DAT_ACTIVE_MASK);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- /* Disable the Bus Power */
- XSdPs_DisableBusPower(InstancePtr);
-
- /* Reset Command and Data Lines */
- Status = XSdPs_Reset(InstancePtr, XSDPS_SWRST_ALL_MASK);
- if (Status != XST_SUCCESS) {
- Status = XST_FAILURE;
- goto RETURN_PATH ;
- }
-
- Status = XST_SUCCESS;
-
-RETURN_PATH:
-#if defined (XCLOCKING)
- Xil_ClockDisable(InstancePtr->Config.RefClk);
-#endif
- return Status;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f/030a9a595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f/030a9a595243001d18b399c1eb9b3628
deleted file mode 100644
index 21c8ced..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f/030a9a595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,75 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache_l.h
-*
-* Contains L1 and L2 specific functions for the ARM cache functionality
-* used by xcache.c. This functionality is being made available here for
-* more sophisticated users.
-*
-* @addtogroup a9_cache_apis
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 01/24/10 First release
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-*
-******************************************************************************/
-#ifndef XIL_CACHE_MACH_H
-#define XIL_CACHE_MACH_H
-
-#include "xil_types.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Function Prototypes ******************************/
-
-void Xil_DCacheInvalidateLine(u32 adr);
-void Xil_DCacheFlushLine(u32 adr);
-void Xil_DCacheStoreLine(u32 adr);
-void Xil_ICacheInvalidateLine(u32 adr);
-
-void Xil_L1DCacheEnable(void);
-void Xil_L1DCacheDisable(void);
-void Xil_L1DCacheInvalidate(void);
-void Xil_L1DCacheInvalidateLine(u32 adr);
-void Xil_L1DCacheInvalidateRange(u32 adr, u32 len);
-void Xil_L1DCacheFlush(void);
-void Xil_L1DCacheFlushLine(u32 adr);
-void Xil_L1DCacheFlushRange(u32 adr, u32 len);
-void Xil_L1DCacheStoreLine(u32 adr);
-
-void Xil_L1ICacheEnable(void);
-void Xil_L1ICacheDisable(void);
-void Xil_L1ICacheInvalidate(void);
-void Xil_L1ICacheInvalidateLine(u32 adr);
-void Xil_L1ICacheInvalidateRange(u32 adr, u32 len);
-
-void Xil_L2CacheEnable(void);
-void Xil_L2CacheDisable(void);
-void Xil_L2CacheInvalidate(void);
-void Xil_L2CacheInvalidateLine(u32 adr);
-void Xil_L2CacheInvalidateRange(u32 adr, u32 len);
-void Xil_L2CacheFlush(void);
-void Xil_L2CacheFlushLine(u32 adr);
-void Xil_L2CacheFlushRange(u32 adr, u32 len);
-void Xil_L2CacheStoreLine(u32 adr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-* @} End of "addtogroup a9_cache_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f/918978575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f/918978575243001d18b399c1eb9b3628
deleted file mode 100644
index 33b33eb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f/918978575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,167 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xgpio_l.h
-* @addtogroup gpio_v4_8
-* @{
-*
-* This header file contains identifiers and driver functions (or
-* macros) that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-*
-* The macros that are available in this file use a multiply to calculate the
-* addresses of registers. The user can control whether that multiply is done
-* at run time or at compile time. A constant passed as the channel parameter
-* will cause the multiply to be done at compile time. A variable passed as the
-* channel parameter will cause it to occur at run time.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a jhl 04/24/02 First release of low level driver
-* 2.00a jhl 11/26/03 Added support for dual channels and interrupts. This
-* change required the functions to be changed such that
-* the interface is not compatible with previous versions.
-* See the examples in the example directory for macros
-* to help compile an application that was designed for
-* previous versions of the driver. The interrupt registers
-* are accessible using the ReadReg and WriteReg macros and
-* a channel parameter was added to the other macros.
-* 2.11a mta 03/21/07 Updated to new coding style
-* 2.12a sv 11/21/07 Updated driver to support access through DCR bus.
-* 3.00a sv 11/21/09 Renamed the macros XGpio_mWriteReg to XGpio_WriteReg
-* XGpio_mReadReg to XGpio_ReadReg.
-* Removed the macros XGpio_mSetDataDirection,
-* XGpio_mGetDataReg and XGpio_mSetDataReg. Users
-* should use XGpio_WriteReg/XGpio_ReadReg to achieve the
-* same functionality.
-* 4.1 lks 11/18/15 Removed support for DCR bridge
-*
-*
-******************************************************************************/
-
-#ifndef XGPIO_L_H /* prevent circular inclusions */
-#define XGPIO_L_H /**< by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-
-/************************** Constant Definitions *****************************/
-
-/** @name Registers
- *
- * Register offsets for this device.
- * @{
- */
-#define XGPIO_DATA_OFFSET 0x0 /**< Data register for 1st channel */
-#define XGPIO_TRI_OFFSET 0x4 /**< I/O direction reg for 1st channel */
-#define XGPIO_DATA2_OFFSET 0x8 /**< Data register for 2nd channel */
-#define XGPIO_TRI2_OFFSET 0xC /**< I/O direction reg for 2nd channel */
-
-#define XGPIO_GIE_OFFSET 0x11C /**< Glogal interrupt enable register */
-#define XGPIO_ISR_OFFSET 0x120 /**< Interrupt status register */
-#define XGPIO_IER_OFFSET 0x128 /**< Interrupt enable register */
-
-/** @} */
-
-/* The following constant describes the offset of each channels data and
- * tristate register from the base address.
- */
-#define XGPIO_CHAN_OFFSET 8 /**< Channel offeset */
-
-/** @name Interrupt Status and Enable Register bitmaps and masks
- *
- * Bit definitions for the interrupt status register and interrupt enable
- * registers.
- * @{
- */
-#define XGPIO_IR_MASK 0x3 /**< Mask of all bits */
-#define XGPIO_IR_CH1_MASK 0x1 /**< Mask for the 1st channel */
-#define XGPIO_IR_CH2_MASK 0x2 /**< Mask for the 2nd channel */
-/** @}*/
-
-
-/** @name Global Interrupt Enable Register bitmaps and masks
- *
- * Bit definitions for the Global Interrupt Enable register
- * @{
- */
-#define XGPIO_GIE_GINTR_ENABLE_MASK 0x80000000 /**< Mask for Global Interrupt */
-/** @}*/
-
-
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#define XGpio_In32 Xil_In32 /**< Input Operations */
-#define XGpio_Out32 Xil_Out32 /**< Output Operations */
-
-
-/****************************************************************************/
-/**
-*
-* Write a value to a GPIO register. A 32 bit write is performed. If the
-* GPIO core is implemented in a smaller width, only the least significant data
-* is written.
-*
-* @param BaseAddress is the base address of the GPIO device.
-* @param RegOffset is the register offset from the base to write to.
-* @param Data is the data written to the register.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XGpio_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
-*
-****************************************************************************/
-#define XGpio_WriteReg(BaseAddress, RegOffset, Data) \
- XGpio_Out32((BaseAddress) + (RegOffset), (u32)(Data))
-
-/****************************************************************************/
-/**
-*
-* Read a value from a GPIO register. A 32 bit read is performed. If the
-* GPIO core is implemented in a smaller width, only the least
-* significant data is read from the register. The most significant data
-* will be read as 0.
-*
-* @param BaseAddress is the base address of the GPIO device.
-* @param RegOffset is the register offset from the base to read from.
-*
-* @return Data read from the register.
-*
-* @note C-style signature:
-* u32 XGpio_ReadReg(u32 BaseAddress, u32 RegOffset)
-*
-****************************************************************************/
-#define XGpio_ReadReg(BaseAddress, RegOffset) \
- XGpio_In32((BaseAddress) + (RegOffset))
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f0/003507585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f0/003507585243001d18b399c1eb9b3628
deleted file mode 100644
index c4b6b47..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f0/003507585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,74 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xqspips_sinit.c
-* @addtogroup qspips_v3_9
-* @{
-*
-* The implementation of the XQspiPs component's static initialization
-* functionality.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00 sdm 11/25/10 First release
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xqspips.h"
-#include "xparameters.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-extern XQspiPs_Config XQspiPs_ConfigTable[];
-
-/*****************************************************************************/
-/**
-*
-* Looks up the device configuration based on the unique device ID. A table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId contains the ID of the device to look up the
-* configuration for.
-*
-* @return
-*
-* A pointer to the configuration found or NULL if the specified device ID was
-* not found. See xqspips.h for the definition of XQspiPs_Config.
-*
-* @note None.
-*
-******************************************************************************/
-XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId)
-{
- XQspiPs_Config *CfgPtr = NULL;
- int Index;
-
- for (Index = 0; Index < XPAR_XQSPIPS_NUM_INSTANCES; Index++) {
- if (XQspiPs_ConfigTable[Index].DeviceId == DeviceId) {
- CfgPtr = &XQspiPs_ConfigTable[Index];
- break;
- }
- }
- return CfgPtr;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f0/50c299565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f0/50c299565243001d18b399c1eb9b3628
deleted file mode 100644
index 3373b83..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f0/50c299565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,149 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2018 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file microblaze_instructions.h
-*
-* It provides wrapper macros to call 32/64 bit variant of specific
-* arithmetic/logical instructions, based on the processor in execution.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.8 mus 10/09/18 First release
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00 drg/jz 01/13/10 First Release
-* 2.2 hk 06/23/14 SW reset of RX and TX should be done when changing
-* baud rate. CR# 804281.
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.1 kvn 04/10/15 Modified code for latest RTL changes.
-* 3.5 NK 09/26/17 Fix the RX Buffer Overflow issue.
-* 3.7 aru 08/17/18 Resolved MISRA-C mandatory violations.(CR#1007755)
-* 3.9 sd 02/06/20 Added clock support
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xstatus.h"
-#include "xuartps.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions ****************************/
-
-/* The following constant defines the amount of error that is allowed for
- * a specified baud rate. This error is the difference between the actual
- * baud rate that will be generated using the specified clock and the
- * desired baud rate.
- */
-#define XUARTPS_MAX_BAUD_ERROR_RATE 3U /* max % error allowed */
-
-/**************************** Type Definitions ******************************/
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Function Prototypes *****************************/
-
-static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
- u32 ByteCount);
-
-u32 XUartPs_SendBuffer(XUartPs *InstancePtr);
-
-u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
-
-/************************** Variable Definitions ****************************/
-
-/****************************************************************************/
-/**
-*
-* Initializes a specific XUartPs instance such that it is ready to be used.
-* The data format of the device is setup for 8 data bits, 1 stop bit, and no
-* parity by default. The baud rate is set to a default value specified by
-* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The
-* receive FIFO threshold is set for 8 bytes. The default operating mode of the
-* driver is polled mode.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param Config is a reference to a structure containing information
-* about a specific XUartPs driver.
-* @param EffectiveAddr is the device base address in the virtual memory
-* address space. The caller is responsible for keeping the address
-* mapping from EffectiveAddr to the device physical base address
-* unchanged once this function is invoked. Unexpected errors may
-* occur if the address mapping changes after this function is
-* called. If address translation is not used, pass in the physical
-* address instead.
-*
-* @return
-*
-* - XST_SUCCESS if initialization was successful
-* - XST_UART_BAUD_ERROR if the baud rate is not possible because
-* the inputclock frequency is not divisible with an acceptable
-* amount of error
-*
-* @note
-*
-* The default configuration for the UART after initialization is:
-*
-* - 19,200 bps or XPAR_DFT_BAUDRATE if defined
-* - 8 data bits
-* - 1 stop bit
-* - no parity
-* - FIFO's are enabled with a receive threshold of 8 bytes
-* - The RX timeout is enabled with a timeout of 1 (4 char times)
-*
-* All interrupts are disabled.
-*
-*****************************************************************************/
-s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
- XUartPs_Config * Config, u32 EffectiveAddr)
-{
- s32 Status;
- u32 ModeRegister;
- u32 BaudRate;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(Config != NULL);
-
- /* Setup the driver instance using passed in parameters */
- InstancePtr->Config.BaseAddress = EffectiveAddr;
- InstancePtr->Config.InputClockHz = Config->InputClockHz;
-#if defined (XCLOCKING)
- InstancePtr->Config.RefClk = Config->RefClk;
-#endif
- InstancePtr->Config.ModemPinsConnected = Config->ModemPinsConnected;
-
- /* Initialize other instance data to default values */
- InstancePtr->Handler = (XUartPs_Handler)XUartPs_StubHandler;
-
- InstancePtr->SendBuffer.NextBytePtr = NULL;
- InstancePtr->SendBuffer.RemainingBytes = 0U;
- InstancePtr->SendBuffer.RequestedBytes = 0U;
-
- InstancePtr->ReceiveBuffer.NextBytePtr = NULL;
- InstancePtr->ReceiveBuffer.RemainingBytes = 0U;
- InstancePtr->ReceiveBuffer.RequestedBytes = 0U;
-
- /* Initialize the platform data */
- InstancePtr->Platform = XGetPlatform_Info();
-
- InstancePtr->is_rxbs_error = 0U;
-
- /* Flag that the driver instance is ready to use */
- InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
-
- /*
- * Set the default baud rate here, can be changed prior to
- * starting the device
- */
- BaudRate = (u32)XUARTPS_DFT_BAUDRATE;
- Status = XUartPs_SetBaudRate(InstancePtr, BaudRate);
- if (Status != (s32)XST_SUCCESS) {
- InstancePtr->IsReady = 0U;
- } else {
-
- /*
- * Set up the default data format: 8 bit data, 1 stop bit, no
- * parity
- */
- ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_MR_OFFSET);
-
- /* Mask off what's already there */
- ModeRegister &= (~((u32)XUARTPS_MR_CHARLEN_MASK |
- (u32)XUARTPS_MR_STOPMODE_MASK |
- (u32)XUARTPS_MR_PARITY_MASK));
-
- /* Set the register value to the desired data format */
- ModeRegister |= ((u32)XUARTPS_MR_CHARLEN_8_BIT |
- (u32)XUARTPS_MR_STOPMODE_1_BIT |
- (u32)XUARTPS_MR_PARITY_NONE);
-
- /* Write the mode register out */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
- ModeRegister);
-
- /* Set the RX FIFO trigger at 8 data bytes. */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_RXWM_OFFSET, 0x08U);
-
- /* Set the RX timeout to 1, which will be 4 character time */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_RXTOUT_OFFSET, 0x01U);
-
- /* Disable all interrupts, polled mode is the default */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
- XUARTPS_IXR_MASK);
-
- Status = XST_SUCCESS;
- }
- return Status;
-}
-
-/****************************************************************************/
-/**
-*
-* This functions sends the specified buffer using the device in either
-* polled or interrupt driven mode. This function is non-blocking, if the device
-* is busy sending data, it will return and indicate zero bytes were sent.
-* Otherwise, it fills the TX FIFO as much as it can, and return the number of
-* bytes sent.
-*
-* In a polled mode, this function will only send as much data as TX FIFO can
-* buffer. The application may need to call it repeatedly to send the entire
-* buffer.
-*
-* In interrupt mode, this function will start sending the specified buffer,
-* then the interrupt handler will continue sending data until the entire
-* buffer has been sent. A callback function, as specified by the application,
-* will be called to indicate the completion of sending.
-*
-* @param InstancePtr is a pointer to the XUartPs instance.
-* @param BufferPtr is pointer to a buffer of data to be sent.
-* @param NumBytes contains the number of bytes to be sent. A value of
-* zero will stop a previous send operation that is in progress
-* in interrupt mode. Any data that was already put into the
-* transmit FIFO will be sent.
-*
-* @return The number of bytes actually sent.
-*
-* @note
-*
-* The number of bytes is not asserted so that this function may be called with
-* a value of zero to stop an operation that is already in progress.
-*
-*
-*****************************************************************************/
-u32 XUartPs_Send(XUartPs *InstancePtr, u8 *BufferPtr,
- u32 NumBytes)
-{
- u32 BytesSent;
-
- /* Asserts validate the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(BufferPtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-#if defined (XCLOCKING)
- Xil_ClockEnable(InstancePtr->Config.RefClk);
-#endif
- /*
- * Disable the UART transmit interrupts to allow this call to stop a
- * previous operation that may be interrupt driven.
- */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
- (XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_TXFULL));
-
- /* Setup the buffer parameters */
- InstancePtr->SendBuffer.RequestedBytes = NumBytes;
- InstancePtr->SendBuffer.RemainingBytes = NumBytes;
- InstancePtr->SendBuffer.NextBytePtr = BufferPtr;
-
- /*
- * Transmit interrupts will be enabled in XUartPs_SendBuffer(), after
- * filling the TX FIFO.
- */
- BytesSent = XUartPs_SendBuffer(InstancePtr);
-
- return BytesSent;
-}
-
-/****************************************************************************/
-/**
-*
-* This function attempts to receive a specified number of bytes of data
-* from the device and store it into the specified buffer. This function works
-* for both polled or interrupt driven modes. It is non-blocking.
-*
-* In a polled mode, this function will only receive the data already in the
-* RX FIFO. The application may need to call it repeatedly to receive the
-* entire buffer. Polled mode is the default mode of operation for the device.
-*
-* In interrupt mode, this function will start the receiving, if not the entire
-* buffer has been received, the interrupt handler will continue receiving data
-* until the entire buffer has been received. A callback function, as specified
-* by the application, will be called to indicate the completion of the
-* receiving or error conditions.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-* @param BufferPtr is pointer to buffer for data to be received into
-* @param NumBytes is the number of bytes to be received. A value of zero
-* will stop a previous receive operation that is in progress in
-* interrupt mode.
-*
-* @return The number of bytes received.
-*
-* @note
-*
-* The number of bytes is not asserted so that this function may be called
-* with a value of zero to stop an operation that is already in progress.
-*
-*****************************************************************************/
-u32 XUartPs_Recv(XUartPs *InstancePtr,
- u8 *BufferPtr, u32 NumBytes)
-{
- u32 ReceivedCount;
- u32 ImrRegister;
-
- /* Assert validates the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(BufferPtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
-#if defined (XCLOCKING)
- Xil_ClockEnable(InstancePtr->Config.RefClk);
-#endif
- /*
- * Disable all the interrupts.
- * This stops a previous operation that may be interrupt driven
- */
- ImrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IMR_OFFSET);
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
- XUARTPS_IXR_MASK);
-
- /* Setup the buffer parameters */
- InstancePtr->ReceiveBuffer.RequestedBytes = NumBytes;
- InstancePtr->ReceiveBuffer.RemainingBytes = NumBytes;
- InstancePtr->ReceiveBuffer.NextBytePtr = BufferPtr;
-
- /* Receive the data from the device */
- ReceivedCount = XUartPs_ReceiveBuffer(InstancePtr);
-
- /* Restore the interrupt state */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
- ImrRegister);
-
- return ReceivedCount;
-}
-
-/****************************************************************************/
-/*
-*
-* This function sends a buffer that has been previously specified by setting
-* up the instance variables of the instance. This function is an internal
-* function for the XUartPs driver such that it may be called from a shell
-* function that sets up the buffer or from an interrupt handler.
-*
-* This function sends the specified buffer in either polled or interrupt
-* driven modes. This function is non-blocking.
-*
-* In a polled mode, this function only sends as much data as the TX FIFO
-* can buffer. The application may need to call it repeatedly to send the
-* entire buffer.
-*
-* In interrupt mode, this function starts the sending of the buffer, if not
-* the entire buffer has been sent, then the interrupt handler continues the
-* sending until the entire buffer has been sent. A callback function, as
-* specified by the application, will be called to indicate the completion of
-* sending.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-*
-* @return The number of bytes actually sent
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XUartPs_SendBuffer(XUartPs *InstancePtr)
-{
- u32 SentCount = 0U;
- u32 ImrRegister;
-
- /*
- * If the TX FIFO is full, send nothing.
- * Otherwise put bytes into the TX FIFO unil it is full, or all of the
- * data has been put into the FIFO.
- */
- while ((!XUartPs_IsTransmitFull(InstancePtr->Config.BaseAddress)) &&
- (InstancePtr->SendBuffer.RemainingBytes > SentCount)) {
-
- /* Fill the FIFO from the buffer */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_FIFO_OFFSET,
- ((u32)InstancePtr->SendBuffer.
- NextBytePtr[SentCount]));
-
- /* Increment the send count. */
- SentCount++;
- }
-
- /* Update the buffer to reflect the bytes that were sent from it */
- InstancePtr->SendBuffer.NextBytePtr += SentCount;
- InstancePtr->SendBuffer.RemainingBytes -= SentCount;
-
- /*
- * If interrupts are enabled as indicated by the receive interrupt, then
- * enable the TX FIFO empty interrupt, so further action can be taken
- * for this sending.
- */
- ImrRegister =
- XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IMR_OFFSET);
- if (((ImrRegister & XUARTPS_IXR_RXFULL) != (u32)0) ||
- ((ImrRegister & XUARTPS_IXR_RXEMPTY) != (u32)0)||
- ((ImrRegister & XUARTPS_IXR_RXOVR) != (u32)0)) {
-
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_IER_OFFSET,
- ImrRegister | (u32)XUARTPS_IXR_TXEMPTY);
- }
-
- return SentCount;
-}
-
-/****************************************************************************/
-/*
-*
-* This function receives a buffer that has been previously specified by setting
-* up the instance variables of the instance. This function is an internal
-* function, and it may be called from a shell function that sets up the buffer
-* or from an interrupt handler.
-*
-* This function attempts to receive a specified number of bytes from the
-* device and store it into the specified buffer. This function works for
-* either polled or interrupt driven modes. It is non-blocking.
-*
-* In polled mode, this function only receives as much data as in the RX FIFO.
-* The application may need to call it repeatedly to receive the entire buffer.
-* Polled mode is the default mode for the driver.
-*
-* In interrupt mode, this function starts the receiving, if not the entire
-* buffer has been received, the interrupt handler will continue until the
-* entire buffer has been received. A callback function, as specified by the
-* application, will be called to indicate the completion of the receiving or
-* error conditions.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-*
-* @return The number of bytes received.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr)
-{
- u32 CsrRegister;
- u32 ReceivedCount = 0U;
- u32 ByteStatusValue, EventData;
- u32 Event;
-
- /*
- * Read the Channel Status Register to determine if there is any data in
- * the RX FIFO
- */
- CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_SR_OFFSET);
-
- /*
- * Loop until there is no more data in RX FIFO or the specified
- * number of bytes has been received
- */
- while((ReceivedCount < InstancePtr->ReceiveBuffer.RemainingBytes)&&
- (((CsrRegister & XUARTPS_SR_RXEMPTY) == (u32)0))){
-
- if (InstancePtr->is_rxbs_error) {
- ByteStatusValue = XUartPs_ReadReg(
- InstancePtr->Config.BaseAddress,
- XUARTPS_RXBS_OFFSET);
- if((ByteStatusValue & XUARTPS_RXBS_MASK)!= (u32)0) {
- EventData = ByteStatusValue;
- Event = XUARTPS_EVENT_PARE_FRAME_BRKE;
- /*
- * Call the application handler to indicate that there is a receive
- * error or a break interrupt, if the application cares about the
- * error it call a function to get the last errors.
- */
- InstancePtr->Handler(InstancePtr->CallBackRef,
- Event, EventData);
- }
- }
-
- InstancePtr->ReceiveBuffer.NextBytePtr[ReceivedCount] =
- XUartPs_ReadReg(InstancePtr->Config.
- BaseAddress,
- XUARTPS_FIFO_OFFSET);
-
- ReceivedCount++;
-
- CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
- XUARTPS_SR_OFFSET);
- }
- InstancePtr->is_rxbs_error = 0;
- /*
- * Update the receive buffer to reflect the number of bytes just
- * received
- */
- if(InstancePtr->ReceiveBuffer.NextBytePtr != NULL){
- InstancePtr->ReceiveBuffer.NextBytePtr += ReceivedCount;
- }
- InstancePtr->ReceiveBuffer.RemainingBytes -= ReceivedCount;
-
- return ReceivedCount;
-}
-
-/*****************************************************************************/
-/**
-*
-* Sets the baud rate for the device. Checks the input value for
-* validity and also verifies that the requested rate can be configured to
-* within the maximum error range specified by XUARTPS_MAX_BAUD_ERROR_RATE.
-* If the provided rate is not possible, the current setting is unchanged.
-*
-* @param InstancePtr is a pointer to the XUartPs instance
-* @param BaudRate to be set
-*
-* @return
-* - XST_SUCCESS if everything configured as expected
-* - XST_UART_BAUD_ERROR if the requested rate is not available
-* because there was too much error
-*
-* @note None.
-*
-*****************************************************************************/
-s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate)
-{
- u32 IterBAUDDIV; /* Iterator for available baud divisor values */
- u32 BRGR_Value; /* Calculated value for baud rate generator */
- u32 CalcBaudRate; /* Calculated baud rate */
- u32 BaudError; /* Diff between calculated and requested baud rate */
- u32 Best_BRGR = 0U; /* Best value for baud rate generator */
- u8 Best_BAUDDIV = 0U; /* Best value for baud divisor */
- u32 Best_Error = 0xFFFFFFFFU;
- u32 PercentError;
- u32 ModeReg;
- u32 InputClk;
-
- /* Asserts validate the input arguments */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(BaudRate <= (u32)XUARTPS_MAX_RATE);
- Xil_AssertNonvoid(BaudRate >= (u32)XUARTPS_MIN_RATE);
-
- /*
- * Make sure the baud rate is not impossilby large.
- * Fastest possible baud rate is Input Clock / 2.
- */
- if ((BaudRate * 2) > InstancePtr->Config.InputClockHz) {
- return XST_UART_BAUD_ERROR;
- }
- /* Check whether the input clock is divided by 8 */
- ModeReg = XUartPs_ReadReg( InstancePtr->Config.BaseAddress,
- XUARTPS_MR_OFFSET);
-
- InputClk = InstancePtr->Config.InputClockHz;
- if(ModeReg & XUARTPS_MR_CLKSEL) {
- InputClk = InstancePtr->Config.InputClockHz / 8;
- }
-
- /*
- * Determine the Baud divider. It can be 4to 254.
- * Loop through all possible combinations
- */
- for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++) {
-
- /* Calculate the value for BRGR register */
- BRGR_Value = InputClk / (BaudRate * (IterBAUDDIV + 1));
-
- /* Calculate the baud rate from the BRGR value */
- CalcBaudRate = InputClk/ (BRGR_Value * (IterBAUDDIV + 1));
-
- /* Avoid unsigned integer underflow */
- if (BaudRate > CalcBaudRate) {
- BaudError = BaudRate - CalcBaudRate;
- }
- else {
- BaudError = CalcBaudRate - BaudRate;
- }
-
- /* Find the calculated baud rate closest to requested baud rate. */
- if (Best_Error > BaudError) {
-
- Best_BRGR = BRGR_Value;
- Best_BAUDDIV = IterBAUDDIV;
- Best_Error = BaudError;
- }
- }
-
- /* Make sure the best error is not too large. */
- PercentError = (Best_Error * 100) / BaudRate;
- if (XUARTPS_MAX_BAUD_ERROR_RATE < PercentError) {
- return XST_UART_BAUD_ERROR;
- }
-
- /* Disable TX and RX to avoid glitches when setting the baud rate. */
- XUartPs_DisableUart(InstancePtr);
-
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_BAUDGEN_OFFSET, Best_BRGR);
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
- XUARTPS_BAUDDIV_OFFSET, Best_BAUDDIV);
-
- /* RX and TX SW reset */
- XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
- XUARTPS_CR_TXRST | XUARTPS_CR_RXRST);
-
- /* Enable device */
- XUartPs_EnableUart(InstancePtr);
-
- InstancePtr->BaudRate = BaudRate;
-
- return XST_SUCCESS;
-
-}
-
-/****************************************************************************/
-/**
-*
-* This function is a stub handler that is the default handler such that if the
-* application has not set the handler when interrupts are enabled, this
-* function will be called.
-*
-* @param CallBackRef is unused by this function.
-* @param Event is unused by this function.
-* @param ByteCount is unused by this function.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
- u32 ByteCount)
-{
- (void) CallBackRef;
- (void) Event;
- (void) ByteCount;
- /* Assert occurs always since this is a stub and should never be called */
- Xil_AssertVoidAlways();
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f0/80fd67595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f0/80fd67595243001d18b399c1eb9b3628
deleted file mode 100644
index 6a5b232..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f0/80fd67595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,46 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2008 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-* microblaze_invalidate_cache_ext()
-*
-*Invalidate the entire L2 Cache
-*
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-#include "microblaze_instructions.h"
-
-#define XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN 16
-#define CACHEABLE_REGION_SIZE (XPAR_MICROBLAZE_DCACHE_HIGHADDR - XPAR_MICROBLAZE_DCACHE_BASEADDR)
-
- .text
- .globl microblaze_invalidate_cache_ext
- .ent microblaze_invalidate_cache_ext
- .align 2
-
-microblaze_invalidate_cache_ext:
-
-#if ((XPAR_MICROBLAZE_INTERCONNECT==3) && (XPAR_MICROBLAZE_USE_DCACHE==1))
- ADDIK r5, r0, XPAR_MICROBLAZE_DCACHE_BASEADDR & (-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN))
-
- ADDIK r6, r0, CACHEABLE_REGION_SIZE-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
- ANDI r6, r6, -(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
-
-Loop_start:
- wdc.ext.clear r5, r6
-#if defined (__arch64__ )
- addlik r6, r6,-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
- beagei r6, Loop_start
-#else
- bgtid r6,Loop_start
- addik r6, r6,-(4 * XPAR_MICROBLAZE_EXT_CACHE_LINE_LEN)
-#endif
-#endif
- rtsd r15, 8
- nop
-
- .end microblaze_invalidate_cache_ext
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f0/a0ea1b575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f0/a0ea1b575243001d18b399c1eb9b3628
deleted file mode 100644
index f06656a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f0/a0ea1b575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,96 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
- *
- * @file xusbps_hw.c
-* @addtogroup usbps_v2_7
-* @{
- *
- * The implementation of the XUsbPs interface reset functionality
- *
- *
- * MODIFICATION HISTORY:
- *
- * Ver Who Date Changes
- * ----- ---- -------- -----------------------------------------------
- * 1.05a kpc 10/10/10 first version
- *
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a drg 01/19/10 First release
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-* 3.10 mus 07/17/18 Updated file to fix the various coding style issues
-* reported by checkpatch. It fixes CR#1006344.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xscugic.h"
-
-/************************** Constant Definitions *****************************/
-
-#define XSCUGIC_PCELL_ID 0xB105F00DU
-
-/**************************** Type Definitions *******************************/
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-*
-* Run a self-test on the driver/device. This test reads the ID registers and
-* compares them.
-*
-* @param InstancePtr is a pointer to the XScuGic instance.
-*
-* @return
-*
-* -XST_SUCCESS if self-test is successful.
-* -XST_FAILURE if the self-test is not successful.
-*
-* @note None.
-*
-******************************************************************************/
-s32 XScuGic_SelfTest(XScuGic *InstancePtr)
-{
- u32 RegValue1 = 0U;
- u32 Index;
- s32 Status;
-
- /*
- * Assert the arguments
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Read the ID registers.
- */
- for (Index = 0U; Index <= 3U; Index++) {
- RegValue1 |= XScuGic_DistReadReg(InstancePtr,
- ((u32)XSCUGIC_PCELLID_OFFSET + (Index * 4U))) <<
- (Index * 8U);
- }
-
- if (XSCUGIC_PCELL_ID != RegValue1) {
- Status = XST_FAILURE;
- } else {
- Status = XST_SUCCESS;
- }
- return Status;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f2/2035b5525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f2/2035b5525243001d18b399c1eb9b3628
deleted file mode 100644
index a146f83..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f2/2035b5525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,387 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_exception.h
-*
-* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
-* For exception related functions that can be used across all Xilinx supported
-* processors, please use xil_exception.h.
-*
-* @addtogroup arm_exception_apis ARM Processor Exception Handling
-* @{
-* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
-* utilized for enabling/disabling IRQ, registering/removing handler for
-* exceptions or initializing exception vector table with null handler.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
-* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler.
-* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.
-* 7.0 mus 01/03/19 Tweak Xil_ExceptionEnableMask and
-* Xil_ExceptionDisableMask macros to support legacy
-* examples for Cortexa72 EL3 exception level.
-* 7.3 mus 04/15/20 Added Xil_EnableNestedInterrupts and
-* Xil_DisableNestedInterrupts macros for ARMv8.
-* For Cortexa72, these macro's would not be supported
-* at EL3, as Cortexa72 is using GIC-500(GICv3), which
-* triggeres only FIQ at EL3. Fix for CR#1062506
-# 7.6 mus 09/17/21 Updated flag checking to fix warning reported with
-# -Wundef compiler option CR#1110261
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
-#define XIL_EXCEPTION_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#include "bspconfig.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions ****************************/
-
-#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
-#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
-#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
-
-#define XIL_EXCEPTION_ID_FIRST 0U
-#if defined (__aarch64__)
-#define XIL_EXCEPTION_ID_SYNC_INT 1U
-#define XIL_EXCEPTION_ID_IRQ_INT 2U
-#define XIL_EXCEPTION_ID_FIQ_INT 3U
-#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
-#define XIL_EXCEPTION_ID_LAST 5U
-#else
-#define XIL_EXCEPTION_ID_RESET 0U
-#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
-#define XIL_EXCEPTION_ID_SWI_INT 2U
-#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
-#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
-#define XIL_EXCEPTION_ID_IRQ_INT 5U
-#define XIL_EXCEPTION_ID_FIQ_INT 6U
-#define XIL_EXCEPTION_ID_LAST 6U
-#endif
-
-/*
- * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
- */
-#if defined (versal) && !defined(ARMR5) && EL3
-#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_FIQ_INT
-#else
-#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
-#endif
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef is the exception handler function.
- */
-typedef void (*Xil_ExceptionHandler)(void *data);
-typedef void (*Xil_InterruptHandler)(void *data);
-
-/**
-*@endcond
-*/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* @brief Enable Exceptions.
-*
-* @param Mask: Value for enabling the exceptions.
-*
-* @return None.
-*
-* @note If bit is 0, exception is enabled.
-* C-Style signature: void Xil_ExceptionEnableMask(Mask)
-*
-******************************************************************************/
-#if defined (versal) && !defined(ARMR5) && EL3
-/*
- * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
- * only FIQ at EL3. Hence, tweaking this macro to always enable FIQ
- * ignoring argument passed by user.
- */
-#define Xil_ExceptionEnableMask(Mask) \
- mtcpsr(mfcpsr() & ~ ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
-#elif defined (__GNUC__) || defined (__ICCARM__)
-#define Xil_ExceptionEnableMask(Mask) \
- mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
-#else
-#define Xil_ExceptionEnableMask(Mask) \
- { \
- register u32 Reg __asm("cpsr"); \
- mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
- }
-#endif
-/****************************************************************************/
-/**
-* @brief Enable the IRQ exception.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-#if defined (versal) && !defined(ARMR5) && EL3
-#define Xil_ExceptionEnable() \
- Xil_ExceptionEnableMask(XIL_EXCEPTION_FIQ)
-#else
-#define Xil_ExceptionEnable() \
- Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
-#endif
-
-/****************************************************************************/
-/**
-* @brief Disable Exceptions.
-*
-* @param Mask: Value for disabling the exceptions.
-*
-* @return None.
-*
-* @note If bit is 1, exception is disabled.
-* C-Style signature: Xil_ExceptionDisableMask(Mask)
-*
-******************************************************************************/
-#if defined (versal) && !defined(ARMR5) && EL3
-/*
- * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
- * only FIQ at EL3. Hence, tweaking this macro to always disable FIQ
- * ignoring argument passed by user.
- */
-#define Xil_ExceptionDisableMask(Mask) \
- mtcpsr(mfcpsr() | ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
-#elif defined (__GNUC__) || defined (__ICCARM__)
-#define Xil_ExceptionDisableMask(Mask) \
- mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
-#else
-#define Xil_ExceptionDisableMask(Mask) \
- { \
- register u32 Reg __asm("cpsr"); \
- mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
- }
-#endif
-/****************************************************************************/
-/**
-* Disable the IRQ exception.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_ExceptionDisable() \
- Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
-
-#if ( defined (PLATFORM_ZYNQMP) && defined (EL3) && (EL3==1) )
-/****************************************************************************/
-/**
-* @brief Enable nested interrupts by clearing the I bit in DAIF.This
-* macro is defined for Cortex-A53 64 bit mode BSP configured to run
-* at EL3.. However,it is not defined for Versal Cortex-A72 BSP
-* configured to run at EL3. Reason is, Cortex-A72 is coupled
-* with GIC-500(GICv3 specifications) and it triggers only FIQ at EL3.
-*
-* @return None.
-*
-* @note This macro is supposed to be used from interrupt handlers. In the
-* interrupt handler the interrupts are disabled by default (I bit
-* is set as 1). To allow nesting of interrupts, this macro should be
-* used. It clears the I bit. Once that bit is cleared and provided the
-* preemption of interrupt conditions are met in the GIC, nesting of
-* interrupts will start happening.
-* Caution: This macro must be used with caution. Before calling this
-* macro, the user must ensure that the source of the current IRQ
-* is appropriately cleared. Otherwise, as soon as we clear the I
-* bit, there can be an infinite loop of interrupts with an
-* eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
- __asm__ __volatile__ ("mrs X1, ELR_EL3"); \
- __asm__ __volatile__ ("mrs X2, SPSR_EL3"); \
- __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-/****************************************************************************/
-/**
-* @brief Disable the nested interrupts by setting the I bit in DAIF. This
-* macro is defined for Cortex-A53 64 bit mode BSP configured to run
-* at EL3.
-*
-* @return None.
-*
-* @note This macro is meant to be called in the interrupt service routines.
-* This macro cannot be used independently. It can only be used when
-* nesting of interrupts have been enabled by using the macro
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-* point. The user then must call this macro before exiting the interrupt
-* service routine. This macro puts the ARM back in IRQ mode and
-* hence sets back the I bit.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
- __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \
- __asm__ __volatile__ ("msr ELR_EL3, X1"); \
- __asm__ __volatile__ ("msr SPSR_EL3, X2"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-#elif (defined (EL1_NONSECURE) && (EL1_NONSECURE==1))
-/****************************************************************************/
-/**
-* @brief Enable nested interrupts by clearing the I bit in DAIF.This
-* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit
-* BSP configured to run at EL1 NON SECURE
-*
-* @return None.
-*
-* @note This macro is supposed to be used from interrupt handlers. In the
-* interrupt handler the interrupts are disabled by default (I bit
-* is set as 1). To allow nesting of interrupts, this macro should be
-* used. It clears the I bit. Once that bit is cleared and provided the
-* preemption of interrupt conditions are met in the GIC, nesting of
-* interrupts will start happening.
-* Caution: This macro must be used with caution. Before calling this
-* macro, the user must ensure that the source of the current IRQ
-* is appropriately cleared. Otherwise, as soon as we clear the I
-* bit, there can be an infinite loop of interrupts with an
-* eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
- __asm__ __volatile__ ("mrs X1, ELR_EL1"); \
- __asm__ __volatile__ ("mrs X2, SPSR_EL1"); \
- __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-/****************************************************************************/
-/**
-* @brief Disable the nested interrupts by setting the I bit in DAIF. This
-* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit
-* BSP configured to run at EL1 NON SECURE
-*
-* @return None.
-*
-* @note This macro is meant to be called in the interrupt service routines.
-* This macro cannot be used independently. It can only be used when
-* nesting of interrupts have been enabled by using the macro
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-* point. The user then must call this macro before exiting the interrupt
-* service routine. This macro puts the ARM back in IRQ mode and
-* hence sets back the I bit.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
- __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \
- __asm__ __volatile__ ("msr ELR_EL1, X1"); \
- __asm__ __volatile__ ("msr SPSR_EL1, X2"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-#elif (!defined (__aarch64__) && !defined (ARMA53_32))
-/****************************************************************************/
-/**
-* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This
-* API is defined for cortex-a9 and cortex-r5.
-*
-* @return None.
-*
-* @note This macro is supposed to be used from interrupt handlers. In the
-* interrupt handler the interrupts are disabled by default (I and F
-* are 1). To allow nesting of interrupts, this macro should be
-* used. It clears the I and F bits by changing the ARM mode to
-* system mode. Once these bits are cleared and provided the
-* preemption of interrupt conditions are met in the GIC, nesting of
-* interrupts will start happening.
-* Caution: This macro must be used with caution. Before calling this
-* macro, the user must ensure that the source of the current IRQ
-* is appropriately cleared. Otherwise, as soon as we clear the I and
-* F bits, there can be an infinite loop of interrupts with an
-* eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
- __asm__ __volatile__ ("stmfd sp!, {lr}"); \
- __asm__ __volatile__ ("mrs lr, spsr"); \
- __asm__ __volatile__ ("stmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
- __asm__ __volatile__ ("stmfd sp!, {lr}");
-/****************************************************************************/
-/**
-* @brief Disable the nested interrupts by setting the I and F bits. This API
-* is defined for cortex-a9 and cortex-r5.
-*
-* @return None.
-*
-* @note This macro is meant to be called in the interrupt service routines.
-* This macro cannot be used independently. It can only be used when
-* nesting of interrupts have been enabled by using the macro
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-* point. The user then must call this macro before exiting the interrupt
-* service routine. This macro puts the ARM back in IRQ/FIQ mode and
-* hence sets back the I and F bits.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr cpsr_c, #0x92"); \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr spsr_cxsf, lr"); \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
-
-#endif
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler Handler,
- void *Data);
-
-extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
-extern void Xil_GetExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler *Handler, void **Data);
-
-extern void Xil_ExceptionInit(void);
-#if defined (__aarch64__)
-void Xil_SyncAbortHandler(void *CallBackRef);
-void Xil_SErrorAbortHandler(void *CallBackRef);
-#else
-extern void Xil_DataAbortHandler(void *CallBackRef);
-extern void Xil_PrefetchAbortHandler(void *CallBackRef);
-extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
-#endif
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_EXCEPTION_H */
-/**
-* @} End of "addtogroup arm_exception_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f2/603528595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f2/603528595243001d18b399c1eb9b3628
deleted file mode 100644
index 0c4863d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f2/603528595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,473 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-* @file boot.S
-*
-* @addtogroup a9_boot_code Cortex A9 Processor Boot Code
-* @{
-*
boot.S
-* The boot code performs minimum configuration which is required for an
-* application to run starting from processor reset state of the processor. Below is a
-* sequence illustrating what all configuration is performed before control
-* reaches to main function.
-*
-* 1. Program vector table base for exception handling
-* 2. Invalidate instruction cache, data cache and TLBs
-* 3. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine,
-* abort, system)
-* 4. Configure MMU with short descriptor translation table format and program
-* base address of translation table
-* 5. Enable data cache, instruction cache and MMU
-* 6. Enable Floating point unit
-* 7. Transfer control to _start which clears BSS sections, initializes
-* global timer and runs global constructor before jumping to main
-* application
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 1.00a ecm/sdm 10/20/09 Initial version
-* 3.06a sgd 05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control
-* register settings.
-* 3.06a asa 06/17/12 Modified the TTBR settings and L2 Cache auxiliary
-* register settings.
-* 3.07a asa 07/16/12 Modified the L2 Cache controller settings to improve
-* performance. Changed the property of the ".boot"
-* section.
-* 3.07a sgd 08/21/12 Modified the L2 Cache controller and cp15 Aux Control
-* Register settings
-* 3.09a sgd 02/06/13 Updated SLCR l2c Ram Control register to a
-* value of 0x00020202. Fix for CR 697094 (SI#687034).
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-* 4.2 pkp 06/19/14 Enabled asynchronous abort exception
-* 5.0 pkp 16/15/14 Modified initialization code to enable scu after
-* MMU is enabled
-* 5.1 pkp 05/13/15 Changed the initialization order so to first invalidate
-* caches and TLB, enable MMU and caches, then enable SMP
-* bit in ACTLR. L2Cache invalidation and enabling of L2Cache
-* is done later.
-* 5.4 asa 12/6/15 Added code to initialize SPSR for all relevant modes.
-* 6.0 mus 08/04/16 Added code to detect zynq-7000 base silicon configuration and
-* attempt to enable dual core behavior on single cpu zynq-7000s
-* devices is prevented from corrupting system behavior.
-* 6.0 mus 08/24/16 Check CPU core before putting cpu1 to reset for single core
-* zynq-7000s devices
-* 7.6 mus 09/02/21 SCU invalidation should be done only from primary CPU, so
-* skipping it when USE_AMP is set to 1. It fixes CR#1109723
-*
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-#include "xparameters.h"
-#include "xil_errata.h"
-
-.globl MMUTable
-.global _prestart
-.global _boot
-.global __stack
-.global __irq_stack
-.global __supervisor_stack
-.global __abort_stack
-.global __fiq_stack
-.global __undef_stack
-.global _vector_table
-
-.set PSS_L2CC_BASE_ADDR, 0xF8F02000
-.set PSS_SLCR_BASE_ADDR, 0xF8000000
-
-.set RESERVED, 0x0fffff00
-.set TblBase , MMUTable
-.set LRemap, 0xFE00000F /* set the base address of the peripheral block as not shared */
-.set L2CCWay, (PSS_L2CC_BASE_ADDR + 0x077C) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)*/
-.set L2CCSync, (PSS_L2CC_BASE_ADDR + 0x0730) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)*/
-.set L2CCCrtl, (PSS_L2CC_BASE_ADDR + 0x0100) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)*/
-.set L2CCAuxCrtl, (PSS_L2CC_BASE_ADDR + 0x0104) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)*/
-.set L2CCTAGLatReg, (PSS_L2CC_BASE_ADDR + 0x0108) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)*/
-.set L2CCDataLatReg, (PSS_L2CC_BASE_ADDR + 0x010C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)*/
-.set L2CCIntClear, (PSS_L2CC_BASE_ADDR + 0x0220) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)*/
-.set L2CCIntRaw, (PSS_L2CC_BASE_ADDR + 0x021C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)*/
-
-.set SLCRlockReg, (PSS_SLCR_BASE_ADDR + 0x04) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/
-.set SLCRUnlockReg, (PSS_SLCR_BASE_ADDR + 0x08) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/
-.set SLCRL2cRamReg, (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/
-.set SLCRCPURSTReg, (0xF8000000 + 0x244) /*(XPS_SYS_CTRL_BASEADDR + A9_CPU_RST_CTRL_OFFSET)*/
-.set EFUSEStaus, (0xF800D000 + 0x10) /*(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)*/
-
-/* workaround for simulation not working when L1 D and I caches,MMU and L2 cache enabled - DT568997 */
-.if SIM_MODE == 1
-.set CRValMmuCac, 0b00000000000000 /* Disable IDC, and MMU */
-.else
-.set CRValMmuCac, 0b01000000000101 /* Enable IDC, and MMU */
-.endif
-
-.set CRValHiVectorAddr, 0b10000000000000 /* Set the Vector address to high, 0xFFFF0000 */
-
-.set L2CCAuxControl, 0x72360000 /* Enable all prefetching, Cache replacement policy, Parity enable,
- Event monitor bus enable and Way Size (64 KB) */
-.set L2CCControl, 0x01 /* Enable L2CC */
-.set L2CCTAGLatency, 0x0111 /* latency for TAG RAM */
-.set L2CCDataLatency, 0x0121 /* latency for DATA RAM */
-
-.set SLCRlockKey, 0x767B /* SLCR lock key */
-.set SLCRUnlockKey, 0xDF0D /* SLCR unlock key */
-.set SLCRL2cRamConfig, 0x00020202 /* SLCR L2C ram configuration */
-
-/* Stack Pointer locations for boot code */
-.set Undef_stack, __undef_stack
-.set FIQ_stack, __fiq_stack
-.set Abort_stack, __abort_stack
-.set SPV_stack, __supervisor_stack
-.set IRQ_stack, __irq_stack
-.set SYS_stack, __stack
-
-.set vector_base, _vector_table
-
-.set FPEXC_EN, 0x40000000 /* FPU enable bit, (1 << 30) */
-
-.section .boot,"ax"
-
-
-/* this initializes the various processor modes */
-
-_prestart:
-_boot:
-
-#if XPAR_CPU_ID==0
- /* only allow cpu0 through */
- mrc p15,0,r1,c0,c0,5
- and r1, r1, #0xf
- cmp r1, #0
- beq CheckEFUSE
- EndlessLoop0:
- wfe
- b EndlessLoop0
-
-CheckEFUSE:
- ldr r0,=EFUSEStaus
- ldr r1,[r0] /* Read eFuse setting */
- ands r1,r1,#0x80 /* Check whether device is having single core */
- beq OKToRun
-
- /* single core device, reset cpu1 */
- ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
- ldr r1,=SLCRUnlockKey /* set unlock key */
- str r1, [r0] /* Unlock SLCR */
-
- ldr r0,=SLCRCPURSTReg
- ldr r1,[r0] /* Read CPU Software Reset Control register */
- orr r1,r1,#0x22
- str r1,[r0] /* Reset CPU1 */
-
- ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
- ldr r1,=SLCRlockKey /* set lock key */
- str r1, [r0] /* lock SLCR */
-
-#elif XPAR_CPU_ID==1
- /* only allow cpu1 through */
- mrc p15,0,r1,c0,c0,5
- and r1, r1, #0xf
- cmp r1, #1
- beq CheckEFUSE1
- b EndlessLoop1
-
-CheckEFUSE1:
- ldr r0,=EFUSEStaus
- ldr r1,[r0] /* Read eFuse setting */
- ands r1,r1,#0x80 /* Check whether device is having single core */
- beq OKToRun
- EndlessLoop1:
- wfe
- b EndlessLoop1
-#endif
-
-OKToRun:
- mrc p15, 0, r0, c0, c0, 0 /* Get the revision */
- and r5, r0, #0x00f00000
- and r6, r0, #0x0000000f
- orr r6, r6, r5, lsr #20-4
-
-#ifdef CONFIG_ARM_ERRATA_742230
- cmp r6, #0x22 /* only present up to r2p2 */
- mrcle p15, 0, r10, c15, c0, 1 /* read diagnostic register */
- orrle r10, r10, #1 << 4 /* set bit #4 */
- mcrle p15, 0, r10, c15, c0, 1 /* write diagnostic register */
-#endif
-
-#ifdef CONFIG_ARM_ERRATA_743622
- teq r5, #0x00200000 /* only present in r2p* */
- mrceq p15, 0, r10, c15, c0, 1 /* read diagnostic register */
- orreq r10, r10, #1 << 6 /* set bit #6 */
- mcreq p15, 0, r10, c15, c0, 1 /* write diagnostic register */
-#endif
-
- /* set VBAR to the _vector_table address in linker script */
- ldr r0, =vector_base
- mcr p15, 0, r0, c12, c0, 0
-
- /*invalidate scu*/
-#if USE_AMP!=1
- ldr r7, =0xf8f0000c
- ldr r6, =0xffff
- str r6, [r7]
-#endif
-
- /* Invalidate caches and TLBs */
- mov r0,#0 /* r0 = 0 */
- mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
- mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
- mcr p15, 0, r0, c7, c5, 6 /* Invalidate branch predictor array */
- bl invalidate_dcache /* invalidate dcache */
-
- /* Disable MMU, if enabled */
- mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */
- bic r0, r0, #0x1 /* clear bit 0 */
- mcr p15, 0, r0, c1, c0, 0 /* write value back */
-
-#ifdef SHAREABLE_DDR
- /* Mark the entire DDR memory as shareable */
- ldr r3, =0x3ff /* 1024 entries to cover 1G DDR */
- ldr r0, =TblBase /* MMU Table address in memory */
- ldr r2, =0x15de6 /* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
-shareable_loop:
- str r2, [r0] /* write the entry to MMU table */
- add r0, r0, #0x4 /* next entry in the table */
- add r2, r2, #0x100000 /* next section */
- subs r3, r3, #1
- bge shareable_loop /* loop till 1G is covered */
-#endif
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the irq stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x12 /* IRQ mode */
- msr cpsr, r2
- ldr r13,=IRQ_stack /* IRQ stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the supervisor stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x13 /* supervisor mode */
- msr cpsr, r2
- ldr r13,=SPV_stack /* Supervisor stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the Abort stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x17 /* Abort mode */
- msr cpsr, r2
- ldr r13,=Abort_stack /* Abort stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the FIQ stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x11 /* FIQ mode */
- msr cpsr, r2
- ldr r13,=FIQ_stack /* FIQ stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the Undefine stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x1b /* Undefine mode */
- msr cpsr, r2
- ldr r13,=Undef_stack /* Undefine stack pointer */
- bic r2, r2, #(0x1 << 9) /* Set EE bit to little-endian */
- msr spsr_fsxc,r2
-
- mrs r0, cpsr /* get the current PSR */
- mvn r1, #0x1f /* set up the system stack pointer */
- and r2, r1, r0
- orr r2, r2, #0x1F /* SYS mode */
- msr cpsr, r2
- ldr r13,=SYS_stack /* SYS stack pointer */
-
- /*set scu enable bit in scu*/
- ldr r7, =0xf8f00000
- ldr r0, [r7]
- orr r0, r0, #0x1
- str r0, [r7]
-
- /* enable MMU and cache */
-
- ldr r0,=TblBase /* Load MMU translation table base */
- orr r0, r0, #0x5B /* Outer-cacheable, WB */
- mcr 15, 0, r0, c2, c0, 0 /* TTB0 */
-
- mvn r0,#0 /* Load MMU domains -- all ones=manager */
- mcr p15,0,r0,c3,c0,0
-
- /* Enable mmu, icahce and dcache */
- ldr r0,=CRValMmuCac
- mcr p15,0,r0,c1,c0,0 /* Enable cache and MMU */
- dsb /* dsb allow the MMU to start up */
- isb /* isb flush prefetch buffer */
-
- /* Write to ACTLR */
- mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/
- orr r0, r0, #(0x01 << 6) /* set SMP bit */
- orr r0, r0, #(0x01 ) /* Cache/TLB maintenance broadcast */
- mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/
-
-/* Invalidate L2 Cache and enable L2 Cache*/
-/* For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) */
-#if USE_AMP!=1
- ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */
- mov r1, #0 /* force the disable bit */
- str r1, [r0] /* disable the L2 Caches */
-
- ldr r0,=L2CCAuxCrtl /* Load L2CC base address base + Aux control register */
- ldr r1,[r0] /* read the register */
- ldr r2,=L2CCAuxControl /* set the default bits */
- orr r1,r1,r2
- str r1, [r0] /* store the Aux Control Register */
-
- ldr r0,=L2CCTAGLatReg /* Load L2CC base address base + TAG Latency address */
- ldr r1,=L2CCTAGLatency /* set the latencies for the TAG*/
- str r1, [r0] /* store the TAG Latency register Register */
-
- ldr r0,=L2CCDataLatReg /* Load L2CC base address base + Data Latency address */
- ldr r1,=L2CCDataLatency /* set the latencies for the Data*/
- str r1, [r0] /* store the Data Latency register Register */
-
- ldr r0,=L2CCWay /* Load L2CC base address base + way register*/
- ldr r2, =0xFFFF
- str r2, [r0] /* force invalidate */
-
- ldr r0,=L2CCSync /* need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET */
- /* Load L2CC base address base + sync register*/
- /* poll for completion */
-Sync: ldr r1, [r0]
- cmp r1, #0
- bne Sync
-
- ldr r0,=L2CCIntRaw /* clear pending interrupts */
- ldr r1,[r0]
- ldr r0,=L2CCIntClear
- str r1,[r0]
-
- ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */
- ldr r1,=SLCRUnlockKey /* set unlock key */
- str r1, [r0] /* Unlock SLCR */
-
- ldr r0,=SLCRL2cRamReg /* Load SLCR base address base + l2c Ram Control register */
- ldr r1,=SLCRL2cRamConfig /* set the configuration value */
- str r1, [r0] /* store the L2c Ram Control Register */
-
- ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */
- ldr r1,=SLCRlockKey /* set lock key */
- str r1, [r0] /* lock SLCR */
-
- ldr r0,=L2CCCrtl /* Load L2CC base address base + control register */
- ldr r1,[r0] /* read the register */
- mov r2, #L2CCControl /* set the enable bit */
- orr r1,r1,r2
- str r1, [r0] /* enable the L2 Caches */
-#endif
-
- mov r0, r0
- mrc p15, 0, r1, c1, c0, 2 /* read cp access control register (CACR) into r1 */
- orr r1, r1, #(0xf << 20) /* enable full access for p10 & p11 */
- mcr p15, 0, r1, c1, c0, 2 /* write back into CACR */
-
- /* enable vfp */
- fmrx r1, FPEXC /* read the exception register */
- orr r1,r1, #FPEXC_EN /* set VFP enable bit, leave the others in orig state */
- fmxr FPEXC, r1 /* write back the exception register */
-
- mrc p15,0,r0,c1,c0,0 /* flow prediction enable */
- orr r0, r0, #(0x01 << 11) /* #0x8000 */
- mcr p15,0,r0,c1,c0,0
-
- mrc p15,0,r0,c1,c0,1 /* read Auxiliary Control Register */
- orr r0, r0, #(0x1 << 2) /* enable Dside prefetch */
- orr r0, r0, #(0x1 << 1) /* enable L2 Prefetch hint */
- mcr p15,0,r0,c1,c0,1 /* write Auxiliary Control Register */
-
- mrs r0, cpsr /* get the current PSR */
- bic r0, r0, #0x100 /* enable asynchronous abort exception */
- msr cpsr_xsf, r0
-
-
- b _start /* jump to C startup code */
- and r0, r0, r0 /* no op */
-
-.Ldone: b .Ldone /* Paranoia: we should never get here */
-
-
-/*
- *************************************************************************
- *
- * invalidate_dcache - invalidate the entire d-cache by set/way
- *
- * Note: for Cortex-A9, there is no cp instruction for invalidating
- * the whole D-cache. Need to invalidate each line.
- *
- *************************************************************************
- */
-invalidate_dcache:
- mrc p15, 1, r0, c0, c0, 1 /* read CLIDR */
- ands r3, r0, #0x7000000
- mov r3, r3, lsr #23 /* cache level value (naturally aligned) */
- beq finished
- mov r10, #0 /* start with level 0 */
-loop1:
- add r2, r10, r10, lsr #1 /* work out 3xcachelevel */
- mov r1, r0, lsr r2 /* bottom 3 bits are the Cache type for this level */
- and r1, r1, #7 /* get those 3 bits alone */
- cmp r1, #2
- blt skip /* no cache or only instruction cache at this level */
- mcr p15, 2, r10, c0, c0, 0 /* write the Cache Size selection register */
- isb /* isb to sync the change to the CacheSizeID reg */
- mrc p15, 1, r1, c0, c0, 0 /* reads current Cache Size ID register */
- and r2, r1, #7 /* extract the line length field */
- add r2, r2, #4 /* add 4 for the line length offset (log2 16 bytes) */
- ldr r4, =0x3ff
- ands r4, r4, r1, lsr #3 /* r4 is the max number on the way size (right aligned) */
- clz r5, r4 /* r5 is the bit position of the way size increment */
- ldr r7, =0x7fff
- ands r7, r7, r1, lsr #13 /* r7 is the max number of the index size (right aligned) */
-loop2:
- mov r9, r4 /* r9 working copy of the max way size (right aligned) */
-loop3:
- orr r11, r10, r9, lsl r5 /* factor in the way number and cache number into r11 */
- orr r11, r11, r7, lsl r2 /* factor in the index number */
- mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */
- subs r9, r9, #1 /* decrement the way number */
- bge loop3
- subs r7, r7, #1 /* decrement the index */
- bge loop2
-skip:
- add r10, r10, #2 /* increment the cache number */
- cmp r3, r10
- bgt loop1
-
-finished:
- mov r10, #0 /* switch back to cache level 0 */
- mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
- dsb
- isb
-
- bx lr
-
-.end
-/**
-* @} End of "addtogroup a9_boot_code".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f2/709c71525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f2/709c71525243001d18b399c1eb9b3628
deleted file mode 100644
index bc4f6dd..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f2/709c71525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,7 +0,0 @@
-/*phased_array_platform*/
-the_ROM_image:
-{
- [bootloader]
-
-
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f2/805bac525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f2/805bac525243001d18b399c1eb9b3628
deleted file mode 100644
index e8b87b5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f2/805bac525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,176 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_assert.h
-*
-* @addtogroup common_assert_apis Assert APIs and Macros
-*
-* The xil_assert.h file contains assert related functions and macros.
-* Assert APIs/Macros specifies that a application program satisfies certain
-* conditions at particular points in its execution. These function can be
-* used by application programs to ensure that, application code is satisfying
-* certain conditions.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 First release
-* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_ASSERT_H /* prevent circular inclusions */
-#define XIL_ASSERT_H /* by using protection macros */
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/***************************** Include Files *********************************/
-
-
-/************************** Constant Definitions *****************************/
-
-#define XIL_ASSERT_NONE 0U
-#define XIL_ASSERT_OCCURRED 1U
-#define XNULL NULL
-
-extern u32 Xil_AssertStatus;
-extern s32 Xil_AssertWait;
-extern void Xil_Assert(const char8 *File, s32 Line);
-/**
- *@endcond
- */
-void XNullHandler(void *NullParameter);
-
-/**
- * This data type defines a callback to be invoked when an
- * assert occurs. The callback is invoked only when asserts are enabled
- */
-typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#ifndef NDEBUG
-
-/*****************************************************************************/
-/**
-* @brief This assert macro is to be used for void functions. This in
-* conjunction with the Xil_AssertWait boolean can be used to
-* accommodate tests so that asserts which fail allow execution to
-* continue.
-*
-* @param Expression: expression to be evaluated. If it evaluates to
-* false, the assert occurs.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertVoid(Expression) \
-{ \
- if (Expression) { \
- Xil_AssertStatus = XIL_ASSERT_NONE; \
- } else { \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* @brief This assert macro is to be used for functions that do return a
-* value. This in conjunction with the Xil_AssertWait boolean can be
-* used to accommodate tests so that asserts which fail allow execution
-* to continue.
-*
-* @param Expression: expression to be evaluated. If it evaluates to false,
-* the assert occurs.
-*
-* @return Returns 0 unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertNonvoid(Expression) \
-{ \
- if (Expression) { \
- Xil_AssertStatus = XIL_ASSERT_NONE; \
- } else { \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return 0; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* @brief Always assert. This assert macro is to be used for void functions.
-* Use for instances where an assert should always occur.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertVoidAlways() \
-{ \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return; \
-}
-
-/*****************************************************************************/
-/**
-* @brief Always assert. This assert macro is to be used for functions that
-* do return a value. Use for instances where an assert should always
-* occur.
-*
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-* case no return is made and an infinite loop is entered.
-*
-******************************************************************************/
-#define Xil_AssertNonvoidAlways() \
-{ \
- Xil_Assert(__FILE__, __LINE__); \
- Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
- return 0; \
-}
-
-
-#else
-
-#define Xil_AssertVoid(Expression)
-#define Xil_AssertVoidAlways()
-#define Xil_AssertNonvoid(Expression)
-#define Xil_AssertNonvoidAlways()
-
-#endif
-
-/************************** Function Prototypes ******************************/
-
-void Xil_AssertSetCallback(Xil_AssertCallback Routine);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_assert_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f2/80c353575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f2/80c353575243001d18b399c1eb9b3628
deleted file mode 100644
index c2e112b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f2/80c353575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,165 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file sd.c
-*
-* Contains code for the SD card FLASH functionality.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a jz 04/28/11 Initial release
-* 7.00a kc 10/18/13 Integrated SD/MMC driver
-* 12.00a ssc 12/11/14 Fix for CR# 839182
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.2 pkp 02/16/17 First release
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xil_types.h"
-#include "xil_smc.h"
-
-#if EL1_NONSECURE
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Function Prototypes *****************************/
-
-/************************** Variable Definitions *****************************/
-XSmc_OutVar SmcResult;
-
-/*****************************************************************************/
-/**
-* @brief Initiate SMC call to EL3 secure monitor to request for secure
-* service. This function is only applicable for EL1 Non-secure bsp.
-*
-* @param FunctionID is the SMC identifier for a particular secure service
-* request
-* @param Arg1 to Arg6 is the arguments passed to EL3 secure monitor
-* @param Arg7 is Hypervisor Client ID register
-*
-* @return Result from secure payload service
-* @note FunctionID and Arg1-Arg7 should be as per SMC calling convention
-*
-******************************************************************************/
-XSmc_OutVar Xil_Smc(u64 FunctionID, u64 Arg1, u64 Arg2, u64 Arg3, u64 Arg4,
- u64 Arg5, u64 Arg6, u64 Arg7){
-
- /*
- * Since registers x8 to x17 are not saved by secure monitor during SMC
- * it must be preserved.
- */
- XSave_X8toX17();
-
- /* Moving to EL3 secure monitor with smc call. */
-
- __asm__ __volatile__ ("smc #0x0");
-
- /*
- * The result of the secure services are stored in x0 - x3. They are
- * moved to SmcResult to return the result.
- */
- __asm__ __volatile__("mov x8, x0");
- __asm__ __volatile__("mov x9, x1");
- __asm__ __volatile__("mov x10, x2");
- __asm__ __volatile__("mov x11, x3");
-
- __asm__ __volatile__("mov %0, x8" : "=r" (SmcResult.Arg0));
- __asm__ __volatile__("mov %0, x9" : "=r" (SmcResult.Arg1));
- __asm__ __volatile__("mov %0, x10" : "=r" (SmcResult.Arg2));
- __asm__ __volatile__("mov %0, x11" : "=r" (SmcResult.Arg3));
-
- XRestore_X8toX17();
-
- return SmcResult;
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f2/e0940e525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f2/e0940e525243001d18b399c1eb9b3628
deleted file mode 100644
index a9552de..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f2/e0940e525243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,306 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-/*
- * helloworld.c: simple test application
- *
- * This application configures UART 16550 to baud rate 9600.
- * PS7 UART (Zynq) is not initialized by this application, since
- * bootrom/bsp configures it to baud rate 115200
- *
- * ------------------------------------------------
- * | UART TYPE BAUD RATE |
- * ------------------------------------------------
- * uartns550 9600
- * uartlite Configurable only in HW design
- * ps7_uart 115200 (configured by bootrom/bsp)
- */
-
-#include
-#include "platform.h"
-#include "xil_printf.h"
-#include "xparameters.h"
-#include
-#include "xgpio.h"
-#include
-#include "animation.h"
-
-// math constants
-#define PI 3.1415926 //PI
-
-// parameters defined if fpga fabric
-#define FREQ 40000 //carrier frequency for the transducers
-#define RESOLUTION 128 //resolution in mm in which the phases can be adjusted.
-
-// array pcb parameters
-#define WIDTH 5 //number of transducers in the x direction
-#define HEIGTH 5 //number of transducers in the y direction
-#define DISTANCE 10.0 //distance between the transducers
-
-// environment parameters
-#define TEMPERATURE 20.0 //ambient temperature used to calculate wavelength
-
-// accoustic lefitation example
-#define MOVEMENT_RES 10 //movement resolution in steps/mm
-#define ARRAY_DISTANCE 70 //distance between the top and bottom array
-
-// calculate wavelength in air based on temperature and frequency
-double wavelength = (331000*sqrt(1 + TEMPERATURE/273.0))/FREQ; //in mm
-
-// gpio's for the columns
-XGpio gpio[2][WIDTH];
-
-// other peripherals
-XGpio gpio_0;
-XGpio gpio_1;
-
-int phases[2][WIDTH][HEIGTH] = {0};
-
-/*
- * these values are measured in real life and
- * correspond to the phase delay offsets from
- * the individual transmitters.
- * formula: (delay_us/25us) * 128
- */
-int offsets[2][WIDTH][HEIGTH] = {
- {{128-28, 128-105, 128-44, 128-108, 128-36},
- {128-44, 128-105, 128-46, 128-38, 128-100},
- {128-38, 128-38, 128-38, 128-41, 128-110},
- {128-44, 128-113, 128-113, 128-97, 128-38},
- {128-30, 128-51, 128-38, 128-49, 128-110}},//*/
-
- {{128-113, 128-41, 128-92, 128-23, 128-105},
- {128-46, 128-97, 128-110, 128-110, 128-41},
- {128-113, 128-92, 128-46, 128-113, 128-36},
- {128-102, 128-33, 128-110, 128-113, 128-97},
- {128-41, 128-108, 128-44, 128-51, 128-100}}//*/
-};
-
-// rows for the delay generators (FPGA fabric)
-int devIds[2][WIDTH] = {
- {XPAR_HIER_0_AXI_GPIO_0_DEVICE_ID,
- XPAR_HIER_1_AXI_GPIO_0_DEVICE_ID,
- XPAR_HIER_2_AXI_GPIO_0_DEVICE_ID,
- XPAR_HIER_3_AXI_GPIO_0_DEVICE_ID,
- XPAR_HIER_4_AXI_GPIO_0_DEVICE_ID},
- {XPAR_HIER_5_AXI_GPIO_0_DEVICE_ID,
- XPAR_HIER_6_AXI_GPIO_0_DEVICE_ID,
- XPAR_HIER_7_AXI_GPIO_0_DEVICE_ID,
- XPAR_HIER_8_AXI_GPIO_0_DEVICE_ID,
- XPAR_HIER_9_AXI_GPIO_0_DEVICE_ID}
-};
-
-// store previous location
-double current_x = 0;
-double current_y = 0;
-double current_z = 0;
-
-// initialize the gpio's
-void driverInit() {
- int status;
- for (int i=0; i> 0;
- int bt2 = (bt & 0b0010) >> 1;
- int bt3 = (bt & 0b0100) >> 2;
- int bt4 = (bt & 0b1000) >> 3;
-
- setPosition(0, 0, 0);
-
- // wait until button press
- XGpio_DiscreteWrite(&gpio_0, 1, 1);
- while (!XGpio_DiscreteRead(&gpio_1, 1)) {
- usleep(10000);
- }
- XGpio_DiscreteWrite(&gpio_0, 1, 0);
-
- for (int i=0; i<198; i++) {
- moveTo(knot_animation[i][0]*3, knot_animation[i][2]*3, knot_animation[i][1]*3, 30);
- }
- moveTo(0, 0, 0, 100);
- }
-
- print("Hello World\n\r");
- print("Successfully ran Hello World application");
- cleanup_platform();
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f3/100ff9585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f3/100ff9585243001d18b399c1eb9b3628
deleted file mode 100644
index 1befce1..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f3/100ff9585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,255 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpm_counter.c
-*
-* This file contains APIs for configuring and controlling the Cortex-A9
-* Performance Monitor Events. For more information about the event counters,
-* see xpm_counter.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 4.2 pkp 07/21/14 Corrected reset value of event counter in function
-* Xpm_ResetEventCounters to fix CR#796275
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00 sdm 11/25/10 First release
-* 2.01a sg 02/03/13 Delay Register test is added with DelayNss parameter.
-* 3.1 hk 06/19/14 Remove checks for CR and ISR register values as they are
-* reset in the previous step.
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xqspips.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-/*****************************************************************************/
-/**
-*
-* Runs a self-test on the driver/device. The self-test is destructive in that
-* a reset of the device is performed in order to check the reset values of
-* the registers and to get the device into a known state.
-*
-* Upon successful return from the self-test, the device is reset.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return
-* - XST_SUCCESS if successful
-* - XST_REGISTER_ERROR indicates a register did not read or write
-* correctly.
-*
-* @note None.
-*
-******************************************************************************/
-int XQspiPs_SelfTest(XQspiPs *InstancePtr)
-{
- int Status;
- u8 DelayTestNss;
- u8 DelayTestBtwn;
- u8 DelayTestAfter;
- u8 DelayTestInit;
-
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Reset the QSPI device to leave it in a known good state
- */
- XQspiPs_Reset(InstancePtr);
-
- DelayTestNss = 0x5A;
- DelayTestBtwn = 0xA5;
- DelayTestAfter = 0xAA;
- DelayTestInit = 0x55;
-
- /*
- * Write and read the delay register, just to be sure there is some
- * hardware out there.
- */
- Status = XQspiPs_SetDelays(InstancePtr, DelayTestNss, DelayTestBtwn,
- DelayTestAfter, DelayTestInit);
- if (Status != XST_SUCCESS) {
- return Status;
- }
-
- XQspiPs_GetDelays(InstancePtr, &DelayTestNss, &DelayTestBtwn,
- &DelayTestAfter, &DelayTestInit);
- if ((0x5A != DelayTestNss) || (0xA5 != DelayTestBtwn) ||
- (0xAA != DelayTestAfter) || (0x55 != DelayTestInit)) {
- return XST_REGISTER_ERROR;
- }
-
- Status = XQspiPs_SetDelays(InstancePtr, 0, 0, 0, 0);
- if (Status != XST_SUCCESS) {
- return Status;
- }
-
- /*
- * Reset the QSPI device to leave it in a known good state
- */
- XQspiPs_Reset(InstancePtr);
-
- return XST_SUCCESS;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f3/b325e9575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f3/b325e9575243001d18b399c1eb9b3628
deleted file mode 100644
index 8731605..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f3/b325e9575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,268 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xgpio_intr.c
-* @addtogroup gpio_v4_8
-* @{
-*
-* Implements GPIO interrupt processing functions for the XGpio driver.
-* See xgpio.h for more information about the driver.
-*
-* The functions in this file require the hardware device to be built with
-* interrupt capabilities. The functions will assert if called using hardware
-* that does not have interrupt capabilities.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 2.00a jhl 11/26/03 Initial release
-* 2.11a mta 03/21/07 Updated to new coding style
-* 2.12a sv 06/05/08 Updated driver to fix the XGpio_InterruptDisable function
-* to properly update the Interrupt Enable register
-* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the macros
-* XGpio_mWriteReg to XGpio_WriteReg, and XGpio_mReadReg
-* to XGpio_ReadReg.
-
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xgpio.h"
-
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-
-/****************************************************************************/
-/**
-* Enable the interrupt output signal. Interrupts enabled through
-* XGpio_InterruptEnable() will not be passed through until the global enable
-* bit is set by this function. This function is designed to allow all
-* interrupts (both channels) to be enabled easily for exiting a critical
-* section. This function will assert if the hardware device has not been
-* built with interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpio_InterruptGlobalEnable(XGpio *InstancePtr)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
-
- XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_GIE_OFFSET,
- XGPIO_GIE_GINTR_ENABLE_MASK);
-}
-
-
-/****************************************************************************/
-/**
-* Disable the interrupt output signal. Interrupts enabled through
-* XGpio_InterruptEnable() will no longer be passed through until the global
-* enable bit is set by XGpio_InterruptGlobalEnable(). This function is
-* designed to allow all interrupts (both channels) to be disabled easily for
-* entering a critical section. This function will assert if the hardware
-* device has not been built with interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpio_InterruptGlobalDisable(XGpio *InstancePtr)
-{
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
-
-
- XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_GIE_OFFSET, 0x0);
-
-}
-
-
-/****************************************************************************/
-/**
-* Enable interrupts. The global interrupt must also be enabled by calling
-* XGpio_InterruptGlobalEnable() for interrupts to occur. This function will
-* assert if the hardware device has not been built with interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-* @param Mask is the mask to enable. Bit positions of 1 are enabled.
-* This mask is formed by OR'ing bits from XGPIO_IR* bits which
-* are contained in xgpio_l.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
-
- /*
- * Read the interrupt enable register and only enable the specified
- * interrupts without disabling or enabling any others.
- */
-
- Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
- XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET,
- Register | Mask);
-
-}
-
-
-/****************************************************************************/
-/**
-* Disable interrupts. This function allows specific interrupts for each
-* channel to be disabled. This function will assert if the hardware device
-* has not been built with interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-* @param Mask is the mask to disable. Bits set to 1 are disabled. This
-* mask is formed by OR'ing bits from XGPIO_IR* bits which are
-* contained in xgpio_l.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
-
- /*
- * Read the interrupt enable register and only disable the specified
- * interrupts without enabling or disabling any others.
- */
- Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
- XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET,
- Register & (~Mask));
-
-}
-
-/****************************************************************************/
-/**
-* Clear pending interrupts with the provided mask. This function should be
-* called after the software has serviced the interrupts that are pending.
-* This function will assert if the hardware device has not been built with
-* interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-* @param Mask is the mask to clear pending interrupts for. Bit positions
-* of 1 are cleared. This mask is formed by OR'ing bits from
-* XGPIO_IR* bits which are contained in xgpio_l.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XGpio_InterruptClear(XGpio * InstancePtr, u32 Mask)
-{
- u32 Register;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid(InstancePtr->InterruptPresent == TRUE);
-
- /*
- * Read the interrupt status register and only clear the interrupts
- * that are specified without affecting any others. Since the register
- * is a toggle on write, make sure any bits to be written are already
- * set.
- */
- Register = XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET);
- XGpio_WriteReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET,
- Register & Mask);
-
-
-}
-
-
-/****************************************************************************/
-/**
-* Returns the interrupt enable mask. This function will assert if the
-* hardware device has not been built with interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-*
-* @return A mask of bits made from XGPIO_IR* bits which are contained in
-* xgpio_l.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XGpio_InterruptGetEnabled(XGpio * InstancePtr)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(InstancePtr->InterruptPresent == TRUE);
-
- return XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_IER_OFFSET);
-}
-
-
-/****************************************************************************/
-/**
-* Returns the status of interrupt signals. Any bit in the mask set to 1
-* indicates that the channel associated with the bit has asserted an interrupt
-* condition. This function will assert if the hardware device has not been
-* built with interrupt capabilities.
-*
-* @param InstancePtr is the GPIO instance to operate on.
-*
-* @return A pointer to a mask of bits made from XGPIO_IR* bits which are
-* contained in xgpio_l.h.
-*
-* @note
-*
-* The interrupt status indicates the status of the device regardless if
-* the interrupts from the devices have been enabled or not through
-* XGpio_InterruptEnable().
-*
-*****************************************************************************/
-u32 XGpio_InterruptGetStatus(XGpio * InstancePtr)
-{
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertNonvoid(InstancePtr->InterruptPresent == TRUE);
-
-
- return XGpio_ReadReg(InstancePtr->BaseAddress, XGPIO_ISR_OFFSET);
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f3/d0ba6f585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f3/d0ba6f585243001d18b399c1eb9b3628
deleted file mode 100644
index 604bd8c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f3/d0ba6f585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
-Copyright DornerWorks 2016
-
-Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-following conditions are met:
-1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
-following disclaimer.
-
-THIS SOFTWARE IS PROVIDED BY DORNERWORKS FOR USE ON THE CONTRACTED PROJECT, AND ANY EXPRESS OR IMPLIED WARRANTY
-IS LIMITED TO THIS USE. FOR ALL OTHER USES THIS SOFTWARE IS PROVIDED ''AS IS'' AND ANY EXPRESS OR IMPLIED
-WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL DORNERWORKS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#ifndef __HYPERCALL_H__
-#define __HYPERCALL_H__
-
-#include "xen.h"
-
-int HYPERVISOR_console_io(int cmd, int count, char *str);
-int HYPERVISOR_hvm_op(int cmd, void* param);
-int HYPERVISOR_memory_op(int cmd, void* param);
-int HYPERVISOR_event_channel_op(int cmd, void* param);
-
-#endif /* __HYPERCALL_H__ */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f4/10a13a585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f4/10a13a585243001d18b399c1eb9b3628
deleted file mode 100644
index 4c55bbd..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f4/10a13a585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,18 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include "xil_types.h"
-
-/* _exit - Simple implementation. Does not return.
-*/
-__attribute__((weak)) void _exit (sint32 status)
-{
- (void)status;
- while (1) {
- ;
- }
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f4/61b167525243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f4/61b167525243001d18b399c1eb9b3628
deleted file mode 100644
index 92705fe..0000000
Binary files a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f4/61b167525243001d18b399c1eb9b3628 and /dev/null differ
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f4/70974b555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f4/70974b555243001d18b399c1eb9b3628
deleted file mode 100644
index cbec306..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f4/70974b555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,420 +0,0 @@
-/*
- ****************************************************************************
- * (C) 2006 - Grzegorz Milos - Cambridge University
- ****************************************************************************
- *
- * File: console.h
- * Author: Grzegorz Milos
- * Changes:
- *
- * Date: Mar 2006
- *
- * Environment: Xen Minimal OS
- * Description: Console interface.
- *
- * Handles console I/O. Defines printk.
- *
- ****************************************************************************
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to
- * deal in the Software without restriction, including without limitation the
- * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-/*
-Copyright DornerWorks 2016
-
-Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-following conditions are met:
-1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
-following disclaimer.
-
-THIS SOFTWARE IS PROVIDED BY DORNERWORKS FOR USE ON THE CONTRACTED PROJECT, AND ANY EXPRESS OR IMPLIED WARRANTY
-IS LIMITED TO THIS USE. FOR ALL OTHER USES THIS SOFTWARE IS PROVIDED ''AS IS'' AND ANY EXPRESS OR IMPLIED
-WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL DORNERWORKS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-#include
-#include
-#include
-#include
-#include "hypercall.h"
-#include "arm64_ops.h"
-#include "xen.h"
-#include "xen_console.h"
-#include "xen_events.h"
-
-#define ECHO_TO_UART 1
-#define SUCCESS 0
-#define ARG_NULL -1
-#define INIT_FAILED -2
-#define INIT_NOT_DONE -3
-#define BUFFER_OVERFLOW -4
-#define PRINT_FAILED -5
-
-#define PAGE_TO_ADDR(x) ((void*)((u64)(x)<out_cons;
- prod = intf->out_prod;
- mb();
- BUG_ON((prod - cons) > sizeof(intf->out));
-
- while ((sent < len) && ((prod - cons) < sizeof(intf->out)))
- {
- intf->out[MASK_XENCONS_IDX(prod++, intf->out)] = data[sent++];
- }
- wmb();
- intf->out_prod = prod;
-
- return sent;
-}
-
-// Copies the characters then raises an event to Xen
-static int xencons_ring_send(const u8 *data, unsigned len)
-{
- int sent;
-
- sent = xencons_ring_send_no_notify(data, len);
- notify_evtch(cons_evtch);
-
- return sent;
-}
-
-// Does some data reformatting to handle newline
-static void console_print(char *data, int length)
-{
- u8 *curr_char, saved_char;
- u8 copied_str[length+1];
- u8 *copied_ptr;
- int part_len;
- int (*ring_send_fn)(const u8 *data, unsigned length);
-
- if(!console_initialised)
- ring_send_fn = xencons_ring_send_no_notify;
- else
- ring_send_fn = xencons_ring_send;
-
- copied_ptr = copied_str;
- memcpy(copied_ptr, data, length);
-
- for(curr_char = copied_ptr; curr_char < copied_ptr+length-1; curr_char++)
- {
- if(*curr_char == '\n')
- {
- *curr_char = '\r';
- saved_char = *(curr_char+1);
- *(curr_char+1) = '\n';
- part_len = curr_char - copied_ptr + 2;
- ring_send_fn(copied_ptr, part_len);
- *(curr_char+1) = saved_char;
- copied_ptr = curr_char+1;
- length -= part_len - 1;
- }
- }
-
- if (copied_ptr[length-1] == '\n') {
- copied_ptr[length-1] = '\r';
- copied_ptr[length] = '\n';
- length++;
- }
-
- ring_send_fn(copied_ptr, length);
-}
-
-// This function will print to Xen's console one way or another
-static void pvc_print(int direct, const char *fmt, va_list args)
-{
- static char buf[1024];
-
- (void)vsnprintf(buf, sizeof(buf), fmt, args);
-
- if(direct)
- {
- // if console ring buffer/event not ready, use the Xen console IO hypercall
- (void)HYPERVISOR_console_io(CONSOLEIO_write, strlen(buf), buf);
- }
- else
- {
- console_print(buf, strlen(buf));
- }
-}
-
-// Use this function to print to the Xen console
-void printk(const char *fmt, ...)
-{
- va_list args;
- va_start(args, fmt);
- pvc_print(console_initialised!=1, fmt, args);
- va_end(args);
-}
-
-
-// Register this function with event handler to take care of console events
-static void console_handle_input(void)
-{
- struct xencons_interface *intf = mfn_to_virt(guest_phys_page);
- u32 cons, prod;
- u8 byte;
- static int cr = 0;
- char data[sizeof(intf->in)+1] = {0};
- int i;
-
-
- cons = intf->in_cons;
- prod = intf->in_prod;
- mb();
- BUG_ON((prod - cons) > sizeof(intf->in));
-
- i = 0;
- while (cons != prod)
- {
- byte = *(intf->in+MASK_XENCONS_IDX(cons,intf->in));
- cons++;
- data[i++] = byte;
- }
-
- mb();
- intf->in_cons = cons;
- notify_evtch(cons_evtch);
- console_input_callback(data, i);
-}
-
-// Initializes the Xen virtual console
-void init_console(void)
-{
- u64 val;
- int rv;
-
- init_events();
-
- // get the page where the console ring buffer is
- if(0 == get_hv_param(HVM_PARAM_CONSOLE_PFN, &val))
- {
- guest_phys_page = val;
- }
-
- // get event channel info necessary to do the things
- if(0 == get_hv_param(HVM_PARAM_CONSOLE_EVTCHN, &val))
- {
- cons_evtch = val;
- register_event_handler(cons_evtch, console_handle_input);
- }
- else
- {
- printk("error getting console event channel ID\r\n");
- }
-
- unmask_evtchn(cons_evtch);
- console_initialised = 1;
-}
-void XPVXenConsole_Init()
-{
- init_console();
-}
-/*****************************************************************************/
-/**
- *
- * @brief This function writes data to xen console output ring buffer &
- * sends event notification to xen
- *
- * @param BufferPtr: Pointer to buffer data to be written/copied to xen
- * console output ring buffer
- *
- * @return
- * Length: if data written to xen console output buffer successfully
- * BUFFER_OVERFLOW: if xen console output buffer overflow
- *
- ******************************************************************************/
- int XPVXenConsole_Write(const char *BufferPtr) {
- u32 Length = 0;
- u32 RingIndex = 0;
- struct xencons_interface *ConsoleInterfacePtr = mfn_to_virt(guest_phys_page);
- u32 Cons = ConsoleInterfacePtr->out_cons;
- u32 Prod = ConsoleInterfacePtr->out_prod;
-
- /*
- * It guarantees that any memory access initiated before the memory
- * barrier will be complete before passing the barrier, and all
- * subsequent memory accesses will be executed after the barrier
- */
- mb();
- if ((Prod - Cons) > sizeof(ConsoleInterfacePtr->out)) {
- notify_evtch(cons_evtch);
- return BUFFER_OVERFLOW;
- }
- /*
- * write buffer data into xen console output ring buffer,
- * taking care not to overflow the console output ring buffer
- */
- while ((*BufferPtr != '\0') &&
- ((Prod - Cons) < sizeof(ConsoleInterfacePtr->out))) {
- RingIndex = MASK_XENCONS_IDX(Prod, ConsoleInterfacePtr->out);
- ConsoleInterfacePtr->out[RingIndex] = *BufferPtr++;
- Prod++;
- Length++;
- }
- /*
- * make sure that data written into xen console output ring buffer
- * before updating the pointer
- */
- wmb();
- ConsoleInterfacePtr->out_prod = Prod;
- notify_evtch(cons_evtch);
-
- return Length;
-}
-/*****************************************************************************/
-/**
- *
- * @brief This API is used to print data on xen console
- *
- * @param FormatPtr: Pointer to format/string to be printed on xen console
- *
- * @return
- * SUCCESS: if xen console printed data successfully
- * INIT_NOT_DONE: if xen console initialization not done
- * ARG_NULL: if null argument passed to function
- * BUFFER_OVERFLOW: if print buffer overflow
- * PRINT_FAILED: if xen console printed data failed
- *
- ******************************************************************************/
-int XPVXenConsole_Printf(const char *FormatPtr, ...) {
- va_list Args;
- struct xencons_interface *ConsoleInterfacePtr = mfn_to_virt(guest_phys_page);
- static char Buf[sizeof(ConsoleInterfacePtr->out) + 1] = { 0 };
- u32 Ret = 0;
- int Length = 0;
-
- if (ConsoleInterfacePtr == NULL) {
- return INIT_NOT_DONE;
- }
- if (FormatPtr == NULL) {
- return ARG_NULL;
- }
-
- va_start(Args, FormatPtr);
- Ret = vsnprintf(Buf, sizeof(Buf), FormatPtr, Args);
- va_end(Args);
- if (Ret > (u32) sizeof(Buf)) {
- return BUFFER_OVERFLOW;
- }
-
- Length = XPVXenConsole_Write(Buf);
- if (Length < 0) {
- return PRINT_FAILED;
- }
-
- return SUCCESS;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f4/93ff82595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f4/93ff82595243001d18b399c1eb9b3628
deleted file mode 100644
index 926da80..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f4/93ff82595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,21 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include "profile.h"
-#include "_profile_timer_hw.h"
-#include "xil_exception.h"
-
-void _profile_clean( void );
-
-/*
- * This function is the exit routine and is called by the crtinit, when the
- * program terminates. The name needs to be changed later..
- */
-void _profile_clean( void )
-{
- Xil_ExceptionDisable();
- disable_timer();
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f4/a0927d575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f4/a0927d575243001d18b399c1eb9b3628
deleted file mode 100644
index e48c5f3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f4/a0927d575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,111 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2013 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_errata.h
-*
-* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
-* @{
-* Various ARM errata are handled in the standalone BSP. The implementation for
-* errata handling follows ARM guidelines and is based on the open source Linux
-* support for these errata.
-*
-* @note The errata handling is enabled by default. To disable handling of all the
-* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
-* disable errata on a per-erratum basis, un-define relevant macros in
-* xil_errata.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a srt 04/18/13 First release
-* 6.6 mus 12/07/17 Removed errata 753970, It fixes CR#989132.
-*
-*
-******************************************************************************/
-#ifndef XIL_ERRATA_H
-#define XIL_ERRATA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *@cond nocomments
- */
-/**
- * @name errata_definitions
- *
- * The errata conditions handled in the standalone BSP are listed below
- * @{
- */
-
-#define ENABLE_ARM_ERRATA 1
-
-/**
- *@endcond
- */
-
-#ifdef ENABLE_ARM_ERRATA
-
-/**
- * Errata No: 742230
- * Description: DMB operation may be faulty
- */
-#define CONFIG_ARM_ERRATA_742230 1
-
-/**
- * Errata No: 743622
- * Description: Faulty hazard checking in the Store Buffer may lead
- * to data corruption.
- */
-#define CONFIG_ARM_ERRATA_743622 1
-
-/**
- * Errata No: 775420
- * Description: A data cache maintenance operation which aborts,
- * might lead to deadlock
- */
-#define CONFIG_ARM_ERRATA_775420 1
-
-/**
- * Errata No: 794073
- * Description: Speculative instruction fetches with MMU disabled
- * might not comply with architectural requirements
- */
-#define CONFIG_ARM_ERRATA_794073 1
-
-
-/** PL310 L2 Cache Errata */
-
-/**
- * Errata No: 588369
- * Description: Clean & Invalidate maintenance operations do not
- * invalidate clean lines
- */
-#define CONFIG_PL310_ERRATA_588369 1
-
-/**
- * Errata No: 727915
- * Description: Background Clean and Invalidate by Way operation
- * can cause data corruption
- */
-#define CONFIG_PL310_ERRATA_727915 1
-
-/*@}*/
-#endif /* ENABLE_ARM_ERRATA */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_ERRATA_H */
-/**
-* @} End of "addtogroup a9_errata".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f4/b0068c565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f4/b0068c565243001d18b399c1eb9b3628
deleted file mode 100644
index e654a6c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f4/b0068c565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,38 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-* File : microblaze_enable_icache.s
-* Date : 2002, March 20.
-* Company: Xilinx
-* Group : Emerging Software Technologies
-*
-* Summary:
-* Enable icache on the microblaze.
-*
-*
-******************************************************************************/
-#include "xparameters.h"
-
- .text
- .globl microblaze_enable_icache
- .ent microblaze_enable_icache
- .align 2
-microblaze_enable_icache:
-#if XPAR_MICROBLAZE_USE_MSR_INSTR == 1
- rtsd r15, 8
- msrset r0, 0x20
-#else /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- #Read the MSR register
- mfs r8, rmsr
- #Set the interrupt enable bit
- ori r8, r8, 0x20
- #Save the MSR register
- mts rmsr, r8
- #Return
- rtsd r15, 8
- nop
-#endif /*XPAR_MICROBLAZE_USE_MSR_INSTR == 1*/
- .end microblaze_enable_icache
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f4/b015c2575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f4/b015c2575243001d18b399c1eb9b3628
deleted file mode 100644
index e567699..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f4/b015c2575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,377 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xdevcfg.h
-* @addtogroup devcfg_v3_7
-* @{
-* @details
-*
-* The is the main header file for the Device Configuration Interface of the Zynq
-* device. The device configuration interface has three main functionality.
-* 1. AXI-PCAP
-* 2. Security Policy
-* 3. XADC
-* This current version of the driver supports only the AXI-PCAP and Security
-* Policy blocks. There is a separate driver for XADC.
-*
-* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream.
-* DMA embedded in the AXI PCAP provides the master interface to
-* the Device configuration block for any DMA transfers. The data transfer can
-* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip
-* RAM/DDR/peripheral memory).
-*
-* The current driver only supports the downloading the FPGA bitstream and
-* readback of the decrypted image (sort of loopback).
-* The driver does not know what information needs to be written to the FPGA to
-* readback FPGA configuration register or memory data. The application above the
-* driver should take care of creating the data that needs to be downloaded to
-* the FPGA so that the bitstream can be readback.
-* This driver also does not support the reading of the internal registers of the
-* PCAP. The driver has no knowledge of the PCAP internals.
-*
-* Initialization and Configuration
-*
-* The device driver enables higher layer software (e.g., an application) to
-* communicate with the Device Configuration device.
-*
-* XDcfg_CfgInitialize() API is used to initialize the Device Configuration
-* Interface. The user needs to first call the XDcfg_LookupConfig() API which
-* returns the Configuration structure pointer which is passed as a parameter to
-* the XDcfg_CfgInitialize() API.
-*
-* Interrupts
-* The Driver implements an interrupt handler to support the interrupts provided
-* by this interface.
-*
-* Threads
-*
-* This driver is not thread safe. Any needs for threads or thread mutual
-* exclusion must be satisfied by the layer above this driver.
-*
-* Asserts
-*
-* Asserts are used within all Xilinx drivers to enforce constraints on argument
-* values. Asserts can be turned off on a system-wide basis by defining, at
-* compile time, the NDEBUG identifier. By default, asserts are turned on and it
-* is recommended that users leave asserts on during development.
-*
-* Building the driver
-*
-* The XDcfg driver is composed of several source files. This allows the user
-* to build and link only those parts of the driver that are necessary.
-*
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- ---------------------------------------------
-* 1.00a hvm 02/07/11 First release
-* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
-* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
-* APIs is words (32 bit) and not bytes.
-* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
-* to add information that 2 LSBs of the Source/Destination
-* address when equal to 2�b01 indicate the last DMA command
-* of an overall transfer.
-* Destination Address passed to this API for secure transfers
-* instead of using 0xFFFFFFFF for CR 662197. This issue was
-* resulting in the failure of secure transfers of
-* non-bitstream images.
-* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
-* set the mask instead of oring it with the
-* value read from the interrupt status register
-* Added defines for the PS Version bits,
-* removed the FIFO Flush bits from the
-* Miscellaneous Control Reg.
-* Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
-* and XDcfg_SelectPcapInterface APIs for CR 643295
-* The user has to call the XDcfg_SelectIcapInterface API
-* for the PL reconfiguration using AXI HwIcap.
-* Updated the XDcfg_Transfer API to clear the
-* QUARTER_PCAP_RATE_EN bit in the control register for
-* non secure writes for CR 675543.
-* 2.02a nm 01/31/13 Fixed CR# 679335.
-* Added Setting and Clearing the internal PCAP loopback.
-* Removed code for enabling/disabling AES engine as BootROM
-* locks down this setting.
-* Fixed CR# 681976.
-* Skip Checking the PCFG_INIT in case of non-secure DMA
-* loopback.
-* Fixed CR# 699558.
-* XDcfg_Transfer fails to transfer data in loopback mode.
-* Fixed CR# 701348.
-* Peripheral test fails with Running
-* DcfgSelfTestExample() in SECURE bootmode.
-* 2.03a nm 04/19/13 Fixed CR# 703728.
-* Updated the register definitions as per the latest TRM
-* version UG585 (v1.4) November 16, 2012.
-* 3.0 adk 10/12/13 Updated as per the New Tcl API's
-* 3.0 kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
-* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
-* updated driver code with != instead of ==,
-* while checking for Interrupt Status with DMA and
-* PCAP Done Mask
-* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
-* XDCFG_INT_STS_OFFSET) &
-* XDCFG_IXR_D_P_DONE_MASK) !=
-* XDCFG_IXR_D_P_DONE_MASK);
-* A new example has been added to read back the
-* configuration registers from the PL region.
-* xdevcfg_reg_readback_example.c
-* 3.3 sk 04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/10/17 Modified filename tag in interrupt and polled examples
-* to include them in doxygen examples.
-* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros
-* definitions of devcfg in xparameters.h
-* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
-*
-*
-******************************************************************************/
-#ifndef XDCFG_H /* prevent circular inclusions */
-#define XDCFG_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xdevcfg_hw.h"
-#include "xstatus.h"
-#include "xil_assert.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-
-/* Types of PCAP transfers */
-
-#define XDCFG_NON_SECURE_PCAP_WRITE 1
-#define XDCFG_SECURE_PCAP_WRITE 2
-#define XDCFG_PCAP_READBACK 3
-#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4
-#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5
-
-
-/**************************** Type Definitions *******************************/
-/**
-* The handler data type allows the user to define a callback function to
-* respond to interrupt events in the system. This function is executed
-* in interrupt context, so amount of processing should be minimized.
-*
-* @param CallBackRef is the callback reference passed in by the upper
-* layer when setting the callback functions, and passed back to
-* the upper layer when the callback is invoked. Its type is
-* unimportant to the driver component, so it is a void pointer.
-* @param Status is the Interrupt status of the XDcfg device.
-*/
-typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddr; /**< Base address of the device */
-} XDcfg_Config;
-
-/**
- * The XDcfg driver instance data.
- */
-typedef struct {
- XDcfg_Config Config; /**< Hardware Configuration */
- u32 IsReady; /**< Device is initialized and ready */
- u32 IsStarted; /**< Device Configuration Interface
- * is running
- */
- XDcfg_IntrHandler StatusHandler; /* Event handler function */
- void *CallBackRef; /* Callback reference for event handler */
-} XDcfg;
-
-/****************************************************************************/
-/**
-*
-* Unlock the Device Config Interface block.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_Unlock(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_Unlock(InstancePtr) \
- XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \
- XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
-
-
-
-/****************************************************************************/
-/**
-*
-* Get the version number of the PS from the Miscellaneous Control Register.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return Version of the PS.
-*
-* @note C-style signature:
-* void XDcfg_GetPsVersion(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_GetPsVersion(InstancePtr) \
- ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
- XDCFG_MCTRL_OFFSET)) & \
- XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \
- XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
-
-
-
-/****************************************************************************/
-/**
-*
-* Read the multiboot config register value.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_ReadMultiBootConfig(InstancePtr) \
- XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
- XDCFG_MULTIBOOT_ADDR_OFFSET)
-
-
-/****************************************************************************/
-/**
-*
-* Selects ICAP interface for reconfiguration after the initial configuration
-* of the PL.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_SelectIcapInterface(InstancePtr) \
- XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
- ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
- & ( ~XDCFG_CTRL_PCAP_PR_MASK)))
-
-/****************************************************************************/
-/**
-*
-* Selects PCAP interface for reconfiguration after the initial configuration
-* of the PL.
-*
-* @param InstancePtr is a pointer to the instance of XDcfg driver.
-*
-* @return None.
-*
-* @note C-style signature:
-* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr)
-*
-*****************************************************************************/
-#define XDcfg_SelectPcapInterface(InstancePtr) \
- XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
- ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
- | XDCFG_CTRL_PCAP_PR_MASK))
-
-
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Lookup configuration in xdevcfg_sinit.c.
- */
-XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId);
-
-/*
- * Selftest function in xdevcfg_selftest.c
- */
-int XDcfg_SelfTest(XDcfg *InstancePtr);
-
-/*
- * Interface functions in xdevcfg.c
- */
-int XDcfg_CfgInitialize(XDcfg *InstancePtr,
- XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
-
-void XDcfg_EnablePCAP(XDcfg *InstancePtr);
-
-void XDcfg_DisablePCAP(XDcfg *InstancePtr);
-
-void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask);
-
-void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask);
-
-u32 XDcfg_GetControlRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetLockRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data);
-
-u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr);
-
-void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask);
-
-u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr);
-
-u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr);
-
-void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
- u32 SrcWordLength, u32 DestWordLength);
-
-u32 XDcfg_Transfer(XDcfg *InstancePtr,
- void *SourcePtr, u32 SrcWordLength,
- void *DestPtr, u32 DestWordLength,
- u32 TransferType);
-
-/*
- * Interrupt related function prototypes implemented in xdevcfg_intr.c
- */
-void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask);
-
-void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask);
-
-u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr);
-
-u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr);
-
-void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask);
-
-void XDcfg_InterruptHandler(XDcfg *InstancePtr);
-
-void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
- void *CallBackRef);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f4/e35abe595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f4/e35abe595243001d18b399c1eb9b3628
deleted file mode 100644
index edf6684..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f4/e35abe595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,558 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpm_counter.h
-*
-* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions
-*
-* Cortex A9 event counter functions can be utilized to configure and control
-* the Cortex-A9 performance monitor events.
-*
-* Cortex-A9 performance monitor has six event counters which can be used to
-* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines
-* configurations XPM_CNTRCFGx which can be used to program the event counters
-* to count a set of events.
-*
-* @note
-* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
-* being used for time keeping.
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a sdm 07/11/11 First release
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-*
-******************************************************************************/
-
-/**
-*@cond nocomments
-*/
-
-#ifndef XPMCOUNTER_H /* prevent circular inclusions */
-#define XPMCOUNTER_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/************************** Constant Definitions ****************************/
-
-/* Number of performance counters */
-#define XPM_CTRCOUNT 6U
-
-/* The following constants define the Cortex-A9 Performance Monitor Events */
-
-/*
- * Software increment. The register is incremented only on writes to the
- * Software Increment Register
- */
-#define XPM_EVENT_SOFTINCR 0x00U
-
-/*
- * Instruction fetch that causes a refill at (at least) the lowest level(s) of
- * instruction or unified cache. Includes the speculative linefills in the
- * count
- */
-#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
-
-/*
- * Instruction fetch that causes a TLB refill at (at least) the lowest level of
- * TLB. Includes the speculative requests in the count
- */
-#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
-
-/*
- * Data read or write operation that causes a refill at (at least) the lowest
- * level(s)of data or unified cache. Counts the number of allocations performed
- * in the Data Cache due to a read or a write
- */
-#define XPM_EVENT_DATA_CACHEREFILL 0x03U
-
-/*
- * Data read or write operation that causes a cache access at (at least) the
- * lowest level(s) of data or unified cache. This includes speculative reads
- */
-#define XPM_EVENT_DATA_CACHEACCESS 0x04U
-
-/*
- * Data read or write operation that causes a TLB refill at (at least) the
- * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
- * CP15 Cache operation by MVA and CP15 VA to PA operations
- */
-#define XPM_EVENT_DATA_TLBREFILL 0x05U
-
-/*
- * Data read architecturally executed. Counts the number of data read
- * instructions accepted by the Load Store Unit. This includes counting the
- * speculative and aborted LDR/LDM, as well as the reads due to the SWP
- * instructions
- */
-#define XPM_EVENT_DATA_READS 0x06U
-
-/*
- * Data write architecturally executed. Counts the number of data write
- * instructions accepted by the Load Store Unit. This includes counting the
- * speculative and aborted STR/STM, as well as the writes due to the SWP
- * instructions
- */
-#define XPM_EVENT_DATA_WRITE 0x07U
-
-/* Exception taken. Counts the number of exceptions architecturally taken.*/
-#define XPM_EVENT_EXCEPTION 0x09U
-
-/* Exception return architecturally executed.*/
-#define XPM_EVENT_EXCEPRETURN 0x0AU
-
-/*
- * Change to ContextID retired. Counts the number of instructions
- * architecturally executed writing into the ContextID Register
- */
-#define XPM_EVENT_CHANGECONTEXT 0x0BU
-
-/*
- * Software change of PC, except by an exception, architecturally executed.
- * Count the number of PC changes architecturally executed, excluding the PC
- * changes due to taken exceptions
- */
-#define XPM_EVENT_SW_CHANGEPC 0x0CU
-
-/*
- * Immediate branch architecturally executed (taken or not taken). This includes
- * the branches which are flushed due to a previous load/store which aborts
- * late
- */
-#define XPM_EVENT_IMMEDBRANCH 0x0DU
-
-/*
- * Unaligned access architecturally executed. Counts the number of aborted
- * unaligned accessed architecturally executed, and the number of not-aborted
- * unaligned accesses, including the speculative ones
- */
-#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
-
-/*
- * Branch mispredicted/not predicted. Counts the number of mispredicted or
- * not-predicted branches executed. This includes the branches which are flushed
- * due to a previous load/store which aborts late
- */
-#define XPM_EVENT_BRANCHMISS 0x10U
-
-/*
- * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
- * event is not exported on the PMUEVENT bus
- */
-#define XPM_EVENT_CLOCKCYCLES 0x11U
-
-/*
- * Branches or other change in program flow that could have been predicted by
- * the branch prediction resources of the processor. This includes the branches
- * which are flushed due to a previous load/store which aborts late
- */
-#define XPM_EVENT_BRANCHPREDICT 0x12U
-
-/*
- * Java bytecode execute. Counts the number of Java bytecodes being decoded,
- * including speculative ones
- */
-#define XPM_EVENT_JAVABYTECODE 0x40U
-
-/*
- * Software Java bytecode executed. Counts the number of software java bytecodes
- * being decoded, including speculative ones
- */
-#define XPM_EVENT_SWJAVABYTECODE 0x41U
-
-/*
- * Jazelle backward branches executed. Counts the number of Jazelle taken
- * branches being executed. This includes the branches which are flushed due
- * to a previous load/store which aborts late
- */
-#define XPM_EVENT_JAVABACKBRANCH 0x42U
-
-/*
- * Coherent linefill miss Counts the number of coherent linefill requests
- * performed by the Cortex-A9 processor which also miss in all the other
- * Cortex-A9 processors, meaning that the request is sent to the external
- * memory
- */
-#define XPM_EVENT_COHERLINEMISS 0x50U
-
-/*
- * Coherent linefill hit. Counts the number of coherent linefill requests
- * performed by the Cortex-A9 processor which hit in another Cortex-A9
- * processor, meaning that the linefill data is fetched directly from the
- * relevant Cortex-A9 cache
- */
-#define XPM_EVENT_COHERLINEHIT 0x51U
-
-/*
- * Instruction cache dependent stall cycles. Counts the number of cycles where
- * the processor is ready to accept new instructions, but does not receive any
- * due to the instruction side not being able to provide any and the
- * instruction cache is currently performing at least one linefill
- */
-#define XPM_EVENT_INSTRSTALL 0x60U
-
-/*
- * Data cache dependent stall cycles. Counts the number of cycles where the core
- * has some instructions that it cannot issue to any pipeline, and the Load
- * Store unit has at least one pending linefill request, and no pending
- */
-#define XPM_EVENT_DATASTALL 0x61U
-
-/*
- * Main TLB miss stall cycles. Counts the number of cycles where the processor
- * is stalled waiting for the completion of translation table walks from the
- * main TLB. The processor stalls can be due to the instruction side not being
- * able to provide the instructions, or to the data side not being able to
- * provide the necessary data, due to them waiting for the main TLB translation
- * table walk to complete
- */
-#define XPM_EVENT_MAINTLBSTALL 0x62U
-
-/*
- * Counts the number of STREX instructions architecturally executed and
- * passed
- */
-#define XPM_EVENT_STREXPASS 0x63U
-
-/*
- * Counts the number of STREX instructions architecturally executed and
- * failed
- */
-#define XPM_EVENT_STREXFAIL 0x64U
-
-/*
- * Data eviction. Counts the number of eviction requests due to a linefill in
- * the data cache
- */
-#define XPM_EVENT_DATAEVICT 0x65U
-
-/*
- * Counts the number of cycles where the issue stage does not dispatch any
- * instruction because it is empty or cannot dispatch any instructions
- */
-#define XPM_EVENT_NODISPATCH 0x66U
-
-/*
- * Counts the number of cycles where the issue stage is empty
- */
-#define XPM_EVENT_ISSUEEMPTY 0x67U
-
-/*
- * Counts the number of instructions going through the Register Renaming stage.
- * This number is an approximate number of the total number of instructions
- * speculatively executed, and even more approximate of the total number of
- * instructions architecturally executed. The approximation depends mainly on
- * the branch misprediction rate.
- * The renaming stage can handle two instructions in the same cycle so the event
- * is two bits long:
- * - b00 no instructions renamed
- * - b01 one instruction renamed
- * - b10 two instructions renamed
- */
-#define XPM_EVENT_INSTRRENAME 0x68U
-
-/*
- * Counts the number of procedure returns whose condition codes do not fail,
- * excluding all returns from exception. This count includes procedure returns
- * which are flushed due to a previous load/store which aborts late.
- * Only the following instructions are reported:
- * - BX R14
- * - MOV PC LR
- * - POP {..,pc}
- * - LDR pc,[sp],#offset
- * The following instructions are not reported:
- * - LDMIA R9!,{..,PC} (ThumbEE state only)
- * - LDR PC,[R9],#offset (ThumbEE state only)
- * - BX R0 (Rm != R14)
- * - MOV PC,R0 (Rm != R14)
- * - LDM SP,{...,PC} (writeback not specified)
- * - LDR PC,[SP,#offset] (wrong addressing mode)
- */
-#define XPM_EVENT_PREDICTFUNCRET 0x6EU
-
-/*
- * Counts the number of instructions being executed in the main execution
- * pipeline of the processor, the multiply pipeline and arithmetic logic unit
- * pipeline. The counted instructions are still speculative
- */
-#define XPM_EVENT_MAINEXEC 0x70U
-
-/*
- * Counts the number of instructions being executed in the processor second
- * execution pipeline (ALU). The counted instructions are still speculative
- */
-#define XPM_EVENT_SECEXEC 0x71U
-
-/*
- * Counts the number of instructions being executed in the Load/Store unit. The
- * counted instructions are still speculative
- */
-#define XPM_EVENT_LDRSTR 0x72U
-
-/*
- * Counts the number of Floating-point instructions going through the Register
- * Rename stage. Instructions are still speculative in this stage.
- *Two floating-point instructions can be renamed in the same cycle so the event
- * is two bitslong:
- *0b00 no floating-point instruction renamed
- *0b01 one floating-point instruction renamed
- *0b10 two floating-point instructions renamed
- */
-#define XPM_EVENT_FLOATRENAME 0x73U
-
-/*
- * Counts the number of Neon instructions going through the Register Rename
- * stage.Instructions are still speculative in this stage.
- * Two NEON instructions can be renamed in the same cycle so the event is two
- * bits long:
- *0b00 no NEON instruction renamed
- *0b01 one NEON instruction renamed
- *0b10 two NEON instructions renamed
- */
-#define XPM_EVENT_NEONRENAME 0x74U
-
-/*
- * Counts the number of cycles where the processor is stalled because PLD slots
- * are all full
- */
-#define XPM_EVENT_PLDSTALL 0x80U
-
-/*
- * Counts the number of cycles when the processor is stalled and the data side
- * is stalled too because it is full and executing writes to the external
- * memory
- */
-#define XPM_EVENT_WRITESTALL 0x81U
-
-/*
- * Counts the number of stall cycles due to main TLB misses on requests issued
- * by the instruction side
- */
-#define XPM_EVENT_INSTRTLBSTALL 0x82U
-
-/*
- * Counts the number of stall cycles due to main TLB misses on requests issued
- * by the data side
- */
-#define XPM_EVENT_DATATLBSTALL 0x83U
-
-/*
- * Counts the number of stall cycles due to micro TLB misses on the instruction
- * side. This event does not include main TLB miss stall cycles that are already
- * counted in the corresponding main TLB event
- */
-#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
-
-/*
- * Counts the number of stall cycles due to micro TLB misses on the data side.
- * This event does not include main TLB miss stall cycles that are already
- * counted in the corresponding main TLB event
- */
-#define XPM_EVENT_DATA_uTLBSTALL 0x85U
-
-/*
- * Counts the number of stall cycles because of the execution of a DMB memory
- * barrier. This includes all DMB instructions being executed, even
- * speculatively
- */
-#define XPM_EVENT_DMB_STALL 0x86U
-
-/*
- * Counts the number of cycles during which the integer core clock is enabled
- */
-#define XPM_EVENT_INT_CLKEN 0x8AU
-
-/*
- * Counts the number of cycles during which the Data Engine clock is enabled
- */
-#define XPM_EVENT_DE_CLKEN 0x8BU
-
-/*
- * Counts the number of ISB instructions architecturally executed
- */
-#define XPM_EVENT_INSTRISB 0x90U
-
-/*
- * Counts the number of DSB instructions architecturally executed
- */
-#define XPM_EVENT_INSTRDSB 0x91U
-
-/*
- * Counts the number of DMB instructions speculatively executed
- */
-#define XPM_EVENT_INSTRDMB 0x92U
-
-/*
- * Counts the number of external interrupts executed by the processor
- */
-#define XPM_EVENT_EXTINT 0x93U
-
-/*
- * PLE cache line request completed
- */
-#define XPM_EVENT_PLE_LRC 0xA0U
-
-/*
- * PLE cache line request skipped
- */
-#define XPM_EVENT_PLE_LRS 0xA1U
-
-/*
- * PLE FIFO flush
- */
-#define XPM_EVENT_PLE_FLUSH 0xA2U
-
-/*
- * PLE request complete
- */
-#define XPM_EVENT_PLE_CMPL 0xA3U
-
-/*
- * PLE FIFO overflow
- */
-#define XPM_EVENT_PLE_OVFL 0xA4U
-
-/*
- * PLE request programmed
- */
-#define XPM_EVENT_PLE_PROG 0xA5U
-
-/*
- * The following constants define the configurations for Cortex-A9 Performance
- * Monitor Events. Each configuration configures the event counters for a set
- * of events.
- * -----------------------------------------------
- * Config PmCtr0... PmCtr5
- * -----------------------------------------------
- * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR,
- * XPM_EVENT_INSRFETCH_CACHEREFILL,
- * XPM_EVENT_INSTRFECT_TLBREFILL,
- * XPM_EVENT_DATA_CACHEREFILL,
- * XPM_EVENT_DATA_CACHEACCESS,
- * XPM_EVENT_DATA_TLBREFILL }
- *
- * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS,
- * XPM_EVENT_DATA_WRITE,
- * XPM_EVENT_EXCEPTION,
- * XPM_EVENT_EXCEPRETURN,
- * XPM_EVENT_CHANGECONTEXT,
- * XPM_EVENT_SW_CHANGEPC }
- *
- * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH,
- * XPM_EVENT_UNALIGNEDACCESS,
- * XPM_EVENT_BRANCHMISS,
- * XPM_EVENT_CLOCKCYCLES,
- * XPM_EVENT_BRANCHPREDICT,
- * XPM_EVENT_JAVABYTECODE }
- *
- * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE,
- * XPM_EVENT_JAVABACKBRANCH,
- * XPM_EVENT_COHERLINEMISS,
- * XPM_EVENT_COHERLINEHIT,
- * XPM_EVENT_INSTRSTALL,
- * XPM_EVENT_DATASTALL }
- *
- * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL,
- * XPM_EVENT_STREXPASS,
- * XPM_EVENT_STREXFAIL,
- * XPM_EVENT_DATAEVICT,
- * XPM_EVENT_NODISPATCH,
- * XPM_EVENT_ISSUEEMPTY }
- *
- * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME,
- * XPM_EVENT_PREDICTFUNCRET,
- * XPM_EVENT_MAINEXEC,
- * XPM_EVENT_SECEXEC,
- * XPM_EVENT_LDRSTR,
- * XPM_EVENT_FLOATRENAME }
- *
- * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME,
- * XPM_EVENT_PLDSTALL,
- * XPM_EVENT_WRITESTALL,
- * XPM_EVENT_INSTRTLBSTALL,
- * XPM_EVENT_DATATLBSTALL,
- * XPM_EVENT_INSTR_uTLBSTALL }
- *
- * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL,
- * XPM_EVENT_DMB_STALL,
- * XPM_EVENT_INT_CLKEN,
- * XPM_EVENT_DE_CLKEN,
- * XPM_EVENT_INSTRISB,
- * XPM_EVENT_INSTRDSB }
- *
- * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB,
- * XPM_EVENT_EXTINT,
- * XPM_EVENT_PLE_LRC,
- * XPM_EVENT_PLE_LRS,
- * XPM_EVENT_PLE_FLUSH,
- * XPM_EVENT_PLE_CMPL }
- *
- * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL,
- * XPM_EVENT_PLE_PROG,
- * XPM_EVENT_PLE_LRC,
- * XPM_EVENT_PLE_LRS,
- * XPM_EVENT_PLE_FLUSH,
- * XPM_EVENT_PLE_CMPL }
- *
- * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL,
- * XPM_EVENT_INSRFETCH_CACHEREFILL,
- * XPM_EVENT_INSTRFECT_TLBREFILL,
- * XPM_EVENT_DATA_CACHEREFILL,
- * XPM_EVENT_DATA_CACHEACCESS,
- * XPM_EVENT_DATA_TLBREFILL }
- */
-#define XPM_CNTRCFG1 0
-#define XPM_CNTRCFG2 1
-#define XPM_CNTRCFG3 2
-#define XPM_CNTRCFG4 3
-#define XPM_CNTRCFG5 4
-#define XPM_CNTRCFG6 5
-#define XPM_CNTRCFG7 6
-#define XPM_CNTRCFG8 7
-#define XPM_CNTRCFG9 8
-#define XPM_CNTRCFG10 9
-#define XPM_CNTRCFG11 10
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/**
-*@endcond
-*/
-
-/************************** Function Prototypes *****************************/
-
-/* Interface functions to access performance counters from abstraction layer */
-void Xpm_SetEvents(s32 PmcrCfg);
-void Xpm_GetEventCounters(u32 *PmCtrValue);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-* @} End of "addtogroup a9_event_counter_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f5/802f4e555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f5/802f4e555243001d18b399c1eb9b3628
deleted file mode 100644
index e8ae20f..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f5/802f4e555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
-Copyright DornerWorks 2016
-
-Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-following conditions are met:
-1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
-following disclaimer.
-
-THIS SOFTWARE IS PROVIDED BY DORNERWORKS FOR USE ON THE CONTRACTED PROJECT, AND ANY EXPRESS OR IMPLIED WARRANTY
-IS LIMITED TO THIS USE. FOR ALL OTHER USES THIS SOFTWARE IS PROVIDED ''AS IS'' AND ANY EXPRESS OR IMPLIED
-WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL DORNERWORKS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#include "xen.h"
-#include "hypercall.h"
-#include "arm64_ops.h"
-#include "xen_events.h"
-#include "xen_console.h"
-
-#define VA_TO_GUEST_PAGE(x) ((u64)x >> PAGE_SHIFT) //BMC set up a direct VA:PA mapping
-
-#define active_evtchns(cpu,sh,idx) \
- ((sh)->evtchn_pending[idx] & \
- ~(sh)->evtchn_mask[idx])
-
-// Structure for going about sharing a page with Xen
-struct xen_add_to_physmap
-{
- /* Which domain to change the mapping for. */
- u16 domid;
-
- /* Number of pages to go through for gmfn_range */
- u16 size;
-
- unsigned int space; /* => enum phys_map_space */
-
- /* Index into space being mapped. */
- u64 idx;
-
- /* GPFN in domid where the source mapping page should appear. */
- u64 gpfn;
-};
-typedef struct xen_add_to_physmap xen_add_to_physmap_t;
-
-struct vcpu_info {
- u8 evtchn_upcall_pending;
- u8 pad0;
- u64 evtchn_pending_sel;
- u8 pad[30];
-}; /* 64 bytes (x86) */
-typedef struct vcpu_info vcpu_info_t;
-
-struct shared_info
-{
- vcpu_info_t vcpu_info[1];
- u64 evtchn_pending[sizeof(u64) * 8];
- u64 evtchn_mask[sizeof(u64) * 8];
-};
-typedef struct shared_info shared_info_t;
-
-struct event_handler
-{
- u32 evtch_id;
- void (*handler_fptr)(void);
-};
-typedef struct event_handler event_handler_t;
-
-static event_handler_t event_handler_table[1] = {{0}};
-static __attribute__((aligned(0x1000))) u8 shared_info_page[1<vcpu_info[0];
-
- synch_clear_bit(port, &s->evtchn_mask[0]);
-
- /*
- * The following is basically the equivalent of 'hw_resend_irq'. Just like
- * a real IO-APIC we 'lose the interrupt edge' if the channel is masked.
- */
- if ( synch_test_bit (port, &s->evtchn_pending[0]) &&
- !synch_test_and_set_bit(port / (sizeof(unsigned long) * 8),
- &vcpu_info->evtchn_pending_sel) )
- {
- vcpu_info->evtchn_upcall_pending = 1;
-#ifdef XEN_HAVE_PV_UPCALL_MASK
- if ( !vcpu_info->evtchn_upcall_mask )
-#endif
- // force_evtchn_callback(); //todo, figure if this is needed
- }
-}
-
-// Clears the event flag so Xen can raise it again later
-static inline void clear_evtchn(uint32_t port)
-{
- shared_info_t *s = shared_info;
- synch_clear_bit(port, &s->evtchn_pending[0]);
-}
-
-// This is where we would call the handler for the specific event, but for now only supporting 1 event
-static int do_event(u32 port)
-{
- clear_evtchn(port);
-
- /* call the handler */
- if(port == event_handler_table[0].evtch_id)
- {
- event_handler_table[0].handler_fptr();
- }
-
- return 1;
-}
-
-// The IRQ handler for the interrupt that Xen uses for events (IRQ 31).
-void handle_event_irq(void* data)
-{
- unsigned long l1, l2, l1i, l2i;
- unsigned int port;
- int cpu = 0;
- shared_info_t *s = shared_info;
- vcpu_info_t *vcpu_info = &s->vcpu_info[cpu];
-
- vcpu_info->evtchn_upcall_pending = 0;
- wmb();
-
- l1 = xchg(&vcpu_info->evtchn_pending_sel, 0);
- while ( l1 != 0 )
- {
- l1i = __ffs(l1);
- l1 &= ~(1UL << l1i);
- while ( (l2 = active_evtchns(cpu, s, l1i)) != 0 )
- {
- l2i = __ffs(l2);
- l2 &= ~(1UL << l2i);
-
- port = (l1i * (sizeof(unsigned long) * 8)) + l2i;
- do_event(port);
-
- }
- }
-}
-
-// Initialize the guest's event framework
-void init_events(void)
-{
- xen_add_to_physmap_t xatp;
-
- /* Map shared_info page */
- xatp.domid = DOMID_SELF;
- xatp.idx = 0;
- xatp.space = XENMAPSPACE_shared_info;
- xatp.gpfn = VA_TO_GUEST_PAGE(shared_info_page);
-
- if(0 != HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp))
- {
- printk("ERROR setting up shared memory!\r\n");
- }
-
- shared_info = (struct shared_info *)shared_info_page;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f5/80d46b565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f5/80d46b565243001d18b399c1eb9b3628
deleted file mode 100644
index e22e04d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f5/80d46b565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,181 +0,0 @@
-/******************************************************************************/
-/**
-* Copyright (c) 2019 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-* @file xil_util.h
-* @addtogroup common_utilities Common Utility APIs
-* @{
-* @details
-*
-* This file contains xil utility functions declaration
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.4 mmd 04/21/19 First release.
-* 6.5 kal 02/29/20 Added Xil_ConvertStringToHexBE API
-* 7.3 kal 06/30/20 Converted Xil_Ceil macro to API
-* rpo 08/19/20 Added function for read, modify and write
-* bsv 08/21/20 Added XSECURE_TEMPORAL_CHECK macro to add
-* redundancy in security critical functions, to avoid
-* glitches from altering the return values of security
-* critical functions. The macro requires a label to be
-* passed to "go to" in case of error.
-* kpt 09/03/20 Added XSECURE_TEMPORAL_IMPL macro for redundancy
-* kal 09/22/20 Changed the param type from const char to const char*
-* to avoid copying key onto stack
-* td 10/16/20 Added Xil_Strcpy, Xil_Strcat, Xil_SecureMemCpy and
-* Xil_MemCmp functions
-* am 10/13/20 Resolved Coverity warning
-* td 11/19/20 Updated XSECURE_TEMPORAL_CHECK and
-* XSECURE_TEMPORAL_IMPL to fix MISRA C Rule 15.3
-* 7.4 am 11/26/20 Added Xil_StrCpyRange function
-* 7.6 kpt 07/15/21 Added Xil_SecureZeroize function
-*
-*
-*
-*****************************************************************************/
-
-#ifndef XIL_UTIL_H_
-#define XIL_UTIL_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xil_types.h"
-#include "xil_io.h"
-#include "xstatus.h"
-
-/*************************** Constant Definitions *****************************/
-#define XIL_SIZE_OF_NIBBLE_IN_BITS 4U
-#define XIL_SIZE_OF_BYTE_IN_BITS 8U
-
-/* Maximum string length handled by Xil_ValidateHexStr function */
-#define XIL_MAX_HEX_STR_LEN 512U
-
-
-/****************** Macros (Inline Functions) Definitions *********************/
-#ifdef __GNUC__
-/******************************************************************************/
-/**
- *
- * Updates the return value of the called function into Var and VarTmp variables
- * for redundancy. This is to avoid glitches from altering the return values of
- * security critical functions.
- *
- * @param Var is the variable which holds the return value of function
- * executed
- * @param VarTmp is the variable which holds the value stored in Var
- * @param Function is the function to be executed
- * @param Other params are arguments to the called function
- *
- * @return None
- *
- ******************************************************************************/
-#define XSECURE_TEMPORAL_IMPL(Var, VarTmp, Function, ...) \
- { \
- Var = XST_FAILURE; \
- VarTmp = XST_FAILURE; \
- Var = Function(__VA_ARGS__); \
- VarTmp = Var; \
- }
-
-/******************************************************************************/
-/**
- *
- * Adds redundancy while checking the status of the called function.
- * This is to avoid glitches from altering the return values of security
- * critical functions. The macro requires a label to be passed to "go to"
- * in case of error.
- *
- * @param Label is the label defined in function and the control
- * will jump to the label in case of XST_FAILURE
- * @param Status is the variable which holds the return value of
- * function executed
- * @param Function is the function to be executed
- * @param Other params are arguments to the called function
- *
- * @return None
- *
- ******************************************************************************/
-#define XSECURE_TEMPORAL_CHECK(Label, Status, Function, ...) \
- { \
- volatile int StatusTmp = XST_FAILURE; \
- XSECURE_TEMPORAL_IMPL(Status, StatusTmp, Function, __VA_ARGS__); \
- if ((Status != XST_SUCCESS) || \
- (StatusTmp != XST_SUCCESS)) { \
- Status |= StatusTmp;\
- goto Label; \
- } \
- }
-#endif
-
-/*************************** Function Prototypes ******************************/
-/* Ceils the provided float value */
-int Xil_Ceil(float Value);
-
-/* Converts input character to nibble */
-u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num);
-
-/* Convert input hex string to array of 32-bits integers */
-u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len);
-
-/* Waits for specified event */
-u32 Xil_WaitForEvent(u32 RegAddr, u32 EventMask, u32 Event, u32 Timeout);
-
-/* Waits for specified events */
-u32 Xil_WaitForEvents(u32 EventsRegAddr, u32 EventsMask, u32 WaitEvents,
- u32 Timeout, u32* Events);
-
-/* Validate input hex character */
-u32 Xil_IsValidHexChar(const char *Ch);
-
-/* Validate the input string contains only hexadecimal characters */
-u32 Xil_ValidateHexStr(const char *HexStr);
-
-/* Convert string to hex numbers in little enidian format */
-u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len);
-
-/* Returns length of the input string */
-u32 Xil_Strnlen(const char *Str, u32 MaxLen);
-
-/* Convert string to hex numbers in big endian format */
-u32 Xil_ConvertStringToHexBE(const char * Str, u8 * Buf, u32 Len);
-
-/*Read, Modify and Write to an address*/
-void Xil_UtilRMW32(u32 Addr, u32 Mask, u32 Value);
-
-/* Copies source string to destination string */
-int Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size);
-
-/* Copies specified range from source string to destination string */
-int Xil_StrCpyRange(const u8 *Src, u8 *Dst, u32 From, u32 To, u32 MaxSrcLen,
- u32 MaxDstLen);
-
-/* Appends string2 to string1 */
-int Xil_Strcat(char* Str1Ptr, const char* Str2Ptr, const u32 Size);
-
-/* Copies Len bytes from source memory to destination memory */
-int Xil_SecureMemCpy(void * DestPtr, u32 DestPtrLen, const void * SrcPtr, u32 Len);
-
-/* Compares Len bytes from memory1 and memory2 */
-int Xil_MemCmp(const void * Buf1Ptr, const void * Buf2Ptr, u32 Len);
-
-/* Zeroizes the memory of given length */
-int Xil_SecureZeroize(u8 *DataPtr, const u32 Length);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_UTIL_H_ */
-/**
-* @} End of "addtogroup common_utilities".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f5/c05688595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f5/c05688595243001d18b399c1eb9b3628
deleted file mode 100644
index 85fb264..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f5/c05688595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,37 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
- .globl dummy_f
-
-#ifdef PROC_MICROBLAZE
- .text
- .align 2
- .ent dummy_f
-
-dummy_f:
- nop
-
- .end dummy_f
-#endif
-
-#ifdef PROC_PPC
- .section .text
- .align 2
- .type dummy_f@function
-
-dummy_f:
- b dummy_f
-
-#endif
-
-#ifdef PROC_CORTEXA9
- .section .text
- .align 2
- .type dummy_f, %function
-
-dummy_f:
- b dummy_f
-
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f5/d07cb5555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f5/d07cb5555243001d18b399c1eb9b3628
deleted file mode 100644
index aeb2024..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f5/d07cb5555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,22 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-/*
- *
- * The "remove" function should remove the file named "filename". It
- * should return 0 on success and nonzero on failure.
- *
- */
-
-#include
-#include "xil_types.h"
-
-sint32 remove(const char8 * filename);
-
-sint32 remove(const char8 * filename)
-{
- return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f5/f3054a545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f5/f3054a545243001d18b399c1eb9b3628
deleted file mode 100644
index 1d18bfb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f5/f3054a545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,203 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_types.h
-*
-* @addtogroup common_types Basic Data types for Xilinx® Software IP
-*
-* The xil_types.h file contains basic types for Xilinx software IP. These data types
-* are applicable for all processors supported by Xilinx.
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/14/09 First release
-* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
-* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
-* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
-* Define LONG and ULONG datatypes and mask values
-* 7.00 mus 01/07/19 Add cpp extern macro
-* 7.1 aru 08/19/19 Shift the value in UPPER_32_BITS only if it
-* is 64-bit processor
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a hbm 08/25/09 First release
-* 7.5 mus 03/10/21 Added new set of Xil_TestMem32, Xil_TestMem16 and
-* Xil_TestMem8 APIs to support memory test for memory
-* regions mapped at extended addresses
-* (addresses > 4 GB). These new set of APIs would be
-* compiled only for 32 bit Microblaze processor, if
-* XPAR_MICROBLAZE_ADDR_SIZE is greater than 32.
-* It fixes CR#1089129.
-* 7.6 mus 07/29/21 Updated Xil_TestMem8 to fix issues reported by static
-* analysis tool. It fixes CR#1105956.
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xil_testmem.h"
-#include "xil_io.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions ****************************/
-/************************** Function Prototypes *****************************/
-
-static u32 RotateLeft(u32 Input, u8 Width);
-
-/* define ROTATE_RIGHT to give access to this functionality */
-/* #define ROTATE_RIGHT */
-#ifdef ROTATE_RIGHT
-static u32 RotateRight(u32 Input, u8 Width);
-#endif /* ROTATE_RIGHT */
-
-#if defined(__MICROBLAZE__) && !defined(__arch64__) && (XPAR_MICROBLAZE_ADDR_SIZE > 32)
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 8-bit wide memory test.
-*
-* @param Addrlow: lower 32 bit address of memory to be tested.
-* @param Addrhigh: upper 32 bit address of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: type of test selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem8(u32 Addrlow, u32 Addrhigh, u32 Words, u8 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u8 Val;
- u8 WordMem8;
- s32 Status = 0;
- u64 Addr = (Addrlow + ((u64)Addrhigh << 32));
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * select the proper Subtest(s)
- */
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from XIL_TESTMEM_INIT_VALUE
- */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- sbea(Addr+I, Val);
- Val++;
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = XIL_TESTMEM_INIT_VALUE;
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference
- * Val
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = lbuea(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val++;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking ones test
- */
-
- for (j = 0U; j < NUM_OF_BITS_IN_BYTE; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
- Val = (u8)((u32)1 << j);
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
- for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) {
- /* write memory location */
- sbea(Addr+I, Val);
- Val = (u8)RotateLeft(Val, 8U);
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u8)((u32)1 << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) {
- /* read memory location */
- WordMem8 = lbuea(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = (u8)RotateLeft(Val, NUM_OF_BITS_IN_BYTE);
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible initial test
- * Patterns for walking zeros test
- */
-
- for (j = 0U; j < NUM_OF_BITS_IN_BYTE; j++) {
- /*
- * Generate an initial value for walking ones test to test
- * for bad data bits
- */
- Val = (u8) (~(1U << j));
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
- for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) {
- /* write memory location */
- sbea(Addr+I, Val);
- Val = ~((u8)RotateLeft(~Val, NUM_OF_BITS_IN_BYTE));
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u8) (~(1U << j));
- /* Read the values from each location that was written */
- for (I = 0U; I < NUM_OF_BITS_IN_BYTE; I++) {
- /* read memory location */
- WordMem8 = lbuea(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val = ~((u8)RotateLeft(~Val, NUM_OF_BITS_IN_BYTE));
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- Val = (u8) (~((INTPTR) (Addr + I)));
- sbea(Addr+I, Val);
- }
-
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = lbuea(Addr+I);
- Val = (u8) (~((INTPTR) (Addr+I)));
- if ((WordMem8 ^ Val) != 0x00U) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
-
- if (Pattern == (u8)0) {
- Val = 0xA5U;
- }
- else {
- Val = Pattern;
- }
- /*
- * Fill the memory with fixed Pattern
- */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- sbea(Addr+I, Val);
- }
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed Pattern
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = lbuea(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
-End_Label:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 16-bit wide memory test.
-*
-* @param Addrlow: lower 32 bit address of memory to be tested.
-* @param Addrhigh: upper 32 bit address of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant Pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: type of test selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem16(u32 Addrlow,u32 Addrhigh, u32 Words, u16 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u16 Val;
- u16 WordMem16;
- s32 Status = 0;
- u64 Addr = (Addrlow + ((u64)Addrhigh << 32));
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * selectthe proper Subtest(s)
- */
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from 'XIL_TESTMEM_INIT_VALUE'
- */
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) {
- /* write memory location */
- shea(Addr+I, Val);
- Val++;
- I = I + NUM_OF_BYTES_IN_HW;
- }
-
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference val
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) {
- /* read memory location */
- WordMem16 = lhuea(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val++;
- I = I + NUM_OF_BYTES_IN_HW;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial test
- * Patterns for walking ones test
- */
-
- for (j = 0U; j < NUM_OF_BITS_IN_HW; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = (u16)((u32)1 << j);
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) {
- /* write memory location */
- shea(Addr+I,Val);
- Val = (u16)RotateLeft(Val, 16U);
- I = I + NUM_OF_BYTES_IN_HW;
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u16)((u32)1 << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) {
- /* read memory location */
- WordMem16 = lhuea(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = (u16)RotateLeft(Val, NUM_OF_BITS_IN_HW);
- I = I + NUM_OF_BYTES_IN_HW;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking zeros test
- */
-
- for (j = 0U; j < NUM_OF_BITS_IN_HW; j++) {
- /*
- * Generate an initial value for walking ones
- * test to test for bad
- * data bits
- */
-
- Val = ~(1U << j);
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW);) {
- shea(Addr+I, Val);
- Val = ~((u16)RotateLeft(~Val, 16U));
- I = I + NUM_OF_BYTES_IN_HW;
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = ~(1U << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * NUM_OF_BITS_IN_HW); ) {
- WordMem16= lhuea(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = ~((u16)RotateLeft(~Val, NUM_OF_BITS_IN_HW));
- I = I + NUM_OF_BYTES_IN_HW;
- }
-
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) {
- /* write memory location */
- Val = (u16) (~((INTPTR)((Addr+I))));
- shea(Addr+I, Val);
- I = I + NUM_OF_BYTES_IN_HW;
- }
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW*Words); ) {
- /* read memory location */
- //WordMem16 = *(Addr+I);
- WordMem16 = lhuea(Addr+I);
- Val = (u16) (~((INTPTR) ((Addr+I))));
- if ((WordMem16 ^ Val) != 0x0000U) {
- Status = -1;
- goto End_Label;
- }
- I = I + NUM_OF_BYTES_IN_HW;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
- if (Pattern == (u16)0) {
- Val = 0xDEADU;
- }
- else {
- Val = Pattern;
- }
-
- /*
- * Fill the memory with fixed pattern
- */
-
- for (I = 0U; I < (2*Words);) {
- /* write memory location */
- shea(Addr+I, Val);
- I = I + NUM_OF_BYTES_IN_HW;
- }
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed pattern
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_HW * Words);) {
- /* read memory location */
- WordMem16=lhuea(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- I = I + NUM_OF_BYTES_IN_HW;
- }
- }
-End_Label:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 32-bit wide memory test.
-*
-* @param Addrlow: lower 32 bit address of memory to be tested.
-* @param Addrhigh: upper 32 bit address of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: test type selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-* - 0 is returned for a pass
-* - 1 is returned for a failure
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem32(u32 Addrlow, u32 Addrhigh, u32 Words, u32 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u32 Val;
- u32 WordMem32;
- s32 Status = 0;
- u64 Addr = (Addrlow + ((u64)Addrhigh << 32));
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
-
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from 'XIL_TESTMEM_INIT_VALUE'
- */
- for (I = 0U; I <(NUM_OF_BYTES_IN_WORD * Words);) {
- swea(Addr+I, Val);
- Val++;
- I = I + NUM_OF_BYTES_IN_WORD;
- }
-
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference
- * Val
- */
-
- for (I = 0U; I < ( NUM_OF_BYTES_IN_WORD * Words);) {
- WordMem32 = lwea(Addr+I);
-
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val++;
- I = I + NUM_OF_BYTES_IN_WORD;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking ones test
- */
-
- for (j = 0U; j < NUM_OF_BITS_IN_WORD; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = (1U << j);
-
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * NUM_OF_BITS_IN_WORD);) {
- /* write memory location */
- swea(Addr+I, Val);
- Val = (u32) RotateLeft(Val, NUM_OF_BITS_IN_WORD);
- I = I + NUM_OF_BYTES_IN_WORD;
- }
-
- /*
- * Restore the reference 'val' to the
- * initial value
- */
- Val = 1U << j;
-
- /* Read the values from each location that was
- * written */
- for (I = 0U; I < ((u32)32 * NUM_OF_BYTES_IN_WORD);) {
- /* read memory location */
-
- WordMem32 = lwea(Addr+I);
-
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val = (u32)RotateLeft(Val, NUM_OF_BITS_IN_WORD);
- I = I + NUM_OF_BYTES_IN_WORD;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible
- * initial test Patterns for walking zeros test
- */
-
- for (j = 0U; j < NUM_OF_BITS_IN_WORD; j++) {
-
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = ~(1U << j);
-
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (NUM_OF_BITS_IN_WORD * NUM_OF_BYTES_IN_WORD);) {
- /* write memory location */
- swea(Addr+I, Val);
- Val = ~((u32)RotateLeft(~Val, NUM_OF_BITS_IN_WORD));
- I = I + NUM_OF_BYTES_IN_WORD;
- }
-
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
-
- Val = ~(1U << j);
-
- /* Read the values from each location that was
- * written */
- for (I = 0U; I < (NUM_OF_BITS_IN_WORD * NUM_OF_BYTES_IN_WORD);) {
- /* read memory location */
- WordMem32 = lwea(Addr+I);
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = ~((u32)RotateLeft(~Val, NUM_OF_BITS_IN_WORD));
- I = I + NUM_OF_BYTES_IN_WORD;
- }
-
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) {
- /* write memory location */
- Val = (u32) (~((INTPTR) (Addr+I)));
- swea(Addr+I, Val);
- I = I + NUM_OF_BYTES_IN_WORD;
- }
-
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) {
- /* Read the location */
- WordMem32 = lwea(Addr+I);
- Val = (u32) (~((INTPTR) (Addr+I)));
-
- if ((WordMem32 ^ Val) != 0x00000000U) {
- Status = -1;
- goto End_Label;
- }
- I = I + NUM_OF_BYTES_IN_WORD;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
-
- if (Pattern == (u32)0) {
- Val = 0xDEADBEEFU;
- }
- else {
- Val = Pattern;
- }
-
- /*
- * Fill the memory with fixed Pattern
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) {
- /* write memory location */
- swea(Addr+I, Val);
- I = I + NUM_OF_BYTES_IN_WORD;
- }
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed Pattern
- */
-
- for (I = 0U; I < (NUM_OF_BYTES_IN_WORD * Words);) {
-
- /* read memory location */
-
- WordMem32 = lwea(Addr+I);
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
- I = I + NUM_OF_BYTES_IN_WORD;
- }
- }
-
-End_Label:
- return Status;
-}
-
-#else
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 32-bit wide memory test.
-*
-* @param Addr: pointer to the region of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: test type selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-* - 0 is returned for a pass
-* - 1 is returned for a failure
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u32 Val;
- u32 FirtVal;
- u32 WordMem32;
- s32 Status = 0;
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
- FirtVal = XIL_TESTMEM_INIT_VALUE;
-
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from 'FirtVal'
- */
- for (I = 0U; I < Words; I++) {
- *(Addr+I) = Val;
- Val++;
- }
-
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = FirtVal;
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference
- * Val
- */
-
- for (I = 0U; I < Words; I++) {
- WordMem32 = *(Addr+I);
-
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val++;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking ones test
- */
-
- for (j = 0U; j < (u32)32; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = (1U << j);
-
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (u32)32; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = (u32) RotateLeft(Val, 32U);
- }
-
- /*
- * Restore the reference 'val' to the
- * initial value
- */
- Val = 1U << j;
-
- /* Read the values from each location that was
- * written */
- for (I = 0U; I < (u32)32; I++) {
- /* read memory location */
-
- WordMem32 = *(Addr+I);
-
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val = (u32)RotateLeft(Val, 32U);
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible
- * initial test Patterns for walking zeros test
- */
-
- for (j = 0U; j < (u32)32; j++) {
-
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = ~(1U << j);
-
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (u32)32; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = ~((u32)RotateLeft(~Val, 32U));
- }
-
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
-
- Val = ~(1U << j);
-
- /* Read the values from each location that was
- * written */
- for (I = 0U; I < (u32)32; I++) {
- /* read memory location */
- WordMem32 = *(Addr+I);
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = ~((u32)RotateLeft(~Val, 32U));
- }
-
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- Val = (u32) (~((INTPTR) (&Addr[I])));
- *(Addr+I) = Val;
- }
-
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < Words; I++) {
- /* Read the location */
- WordMem32 = *(Addr+I);
- Val = (u32) (~((INTPTR) (&Addr[I])));
-
- if ((WordMem32 ^ Val) != 0x00000000U) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
-
- if (Pattern == (u32)0) {
- Val = 0xDEADBEEFU;
- }
- else {
- Val = Pattern;
- }
-
- /*
- * Fill the memory with fixed Pattern
- */
-
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- }
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed Pattern
- */
-
- for (I = 0U; I < Words; I++) {
-
- /* read memory location */
-
- WordMem32 = *(Addr+I);
- if (WordMem32 != Val) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
-End_Label:
- return Status;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 16-bit wide memory test.
-*
-* @param Addr: pointer to the region of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant Pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: type of test selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-* @note Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u16 Val;
- u16 FirtVal;
- u16 WordMem16;
- s32 Status = 0;
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
- FirtVal = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * selectthe proper Subtest(s)
- */
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from 'FirtVal'
- */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val++;
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = FirtVal;
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference val
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val++;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial test
- * Patterns for walking ones test
- */
-
- for (j = 0U; j < (u32)16; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
-
- Val = (u16)((u32)1 << j);
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (u32)16; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = (u16)RotateLeft(Val, 16U);
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u16)((u32)1 << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < (u32)16; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = (u16)RotateLeft(Val, 16U);
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking zeros test
- */
-
- for (j = 0U; j < (u32)16; j++) {
- /*
- * Generate an initial value for walking ones
- * test to test for bad
- * data bits
- */
-
- Val = ~(1U << j);
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
-
- for (I = 0U; I < (u32)16; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = ~((u16)RotateLeft(~Val, 16U));
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = ~(1U << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < (u32)16; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = ~((u16)RotateLeft(~Val, 16U));
- }
-
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- Val = (u16) (~((INTPTR)(&Addr[I])));
- *(Addr+I) = Val;
- }
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- Val = (u16) (~((INTPTR) (&Addr[I])));
- if ((WordMem16 ^ Val) != 0x0000U) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
- if (Pattern == (u16)0) {
- Val = 0xDEADU;
- }
- else {
- Val = Pattern;
- }
-
- /*
- * Fill the memory with fixed pattern
- */
-
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- }
-
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed pattern
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem16 = *(Addr+I);
- if (WordMem16 != Val) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
-End_Label:
- return Status;
-}
-
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform a destructive 8-bit wide memory test.
-*
-* @param Addr: pointer to the region of memory to be tested.
-* @param Words: length of the block.
-* @param Pattern: constant used for the constant pattern test, if 0,
-* 0xDEADBEEF is used.
-* @param Subtest: type of test selected. See xil_testmem.h for possible
-* values.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-* @note
-* Used for spaces where the address range of the region is smaller than
-* the data width. If the memory range is greater than 2 ** Width,
-* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
-* repeat on a boundary of a power of two making it more difficult to detect
-* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
-* tests suffer the same problem. Ideally, if large blocks of memory are to be
-* tested, break them up into smaller regions of memory to allow the test
-* patterns used not to repeat over the region tested.
-*
-*****************************************************************************/
-s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
-{
- u32 I;
- u32 j;
- u8 Val;
- u8 FirtVal;
- u8 WordMem8;
- s32 Status = 0;
-
- Xil_AssertNonvoid(Words != (u32)0);
- Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
-
- /*
- * variable initialization
- */
- Val = XIL_TESTMEM_INIT_VALUE;
- FirtVal = XIL_TESTMEM_INIT_VALUE;
-
- /*
- * select the proper Subtest(s)
- */
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
- /*
- * Fill the memory with incrementing
- * values starting from 'FirtVal'
- */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val++;
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = FirtVal;
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the incrementing reference
- * Val
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val++;
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
- /*
- * set up to cycle through all possible initial
- * test Patterns for walking ones test
- */
-
- for (j = 0U; j < (u32)8; j++) {
- /*
- * Generate an initial value for walking ones test
- * to test for bad data bits
- */
- Val = (u8)((u32)1 << j);
- /*
- * START walking ones test
- * Write a one to each data bit indifferent locations
- */
- for (I = 0U; I < (u32)8; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = (u8)RotateLeft(Val, 8U);
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u8)((u32)1 << j);
- /* Read the values from each location that was written */
- for (I = 0U; I < (u32)8; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- Val = (u8)RotateLeft(Val, 8U);
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
- /*
- * set up to cycle through all possible initial test
- * Patterns for walking zeros test
- */
-
- for (j = 0U; j < (u32)8; j++) {
- /*
- * Generate an initial value for walking ones test to test
- * for bad data bits
- */
- Val = (u8) (~(1U << j));
- /*
- * START walking zeros test
- * Write a one to each data bit indifferent locations
- */
- for (I = 0U; I < (u32)8; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- Val = ~((u8)RotateLeft(~Val, 8U));
- }
- /*
- * Restore the reference 'Val' to the
- * initial value
- */
- Val = (u8) (~(1U << j));
- /* Read the values from each location that was written */
- for (I = 0U; I < (u32)8; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
-
- Val = ~((u8)RotateLeft(~Val, 8U));
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
- /* Fill the memory with inverse of address */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- Val = (u8) (~((INTPTR) (&Addr[I])));
- *(Addr+I) = Val;
- }
-
- /*
- * Check every word within the words
- * of tested memory
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- Val = (u8) (~((INTPTR) (&Addr[I])));
- if ((WordMem8 ^ Val) != 0x00U) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
- if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
- /*
- * Generate an initial value for
- * memory testing
- */
-
- if (Pattern == (u8)0) {
- Val = 0xA5U;
- }
- else {
- Val = Pattern;
- }
- /*
- * Fill the memory with fixed Pattern
- */
- for (I = 0U; I < Words; I++) {
- /* write memory location */
- *(Addr+I) = Val;
- }
- /*
- * Check every word within the words
- * of tested memory and compare it
- * with the fixed Pattern
- */
-
- for (I = 0U; I < Words; I++) {
- /* read memory location */
- WordMem8 = *(Addr+I);
- if (WordMem8 != Val) {
- Status = -1;
- goto End_Label;
- }
- }
- }
-
-End_Label:
- return Status;
-}
-#endif
-
-/*****************************************************************************/
-/**
-*
-* @brief Rotates the provided value to the left one bit position
-*
-* @param Input is value to be rotated to the left
-* @param Width is the number of bits in the input data
-*
-* @return The resulting unsigned long value of the rotate left
-*
-*
-*****************************************************************************/
-static u32 RotateLeft(u32 Input, u8 Width)
-{
- u32 Msb;
- u32 ReturnVal;
- u32 WidthMask;
- u32 MsbMask;
- u32 LocalInput = Input;
-
- /*
- * set up the WidthMask and the MsbMask
- */
-
- MsbMask = 1U << (Width - 1U);
-
- WidthMask = (MsbMask << (u32)1) - (u32)1;
-
- /*
- * set the Width of the Input to the correct width
- */
-
- LocalInput = LocalInput & WidthMask;
-
- Msb = LocalInput & MsbMask;
-
- ReturnVal = LocalInput << 1U;
-
- if (Msb != 0x00000000U) {
- ReturnVal = ReturnVal | (u32)0x00000001;
- }
-
- ReturnVal = ReturnVal & WidthMask;
-
- return ReturnVal;
-
-}
-
-#ifdef ROTATE_RIGHT
-/*****************************************************************************/
-/**
-*
-* @brief Rotates the provided value to the right one bit position
-*
-* @param Input: value to be rotated to the right
-* @param Width: number of bits in the input data
-*
-* @return
-* The resulting u32 value of the rotate right
-*
-*****************************************************************************/
-static u32 RotateRight(u32 Input, u8 Width)
-{
- u32 Lsb;
- u32 ReturnVal;
- u32 WidthMask;
- u32 MsbMask;
- u32 LocalInput = Input;
- /*
- * set up the WidthMask and the MsbMask
- */
-
- MsbMask = 1U << (Width - 1U);
-
- WidthMask = (MsbMask << 1U) - 1U;
-
- /*
- * set the width of the input to the correct width
- */
-
- LocalInput = LocalInput & WidthMask;
-
- ReturnVal = LocalInput >> 1U;
-
- Lsb = LocalInput & 0x00000001U;
-
- if (Lsb != 0x00000000U) {
- ReturnVal = ReturnVal | MsbMask;
- }
-
- ReturnVal = ReturnVal & WidthMask;
-
- return ReturnVal;
-
-}
-#endif /* ROTATE_RIGHT */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f6/1073a7555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f6/1073a7555243001d18b399c1eb9b3628
deleted file mode 100644
index 61bfc0b..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f6/1073a7555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,15 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include "xil_types.h"
-
-sint32 __close(sint32 fd)
-{
- (void)fd;
- return (0);
-
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f6/41907a585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f6/41907a585243001d18b399c1eb9b3628
deleted file mode 100644
index c13b354..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f6/41907a585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,164 +0,0 @@
-/*******************************************************************************
-* Copyright (c) 2018 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-*******************************************************************************/
-
-
-#ifndef __XLPD_XIOU_SECURE_SLCR_H__
-#define __XLPD_XIOU_SECURE_SLCR_H__
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *@cond nocomments
- */
-
-/**
- * XlpdXiouSecureSlcr Base Address
- */
-#define XLPD_XIOU_SECURE_SLCR_BASEADDR 0xFF0A0000UL
-
-/**
- * Register: XlpdXiouSecureSlcrAxiWprtcnGem0
- */
-#define XLPD_XIOU_SECURE_SLCR_AXI_WPRTCN_GEM0 ( ( XLPD_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000000UL )
-#define XLPD_XIOU_SECURE_SLCR_AXI_WPRTCN_GEM0_RSTVAL 0x00000000UL
-
-#define XLPD_XIOU_SECURE_SLCR_AXI_WPRTCN_GEM0_AWPROT_SHIFT 0UL
-#define XLPD_XIOU_SECURE_SLCR_AXI_WPRTCN_GEM0_AWPROT_WIDTH 3UL
-#define XLPD_XIOU_SECURE_SLCR_AXI_WPRTCN_GEM0_AWPROT_MASK 0x00000007UL
-#define XLPD_XIOU_SECURE_SLCR_AXI_WPRTCN_GEM0_AWPROT_DEFVAL 0x0UL
-
-/**
- * Register: XlpdXiouSecureSlcrAxiRprtcnGem0
- */
-#define XLPD_XIOU_SECURE_SLCR_AXI_RPRTCN_GEM0 ( ( XLPD_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000004UL )
-#define XLPD_XIOU_SECURE_SLCR_AXI_RPRTCN_GEM0_RSTVAL 0x00000000UL
-
-#define XLPD_XIOU_SECURE_SLCR_AXI_RPRTCN_GEM0_ARPROT_SHIFT 0UL
-#define XLPD_XIOU_SECURE_SLCR_AXI_RPRTCN_GEM0_ARPROT_WIDTH 3UL
-#define XLPD_XIOU_SECURE_SLCR_AXI_RPRTCN_GEM0_ARPROT_MASK 0x00000007UL
-#define XLPD_XIOU_SECURE_SLCR_AXI_RPRTCN_GEM0_ARPROT_DEFVAL 0x0UL
-
-/**
- * Register: XlpdXiouSecureSlcrAxiWprtcnGem1
- */
-#define XLPD_XIOU_SECURE_SLCR_AXI_WPRTCN_GEM1 ( ( XLPD_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000010UL )
-#define XLPD_XIOU_SECURE_SLCR_AXI_WPRTCN_GEM1_RSTVAL 0x00000000UL
-
-#define XLPD_XIOU_SECURE_SLCR_AXI_WPRTCN_GEM1_AWPROT_SHIFT 0UL
-#define XLPD_XIOU_SECURE_SLCR_AXI_WPRTCN_GEM1_AWPROT_WIDTH 3UL
-#define XLPD_XIOU_SECURE_SLCR_AXI_WPRTCN_GEM1_AWPROT_MASK 0x00000007UL
-#define XLPD_XIOU_SECURE_SLCR_AXI_WPRTCN_GEM1_AWPROT_DEFVAL 0x0UL
-
-/**
- * Register: XlpdXiouSecureSlcrAxiRprtcnGem1
- */
-#define XLPD_XIOU_SECURE_SLCR_AXI_RPRTCN_GEM1 ( ( XLPD_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000014UL )
-#define XLPD_XIOU_SECURE_SLCR_AXI_RPRTCN_GEM1_RSTVAL 0x00000000UL
-
-#define XLPD_XIOU_SECURE_SLCR_AXI_RPRTCN_GEM1_ARPROT_SHIFT 0UL
-#define XLPD_XIOU_SECURE_SLCR_AXI_RPRTCN_GEM1_ARPROT_WIDTH 3UL
-#define XLPD_XIOU_SECURE_SLCR_AXI_RPRTCN_GEM1_ARPROT_MASK 0x00000007UL
-#define XLPD_XIOU_SECURE_SLCR_AXI_RPRTCN_GEM1_ARPROT_DEFVAL 0x0UL
-
-/**
- * Register: XlpdXiouSecureSlcrUsb2Tz
- */
-#define XLPD_XIOU_SECURE_SLCR_USB2_TZ ( ( XLPD_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000020UL )
-#define XLPD_XIOU_SECURE_SLCR_USB2_TZ_RSTVAL 0x00000001UL
-
-#define XLPD_XIOU_SECURE_SLCR_USB2_TZ_0_SHIFT 0UL
-#define XLPD_XIOU_SECURE_SLCR_USB2_TZ_0_WIDTH 1UL
-#define XLPD_XIOU_SECURE_SLCR_USB2_TZ_0_MASK 0x00000001UL
-#define XLPD_XIOU_SECURE_SLCR_USB2_TZ_0_DEFVAL 0x1UL
-
-/**
- * Register: XlpdXiouSecureSlcrCtrl
- */
-#define XLPD_XIOU_SECURE_SLCR_CTRL ( ( XLPD_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000040UL )
-#define XLPD_XIOU_SECURE_SLCR_CTRL_RSTVAL 0x00000000UL
-
-#define XLPD_XIOU_SECURE_SLCR_CTRL_SLVERR_EN_SHIFT 0UL
-#define XLPD_XIOU_SECURE_SLCR_CTRL_SLVERR_EN_WIDTH 1UL
-#define XLPD_XIOU_SECURE_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL
-#define XLPD_XIOU_SECURE_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL
-
-/**
- * Register: XlpdXiouSecureSlcrIsr
- */
-#define XLPD_XIOU_SECURE_SLCR_ISR ( ( XLPD_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000044UL )
-#define XLPD_XIOU_SECURE_SLCR_ISR_RSTVAL 0x00000000UL
-
-#define XLPD_XIOU_SECURE_SLCR_ISR_ADDR_DECODE_ERR_SHIFT 0UL
-#define XLPD_XIOU_SECURE_SLCR_ISR_ADDR_DECODE_ERR_WIDTH 1UL
-#define XLPD_XIOU_SECURE_SLCR_ISR_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XLPD_XIOU_SECURE_SLCR_ISR_ADDR_DECODE_ERR_DEFVAL 0x0UL
-
-/**
- * Register: XlpdXiouSecureSlcrImr
- */
-#define XLPD_XIOU_SECURE_SLCR_IMR ( ( XLPD_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000048UL )
-#define XLPD_XIOU_SECURE_SLCR_IMR_RSTVAL 0x00000001UL
-
-#define XLPD_XIOU_SECURE_SLCR_IMR_ADDR_DECODE_ERR_SHIFT 0UL
-#define XLPD_XIOU_SECURE_SLCR_IMR_ADDR_DECODE_ERR_WIDTH 1UL
-#define XLPD_XIOU_SECURE_SLCR_IMR_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XLPD_XIOU_SECURE_SLCR_IMR_ADDR_DECODE_ERR_DEFVAL 0x1UL
-
-/**
- * Register: XlpdXiouSecureSlcrIer
- */
-#define XLPD_XIOU_SECURE_SLCR_IER ( ( XLPD_XIOU_SECURE_SLCR_BASEADDR ) + 0x0000004CUL )
-#define XLPD_XIOU_SECURE_SLCR_IER_RSTVAL 0x00000000UL
-
-#define XLPD_XIOU_SECURE_SLCR_IER_ADDR_DECODE_ERR_SHIFT 0UL
-#define XLPD_XIOU_SECURE_SLCR_IER_ADDR_DECODE_ERR_WIDTH 1UL
-#define XLPD_XIOU_SECURE_SLCR_IER_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XLPD_XIOU_SECURE_SLCR_IER_ADDR_DECODE_ERR_DEFVAL 0x0UL
-
-/**
- * Register: XlpdXiouSecureSlcrIdr
- */
-#define XLPD_XIOU_SECURE_SLCR_IDR ( ( XLPD_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000050UL )
-#define XLPD_XIOU_SECURE_SLCR_IDR_RSTVAL 0x00000000UL
-
-#define XLPD_XIOU_SECURE_SLCR_IDR_ADDR_DECODE_ERR_SHIFT 0UL
-#define XLPD_XIOU_SECURE_SLCR_IDR_ADDR_DECODE_ERR_WIDTH 1UL
-#define XLPD_XIOU_SECURE_SLCR_IDR_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XLPD_XIOU_SECURE_SLCR_IDR_ADDR_DECODE_ERR_DEFVAL 0x0UL
-
-/**
- * Register: XlpdXiouSecureSlcrItr
- */
-#define XLPD_XIOU_SECURE_SLCR_ITR ( ( XLPD_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000054UL )
-#define XLPD_XIOU_SECURE_SLCR_ITR_RSTVAL 0x00000000UL
-
-#define XLPD_XIOU_SECURE_SLCR_ITR_ADDR_DECODE_ERR_SHIFT 0UL
-#define XLPD_XIOU_SECURE_SLCR_ITR_ADDR_DECODE_ERR_WIDTH 1UL
-#define XLPD_XIOU_SECURE_SLCR_ITR_ADDR_DECODE_ERR_MASK 0x00000001UL
-#define XLPD_XIOU_SECURE_SLCR_ITR_ADDR_DECODE_ERR_DEFVAL 0x0UL
-
-/**
- * Register: XlpdXiouSecureSlcrTzprot
- */
-#define XLPD_XIOU_SECURE_SLCR_TZPROT ( ( XLPD_XIOU_SECURE_SLCR_BASEADDR ) + 0x0000007CUL )
-#define XLPD_XIOU_SECURE_SLCR_TZPROT_RSTVAL 0x00000000UL
-
-#define XLPD_XIOU_SECURE_SLCR_TZPROT_ACT_SHIFT 0UL
-#define XLPD_XIOU_SECURE_SLCR_TZPROT_ACT_WIDTH 1UL
-#define XLPD_XIOU_SECURE_SLCR_TZPROT_ACT_MASK 0x00000001UL
-#define XLPD_XIOU_SECURE_SLCR_TZPROT_ACT_DEFVAL 0x0UL
-
-/**
- *@endcond
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __XLPD_XIOU_SECURE_SLCR_H__ */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f6/51c730565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f6/51c730565243001d18b399c1eb9b3628
deleted file mode 100644
index f9511df..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f6/51c730565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,539 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpm_counter.h
-*
-* @addtogroup r5_event_counter_apis Cortex R5 Event Counters Functions
-*
-* Cortex R5 event counter functions can be utilized to configure and control
-* the Cortex-R5 performance monitor events.
-* Cortex-R5 Performance Monitor has 3 event counters which can be used to
-* count a variety of events described in Coretx-R5 TRM. The xpm_counter.h file
-* defines configurations XPM_CNTRCFGx which can be used to program the event
-* counters to count a set of events.
-*
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.00 pkp 02/10/14 Initial version
-* 7.1 aru 04/15/19 Updated the events correctly
-* 7.2 mus 01/29/20 Added new macro Xpm_ReadCycleCounterVal, to
-* read PMU cycle counter value
-* 7.2 asa 03/18/20 Add prototypes for new APIs. Deprecate older
-* APIs. Add new macros being used in the new APIs.
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XPMCOUNTER_H /* prevent circular inclusions */
-#define XPMCOUNTER_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include
-#include "xpseudo_asm.h"
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/************************** Constant Definitions ****************************/
-
-/* Number of performance counters */
-#define XPM_CTRCOUNT 3U
-
-/* The following constants define the Cortex-R5 Performance Monitor Events */
-
-/*
- * Software increment. The register is incremented only on writes to the
- * Software Increment Register
- */
-#define XPM_EVENT_SOFTINCR 0x00U
-
-/*
- * Instruction cache miss
- * Each Instruction fetch from normal cacheable memory that causes a refill from
- * the level 2 memory system generates this event.Accesses that do not cause a new
- * cache refill, but are satisfied from refilling data of a previous miss are not
- * counted. Where instruction fetches consists of multiple instructions, these
- * accesses count as single events.
- */
-#define XPM_EVENT_INSTRCACHEMISS 0x01
-
-/*
- * Data cache miss
- * Each data read from or write to normal cacheable memory that causes a refill
- * from the level 2 memory system generates this event.Accesses that do not cause
- * a new cache refill, but are satisfied from refilling data of a previous miss are
- * not counted. Each access to a cache line to normal cacheable memory that causes
- * a new linefill is counted,including the multiple transactions of an LDM and STM
- */
-
-#define XPM_EVENT_DATACACHEMISS 0x03
-
-/*
- * Each access to a cache line is counted including the multiple transactions of
- * an LDM, STM, or other operations.
- */
-
-#define XPM_EVENT_DATACACHEACCESS 0x04
-
-/*
- *Data read architecturally executed
- *This evevt occurs for every every instruction that explicitly reads data,
- *including SWP.
- */
-
-#define XPM_EVENT_DATAREAD 0x06
-
-/*
- *Data write architecturally executed
- *This evevt occurs for every every instruction that explicitly writes data,
- *including SWP.
- */
-
-#define XPM_EVENT_DATAWRITE 0x07
-
-/*
- *Instruction architecturally executed
- */
-
-#define XPM_EVENT_INSTR 0x08
-/*
- * Dual-issued pair of instructions architecturally executed
- */
-
-#define XPM_EVENT_DUALINSTR 0x5E
-
-/*
- * Exception taken
- * This event occurs on each exception taken
- */
-
-#define XPM_EVENT_EXCEPTION 0x09
-
-/*
- * Exception return architecturally executed.
- * This event occurs on every exception return
- * for example:
- * RFE,MOVS PC,LDM Rn, {..,PC}^
- */
-
-#define XPM_EVENT_EXCEPTIONRET 0x0A
-
-/*
- * Change to Context ID Executed
- */
-
-#define XPM_EVENT_CHANGETOCONTEXID 0x0B
-
-/*
- * Software Change of PC, except by an exception,
- * architecturally executed
- */
-
-#define XPM_EVENT_SWCHANGE 0x0C
-
-/*
- * B immediate, BL immediate or BLX immediate instruction
- * architecturally executed
- *
- */
-
-#define XPM_EVENT_IMMEDIATEINSTR 0x0D
-
-/*
- * Procedure return architecturally executed, other than exception returns
- * For example:
- * BZ Rm, "LDM Rn, {..,PC}"
- */
-
-#define XPM_EVENT_PROCEDURERET 0x0E
-
-/*
- * Unaligned access architecturally executed
- * This event occurs for each instruction that was to an unaligned
- * address that either triggered an alignment fault, or would have done
- * so if the SCTLR A-bit had been set.
- */
-
-#define XPM_EVENT_UNALIGNACCESS 0x0F
-
-/*
- * Branch mispredicted or not predicted
- * This event ocurs for every pipeline flush
- * caused by a branch
- */
-
-#define XPM_EVENT_BRANCHMISPREDICT 0x10
-
-/*
- * Counts clock cycles when the Cortex-r5 processor is not in WFE/WFI. This
- * event is not exported on the EVENT bus
- */
-
-#define XPM_EVENT_CLOCKCYCLES 0x11U
-
-/*
- * Branches or other change in program flow that could have
- * been predicted by the branch prediction resources of the processor.
- */
-
-#define XPM_EVENT_BRANCHPREDICT 0x12
-
-/*
- * Stall because instruction buffer cannot deliver an instruction
- * This can indicate a cache miss. This event occurs every cycle where
- * the conditions is present.
- */
-
-#define XPM_EVENT_INSTRSTALL 0x40
-
-/*
- * Stall because of data dependency between instructions.
- * This event occurs every cycle where the condition is present.
- */
-
-#define XPM_EVENT_DATASTALL 0x41
-
-/*
- * Data cache write-back
- * This event occurs once for each line that is written back from the cache.
- */
-
-#define XPM_EVENT_DATACACHEWRITE 0x42
-
-/*
- * External memory request
- * Examples of this are cache refill, Non-cacheable accesses, write through
- * writes, cache line evictions(write-back)
- */
-
-#define XPM_EVENT_EXTERNALMEMREQ 0x43U
-
-/*
- * Stall because of LSU being busy
- * This event takes place each clock cycle where the condition is met.
- * A high incidence of this event indicates the pipeline is often waiting
- * for transactions to complete on the external bus.
- */
-
-#define XPM_EVENT_LSUSTALL 0x44
-
-/*
- * Store Buffer was forced to drain completely
- * Examples of this Fir cortex-R5 are DMB, Strongly ordered memory access,
- * or similar events.
- *
- */
-
-#define XPM_EVENT_FORCEDRAINSTORE 0x45
-
-/*
- * Instruction cache tag RAm parity or correctable ECC error
- */
-
-#define XPM_EVENT_INSTRTAGPARITY 0x4A
-
-/*
- * Instruction cache data RAm parity or correctable ECC error
- */
-
-#define XPM_EVENT_INSTRDATAPARITY 0x4B
-
-/*
- * Data cache tag or dirty RAM parity error or correctable ECC error,
- * from data-side or ACP
- */
-
-#define XPM_EVENT_DATATAGPARITY 0x4C
-
-/*
- * Data cache data RAM parity error or correctable ECC error
- */
-
-#define XPM_EVENT_DATADATAPARITY 0x4D
-
-/*
- * TCM fatal ECC error reported from the prefetch unit
- */
-
-#define XPM_EVENT_TCMERRORPREFETCH 0x4E
-
-/*
- * TCM fatal ECC error reported from the load/store unit
- */
-
-#define XPM_EVENT_TCMERRORSTORE 0x4F
-
-/*
- * Instruction cache access
- */
-
-#define XPM_EVENT_INSTRCACHEACCESS 0x58
-
-/*
- * Dual issue case A(branch)
- */
-
-#define XPM_EVENT_DUALISSUEA 0x5A
-
-/*
- * Dual issue case B1,B2,F2(load/store), F2D.
- */
-
-#define XPM_EVENT_DUALISSUEB 0x5B
-
-/*
- * Dual issue other case
- */
-
-#define XPM_EVENT_DUALISSUEOTHER 0x5C
-
-/*
- * Double precision floating point arithmetic or
- * conversion instruction executed.
- */
-
-#define XPM_EVENT_FPA 0x5D
-
-/*
- * Data cache data RAM fatal ECC error
- */
-
-#define XPM_EVENT_DATACACHEDATAERROR 0x60
-
-/*
- * Data cache tag/dirty RAM fatal ECC error, from data-side or ACP
- */
-
-#define XPM_EVENT_DATACACHETAGERROR 0x61
-
-/*
- * Processor livelock because of hard errors or exception vector
- */
-
-#define XPM_EVENT_PROCESSORLIVELOCK 0x62
-
-/*
- * ATCM Multi-bit error
- */
-
-#define XPM_EVENT_ATCMMULTIBITERROR 0x64
-
-/*
- * B0TCM Multi-bit error
- */
-
-#define XPM_EVENT_B0TCMMULTIBITERROR 0x65
-
-/*
- * B1TCM Multi-bit error
- */
-
-#define XPM_EVENT_B1TCMMULTIBITERROR 0x66
-
-/*
- * ATCM Single-bit error
- */
-
-#define XPM_EVENT_ATCMSINGLEBITERROR 0x67
-
-/*
- * B0TCM Single-bit error
- */
-
-#define XPM_EVENT_B0TCMSINGLEBITERROR 0x68
-
-/*
- * B1TCM Single-bit error
- */
-
-#define XPM_EVENT_B1TCMSINGLEBITERROR 0x69
-
-/*
- * TCM correctable ECC error reported by load/store unit
- */
-
-#define XPM_EVENT_TCMERRORLSU 0x6A
-
-/*
- * TCM correctable ECC error reported by prefetch unit
- */
-
-#define XPM_EVENT_TCMERRORPFU 0x6B
-
-/*
- * TCM fatal ECC error reported by AXI slave unit
- */
-
-#define XPM_EVENT_TCMFATALERRORAXI 0x6C
-
-/*
- * TCM correctable ECC error reported by AXI slave unit
- */
-
-#define XPM_EVENT_TCMERRORAXI 0x6D
-
-/*
- * ACP D-cache access, lookup or invalidate
- */
-
-
-#define XPM_EVENT_DCACHEACCESS 0x72
-
-/*
- * ACP D-cache invalidate
- */
-
-#define XPM_EVENT_DCACHEINVALIDATE 0x73
-
-
-/*
- * The following constants define the configurations for Cortex-R5 Performance
- * Monitor Events. Each configuration configures the event counters for a set
- * of events.
- * -----------------------------------------------
- * Config PmCtr0... PmCtr5
- * -----------------------------------------------
- * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR,
- * XPM_EVENT_INSTRCACHEMISS,
- * XPM_EVENT_DATACACHEMISS }
- *
- * XPM_CNTRCFG2 { XPM_EVENT_DATACACHEACCESS,
- * XPM_EVENT_DATAREAD,
- * XPM_EVENT_DATAWRITE }
- *
- * XPM_CNTRCFG3 { XPM_EVENT_INSTR,
- * XPM_EVENT_DUALINSTR,
- * XPM_EVENT_EXCEPTION }
- *
- * XPM_CNTRCFG4 { XPM_EVENT_EXCEPTIONRET,
- * XPM_EVENT_CHANGETOCONTEXID,
- * XPM_EVENT_SWCHANGE }
- *
- * XPM_CNTRCFG5 { XPM_EVENT_IMMEDIATEINSTR,
- * XPM_EVENT_PROCEDURERET,
- * XPM_EVENT_UNALIGNACCESS }
- *
- * XPM_CNTRCFG6 { XPM_EVENT_BRANCHMISPREDICT,
- * XPM_EVENT_CLOCKCYCLES,
- * XPM_EVENT_BRANCHPREDICT }
- *
- * XPM_CNTRCFG7 { XPM_EVENT_INSTRSTALL,
- * XPM_EVENT_DATASTALL,
- * XPM_EVENT_DATACACHEWRITE }
- *
- * XPM_CNTRCFG8 { XPM_EVENT_EXTERNALMEMREQ,
- * XPM_EVENT_LSUSTALL,
- * XPM_EVENT_FORCEDRAINSTORE }
- *
- * XPM_CNTRCFG9 { XPM_EVENT_INSTRTAGPARITY,
- * XPM_EVENT_INSTRDATAPARITY,
- * XPM_EVENT_DATATAGPARITY }
- *
- * XPM_CNTRCFG10 { XPM_EVENT_DATADATAPARITY,
- * XPM_EVENT_TCMERRORPREFETCH,
- * XPM_EVENT_TCMERRORSTORE }
- *
- * XPM_CNTRCFG11 { XPM_EVENT_INSTRCACHEACCESS,
- * XPM_EVENT_DUALISSUEA,
- * XPM_EVENT_DUALISSUEB }
- *
- * XPM_CNTRCFG12 { XPM_EVENT_DUALISSUEOTHER,
- * XPM_EVENT_FPA,
- * XPM_EVENT_DATACACHEDATAERROR }
- *
- * XPM_CNTRCFG13 { XPM_EVENT_DATACACHETAGERROR,
- * XPM_EVENT_PROCESSORLIVELOCK,
- * XPM_EVENT_ATCMMULTIBITERROR }
- *
- * XPM_CNTRCFG14 { XPM_EVENT_B0TCMMULTIBITERROR,
- * XPM_EVENT_B1TCMMULTIBITERROR,
- * XPM_EVENT_ATCMSINGLEBITERROR }
- *
- * XPM_CNTRCFG15 { XPM_EVENT_B0TCMSINGLEBITERROR,
- * XPM_EVENT_B1TCMSINGLEBITERROR,
- * XPM_EVENT_TCMERRORLSU }
- *
- * XPM_CNTRCFG16 { XPM_EVENT_TCMERRORPFU,
- * XPM_EVENT_TCMFATALERRORAXI,
- * XPM_EVENT_TCMERRORAXI }
- */
-#define XPM_CNTRCFG1 0
-#define XPM_CNTRCFG2 1
-#define XPM_CNTRCFG3 2
-#define XPM_CNTRCFG4 3
-#define XPM_CNTRCFG5 4
-#define XPM_CNTRCFG6 5
-#define XPM_CNTRCFG7 6
-#define XPM_CNTRCFG8 7
-#define XPM_CNTRCFG9 8
-#define XPM_CNTRCFG10 9
-#define XPM_CNTRCFG11 10
-#define XPM_CNTRCFG12 11
-#define XPM_CNTRCFG13 12
-#define XPM_CNTRCFG14 13
-#define XPM_CNTRCFG15 14
-#define XPM_CNTRCFG16 15
-#endif
-
-#define XPM_NO_COUNTERS_AVAILABLE 0xFFU
-#define XPM_MAX_EVENTHANDLER_ID 0x2U
-#define XPM_EVENT_CNTRS_BIT_MASK 0x7U
-#define XPM_ALL_EVENT_CNTRS_IN_USE 0x7U
-#define XPM_EVENT_CNTRS_MASK 0x3U
-
-/**************************** Type Definitions ******************************/
-/**
- *@endcond
- */
-/***************** Macros (Inline Functions) Definitions ********************/
-#if defined(__GNUC__)
-#define Xpm_ReadCycleCounterVal() mfcp(XREG_CP15_PERF_CYCLE_COUNTER)
-#elif defined (__ICCARM__)
-#define Xpm_ReadCycleCounterVal(val) mfcp(XREG_CP15_PERF_CYCLE_COUNTER,val)
-#endif
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-/* Interface functions to access performance counters from abstraction layer */
-#if defined(__GNUC__)
-void Xpm_SetEvents(s32 PmcrCfg) __attribute__ ((deprecated));
-void Xpm_GetEventCounters(u32 *PmCtrValue) __attribute__ ((deprecated));
-#else
-void Xpm_SetEvents(s32 PmcrCfg);
-void Xpm_GetEventCounters(u32 *PmCtrValue);
-#endif
-u32 Xpm_DisableEvent(u32 EventHandlerId);
-u32 Xpm_SetUpAnEvent(u32 EventID);
-u32 Xpm_GetEventCounter(u32 EventHandlerId, u32 *CntVal);
-void Xpm_DisableEventCounters(void);
-void Xpm_EnableEventCounters (void);
-void Xpm_ResetEventCounters (void);
-
-/* This is helper function for sleep/usleep APIs */
-void Xpm_SleepPerfCounter(u32 delay, u64 frequency);
-
-#ifdef __cplusplus
-}
-#endif
-
-/**
-* @} End of "addtogroup r5_event_counter_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f6/e08fca595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f6/e08fca595243001d18b399c1eb9b3628
deleted file mode 100644
index c19c95a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f6/e08fca595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,154 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xuartps_hw.c
-* @addtogroup uartps_v3_11
-* @{
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------ -------- ----------------------------------------------
-* 1.00 drg/jz 01/12/10 First Release
-* 1.05a hk 08/22/13 Added reset function
-* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-#include "xuartps_hw.h"
-
-/************************** Constant Definitions ****************************/
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Function Prototypes ******************************/
-
-
-/************************** Variable Definitions *****************************/
-
-/****************************************************************************/
-/**
-*
-* This function sends one byte using the device. This function operates in
-* polled mode and blocks until the data has been put into the TX FIFO register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param Data contains the byte to be sent.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartPs_SendByte(u32 BaseAddress, u8 Data)
-{
- /* Wait until there is space in TX FIFO */
- while (XUartPs_IsTransmitFull(BaseAddress)) {
- ;
- }
-
- /* Write the byte into the TX FIFO */
- XUartPs_WriteReg(BaseAddress, XUARTPS_FIFO_OFFSET, (u32)Data);
-}
-
-/****************************************************************************/
-/**
-*
-* This function receives a byte from the device. It operates in polled mode
-* and blocks until a byte has received.
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return The data byte received.
-*
-* @note None.
-*
-*****************************************************************************/
-u8 XUartPs_RecvByte(u32 BaseAddress)
-{
- u32 RecievedByte;
- /* Wait until there is data */
- while (!XUartPs_IsReceiveData(BaseAddress)) {
- ;
- }
- RecievedByte = XUartPs_ReadReg(BaseAddress, XUARTPS_FIFO_OFFSET);
- /* Return the byte received */
- return (u8)RecievedByte;
-}
-
-/****************************************************************************/
-/**
-*
-* This function resets UART
-*
-* @param BaseAddress contains the base address of the device.
-*
-* @return None
-*
-* @note None.
-*
-*****************************************************************************/
-void XUartPs_ResetHw(u32 BaseAddress)
-{
-
- /* Disable interrupts */
- XUartPs_WriteReg(BaseAddress, XUARTPS_IDR_OFFSET, XUARTPS_IXR_MASK);
-
- /* Disable receive and transmit */
- XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
- ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS));
-
- /*
- * Software reset of receive and transmit
- * This clears the FIFO.
- */
- XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
- ((u32)XUARTPS_CR_TXRST | (u32)XUARTPS_CR_RXRST));
-
- /* Clear status flags - SW reset wont clear sticky flags. */
- XUartPs_WriteReg(BaseAddress, XUARTPS_ISR_OFFSET, XUARTPS_IXR_MASK);
-
- /*
- * Mode register reset value : All zeroes
- * Normal mode, even parity, 1 stop bit
- */
- XUartPs_WriteReg(BaseAddress, XUARTPS_MR_OFFSET,
- XUARTPS_MR_CHMODE_NORM);
-
- /* Rx and TX trigger register reset values */
- XUartPs_WriteReg(BaseAddress, XUARTPS_RXWM_OFFSET,
- XUARTPS_RXWM_RESET_VAL);
- XUartPs_WriteReg(BaseAddress, XUARTPS_TXWM_OFFSET,
- XUARTPS_TXWM_RESET_VAL);
-
- /* Rx timeout disabled by default */
- XUartPs_WriteReg(BaseAddress, XUARTPS_RXTOUT_OFFSET,
- XUARTPS_RXTOUT_DISABLE);
-
- /* Baud rate generator and dividor reset values */
- XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDGEN_OFFSET,
- XUARTPS_BAUDGEN_RESET_VAL);
- XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDDIV_OFFSET,
- XUARTPS_BAUDDIV_RESET_VAL);
-
- /*
- * Control register reset value -
- * RX and TX are disable by default
- */
- XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
- ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS |
- (u32)XUARTPS_CR_STOPBRK));
-
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f6/e09f0f555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f6/e09f0f555243001d18b399c1eb9b3628
deleted file mode 100644
index 2b5b4fd..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f6/e09f0f555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,323 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xparameters_ps.h
-*
-* This file contains the address definitions for the hard peripherals
-* attached to the ARM Cortex A53 core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 6.0 mus 18/08/16 Defined ARMA53_32 flag
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 6.0 mus 27/07/16 Added Undefined exception handler
-* 6.4 mus 25/07/17 Added support for hard floating point
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-
-.org 0
-.text
-
-.globl _boot
-.globl _vector_table
-
-.globl FIQInterrupt
-.globl IRQInterrupt
-.globl SWInterrupt
-.globl DataAbortInterrupt
-.globl PrefetchAbortInterrupt
-
-.globl IRQHandler
-.globl prof_pc
-
-.section .vectors, "a"
-_vector_table:
- B _boot
- B Undefined
- B SVCHandler
- B PrefetchAbortHandler
- B DataAbortHandler
- NOP /* Placeholder for address exception vector*/
- B IRQHandler
- B FIQHandler
-
-
-IRQHandler: /* IRQ vector handler */
-
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/
- vpush {d0-d7}
- vpush {d16-d31}
- vmrs r1, FPSCR
- push {r1}
- vmrs r1, FPEXC
- push {r1}
-
- bl IRQInterrupt /* IRQ vector */
- pop {r1}
- vmsr FPEXC, r1
- pop {r1}
- vmsr FPSCR, r1
- vpop {d16-d31}
- vpop {d0-d7}
-
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
-
- subs pc, lr, #4 /* adjust return */
-
-
-FIQHandler: /* FIQ vector handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
-
- vpush {d0-d7}
- vpush {d16-d31}
- vmrs r1, FPSCR
- push {r1}
- vmrs r1, FPEXC
- push {r1}
-FIQLoop:
- bl FIQInterrupt /* FIQ vector */
-
- pop {r1}
- vmsr FPEXC, r1
- pop {r1}
- vmsr FPSCR, r1
- vpop {d16-d31}
- vpop {d0-d7}
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
- subs pc, lr, #4 /* adjust return */
-
-
-Undefined: /* Undefined handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- ldr r0, =UndefinedExceptionAddr
- sub r1, lr, #4
- str r1, [r0] /* Store address of instruction causing undefined exception */
-
- bl UndefinedException /* UndefinedException: call C function here */
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
- movs pc, lr
-
-
-SVCHandler: /* SWI handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
-
- tst r0, #0x20 /* check the T bit */
- ldrneh r0, [lr,#-2] /* Thumb mode */
- bicne r0, r0, #0xff00 /* Thumb mode */
- ldreq r0, [lr,#-4] /* ARM mode */
- biceq r0, r0, #0xff000000 /* ARM mode */
-
- bl SWInterrupt /* SWInterrupt: call C function here */
-
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
- movs pc, lr /*return to the next instruction after the SWI instruction */
-
-
-DataAbortHandler: /* Data Abort handler */
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- ldr r0, =DataAbortAddr
- sub r1, lr, #8
- str r1, [r0] /* Stores instruction causing data abort */
- bl DataAbortInterrupt /*DataAbortInterrupt :call C function here */
-
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
- subs pc, lr, #8 /* points to the instruction that caused the Data Abort exception */
-
-PrefetchAbortHandler: /* Prefetch Abort handler */
-
- stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
- ldr r0, =PrefetchAbortAddr
- sub r1, lr, #4
- str r1, [r0] /* Stores instruction causing prefetch abort */
-
- bl PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */
-
- ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */
-
- subs pc, lr, #4 /* points to the instruction that caused the Prefetch Abort exception */
-
-
-.end
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f8/b025e9575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f8/b025e9575243001d18b399c1eb9b3628
deleted file mode 100644
index 7ea2129..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f8/b025e9575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,138 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xgpio_extra.c
-* @addtogroup gpio_v4_8
-* @{
-*
-* The implementation of the XGpio driver's advanced discrete functions.
-* See xgpio.h for more information about the driver.
-*
-* @note
-*
-* These APIs can only be used if the GPIO_IO ports in the IP are used for
-* connecting to the external output ports.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 02/04/02 First release
-* 2.00a jhl 12/16/02 Update for dual channel and interrupt support
-* 2.11a mta 03/21/07 Updated to new coding style
-* 3.00a sv 11/21/09 Updated to use HAL Processor APIs. Renamed the macros
-* XGpio_mWriteReg to XGpio_WriteReg, and XGpio_mReadReg
-* to XGpio_ReadReg.
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xgpio.h"
-#include "xgpio_i.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-
-/****************************************************************************/
-/**
-* Set output discrete(s) to logic 1 for the specified GPIO channel.
-*
-* @param InstancePtr is a pointer to an XGpio instance to be worked on.
-* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
-* @param Mask is the set of bits that will be set to 1 in the discrete
-* data register. All other bits in the data register are
-* unaffected.
-*
-* @return None.
-*
-* @note
-*
-* The hardware must be built for dual channels if this function is used
-* with any channel other than 1. If it is not, this function will assert.
-*
-* This API can only be used if the GPIO_IO ports in the IP are used for
-* connecting to the external output ports.
-*
-*****************************************************************************/
-void XGpio_DiscreteSet(XGpio * InstancePtr, unsigned Channel, u32 Mask)
-{
- u32 Current;
- unsigned DataOffset;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((Channel == 1) ||
- ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
-
- /* Calculate the offset to the data register of the GPIO */
- DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET;
-
- /*
- * Read the contents of the data register, merge in Mask and write
- * back results
- */
- Current = XGpio_ReadReg(InstancePtr->BaseAddress, DataOffset);
- Current |= Mask;
- XGpio_WriteReg(InstancePtr->BaseAddress, DataOffset, Current);
-}
-
-
-/****************************************************************************/
-/**
-* Set output discrete(s) to logic 0 for the specified GPIO channel.
-*
-* @param InstancePtr is a pointer to an XGpio instance to be worked on.
-* @param Channel contains the channel of the GPIO (1 or 2) to operate on.
-* @param Mask is the set of bits that will be set to 0 in the discrete
-* data register. All other bits in the data register are
-* unaffected.
-*
-* @return None.
-*
-* @note
-*
-* The hardware must be built for dual channels if this function is used
-* with any channel other than 1. If it is not, this function will assert.
-*
-* This API can only be used if the GPIO_IO ports in the IP are used for
-* connecting to the external output ports.
-*
-*****************************************************************************/
-void XGpio_DiscreteClear(XGpio * InstancePtr, unsigned Channel, u32 Mask)
-{
- u32 Current;
- unsigned DataOffset;
-
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
- Xil_AssertVoid((Channel == 1) ||
- ((Channel == 2) && (InstancePtr->IsDual == TRUE)));
-
- /* Calculate the offset to the data register of the GPIO */
- DataOffset = ((Channel - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET;
-
- /*
- * Read the contents of the data register, merge in Mask and write
- * back results
- */
- Current = XGpio_ReadReg(InstancePtr->BaseAddress, DataOffset);
- Current &= ~Mask;
- XGpio_WriteReg(InstancePtr->BaseAddress, DataOffset, Current);
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f8/d24ff5565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f8/d24ff5565243001d18b399c1eb9b3628
deleted file mode 100644
index b3cd2ea..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f8/d24ff5565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,113 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2014 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xplatform_info.h
-*
-*
-* @addtogroup common_platform_info APIs to Get Platform Information
-*
-*
-* The xplatform_info.h file contains definitions for various available Xilinx®
-* platforms. Also, it contains prototype of APIs, which can be used to get the
-* platform information.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- --------- -------------------------------------------------------
-* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
-* function for PMUFW.
-* 7.2 adk 08/01/20 Added versal support for the XGetPSVersion_Info function.
-* 7.6 mus 08/23/21 Updated prototypes for functions which are not taking any
-* arguments with void keyword. This has been done to fix
-* compilation warnings with "-Wstrict-prototypes" flag.
-* It fixes CR#1108601.
-* 7.6 mus 08/30/21 Updated flag checking to fix compilation warnings
-* reported with "-Wundef" flag.
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */
-#define XPLATFORM_INFO_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-
-/************************** Constant Definitions *****************************/
-#if defined (versal)
-#define XPAR_PMC_TAP_BASEADDR 0xF11A0000U
-#define XPAR_PMC_TAP_VERSION_OFFSET 0x00000004U
-#define XPLAT_PS_VERSION_ADDRESS (XPAR_PMC_TAP_BASEADDR + \
- XPAR_PMC_TAP_VERSION_OFFSET)
-#else
-#define XPAR_CSU_BASEADDR 0xFFCA0000U
-#define XPAR_CSU_VER_OFFSET 0x00000044U
-#define XPLAT_PS_VERSION_ADDRESS (XPAR_CSU_BASEADDR + \
- XPAR_CSU_VER_OFFSET)
-#endif
-#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
-#define XPLAT_ZYNQ_ULTRA_MP 0x1
-#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
-#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
-#define XPLAT_ZYNQ 0x4
-#define XPLAT_MICROBLAZE 0x5
-#define XPLAT_VERSAL 0x6U
-
-#define XPS_VERSION_1 0x0
-#define XPS_VERSION_2 0x1
-#define XPLAT_INFO_MASK (0xF)
-
-#if defined (versal)
-#define XPS_VERSION_INFO_MASK 0xFF00U
-#define XPS_VERSION_INFO_SHIFT 0x8U
-#define XPLAT_INFO_SHIFT 0x18U
-#else
-#define XPS_VERSION_INFO_MASK (0xF)
-#define XPS_VERSION_INFO_SHIFT 0x0U
-#define XPLAT_INFO_SHIFT 0xCU
-#endif
-
-/**************************** Type Definitions *******************************/
-/**
- *@endcond
- */
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-u32 XGetPlatform_Info(void);
-
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU) || defined (versal)
-u32 XGetPSVersion_Info(void);
-#endif
-
-#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
-u32 XGet_Zynq_UltraMp_Platform_info(void);
-#endif
-/************************** Function Prototypes ******************************/
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/**
-* @} End of "addtogroup common_platform_info".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f8/e005f3565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f8/e005f3565243001d18b399c1eb9b3628
deleted file mode 100644
index 379023c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f8/e005f3565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,154 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xl2cc.h
-*
-* This file contains the address definitions for the PL310 Level-2 Cache
-* Controller.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 1.00a sdm 02/01/10 Initial version
-* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
-* 'xil_errata.h' for errata description
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef _XL2CC_H_
-#define _XL2CC_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions *****************************/
-/* L2CC Register Offsets */
-#define XPS_L2CC_ID_OFFSET 0x0000U
-#define XPS_L2CC_TYPE_OFFSET 0x0004U
-#define XPS_L2CC_CNTRL_OFFSET 0x0100U
-#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104U
-#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108U
-#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010CU
-
-#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200U
-#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204U
-#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208U
-#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020CU
-#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210U
-
-#define XPS_L2CC_IER_OFFSET 0x0214U /* Interrupt Mask */
-#define XPS_L2CC_IPR_OFFSET 0x0218U /* Masked interrupt status */
-#define XPS_L2CC_ISR_OFFSET 0x021CU /* Raw Interrupt Status */
-#define XPS_L2CC_IAR_OFFSET 0x0220U /* Interrupt Clear */
-
-#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730U /* Cache Sync */
-#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740U /* Dummy Register for Cache Sync */
-#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770U /* Cache Invalid by PA */
-#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077CU /* Cache Invalid by Way */
-#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0U /* Cache Clean by PA */
-#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8U /* Cache Clean by Index */
-#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BCU /* Cache Clean by Way */
-#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0U /* Cache Invalidate and Clean by PA */
-#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8U /* Cache Invalidate and Clean by Index */
-#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FCU /* Cache Invalidate and Clean by Way */
-
-#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900U /* Cache Data Lockdown 0 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904U /* Cache Instruction Lockdown 0 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908U /* Cache Data Lockdown 1 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090CU /* Cache Instruction Lockdown 1 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910U /* Cache Data Lockdown 2 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914U /* Cache Instruction Lockdown 2 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918U /* Cache Data Lockdown 3 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091CU /* Cache Instruction Lockdown 3 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920U /* Cache Data Lockdown 4 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924U /* Cache Instruction Lockdown 4 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928U /* Cache Data Lockdown 5 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092CU /* Cache Instruction Lockdown 5 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930U /* Cache Data Lockdown 6 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934U /* Cache Instruction Lockdown 6 by Way */
-#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938U /* Cache Data Lockdown 7 by Way */
-#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093CU /* Cache Instruction Lockdown 7 by Way */
-
-#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U /* Cache Lockdown Line Enable */
-#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954U /* Cache Unlock All Lines by Way */
-
-#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00U /* Start of address filtering */
-#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04U /* Start of address filtering */
-
-#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40U /* Debug Control Register */
-
-/* XPS_L2CC_CNTRL_OFFSET bit masks */
-#define XPS_L2CC_ENABLE_MASK 0x00000001U /* enables the L2CC */
-
-/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */
-#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000U /* Early BRESP Enable */
-#define XPS_L2CC_AUX_IPFE_MASK 0x20000000U /* Instruction Prefetch Enable */
-#define XPS_L2CC_AUX_DPFE_MASK 0x10000000U /* Data Prefetch Enable */
-#define XPS_L2CC_AUX_NSIC_MASK 0x08000000U /* Non-secure interrupt access control */
-#define XPS_L2CC_AUX_NSLE_MASK 0x04000000U /* Non-secure lockdown enable */
-#define XPS_L2CC_AUX_CRP_MASK 0x02000000U /* Cache replacement policy */
-#define XPS_L2CC_AUX_FWE_MASK 0x01800000U /* Force write allocate */
-#define XPS_L2CC_AUX_SAOE_MASK 0x00400000U /* Shared attribute override enable */
-#define XPS_L2CC_AUX_PE_MASK 0x00200000U /* Parity enable */
-#define XPS_L2CC_AUX_EMBE_MASK 0x00100000U /* Event monitor bus enable */
-#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000U /* Way-size */
-#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000U /* Associativity */
-#define XPS_L2CC_AUX_SAIE_MASK 0x00002000U /* Shared attribute invalidate enable */
-#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000U /* Exclusive cache configuration */
-#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800U /* Store buffer device limitation Enable */
-#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400U /* High Priority for SO and Dev Reads Enable */
-#define XPS_L2CC_AUX_FLZE_MASK 0x00000001U /* Full line of zero enable */
-
-#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000U /* Enable all prefetching, */
- /* Cache replacement policy, Parity enable, */
- /* Event monitor bus enable and Way Size (64 KB) */
-#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFFU /* */
-
-#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111U /* latency for TAG RAM */
-#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121U /* latency for DATA RAM */
-
-/* Interrupt bit masks */
-#define XPS_L2CC_IXR_DECERR_MASK 0x00000100U /* DECERR from L3 */
-#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080U /* SLVERR from L3 */
-#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040U /* Error on L2 data RAM (Read) */
-#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020U /* Error on L2 tag RAM (Read) */
-#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010U /* Error on L2 data RAM (Write) */
-#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008U /* Error on L2 tag RAM (Write) */
-#define XPS_L2CC_IXR_PARRD_MASK 0x00000004U /* Parity Error on L2 data RAM (Read) */
-#define XPS_L2CC_IXR_PARRT_MASK 0x00000002U /* Parity Error on L2 tag RAM (Read) */
-#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001U /* Event Counter1/0 Overflow Increment */
-
-/* Address filtering mask and enable bit */
-#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000U /* Address filtering valid bits*/
-#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U /* Address filtering enable bit*/
-
-/* Debug control bits */
-#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004U /* Debug SPIDEN bit */
-#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002U /* Debug DWB bit, forces write through */
-#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002U /* Debug DCL bit, disables cache line fill */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* protection macro */
-
-/**
- *@endcond
- */
\ No newline at end of file
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f9/20b55e565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f9/20b55e565243001d18b399c1eb9b3628
deleted file mode 100644
index 60f4ba3..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f9/20b55e565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,53 +0,0 @@
-/******************************************************************************
-* Copyright (c) 1995 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-*******************************************************************************/
- #ifndef XIL_PRINTF_H
- #define XIL_PRINTF_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include
-#include
-#include
-#include "xil_types.h"
-#include "xparameters.h"
-#include "bspconfig.h"
-#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
-#include "xen_console.h"
-#endif
-
-/*----------------------------------------------------*/
-/* Use the following parameter passing structure to */
-/* make xil_printf re-entrant. */
-/*----------------------------------------------------*/
-
-struct params_s;
-
-
-/*---------------------------------------------------*/
-/* The purpose of this routine is to output data the */
-/* same as the standard printf function without the */
-/* overhead most run-time libraries involve. Usually */
-/* the printf brings in many kilobytes of code and */
-/* that is unacceptable in most embedded systems. */
-/*---------------------------------------------------*/
-
-typedef char8* charptr;
-typedef s32 (*func_ptr)(int c);
-
-/* */
-
-void xil_printf( const char8 *ctrl1, ...);
-void xil_vprintf(const char8 *ctrl1, va_list argp);
-void print( const char8 *ptr);
-extern void outbyte (char8 c);
-extern char8 inbyte(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f9/21a5a8585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f9/21a5a8585243001d18b399c1eb9b3628
deleted file mode 100644
index d7fff05..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f9/21a5a8585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,18 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-#include
-
-/*
- * clock -- It supposed to return processor time. We are not implementing
- * this function, as timekeeping is tightly coupled with system, hence
- * always returning 0. Users can override this with their system
- * specific implementation.
- *
- */
-__attribute__((weak)) clock_t clock(void)
-{
- return (0);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f9/706cfc515243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f9/706cfc515243001d18b399c1eb9b3628
deleted file mode 100644
index 73816fb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f9/706cfc515243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,6 +0,0 @@
-make --dry-run --always-make --keep-going --print-directory
-make: Entering directory '/home/dylan/workspace/phased_array'
-make: Leaving directory '/home/dylan/workspace/phased_array'
-
-make: *** No targets specified and no makefile found. Stop.
-
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f9/900940565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f9/900940565243001d18b399c1eb9b3628
deleted file mode 100644
index 50df3c5..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f9/900940565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,128 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_clocking.c
-*
-* The xil_clocking.c file contains clocking related functions and macros.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 7.2 sd 02/06/20 First release of clocking
-* 7.2 sd 03/20/20 Added checking for isolation case
-*
-*
-******************************************************************************/
-
-#include "xil_clocking.h"
-/************************** Variable Definitions *****************************/
-
-#if defined (XPAR_XCRPSU_0_DEVICE_ID) && defined (XCLOCKING)
-
-XClock ClockInstance; /* Instance of clock Controller */
-XClockPs_Config *ConfigPtr;
-
-
-XStatus Xil_ClockInit(void)
-{
- XStatus Status = XST_FAILURE;
-
- /* Lookup clock configurations */
- ConfigPtr = XClock_LookupConfig(XPAR_XCLOCKPS_DEVICE_ID);
-
- /* Initialize the Clock controller driver */
- Status = XClock_CfgInitialize(&ClockInstance, ConfigPtr);
- return Status;
-}
-
-XStatus Xil_ClockEnable(XClock_OutputClks ClockId)
-{
-
- XStatus Status = XST_FAILURE;
-
- Status = XClock_EnableClock(ClockId);
- return Status;
-}
-
-XStatus Xil_ClockDisable(XClock_OutputClks ClockId)
-{
- XStatus Status = XST_FAILURE;
-
- Status = XClock_DisableClock(ClockId);
- return Status;
-}
-
-XStatus Xil_ClockGetRate(XClock_OutputClks ClockId, XClockRate *Rate)
-{
- XStatus Status = XST_FAILURE;
-
- Xil_AssertNonvoid(Rate != NULL);
-
- Status = XClock_GetRate(ClockId, Rate);
- if (XST_SUCCESS == Status) {
- xdbg_printf(XDBG_DEBUG_GENERAL, "Operating rate = %lx\n",*Rate);
- } else {
- xdbg_printf(XDBG_DEBUG_ERROR, "Failed: Fetching rate\r\n");
- }
- return Status;
-}
-
-XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate,
- XClockRate *SetRate)
-{
- XStatus Status = XST_FAILURE;
-
- Xil_AssertNonvoid(SetRate != NULL);
-
- if (Rate == 0) {
- return XST_FAILURE;
- }
- Status = XClock_SetRate(ClockId, Rate, SetRate);
- if (XST_SUCCESS != Status) {
- xdbg_printf(XDBG_DEBUG_ERROR, "Failed Setting rate\n");
- }
- return Status;
-}
-
-#else
-XStatus Xil_ClockGetRate(XClock_OutputClks ClockId, XClockRate *Rate)
-{
- (void) ClockId;
- (void) Rate;
- return XST_FAILURE;
-}
-
-XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate,
- XClockRate *SetRate) {
- (void) ClockId;
- (void) Rate;
- (void) SetRate;
- return XST_FAILURE;
-}
-
-XStatus Xil_ClockInit(void)
-{
- return XST_SUCCESS;
-}
-
-XStatus Xil_ClockEnable(XClock_OutputClks ClockId)
-{
- (void) ClockId;
- return XST_SUCCESS;
-}
-
-XStatus Xil_ClockDisable(XClock_OutputClks ClockId)
-{
- (void) ClockId;
- return XST_SUCCESS;
-}
-
-#endif /* XCLOCKING */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f9/b057cf535243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f9/b057cf535243001d18b399c1eb9b3628
deleted file mode 100644
index 6d07851..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f9/b057cf535243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,60 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm.h
-*
-* @addtogroup a9_specific Cortex A9 Processor Specific Include Files
-*
-* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h.
-*
-* The xreg_cortexa9.h file contains definitions for inline assembler code.
-* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers,
-* co-processor registers and Debug registers.
-*
-* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
-* assembler instructions, available as macros. These can be very useful for
-* tasks such as setting or getting special purpose registers, synchronization,
-* or cache manipulation etc. These inline assembler instructions can be used
-* from drivers and user applications written in C.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 10/18/09 First release
-* 3.04a sdm 01/02/12 Remove redundant dsb in mcr instruction.
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-*
-******************************************************************************/
-#ifndef XPSEUDO_ASM_H
-#define XPSEUDO_ASM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xreg_cortexa9.h"
-#ifdef __GNUC__
- #include "xpseudo_asm_gcc.h"
-#elif defined (__ICCARM__)
- #include "xpseudo_asm_iccarm.h"
-#else
- #include "xpseudo_asm_rvct.h"
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XPSEUDO_ASM_H */
-/**
-* @} End of "addtogroup a9_specific".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f9/c01337575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f9/c01337575243001d18b399c1eb9b3628
deleted file mode 100644
index 822dc3a..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f9/c01337575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,195 +0,0 @@
-#ifdef __GNUC__
-/******************************************************************************
-*
-* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file handoff.S
-*
-* Contains the code that does the handoff to the loaded application. This
-* code lives high in the ROM.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date.word Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a ecm 03/01/10 Initial release
-* 7.00a kc 10/23/13 Added support for armcc compiler
-*
-*
-* @note
-* Assumes that the starting address of the FSBL is provided by the calling routine
-* in R0.
-*
-******************************************************************************/
-
-.globl FsblHandoffJtagExit
-
-.globl FsblHandoffExit
-
-.section .handoff,"axS"
-
-/***************************** Include Files *********************************/
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-FsblHandoffJtagExit:
- mcr 15,0,r0,cr7,cr5,0 /* Invalidate Instruction cache */
- mcr 15,0,r0,cr7,cr5,6 /* Invalidate branch predictor array */
-
- dsb
- isb /* make sure it completes */
-
- ldr r4, =0
- mcr 15,0,r4,cr1,cr0,0 /* disable the ICache and MMU */
-
- isb /* make sure it completes */
-Loop:
- wfe
- b Loop
-
-FsblHandoffExit:
- mov lr, r0 /* move the destination address into link register */
-
- mcr 15,0,r0,cr7,cr5,0 /* Invalidate Instruction cache */
- mcr 15,0,r0,cr7,cr5,6 /* Invalidate branch predictor array */
-
- dsb
- isb /* make sure it completes */
-
- ldr r4, =0
- mcr 15,0,r4,cr1,cr0,0 /* disable the ICache and MMU */
-
- isb /* make sure it completes */
-
-
- bx lr /* force the switch, destination should have been in r0 */
-
-.Ldone: b .Ldone /* Paranoia: we should never get here */
-.end
-
-#elif defined (__IASMARM__)
-
- PUBLIC FsblHandoffJtagExit
-
- PUBLIC FsblHandoffExit
-
- SECTION .handoff:CODE:NOROOT(2)
-
-/***************************** Include Files *********************************/
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-FsblHandoffJtagExit
- mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
- mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
-
- dsb
- isb ;/* make sure it completes */
-
- ldr r4, =0
- mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
-
- isb ;/* make sure it completes */
-Loop
- wfe
- b Loop
-
-FsblHandoffExit
- mov lr, r0 ;/* move the destination address into link register */
-
- mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
- mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
-
- dsb
- isb ;/* make sure it completes */
-
- ldr r4, =0
- mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
-
- isb ;/* make sure it completes */
-
-
- bx lr ;/* force the switch, destination should have been in r0 */
-
-.Ldone
- b .Ldone ;/* Paranoia: we should never get here */
-
- END
-
-
-#else
- EXPORT FsblHandoffJtagExit
-
- EXPORT FsblHandoffExit
-
- AREA |.handoff|,CODE
-
-;/***************************** Include Files *********************************/
-
-;/************************** Constant Definitions *****************************/
-
-;/**************************** Type Definitions *******************************/
-
-;/***************** Macros (Inline Functions) Definitions *********************/
-
-;/************************** Function Prototypes ******************************/
-
-;/************************** Variable Definitions *****************************/
-
-
-FsblHandoffJtagExit
- mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
- mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
-
- dsb
- isb ;/* make sure it completes */
-
- ldr r4, =0
- mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
-
- isb ;/* make sure it completes */
-Loop
- wfe
- b Loop
-
-FsblHandoffExit
- mov lr, r0 ;/* move the destination address into link register */
-
- mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
- mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
-
- dsb
- isb ;/* make sure it completes */
-
- ldr r4, =0
- mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
-
- isb ;/* make sure it completes */
-
-
- bx lr ;/* force the switch, destination should have been in r0 */
-
-Ldone b Ldone ;/* Paranoia: we should never get here */
- END
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f9/e084c9565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f9/e084c9565243001d18b399c1eb9b3628
deleted file mode 100644
index f0102aa..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/f9/e084c9565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,54 +0,0 @@
-/* putnum.c -- put a hex number on the output device.
- *
- * Copyright (c) 1995 Cygnus Support
- *
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
- * putnum -- print a 32 bit number in hex
- */
-
-/***************************** Include Files *********************************/
-#include "xil_types.h"
-
-/************************** Function Prototypes ******************************/
-extern void print (const char8 *ptr);
-void putnum(u32 num);
-
-void putnum(u32 num)
-{
- char8 buf[9];
- s32 cnt;
- s32 i;
- char8 *ptr;
- u32 digit;
- for(i = 0; i<9; i++) {
- buf[i] = '0';
- }
-
- ptr = buf;
- for (cnt = 7 ; cnt >= 0 ; cnt--) {
- digit = (num >> (cnt * 4U)) & 0x0000000fU;
-
- if (digit <= 9U) {
- digit += (u32)'0';
- *ptr = ((char8) digit);
- ptr += 1;
- } else {
- digit += ((u32)'a' - (u32)10);
- *ptr = ((char8)digit);
- ptr += 1;
- }
- }
-
- print (buf);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/02ec9e595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/02ec9e595243001d18b399c1eb9b3628
deleted file mode 100644
index a146f83..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/02ec9e595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,387 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_exception.h
-*
-* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
-* For exception related functions that can be used across all Xilinx supported
-* processors, please use xil_exception.h.
-*
-* @addtogroup arm_exception_apis ARM Processor Exception Handling
-* @{
-* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
-* utilized for enabling/disabling IRQ, registering/removing handler for
-* exceptions or initializing exception vector table with null handler.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
-* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler.
-* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.
-* 7.0 mus 01/03/19 Tweak Xil_ExceptionEnableMask and
-* Xil_ExceptionDisableMask macros to support legacy
-* examples for Cortexa72 EL3 exception level.
-* 7.3 mus 04/15/20 Added Xil_EnableNestedInterrupts and
-* Xil_DisableNestedInterrupts macros for ARMv8.
-* For Cortexa72, these macro's would not be supported
-* at EL3, as Cortexa72 is using GIC-500(GICv3), which
-* triggeres only FIQ at EL3. Fix for CR#1062506
-# 7.6 mus 09/17/21 Updated flag checking to fix warning reported with
-# -Wundef compiler option CR#1110261
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
-#define XIL_EXCEPTION_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#include "bspconfig.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Constant Definitions ****************************/
-
-#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
-#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
-#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
-
-#define XIL_EXCEPTION_ID_FIRST 0U
-#if defined (__aarch64__)
-#define XIL_EXCEPTION_ID_SYNC_INT 1U
-#define XIL_EXCEPTION_ID_IRQ_INT 2U
-#define XIL_EXCEPTION_ID_FIQ_INT 3U
-#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
-#define XIL_EXCEPTION_ID_LAST 5U
-#else
-#define XIL_EXCEPTION_ID_RESET 0U
-#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
-#define XIL_EXCEPTION_ID_SWI_INT 2U
-#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
-#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
-#define XIL_EXCEPTION_ID_IRQ_INT 5U
-#define XIL_EXCEPTION_ID_FIQ_INT 6U
-#define XIL_EXCEPTION_ID_LAST 6U
-#endif
-
-/*
- * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
- */
-#if defined (versal) && !defined(ARMR5) && EL3
-#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_FIQ_INT
-#else
-#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
-#endif
-
-/**************************** Type Definitions ******************************/
-
-/**
- * This typedef is the exception handler function.
- */
-typedef void (*Xil_ExceptionHandler)(void *data);
-typedef void (*Xil_InterruptHandler)(void *data);
-
-/**
-*@endcond
-*/
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/****************************************************************************/
-/**
-* @brief Enable Exceptions.
-*
-* @param Mask: Value for enabling the exceptions.
-*
-* @return None.
-*
-* @note If bit is 0, exception is enabled.
-* C-Style signature: void Xil_ExceptionEnableMask(Mask)
-*
-******************************************************************************/
-#if defined (versal) && !defined(ARMR5) && EL3
-/*
- * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
- * only FIQ at EL3. Hence, tweaking this macro to always enable FIQ
- * ignoring argument passed by user.
- */
-#define Xil_ExceptionEnableMask(Mask) \
- mtcpsr(mfcpsr() & ~ ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
-#elif defined (__GNUC__) || defined (__ICCARM__)
-#define Xil_ExceptionEnableMask(Mask) \
- mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
-#else
-#define Xil_ExceptionEnableMask(Mask) \
- { \
- register u32 Reg __asm("cpsr"); \
- mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
- }
-#endif
-/****************************************************************************/
-/**
-* @brief Enable the IRQ exception.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-#if defined (versal) && !defined(ARMR5) && EL3
-#define Xil_ExceptionEnable() \
- Xil_ExceptionEnableMask(XIL_EXCEPTION_FIQ)
-#else
-#define Xil_ExceptionEnable() \
- Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
-#endif
-
-/****************************************************************************/
-/**
-* @brief Disable Exceptions.
-*
-* @param Mask: Value for disabling the exceptions.
-*
-* @return None.
-*
-* @note If bit is 1, exception is disabled.
-* C-Style signature: Xil_ExceptionDisableMask(Mask)
-*
-******************************************************************************/
-#if defined (versal) && !defined(ARMR5) && EL3
-/*
- * Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
- * only FIQ at EL3. Hence, tweaking this macro to always disable FIQ
- * ignoring argument passed by user.
- */
-#define Xil_ExceptionDisableMask(Mask) \
- mtcpsr(mfcpsr() | ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
-#elif defined (__GNUC__) || defined (__ICCARM__)
-#define Xil_ExceptionDisableMask(Mask) \
- mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
-#else
-#define Xil_ExceptionDisableMask(Mask) \
- { \
- register u32 Reg __asm("cpsr"); \
- mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
- }
-#endif
-/****************************************************************************/
-/**
-* Disable the IRQ exception.
-*
-* @return None.
-*
-* @note None.
-*
-******************************************************************************/
-#define Xil_ExceptionDisable() \
- Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
-
-#if ( defined (PLATFORM_ZYNQMP) && defined (EL3) && (EL3==1) )
-/****************************************************************************/
-/**
-* @brief Enable nested interrupts by clearing the I bit in DAIF.This
-* macro is defined for Cortex-A53 64 bit mode BSP configured to run
-* at EL3.. However,it is not defined for Versal Cortex-A72 BSP
-* configured to run at EL3. Reason is, Cortex-A72 is coupled
-* with GIC-500(GICv3 specifications) and it triggers only FIQ at EL3.
-*
-* @return None.
-*
-* @note This macro is supposed to be used from interrupt handlers. In the
-* interrupt handler the interrupts are disabled by default (I bit
-* is set as 1). To allow nesting of interrupts, this macro should be
-* used. It clears the I bit. Once that bit is cleared and provided the
-* preemption of interrupt conditions are met in the GIC, nesting of
-* interrupts will start happening.
-* Caution: This macro must be used with caution. Before calling this
-* macro, the user must ensure that the source of the current IRQ
-* is appropriately cleared. Otherwise, as soon as we clear the I
-* bit, there can be an infinite loop of interrupts with an
-* eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
- __asm__ __volatile__ ("mrs X1, ELR_EL3"); \
- __asm__ __volatile__ ("mrs X2, SPSR_EL3"); \
- __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-/****************************************************************************/
-/**
-* @brief Disable the nested interrupts by setting the I bit in DAIF. This
-* macro is defined for Cortex-A53 64 bit mode BSP configured to run
-* at EL3.
-*
-* @return None.
-*
-* @note This macro is meant to be called in the interrupt service routines.
-* This macro cannot be used independently. It can only be used when
-* nesting of interrupts have been enabled by using the macro
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-* point. The user then must call this macro before exiting the interrupt
-* service routine. This macro puts the ARM back in IRQ mode and
-* hence sets back the I bit.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
- __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \
- __asm__ __volatile__ ("msr ELR_EL3, X1"); \
- __asm__ __volatile__ ("msr SPSR_EL3, X2"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-#elif (defined (EL1_NONSECURE) && (EL1_NONSECURE==1))
-/****************************************************************************/
-/**
-* @brief Enable nested interrupts by clearing the I bit in DAIF.This
-* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit
-* BSP configured to run at EL1 NON SECURE
-*
-* @return None.
-*
-* @note This macro is supposed to be used from interrupt handlers. In the
-* interrupt handler the interrupts are disabled by default (I bit
-* is set as 1). To allow nesting of interrupts, this macro should be
-* used. It clears the I bit. Once that bit is cleared and provided the
-* preemption of interrupt conditions are met in the GIC, nesting of
-* interrupts will start happening.
-* Caution: This macro must be used with caution. Before calling this
-* macro, the user must ensure that the source of the current IRQ
-* is appropriately cleared. Otherwise, as soon as we clear the I
-* bit, there can be an infinite loop of interrupts with an
-* eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
- __asm__ __volatile__ ("mrs X1, ELR_EL1"); \
- __asm__ __volatile__ ("mrs X2, SPSR_EL1"); \
- __asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-/****************************************************************************/
-/**
-* @brief Disable the nested interrupts by setting the I bit in DAIF. This
-* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit
-* BSP configured to run at EL1 NON SECURE
-*
-* @return None.
-*
-* @note This macro is meant to be called in the interrupt service routines.
-* This macro cannot be used independently. It can only be used when
-* nesting of interrupts have been enabled by using the macro
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-* point. The user then must call this macro before exiting the interrupt
-* service routine. This macro puts the ARM back in IRQ mode and
-* hence sets back the I bit.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
- __asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \
- __asm__ __volatile__ ("msr ELR_EL1, X1"); \
- __asm__ __volatile__ ("msr SPSR_EL1, X2"); \
- __asm__ __volatile__ ("mrs X1, DAIF"); \
- __asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \
- __asm__ __volatile__ ("msr DAIF, X1"); \
-
-#elif (!defined (__aarch64__) && !defined (ARMA53_32))
-/****************************************************************************/
-/**
-* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This
-* API is defined for cortex-a9 and cortex-r5.
-*
-* @return None.
-*
-* @note This macro is supposed to be used from interrupt handlers. In the
-* interrupt handler the interrupts are disabled by default (I and F
-* are 1). To allow nesting of interrupts, this macro should be
-* used. It clears the I and F bits by changing the ARM mode to
-* system mode. Once these bits are cleared and provided the
-* preemption of interrupt conditions are met in the GIC, nesting of
-* interrupts will start happening.
-* Caution: This macro must be used with caution. Before calling this
-* macro, the user must ensure that the source of the current IRQ
-* is appropriately cleared. Otherwise, as soon as we clear the I and
-* F bits, there can be an infinite loop of interrupts with an
-* eventual crash (all the stack space getting consumed).
-******************************************************************************/
-#define Xil_EnableNestedInterrupts() \
- __asm__ __volatile__ ("stmfd sp!, {lr}"); \
- __asm__ __volatile__ ("mrs lr, spsr"); \
- __asm__ __volatile__ ("stmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
- __asm__ __volatile__ ("stmfd sp!, {lr}");
-/****************************************************************************/
-/**
-* @brief Disable the nested interrupts by setting the I and F bits. This API
-* is defined for cortex-a9 and cortex-r5.
-*
-* @return None.
-*
-* @note This macro is meant to be called in the interrupt service routines.
-* This macro cannot be used independently. It can only be used when
-* nesting of interrupts have been enabled by using the macro
-* Xil_EnableNestedInterrupts(). In a typical flow, the user first
-* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
-* point. The user then must call this macro before exiting the interrupt
-* service routine. This macro puts the ARM back in IRQ/FIQ mode and
-* hence sets back the I and F bits.
-******************************************************************************/
-#define Xil_DisableNestedInterrupts() \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr cpsr_c, #0x92"); \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
- __asm__ __volatile__ ("msr spsr_cxsf, lr"); \
- __asm__ __volatile__ ("ldmfd sp!, {lr}"); \
-
-#endif
-/************************** Variable Definitions ****************************/
-
-/************************** Function Prototypes *****************************/
-
-extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler Handler,
- void *Data);
-
-extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
-extern void Xil_GetExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler *Handler, void **Data);
-
-extern void Xil_ExceptionInit(void);
-#if defined (__aarch64__)
-void Xil_SyncAbortHandler(void *CallBackRef);
-void Xil_SErrorAbortHandler(void *CallBackRef);
-#else
-extern void Xil_DataAbortHandler(void *CallBackRef);
-extern void Xil_PrefetchAbortHandler(void *CallBackRef);
-extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
-#endif
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_EXCEPTION_H */
-/**
-* @} End of "addtogroup arm_exception_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/14dcce565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/14dcce565243001d18b399c1eb9b3628
deleted file mode 100644
index 29be8d2..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/14dcce565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,73 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#ifndef XDEBUG
-#define XDEBUG
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(DEBUG) && !defined(NDEBUG)
-
-#ifndef XDEBUG_WARNING
-#define XDEBUG_WARNING
-#warning DEBUG is enabled
-#endif
-
-int printf(const char *format, ...);
-
-#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */
-#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */
-#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */
-
-#define XDBG_DEBUG_FIFO_REG 0x00000100U /* display register reads/writes */
-#define XDBG_DEBUG_FIFO_RX 0x00000101U /* receive debug messages */
-#define XDBG_DEBUG_FIFO_TX 0x00000102U /* transmit debug messages */
-#define XDBG_DEBUG_FIFO_ALL 0x0000010FU /* all fifo debug messages */
-
-#define XDBG_DEBUG_TEMAC_REG 0x00000400U /* display register reads/writes */
-#define XDBG_DEBUG_TEMAC_RX 0x00000401U /* receive debug messages */
-#define XDBG_DEBUG_TEMAC_TX 0x00000402U /* transmit debug messages */
-#define XDBG_DEBUG_TEMAC_ALL 0x0000040FU /* all temac debug messages */
-
-#define XDBG_DEBUG_TEMAC_ADPT_RX 0x00000800U /* receive debug messages */
-#define XDBG_DEBUG_TEMAC_ADPT_TX 0x00000801U /* transmit debug messages */
-#define XDBG_DEBUG_TEMAC_ADPT_IOCTL 0x00000802U /* ioctl debug messages */
-#define XDBG_DEBUG_TEMAC_ADPT_MISC 0x00000803U /* debug msg for other routines */
-#define XDBG_DEBUG_TEMAC_ADPT_ALL 0x0000080FU /* all temac adapter debug messages */
-
-
-#define xdbg_current_types (XDBG_DEBUG_GENERAL | XDBG_DEBUG_ERROR | XDBG_DEBUG_TEMAC_REG | XDBG_DEBUG_FIFO_RX | XDBG_DEBUG_FIFO_TX | XDBG_DEBUG_FIFO_REG)
-
-#define xdbg_stmnt(x) x
-
-/* In VxWorks, if _WRS_GNU_VAR_MACROS is defined, special syntax is needed for
- * macros that accept variable number of arguments
- */
-#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
-#define xdbg_printf(type, args...) (((type) & xdbg_current_types) ? printf (## args) : 0)
-#else /* ANSI Syntax */
-#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
-#endif
-
-#else /* defined(DEBUG) && !defined(NDEBUG) */
-
-#define xdbg_stmnt(x)
-
-/* See VxWorks comments above */
-#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
-#define xdbg_printf(type, args...)
-#else /* ANSI Syntax */
-#define xdbg_printf(...)
-#endif
-#endif /* defined(DEBUG) && !defined(NDEBUG) */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XDEBUG */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/30cd28555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/30cd28555243001d18b399c1eb9b3628
deleted file mode 100644
index d8ea488..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/30cd28555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,84 +0,0 @@
-###############################################################################
-# Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
-# SPDX-License-Identifier: MIT
-###############################################################################
-DRIVER_LIB_VERSION = v1.0
-
-include config.make
-
-CC=$(COMPILER)
-AR=$(ARCHIVER)
-CP=cp
-COMPILER_FLAGS=
-EXTRA_COMPILER_FLAGS=
-LIB=libxil.a
-CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS))
-ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS))
-
-ECC_FLAGS += -nostartfiles\
- -march=armv8-a
-ECC_FLAGS_NO_FLTO1 = $(subst -flto,,$(ECC_FLAGS))
-ECC_FLAGS_NO_FLTO = $(subst -ffat-lto-objects,,$(ECC_FLAGS_NO_FLTO1))
-
-
-RELEASEDIR=../../../lib/
-INCLUDEDIR=../../../include/
-INCLUDES=-I./. -I${INCLUDEDIR}
-
-SRCFILES:=$(wildcard *.c)
-
-ASSEMBLY_SRCFILES:=$(wildcard *.S)
-
-OBJECTS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(filter-out _exit.c, $(wildcard *.c)))))
-
-ASSEMBLY_OBJECTS = $(addprefix $(RELEASEDIR),$(addsuffix .o, $(basename $(wildcard *.S))))
-
-EXIT_OBJ = $(addprefix $(RELEASEDIR),$(addsuffix .o,$(basename _exit.c)))
-
-
-INCLUDEFILES=*.h
-INCLUDEFILES+=includes_ps/*.h
-libs: $(LIBS)
-
-
-standalone_libs: $(OBJECTS) $(ASSEMBLY_OBJECTS) $(EXIT_OBJ)
-
-DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
-
-include $(wildcard $(DEPFILES))
-
-ASSEMBLY_DEPFILES := $(ASSEMBLY_SRCFILES:%.S=$(RELEASEDIR)%.d)
-
-include $(wildcard $(ASSEMBLY_DEPFILES))
-
-include $(wildcard ../../../../dep.mk)
-
-$(RELEASEDIR)_exit.o: _exit.c
- $(CC) $(CC_FLAGS) $(ECC_FLAGS_NO_FLTO) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $<
-
-$(RELEASEDIR)%.o: %.S
- $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $<
-
-$(RELEASEDIR)%.o: %.c
- $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) -o $@ $<
-
-
-.PHONY: include
-include: $(addprefix $(INCLUDEDIR),$(wildcard *.h)) $(addprefix $(INCLUDEDIR), $(subst includes_ps/,,$(wildcard includes_ps/*.h)))
-
-
-
-$(INCLUDEDIR)%.h: includes_ps/%.h
- $(CP) $< $@
-
-
-
-$(INCLUDEDIR)%.h: %.h
- $(CP) $< $@
-
-clean:
- rm -rf ${OBJECTS}
- rm -rf ${ASSEMBLY_OBJECTS}
- rm -rf $(DEPFILES)
- rm -rf $(ASSEMBLY_DEPFILES)
- rm -rf $(EXIT_OBJ)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/31e59b565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/31e59b565243001d18b399c1eb9b3628
deleted file mode 100644
index 362b6e9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/31e59b565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,59 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2008 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file microblaze_interrupts_i.h
-*
-* This header file contains identifiers and low-level driver functions (or
-* macros) that can be used to access the device. The user should refer to the
-* hardware device specification for more details of the device operation.
-* High-level driver functions are defined in xintc.h.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Date Changes
-* ----- -------- -----------------------------------------------
-* 1.00b 10/03/03 First release
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef MICROBLAZE_INTERRUPTS_I_H /* prevent circular inclusions */
-#define MICROBLAZE_INTERRUPTS_I_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_exception.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct
-{
- XInterruptHandler Handler;
- void *CallBackRef;
-} MB_InterruptVectorTableEntry;
-
-#define MB_INTERRUPT_VECTOR_TABLE_ENTRIES 1
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/509d43545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/509d43545243001d18b399c1eb9b3628
deleted file mode 100644
index d6bc637..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/509d43545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,47 +0,0 @@
-/******************************************************************************/
-/**
-* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-* @file xil_mem.h
-*
-* @addtogroup common_mem_operation_api Customized APIs for Memory Operations
-*
-* The xil_mem.h file contains prototype for functions related
-* to memory operations. These APIs are applicable for all processors supported
-* by Xilinx.
-*
-* @{
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 6.1 nsk 11/07/16 First release.
-* 7.0 mus 01/07/19 Add cpp extern macro
-*
-*
-*
-*****************************************************************************/
-#ifndef XIL_MEM_H /* prevent circular inclusions */
-#define XIL_MEM_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/************************** Function Prototypes *****************************/
-
-void Xil_MemCpy(void* dst, const void* src, u32 cnt);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XIL_MEM_H */
-/**
-* @} End of "addtogroup common_mem_operation_api".
-*/
\ No newline at end of file
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/50cbd6565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/50cbd6565243001d18b399c1eb9b3628
deleted file mode 100644
index 75cd6f6..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/50cbd6565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,105 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_cache.h
-*
-* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions
-*
-* Cache functions provide access to cache related operations such as flush
-* and invalidate for instruction and data caches. It gives option to perform
-* the cache operations on a single cacheline, a range of memory and an entire
-* cache.
-*
-* @{
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a ecm 01/29/10 First release
-* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
-* APIs.
-* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
-*
-*
-******************************************************************************/
-
-/**
-*@cond nocomments
-*/
-
-#ifndef XIL_CACHE_H
-#define XIL_CACHE_H
-
-#include "xil_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef __GNUC__
-
-#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
- XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
-
-#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
- XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
-
-#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
- XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
-
-#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
- XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
-
-#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
- XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
-
-#elif defined (__ICCARM__)
-
-#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
- XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
-
-#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
- XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
-
-#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \
- XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
-
-#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \
- XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
-
-#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \
- XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
-
-#endif
-
-/**
-*@endcond
-*/
-
-void Xil_DCacheEnable(void);
-void Xil_DCacheDisable(void);
-void Xil_DCacheInvalidate(void);
-void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
-void Xil_DCacheFlush(void);
-void Xil_DCacheFlushRange(INTPTR adr, u32 len);
-
-void Xil_ICacheEnable(void);
-void Xil_ICacheDisable(void);
-void Xil_ICacheInvalidate(void);
-void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-/**
-* @} End of "addtogroup a9_cache_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/619c1a555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/619c1a555243001d18b399c1eb9b3628
deleted file mode 100644
index 41c9c9c..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/619c1a555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,53 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm.h
-*
-* @addtogroup a53_32_specific Cortex A53 32bit Processor Specific Include Files
-*
-* The xpseudo_asm.h includes xreg_cortexa53.h and xpseudo_asm_gcc.h.
-* The xreg_cortexa53.h file contains definitions for inline assembler code.
-* It provides inline definitions for Cortex A53 GPRs, SPRs, co-processor
-* registers and floating point registers.
-*
-* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
-* assembler instructions, available as macros. These can be very useful for
-* tasks such as setting or getting special purpose registers, synchronization,
-* or cache manipulation etc. These inline assembler instructions can be used
-* from drivers and user applications written in C.
-*
-* @{
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 5.2 pkp 28/05/15 First release
-*
-*
-******************************************************************************/
-#ifndef XPSEUDO_ASM_H
-#define XPSEUDO_ASM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xreg_cortexa53.h"
-#include "xpseudo_asm_gcc.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XPSEUDO_ASM_H */
-/**
-* @} End of "addtogroup a53_32_specific".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/70f826555243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/70f826555243001d18b399c1eb9b3628
deleted file mode 100644
index 3d5b832..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/70f826555243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,136 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2019 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xpseudo_asm_armclang.h
-*
-* This header file contains macros for using __inline assembler code.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 7.0 cjp 02/26/19 First Release
-* 7.2 asa 04/03/20 Renamed the str macro to strw.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 7.2 sd 12/11/19 First release
-* 7.2 sd 03/20/20 Added checking for isolation case
-*
-*
-******************************************************************************/
-
-#ifndef XIL_CLOCKING_H /* prevent circular inclusions */
-#define XIL_CLOCKING_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "xdebug.h"
-#include "xil_printf.h"
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xparameters.h"
-#include "xstatus.h"
-#if defined (XPAR_XCRPSU_0_DEVICE_ID)
-#include "xclockps.h"
-#else
-typedef u32 XClock_OutputClks;
-typedef u64 XClockRate;
-#endif
-
-/***************************** Include Files *********************************/
-
-
-/************************** Constant Definitions *****************************/
-
-
-XStatus Xil_ClockDisable(XClock_OutputClks ClockId);
-XStatus Xil_ClockEnable(XClock_OutputClks ClockId);
-XStatus Xil_ClockInit(void);
-XStatus Xil_ClockGet(void);
-XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate, XClockRate *SetRate);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/b24446595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/b24446595243001d18b399c1eb9b3628
deleted file mode 100644
index 1e9e6fb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fa/b24446595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,522 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xstatus.h
-*
-* @addtogroup common_status_codes Xilinx software status codes
-*
-* The xstatus.h file contains the Xilinx software status codes.These codes are
-* used throughout the Xilinx device drivers.
-*
-* @{
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XSTATUS_H /* prevent circular inclusions */
-#define XSTATUS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-
-/************************** Constant Definitions *****************************/
-
-/*********************** Common statuses 0 - 500 *****************************/
-/**
-@name Common Status Codes for All Device Drivers
-@{
-*/
-#define XST_SUCCESS 0L
-#define XST_FAILURE 1L
-#define XST_DEVICE_NOT_FOUND 2L
-#define XST_DEVICE_BLOCK_NOT_FOUND 3L
-#define XST_INVALID_VERSION 4L
-#define XST_DEVICE_IS_STARTED 5L
-#define XST_DEVICE_IS_STOPPED 6L
-#define XST_FIFO_ERROR 7L /*!< An error occurred during an
- operation with a FIFO such as
- an underrun or overrun, this
- error requires the device to
- be reset */
-#define XST_RESET_ERROR 8L /*!< An error occurred which requires
- the device to be reset */
-#define XST_DMA_ERROR 9L /*!< A DMA error occurred, this error
- typically requires the device
- using the DMA to be reset */
-#define XST_NOT_POLLED 10L /*!< The device is not configured for
- polled mode operation */
-#define XST_FIFO_NO_ROOM 11L /*!< A FIFO did not have room to put
- the specified data into */
-#define XST_BUFFER_TOO_SMALL 12L /*!< The buffer is not large enough
- to hold the expected data */
-#define XST_NO_DATA 13L /*!< There was no data available */
-#define XST_REGISTER_ERROR 14L /*!< A register did not contain the
- expected value */
-#define XST_INVALID_PARAM 15L /*!< An invalid parameter was passed
- into the function */
-#define XST_NOT_SGDMA 16L /*!< The device is not configured for
- scatter-gather DMA operation */
-#define XST_LOOPBACK_ERROR 17L /*!< A loopback test failed */
-#define XST_NO_CALLBACK 18L /*!< A callback has not yet been
- registered */
-#define XST_NO_FEATURE 19L /*!< Device is not configured with
- the requested feature */
-#define XST_NOT_INTERRUPT 20L /*!< Device is not configured for
- interrupt mode operation */
-#define XST_DEVICE_BUSY 21L /*!< Device is busy */
-#define XST_ERROR_COUNT_MAX 22L /*!< The error counters of a device
- have maxed out */
-#define XST_IS_STARTED 23L /*!< Used when part of device is
- already started i.e.
- sub channel */
-#define XST_IS_STOPPED 24L /*!< Used when part of device is
- already stopped i.e.
- sub channel */
-#define XST_DATA_LOST 26L /*!< Driver defined error */
-#define XST_RECV_ERROR 27L /*!< Generic receive error */
-#define XST_SEND_ERROR 28L /*!< Generic transmit error */
-#define XST_NOT_ENABLED 29L /*!< A requested service is not
- available because it has not
- been enabled */
-#define XST_NO_ACCESS 30L /* Generic access error */
-#define XST_TIMEOUT 31L /*!< Event timeout occurred */
-
-/** @} */
-/***************** Utility Component statuses 401 - 500 *********************/
-/**
-@name Utility Component Status Codes 401 - 500
-@{
-*/
-#define XST_MEMTEST_FAILED 401L /*!< Memory test failed */
-
-/** @} */
-/***************** Common Components statuses 501 - 1000 *********************/
-/**
-@name Packet Fifo Status Codes 501 - 510
-@{
-*/
-/********************* Packet Fifo statuses 501 - 510 ************************/
-
-#define XST_PFIFO_LACK_OF_DATA 501L /*!< Not enough data in FIFO */
-#define XST_PFIFO_NO_ROOM 502L /*!< Not enough room in FIFO */
-#define XST_PFIFO_BAD_REG_VALUE 503L /*!< Self test, a register value
- was invalid after reset */
-#define XST_PFIFO_ERROR 504L /*!< Generic packet FIFO error */
-#define XST_PFIFO_DEADLOCK 505L /*!< Packet FIFO is reporting
- * empty and full simultaneously
- */
-/** @} */
-/**
-@name DMA Status Codes 511 - 530
-@{
-*/
-/************************** DMA statuses 511 - 530 ***************************/
-
-#define XST_DMA_TRANSFER_ERROR 511L /*!< Self test, DMA transfer
- failed */
-#define XST_DMA_RESET_REGISTER_ERROR 512L /*!< Self test, a register value
- was invalid after reset */
-#define XST_DMA_SG_LIST_EMPTY 513L /*!< Scatter gather list contains
- no buffer descriptors ready
- to be processed */
-#define XST_DMA_SG_IS_STARTED 514L /*!< Scatter gather not stopped */
-#define XST_DMA_SG_IS_STOPPED 515L /*!< Scatter gather not running */
-#define XST_DMA_SG_LIST_FULL 517L /*!< All the buffer descriptors of
- the scatter gather list are
- being used */
-#define XST_DMA_SG_BD_LOCKED 518L /*!< The scatter gather buffer
- descriptor which is to be
- copied over in the scatter
- list is locked */
-#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /*!< No buffer descriptors have been
- put into the scatter gather
- list to be committed */
-#define XST_DMA_SG_COUNT_EXCEEDED 521L /*!< The packet count threshold
- specified was larger than the
- total # of buffer descriptors
- in the scatter gather list */
-#define XST_DMA_SG_LIST_EXISTS 522L /*!< The scatter gather list has
- already been created */
-#define XST_DMA_SG_NO_LIST 523L /*!< No scatter gather list has
- been created */
-#define XST_DMA_SG_BD_NOT_COMMITTED 524L /*!< The buffer descriptor which was
- being started was not committed
- to the list */
-#define XST_DMA_SG_NO_DATA 525L /*!< The buffer descriptor to start
- has already been used by the
- hardware so it can't be reused
- */
-#define XST_DMA_SG_LIST_ERROR 526L /*!< General purpose list access
- error */
-#define XST_DMA_BD_ERROR 527L /*!< General buffer descriptor
- error */
-/** @} */
-/**
-@name IPIF Status Codes Codes 531 - 550
-@{
-*/
-/************************** IPIF statuses 531 - 550 ***************************/
-
-#define XST_IPIF_REG_WIDTH_ERROR 531L /*!< An invalid register width
- was passed into the function */
-#define XST_IPIF_RESET_REGISTER_ERROR 532L /*!< The value of a register at
- reset was not valid */
-#define XST_IPIF_DEVICE_STATUS_ERROR 533L /*!< A write to the device interrupt
- status register did not read
- back correctly */
-#define XST_IPIF_DEVICE_ACK_ERROR 534L /*!< The device interrupt status
- register did not reset when
- acked */
-#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /*!< The device interrupt enable
- register was not updated when
- other registers changed */
-#define XST_IPIF_IP_STATUS_ERROR 536L /*!< A write to the IP interrupt
- status register did not read
- back correctly */
-#define XST_IPIF_IP_ACK_ERROR 537L /*!< The IP interrupt status register
- did not reset when acked */
-#define XST_IPIF_IP_ENABLE_ERROR 538L /*!< IP interrupt enable register was
- not updated correctly when other
- registers changed */
-#define XST_IPIF_DEVICE_PENDING_ERROR 539L /*!< The device interrupt pending
- register did not indicate the
- expected value */
-#define XST_IPIF_DEVICE_ID_ERROR 540L /*!< The device interrupt ID register
- did not indicate the expected
- value */
-#define XST_IPIF_ERROR 541L /*!< Generic ipif error */
-/** @} */
-
-/****************** Device specific statuses 1001 - 4095 *********************/
-/**
-@name Ethernet Status Codes 1001 - 1050
-@{
-*/
-/********************* Ethernet statuses 1001 - 1050 *************************/
-
-#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /*!< Memory space is not big enough
- * to hold the minimum number of
- * buffers or descriptors */
-#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /*!< Memory allocation failed */
-#define XST_EMAC_MII_READ_ERROR 1003L /*!< MII read error */
-#define XST_EMAC_MII_BUSY 1004L /*!< An MII operation is in progress */
-#define XST_EMAC_OUT_OF_BUFFERS 1005L /*!< Driver is out of buffers */
-#define XST_EMAC_PARSE_ERROR 1006L /*!< Invalid driver init string */
-#define XST_EMAC_COLLISION_ERROR 1007L /*!< Excess deferral or late
- * collision on polled send */
-/** @} */
-/**
-@name UART Status Codes 1051 - 1075
-@{
-*/
-/*********************** UART statuses 1051 - 1075 ***************************/
-#define XST_UART
-
-#define XST_UART_INIT_ERROR 1051L
-#define XST_UART_START_ERROR 1052L
-#define XST_UART_CONFIG_ERROR 1053L
-#define XST_UART_TEST_FAIL 1054L
-#define XST_UART_BAUD_ERROR 1055L
-#define XST_UART_BAUD_RANGE 1056L
-
-/** @} */
-/**
-@name IIC Status Codes 1076 - 1100
-@{
-*/
-/************************ IIC statuses 1076 - 1100 ***************************/
-
-#define XST_IIC_SELFTEST_FAILED 1076 /*!< self test failed */
-#define XST_IIC_BUS_BUSY 1077 /*!< bus found busy */
-#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /*!< mastersend attempted with */
- /* general call address */
-#define XST_IIC_STAND_REG_RESET_ERROR 1079 /*!< A non parameterizable reg */
- /* value after reset not valid */
-#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /*!< Tx fifo included in design */
- /* value after reset not valid */
-#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /*!< Rx fifo included in design */
- /* value after reset not valid */
-#define XST_IIC_TBA_REG_RESET_ERROR 1082 /*!< 10 bit addr incl in design */
- /* value after reset not valid */
-#define XST_IIC_CR_READBACK_ERROR 1083 /*!< Read of the control register */
- /* didn't return value written */
-#define XST_IIC_DTR_READBACK_ERROR 1084 /*!< Read of the data Tx reg */
- /* didn't return value written */
-#define XST_IIC_DRR_READBACK_ERROR 1085 /*!< Read of the data Receive reg */
- /* didn't return value written */
-#define XST_IIC_ADR_READBACK_ERROR 1086 /*!< Read of the data Tx reg */
- /* didn't return value written */
-#define XST_IIC_TBA_READBACK_ERROR 1087 /*!< Read of the 10 bit addr reg */
- /* didn't return written value */
-#define XST_IIC_NOT_SLAVE 1088 /*!< The device isn't a slave */
-#define XST_IIC_ARB_LOST 1089 /*!< Arbitration lost for master */
-/** @} */
-/**
-@name ATMC Status Codes 1101 - 1125
-@{
-*/
-/*********************** ATMC statuses 1101 - 1125 ***************************/
-
-#define XST_ATMC_ERROR_COUNT_MAX 1101L /*!< the error counters in the ATM
- controller hit the max value
- which requires the statistics
- to be cleared */
-/** @} */
-/**
-@name Flash Status Codes 1126 - 1150
-@{
-*/
-/*********************** Flash statuses 1126 - 1150 **************************/
-
-#define XST_FLASH_BUSY 1126L /*!< Flash is erasing or programming
- */
-#define XST_FLASH_READY 1127L /*!< Flash is ready for commands */
-#define XST_FLASH_ERROR 1128L /*!< Flash had detected an internal
- error. Use XFlash_DeviceControl
- to retrieve device specific codes
- */
-#define XST_FLASH_ERASE_SUSPENDED 1129L /*!< Flash is in suspended erase state
- */
-#define XST_FLASH_WRITE_SUSPENDED 1130L /*!< Flash is in suspended write state
- */
-#define XST_FLASH_PART_NOT_SUPPORTED 1131L /*!< Flash type not supported by
- driver */
-#define XST_FLASH_NOT_SUPPORTED 1132L /*!< Operation not supported */
-#define XST_FLASH_TOO_MANY_REGIONS 1133L /*!< Too many erase regions */
-#define XST_FLASH_TIMEOUT_ERROR 1134L /*!< Programming or erase operation
- aborted due to a timeout */
-#define XST_FLASH_ADDRESS_ERROR 1135L /*!< Accessed flash outside its
- addressible range */
-#define XST_FLASH_ALIGNMENT_ERROR 1136L /*!< Write alignment error */
-#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /*!< Couldn't return immediately from
- write/erase function with
- XFL_NON_BLOCKING_WRITE/ERASE
- option cleared */
-#define XST_FLASH_CFI_QUERY_ERROR 1138L /*!< Failed to query the device */
-/** @} */
-/**
-@name SPI Status Codes 1151 - 1175
-@{
-*/
-/*********************** SPI statuses 1151 - 1175 ****************************/
-
-#define XST_SPI_MODE_FAULT 1151 /*!< master was selected as slave */
-#define XST_SPI_TRANSFER_DONE 1152 /*!< data transfer is complete */
-#define XST_SPI_TRANSMIT_UNDERRUN 1153 /*!< slave underruns transmit register */
-#define XST_SPI_RECEIVE_OVERRUN 1154 /*!< device overruns receive register */
-#define XST_SPI_NO_SLAVE 1155 /*!< no slave has been selected yet */
-#define XST_SPI_TOO_MANY_SLAVES 1156 /*!< more than one slave is being
- * selected */
-#define XST_SPI_NOT_MASTER 1157 /*!< operation is valid only as master */
-#define XST_SPI_SLAVE_ONLY 1158 /*!< device is configured as slave-only
- */
-#define XST_SPI_SLAVE_MODE_FAULT 1159 /*!< slave was selected while disabled */
-#define XST_SPI_SLAVE_MODE 1160 /*!< device has been addressed as slave */
-#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /*!< device received data in slave mode */
-
-#define XST_SPI_COMMAND_ERROR 1162 /*!< unrecognised command - qspi only */
-#define XST_SPI_POLL_DONE 1163 /*!< controller completed polling the
- device for status */
-/** @} */
-/**
-@name OPB Arbiter Status Codes 1176 - 1200
-@{
-*/
-/********************** OPB Arbiter statuses 1176 - 1200 *********************/
-
-#define XST_OPBARB_INVALID_PRIORITY 1176 /*!< the priority registers have either
- * one master assigned to two or more
- * priorities, or one master not
- * assigned to any priority
- */
-#define XST_OPBARB_NOT_SUSPENDED 1177 /*!< an attempt was made to modify the
- * priority levels without first
- * suspending the use of priority
- * levels
- */
-#define XST_OPBARB_PARK_NOT_ENABLED 1178 /*!< bus parking by id was enabled but
- * bus parking was not enabled
- */
-#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /*!< the arbiter must be in fixed
- * priority mode to allow the
- * priorities to be changed
- */
-/** @} */
-/**
-@name INTC Status Codes 1201 - 1225
-@{
-*/
-/************************ Intc statuses 1201 - 1225 **************************/
-
-#define XST_INTC_FAIL_SELFTEST 1201 /*!< self test failed */
-#define XST_INTC_CONNECT_ERROR 1202 /*!< interrupt already in use */
-/** @} */
-/**
-@name TmrCtr Status Codes 1226 - 1250
-@{
-*/
-/********************** TmrCtr statuses 1226 - 1250 **************************/
-
-#define XST_TMRCTR_TIMER_FAILED 1226 /*!< self test failed */
-/** @} */
-/**
-@name WdtTb Status Codes 1251 - 1275
-@{
-*/
-/********************** WdtTb statuses 1251 - 1275 ***************************/
-
-#define XST_WDTTB_TIMER_FAILED 1251L
-/** @} */
-/**
-@name PlbArb status Codes 1276 - 1300
-@{
-*/
-/********************** PlbArb statuses 1276 - 1300 **************************/
-
-#define XST_PLBARB_FAIL_SELFTEST 1276L
-/** @} */
-/**
-@name Plb2Opb Status Codes 1301 - 1325
-@{
-*/
-/********************** Plb2Opb statuses 1301 - 1325 *************************/
-
-#define XST_PLB2OPB_FAIL_SELFTEST 1301L
-/** @} */
-/**
-@name Opb2Plb Status 1326 - 1350
-@{
-*/
-/********************** Opb2Plb statuses 1326 - 1350 *************************/
-
-#define XST_OPB2PLB_FAIL_SELFTEST 1326L
-/** @} */
-/**
-@name SysAce Status Codes 1351 - 1360
-@{
-*/
-/********************** SysAce statuses 1351 - 1360 **************************/
-
-#define XST_SYSACE_NO_LOCK 1351L /*!< No MPU lock has been granted */
-/** @} */
-/**
-@name PCI Bridge Status Codes 1361 - 1375
-@{
-*/
-/********************** PCI Bridge statuses 1361 - 1375 **********************/
-
-#define XST_PCI_INVALID_ADDRESS 1361L
-/** @} */
-/**
-@name FlexRay Constants 1400 - 1409
-@{
-*/
-/********************** FlexRay constants 1400 - 1409 *************************/
-
-#define XST_FR_TX_ERROR 1400
-#define XST_FR_TX_BUSY 1401
-#define XST_FR_BUF_LOCKED 1402
-#define XST_FR_NO_BUF 1403
-/** @} */
-/**
-@name USB constants 1410 - 1420
-@{
-*/
-/****************** USB constants 1410 - 1420 *******************************/
-
-#define XST_USB_ALREADY_CONFIGURED 1410
-#define XST_USB_BUF_ALIGN_ERROR 1411
-#define XST_USB_NO_DESC_AVAILABLE 1412
-#define XST_USB_BUF_TOO_BIG 1413
-#define XST_USB_NO_BUF 1414
-/** @} */
-/**
-@name HWICAP constants 1421 - 1429
-@{
-*/
-/****************** HWICAP constants 1421 - 1429 *****************************/
-
-#define XST_HWICAP_WRITE_DONE 1421
-
-/** @} */
-/**
-@name AXI VDMA constants 1430 - 1440
-@{
-*/
-/****************** AXI VDMA constants 1430 - 1440 *****************************/
-
-#define XST_VDMA_MISMATCH_ERROR 1430
-/** @} */
-/**
-@name NAND Flash Status Codes 1441 - 1459
-@{
-*/
-/*********************** NAND Flash statuses 1441 - 1459 *********************/
-
-#define XST_NAND_BUSY 1441L /*!< Flash is erasing or
- * programming
- */
-#define XST_NAND_READY 1442L /*!< Flash is ready for commands
- */
-#define XST_NAND_ERROR 1443L /*!< Flash had detected an
- * internal error.
- */
-#define XST_NAND_PART_NOT_SUPPORTED 1444L /*!< Flash type not supported by
- * driver
- */
-#define XST_NAND_OPT_NOT_SUPPORTED 1445L /*!< Operation not supported
- */
-#define XST_NAND_TIMEOUT_ERROR 1446L /*!< Programming or erase
- * operation aborted due to a
- * timeout
- */
-#define XST_NAND_ADDRESS_ERROR 1447L /*!< Accessed flash outside its
- * addressible range
- */
-#define XST_NAND_ALIGNMENT_ERROR 1448L /*!< Write alignment error
- */
-#define XST_NAND_PARAM_PAGE_ERROR 1449L /*!< Failed to read parameter
- * page of the device
- */
-#define XST_NAND_CACHE_ERROR 1450L /*!< Flash page buffer error
- */
-
-#define XST_NAND_WRITE_PROTECTED 1451L /*!< Flash is write protected
- */
-/** @} */
-
-/**************************** Type Definitions *******************************/
-
-typedef s32 XStatus;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-
-/************************** Function Prototypes ******************************/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
-
-/**
-* @} End of "addtogroup common_status_codes".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fb/c1bdeb575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fb/c1bdeb575243001d18b399c1eb9b3628
deleted file mode 100644
index 24e1515..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fb/c1bdeb575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,84 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xgpio_selftest.c
-* @addtogroup gpio_v4_8
-* @{
-*
-* The implementation of the XGpio driver's self test function.
-* See xgpio.h for more information about the driver.
-*
-* @note
-*
-* None
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00a rmm 02/04/02 First release
-* 2.00a jhl 01/13/04 Addition of dual channels and interrupts.
-* 2.11a mta 03/21/07 Updated to new coding style
-* 3.00a sv 11/21/09 Updated to use HAL Processor APIs.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00 hbm 07/28/09 Initial release
-* 3.02a sdm 10/24/11 Updated the file to include xparameters.h so that
-* the correct cache flush routines are used based on
-* whether the write-back or write-through caches are
-* used (cr #630532).
-* 3.10a asa 05/04/13 This version of MicroBlaze BSP adds support for system
-* cache/L2 cache. The existing/old APIs/macros in this
-* file are renamed to imply that they deal with L1 cache.
-* New macros/APIs are added to address similar features for
-* L2 cache. Users can include this file in their application
-* to use the various cache related APIs. These changes are
-* done for implementing PR #697214.
-*
-*
-*
-*
-******************************************************************************/
-
-#ifndef XIL_CACHE_H
-#define XIL_CACHE_H
-
-#if defined XENV_VXWORKS
-/* VxWorks environment */
-#error "Unknown processor / architecture. Must be PPC for VxWorks."
-#else
-/* standalone environment */
-
-#include "mb_interface.h"
-#include "xil_types.h"
-#include "xparameters.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/****************************************************************************/
-/**
-*
-* @brief Invalidate the entire L1 data cache. If the cacheline is modified
-* (dirty), the modified contents are lost.
-*
-*
-* @return None.
-*
-* @note Processor must be in real mode.
-****************************************************************************/
-#define Xil_L1DCacheInvalidate() microblaze_invalidate_dcache()
-
-/****************************************************************************/
-/**
-*
-* @brief Invalidate the entire L2 data cache. If the cacheline is modified
-* (dirty),the modified contents are lost.
-*
-* @return None.
-*
-* @note Processor must be in real mode.
-****************************************************************************/
-#define Xil_L2CacheInvalidate() microblaze_invalidate_cache_ext()
-
-/****************************************************************************/
-/**
-*
-* @brief Invalidate the L1 data cache for the given address range.
-* If the bytes specified by the address (Addr) are cached by the L1
-* data cache, the cacheline containing that byte is invalidated.If
-* the cacheline is modified (dirty), the modified contents are lost.
-*
-* @param Addr is address of range to be invalidated.
-* @param Len is the length in bytes to be invalidated.
-*
-* @return None.
-*
-* @note Processor must be in real mode.
-****************************************************************************/
-#define Xil_L1DCacheInvalidateRange(Addr, Len) \
- microblaze_invalidate_dcache_range((Addr), (Len))
-
-/****************************************************************************/
-/**
-*
-* @brief Invalidate the L1 data cache for the given address range.
-* If the bytes specified by the address (Addr) are cached by the
-* L1 data cache, the cacheline containing that byte is invalidated.
-* If the cacheline is modified (dirty), the modified contents are lost.
-*
-* @param Addr: address of range to be invalidated.
-* @param Len: length in bytes to be invalidated.
-*
-* @return None.
-*
-* @note Processor must be in real mode.
-****************************************************************************/
-#define Xil_L2CacheInvalidateRange(Addr, Len) \
- microblaze_invalidate_cache_ext_range((Addr), (Len))
-
-/****************************************************************************/
-/**
-* @brief Flush the L1 data cache for the given address range.
-* If the bytes specified by the address (Addr) are cached by the
-* data cache, and is modified (dirty), the cacheline will be written
-* to system memory.The cacheline will also be invalidated.
-*
-* @param Addr: the starting address of the range to be flushed.
-* @param Len: length in byte to be flushed.
-*
-* @return None.
-*
-****************************************************************************/
-#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
-# define Xil_L1DCacheFlushRange(Addr, Len) \
- microblaze_flush_dcache_range((Addr), (Len))
-#else
-# define Xil_L1DCacheFlushRange(Addr, Len) \
- microblaze_invalidate_dcache_range((Addr), (Len))
-#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */
-
-/****************************************************************************/
-/**
-* @brief Flush the L2 data cache for the given address range.
-* If the bytes specified by the address (Addr) are cached by the
-* data cache, and is modified (dirty), the cacheline will be
-* written to system memory. The cacheline will also be invalidated.
-*
-* @param Addr: the starting address of the range to be flushed.
-* @param Len: length in byte to be flushed.
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_L2CacheFlushRange(Addr, Len) \
- microblaze_flush_cache_ext_range((Addr), (Len))
-
-/****************************************************************************/
-/**
-* @brief Flush the entire L1 data cache. If any cacheline is dirty, the
-* cacheline will be written to system memory. The entire data cache
-* will be invalidated.
-*
-* @return None.
-*
-****************************************************************************/
-#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
-# define Xil_L1DCacheFlush() microblaze_flush_dcache()
-#else
-# define Xil_L1DCacheFlush() microblaze_invalidate_dcache()
-#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */
-
-/****************************************************************************/
-/**
-* @brief Flush the entire L2 data cache. If any cacheline is dirty, the
-* cacheline will be written to system memory. The entire data cache
-* will be invalidated.
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_L2CacheFlush() microblaze_flush_cache_ext()
-
-/****************************************************************************/
-/**
-*
-* @brief Invalidate the instruction cache for the given address range.
-*
-* @param Addr is address of ragne to be invalidated.
-* @param Len is the length in bytes to be invalidated.
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_L1ICacheInvalidateRange(Addr, Len) \
- microblaze_invalidate_icache_range((Addr), (Len))
-
-/****************************************************************************/
-/**
-*
-* @brief Invalidate the entire instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_L1ICacheInvalidate() \
- microblaze_invalidate_icache()
-
-
-/****************************************************************************/
-/**
-*
-* @brief Enable the L1 data cache.
-*
-* @return None.
-*
-* @note This is processor specific.
-*
-****************************************************************************/
-#define Xil_L1DCacheEnable() \
- microblaze_enable_dcache()
-
-/****************************************************************************/
-/**
-*
-* @brief Disable the L1 data cache.
-*
-* @return None.
-*
-* @note This is processor specific.
-*
-****************************************************************************/
-#define Xil_L1DCacheDisable() \
- microblaze_disable_dcache()
-
-/****************************************************************************/
-/**
-*
-* @brief Enable the instruction cache.
-*
-* @return None.
-*
-* @note This is processor specific.
-*
-****************************************************************************/
-#define Xil_L1ICacheEnable() \
- microblaze_enable_icache()
-
-/****************************************************************************/
-/**
-*
-* @brief Disable the L1 Instruction cache.
-*
-* @return None.
-*
-* @note This is processor specific.
-*
-****************************************************************************/
-#define Xil_L1ICacheDisable() \
- microblaze_disable_icache()
-
-/****************************************************************************/
-/**
-*
-* @brief Enable the data cache.
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_DCacheEnable() Xil_L1DCacheEnable()
-
-/****************************************************************************/
-/**
-*
-* @brief Enable the instruction cache.
-*
-* @return None.
-*
-*
-****************************************************************************/
-#define Xil_ICacheEnable() Xil_L1ICacheEnable()
-
-/****************************************************************************/
-/**
-*
-* @brief Invalidate the entire Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_DCacheInvalidate() \
- Xil_L2CacheInvalidate(); \
- Xil_L1DCacheInvalidate();
-
-
-/****************************************************************************/
-/**
-*
-* @brief Invalidate the Data cache for the given address range.
-* If the bytes specified by the address (adr) are cached by the
-* Data cache, the cacheline containing that byte is invalidated.
-* If the cacheline is modified (dirty), the modified contents are
-* lost and are NOT written to system memory before the line is
-* invalidated.
-*
-* @param Addr: Start address of range to be invalidated.
-* @param Len: Length of range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_DCacheInvalidateRange(Addr, Len) \
- Xil_L2CacheInvalidateRange((Addr), (Len)); \
- Xil_L1DCacheInvalidateRange((Addr), (Len));
-
-
-/****************************************************************************/
-/**
-*
-* @brief Flush the entire Data cache.
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_DCacheFlush() \
- Xil_L2CacheFlush(); \
- Xil_L1DCacheFlush();
-
-/****************************************************************************/
-/**
-* @brief Flush the Data cache for the given address range.
-* If the bytes specified by the address (adr) are cached by the
-* Data cache, the cacheline containing that byte is invalidated.
-* If the cacheline is modified (dirty), the written to system
-* memory first before the before the line is invalidated.
-*
-* @param Addr: Start address of range to be flushed.
-* @param Len: Length of range to be flushed in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_DCacheFlushRange(Addr, Len) \
- Xil_L2CacheFlushRange((Addr), (Len)); \
- Xil_L1DCacheFlushRange((Addr), (Len));
-
-
-/****************************************************************************/
-/**
-* @brief Invalidate the entire instruction cache.
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_ICacheInvalidate() \
- Xil_L2CacheInvalidate(); \
- Xil_L1ICacheInvalidate();
-
-
-/****************************************************************************/
-/**
-* @brief Invalidate the instruction cache for the given address range.
-* If the bytes specified by the address (adr) are cached by the
-* Data cache, the cacheline containing that byte is invalidated.
-* If the cacheline is modified (dirty), the modified contents are
-* lost and are NOT written to system memory before the line is
-* invalidated.
-*
-* @param Addr: Start address of ragne to be invalidated.
-* @param Len: Length of range to be invalidated in bytes.
-*
-* @return None.
-*
-****************************************************************************/
-#define Xil_ICacheInvalidateRange(Addr, Len) \
- Xil_L2CacheInvalidateRange((Addr), (Len)); \
- Xil_L1ICacheInvalidateRange((Addr), (Len));
-
-void Xil_DCacheDisable(void);
-void Xil_ICacheDisable(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
-/**
-* @} End of "addtogroup microblaze_cache_apis".
-*/
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fc/806e6a595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fc/806e6a595243001d18b399c1eb9b3628
deleted file mode 100644
index 229a7cb..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fc/806e6a595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,80 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2008 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-*
-* microblaze_invalidate_icache_range(unsigned int cacheaddr, unsigned int len)
-*
-* Invalidate an ICache range
-*
-* Parameters:
-* 'cacheaddr' - address in the Icache where invalidation begins
-* 'len' - length (in bytes) worth of Icache to be invalidated
-*
-*
-*******************************************************************************/
-
-#include "xparameters.h"
-#include "microblaze_instructions.h"
-
-#define MICROBLAZE_MSR_ICACHE_ENABLE 0x00000020
-#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
-
-#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
-#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
-#endif
-
-#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
-#define MB_VERSION_LT_v720
-#endif
-
- .text
- .globl microblaze_invalidate_icache_range
- .ent microblaze_invalidate_icache_range
- .align 2
-
-microblaze_invalidate_icache_range:
-#if (XPAR_MICROBLAZE_USE_ICACHE==1) && (XPAR_MICROBLAZE_ALLOW_ICACHE_WR==1)
-
-#ifdef MB_VERSION_LT_v720 /* Disable Icache and interrupts before invalidating */
- mfs r9, rmsr
- andi r10, r9, ~(MICROBLAZE_MSR_ICACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
- mts rmsr, r10
-#endif
-
- BEQI r6, L_done /* Skip loop if size is zero */
-
- ADD r6, r5, r6 /* Compute end address */
- ADDIK r6, r6, -1
-
- ANDI r6, r6, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align end down to cache line */
- ANDI r5, r5, -(4 * XPAR_MICROBLAZE_ICACHE_LINE_LEN) /* Align start down to cache line */
-
-L_start:
- CMPU r18, r5, r6 /* Are we at the end? */
- BLTI r18, L_done
-
- wic r5, r0 /* Invalidate the cache line */
-
-#if defined (__arch64__ )
- addlik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the address by 4 */
- breai L_start /* Branch to the beginning of the loop */
-#else
- brid L_start /* Branch to the beginning of the loop */
- addik r5, r5, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4) /* Increment the address by 4 (delay slot) */
-#endif
-L_done:
- rtsd r15, 8 /* Return */
-#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
- mts rmsr, r9
-#else
- nop
-#endif
-
-#else
- rtsd r15, 8 /* Return */
- nop
-#endif
-.end microblaze_invalidate_icache_range
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fc/a194d0575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fc/a194d0575243001d18b399c1eb9b3628
deleted file mode 100644
index 751df21..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fc/a194d0575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,78 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* @file xdmaps_sinit.c
-* @addtogroup dmaps_v2_8
-* @{
-*
-* The implementation of the XDmaPs driver's static initialzation
-* functionality.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00 hbm 08/13/10 First Release
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xstatus.h"
-#include "xparameters.h"
-#include "xdmaps.h"
-
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Variable Definitions ****************************/
-extern XDmaPs_Config XDmaPs_ConfigTable[];
-
-/************************** Function Prototypes *****************************/
-
-/****************************************************************************/
-/**
-*
-* Looks up the device configuration based on the unique device ID. The table
-* contains the configuration info for each device in the system.
-*
-* @param DeviceId contains the ID of the device
-*
-* @return
-*
-* A pointer to the configuration structure or NULL if the specified device
-* is not in the system.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId)
-{
- XDmaPs_Config *CfgPtr = NULL;
-
- int i;
-
- for (i = 0; i < XPAR_XDMAPS_NUM_INSTANCES; i++) {
- if (XDmaPs_ConfigTable[i].DeviceId == DeviceId) {
- CfgPtr = &XDmaPs_ConfigTable[i];
- break;
- }
- }
-
- return CfgPtr;
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fc/f0b060565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fc/f0b060565243001d18b399c1eb9b3628
deleted file mode 100644
index f101c14..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fc/f0b060565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,341 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xil_testcache.c
-* @addtogroup common_test_utils
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a hbm 07/28/09 Initial release
-* 4.1 asa 05/09/14 Ensured that the address uses for cache test is aligned
-* cache line.
-*
-*
-******************************************************************************/
-#ifdef __ARM__
-#include "xil_cache.h"
-#include "xil_testcache.h"
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#ifdef __aarch64__
-#include "xreg_cortexa53.h"
-#else
-#include "xreg_cortexr5.h"
-#endif
-
-#include "xil_types.h"
-
-extern void xil_printf(const char8 *ctrl1, ...);
-
-#define DATA_LENGTH 128
-
-#ifdef __aarch64__
-static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64)));
-#else
-static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32)));
-#endif
-
-
-/*****************************************************************************/
-/**
-*
-* @brief Perform DCache range related API test such as Xil_DCacheFlushRange
-* and Xil_DCacheInvalidateRange. This test function writes a constant
-* value to the Data array, flushes the range, writes a new value, then
-* invalidates the corresponding range.
-*
-* @return
-* - -1 is returned for a failure
-* - 0 is returned for a pass
-*
-*****************************************************************************/
-s32 Xil_TestDCacheRange(void)
-{
- s32 Index;
- s32 Status = 0;
- u32 CtrlReg;
- INTPTR Value;
-
- xil_printf("-- Cache Range Test --\n\r");
-
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0xA0A00505;
-
- xil_printf(" initialize Data done:\r\n");
-
- Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
-
- xil_printf(" flush range done\r\n");
-
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
-
- Status = 0;
-
- for (Index = 0; Index < DATA_LENGTH; Index++) {
- Value = Data[Index];
- if (Value != 0xA0A00505) {
- Status = -1;
- xil_printf("Data[%d] = %x\r\n", Index, Value);
- break;
- }
- }
-
- if (!Status) {
- xil_printf(" Flush worked\r\n");
- }
- else {
- xil_printf("Error: flush dcache range not working\r\n");
- }
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0xA0A0C505;
-
-
-
- Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
-
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = Index + 3;
-
- Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
-
- xil_printf(" invalidate dcache range done\r\n");
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0xA0A0A05;
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
-
- Status = 0;
-
- for (Index = 0; Index < DATA_LENGTH; Index++) {
- Value = Data[Index];
- if (Value != 0xA0A0A05) {
- Status = -1;
- xil_printf("Data[%d] = %x\r\n", Index, Value);
- break;
- }
- }
-
-
- if (!Status) {
- xil_printf(" Invalidate worked\r\n");
- }
- else {
- xil_printf("Error: Invalidate dcache range not working\r\n");
- }
- xil_printf("-- Cache Range Test Complete --\r\n");
- return Status;
-
-}
-
-/*****************************************************************************/
-/**
-* @brief Perform DCache all related API test such as Xil_DCacheFlush and
-* Xil_DCacheInvalidate. This test function writes a constant value
-* to the Data array, flushes the DCache, writes a new value,
-* then invalidates the DCache.
-*
-* @return
-* - 0 is returned for a pass
-* - -1 is returned for a failure
-*****************************************************************************/
-s32 Xil_TestDCacheAll(void)
-{
- s32 Index;
- s32 Status;
- INTPTR Value;
- u32 CtrlReg;
-
- xil_printf("-- Cache All Test --\n\r");
-
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0x50500A0A;
- xil_printf(" initialize Data done:\r\n");
-
- Xil_DCacheFlush();
- xil_printf(" flush all done\r\n");
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
- Status = 0;
-
- for (Index = 0; Index < DATA_LENGTH; Index++) {
- Value = Data[Index];
-
- if (Value != 0x50500A0A) {
- Status = -1;
- xil_printf("Data[%d] = %x\r\n", Index, Value);
- break;
- }
- }
-
- if (!Status) {
- xil_printf(" Flush all worked\r\n");
- }
- else {
- xil_printf("Error: Flush dcache all not working\r\n");
- }
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0x505FFA0A;
-
- Xil_DCacheFlush();
-
-
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = Index + 3;
-
- Xil_DCacheInvalidate();
-
- xil_printf(" invalidate all done\r\n");
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
- for (Index = 0; Index < DATA_LENGTH; Index++)
- Data[Index] = 0x50CFA0A;
- dsb();
- #ifdef __aarch64__
- CtrlReg = mfcp(SCTLR_EL3);
- CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
- mtcp(SCTLR_EL3,CtrlReg);
- #else
- CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
- CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
- mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
- #endif
- dsb();
- Status = 0;
-
- for (Index = 0; Index < DATA_LENGTH; Index++) {
- Value = Data[Index];
- if (Value != 0x50CFA0A) {
- Status = -1;
- xil_printf("Data[%d] = %x\r\n", Index, Value);
- break;
- }
- }
-
- if (!Status) {
- xil_printf(" Invalidate all worked\r\n");
- }
- else {
- xil_printf("Error: Invalidate dcache all not working\r\n");
- }
-
- xil_printf("-- DCache all Test Complete --\n\r");
-
- return Status;
-}
-
-/*****************************************************************************/
-/**
-* @brief Perform Xil_ICacheInvalidateRange() on a few function pointers.
-*
-* @return
-* - 0 is returned for a pass
-*
-* @note The function will hang if it fails.
-*****************************************************************************/
-s32 Xil_TestICacheRange(void)
-{
-
- Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024);
- Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024);
- Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024);
-
- xil_printf("-- Invalidate icache range done --\r\n");
-
- return 0;
-}
-
-/*****************************************************************************/
-/**
-* @brief Perform Xil_ICacheInvalidate() on a few function pointers.
-*
-* @return
-* - 0 is returned for a pass
-*
-* @note The function will hang if it fails.
-*****************************************************************************/
-s32 Xil_TestICacheAll(void)
-{
- Xil_ICacheInvalidate();
- xil_printf("-- Invalidate icache all done --\r\n");
- return 0;
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fc/f0e74e545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fc/f0e74e545243001d18b399c1eb9b3628
deleted file mode 100644
index d1bd537..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fc/f0e74e545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,320 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xparameters_ps.h
-*
-* This file contains the address definitions for the hard peripherals
-* attached to the ARM Cortex A9 core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 1.00a ecm/sdm 02/01/10 Initial version
-* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
-* driver tcl
-* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
-* 6.6 srm 10/18/17 Added ARMA9 macro to identify CortexA9
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 6.0 mus 27/07/16 Consolidated exceptions for a53,a9 and r5
-* processors and added Xil_UndefinedExceptionHandler
-* for a53 32 bit and r5 as well.
-* 6.4 mus 08/06/17 Updated debug prints to replace %x with the %lx, to
-* fix the warnings.
-* 6.7 mna 26/04/18 Add an API to obtain a corresponding
-* Xil_ExceptionHandler entry from XExc_VectorTable.
-* 6.7 asa 18/05/18 Fix bugs in the API Xil_GetExceptionRegisterHandler.
-* 7.0 mus 07/03/19 Tweak Xil_ExceptionRegisterHandler and
-* Xil_GetExceptionRegisterHandler to support legacy
-* examples for Cortexa72 EL3 exception level.
-* 7.3 mus 07/27/20 Updated Xil_ExceptionRegisterHandler and
-* Xil_GetExceptionRegisterHandler to ignore
-* Exception_id, only if its pointing to IRQ.
-* It fixes CR#1069524
-*
-*
-*
-*****************************************************************************/
-
-/***************************** Include Files ********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_exception.h"
-#include "xpseudo_asm.h"
-#include "xdebug.h"
-/************************** Constant Definitions ****************************/
-
-/**************************** Type Definitions ******************************/
-
-typedef struct {
- Xil_ExceptionHandler Handler;
- void *Data;
-} XExc_VectorTableEntry;
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-/************************** Function Prototypes *****************************/
-static void Xil_ExceptionNullHandler(void *Data);
-/************************** Variable Definitions *****************************/
-/*
- * Exception vector table to store handlers for each exception vector.
- */
-#if defined (__aarch64__)
-XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
-{
- {Xil_ExceptionNullHandler, NULL},
- {Xil_SyncAbortHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
- {Xil_SErrorAbortHandler, NULL},
-
-};
-#else
-XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
-{
- {Xil_ExceptionNullHandler, NULL},
- {Xil_UndefinedExceptionHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
- {Xil_PrefetchAbortHandler, NULL},
- {Xil_DataAbortHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
- {Xil_ExceptionNullHandler, NULL},
-};
-#endif
-#if !defined (__aarch64__)
-u32 DataAbortAddr; /* Address of instruction causing data abort */
-u32 PrefetchAbortAddr; /* Address of instruction causing prefetch abort */
-u32 UndefinedExceptionAddr; /* Address of instruction causing Undefined
- exception */
-#endif
-
-/*****************************************************************************/
-
-/****************************************************************************/
-/**
-*
-* This function is a stub Handler that is the default Handler that gets called
-* if the application has not setup a Handler for a specific exception. The
-* function interface has to match the interface specified for a Handler even
-* though none of the arguments are used.
-*
-* @param Data is unused by this function.
-*
-* @return None.
-*
-*****************************************************************************/
-static void Xil_ExceptionNullHandler(void *Data)
-{
- (void) Data;
-DieLoop: goto DieLoop;
-}
-
-/****************************************************************************/
-/**
-* @brief The function is a common API used to initialize exception handlers
-* across all supported arm processors. For ARM Cortex-A53, Cortex-R5,
-* and Cortex-A9, the exception handlers are being initialized
-* statically and this function does not do anything.
-* However, it is still present to take care of backward compatibility
-* issues (in earlier versions of BSPs, this API was being used to
-* initialize exception handlers).
-*
-* @return None.
-*
-*****************************************************************************/
-void Xil_ExceptionInit(void)
-{
- return;
-}
-
-/*****************************************************************************/
-/**
-* @brief Register a handler for a specific exception. This handler is being
-* called when the processor encounters the specified exception.
-*
-* @param Exception_id contains the ID of the exception source and should
-* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
-* See xil_exception.h for further information.
-* @param Handler to the Handler for that exception.
-* @param Data is a reference to Data that will be passed to the
-* Handler when it gets called.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler Handler,
- void *Data)
-{
-#if defined (versal) && !defined(ARMR5) && EL3
- if ( XIL_EXCEPTION_ID_IRQ_INT == Exception_id )
- {
- /*
- * Cortexa72 processor in versal is coupled with GIC-500, and
- * GIC-500 supports only FIQ at EL3. Hence, tweaking this API
- * to act on IRQ, if Exception_id is pointing to IRQ
- */
- Exception_id = XIL_EXCEPTION_ID_FIQ_INT;
- }
-#endif
- XExc_VectorTable[Exception_id].Handler = Handler;
- XExc_VectorTable[Exception_id].Data = Data;
-}
-
-/*****************************************************************************/
-/**
-* @brief Get a handler for a specific exception. This handler is being
-* called when the processor encounters the specified exception.
-*
-* @param Exception_id contains the ID of the exception source and should
-* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
-* See xil_exception.h for further information.
-* @param Handler to the Handler for that exception.
-* @param Data is a reference to Data that will be passed to the
-* Handler when it gets called.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_GetExceptionRegisterHandler(u32 Exception_id,
- Xil_ExceptionHandler *Handler,
- void **Data)
-{
-#if defined (versal) && !defined(ARMR5) && EL3
- if ( XIL_EXCEPTION_ID_IRQ_INT == Exception_id )
- {
- /*
- * Cortexa72 processor in versal is coupled with GIC-500, and
- * GIC-500 supports only FIQ at EL3. Hence, tweaking this API
- * to act on IRQ, if Exception_id is pointing to IRQ
- */
-
- Exception_id = XIL_EXCEPTION_ID_FIQ_INT;
- }
-#endif
-
- *Handler = XExc_VectorTable[Exception_id].Handler;
- *Data = XExc_VectorTable[Exception_id].Data;
-}
-
-/*****************************************************************************/
-/**
-*
-* @brief Removes the Handler for a specific exception Id. The stub Handler
-* is then registered for this exception Id.
-*
-* @param Exception_id contains the ID of the exception source and should
-* be in the range of 0 to XIL_EXCEPTION_ID_LAST.
-* See xil_exception.h for further information.
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_ExceptionRemoveHandler(u32 Exception_id)
-{
- Xil_ExceptionRegisterHandler(Exception_id,
- Xil_ExceptionNullHandler,
- NULL);
-}
-
-#if defined (__aarch64__)
-/*****************************************************************************/
-/**
-*
-* Default Synchronous abort handler which prints a debug message on console if
-* Debug flag is enabled
-*
-* @return None.
-*
-****************************************************************************/
-
-void Xil_SyncAbortHandler(void *CallBackRef){
- (void) CallBackRef;
- xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
- while(1) {
- ;
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Default SError abort handler which prints a debug message on console if
-* Debug flag is enabled
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_SErrorAbortHandler(void *CallBackRef){
- (void) CallBackRef;
- xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
- while(1) {
- ;
- }
-}
-#else
-/*****************************************************************************/
-/**
-*
-* Default Data abort handler which prints data fault status register through
-* which information about data fault can be acquired
-*
-* @return None.
-*
-****************************************************************************/
-
-void Xil_DataAbortHandler(void *CallBackRef){
- (void) CallBackRef;
-#ifdef DEBUG
- u32 FaultStatus;
-
- xdbg_printf(XDBG_DEBUG_ERROR, "Data abort \n");
- #ifdef __GNUC__
- FaultStatus = mfcp(XREG_CP15_DATA_FAULT_STATUS);
- #elif defined (__ICCARM__)
- mfcp(XREG_CP15_DATA_FAULT_STATUS,FaultStatus);
- #else
- { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS);
- FaultStatus = Reg; }
- #endif
- xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register %lx\n",FaultStatus);
- xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Data abort %lx\n",DataAbortAddr);
-#endif
- while(1) {
- ;
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Default Prefetch abort handler which prints prefetch fault status register through
-* which information about instruction prefetch fault can be acquired
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_PrefetchAbortHandler(void *CallBackRef){
- (void) CallBackRef;
-#ifdef DEBUG
- u32 FaultStatus;
-
- xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort \n");
- #ifdef __GNUC__
- FaultStatus = mfcp(XREG_CP15_INST_FAULT_STATUS);
- #elif defined (__ICCARM__)
- mfcp(XREG_CP15_INST_FAULT_STATUS,FaultStatus);
- #else
- { volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS);
- FaultStatus = Reg; }
- #endif
- xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register %lx\n",FaultStatus);
- xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Prefetch abort %lx\n",PrefetchAbortAddr);
-#endif
- while(1) {
- ;
- }
-}
-/*****************************************************************************/
-/**
-*
-* Default undefined exception handler which prints address of the undefined
-* instruction if debug prints are enabled
-*
-* @return None.
-*
-****************************************************************************/
-void Xil_UndefinedExceptionHandler(void *CallBackRef){
- (void) CallBackRef;
- xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %lx\n",UndefinedExceptionAddr);
- while(1) {
- ;
- }
-}
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fd/40c2d1565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fd/40c2d1565243001d18b399c1eb9b3628
deleted file mode 100644
index d8aef59..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fd/40c2d1565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,169 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xenv.h
-*
-* Defines common services that are typically found in a host operating.
-* environment. This include file simply includes an OS specific file based
-* on the compile-time constant BUILD_ENV_*, where * is the name of the target
-* environment.
-*
-* All services are defined as macros.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b ch 10/24/02 Added XENV_LINUX
-* 1.00a rmm 04/17/02 First release
-*
-*
-******************************************************************************/
-
-/**
- *@cond nocomments
- */
-
-#ifndef XENV_H /* prevent circular inclusions */
-#define XENV_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * Select which target environment we are operating under
- */
-
-/* VxWorks target environment */
-#if defined XENV_VXWORKS
-#include "xenv_vxworks.h"
-
-/* Linux target environment */
-#elif defined XENV_LINUX
-#include "xenv_linux.h"
-
-/* Unit test environment */
-#elif defined XENV_UNITTEST
-#include "ut_xenv.h"
-
-/* Integration test environment */
-#elif defined XENV_INTTEST
-#include "int_xenv.h"
-
-/* Standalone environment selected */
-#else
-#include "xenv_standalone.h"
-#endif
-
-
-/*
- * The following comments specify the types and macro wrappers that are
- * expected to be defined by the target specific header files
- */
-
-/**************************** Type Definitions *******************************/
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP
- *
- * A structure that contains a time stamp used by other time stamp macros
- * defined below. This structure is processor dependent.
- */
-
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
- *
- * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
- *
- * Copies a non-overlapping block of memory.
- *
- * @param DestPtr is the destination address to copy data to.
- * @param SrcPtr is the source address to copy data from.
- * @param Bytes is the number of bytes to copy.
- *
- * @return None
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
- *
- * Fills an area of memory with constant data.
- *
- * @param DestPtr is the destination address to set.
- * @param Data contains the value to set.
- * @param Bytes is the number of bytes to set.
- *
- * @return None
- */
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
- *
- * Samples the processor's or external timer's time base counter.
- *
- * @param StampPtr is the storage for the retrieved time stamp.
- *
- * @return None
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
- *
- * Computes the delta between the two time stamps.
- *
- * @param Stamp1Ptr - First sampled time stamp.
- * @param Stamp1Ptr - Sedond sampled time stamp.
- *
- * @return An unsigned int value with units of microseconds.
- */
-
-/*****************************************************************************/
-/**
- *
- * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
- *
- * Computes the delta between the two time stamps.
- *
- * @param Stamp1Ptr - First sampled time stamp.
- * @param Stamp1Ptr - Sedond sampled time stamp.
- *
- * @return An unsigned int value with units of milliseconds.
- */
-
-/*****************************************************************************//**
- *
- * XENV_USLEEP(unsigned delay)
- *
- * Delay the specified number of microseconds.
- *
- * @param delay is the number of microseconds to delay.
- *
- * @return None
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-
-/**
- *@endcond
- */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fd/41d5ad585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fd/41d5ad585243001d18b399c1eb9b3628
deleted file mode 100644
index 4c9faef..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fd/41d5ad585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,16 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-
-#include
-#include
-
-/*
- * abort -- go out via exit...
- */
-__attribute__((weak)) void abort(void)
-{
- _exit(1);
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fd/b0b72a575243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fd/b0b72a575243001d18b399c1eb9b3628
deleted file mode 100644
index dfb1d2d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fd/b0b72a575243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,224 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xadcps_intr.c
-* @addtogroup xadcps_v2_6
-* @{
-*
-* This file contains interrupt handling API functions of the XADC
-* device.
-*
-* The device must be configured at hardware build time to support interrupt
-* for all the functions in this file to work.
-*
-* Refer to xadcps.h header file and device specification for more information.
-*
-* @note
-*
-* Calling the interrupt functions without including the interrupt component will
-* result in asserts if asserts are enabled, and will result in a unpredictable
-* behavior if the asserts are not enabled.
-*
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ----- -------- -----------------------------------------------------
-* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
-*
-*
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xadcps.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/************************** Variable Definitions *****************************/
-
-
-/****************************************************************************/
-/**
-*
-* This function enables the specified interrupts in the device.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Mask is the bit-mask of the interrupts to be enabled.
-* Bit positions of 1 will be enabled. Bit positions of 0 will
-* keep the previous setting. This mask is formed by OR'ing
-* XADCPS_INTX_* bits defined in xadcps_hw.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Disable the specified interrupts in the IPIER.
- */
- RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
- XADCPS_INT_MASK_OFFSET);
- RegValue &= ~(Mask & XADCPS_INTX_ALL_MASK);
- XAdcPs_WriteReg(InstancePtr->Config.BaseAddress,
- XADCPS_INT_MASK_OFFSET,
- RegValue);
-}
-
-
-/****************************************************************************/
-/**
-*
-* This function disables the specified interrupts in the device.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Mask is the bit-mask of the interrupts to be disabled.
-* Bit positions of 1 will be disabled. Bit positions of 0 will
-* keep the previous setting. This mask is formed by OR'ing
-* XADCPS_INTX_* bits defined in xadcps_hw.h.
-*
-* @return None.
-*
-* @note None
-*
-*****************************************************************************/
-void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Enable the specified interrupts in the IPIER.
- */
- RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
- XADCPS_INT_MASK_OFFSET);
- RegValue |= (Mask & XADCPS_INTX_ALL_MASK);
- XAdcPs_WriteReg(InstancePtr->Config.BaseAddress,
- XADCPS_INT_MASK_OFFSET,
- RegValue);
-}
-/****************************************************************************/
-/**
-*
-* This function returns the enabled interrupts read from the Interrupt Mask
-* Register (IPIER). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h to
-* interpret the returned value.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return A 32-bit value representing the contents of the I.
-*
-* @note None.
-*
-*****************************************************************************/
-u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Return the value read from the Interrupt Enable Register.
- */
- return (~ XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
- XADCPS_INT_MASK_OFFSET) & XADCPS_INTX_ALL_MASK);
-}
-
-/****************************************************************************/
-/**
-*
-* This function returns the interrupt status read from Interrupt Status
-* Register(IPISR). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h
-* to interpret the returned value.
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-*
-* @return A 32-bit value representing the contents of the IPISR.
-*
-* @note The device must be configured at hardware build time to include
-* interrupt component for this function to work.
-*
-*****************************************************************************/
-u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr)
-{
- /*
- * Assert the arguments.
- */
- Xil_AssertNonvoid(InstancePtr != NULL);
- Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Return the value read from the Interrupt Status register.
- */
- return XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
- XADCPS_INT_STS_OFFSET) & XADCPS_INTX_ALL_MASK;
-}
-
-/****************************************************************************/
-/**
-*
-* This function clears the specified interrupts in the Interrupt Status
-* Register (IPISR).
-*
-* @param InstancePtr is a pointer to the XAdcPs instance.
-* @param Mask is the bit-mask of the interrupts to be cleared.
-* Bit positions of 1 will be cleared. Bit positions of 0 will not
-* change the previous interrupt status. This mask is formed by
-* OR'ing XADCPS_IPIXR_* bits which are defined in xadcps_hw.h.
-*
-* @return None.
-*
-* @note None.
-*
-*****************************************************************************/
-void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask)
-{
- u32 RegValue;
-
- /*
- * Assert the arguments.
- */
- Xil_AssertVoid(InstancePtr != NULL);
- Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-
- /*
- * Clear the specified interrupts in the Interrupt Status register.
- */
- RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
- XADCPS_INT_STS_OFFSET);
- RegValue &= (Mask & XADCPS_INTX_ALL_MASK);
- XAdcPs_WriteReg(InstancePtr->Config.BaseAddress, XADCPS_INT_STS_OFFSET,
- RegValue);
-
-}
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fd/f2c953545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fd/f2c953545243001d18b399c1eb9b3628
deleted file mode 100644
index e79ba0d..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fd/f2c953545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,788 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xqspips.h
-* @addtogroup qspips_v3_9
-* @{
-* @details
-*
-* This file contains the implementation of the XQspiPs driver. It supports only
-* master mode. User documentation for the driver functions is contained in this
-* file in the form of comment blocks at the front of each function.
-*
-* A QSPI device connects to an QSPI bus through a 4-wire serial interface.
-* The QSPI bus is a full-duplex, synchronous bus that facilitates communication
-* between one master and one slave. The device is always full-duplex,
-* which means that for every byte sent, one is received, and vice-versa.
-* The master controls the clock, so it can regulate when it wants to
-* send or receive data. The slave is under control of the master, it must
-* respond quickly since it has no control of the clock and must send/receive
-* data as fast or as slow as the master does.
-*
-* Linear Mode
-* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller�s
-* functionality by adding a linear addressing scheme that allows the SPI flash
-* memory subsystem to behave like a typical ROM device. The new feature hides
-* the normal SPI protocol from a master reading from the SPI flash memory. The
-* feature improves both the user friendliness and the overall read memory
-* throughput over that of the current Quad-SPI Controller by lessening the
-* amount of software overheads required and by the use of the faster AXI
-* interface.
-*
-* Initialization & Configuration
-*
-* The XQspiPs_Config structure is used by the driver to configure itself. This
-* configuration structure is typically created by the tool-chain based on HW
-* build properties.
-*
-* To support multiple runtime loading and initialization strategies employed by
-* various operating systems, the driver instance can be initialized in the
-* following way:
-* - XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find
-* static configuration structure defined in xqspips_g.c. This is setup
-* by the tools. For some operating systems the config structure will be
-* initialized by the software and this call is not needed.
-* - XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
-* configuration structure provided by the caller. If running in a system
-* with address translation, the provided virtual memory base address
-* replaces the physical address present in the configuration structure.
-*
-* Multiple Masters
-*
-* More than one master can exist, but arbitration is the responsibility of
-* the higher layer software. The device driver does not perform any type of
-* arbitration.
-*
-* Modes of Operation
-*
-* There are four modes to perform a data transfer and the selection of a mode
-* is based on Chip Select(CS) and Start. These two options individually, can
-* be controlled either by software(Manual) or hardware(Auto).
-* - Auto CS: Chip select is automatically asserted as soon as the first word
-* is written into the TXFIFO and de asserted when the TXFIFO becomes
-* empty
-* - Manual CS: Software must assert and de assert CS.
-* - Auto Start: Data transmission starts as soon as there is data in the
-* TXFIFO and stalls when the TXFIFO is empty
-* - Manual Start: Software must start data transmission at the beginning of
-* the transaction or whenever the TXFIFO has become empty
-*
-* The preferred combination is Manual CS and Auto Start.
-* In this combination, the software asserts CS before loading any data into
-* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
-* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
-* data is available. If no further data, software disables CS.
-*
-* Risks/challenges of other combinations:
-* - Manual CS and Manual Start: Manual Start bit should be set after each
-* TXFIFO write otherwise there could be a race condition where the TXFIFO
-* becomes empty before the new word is written. In that case the
-* transmission stops.
-* - Auto CS with Manual or Auto Start: It is very difficult for software to
-* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted.
-* This results in a single transaction to be split into multiple pieces each
-* with its own chip select. This will result in garbage data to be sent.
-*
-* Interrupts
-*
-* The user must connect the interrupt handler of the driver,
-* XQspiPs_InterruptHandler, to an interrupt system such that it will be
-* called when an interrupt occurs. This function does not save and restore
-* the processor context such that the user must provide this processing.
-*
-* The driver handles the following interrupts:
-* - Data Transmit Register/FIFO Underflow
-* - Data Receive Register/FIFO Not Empty
-* - Data Transmit Register/FIFO Overwater
-* - Data Receive Register/FIFO Overrun
-*
-* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
-* QSPI device has transmitted the data available to transmit, and now its data
-* register and FIFO is ready to accept more data. The driver uses this
-* interrupt to indicate progress while sending data. The driver may have
-* more data to send, in which case the data transmit register and FIFO is
-* filled for subsequent transmission. When this interrupt arrives and all
-* the data has been sent, the driver invokes the status callback with a
-* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
-* all data has been sent.
-*
-* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
-* as slave, the QSPI device was required to transmit but there was no data
-* available to transmit in the transmit register (or FIFO). This may not
-* be an error if the master is not expecting data. But in the case where
-* the master is expecting data, this serves as a notification of such a
-* condition. The driver reports this condition to the upper layer
-* software through the status handler.
-*
-* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI
-* device received data and subsequently dropped the data because the data
-* receive register and FIFO was full. The driver reports this condition to the
-* upper layer software through the status handler. This likely indicates a
-* problem with the higher layer protocol, or a problem with the slave
-* performance.
-*
-*
-* Polled Operation
-*
-* Transfer in polled mode is supported through a separate interface function
-* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
-* this function blocks until all data has been sent/received.
-*
-* Device Busy
-*
-* Some operations are disallowed when the device is busy. The driver tracks
-* whether a device is busy. The device is considered busy when a data transfer
-* request is outstanding, and is considered not busy only when that transfer
-* completes (or is aborted with a mode fault error).
-*
-* Device Configuration
-*
-* The device can be configured in various ways during the FPGA implementation
-* process. Configuration parameters are stored in the xqspips_g.c file or
-* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry
-* contains configuration information for an QSPI device, including the base
-* address for the device.
-*
-* RTOS Independence
-*
-* This driver is intended to be RTOS and processor independent. It works with
-* physical addresses only. Any needs for dynamic memory management, threads or
-* thread mutual exclusion, virtual memory, or cache control must be satisfied
-* by the layer above this driver.
-*
-* NOTE: This driver was always tested with endianness set to little-endian.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- -------- -----------------------------------------------
-* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
-* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
-* in xparameters.h
-* 2.00a kka 07/25/12 Added a few register defines for CR 670297
-* Removed code related to mode fault for CR 671468
-* The XQspiPs_SetSlaveSelect has been modified to remove
-* the argument of the slave select as the QSPI controller
-* only supports one slave.
-* XQspiPs_GetSlaveSelect API has been removed
-* Added a flag ShiftReadData to the instance structure
-*. and is used in the XQspiPs_GetReadData API.
-* The ShiftReadData Flag indicates whether the data
-* read from the Rx FIFO needs to be shifted
-* in cases where the data is less than 4 bytes
-* Removed the selection for the following options:
-* Master mode (XQSPIPS_MASTER_OPTION) and
-* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
-* as the QSPI driver supports the Master mode
-* and Flash Interface mode and doesnot support
-* Slave mode or the legacy mode.
-* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
-* APIs so that the last argument (IsInst) specifying whether
-* it is instruction or data has been removed. The first byte
-* in the SendBufPtr argument of these APIs specify the
-* instruction to be sent to the Flash Device.
-* This version of the driver fixes CRs 670197/663787/
-* 670297/671468.
-* Added the option for setting the Holdb_dr bit in the
-* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
-* is the option to be used for setting this bit in the
-* configuration register.
-* The XQspiPs_PolledTransfer function has been updated
-* to fill the data to fifo depth.
-* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
-* Added macros for Set/Get Rx Watermark. Changed QSPI
-* Enable/Disable macro argument from BaseAddress to
-* Instance Pointer. Added DelayNss argument to SetDelays
-* and GetDelays API's.
-* Created macros XQspiPs_IsManualStart and
-* XQspiPs_IsManualChipSelect.
-* Changed QSPI transfer logic for polled and interrupt
-* modes to be based on filled tx fifo count and receive
-* based on it. RXNEMPTY interrupt is not used.
-* Added assertions to XQspiPs_LqspiRead function.
-* SetDelays and GetDelays API's include DelayNss parameter.
-* Added defines for DelayNss,Rx Watermark,Interrupts
-* which need write to clear. Removed Read zeros mask from
-* LQSPI Config register. Renamed Fixed burst error to
-* data FSM error in LQSPI Status register.
-*
-* 2.02a hk 05/07/13 Added ConnectionMode to config structure.
-* Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
-* Added enable and disable to the XQspiPs_LqspiRead() function
-* Removed XQspi_Reset() in Set_Options() function when
-* LQSPI_MODE_OPTION is set.
-* Added instructions for bank selection, die erase and
-* flag status register to the flash instruction table
-* Handling for instructions not in flash instruction
-* table added. Checking for Tx FIFO empty when switching from
-* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
-* byte count 3 (spansion), instruction size and TXD register
-* changed accordingly. CR# 712502 and 703869.
-* Added prefix to constant definitions for ConnectionMode
-* Added (\#ifdef linear base address) in the Linear read function.
-* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to
-* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
-* XQspiPs_LqspiRead function. Fix for CR#718141.
-*
-* 2.03a hk 09/17/13 Modified polled and interrupt transfers to make use of
-* thresholds. This is to improve performance.
-* Added API's for QSPI reset and
-* linear mode initialization for boot.
-* Added RX and TX threshold reset to one in XQspiPs_Abort.
-* Added RX threshold reset(1) after transfer in polled and
-* interrupt transfers. Made changes to make sure threshold
-* change is done only when no transfer is in progress.
-* Updated linear init API for parallel and stacked modes.
-* CR#737760.
-* 3.1 hk 08/13/14 When writing to the configuration register, set/reset
-* required bits leaving reserved bits untouched. CR# 796813.
-* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
-* controller does not update FIFO status flags as expected
-* when thresholds are used.
-* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
-* to remove compilation warnings. CR# 868893.
-* ms 03/17/17 Added readme.txt file in examples folder for doxygen
-* generation.
-* ms 04/05/17 Modified Comment lines in functions of qspips
-* examples to recognize it as documentation block
-* and modified filename tag in
-* xqspips_dual_flash_stack_lqspi_example.c to include it in
-* doxygen examples.
-* 3.4 nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file
-* 3.5 tjs 08/21/18 Fixed compilation warnings for the ARMCC.
-* 3.5 tjs 07/16/18 Added support for low density ISSI flash parts.
-* 3.6 akm 03/28/19 Fixed memory leak issue while reading from qspi.(CR#1016357)
-* 3.6 akm 04/15/19 Modified FlashQuadEnable, FlashWrie and FlashErase APIs,
-* to wait for the on going operation to complete before
-* performing the next operation.
-* 3.6 akm 04/15/19 Modified the mask in XQspiPs_GetReadData() API to retrieve
-* configuration register values of both the Flashes in dual
-* parellel connection.
-* 3.7 akm 11/19/19 Fixed Coverity unused value warning in XQspiPs_PolledTransfer()
-* and XQspiPs_Transfer() APIs.
-* 3.7 akm 03/19/20 Modified XQspiPs_PolledTransfer(), XQspiPs_Transfer() and
-* XQspiPs_InterruptHandler() APIs to fill TX FIFO with valid
-* data when RX buffer is not NULL.
-* 3.8 akm 09/02/20 Updated the Makefile to support parallel make execution.
-*
-*
-*
-******************************************************************************/
-#ifndef XQSPIPS_H /* prevent circular inclusions */
-#define XQSPIPS_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xstatus.h"
-#include "xqspips_hw.h"
-#include
-
-/************************** Constant Definitions *****************************/
-
-/** @name Configuration options
- *
- * The following options are supported to enable/disable certain features of
- * an QSPI device. Each of the options is a bit mask, so more than one may be
- * specified.
- *
- *
- * The Active Low Clock option configures the device's clock polarity.
- * Setting this option means the clock is active low and the SCK signal idles
- * high. By default, the clock is active high and SCK idles low.
- *
- * The Clock Phase option configures the QSPI device for one of two
- * transfer formats. A clock phase of 0, the default, means data is valid on
- * the first SCK edge (rising or falling) after the slave select (SS) signal
- * has been asserted. A clock phase of 1 means data is valid on the second SCK
- * edge (rising or falling) after SS has been asserted.
- *
- *
- * The QSPI Force Slave Select option is used to enable manual control of
- * the slave select signal.
- * 0: The SPI_SS signal is controlled by the QSPI controller during
- * transfers. (Default)
- * 1: The SPI_SS signal is forced active (driven low) regardless of any
- * transfers in progress.
- *
- * NOTE: The driver will handle setting and clearing the Slave Select when
- * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
- * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the
- * processor cannot empty and refill the FIFOs before the TX FIFO is empty
- * When the QSPI hardware is controlling the Slave Select signals, this
- * will cause slave to be de-selected and terminate the transfer.
- *
- * The Manual Start option is used to enable manual control of
- * the Start command to perform data transfer.
- * 0: The Start command is controlled by the QSPI controller during
- * transfers(Default). Data transmission starts as soon as there is data in
- * the TXFIFO and stalls when the TXFIFO is empty
- * 1: The Start command must be issued by software to perform data transfer.
- * Bit 15 of Configuration register is used to issue Start command. This bit
- * must be set whenever TXFIFO is filled with new data.
- *
- * NOTE: The driver will set the Manual Start Enable bit in Configuration
- * Register, if Manual Start option is selected. Software will issue
- * Manual Start command whenever TXFIFO is filled with data. When there is
- * no further data, driver will clear the Manual Start Enable bit.
- *
- * @{
- */
-#define XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2 /**< Active Low Clock option */
-#define XQSPIPS_CLK_PHASE_1_OPTION 0x4 /**< Clock Phase one option */
-#define XQSPIPS_FORCE_SSELECT_OPTION 0x10 /**< Force Slave Select */
-#define XQSPIPS_MANUAL_START_OPTION 0x20 /**< Manual Start enable */
-#define XQSPIPS_LQSPI_MODE_OPTION 0x80 /**< Linear QPSI mode */
-#define XQSPIPS_HOLD_B_DRIVE_OPTION 0x100 /**< Drive HOLD_B Pin */
-/*@}*/
-
-
-/** @name QSPI Clock Prescaler options
- * The QSPI Clock Prescaler Configuration bits are used to program master mode
- * bit rate. The bit rate can be programmed in divide-by-two decrements from
- * pclk/2 to pclk/256.
- *
- * @{
- */
-#define XQSPIPS_CLK_PRESCALE_2 0x00 /**< PCLK/2 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_4 0x01 /**< PCLK/4 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_8 0x02 /**< PCLK/8 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_16 0x03 /**< PCLK/16 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_32 0x04 /**< PCLK/32 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_64 0x05 /**< PCLK/64 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_128 0x06 /**< PCLK/128 Prescaler */
-#define XQSPIPS_CLK_PRESCALE_256 0x07 /**< PCLK/256 Prescaler */
-
-/*@}*/
-
-
-/** @name Callback events
- *
- * These constants specify the handler events that are passed to
- * a handler from the driver. These constants are not bit masks such that
- * only one will be passed at a time to the handler.
- *
- * @{
- */
-#define XQSPIPS_EVENT_TRANSFER_DONE 2 /**< Transfer done */
-#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
-#define XQSPIPS_EVENT_RECEIVE_OVERRUN 4 /**< Receive data loss because
- * RX FIFO full
- */
-/*@}*/
-
-/** @name Flash commands
- *
- * The following constants define most of the commands supported by flash
- * devices. Users can add more commands supported by the flash devices
- *
- * @{
- */
-#define XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */
-#define XQSPIPS_FLASH_OPCODE_PP 0x02 /* Page program */
-#define XQSPIPS_FLASH_OPCODE_NORM_READ 0x03 /* Normal read data bytes */
-#define XQSPIPS_FLASH_OPCODE_WRDS 0x04 /* Write disable */
-#define XQSPIPS_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */
-#define XQSPIPS_FLASH_OPCODE_WREN 0x06 /* Write enable */
-#define XQSPIPS_FLASH_OPCODE_FAST_READ 0x0B /* Fast read data bytes */
-#define XQSPIPS_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */
-#define XQSPIPS_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */
-#define XQSPIPS_FLASH_OPCODE_DUAL_READ 0x3B /* Dual read data bytes */
-#define XQSPIPS_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */
-#define XQSPIPS_FLASH_OPCODE_QUAD_READ 0x6B /* Quad read data bytes */
-#define XQSPIPS_FLASH_OPCODE_ERASE_SUS 0x75 /* Erase suspend */
-#define XQSPIPS_FLASH_OPCODE_ERASE_RES 0x7A /* Erase resume */
-#define XQSPIPS_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */
-#define XQSPIPS_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */
-#define XQSPIPS_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/
-#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */
-#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */
-#define XQSPIPS_FLASH_OPCODE_BRWR 0x17 /* Bank Register Write */
-#define XQSPIPS_FLASH_OPCODE_BRRD 0x16 /* Bank Register Read */
-/* Extende Address Register Write - Micron's equivalent of Bank Register */
-#define XQSPIPS_FLASH_OPCODE_EARWR 0xC5
-/* Extende Address Register Read - Micron's equivalent of Bank Register */
-#define XQSPIPS_FLASH_OPCODE_EARRD 0xC8
-#define XQSPIPS_FLASH_OPCODE_DIE_ERASE 0xC4
-#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR 0x70
-#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR 0x50
-#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG 0xE8 /* Lock Reg Read */
-#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG 0xE5 /* Lock Reg Write */
-
-/*@}*/
-
-/** @name Instruction size
- *
- * The following constants define numbers 1 to 4.
- * Used to identify whether TXD0,1,2 or 3 is to be used.
- *
- * @{
- */
-#define XQSPIPS_SIZE_ONE 1
-#define XQSPIPS_SIZE_TWO 2
-#define XQSPIPS_SIZE_THREE 3
-#define XQSPIPS_SIZE_FOUR 4
-
-/*@}*/
-
-/** @name ConnectionMode
- *
- * The following constants are the possible values of ConnectionMode in
- * Config structure.
- *
- * @{
- */
-#define XQSPIPS_CONNECTION_MODE_SINGLE 0
-#define XQSPIPS_CONNECTION_MODE_STACKED 1
-#define XQSPIPS_CONNECTION_MODE_PARALLEL 2
-
-/*@}*/
-
-/** @name FIFO threshold value
- *
- * This is the Rx FIFO threshold (in words) that was found to be most
- * optimal in terms of performance
- *
- * @{
- */
-#define XQSPIPS_RXFIFO_THRESHOLD_OPT 32
-
-/*@}*/
-
-/**************************** Type Definitions *******************************/
-/**
- * The handler data type allows the user to define a callback function to
- * handle the asynchronous processing for the QSPI device. The application
- * using this driver is expected to define a handler of this type to support
- * interrupt driven mode. The handler executes in an interrupt context, so
- * only minimal processing should be performed.
- *
- * @param CallBackRef is the callback reference passed in by the upper
- * layer when setting the callback functions, and passed back to
- * the upper layer when the callback is invoked. Its type is
- * not important to the driver, so it is a void pointer.
- * @param StatusEvent holds one or more status events that have occurred.
- * See the XQspiPs_SetStatusHandler() for details on the status
- * events that can be passed in the callback.
- * @param ByteCount indicates how many bytes of data were successfully
- * transferred. This may be less than the number of bytes
- * requested if the status event indicates an error.
- */
-typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
- unsigned ByteCount);
-
-/**
- * This typedef contains configuration information for the device.
- */
-typedef struct {
- u16 DeviceId; /**< Unique ID of device */
- u32 BaseAddress; /**< Base address of the device */
- u32 InputClockHz; /**< Input clock frequency */
- u8 ConnectionMode; /**< Single, Stacked and Parallel mode */
-} XQspiPs_Config;
-
-/**
- * The XQspiPs driver instance data. The user is required to allocate a
- * variable of this type for every QSPI device in the system. A pointer
- * to a variable of this type is then passed to the driver API functions.
- */
-typedef struct {
- XQspiPs_Config Config; /**< Configuration structure */
- u32 IsReady; /**< Device is initialized and ready */
-
- u8 *SendBufferPtr; /**< Buffer to send (state) */
- u8 *RecvBufferPtr; /**< Buffer to receive (state) */
- int RequestedBytes; /**< Number of bytes to transfer (state) */
- int RemainingBytes; /**< Number of bytes left to transfer(state) */
- u32 IsBusy; /**< A transfer is in progress (state) */
- XQspiPs_StatusHandler StatusHandler;
- void *StatusRef; /**< Callback reference for status handler */
- u32 ShiftReadData; /**< Flag to indicate whether the data
- * read from the Rx FIFO needs to be shifted
- * in cases where the data is less than 4
- * bytes
- */
-} XQspiPs;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/****************************************************************************/
-/*
-*
-* Check in OptionsTable if Manual Start Option is enabled or disabled.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return
-* - TRUE if option is set
-* - FALSE if option is not set
-*
-* @note C-Style signature:
-* u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr);
-*
-*****************************************************************************/
-#define XQspiPs_IsManualStart(InstancePtr) \
- ((XQspiPs_GetOptions(InstancePtr) & \
- XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
-
-/****************************************************************************/
-/*
-*
-* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
-*
-* @param InstancePtr is a pointer to the XSpiPs instance.
-*
-* @return
-* - TRUE if option is set
-* - FALSE if option is not set
-*
-* @note C-Style signature:
-* u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr);
-*
-*****************************************************************************/
-#define XQspiPs_IsManualChipSelect(InstancePtr) \
- ((XQspiPs_GetOptions(InstancePtr) & \
- XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the slave idle count register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written, valid values are
-* 0-255.
-*
-* @return None
-*
-* @note C-Style signature:
-* void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr,
-* u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_SICR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_*
-* constants defined in xqspips_hw.h to interpret the bit-mask returned.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return An 8-bit value representing Slave Idle Count.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetSlaveIdle(InstancePtr) \
- XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_SICR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the transmit FIFO watermark register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written, valid values are 1-63.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr,
-* u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_TXWR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the transmit FIFO watermark register.
-* Valid values are in the range 1-63.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return A 6-bit value representing Tx Watermark level.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetTXWatermark(InstancePtr) \
- XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the receive FIFO watermark register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written, valid values are 1-63.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr,
-* u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_RXWR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the receive FIFO watermark register.
-* Valid values are in the range 1-63.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return A 6-bit value representing Rx Watermark level.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetRXWatermark(InstancePtr) \
- XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
-
-/****************************************************************************/
-/**
-*
-* Enable the device and uninhibit master transactions.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_Enable(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_Enable(InstancePtr) \
- XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
- XQSPIPS_ER_ENABLE_MASK)
-
-/****************************************************************************/
-/**
-*
-* Disable the device.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_Disable(XQspiPs *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_Disable(InstancePtr) \
- XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
-
-/****************************************************************************/
-/**
-*
-* Set the contents of the Linear QSPI Configuration register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-* @param RegisterValue is the value to be written to the Linear QSPI
-* configuration register.
-*
-* @return None.
-*
-* @note C-Style signature:
-* void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr,
-* u32 RegisterValue)
-*
-*****************************************************************************/
-#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \
- XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
- XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
-
-/****************************************************************************/
-/**
-*
-* Get the contents of the Linear QSPI Configuration register.
-*
-* @param InstancePtr is a pointer to the XQspiPs instance.
-*
-* @return A 32-bit value representing the contents of the LQSPI Config
-* register.
-*
-* @note C-Style signature:
-* u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)
-*
-*****************************************************************************/
-#define XQspiPs_GetLqspiConfigReg(InstancePtr) \
- XQspiPs_In32((InstancePtr->Config.BaseAddress) + \
- XQSPIPS_LQSPI_CR_OFFSET)
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Initialization function, implemented in xqspips_sinit.c
- */
-XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
-
-/*
- * Functions implemented in xqspips.c
- */
-int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *Config,
- u32 EffectiveAddr);
-void XQspiPs_Reset(XQspiPs *InstancePtr);
-void XQspiPs_Abort(XQspiPs *InstancePtr);
-
-s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
- u32 ByteCount);
-s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
- u8 *RecvBufPtr, u32 ByteCount);
-int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
- u32 Address, unsigned ByteCount);
-
-int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
-
-void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
- XQspiPs_StatusHandler FuncPtr);
-void XQspiPs_InterruptHandler(void *InstancePtr);
-
-/*
- * Functions for selftest, in xqspips_selftest.c
- */
-int XQspiPs_SelfTest(XQspiPs *InstancePtr);
-
-/*
- * Functions for options, in xqspips_options.c
- */
-s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options);
-u32 XQspiPs_GetOptions(XQspiPs *InstancePtr);
-
-s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
-u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
-
-int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
- u8 DelayAfter, u8 DelayInit);
-void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
- u8 *DelayAfter, u8 *DelayInit);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fe/c1eaab565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fe/c1eaab565243001d18b399c1eb9b3628
deleted file mode 100644
index 5b2d4ed..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/fe/c1eaab565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,83 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2006 - 2020 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-/******************************************************************************
-*
-* File : microblaze_update_icache.s
-* Date : 2003, September 24
-* Company: Xilinx
-* Group : Emerging Software Technologies
-*
-* Summary:
-* Update icache on the microblaze.
-* Takes in three parameters
-* r5 : Cache Tag Line
-* r6 : Cache Data
-* r7 : Lock/Valid information
-* Bit 30 is Lock [ 1 indicates locked ]
-* Bit 31 is Valid [ 1 indicates valid ]
-*
-* --------------------------------------------------------------
-* | Lock | Valid | Effect
-* --------------------------------------------------------------
-* | 0 | 0 | Invalidate Cache
-* | 0 | 1 | Valid, but unlocked cacheline
-* | 1 | 0 | Invalidate Cache, No effect of lock
-* | 1 | 1 | Valid cache. Locked to a
-* | | | particular address
-* --------------------------------------------------------------
-*
-*
-**********************************************************************************/
-#include "xparameters.h"
-
-#ifndef XPAR_MICROBLAZE_ICACHE_LINE_LEN
-#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 1
-#endif
-
- .text
- .globl microblaze_update_icache
- .ent microblaze_update_icache
- .align 2
-microblaze_update_icache:
-#if (XPAR_MICROBLAZE_USE_ICACHE==1) && (XPAR_MICROBLAZE_ALLOW_ICACHE_WR==1)
-
-#if XPAR_MICROBLAZE_ICACHE_LINE_LEN == 1
-
-/* Read the MSR register into a temp register */
- mfs r18, rmsr
-
-/* Clear the icache enable bit to disable the cache
- Register r10,r18 are volatile registers and hence do not need to be saved before use */
- andi r10, r18, ~32
- mts rmsr, r10
-
-/* Update the lock and valid info */
- andi r5, r5, 0xfffffffc
- or r5, r5, r7
-
-/* Update icache */
- wic r5, r6
-
-/* Return */
- rtsd r15, 8
- mts rmsr, r18
-
-#else
-
- /* The only valid usage of this routine for larger cache line lengths is to invalidate an instruction cache line
- So call microblaze_init_icache_range appropriately to do the job */
-
- brid microblaze_init_icache_range
- addik r6, r0, (XPAR_MICROBLAZE_ICACHE_LINE_LEN * 4)
-
- /* We don't have a return instruction here. This is tail call optimization :) */
-
-#endif /* XPAR_MICROBLAZE_ICACHE_LINE_LEN == 1 */
-
-#else
- rtsd r15, 8
- nop
-#endif
- .end microblaze_update_icache
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ff/104afe595243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ff/104afe595243001d18b399c1eb9b3628
deleted file mode 100644
index 484d9d9..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ff/104afe595243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,29 +0,0 @@
-###############################################################################
-# Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
-# SPDX-License-Identifier: MIT
-###############################################################################
-
-COMPILER=
-ARCHIVER=
-CP=cp
-COMPILER_FLAGS=
-LIB=librsa.a
-
-RELEASEDIR=../../../lib
-INCLUDEDIR=../../../include
-INCLUDES=-I./include/ -I${INCLUDEDIR}
-LIBRSA_DIR = .
-
-EXPORT_INCLUDE_DIR = $(LIBRSA_DIR)/include
-
-libs:
- cp $(LIBRSA_DIR)/librsa.a $(RELEASEDIR)
-
-.PHONY: include
-include: xilrsa_includes
-
-xilrsa_includes:
- cp -r ${EXPORT_INCLUDE_DIR}/xilrsa.h ${INCLUDEDIR}
-
-clean:
- rm -rf $(RELEASEDIR)/$(LIB)
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ff/50c228545243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ff/50c228545243001d18b399c1eb9b3628
deleted file mode 100644
index d039278..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ff/50c228545243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,267 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2009 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-*
-* @file xdmaps_hw.h
-* @addtogroup dmaps_v2_8
-* @{
-*
-* This header file contains the hardware interface of an XDmaPs device.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ----------------------------------------------
-* 1.00a hbm 08/18/10 First Release
-* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
-* the maximum number of channels.
-* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
-* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
-* 1.02a sg 05/16/12 Made changes for doxygen
-* 1.06a kpc 07/10/13 Added function prototype
-*
-*
-******************************************************************************/
-
-#ifndef XDMAPS_HW_H /* prevent circular inclusions */
-#define XDMAPS_HW_H /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xil_assert.h"
-#include "xil_io.h"
-
-/************************** Constant Definitions *****************************/
-
-/** @name Register Map
- *
- * Register offsets for the DMAC.
- * @{
- */
-
-#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */
-#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */
-#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */
-#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */
-#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register
- */
-#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */
-#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager
- * Register
- */
-#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register
- */
-#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */
-
-#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */
-/*
- * The offset for the rest of the FTC registers is calculated as
- * FTC0 + dev_chan_num * 4
- */
-#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4)
-
-#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */
-/*
- * The offset for the rest of the CS registers is calculated as
- * CS0 + * dev_chan_num * 0x08
- */
-#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8)
-
-#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA
- * Channel 0
- */
-/*
- * The offset for the rest of the CPC registers is calculated as
- * CPC0 + dev_chan_num * 0x08
- */
-#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8)
-
-#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA
- * Channel 0
- */
-/* The offset for the rest of the SA registers is calculated as
- * SA_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for
- * DMA Channel 0
- */
-/* The offset for the rest of the DA registers is calculated as
- * DA_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for
- * DMA Channel 0
- */
-/*
- * The offset for the rest of the CC registers is calculated as
- * CC_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */
-/*
- * The offset for the rest of the LC0 registers is calculated as
- * LC_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20)
-#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */
-/*
- * The offset for the rest of the LC1 registers is calculated as
- * LC_0 + dev_chan_num * 0x20
- */
-#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20)
-
-#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */
-#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */
-#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */
-#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */
-
-#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */
-#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */
-#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */
-#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */
-#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */
-#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */
-
-#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification
- * Register 0
- */
-#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification
- * Register 1
- */
-#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification
- * Register 2
- */
-#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification
- * Register 3
- */
-#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification
- * Register 0
- */
-#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification
- * Register 1
- */
-#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification
- * Register 2
- */
-#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification
- * Register 3
- */
-
-/*
- * Some useful register masks
- */
-#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */
-#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */
-
-#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */
-
-#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask,
- * llast 3 bits of CS register
- */
-
-#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */
-
-
-/*
- * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register.
- * @b1: Instruction byte 1
- * @b0: Instruction byte 0
- * @ch: Channel number
- * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel
- */
-#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \
- (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1)))
-
-/* @} */
-
-/** @name Control Register
- *
- * The Control register (CR) controls the major functions of the device.
- *
- * Control Register Bit Definition
- */
-
-/* @}*/
-
-
-#define XDMAPS_CHANNELS_PER_DEV 8
-
-
-/** @name Mode Register
- *
- * The mode register (MR) defines the mode of transfer as well as the data
- * format. If this register is modified during transmission or reception,
- * data validity cannot be guaranteed.
- *
- * Mode Register Bit Definition
- * @{
- */
-
-/* @} */
-
-
-/** @name Interrupt Registers
- *
- * Interrupt control logic uses the interrupt enable register (IER) and the
- * interrupt disable register (IDR) to set the value of the bits in the
- * interrupt mask register (IMR). The IMR determines whether to pass an
- * interrupt to the interrupt status register (ISR).
- * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
- * interrupt. IMR and ISR are read only, and IER and IDR are write only.
- * Reading either IER or IDR returns 0x00.
- *
- * All four registers have the same bit definitions.
- *
- * @{
- */
-
-/* @} */
-#define XDMAPS_INTCLR_ALL_MASK 0xFF
-
-#define XDmaPs_ReadReg(BaseAddress, RegOffset) \
- Xil_In32((BaseAddress) + (RegOffset))
-
-/***************************************************************************/
-/**
-* Write a DMAC register.
-*
-* @param BaseAddress contains the base address of the device.
-* @param RegOffset contains the offset from the base address of the device.
-* @param RegisterValue is the value to be written to the register.
-*
-* @return None.
-*
-* @note
-* C-Style signature:
-* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset,
-* u32 RegisterValue)
-******************************************************************************/
-#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
- Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes *****************************/
-/*
- * Perform reset operation to the dmaps interface
- */
-void XDmaPs_ResetHw(u32 BaseAddr);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
-/** @} */
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ff/60b924565243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ff/60b924565243001d18b399c1eb9b3628
deleted file mode 100644
index c73d6b2..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ff/60b924565243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,344 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2018 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file mpu.c
-*
-* This file contains initial configuration of the MPU.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ---------------------------------------------------
-* 7.00 mus 02/20/14 First release
-* 7.00 mus 03/16/19 Updated MPU region to mark DDR regions as
-* memory, based on the DDR size in hdf
-* 7.01 nis 09/02/19 Map AIE region if AIE instance is defined
-* 7.3 asa 09/25/20 Make changes to update the global array
-* Mpu_Config for the static regions created
-* during boot up.
-* 7.5 mus 01/13/21 Removed redundant declaration for Mpu_Config,
-* declaration is present in xil_mpu.h.
-* 7.5 asa 03/07/21 Ensure that Update_MpuConfig_Array stays in .boot section
-* as it is used only during bootup.
-* Add function header to Init_MPU function.
-*
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xreg_cortexr5.h"
-#include "xil_mpu.h"
-#include "xpseudo_asm.h"
-#include "xparameters.h"
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/**************************** Type Definitions *******************************/
-
-/************************** Constant Definitions *****************************/
-
-/************************** Variable Definitions *****************************/
-
-static const struct {
- u64 size;
- unsigned int encoding;
-}region_size[] = {
- { 0x20, REGION_32B },
- { 0x40, REGION_64B },
- { 0x80, REGION_128B },
- { 0x100, REGION_256B },
- { 0x200, REGION_512B },
- { 0x400, REGION_1K },
- { 0x800, REGION_2K },
- { 0x1000, REGION_4K },
- { 0x2000, REGION_8K },
- { 0x4000, REGION_16K },
- { 0x8000, REGION_32K },
- { 0x10000, REGION_64K },
- { 0x20000, REGION_128K },
- { 0x40000, REGION_256K },
- { 0x80000, REGION_512K },
- { 0x100000, REGION_1M },
- { 0x200000, REGION_2M },
- { 0x400000, REGION_4M },
- { 0x800000, REGION_8M },
- { 0x1000000, REGION_16M },
- { 0x2000000, REGION_32M },
- { 0x4000000, REGION_64M },
- { 0x8000000, REGION_128M },
- { 0x10000000, REGION_256M },
- { 0x20000000, REGION_512M },
- { 0x40000000, REGION_1G },
- { 0x80000000, REGION_2G },
- { 0x100000000, REGION_4G },
-};
-
-/************************** Function Prototypes ******************************/
-#if defined (__GNUC__)
-void Init_MPU(void) __attribute__((__section__(".boot")));
-static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib) __attribute__((__section__(".boot")));
-static void Xil_DisableMPURegions(void) __attribute__((__section__(".boot")));
-static inline void Update_MpuConfig_Array(u32 Addr,u32 RegSize,u32 RegNum, u32 Attrib) __attribute__((__section__(".boot")));
-#elif defined (__ICCARM__)
-#pragma default_function_attributes = @ ".boot"
-void Init_MPU(void);
-static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib);
-static void Xil_DisableMPURegions(void);
-#endif
-/*****************************************************************************
-*
-* Initialize MPU for a given address map and Enabled the background Region in
-* MPU with default memory attributes for rest of address range for Cortex R5
-* processor.
-*
-* @param None.
-*
-* @return None.
-*
-*
-******************************************************************************/
-static inline void Update_MpuConfig_Array(u32 Addr,u32 RegSize,u32 RegNum,
- u32 Attrib)
-{
- Mpu_Config[RegNum].RegionStatus = MPU_REG_ENABLED;
- Mpu_Config[RegNum].BaseAddress = Addr;
- Mpu_Config[RegNum].Size = RegSize;
- Mpu_Config[RegNum].Attribute = Attrib;
-}
-
-/*****************************************************************************
-*
-* Initialize MPU for during bootup with predefined region attributes.
-*
-* @param None.
-*
-* @return None.
-*
-*
-******************************************************************************/
-void Init_MPU(void)
-{
- u32 Addr;
- u32 RegSize = 0U;
- u32 Attrib;
- u32 RegNum = 0, i;
- u64 size;
-
- Xil_DisableMPURegions();
-
- Addr = 0x00000000U;
-#ifdef XPAR_AXI_NOC_DDR_LOW_0_BASEADDR
- /* If the DDR is present, configure region as per DDR size */
- size = (XPAR_AXI_NOC_DDR_LOW_0_HIGHADDR - XPAR_AXI_NOC_DDR_LOW_0_BASEADDR) + 1;
- if (size < 0x80000000) {
- /* Lookup the size. */
- for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) {
- if (size <= region_size[i].size) {
- RegSize = region_size[i].encoding;
- break;
- }
- }
- } else {
-#ifdef XPAR_AIE_NUM_INSTANCES
- /* If AIE is mapped, DDR space is reduced to 1GB */
- RegSize = REGION_1G;
-#else
- /* if the DDR size is > 2GB, truncate it to 2GB */
- RegSize = REGION_2G;
-#endif
- }
-#else
- /* For DDRless system, configure region for TCM */
- RegSize = REGION_256K;
-#endif
-
- Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /*
- * 1G of strongly ordered memory from 0x80000000 to 0xBFFFFFFF for PL.
- * 256 MB - LPD-AFI
- * 64 MB - VCU controller
- * 192 MB - FPD-AFI-0
- * 256 MB - FPD-AFI-1
- *
- *
- */
- Addr = 0x80000000;
- RegSize = REGION_1G;
- Attrib = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 512M of device memory from 0xC0000000 to 0xDFFFFFFF for QSPI */
- Addr = 0xC0000000U;
- RegSize = REGION_512M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 256M of device memory from 0xE0000000 to 0xEFFFFFFF for PCIe Low */
- Addr = 0xE0000000U;
- RegSize = REGION_256M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 128M of device memory from 0xF0000000 to 0xF7FFFFFF for PMC */
- Addr = 0xF0000000U;
- RegSize = REGION_128M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 16M of device memory from 0xF8000000 to 0xF8FFFFFF for STM_CORESIGHT */
- Addr = 0xF8000000U;
- RegSize = REGION_16M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 1M of device memory from 0xF9000000 to 0xF90FFFFF for RPU_A53_GIC */
- Addr = 0xF9000000U;
- RegSize = REGION_1M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 16M of device memory from 0xFD000000 to 0xFDFFFFFF for FPS slaves */
- Addr = 0xFD000000U;
- RegSize = REGION_16M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /* 16M of device memory from 0xFE000000 to 0xFEFFFFFF for Upper LPS slaves */
- Addr = 0xFE000000U;
- RegSize = REGION_16M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /*
- * 16M of device memory from 0xFF000000 to 0xFFFFFFFF for Lower LPS slaves,
- * CSU, PMU, TCM, OCM
- */
- Addr = 0xFF000000U;
- RegSize = REGION_16M;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-
- /**
- * 1G of remapped adddress space from 0x40000000 to 0x7FFFFFFF for AIE.
- * The number of allocated MPU regions would be 12, 4 being free for
- * the user.
- * TODO: The value assigned to Addr must be parsed from XSA if the
- * remap address is part of it (currently we are not sure if that's
- * the case).
- */
-#ifdef XPAR_AIE_NUM_INSTANCES
- Addr = 0x40000000U;
- RegSize = REGION_1G;
- Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
- RegNum++;
-#endif
-
- /* 256K of OCM RAM from 0xFFFC0000 to 0xFFFFFFFF marked as normal memory */
- Addr = 0xFFFC0000U;
- RegSize = REGION_256K;
- Attrib = NORM_NSHARED_WB_WA| PRIV_RW_USER_RW ;
- Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
- Update_MpuConfig_Array(Addr,RegSize,RegNum, Attrib);
-
- /* A total of 11 MPU regions are allocated with another 5 being free for users */
-
-}
-
-/*****************************************************************************
-*
-* Set the memory attributes for a section of memory with starting address addr
-* of the region size defined by reg_size having attributes attrib of region number
-* reg_num
-*
-* @param addr is the address for which attributes are to be set.
-* @param attrib specifies the attributes for that memory region.
-* @param reg_size specifies the size for that memory region.
-* @param reg_num specifies the number for that memory region.
-* @return None.
-*
-*
-******************************************************************************/
-static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib)
-{
- u32 Local_reg_size = reg_size;
-
- Local_reg_size = Local_reg_size<<1U;
- Local_reg_size |= REGION_EN;
- dsb();
- mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num);
- isb();
- mtcp(XREG_CP15_MPU_REG_BASEADDR,addr); /* Set base address of a region */
- mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL,attrib); /* Set the control attribute */
- mtcp(XREG_CP15_MPU_REG_SIZE_EN,Local_reg_size); /* set the region size and enable it*/
- dsb();
- isb(); /* synchronize context on this processor */
-}
-
-
-/*****************************************************************************
-*
-* Disable all the MPU regions if any of them is enabled
-*
-* @param None.
-*
-* @return None.
-*
-*
-******************************************************************************/
-static void Xil_DisableMPURegions(void)
-{
- u32 Temp = 0U;
- u32 Index = 0U;
- for (Index = 0; Index <= 15; Index++) {
- mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index);
-#if defined (__GNUC__)
- Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN);
-#elif defined (__ICCARM__)
- mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
-#endif
- Temp &= (~REGION_EN);
- dsb();
- mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
- dsb();
- isb();
- }
-
-}
-
-#if defined (__ICCARM__)
-#pragma default_function_attributes =
-#endif
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ff/704f45585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ff/704f45585243001d18b399c1eb9b3628
deleted file mode 100644
index 2b5b4fd..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ff/704f45585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,323 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2015 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xparameters_ps.h
-*
-* This file contains the address definitions for the hard peripherals
-* attached to the ARM Cortex A53 core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 5.2 pkp 28/05/15 First release
-* 6.0 mus 18/08/16 Defined ARMA53_32 flag
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 pkp 02/20/14 First release
-* 5.04 pkp 02/19/16 sleep routine is modified to use TTC3 if present
-* else it will use set of assembly instructions to
-* provide the required delay
-* 5.04 pkp 03/09/16 Assembly routine for sleep is modified to avoid
-* disabling the interrupt
-* 5.04 pkp 03/11/16 Compare the counter value to previously read value
-* to detect the overflow for TTC3
-* 6.0 asa 08/15/16 Updated the sleep signature. Fix for CR#956899.
-* 6.6 srm 10/18/17 Updated sleep routines to support user configurable
-* implementation. Now sleep routines will use TTC
-* instance specified by user.
-* 7.2 mus 01/29/20 Updated sleep routines to use CortexR5 PMU for delay
-* generation, in case TTC3/TTC2 instances are not
-* present in HW design. If user dont want to use PMU
-* counter for sleep routines, BSP needs to be compiled
-* with "DONT_USE_PMU_FOR_SLEEP_ROUTINES" flag. It fixes
-* CR#1051591.
-*
-*
-*
-******************************************************************************/
-/***************************** Include Files *********************************/
-
-#include "sleep.h"
-#include "xtime_l.h"
-#include "xparameters.h"
-#include "xil_sleeptimer.h"
-#include "xpm_counter.h"
-
-/*****************************************************************************/
-/*
-*
-* This API is used to provide delays in seconds.
-*
-* @param seconds requested
-*
-* @return 0 always
-*
-* @note By default, sleep is implemented using TTC3. Although user is
-* given an option to select other instances of TTC. When the user
-* selects other instances of TTC, sleep is implemented by that
-* specific TTC instance. If the user didn't select any other instance
-* of TTC specifically and when TTC3 is absent, sleep is implemented
-* using assembly instructions which is tested with instruction and
-* data caches enabled and it gives proper delay. It may give more
-* delay than exepcted when caches are disabled. If interrupt comes
-* when sleep using assembly instruction is being executed, the delay
-* may be greater than what is expected since once the interrupt is
-* served count resumes from where it was interrupted unlike the case
-* of TTC3 where counter keeps running while interrupt is being served.
-*
-****************************************************************************/
-
-unsigned sleep_R5(unsigned int seconds)
-{
-#if defined (SLEEP_TIMER_BASEADDR)
- Xil_SleepTTCCommon(seconds, COUNTS_PER_SECOND);
-#elif !defined (DONT_USE_PMU_FOR_SLEEP_ROUTINES)
- Xpm_SleepPerfCounter(seconds, COUNTS_PER_SECOND);
-#else
-#if defined (__GNUC__)
- __asm__ __volatile__ (
-#elif defined (__ICCARM__)
- __asm volatile (
-#endif
-
- "push {r0,r1,r3} \n"
- "mov r0, %[sec] \n"
- "mov r1, %[iter] \n"
- "1: \n"
- "mov r3, r1\n"
- "2: \n"
- "subs r3, r3, #0x1 \n"
- "bne 2b \n"
- "subs r0, r0, #0x1 \n"
- "bne 1b \n"
- "pop {r0,r1,r3} \n"
- ::[iter] "r" (ITERS_PER_SEC), [sec] "r" (seconds)
- );
-#endif
-
-return 0;
-}
diff --git a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ff/f0f848585243001d18b399c1eb9b3628 b/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ff/f0f848585243001d18b399c1eb9b3628
deleted file mode 100644
index 2d63a10..0000000
--- a/Vitis/.metadata/.plugins/org.eclipse.core.resources/.history/ff/f0f848585243001d18b399c1eb9b3628
+++ /dev/null
@@ -1,285 +0,0 @@
-/******************************************************************************
-* Copyright (c) 2018 - 2021 Xilinx, Inc. All rights reserved.
-* SPDX-License-Identifier: MIT
-******************************************************************************/
-
-/*****************************************************************************/
-/**
-* @file xparameters_ps.h
-*
-* This file contains the address definitions for the hard peripherals
-* attached to the ARM Cortex A72 core.
-*
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ------- -------- ---------------------------------------------------
-* 7.00 mus 01/11/18 First release
-* mn 03/26/18 Change Interrupt IDs for versal
-* mn 03/26/18 Update SLCR base address
-*