tinyriscv/rtl/core
liangkangnan 01c3159a83 use larger ram
Signed-off-by: liangkangnan <liangkangnan@163.com>
2021-05-21 09:43:34 +08:00
..
csr.sv debug: add hw breakpoint support 2021-05-14 14:37:47 +08:00
csr_reg.sv debug: add hw breakpoint support 2021-05-14 14:37:47 +08:00
defines.sv use larger ram 2021-05-21 09:43:34 +08:00
divider.sv temp commit 2021-04-30 18:27:30 +08:00
exception.sv debug: fix breakpoint 2021-05-19 19:09:17 +08:00
exu.sv debug: fix step 2021-05-19 15:35:11 +08:00
exu_alu_datapath.sv temp commit 2021-03-31 18:00:19 +08:00
exu_commit.sv temp commit 2021-03-31 18:00:19 +08:00
exu_dispatch.sv temp commit 2021-04-25 17:14:09 +08:00
exu_mem.sv optimize ifu and lsu 2021-04-09 20:22:34 +08:00
exu_muldiv.sv temp commit 2021-04-30 18:27:30 +08:00
gpr_reg.sv temp commit 2021-03-31 18:00:19 +08:00
idu.sv temp commit 2021-04-25 17:14:09 +08:00
idu_exu.sv temp commit 2021-04-01 11:29:00 +08:00
ifu.sv temp commit 2021-04-09 20:27:33 +08:00
ifu_idu.sv temp commit 2021-04-01 11:29:00 +08:00
pipe_ctrl.sv temp commit 2021-03-31 18:00:19 +08:00
rst_gen.sv rtl: add reset module 2021-04-13 14:12:47 +08:00
tinyriscv_core.sv debug: fix step 2021-05-19 15:35:11 +08:00
tracer.sv temp commit 2021-05-04 21:11:43 +08:00