162 lines
5.4 KiB
Systemverilog
162 lines
5.4 KiB
Systemverilog
/*
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Copyright 2021 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module rvic_core (
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input logic clk_i,
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input logic rst_ni,
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input logic [31:0] src_i,
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output logic [ 7:0] irq_id_o,
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output logic irq_o,
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input logic reg_we_i,
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input logic reg_re_i,
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input logic [31:0] reg_wdata_i,
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input logic [ 3:0] reg_be_i,
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input logic [31:0] reg_addr_i,
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output logic [31:0] reg_rdata_o
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);
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import rvic_reg_pkg::*;
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rvic_reg_pkg::rvic_reg2hw_t reg2hw;
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rvic_reg_pkg::rvic_hw2reg_t hw2reg;
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logic [31:0] priority_array[8];
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logic [31:0] irq_enable;
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logic [31:0] irq_pending;
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assign priority_array[0] = reg2hw.priority0.q;
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assign priority_array[1] = reg2hw.priority1.q;
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assign priority_array[2] = reg2hw.priority2.q;
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assign priority_array[3] = reg2hw.priority3.q;
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assign priority_array[4] = reg2hw.priority4.q;
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assign priority_array[5] = reg2hw.priority5.q;
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assign priority_array[6] = reg2hw.priority6.q;
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assign priority_array[7] = reg2hw.priority7.q;
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assign irq_enable = reg2hw.enable.q;
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assign irq_pending = reg2hw.pending.q;
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// 找出优先级最高(优先级值最大)的中断源
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// 二分法查找
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logic [7:0] each_prio[32];
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for (genvar i = 0; i < 8; i = i + 1) begin
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for (genvar j = 0; j < 4; j = j + 1) begin
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// 只有当中断使能了，优先级才有效
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assign each_prio[i*4+j] = priority_array[i][8*j+7:8*j] & {8{irq_enable[i*4+j]}};
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end
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end
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typedef struct packed {
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logic [7:0] id;
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logic [7:0] prio;
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} int_info_t;
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int_info_t l1_max[16];
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always_comb begin
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for (int i = 0; i < 16; i = i + 1) begin
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if (each_prio[2*i+1] > each_prio[2*i]) begin
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l1_max[i].id = 2*i+1;
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l1_max[i].prio = each_prio[2*i+1];
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end else begin
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l1_max[i].id = 2*i;
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l1_max[i].prio = each_prio[2*i];
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end
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end
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end
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int_info_t l2_max[8];
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always_comb begin
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for (int i = 0; i < 8; i = i + 1) begin
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if (l1_max[2*i+1].prio > l1_max[2*i].prio) begin
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l2_max[i].id = l1_max[2*i+1].id;
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l2_max[i].prio = l1_max[2*i+1].prio;
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end else begin
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l2_max[i].id = l1_max[2*i].id;
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l2_max[i].prio = l1_max[2*i].prio;
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end
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end
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end
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int_info_t l3_max[4];
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always_comb begin
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for (int i = 0; i < 4; i = i + 1) begin
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if (l2_max[2*i+1].prio > l2_max[2*i].prio) begin
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l3_max[i].id = l2_max[2*i+1].id;
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l3_max[i].prio = l2_max[2*i+1].prio;
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end else begin
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l3_max[i].id = l2_max[2*i].id;
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l3_max[i].prio = l2_max[2*i].prio;
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end
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end
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end
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int_info_t l4_max[2];
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always_comb begin
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for (int i = 0; i < 2; i = i + 1) begin
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if (l3_max[2*i+1].prio > l3_max[2*i].prio) begin
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l4_max[i].id = l3_max[2*i+1].id;
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l4_max[i].prio = l3_max[2*i+1].prio;
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end else begin
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l4_max[i].id = l3_max[2*i].id;
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l4_max[i].prio = l3_max[2*i].prio;
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end
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end
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end
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logic [7:0] irq_id;
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// 最终查找结果
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assign irq_id = (l4_max[1].prio > l4_max[0].prio) ? l4_max[1].id : l4_max[0].id;
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// 将irq_id打一拍后，irq_id_o就与irq_o同步
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always_ff @ (posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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irq_id_o <= 8'h0;
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end else begin
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irq_id_o <= irq_id;
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end
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end
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// 只要有pending就向MCU发起中断请求
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assign irq_o = |irq_pending;
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// 最多32个中断源
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logic [4:0] id = irq_id[4:0];
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// 硬件置位pending
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assign hw2reg.pending.de = src_i[id] & irq_enable[id];
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assign hw2reg.pending.d = irq_pending | (1 << id);
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rvic_reg_top u_rvic_reg_top (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.reg2hw (reg2hw),
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.hw2reg (hw2reg),
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.reg_we (reg_we_i),
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.reg_re (reg_re_i),
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.reg_wdata (reg_wdata_i),
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.reg_be (reg_be_i),
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.reg_addr (reg_addr_i),
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.reg_rdata (reg_rdata_o)
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);
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endmodule
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