tinyriscv/rtl/perips
liangkangnan 0e188d4934 reorganize example and optimize interrupt
Signed-off-by: liangkangnan <liangkangnan@163.com>
2020-04-11 19:03:49 +08:00
..
gpio.v perips: add uart_tx and gpio 2020-04-05 22:27:00 +08:00
ram.v reorganize example and optimize interrupt 2020-04-11 19:03:49 +08:00
rom.v reorganize example and optimize interrupt 2020-04-11 19:03:49 +08:00
timer.v reorganize example and optimize interrupt 2020-04-11 19:03:49 +08:00
uart_tx.v uart: update 2020-04-06 19:54:40 +08:00