52 lines
1.8 KiB
Verilog
52 lines
1.8 KiB
Verilog
/*
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Copyright 2019 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.v"
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// PC寄存器模块
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module pc_reg(
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input wire clk,
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input wire rst,
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input wire jump_flag_i, // 跳转标志
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input wire[`InstAddrBus] jump_addr_i, // 跳转地址
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input wire[`Hold_Flag_Bus] hold_flag_i, // 流水线暂停标志
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input wire jtag_reset_flag_i, // 复位标志
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output reg[`InstAddrBus] pc_o // PC指针
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);
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always @ (posedge clk) begin
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// 复位
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if (rst == `RstEnable || jtag_reset_flag_i == 1'b1) begin
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pc_o <= `CpuResetAddr;
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// 跳转
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end else if (jump_flag_i == `JumpEnable) begin
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pc_o <= jump_addr_i;
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// 暂停
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end else if (hold_flag_i >= `Hold_Pc) begin
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pc_o <= pc_o;
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// 地址加4
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end else begin
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pc_o <= pc_o + 4'h4;
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end
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end
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endmodule
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