tinyriscv/rtl/perips/spi
liangkangnan 274b19363b rtl:perips:spi: fix ss delay ctrl by sw
Signed-off-by: liangkangnan <liangkangnan@163.com>
2021-11-01 09:55:10 +08:00
..
spi.hjson rtl:perips:spi: add fifo reset 2021-10-12 10:22:02 +08:00
spi_core.sv rtl:perips:spi: add fifo reset 2021-10-12 10:22:02 +08:00
spi_master.sv rtl:perips:spi: fix ss delay ctrl by sw 2021-11-01 09:55:10 +08:00
spi_reg_pkg.sv rtl:perips:spi: add fifo reset 2021-10-12 10:22:02 +08:00
spi_reg_top.sv rtl:perips:spi: add fifo reset 2021-10-12 10:22:02 +08:00
spi_top.sv rtl:perips: add spi master 2021-09-06 10:01:56 +08:00
spi_transmit_byte.sv rtl:perips: add spi master 2021-09-06 10:01:56 +08:00