152 lines
4.9 KiB
Systemverilog
152 lines
4.9 KiB
Systemverilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "../core/defines.sv"
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// 32位向上计数定时器模块
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module timer(
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input wire clk,
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input wire rst_n,
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input wire[31:0] addr_i,
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input wire[31:0] data_i,
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input wire[3:0] sel_i,
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input wire we_i,
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output wire[31:0] data_o,
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output wire int_sig_o
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);
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// 寄存器(偏移)地址
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localparam REG_CTRL = 4'h0;
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localparam REG_COUNT = 4'h4;
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localparam REG_VALUE = 4'h8;
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// 定时器控制寄存器，可读可写
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// bit[0]: 定时器使能
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// bit[1]: 定时器中断使能
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// bit[2]: 定时器中断pending标志，写1清零
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reg[31:0] timer_ctrl;
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// 定时器当前计数值寄存器, 只读
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reg[31:0] timer_count;
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// 定时器溢出值寄存器，当定时器计数值达到该值时产生pending，可读可写
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reg[31:0] timer_value;
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wire wen = we_i & req_valid_i;
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wire ren = (~we_i) & req_valid_i;
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wire timer_en = (timer_ctrl[0] == 1'b1);
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wire timer_int_en = (timer_ctrl[1] == 1'b1);
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wire timer_expired = (timer_count >= timer_value);
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wire write_reg_ctrl_en = wen & (addr_i[3:0] == REG_CTRL);
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wire write_reg_value_en = wen & (addr_i[3:0] == REG_VALUE);
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// 计数
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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timer_count <= 32'h0;
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end else begin
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if (timer_en) begin
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if (timer_expired) begin
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timer_count <= 32'h0;
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end else begin
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timer_count <= timer_count + 1'b1;
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end
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end else begin
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timer_count <= 32'h0;
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end
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end
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end
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reg int_sig_r;
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// 产生中断信号
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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int_sig_r <= 1'b0;
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end else begin
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if (write_reg_ctrl_en & (data_i[2] == 1'b1)) begin
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int_sig_r <= 1'b0;
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end else if (timer_int_en & timer_en & timer_expired) begin
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int_sig_r <= 1'b1;
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end
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end
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end
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assign int_sig_o = int_sig_r;
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// 写timer_ctrl
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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timer_ctrl <= 32'h0;
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end else begin
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if (write_reg_ctrl_en) begin
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if (sel_i[0]) begin
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timer_ctrl[7:0] <= {data_i[7:3], timer_ctrl[2] & (~data_i[2]), data_i[1:0]};
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end
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end else begin
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if (timer_expired) begin
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timer_ctrl[0] <= 1'b0;
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end
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end
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end
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end
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// 写timer_value
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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timer_value <= 32'h0;
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end else begin
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if (write_reg_value_en) begin
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if (sel_i[0]) begin
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timer_value[7:0] <= data_i[7:0];
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end
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if (sel_i[1]) begin
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timer_value[15:8] <= data_i[15:8];
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end
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if (sel_i[2]) begin
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timer_value[23:16] <= data_i[23:16];
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end
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if (sel_i[3]) begin
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timer_value[31:24] <= data_i[31:24];
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end
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end
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end
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end
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reg[31:0] data_r;
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// 读寄存器
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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data_r <= 32'h0;
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end else begin
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if (ren) begin
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case (addr_i[3:0])
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REG_VALUE: data_r <= timer_value;
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REG_CTRL: data_r <= timer_ctrl;
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REG_COUNT: data_r <= timer_count;
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default: data_r <= 32'h0;
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endcase
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end else begin
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data_r <= 32'h0;
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end
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end
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end
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assign data_o = data_r;
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endmodule
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