148 lines
5.8 KiB
Systemverilog
148 lines
5.8 KiB
Systemverilog
/*
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Copyright 2021 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// obi总线交叉互联矩阵，支持一对多、多对一、多对多
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// master之间采用优先级总裁方式，LSB优先级最高，MSB优先级最低
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module obi_interconnect #(
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parameter int MASTERS = 3, // number of masters
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parameter int SLAVES = 5, // number of slaves
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parameter MASTER_BITS = MASTERS == 1 ? 1 : $clog2(MASTERS),
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parameter SLAVE_BITS = SLAVES == 1 ? 1 : $clog2(SLAVES)
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)(
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input logic clk_i,
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input logic rst_ni,
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input logic master_req_i [MASTERS],
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output logic master_gnt_o [MASTERS],
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output logic master_rvalid_o [MASTERS],
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input logic master_we_i [MASTERS],
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input logic [ 3:0] master_be_i [MASTERS],
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input logic [31:0] master_addr_i [MASTERS],
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input logic [31:0] master_wdata_i [MASTERS],
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output logic [31:0] master_rdata_o [MASTERS],
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input logic [31:0] slave_addr_mask_i [SLAVES],
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input logic [31:0] slave_addr_base_i [SLAVES],
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output logic slave_req_o [SLAVES],
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input logic slave_gnt_i [SLAVES],
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input logic slave_rvalid_i [SLAVES],
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output logic slave_we_o [SLAVES],
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output logic [ 3:0] slave_be_o [SLAVES],
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output logic [31:0] slave_addr_o [SLAVES],
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output logic [31:0] slave_wdata_o [SLAVES],
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input logic [31:0] slave_rdata_i [SLAVES]
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);
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genvar m, s;
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logic [MASTER_BITS-1:0] master_sel_int[SLAVES];
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logic [MASTERS-1:0] master_sel_vec[SLAVES];
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logic granted_master[SLAVES];
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// 为每个slave选择一个master
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generate
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for (s = 0; s < SLAVES; s = s + 1) begin: master_sel
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obi_interconnect_master_sel #(
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.MASTERS(MASTERS)
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) master_sel (
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.clk_i(clk_i),
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.rst_ni(rst_ni),
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.master_req_i(master_req_i),
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.master_addr_i(master_addr_i),
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.slave_addr_mask_i(slave_addr_mask_i[s]),
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.slave_addr_base_i(slave_addr_base_i[s]),
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.master_sel_int_o(master_sel_int[s]),
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.master_sel_vec_o(master_sel_vec[s]),
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.granted_master_o(granted_master[s])
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);
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end
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endgenerate
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logic [SLAVE_BITS-1:0] slave_sel_int[MASTERS];
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// 为每个master选择一个slave
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generate
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for (m = 0; m < MASTERS; m = m + 1) begin: slave_sel
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obi_interconnect_slave_sel #(
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.SLAVES(SLAVES)
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) slave_sel (
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.clk_i(clk_i),
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.rst_ni(rst_ni),
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.master_req_i(master_req_i[m]),
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.master_addr_i(master_addr_i[m]),
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.slave_addr_mask_i(slave_addr_mask_i),
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.slave_addr_base_i(slave_addr_base_i),
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.slave_sel_int_o(slave_sel_int[m])
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);
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end
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endgenerate
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// slave信号赋值
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generate
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for (s = 0; s < SLAVES; s = s + 1) begin: slave_signal
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assign slave_req_o[s] = master_req_i[master_sel_int[s]] & granted_master[s];
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assign slave_we_o[s] = master_we_i[master_sel_int[s]] & granted_master[s];
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assign slave_be_o[s] = master_be_i[master_sel_int[s]];
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assign slave_addr_o[s] = master_addr_i[master_sel_int[s]];
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assign slave_wdata_o[s] = master_wdata_i[master_sel_int[s]];
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end
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endgenerate
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logic [MASTERS-1:0] master_sel_or;
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always_comb begin
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master_sel_or = 'b0;
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for (integer i = 0; i < SLAVES; i = i + 1) begin: gen_master_sel_or_vec
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master_sel_or = master_sel_or | master_sel_vec[i];
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end
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end
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logic [SLAVE_BITS-1:0] slave_sel_int_q[MASTERS];
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generate
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for (m = 0; m < MASTERS; m = m + 1) begin: master_data_q
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always_ff @ (posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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slave_sel_int_q[m] <= 'b0;
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end else begin
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slave_sel_int_q[m] <= slave_sel_int[m];
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end
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end
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end
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endgenerate
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logic [MASTERS-1:0] master_sel_or_q;
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always_ff @ (posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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master_sel_or_q <= 'b0;
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end else begin
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master_sel_or_q <= master_sel_or;
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end
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end
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// master信号赋值
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generate
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for (m = 0; m < MASTERS; m = m + 1) begin: master_data
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assign master_gnt_o[m] = master_sel_or[m];
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assign master_rdata_o[m] = slave_rdata_i[slave_sel_int_q[m]];
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assign master_rvalid_o[m] = master_sel_or_q[m];
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end
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endgenerate
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endmodule
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