liangkangnan 64041b4d2b rtl: perips: rewrite timer module ... Signed-off-by: liangkangnan <liangkangnan@163.com>		2021-08-10 09:47:37 +08:00
..
bpu.sv	rtl: add static branch predict unit	2021-06-11 09:44:26 +08:00
csr.sv	debug: add hw breakpoint support	2021-05-14 14:37:47 +08:00
csr_reg.sv	test: use csr_sstatus for test result	2021-07-10 14:49:36 +08:00
defines.sv	rtl: perips: rewrite timer module	2021-08-10 09:47:37 +08:00
divider.sv	temp commit	2021-04-30 18:27:30 +08:00
exception.sv	use none-vector interrupt mode	2021-07-26 09:54:38 +08:00
exu.sv	rtl: add config for branch predictor	2021-06-28 11:31:04 +08:00
exu_alu_datapath.sv	temp commit	2021-03-31 18:00:19 +08:00
exu_commit.sv	temp commit	2021-03-31 18:00:19 +08:00
exu_dispatch.sv	rtl: add static branch predict unit	2021-06-11 09:44:26 +08:00
exu_mem.sv	rtl: core: optimize mem access	2021-06-05 20:00:15 +08:00
exu_muldiv.sv	temp commit	2021-04-30 18:27:30 +08:00
gpr_reg.sv	temp commit	2021-03-31 18:00:19 +08:00
idu.sv	temp commit	2021-06-18 20:04:46 +08:00
idu_exu.sv	temp commit	2021-06-18 20:04:46 +08:00
ifu.sv	rtl: ifu optimization	2021-07-03 15:09:13 +08:00
ifu_idu.sv	rtl: ifu optimization	2021-07-03 15:09:13 +08:00
pipe_ctrl.sv	temp commit	2021-07-01 09:46:56 +08:00
rst_gen.sv	rtl: add reset module	2021-04-13 14:12:47 +08:00
tinyriscv_core.sv	rtl:perips: add rvic	2021-07-22 09:36:04 +08:00
tracer.sv	temp commit	2021-05-04 21:11:43 +08:00