zcy
/
tinyriscv
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
175 Commits
3 Branches
9 Tags
66 MiB
C 59.1%
Assembly 28%
Verilog 11.4%
Makefile 0.8%
Python 0.7%
 
 
 
 
 
Go to file
liangkangnan ceddc1af24 test:example: move C examples to sdk directory 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 		2020-11-08 22:09:38 +08:00
doc first release 2020-10-23 21:26:18 +08:00
fpga first release 2020-10-23 21:26:18 +08:00
pic pic: update arch.jpg 2020-06-27 10:11:46 +08:00
rtl rtl: add mem access misaligned exception 2020-11-08 22:08:03 +08:00
sdk test:example: move C examples to sdk directory 2020-11-08 22:09:38 +08:00
sim python scripts: remove verison 2020-10-25 12:02:26 +08:00
tb first release 2020-10-23 21:26:18 +08:00
tests test:example: move C examples to sdk directory 2020-11-08 22:09:38 +08:00
tools first release 2020-10-23 21:26:18 +08:00
.gitignore first release 2020-10-23 21:26:18 +08:00
LICENSE first release 2019-12-04 08:47:19 +08:00
README.md first release 2020-10-23 21:26:18 +08:00

README.md

本分支(bram)是在master分支的基础上，将指令和数据存储器由LUTRAM(DRAM)改为BRAM，以便可以运行更大的(C语言)程序。