86 lines
3.2 KiB
Verilog
86 lines
3.2 KiB
Verilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.v"
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// identification to execute module
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module id_ex(
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input wire clk,
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input wire rst,
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input wire[`InstBus] inst_i, // inst content
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input wire[`InstAddrBus] inst_addr_i, // inst addr
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input wire reg_we_i,
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input wire[`RegAddrBus] reg_waddr_i,
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input wire[`RegBus] reg1_rdata_i, // reg1 read data
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input wire[`RegBus] reg2_rdata_i, // reg2 read data
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input wire csr_we_i,
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input wire[`MemAddrBus] csr_waddr_i,
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input wire[`RegBus] csr_rdata_i,
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input wire[`Hold_Flag_Bus] hold_flag_i,
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output reg[`InstBus] inst_o, // inst content
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output reg[`InstAddrBus] inst_addr_o, // inst addr
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output reg reg_we_o,
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output reg[`RegAddrBus] reg_waddr_o,
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output reg[`RegBus] reg1_rdata_o, // reg1 read data
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output reg[`RegBus] reg2_rdata_o, // reg2 read data
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output reg csr_we_o,
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output reg[`MemAddrBus] csr_waddr_o,
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output reg[`RegBus] csr_rdata_o
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);
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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inst_o <= `INST_NOP;
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inst_addr_o <= `ZeroWord;
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reg_we_o <= `WriteDisable;
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reg_waddr_o <= `ZeroWord;
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reg1_rdata_o <= `ZeroWord;
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reg2_rdata_o <= `ZeroWord;
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csr_we_o <= `WriteDisable;
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csr_waddr_o <= `ZeroWord;
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csr_rdata_o <= `ZeroWord;
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end else begin
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if (hold_flag_i >= `Hold_Id) begin
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inst_o <= `INST_NOP;
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inst_addr_o <= inst_addr_i;
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reg_we_o <= `WriteDisable;
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reg_waddr_o <= `ZeroWord;
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reg1_rdata_o <= `ZeroWord;
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reg2_rdata_o <= `ZeroWord;
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csr_we_o <= `WriteDisable;
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csr_waddr_o <= `ZeroWord;
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csr_rdata_o <= `ZeroWord;
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end else begin
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inst_o <= inst_i;
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inst_addr_o <= inst_addr_i;
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reg_we_o <= reg_we_i;
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reg_waddr_o <= reg_waddr_i;
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reg1_rdata_o <= reg1_rdata_i;
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reg2_rdata_o <= reg2_rdata_i;
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csr_we_o <= csr_we_i;
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csr_waddr_o <= csr_waddr_i;
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csr_rdata_o <= csr_rdata_i;
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end
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end
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end
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endmodule
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