tinyriscv/rtl/core
liangkangnan ce225394df fix reg1 reg2 bits width
Signed-off-by: liangkangnan <liangkangnan@163.com>
2020-04-18 11:35:43 +08:00
..
clint.v optimized: use statemachine 2020-04-18 11:21:09 +08:00
csr_reg.v add mepc reg 2020-04-18 11:22:20 +08:00
ctrl.v reorganize example and optimize interrupt 2020-04-11 19:03:49 +08:00
defines.v add mepc reg 2020-04-18 11:22:20 +08:00
div.v update 2020-03-29 23:19:14 +08:00
ex.v optimize div 2020-04-18 11:23:46 +08:00
id.v fix reg1 reg2 bits width 2020-04-18 11:35:43 +08:00
id_ex.v reorganize example and optimize interrupt 2020-04-11 19:03:49 +08:00
if_id.v reorganize example and optimize interrupt 2020-04-11 19:03:49 +08:00
pc_reg.v update 2020-03-29 23:19:14 +08:00
regs.v update 2020-03-29 23:19:14 +08:00
rib.v perips: add uart_tx and gpio 2020-04-05 22:27:00 +08:00
tinyriscv.v reorganize example and optimize interrupt 2020-04-11 19:03:49 +08:00