152 lines
5.3 KiB
Smarty
152 lines
5.3 KiB
Smarty
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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// UVM registers auto-generated by `reggen` containing UVM definitions for the entire top-level
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<%!
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from topgen.gen_dv import sv_base_addr
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from reggen.gen_dv import bcname, mcname, miname
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%>
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##
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## This template is used for chip-wide tests. It expects to be run with the
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## following arguments
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##
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## top a Top object
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##
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## dv_base_prefix a string for the base register type. If it is FOO, then
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## we will inherit from FOO_reg (assumed to be a subclass
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## of uvm_reg).
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##
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## Like uvm_reg.sv.tpl, we use functions from uvm_reg_base.sv.tpl to define
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## per-device-interface code.
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##
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<%namespace file="uvm_reg_base.sv.tpl" import="*"/>\
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##
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##
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## Waive the package-filename check: we're going to be defining all sorts of
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## packages in a single file.
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// verilog_lint: waive-start package-filename
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##
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## Iterate over the device interfaces of blocks in Top, constructing a package
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## for each. Sorting items like this guarantees we'll work alphabetically in
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## block name.
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% for block_name, block in sorted(top.blocks.items()):
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% for if_name, rb in block.reg_blocks.items():
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<%
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if_suffix = '' if if_name is None else '_' + if_name
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esc_if_name = block_name.lower() + if_suffix
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if_desc = '' if if_name is None else '; interface {}'.format(if_name)
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reg_block_path = 'u_reg' + if_suffix
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reg_block_path = reg_block_path if block.hier_path is None else block.hier_path + "." + reg_block_path
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%>\
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// Block: ${block_name.lower()}${if_desc}
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${make_ral_pkg(dv_base_prefix, top.regwidth, reg_block_path, rb, esc_if_name)}
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% endfor
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% endfor
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##
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##
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## Now that we've made the block-level packages, re-instate the
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## package-filename check. The only package left is chip_ral_pkg, which should
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## match the generated filename.
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// verilog_lint: waive-start package-filename
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// Block: chip
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package chip_ral_pkg;
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<%
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if_packages = []
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for block_name, block in sorted(top.blocks.items()):
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for if_name in block.reg_blocks:
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if_suffix = '' if if_name is None else '_' + if_name
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if_packages.append('{}{}_ral_pkg'.format(block_name.lower(), if_suffix))
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windows = top.window_block.windows
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%>\
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${make_ral_pkg_hdr(dv_base_prefix, if_packages)}
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${make_ral_pkg_fwd_decls('chip', [], windows)}
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% for window in windows:
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${make_ral_pkg_window_class(dv_base_prefix, 'chip', window)}
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% endfor
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class chip_reg_block extends ${dv_base_prefix}_reg_block;
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// sub blocks
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% for block_name, block in sorted(top.blocks.items()):
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% for inst_name in top.block_instances[block_name.lower()]:
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% for if_name, rb in block.reg_blocks.items():
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<%
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if_suffix = '' if if_name is None else '_' + if_name
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esc_if_name = block_name.lower() + if_suffix
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if_inst = inst_name + if_suffix
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%>\
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rand ${bcname(esc_if_name)} ${if_inst};
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% endfor
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% endfor
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% endfor
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% if windows:
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// memories
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% for window in windows:
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rand ${mcname('chip', window)} ${miname(window)};
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% endfor
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% endif
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`uvm_object_utils(chip_reg_block)
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function new(string name = "chip_reg_block",
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int has_coverage = UVM_NO_COVERAGE);
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super.new(name, has_coverage);
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endfunction : new
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virtual function void build(uvm_reg_addr_t base_addr,
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csr_excl_item csr_excl = null);
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// create default map
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this.default_map = create_map(.name("default_map"),
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.base_addr(base_addr),
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.n_bytes(${top.regwidth//8}),
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.endian(UVM_LITTLE_ENDIAN));
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if (csr_excl == null) begin
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csr_excl = csr_excl_item::type_id::create("csr_excl");
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this.csr_excl = csr_excl;
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end
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// create sub blocks and add their maps
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% for block_name, block in sorted(top.blocks.items()):
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% for inst_name in top.block_instances[block_name.lower()]:
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% for if_name, rb in block.reg_blocks.items():
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<%
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if_suffix = '' if if_name is None else '_' + if_name
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esc_if_name = block_name.lower() + if_suffix
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if_inst = inst_name + if_suffix
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if top.attrs.get(inst_name) == 'reggen_only':
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hdl_path = 'tb.dut.u_' + inst_name
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else:
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hdl_path = 'tb.dut.top_earlgrey.u_' + inst_name
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qual_if_name = (inst_name, if_name)
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base_addr = top.if_addrs[qual_if_name]
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base_addr_txt = sv_base_addr(top, qual_if_name)
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hpr_indent = (len(if_inst) + len('.set_hdl_path_root(')) * ' '
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%>\
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${if_inst} = ${bcname(esc_if_name)}::type_id::create("${if_inst}");
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${if_inst}.configure(.parent(this));
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${if_inst}.build(.base_addr(base_addr + ${base_addr_txt}), .csr_excl(csr_excl));
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${if_inst}.set_hdl_path_root("${hdl_path}",
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${hpr_indent}"BkdrRegPathRtl");
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${if_inst}.set_hdl_path_root("${hdl_path}",
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${hpr_indent}"BkdrRegPathRtlCommitted");
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${if_inst}.set_hdl_path_root("${hdl_path}",
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${hpr_indent}"BkdrRegPathRtlShadow");
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default_map.add_submap(.child_map(${if_inst}.default_map),
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.offset(base_addr + ${base_addr_txt}));
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% endfor
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% endfor
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% endfor
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${make_ral_pkg_window_instances(top.regwidth, 'chip', top.window_block)}
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endfunction : build
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endclass : chip_reg_block
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endpackage
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