453 lines
18 KiB
Python
453 lines
18 KiB
Python
# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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"""This contains a class which is used to help generate `top_{name}.h` and
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`top_{name}.h`.
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"""
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from collections import OrderedDict
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from typing import Dict, List, Optional, Tuple
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from mako.template import Template
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from .lib import get_base_and_size, Name
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from reggen.ip_block import IpBlock
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class MemoryRegion(object):
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def __init__(self, name: Name, base_addr: int, size_bytes: int):
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assert isinstance(base_addr, int)
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self.name = name
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self.base_addr = base_addr
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self.size_bytes = size_bytes
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self.size_words = (size_bytes + 3) // 4
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def base_addr_name(self):
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return self.name + Name(["base", "addr"])
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def offset_name(self):
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return self.name + Name(["offset"])
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def size_bytes_name(self):
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return self.name + Name(["size", "bytes"])
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def size_words_name(self):
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return self.name + Name(["size", "words"])
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class CEnum(object):
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def __init__(self, name):
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self.name = name
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self.enum_counter = 0
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self.finalized = False
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self.constants = []
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def add_constant(self, constant_name, docstring=""):
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assert not self.finalized
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full_name = self.name + constant_name
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value = self.enum_counter
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self.enum_counter += 1
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self.constants.append((full_name, value, docstring))
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return full_name
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def add_last_constant(self, docstring=""):
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assert not self.finalized
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full_name = self.name + Name(["last"])
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_, last_val, _ = self.constants[-1]
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self.constants.append((full_name, last_val, r"\internal " + docstring))
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self.finalized = True
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def render(self):
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template = ("typedef enum ${enum.name.as_snake_case()} {\n"
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"% for name, value, docstring in enum.constants:\n"
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" ${name.as_c_enum()} = ${value}, /**< ${docstring} */\n"
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"% endfor\n"
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"} ${enum.name.as_c_type()};")
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return Template(template).render(enum=self)
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class CArrayMapping(object):
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def __init__(self, name, output_type_name):
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self.name = name
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self.output_type_name = output_type_name
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self.mapping = OrderedDict()
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def add_entry(self, in_name, out_name):
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self.mapping[in_name] = out_name
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def render_declaration(self):
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template = (
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"extern const ${mapping.output_type_name.as_c_type()}\n"
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" ${mapping.name.as_snake_case()}[${len(mapping.mapping)}];")
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return Template(template).render(mapping=self)
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def render_definition(self):
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template = (
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"const ${mapping.output_type_name.as_c_type()}\n"
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" ${mapping.name.as_snake_case()}[${len(mapping.mapping)}] = {\n"
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"% for in_name, out_name in mapping.mapping.items():\n"
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" [${in_name.as_c_enum()}] = ${out_name.as_c_enum()},\n"
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"% endfor\n"
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"};\n")
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return Template(template).render(mapping=self)
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class TopGenC:
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def __init__(self, top_info, name_to_block: Dict[str, IpBlock]):
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self.top = top_info
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self._top_name = Name(["top"]) + Name.from_snake_case(top_info["name"])
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self._name_to_block = name_to_block
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# The .c file needs the .h file's relative path, store it here
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self.header_path = None
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self._init_plic_targets()
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self._init_plic_mapping()
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self._init_alert_mapping()
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self._init_pinmux_mapping()
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self._init_pwrmgr_wakeups()
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self._init_rstmgr_sw_rsts()
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self._init_pwrmgr_reset_requests()
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self._init_clkmgr_clocks()
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def devices(self) -> List[Tuple[Tuple[str, Optional[str]], MemoryRegion]]:
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'''Return a list of MemoryRegion objects for devices on the bus
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The list returned is pairs (full_if, region) where full_if is itself a
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pair (inst_name, if_name). inst_name is the name of some IP block
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instantiation. if_name is the name of the interface (may be None).
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region is a MemoryRegion object representing the device.
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'''
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ret = [] # type: List[Tuple[Tuple[str, Optional[str]], MemoryRegion]]
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for inst in self.top['module']:
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block = self._name_to_block[inst['type']]
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for if_name, rb in block.reg_blocks.items():
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full_if = (inst['name'], if_name)
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full_if_name = Name.from_snake_case(full_if[0])
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if if_name is not None:
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full_if_name += Name.from_snake_case(if_name)
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name = self._top_name + full_if_name
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base, size = get_base_and_size(self._name_to_block,
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inst, if_name)
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region = MemoryRegion(name, base, size)
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ret.append((full_if, region))
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return ret
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def memories(self):
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ret = []
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for m in self.top["memory"]:
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ret.append((m["name"],
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MemoryRegion(self._top_name +
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Name.from_snake_case(m["name"]),
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int(m["base_addr"], 0),
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int(m["size"], 0))))
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for inst in self.top['module']:
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if "memory" in inst:
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for if_name, val in inst["memory"].items():
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base, size = get_base_and_size(self._name_to_block,
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inst, if_name)
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name = self._top_name + Name.from_snake_case(val["label"])
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region = MemoryRegion(name, base, size)
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ret.append((val["label"], region))
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return ret
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def _init_plic_targets(self):
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enum = CEnum(self._top_name + Name(["plic", "target"]))
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for core_id in range(int(self.top["num_cores"])):
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enum.add_constant(Name(["ibex", str(core_id)]),
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docstring="Ibex Core {}".format(core_id))
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enum.add_last_constant("Final PLIC target")
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self.plic_targets = enum
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def _init_plic_mapping(self):
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"""We eventually want to generate a mapping from interrupt id to the
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source peripheral.
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In order to do so, we generate two enums (one for interrupts, one for
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sources), and store the generated names in a dictionary that represents
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the mapping.
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PLIC Interrupt ID 0 corresponds to no interrupt, and so no peripheral,
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so we encode that in the enum as "unknown".
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The interrupts have to be added in order, with "none" first, to ensure
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that they get the correct mapping to their PLIC id, which is used for
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addressing the right registers and bits.
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"""
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sources = CEnum(self._top_name + Name(["plic", "peripheral"]))
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interrupts = CEnum(self._top_name + Name(["plic", "irq", "id"]))
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plic_mapping = CArrayMapping(
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self._top_name + Name(["plic", "interrupt", "for", "peripheral"]),
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sources.name)
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unknown_source = sources.add_constant(Name(["unknown"]),
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docstring="Unknown Peripheral")
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none_irq_id = interrupts.add_constant(Name(["none"]),
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docstring="No Interrupt")
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plic_mapping.add_entry(none_irq_id, unknown_source)
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# When we generate the `interrupts` enum, the only info we have about
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# the source is the module name. We'll use `source_name_map` to map a
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# short module name to the full name object used for the enum constant.
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source_name_map = {}
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for name in self.top["interrupt_module"]:
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source_name = sources.add_constant(Name.from_snake_case(name),
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docstring=name)
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source_name_map[name] = source_name
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sources.add_last_constant("Final PLIC peripheral")
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for intr in self.top["interrupt"]:
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# Some interrupts are multiple bits wide. Here we deal with that by
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# adding a bit-index suffix
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if "width" in intr and int(intr["width"]) != 1:
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for i in range(int(intr["width"])):
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name = Name.from_snake_case(intr["name"]) + Name([str(i)])
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irq_id = interrupts.add_constant(name,
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docstring="{} {}".format(
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intr["name"], i))
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source_name = source_name_map[intr["module_name"]]
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plic_mapping.add_entry(irq_id, source_name)
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else:
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name = Name.from_snake_case(intr["name"])
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irq_id = interrupts.add_constant(name, docstring=intr["name"])
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source_name = source_name_map[intr["module_name"]]
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plic_mapping.add_entry(irq_id, source_name)
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interrupts.add_last_constant("The Last Valid Interrupt ID.")
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self.plic_sources = sources
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self.plic_interrupts = interrupts
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self.plic_mapping = plic_mapping
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def _init_alert_mapping(self):
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"""We eventually want to generate a mapping from alert id to the source
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peripheral.
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In order to do so, we generate two enums (one for alerts, one for
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sources), and store the generated names in a dictionary that represents
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the mapping.
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Alert Handler has no concept of "no alert", unlike the PLIC.
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The alerts have to be added in order, to ensure that they get the
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correct mapping to their alert id, which is used for addressing the
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right registers and bits.
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"""
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sources = CEnum(self._top_name + Name(["alert", "peripheral"]))
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alerts = CEnum(self._top_name + Name(["alert", "id"]))
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alert_mapping = CArrayMapping(
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self._top_name + Name(["alert", "for", "peripheral"]),
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sources.name)
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# When we generate the `alerts` enum, the only info we have about the
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# source is the module name. We'll use `source_name_map` to map a short
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# module name to the full name object used for the enum constant.
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source_name_map = {}
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for name in self.top["alert_module"]:
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source_name = sources.add_constant(Name.from_snake_case(name),
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docstring=name)
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source_name_map[name] = source_name
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sources.add_last_constant("Final Alert peripheral")
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for alert in self.top["alert"]:
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if "width" in alert and int(alert["width"]) != 1:
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for i in range(int(alert["width"])):
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name = Name.from_snake_case(alert["name"]) + Name([str(i)])
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irq_id = alerts.add_constant(name,
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docstring="{} {}".format(
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alert["name"], i))
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source_name = source_name_map[alert["module_name"]]
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alert_mapping.add_entry(irq_id, source_name)
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else:
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name = Name.from_snake_case(alert["name"])
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alert_id = alerts.add_constant(name, docstring=alert["name"])
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source_name = source_name_map[alert["module_name"]]
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alert_mapping.add_entry(alert_id, source_name)
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alerts.add_last_constant("The Last Valid Alert ID.")
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self.alert_sources = sources
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self.alert_alerts = alerts
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self.alert_mapping = alert_mapping
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def _init_pinmux_mapping(self):
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"""Generate C enums for addressing pinmux registers and in/out selects.
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Inputs/outputs are connected in the order the modules are listed in
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the hjson under the "mio_modules" key. For each module, the corresponding
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inouts are connected first, followed by either the inputs or the outputs.
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Inputs:
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- Peripheral chooses register field (pinmux_peripheral_in)
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- Insel chooses MIO input (pinmux_insel)
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Outputs:
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- MIO chooses register field (pinmux_mio_out)
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- Outsel chooses peripheral output (pinmux_outsel)
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Insel and outsel have some special values which are captured here too.
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"""
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pinmux_info = self.top['pinmux']
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pinout_info = self.top['pinout']
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# Peripheral Inputs
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peripheral_in = CEnum(self._top_name +
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Name(['pinmux', 'peripheral', 'in']))
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i = 0
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for sig in pinmux_info['ios']:
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if sig['connection'] == 'muxed' and sig['type'] in ['inout', 'input']:
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index = Name([str(sig['idx'])]) if sig['idx'] != -1 else Name([])
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name = Name.from_snake_case(sig['name']) + index
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peripheral_in.add_constant(name, docstring='Peripheral Input {}'.format(i))
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i += 1
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peripheral_in.add_last_constant('Last valid peripheral input')
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# Pinmux Input Selects
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insel = CEnum(self._top_name + Name(['pinmux', 'insel']))
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insel.add_constant(Name(['constant', 'zero']),
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docstring='Tie constantly to zero')
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insel.add_constant(Name(['constant', 'one']),
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docstring='Tie constantly to one')
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i = 0
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for pad in pinout_info['pads']:
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if pad['connection'] == 'muxed':
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insel.add_constant(Name([pad['name']]),
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docstring='MIO Pad {}'.format(i))
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i += 1
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insel.add_last_constant('Last valid insel value')
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# MIO Outputs
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mio_out = CEnum(self._top_name + Name(['pinmux', 'mio', 'out']))
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i = 0
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for pad in pinout_info['pads']:
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if pad['connection'] == 'muxed':
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mio_out.add_constant(Name.from_snake_case(pad['name']),
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docstring='MIO Pad {}'.format(i))
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i += 1
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mio_out.add_last_constant('Last valid mio output')
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# Pinmux Output Selects
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outsel = CEnum(self._top_name + Name(['pinmux', 'outsel']))
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outsel.add_constant(Name(['constant', 'zero']),
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docstring='Tie constantly to zero')
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outsel.add_constant(Name(['constant', 'one']),
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docstring='Tie constantly to one')
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outsel.add_constant(Name(['constant', 'high', 'z']),
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docstring='Tie constantly to high-Z')
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i = 0
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for sig in pinmux_info['ios']:
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if sig['connection'] == 'muxed' and sig['type'] in ['inout', 'output']:
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index = Name([str(sig['idx'])]) if sig['idx'] != -1 else Name([])
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name = Name.from_snake_case(sig['name']) + index
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outsel.add_constant(name, docstring='Peripheral Output {}'.format(i))
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i += 1
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outsel.add_last_constant('Last valid outsel value')
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self.pinmux_peripheral_in = peripheral_in
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self.pinmux_insel = insel
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self.pinmux_mio_out = mio_out
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self.pinmux_outsel = outsel
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def _init_pwrmgr_wakeups(self):
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enum = CEnum(self._top_name +
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Name(["power", "manager", "wake", "ups"]))
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for signal in self.top["wakeups"]:
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enum.add_constant(
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Name.from_snake_case(signal["module"]) +
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Name.from_snake_case(signal["name"]))
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enum.add_last_constant("Last valid pwrmgr wakeup signal")
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self.pwrmgr_wakeups = enum
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# Enumerates the positions of all software controllable resets
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def _init_rstmgr_sw_rsts(self):
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sw_rsts = self.top['resets'].get_sw_resets()
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enum = CEnum(self._top_name +
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Name(["reset", "manager", "sw", "resets"]))
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for rst in sw_rsts:
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enum.add_constant(Name.from_snake_case(rst))
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enum.add_last_constant("Last valid rstmgr software reset request")
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self.rstmgr_sw_rsts = enum
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def _init_pwrmgr_reset_requests(self):
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enum = CEnum(self._top_name +
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Name(["power", "manager", "reset", "requests"]))
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for signal in self.top["reset_requests"]:
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enum.add_constant(
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Name.from_snake_case(signal["module"]) +
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Name.from_snake_case(signal["name"]))
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enum.add_last_constant("Last valid pwrmgr reset_request signal")
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self.pwrmgr_reset_requests = enum
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def _init_clkmgr_clocks(self):
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"""
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Creates CEnums for accessing the software-controlled clocks in the
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design.
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The logic here matches the logic in topgen.py in how it instantiates the
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clock manager with the described clocks.
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We differentiate "gateable" clocks and "hintable" clocks because the
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clock manager has separate register interfaces for each group.
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"""
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clocks = self.top['clocks']
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aon_clocks = set(src.name
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for src in clocks.all_srcs.values() if src.aon)
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gateable_clocks = CEnum(self._top_name + Name(["gateable", "clocks"]))
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hintable_clocks = CEnum(self._top_name + Name(["hintable", "clocks"]))
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# This replicates the behaviour in `topgen.py` in deriving `hints` and
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# `sw_clocks`.
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for group in clocks.groups.values():
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for name, source in group.clocks.items():
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if source.name not in aon_clocks:
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# All these clocks start with `clk_` which is redundant.
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clock_name = Name.from_snake_case(name).remove_part("clk")
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docstring = "Clock {} in group {}".format(name, group.name)
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if group.sw_cg == "yes":
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gateable_clocks.add_constant(clock_name, docstring)
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elif group.sw_cg == "hint":
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hintable_clocks.add_constant(clock_name, docstring)
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gateable_clocks.add_last_constant("Last Valid Gateable Clock")
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hintable_clocks.add_last_constant("Last Valid Hintable Clock")
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self.clkmgr_gateable_clocks = gateable_clocks
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self.clkmgr_hintable_clocks = hintable_clocks
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