241 lines
8.0 KiB
Systemverilog
241 lines
8.0 KiB
Systemverilog
/*
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Copyright 2021 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "../core/defines.sv"
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// RISC-V中断控制器
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// 支持32个中断源，每个中断源支持256级优先级
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module rvic #(
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)(
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input logic clk_i,
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input logic rst_ni,
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input logic [31:0] src_i,
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output logic irq_o, // 中断请求信号
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output logic [7:0] irq_id_o, // 中断号
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input logic [31:0] addr_i,
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input logic [31:0] data_i,
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input logic [3:0] be_i,
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input logic we_i,
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output logic [31:0] data_o
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);
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// 寄存器地址偏移
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parameter logic [7:0] IE_OFFSET = 8'h0;
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parameter logic [7:0] IP_OFFSET = 8'h4;
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parameter logic [7:0] PRIO0_OFFSET = 8'h8;
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parameter logic [7:0] PRIO1_OFFSET = 8'hc;
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parameter logic [7:0] PRIO2_OFFSET = 8'h10;
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parameter logic [7:0] PRIO3_OFFSET = 8'h14;
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parameter logic [7:0] PRIO4_OFFSET = 8'h18;
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parameter logic [7:0] PRIO5_OFFSET = 8'h1c;
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parameter logic [7:0] PRIO6_OFFSET = 8'h20;
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parameter logic [7:0] PRIO7_OFFSET = 8'h24;
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parameter logic [7:0] ID_OFFSET = 8'h28;
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logic ie_we;
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logic ip_we;
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logic [7:0] prio_we;
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logic [31:0] prio_q[8];
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logic [31:0] ie_q;
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logic [31:0] ip_q;
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logic [31:0] id_q;
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logic [10:0] addr_hit;
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logic [7:0] reg_addr = addr_i[7:0];
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always_comb begin
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addr_hit = 11'h0;
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addr_hit[ 0] = (reg_addr == IE_OFFSET);
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addr_hit[ 1] = (reg_addr == IP_OFFSET);
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addr_hit[ 2] = (reg_addr == PRIO0_OFFSET);
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addr_hit[ 3] = (reg_addr == PRIO1_OFFSET);
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addr_hit[ 4] = (reg_addr == PRIO2_OFFSET);
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addr_hit[ 5] = (reg_addr == PRIO3_OFFSET);
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addr_hit[ 6] = (reg_addr == PRIO4_OFFSET);
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addr_hit[ 7] = (reg_addr == PRIO5_OFFSET);
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addr_hit[ 8] = (reg_addr == PRIO6_OFFSET);
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addr_hit[ 9] = (reg_addr == PRIO7_OFFSET);
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addr_hit[10] = (reg_addr == ID_OFFSET);
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end
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assign ie_we = we_i & addr_hit[0];
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assign ip_we = we_i & addr_hit[1];
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for (genvar p = 0; p < 8; p = p + 1) begin
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assign prio_we[p] = we_i & addr_hit[p + 2];
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end
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// 写寄存器
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logic [31:0] reg_wdata;
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always_comb begin
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reg_wdata = 32'h0;
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// IP寄存器是写1清零的，因此要区别对待
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if (ip_we) begin
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reg_wdata = ip_q;
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if (be_i[0])
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reg_wdata[7:0] = ip_q[7:0] & (~data_i[7:0]);
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if (be_i[1])
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reg_wdata[15:8] = ip_q[15:8] & (~data_i[15:8]);
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if (be_i[2])
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reg_wdata[23:16] = ip_q[23:16] & (~data_i[23:16]);
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if (be_i[3])
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reg_wdata[31:24] = ip_q[31:24] & (~data_i[31:24]);
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end else begin
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if (ie_we) begin
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reg_wdata = ie_q;
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end
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for (int j = 0; j < 8; j = j + 1) begin
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if (prio_we[j]) begin
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reg_wdata = prio_q[j];
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end
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end
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if (be_i[0])
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reg_wdata[7:0] = data_i[7:0];
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if (be_i[1])
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reg_wdata[15:8] = data_i[15:8];
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if (be_i[2])
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reg_wdata[23:16] = data_i[23:16];
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if (be_i[3])
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reg_wdata[31:24] = data_i[31:24];
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end
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end
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gen_en_dff #(32) ie_ff(clk_i, rst_ni, ie_we, reg_wdata, ie_q);
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logic [31:0] ip_wdata;
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assign ip_wdata = ip_we ? reg_wdata : (ip_q | src_i);
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gen_en_dff #(32) ip_ff(clk_i, rst_ni, 1'b1, ip_wdata, ip_q);
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for (genvar m = 0; m < 8; m = m + 1) begin
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gen_en_dff #(32) prio_ff(clk_i, rst_ni, prio_we[m], reg_wdata, prio_q[m]);
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end
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// 读寄存器
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always_ff @ (posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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data_o <= 32'h0;
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end else begin
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case (addr_i[7:0])
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IE_OFFSET: data_o <= ie_q;
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IP_OFFSET: data_o <= ip_q;
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PRIO0_OFFSET: data_o <= prio_q[0];
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PRIO1_OFFSET: data_o <= prio_q[1];
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PRIO2_OFFSET: data_o <= prio_q[2];
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PRIO3_OFFSET: data_o <= prio_q[3];
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PRIO4_OFFSET: data_o <= prio_q[4];
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PRIO5_OFFSET: data_o <= prio_q[5];
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PRIO6_OFFSET: data_o <= prio_q[6];
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PRIO7_OFFSET: data_o <= prio_q[7];
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ID_OFFSET: data_o <= id_q;
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default: data_o <= 32'h0;
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endcase
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end
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end
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// 找出优先级最高(优先级值最大)的中断源
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// 二分法查找
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logic [7:0] each_prio[32];
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for (genvar i = 0; i < 8; i = i + 1) begin
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for (genvar j = 0; j < 4; j = j + 1) begin
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assign each_prio[i*4+j] = prio_q[i][8*j+7:8*j] & {8{ie_q[i*4+j]}};
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end
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end
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typedef struct packed {
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logic [7:0] id;
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logic [7:0] prio;
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} int_info_t;
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int_info_t l1_max[16];
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always_comb begin
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for (int i = 0; i < 16; i = i + 1) begin
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if (each_prio[2*i+1] > each_prio[2*i]) begin
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l1_max[i].id = 2*i+1;
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l1_max[i].prio = each_prio[2*i+1];
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end else begin
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l1_max[i].id = 2*i;
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l1_max[i].prio = each_prio[2*i];
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end
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end
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end
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int_info_t l2_max[8];
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always_comb begin
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for (int i = 0; i < 8; i = i + 1) begin
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if (l1_max[2*i+1].prio > l1_max[2*i].prio) begin
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l2_max[i].id = l1_max[2*i+1].id;
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l2_max[i].prio = l1_max[2*i+1].prio;
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end else begin
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l2_max[i].id = l1_max[2*i].id;
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l2_max[i].prio = l1_max[2*i].prio;
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end
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end
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end
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int_info_t l3_max[4];
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always_comb begin
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for (int i = 0; i < 4; i = i + 1) begin
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if (l2_max[2*i+1].prio > l2_max[2*i].prio) begin
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l3_max[i].id = l2_max[2*i+1].id;
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l3_max[i].prio = l2_max[2*i+1].prio;
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end else begin
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l3_max[i].id = l2_max[2*i].id;
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l3_max[i].prio = l2_max[2*i].prio;
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end
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end
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end
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int_info_t l4_max[2];
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always_comb begin
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for (int i = 0; i < 2; i = i + 1) begin
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if (l3_max[2*i+1].prio > l3_max[2*i].prio) begin
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l4_max[i].id = l3_max[2*i+1].id;
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l4_max[i].prio = l3_max[2*i+1].prio;
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end else begin
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l4_max[i].id = l3_max[2*i].id;
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l4_max[i].prio = l3_max[2*i].prio;
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end
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end
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end
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logic [7:0] irq_id;
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assign irq_id = (l4_max[1].prio > l4_max[0].prio) ? l4_max[1].id : l4_max[0].id;
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always_ff @ (posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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irq_id_o <= 8'h0;
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irq_o <= 1'b0;
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end else begin
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irq_id_o <= irq_id;
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irq_o <= |((src_i | ip_q) & ie_q);
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end
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end
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assign id_q = {24'h0, irq_id};
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endmodule
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