tinyriscv/rtl/perips
liangkangnan 07b33baf94 perips: add spi master
Signed-off-by: liangkangnan <liangkangnan@163.com>
2020-05-05 18:31:08 +08:00
..
gpio.v use = instead of <= in combination logic 2020-05-02 11:57:25 +08:00
ram.v use = instead of <= in combination logic 2020-05-02 11:57:25 +08:00
rom.v use = instead of <= in combination logic 2020-05-02 11:57:25 +08:00
spi.v perips: add spi master 2020-05-05 18:31:08 +08:00
timer.v use = instead of <= in combination logic 2020-05-02 11:57:25 +08:00
uart_tx.v use = instead of <= in combination logic 2020-05-02 11:57:25 +08:00