126 lines
4.0 KiB
Systemverilog
126 lines
4.0 KiB
Systemverilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.sv"
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// 取指模块
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module ifu(
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input wire clk,
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input wire rst_n,
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input wire flush_i,
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input wire[31:0] flush_addr_i, // 跳转地址
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input wire[`STALL_WIDTH-1:0] stall_i, // 流水线暂停标志
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input wire jtag_halt_i,
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output wire[31:0] inst_o,
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output wire[31:0] pc_o,
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output wire inst_valid_o,
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output wire[31:0] ibus_addr_o,
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input wire[31:0] ibus_data_i,
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output wire[31:0] ibus_data_o,
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output wire[3:0] ibus_sel_o,
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output wire ibus_we_o,
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output wire req_valid_o,
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input wire req_ready_i,
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input wire rsp_valid_i,
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output wire rsp_ready_o
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);
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assign req_valid_o = (~rst_n)? 1'b0:
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(flush_i)? 1'b0:
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stall_i[`STALL_PC]? 1'b0:
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jtag_halt_i? 1'b0:
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1'b1;
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assign rsp_ready_o = (~rst_n)? 1'b0: 1'b1;
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wire ifu_req_hsked = (req_valid_o & req_ready_i);
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wire ifu_rsp_hsked = (rsp_valid_i & rsp_ready_o);
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// 在执行多周期指令或者请求不到总线时需要暂停
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wire stall = stall_i[`STALL_PC] | (~ifu_req_hsked);
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reg[31:0] pc;
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reg[31:0] pc_prev;
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always @ (posedge clk or negedge rst_n) begin
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// 复位
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if (!rst_n) begin
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pc <= `CPU_RESET_ADDR;
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pc_prev <= 32'h0;
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// 冲刷
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end else if (flush_i) begin
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pc <= flush_addr_i;
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// 暂停，取上一条指令
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end else if (stall) begin
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pc <= pc_prev;
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// 取下一条指令
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end else begin
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pc <= pc + 32'h4;
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pc_prev <= pc;
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end
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end
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wire[31:0] pc_r;
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// 将PC打一拍
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wire pc_ena = (~stall);
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gen_en_dff #(32) pc_dff(clk, rst_n, pc_ena, pc, pc_r);
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reg req_hasked_r;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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req_hasked_r <= 1'b1;
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end else begin
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req_hasked_r <= ifu_req_hsked;
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end
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end
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wire req_switched = ifu_req_hsked & (~req_hasked_r);
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reg rsp_hasked_r;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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rsp_hasked_r <= 1'b1;
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end else begin
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rsp_hasked_r <= ifu_rsp_hsked;
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end
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end
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wire rsp_switched = ifu_rsp_hsked & (~rsp_hasked_r);
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// 总线切换有两种情况：
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// 1.访存地址位于指令存储器：当访存完成后，ifu_req_hsked和ifu_rsp_hsked信号会同时从0变为1
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// 2.访存地址不位于指令存储器：当访存完成后，ifu_req_hsked先从0变为1和ifu_rsp_hsked后从0变为1
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// 只有第2种情况下取出来的指令是有效的，这里要把这两种情况识别出来
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wire bus_switched = req_switched & rsp_switched;
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// 取指地址
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assign ibus_addr_o = pc;
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assign pc_o = pc_r;
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wire inst_valid = ifu_rsp_hsked & (~flush_i) & (~bus_switched);
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assign inst_o = inst_valid? ibus_data_i: `INST_NOP;
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assign ibus_sel_o = 4'b1111;
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assign ibus_we_o = 1'b0;
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assign ibus_data_o = 32'h0;
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endmodule
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