141 lines
4.5 KiB
Systemverilog
141 lines
4.5 KiB
Systemverilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.sv"
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// CSR寄存器模块
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module csr_reg(
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input wire clk,
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input wire rst_n,
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// exu
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input wire exu_we_i, // exu模块写寄存器标志
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input wire[31:0] exu_waddr_i, // exu模块写寄存器地址
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input wire[31:0] exu_wdata_i, // exu模块写寄存器数据
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input wire[31:0] exu_raddr_i, // exu模块读寄存器地址
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output wire[31:0] exu_rdata_o, // exu模块读寄存器数据
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// clint
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input wire clint_we_i, // clint模块写寄存器标志
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input wire[31:0] clint_waddr_i, // clint模块写寄存器地址
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input wire[31:0] clint_wdata_i, // clint模块写寄存器数据
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output wire[31:0] mtvec_o, // mtvec寄存器值
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output wire[31:0] mepc_o, // mepc寄存器值
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output wire[31:0] mstatus_o // mstatus寄存器值
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);
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reg[63:0] cycle;
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reg[31:0] mtvec;
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reg[31:0] mcause;
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reg[31:0] mepc;
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reg[31:0] mie;
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reg[31:0] mstatus;
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reg[31:0] mscratch;
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assign mtvec_o = mtvec;
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assign mepc_o = mepc;
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assign mstatus_o = mstatus;
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// cycle counter
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// 复位撤销后就一直计数
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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cycle <= {32'h0, 32'h0};
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end else begin
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cycle <= cycle + 1'b1;
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end
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end
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wire we = exu_we_i | clint_we_i;
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wire[31:0] waddr = exu_we_i? exu_waddr_i: clint_waddr_i;
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wire[31:0] wdata = exu_we_i? exu_wdata_i: clint_wdata_i;
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// 写寄存器
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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mtvec <= 32'h0;
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mcause <= 32'h0;
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mepc <= 32'h0;
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mie <= 32'h0;
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mstatus <= 32'h0;
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mscratch <= 32'h0;
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end else begin
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if (we) begin
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case (waddr[11:0])
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`CSR_MTVEC: begin
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mtvec <= wdata;
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end
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`CSR_MCAUSE: begin
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mcause <= wdata;
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end
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`CSR_MEPC: begin
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mepc <= wdata;
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end
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`CSR_MIE: begin
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mie <= wdata;
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end
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`CSR_MSTATUS: begin
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mstatus <= wdata;
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end
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`CSR_MSCRATCH: begin
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mscratch <= wdata;
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end
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endcase
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end
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end
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end
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reg[31:0] exu_rdata;
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// exu模块读CSR寄存器
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always @ (*) begin
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case (exu_raddr_i[11:0])
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`CSR_CYCLE: begin
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exu_rdata = cycle[31:0];
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end
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`CSR_CYCLEH: begin
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exu_rdata = cycle[63:32];
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end
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`CSR_MTVEC: begin
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exu_rdata = mtvec;
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end
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`CSR_MCAUSE: begin
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exu_rdata = mcause;
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end
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`CSR_MEPC: begin
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exu_rdata = mepc;
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end
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`CSR_MIE: begin
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exu_rdata = mie;
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end
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`CSR_MSTATUS: begin
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exu_rdata = mstatus;
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end
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`CSR_MSCRATCH: begin
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exu_rdata = mscratch;
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end
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default: begin
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exu_rdata = 32'h0;
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end
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endcase
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end
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assign exu_rdata_o = exu_rdata;
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endmodule
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