52 lines
1.9 KiB
Systemverilog
52 lines
1.9 KiB
Systemverilog
/*
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Copyright 2021 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module up_counter #(
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parameter int unsigned WIDTH = 4
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)(
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input logic clk_i,
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input logic rst_ni,
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input logic clear_i, // 同步清零
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input logic en_i, // 使能，开始计数
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output logic [WIDTH-1:0] q_o, // 当前计数值
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output logic overflow_o // 溢出标志
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);
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logic [WIDTH:0] counter_d, counter_q;
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assign overflow_o = counter_q[WIDTH];
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assign q_o = counter_q[WIDTH-1:0];
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always_comb begin
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counter_d = counter_q;
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if (clear_i) begin
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counter_d = '0;
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end else if (en_i) begin
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counter_d = counter_q + 1'b1;
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end
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end
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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counter_q <= '0;
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end else begin
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counter_q <= counter_d;
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end
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end
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endmodule
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