124 lines
4.2 KiB
Smarty
124 lines
4.2 KiB
Smarty
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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//
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// tb__xbar_connect generated by `topgen.py` tool
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<%
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from collections import OrderedDict
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import topgen.lib as lib
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top_hier = 'tb.dut.top_' + top["name"] + '.'
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clk_hier = top_hier + top["clocks"].hier_paths["top"]
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clk_src = OrderedDict()
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for xbar in top["xbar"]:
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for clk, src in xbar["clock_srcs"].items():
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clk_src[clk] = src
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clk_freq = OrderedDict()
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for clock in top["clocks"].all_srcs.values():
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if clock.name in clk_src.values():
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clk_freq[clock.name] = clock.freq
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hosts = OrderedDict()
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devices = OrderedDict()
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for xbar in top["xbar"]:
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for node in xbar["nodes"]:
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if node["type"] == "host" and not node["xbar"]:
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hosts[node["name"]] = "clk_" + clk_src[node["clock"]]
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elif node["type"] == "device" and not node["xbar"]:
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devices[node["name"]] = "clk_" + clk_src[node["clock"]]
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def escape_if_name(qual_if_name):
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return qual_if_name.replace('.', '__')
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%>\
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<%text>
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`define DRIVE_CHIP_TL_HOST_IF(tl_name, inst_name, sig_name) \
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force ``tl_name``_tl_if.d2h = dut.top_earlgrey.u_``inst_name``.``sig_name``_i; \
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force dut.top_earlgrey.u_``inst_name``.``sig_name``_o = ``tl_name``_tl_if.h2d; \
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force dut.top_earlgrey.u_``inst_name``.clk_i = 0; \
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uvm_config_db#(virtual tl_if)::set(null, $sformatf("*env.%0s_agent", `"tl_name`"), "vif", \
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``tl_name``_tl_if);
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`define DRIVE_CHIP_TL_DEVICE_IF(tl_name, inst_name, sig_name) \
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force ``tl_name``_tl_if.h2d = dut.top_earlgrey.u_``inst_name``.``sig_name``_i; \
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force dut.top_earlgrey.u_``inst_name``.``sig_name``_o = ``tl_name``_tl_if.d2h; \
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force dut.top_earlgrey.u_``inst_name``.clk_i = 0; \
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uvm_config_db#(virtual tl_if)::set(null, $sformatf("*env.%0s_agent", `"tl_name`"), "vif", \
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``tl_name``_tl_if);
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`define DRIVE_CHIP_TL_EXT_DEVICE_IF(tl_name, port_name) \
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force ``tl_name``_tl_if.h2d = dut.top_earlgrey.``port_name``_req_o; \
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force dut.top_earlgrey.``port_name``_rsp_i = ``tl_name``_tl_if.d2h; \
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uvm_config_db#(virtual tl_if)::set(null, $sformatf("*env.%0s_agent", `"tl_name`"), "vif", \
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``tl_name``_tl_if);
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</%text>\
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% for c in clk_freq.keys():
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wire clk_${c};
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clk_rst_if clk_rst_if_${c}(.clk(clk_${c}), .rst_n(rst_n));
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% endfor
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% for i, clk in hosts.items():
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tl_if ${escape_if_name(i)}_tl_if(${clk}, rst_n);
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% endfor
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% for i, clk in devices.items():
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tl_if ${escape_if_name(i)}_tl_if(${clk}, rst_n);
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% endfor
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initial begin
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bit xbar_mode;
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void'($value$plusargs("xbar_mode=%0b", xbar_mode));
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if (xbar_mode) begin
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// only enable assertions in xbar as many pins are unconnected
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$assertoff(0, tb);
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% for xbar in top["xbar"]:
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$asserton(0, tb.dut.top_${top["name"]}.u_xbar_${xbar["name"]});
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% endfor
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% for c in clk_freq.keys():
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clk_rst_if_${c}.set_active(.drive_rst_n_val(0));
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clk_rst_if_${c}.set_freq_khz(${clk_freq[c]} / 1000);
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% endfor
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// bypass clkmgr, force clocks directly
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% for xbar in top["xbar"]:
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% for clk, src in xbar["clock_srcs"].items():
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force ${top_hier}u_xbar_${xbar["name"]}.${clk} = clk_${src};
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% endfor
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% endfor
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// bypass rstmgr, force resets directly
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% for xbar in top["xbar"]:
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% for rst in xbar["reset_connections"]:
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force ${top_hier}u_xbar_${xbar["name"]}.${rst} = rst_n;
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% endfor
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% endfor
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% for xbar in top["xbar"]:
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% for node in xbar["nodes"]:
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<%
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clk = 'clk_' + clk_src[node["clock"]]
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esc_name = node['name'].replace('.', '__')
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inst_sig_list = lib.find_otherside_modules(top, xbar["name"], 'tl_' + esc_name)
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inst_name = inst_sig_list[0][1]
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sig_name = inst_sig_list[0][2]
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%>\
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% if node["type"] == "host" and not node["xbar"]:
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`DRIVE_CHIP_TL_HOST_IF(${esc_name}, ${inst_name}, ${sig_name})
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% elif node["type"] == "device" and not node["xbar"] and node["stub"]:
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`DRIVE_CHIP_TL_EXT_DEVICE_IF(${esc_name}, ${inst_name}_${sig_name})
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% elif node["type"] == "device" and not node["xbar"]:
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`DRIVE_CHIP_TL_DEVICE_IF(${esc_name}, ${inst_name}, ${sig_name})
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% endif
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% endfor
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% endfor
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end
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end
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`undef DRIVE_CHIP_TL_HOST_IF
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`undef DRIVE_CHIP_TL_DEVICE_IF
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`undef DRIVE_CHIP_TL_EXT_DEVICE_IF
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