94 lines
3.4 KiB
ArmAsm
94 lines
3.4 KiB
ArmAsm
# See LICENSE for license details.
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#*****************************************************************************
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# srl.S
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#-----------------------------------------------------------------------------
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#
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# Test srl instruction.
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#
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#include "riscv_test.h"
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#include "test_macros.h"
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RVTEST_RV64U
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RVTEST_CODE_BEGIN
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#-------------------------------------------------------------
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# Arithmetic tests
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#-------------------------------------------------------------
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#define TEST_SRL(n, v, a) \
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TEST_RR_OP(n, srl, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a)
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TEST_SRL( 2, 0xffffffff80000000, 0 );
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TEST_SRL( 3, 0xffffffff80000000, 1 );
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TEST_SRL( 4, 0xffffffff80000000, 7 );
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TEST_SRL( 5, 0xffffffff80000000, 14 );
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TEST_SRL( 6, 0xffffffff80000001, 31 );
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TEST_SRL( 7, 0xffffffffffffffff, 0 );
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TEST_SRL( 8, 0xffffffffffffffff, 1 );
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TEST_SRL( 9, 0xffffffffffffffff, 7 );
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TEST_SRL( 10, 0xffffffffffffffff, 14 );
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TEST_SRL( 11, 0xffffffffffffffff, 31 );
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TEST_SRL( 12, 0x0000000021212121, 0 );
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TEST_SRL( 13, 0x0000000021212121, 1 );
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TEST_SRL( 14, 0x0000000021212121, 7 );
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TEST_SRL( 15, 0x0000000021212121, 14 );
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TEST_SRL( 16, 0x0000000021212121, 31 );
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# Verify that shifts only use bottom five bits
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TEST_RR_OP( 17, srl, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 );
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TEST_RR_OP( 18, srl, 0x0000000010909090, 0x0000000021212121, 0xffffffffffffffc1 );
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TEST_RR_OP( 19, srl, 0x0000000000424242, 0x0000000021212121, 0xffffffffffffffc7 );
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TEST_RR_OP( 20, srl, 0x0000000000008484, 0x0000000021212121, 0xffffffffffffffce );
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TEST_RR_OP( 21, srl, 0x0000000000000000, 0x0000000021212121, 0xffffffffffffffff );
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#-------------------------------------------------------------
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# Source/Destination tests
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#-------------------------------------------------------------
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TEST_RR_SRC1_EQ_DEST( 22, srl, 0x01000000, 0x80000000, 7 );
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TEST_RR_SRC2_EQ_DEST( 23, srl, 0x00020000, 0x80000000, 14 );
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TEST_RR_SRC12_EQ_DEST( 24, srl, 0, 7 );
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#-------------------------------------------------------------
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# Bypassing tests
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#-------------------------------------------------------------
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TEST_RR_DEST_BYPASS( 25, 0, srl, 0x01000000, 0x80000000, 7 );
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TEST_RR_DEST_BYPASS( 26, 1, srl, 0x00020000, 0x80000000, 14 );
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TEST_RR_DEST_BYPASS( 27, 2, srl, 0x00000001, 0x80000000, 31 );
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TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0x01000000, 0x80000000, 7 );
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TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0x00020000, 0x80000000, 14 );
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TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0x00000001, 0x80000000, 31 );
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TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0x01000000, 0x80000000, 7 );
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TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0x00020000, 0x80000000, 14 );
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TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0x00000001, 0x80000000, 31 );
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TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0x01000000, 0x80000000, 7 );
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TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0x00020000, 0x80000000, 14 );
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TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0x00000001, 0x80000000, 31 );
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TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0x01000000, 0x80000000, 7 );
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TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0x00020000, 0x80000000, 14 );
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TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0x00000001, 0x80000000, 31 );
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TEST_RR_ZEROSRC1( 40, srl, 0, 15 );
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TEST_RR_ZEROSRC2( 41, srl, 32, 32 );
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TEST_RR_ZEROSRC12( 42, srl, 0 );
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TEST_RR_ZERODEST( 43, srl, 1024, 2048 );
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TEST_PASSFAIL
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
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TEST_DATA
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RVTEST_DATA_END
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