112 lines
4.6 KiB
Verilog
112 lines
4.6 KiB
Verilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.v"
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// 将译码结果向执行模块传递
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module id_ex(
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input wire clk,
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input wire rst,
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input wire[`InstBus] inst_i, // 指令内容
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input wire[`InstAddrBus] inst_addr_i, // 指令地址
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input wire reg_we_i, // 写通用寄存器标志
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input wire[`RegAddrBus] reg_waddr_i, // 写通用寄存器地址
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input wire[`RegBus] reg1_rdata_i, // 通用寄存器1读数据
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input wire[`RegBus] reg2_rdata_i, // 通用寄存器2读数据
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input wire csr_we_i, // 写CSR寄存器标志
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input wire[`MemAddrBus] csr_waddr_i, // 写CSR寄存器地址
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input wire[`RegBus] csr_rdata_i, // CSR寄存器读数据
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input wire[`MemAddrBus] op1_i,
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input wire[`MemAddrBus] op2_i,
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input wire[`MemAddrBus] op1_jump_i,
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input wire[`MemAddrBus] op2_jump_i,
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input wire[`Hold_Flag_Bus] hold_flag_i, // 流水线暂停标志
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output wire[`MemAddrBus] op1_o,
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output wire[`MemAddrBus] op2_o,
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output wire[`MemAddrBus] op1_jump_o,
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output wire[`MemAddrBus] op2_jump_o,
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output wire[`InstBus] inst_o, // 指令内容
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output wire[`InstAddrBus] inst_addr_o, // 指令地址
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output wire reg_we_o, // 写通用寄存器标志
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output wire[`RegAddrBus] reg_waddr_o, // 写通用寄存器地址
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output wire[`RegBus] reg1_rdata_o, // 通用寄存器1读数据
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output wire[`RegBus] reg2_rdata_o, // 通用寄存器2读数据
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output wire csr_we_o, // 写CSR寄存器标志
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output wire[`MemAddrBus] csr_waddr_o, // 写CSR寄存器地址
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output wire[`RegBus] csr_rdata_o // CSR寄存器读数据
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);
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wire hold_en = (hold_flag_i >= `Hold_Id);
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wire[`InstBus] inst;
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gen_pipe_dff #(32) inst_ff(clk, rst, hold_en, `INST_NOP, inst_i, inst);
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assign inst_o = inst;
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wire[`InstAddrBus] inst_addr;
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gen_pipe_dff #(32) inst_addr_ff(clk, rst, hold_en, `ZeroWord, inst_addr_i, inst_addr);
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assign inst_addr_o = inst_addr;
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wire reg_we;
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gen_pipe_dff #(1) reg_we_ff(clk, rst, hold_en, `WriteDisable, reg_we_i, reg_we);
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assign reg_we_o = reg_we;
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wire[`RegAddrBus] reg_waddr;
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gen_pipe_dff #(5) reg_waddr_ff(clk, rst, hold_en, `ZeroReg, reg_waddr_i, reg_waddr);
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assign reg_waddr_o = reg_waddr;
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wire[`RegBus] reg1_rdata;
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gen_pipe_dff #(32) reg1_rdata_ff(clk, rst, hold_en, `ZeroWord, reg1_rdata_i, reg1_rdata);
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assign reg1_rdata_o = reg1_rdata;
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wire[`RegBus] reg2_rdata;
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gen_pipe_dff #(32) reg2_rdata_ff(clk, rst, hold_en, `ZeroWord, reg2_rdata_i, reg2_rdata);
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assign reg2_rdata_o = reg2_rdata;
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wire csr_we;
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gen_pipe_dff #(1) csr_we_ff(clk, rst, hold_en, `WriteDisable, csr_we_i, csr_we);
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assign csr_we_o = csr_we;
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wire[`MemAddrBus] csr_waddr;
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gen_pipe_dff #(32) csr_waddr_ff(clk, rst, hold_en, `ZeroWord, csr_waddr_i, csr_waddr);
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assign csr_waddr_o = csr_waddr;
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wire[`RegBus] csr_rdata;
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gen_pipe_dff #(32) csr_rdata_ff(clk, rst, hold_en, `ZeroWord, csr_rdata_i, csr_rdata);
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assign csr_rdata_o = csr_rdata;
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wire[`MemAddrBus] op1;
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gen_pipe_dff #(32) op1_ff(clk, rst, hold_en, `ZeroWord, op1_i, op1);
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assign op1_o = op1;
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wire[`MemAddrBus] op2;
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gen_pipe_dff #(32) op2_ff(clk, rst, hold_en, `ZeroWord, op2_i, op2);
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assign op2_o = op2;
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wire[`MemAddrBus] op1_jump;
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gen_pipe_dff #(32) op1_jump_ff(clk, rst, hold_en, `ZeroWord, op1_jump_i, op1_jump);
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assign op1_jump_o = op1_jump;
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wire[`MemAddrBus] op2_jump;
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gen_pipe_dff #(32) op2_jump_ff(clk, rst, hold_en, `ZeroWord, op2_jump_i, op2_jump);
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assign op2_jump_o = op2_jump;
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endmodule
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