247 lines
8.1 KiB
Verilog
247 lines
8.1 KiB
Verilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// spi master模块
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module spi(
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input wire clk,
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input wire rst,
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input wire[31:0] data_i,
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input wire[31:0] addr_i,
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input wire we_i,
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input wire req_i,
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output reg[31:0] data_o,
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output reg ack_o,
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output reg spi_mosi, // spi控制器输出、spi设备输入信号
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input wire spi_miso, // spi控制器输入、spi设备输出信号
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output wire spi_ss, // spi设备片选
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output reg spi_clk // spi设备时钟，最大频率为输入clk的一半
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);
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localparam SPI_CTRL = 4'h0; // spi_ctrl寄存器地址偏移
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localparam SPI_DATA = 4'h4; // spi_data寄存器地址偏移
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localparam SPI_STATUS = 4'h8; // spi_status寄存器地址偏移
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// spi控制寄存器
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// addr: 0x00
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// [0]: 1: enable, 0: disable
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// [1]: CPOL
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// [2]: CPHA
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// [3]: select slave, 1: select, 0: deselect
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// [15:8]: clk div
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reg[31:0] spi_ctrl;
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// spi数据寄存器
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// addr: 0x04
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// [7:0] cmd or inout data
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reg[31:0] spi_data;
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// spi状态寄存器
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// addr: 0x08
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// [0]: 1: busy, 0: idle
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reg[31:0] spi_status;
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reg[8:0] clk_cnt; // 分频计数
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reg en; // 使能，开始传输信号，传输期间一直有效
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reg[4:0] spi_clk_edge_cnt; // spi clk时钟沿的个数
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reg spi_clk_edge_level; // spi clk沿电平
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reg[7:0] rdata; // 从spi设备读回来的数据
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reg done; // 传输完成信号
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reg[3:0] bit_index; // 数据bit索引
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wire[8:0] div_cnt;
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assign spi_ss = ~spi_ctrl[3]; // SPI设备片选信号
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assign div_cnt = spi_ctrl[15:8];// 0: 2分频，1：4分频，2：8分频，3：16分频，4：32分频，以此类推
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// 产生使能信号
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// 传输期间一直有效
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always @ (posedge clk) begin
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if (rst == 1'b0) begin
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en <= 1'b0;
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end else begin
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if (spi_ctrl[0] == 1'b1) begin
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en <= 1'b1;
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end else if (done == 1'b1) begin
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en <= 1'b0;
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end else begin
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en <= en;
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end
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end
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end
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// 对输入时钟进行计数
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always @ (posedge clk) begin
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if (rst == 1'b0) begin
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clk_cnt <= 9'h0;
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end else if (en == 1'b1) begin
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if (clk_cnt == div_cnt) begin
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clk_cnt <= 9'h0;
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end else begin
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clk_cnt <= clk_cnt + 1'b1;
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end
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end else begin
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clk_cnt <= 9'h0;
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end
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end
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// 对spi clk沿进行计数
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// 每当计数到分频值时产生一个上升沿脉冲
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always @ (posedge clk) begin
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if (rst == 1'b0) begin
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spi_clk_edge_cnt <= 5'h0;
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spi_clk_edge_level <= 1'b0;
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end else if (en == 1'b1) begin
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// 计数达到分频值
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if (clk_cnt == div_cnt) begin
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if (spi_clk_edge_cnt == 5'd17) begin
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spi_clk_edge_cnt <= 5'h0;
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spi_clk_edge_level <= 1'b0;
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end else begin
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spi_clk_edge_cnt <= spi_clk_edge_cnt + 1'b1;
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spi_clk_edge_level <= 1'b1;
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end
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end else begin
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spi_clk_edge_level <= 1'b0;
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end
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end else begin
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spi_clk_edge_cnt <= 5'h0;
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spi_clk_edge_level <= 1'b0;
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end
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end
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// bit序列
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always @ (posedge clk) begin
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if (rst == 1'b0) begin
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spi_clk <= 1'b0;
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rdata <= 8'h0;
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spi_mosi <= 1'b0;
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bit_index <= 4'h0;
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end else begin
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if (en) begin
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if (spi_clk_edge_level == 1'b1) begin
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case (spi_clk_edge_cnt)
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// 第奇数个时钟沿
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1, 3, 5, 7, 9, 11, 13, 15: begin
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spi_clk <= ~spi_clk;
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if (spi_ctrl[2] == 1'b1) begin
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spi_mosi <= spi_data[bit_index]; // 送出1bit数据
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bit_index <= bit_index - 1'b1;
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end else begin
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rdata <= {rdata[6:0], spi_miso}; // 读1bit数据
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end
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end
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// 第偶数个时钟沿
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2, 4, 6, 8, 10, 12, 14, 16: begin
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spi_clk <= ~spi_clk;
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if (spi_ctrl[2] == 1'b1) begin
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rdata <= {rdata[6:0], spi_miso}; // 读1bit数据
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end else begin
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spi_mosi <= spi_data[bit_index]; // 送出1bit数据
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bit_index <= bit_index - 1'b1;
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end
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end
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17: begin
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spi_clk <= spi_ctrl[1];
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end
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endcase
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end
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end else begin
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// 初始状态
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spi_clk <= spi_ctrl[1];
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if (spi_ctrl[2] == 1'b0) begin
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spi_mosi <= spi_data[7]; // 送出最高位数据
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bit_index <= 4'h6;
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end else begin
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bit_index <= 4'h7;
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end
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end
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end
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end
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// 产生结束(完成)信号
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always @ (posedge clk) begin
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if (rst == 1'b0) begin
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done <= 1'b0;
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end else begin
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if (en && spi_clk_edge_cnt == 5'd17) begin
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done <= 1'b1;
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end else begin
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done <= 1'b0;
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end
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end
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end
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// write reg
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always @ (posedge clk) begin
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if (rst == 1'b0) begin
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spi_ctrl <= 32'h0;
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spi_data <= 32'h0;
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spi_status <= 32'h0;
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end else begin
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spi_status[0] <= en;
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if (we_i == 1'b1) begin
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case (addr_i[3:0])
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SPI_CTRL: begin
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spi_ctrl <= data_i;
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end
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SPI_DATA: begin
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spi_data <= data_i;
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end
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default: begin
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end
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endcase
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end else begin
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spi_ctrl[0] <= 1'b0;
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// 发送完成后更新数据寄存器
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if (done == 1'b1) begin
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spi_data <= {24'h0, rdata};
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end
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end
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end
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end
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// read reg
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always @ (*) begin
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if (rst == 1'b0) begin
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data_o = 32'h0;
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end else begin
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case (addr_i[3:0])
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SPI_CTRL: begin
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data_o = spi_ctrl;
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end
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SPI_DATA: begin
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data_o = spi_data;
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end
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SPI_STATUS: begin
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data_o = spi_status;
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end
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default: begin
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data_o = 32'h0;
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end
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endcase
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end
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end
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endmodule
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