518 lines
16 KiB
Systemverilog
518 lines
16 KiB
Systemverilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.sv"
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// CSR寄存器模块
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module csr_reg(
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input wire clk,
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input wire rst_n,
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// from exu
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input wire exu_we_i, // exu模块写寄存器标志
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input wire[31:0] exu_waddr_i, // exu模块写寄存器地址
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input wire[31:0] exu_wdata_i, // exu模块写寄存器数据
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input wire[31:0] exu_raddr_i, // exu模块读寄存器地址
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output wire[31:0] exu_rdata_o, // exu模块读寄存器数据
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input wire[31:0] pc_if_i, // 取指地址
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output wire trigger_match_o, // 断点
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// form exception
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input wire excep_we_i, // exception模块写寄存器标志
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input wire[31:0] excep_waddr_i, // exception模块写寄存器地址
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input wire[31:0] excep_wdata_i, // exception模块写寄存器数据
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output wire[31:0] mtvec_o, // mtvec寄存器值
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output wire[31:0] mepc_o, // mepc寄存器值
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output wire[31:0] mstatus_o, // mstatus寄存器值
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output wire[31:0] mie_o, // mie寄存器值
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output wire[31:0] dpc_o, // dpc寄存器值
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output wire[31:0] dcsr_o // dcsr寄存器值
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);
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// 硬件断点个数(必须大于等于1)
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localparam HwBpNum = 3;
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localparam DbgHwNumLen = HwBpNum > 1 ? $clog2(HwBpNum) : 1;
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localparam MaxTselect = HwBpNum - 1;
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wire[31:0] max_tselect = MaxTselect;
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wire[31:0] misa = 32'h40001100; // 32bits, IM
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// for verification result
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reg[31:0] sstatus_d;
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wire[31:0] sstatus_q;
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reg sstatus_we;
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reg[31:0] mtvec_d;
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wire[31:0] mtvec_q;
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reg mtvec_we;
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reg[31:0] mcause_d;
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wire[31:0] mcause_q;
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reg mcause_we;
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reg[31:0] mepc_d;
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wire[31:0] mepc_q;
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reg mepc_we;
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reg[31:0] mie_d;
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wire[31:0] mie_q;
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reg mie_we;
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reg[31:0] mstatus_d;
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wire[31:0] mstatus_q;
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reg mstatus_we;
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reg[31:0] mscratch_d;
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wire[31:0] mscratch_q;
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reg mscratch_we;
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reg[31:0] dscratch0_d;
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wire[31:0] dscratch0_q;
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reg dscratch0_we;
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reg[31:0] dscratch1_d;
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wire[31:0] dscratch1_q;
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reg dscratch1_we;
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reg[31:0] mhartid_d;
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wire[31:0] mhartid_q;
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reg mhartid_we;
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reg[31:0] dpc_d;
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wire[31:0] dpc_q;
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reg dpc_we;
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reg[31:0] dcsr_d;
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wire[31:0] dcsr_q;
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reg dcsr_we;
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reg[31:0] tselect_d;
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wire[31:0] tselect_q;
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reg tselect_we;
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wire tmatch_control_d;
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wire[HwBpNum-1:0] tmatch_control_q;
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wire[HwBpNum-1:0] tmatch_control_we;
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wire[31:0] tmatch_value_d;
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wire[31:0] tmatch_value_q[HwBpNum];
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wire[HwBpNum-1:0] tmatch_value_we;
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wire[HwBpNum-1:0] trigger_match;
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wire[31:0] tmatch_control_rdata;
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wire[31:0] tmatch_value_rdata;
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wire selected_tmatch_control;
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wire[31:0] selected_tmatch_value;
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reg[63:0] cycle;
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// cycle counter
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// 复位撤销后就一直计数
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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cycle <= {32'h0, 32'h0};
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end else begin
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cycle <= cycle + 1'b1;
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end
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end
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assign mtvec_o = mtvec_q;
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assign mepc_o = mepc_q;
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assign mstatus_o = mstatus_q;
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assign mie_o = mie_q;
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assign dpc_o = dpc_q;
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assign dcsr_o = dcsr_q;
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reg[31:0] exu_rdata;
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// exu模块读CSR寄存器
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always @ (*) begin
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case (exu_raddr_i[11:0])
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`CSR_CYCLE: begin
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exu_rdata = cycle[31:0];
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end
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`CSR_CYCLEH: begin
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exu_rdata = cycle[63:32];
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end
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`CSR_MTVEC: begin
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exu_rdata = mtvec_q;
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end
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`CSR_MCAUSE: begin
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exu_rdata = mcause_q;
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end
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`CSR_MEPC: begin
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exu_rdata = mepc_q;
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end
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`CSR_MIE: begin
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exu_rdata = mie_q;
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end
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`CSR_MSTATUS: begin
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exu_rdata = mstatus_q;
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end
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`CSR_MSCRATCH: begin
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exu_rdata = mscratch_q;
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end
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`CSR_DSCRATCH0: begin
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exu_rdata = dscratch0_q;
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end
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`CSR_DSCRATCH1: begin
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exu_rdata = dscratch1_q;
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end
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`CSR_MHARTID: begin
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exu_rdata = mhartid_q;
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end
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`CSR_DPC: begin
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exu_rdata = dpc_q;
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end
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`CSR_DCSR: begin
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exu_rdata = dcsr_q;
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end
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`CSR_MISA: begin
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exu_rdata = misa;
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end
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`CSR_TSELECT: begin
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exu_rdata = tselect_q;
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end
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`CSR_TDATA1: begin
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exu_rdata = tmatch_control_rdata;
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end
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`CSR_TDATA2: begin
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exu_rdata = tmatch_value_rdata;
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end
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default: begin
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exu_rdata = 32'h0;
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end
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endcase
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end
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assign exu_rdata_o = exu_rdata;
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// 写CSR寄存器
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wire we = exu_we_i | excep_we_i;
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wire[31:0] waddr = exu_we_i? exu_waddr_i: excep_waddr_i;
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wire[31:0] wdata = exu_we_i? exu_wdata_i: excep_wdata_i;
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always @ (*) begin
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mtvec_d = mtvec_q;
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mtvec_we = 1'b0;
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mcause_d = mcause_q;
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mcause_we = 1'b0;
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mepc_d = mepc_q;
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mepc_we = 1'b0;
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mie_d = mie_q;
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mie_we = 1'b0;
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mstatus_d = mstatus_q;
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mstatus_we = 1'b0;
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mscratch_d = mscratch_q;
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mscratch_we = 1'b0;
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dscratch0_d = dscratch0_q;
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dscratch0_we = 1'b0;
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dscratch1_d = dscratch1_q;
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dscratch1_we = 1'b0;
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mhartid_d = mhartid_q;
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mhartid_we = 1'b0;
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dpc_d = dpc_q;
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dpc_we = 1'b0;
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dcsr_d = dcsr_q;
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dcsr_we = 1'b0;
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sstatus_d = sstatus_q;
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sstatus_we = 1'b0;
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if (we) begin
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case (waddr[11:0])
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`CSR_MTVEC: begin
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mtvec_d = wdata;
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mtvec_we = 1'b1;
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end
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`CSR_MCAUSE: begin
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mcause_d = wdata;
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mcause_we = 1'b1;
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end
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`CSR_MEPC: begin
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mepc_d = wdata;
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mepc_we = 1'b1;
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end
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`CSR_MIE: begin
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mie_d = wdata;
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mie_we = 1'b1;
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end
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`CSR_MSTATUS: begin
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mstatus_d = wdata;
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mstatus_we = 1'b1;
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end
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`CSR_MSCRATCH: begin
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mscratch_d = wdata;
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mscratch_we = 1'b1;
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end
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`CSR_DSCRATCH0: begin
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dscratch0_d = wdata;
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dscratch0_we = 1'b1;
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end
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`CSR_DSCRATCH1: begin
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dscratch1_d = wdata;
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dscratch1_we = 1'b1;
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end
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`CSR_MHARTID: begin
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mhartid_d = wdata;
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mhartid_we = 1'b1;
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end
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`CSR_SSTATUS: begin
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sstatus_d = wdata;
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sstatus_we = 1'b1;
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end
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`CSR_DPC: begin
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dpc_d = wdata;
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dpc_we = 1'b1;
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end
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`CSR_DCSR: begin
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// Not all bits in DCSR are writable by exu
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if (exu_we_i) begin
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dcsr_d = {dcsr_q[31:28], wdata[27:9], dcsr_q[8:6], wdata[5:4], dcsr_q[3], wdata[2:0]};
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end else begin
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dcsr_d = wdata;
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end
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dcsr_we = 1'b1;
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end
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default:;
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endcase
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end
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end
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// trigger control
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assign tselect_we = (exu_waddr_i[11:0] == `CSR_TSELECT) & exu_we_i;
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for (genvar i = 0; i < HwBpNum; i = i + 1) begin : dbg_tmatch_we
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assign tmatch_control_we[i] = (i == tselect_q) &
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exu_we_i &
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(exu_waddr_i[11:0] == `CSR_TDATA1);
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assign tmatch_value_we[i] = (i == tselect_q) &
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exu_we_i &
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(exu_waddr_i[11:0] == `CSR_TDATA2);
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end
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assign tselect_d = (exu_wdata_i < HwBpNum) ? exu_wdata_i : max_tselect;
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assign tmatch_control_d = exu_wdata_i[2];
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assign tmatch_value_d = exu_wdata_i;
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if (HwBpNum > 1) begin : dbg_tmatch_multiple_select
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assign selected_tmatch_control = tmatch_control_q[tselect_q];
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assign selected_tmatch_value = tmatch_value_q[tselect_q];
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end else begin : dbg_tmatch_single_select
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assign selected_tmatch_control = tmatch_control_q[0];
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assign selected_tmatch_value = tmatch_value_q[0];
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end
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// TDATA0 - only support simple address matching
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assign tmatch_control_rdata = {4'h2, // type : address/data match
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1'b1, // dmode : access from D mode only
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6'h00, // maskmax : exact match only
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1'b0, // hit : not supported
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1'b0, // select : address match only
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1'b0, // timing : match before execution
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2'b00, // sizelo : match any access
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4'h1, // action : enter debug mode
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1'b0, // chain : not supported
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4'h0, // match : simple match
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1'b1, // m : match in m-mode
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1'b0, // 0 : zero
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1'b0, // s : not supported
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1'b1, // u : match in u-mode
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selected_tmatch_control, // execute : match instruction address
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1'b0, // store : not supported
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1'b0}; // load : not supported
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// TDATA1 - address match value only
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assign tmatch_value_rdata = selected_tmatch_value;
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// Breakpoint matching
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// We match against the next address, as the breakpoint must be taken before execution
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for (genvar i = 0; i < HwBpNum; i = i + 1) begin : dbg_trigger_match
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assign trigger_match[i] = tmatch_control_q[i] & (pc_if_i == tmatch_value_q[i]);
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end
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assign trigger_match_o = |trigger_match;
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// mtvec
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csr #(
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.RESET_VAL(32'h0)
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) mtvec_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(mtvec_d),
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.we_i(mtvec_we),
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.rdata_o(mtvec_q)
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);
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// mcause
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csr #(
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.RESET_VAL(32'h0)
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) mcause_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(mcause_d),
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.we_i(mcause_we),
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.rdata_o(mcause_q)
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);
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// mepc
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csr #(
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.RESET_VAL(32'h0)
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) mepc_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(mepc_d),
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.we_i(mepc_we),
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.rdata_o(mepc_q)
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);
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// mie
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csr #(
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.RESET_VAL(32'h0)
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) mie_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(mie_d),
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.we_i(mie_we),
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.rdata_o(mie_q)
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);
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// mstatus
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csr #(
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.RESET_VAL(32'h0)
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) mstatus_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(mstatus_d),
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.we_i(mstatus_we),
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.rdata_o(mstatus_q)
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);
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// mscratch
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csr #(
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.RESET_VAL(32'h0)
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) mscratch_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(mscratch_d),
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.we_i(mscratch_we),
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.rdata_o(mscratch_q)
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);
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// dscratch0
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csr #(
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.RESET_VAL(32'h0)
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) dscratch0_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(dscratch0_d),
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.we_i(dscratch0_we),
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.rdata_o(dscratch0_q)
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);
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// dscratch1
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csr #(
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.RESET_VAL(32'h0)
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) dscratch1_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(dscratch1_d),
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.we_i(dscratch1_we),
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.rdata_o(dscratch1_q)
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);
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// mhartid
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csr #(
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.RESET_VAL(32'h0)
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) mhartid_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(mhartid_d),
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.we_i(mhartid_we),
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.rdata_o(mhartid_q)
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);
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// dpc
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csr #(
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.RESET_VAL(32'h0)
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) dpc_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(dpc_d),
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.we_i(dpc_we),
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.rdata_o(dpc_q)
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);
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// dcsr
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csr #(
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.RESET_VAL(32'h40000000)
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) dcsr_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(dcsr_d),
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.we_i(dcsr_we),
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.rdata_o(dcsr_q)
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);
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// tselect
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csr #(
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.RESET_VAL(32'h0)
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) tselect_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(tselect_d),
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.we_i(tselect_we),
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.rdata_o(tselect_q)
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);
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// sstatus
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csr #(
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.RESET_VAL(32'h0)
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) sstatus_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(sstatus_d),
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.we_i(sstatus_we),
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.rdata_o(sstatus_q)
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);
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for (genvar i = 0; i < HwBpNum; i = i + 1) begin : dbg_tmatch_reg
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// tdata1
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csr #(
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.RESET_VAL(1'b0),
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.WIDTH(1)
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) tmatch_control_csr (
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.clk(clk),
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.rst_n(rst_n),
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.wdata_i(tmatch_control_d),
|
|
.we_i(tmatch_control_we[i]),
|
|
.rdata_o(tmatch_control_q[i])
|
|
);
|
|
|
|
// tdata2
|
|
csr #(
|
|
.RESET_VAL(32'h0)
|
|
) tmatch_value_csr (
|
|
.clk(clk),
|
|
.rst_n(rst_n),
|
|
.wdata_i(tmatch_value_d),
|
|
.we_i(tmatch_value_we[i]),
|
|
.rdata_o(tmatch_value_q[i])
|
|
);
|
|
end
|
|
|
|
// for debug
|
|
wire[31:0] mtvec = mtvec_q;
|
|
wire[31:0] mstatus = mstatus_q;
|
|
wire[31:0] mepc = mepc_q;
|
|
wire[31:0] mie = mie_q;
|
|
wire[31:0] dpc = dpc_q;
|
|
wire[31:0] dcsr = dcsr_q;
|
|
|
|
endmodule
|