98 lines
3.6 KiB
Systemverilog
98 lines
3.6 KiB
Systemverilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.sv"
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// 将译码结果向执行模块传递
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module idu_exu(
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input wire clk,
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input wire rst_n,
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input wire[`STALL_WIDTH-1:0] stall_i, // 流水线暂停
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input wire flush_i, // 流水线冲刷
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input wire[31:0] inst_i,
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input wire inst_valid_i,
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input wire[`DECINFO_WIDTH-1:0] dec_info_bus_i,
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input wire[31:0] dec_imm_i,
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input wire[31:0] dec_pc_i,
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input wire[31:0] rs1_rdata_i,
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input wire[31:0] rs2_rdata_i,
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input wire[4:0] rd_waddr_i,
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input wire rd_we_i,
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output wire[31:0] inst_o,
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output wire inst_valid_o,
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output wire[`DECINFO_WIDTH-1:0] dec_info_bus_o,
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output wire[31:0] dec_imm_o,
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output wire[31:0] dec_pc_o,
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output wire[31:0] rs1_rdata_o,
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output wire[31:0] rs2_rdata_o,
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output wire[4:0] rd_waddr_o,
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output wire rd_we_o
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);
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wire en = !stall_i[`STALL_EX] | flush_i;
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wire[`DECINFO_WIDTH-1:0] i_dec_info_bus = flush_i? {`DECINFO_WIDTH{1'b0}}: dec_info_bus_i;
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wire[`DECINFO_WIDTH-1:0] dec_info_bus;
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gen_en_dff #(`DECINFO_WIDTH) info_bus_ff(clk, rst_n, en, i_dec_info_bus, dec_info_bus);
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assign dec_info_bus_o = dec_info_bus;
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wire[31:0] i_dec_imm = flush_i? 32'h0: dec_imm_i;
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wire[31:0] dec_imm;
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gen_en_dff #(32) imm_ff(clk, rst_n, en, i_dec_imm, dec_imm);
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assign dec_imm_o = dec_imm;
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wire[31:0] i_dec_pc = flush_i? 32'h0: dec_pc_i;
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wire[31:0] dec_pc;
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gen_en_dff #(32) pc_ff(clk, rst_n, en, i_dec_pc, dec_pc);
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assign dec_pc_o = dec_pc;
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wire[31:0] i_rs1_rdata = flush_i? 32'h0: rs1_rdata_i;
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wire[31:0] rs1_rdata;
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gen_en_dff #(32) rs1_rdata_ff(clk, rst_n, en, i_rs1_rdata, rs1_rdata);
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assign rs1_rdata_o = rs1_rdata;
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wire[31:0] i_rs2_rdata = flush_i? 32'h0: rs2_rdata_i;
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wire[31:0] rs2_rdata;
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gen_en_dff #(32) rs2_rdata_ff(clk, rst_n, en, i_rs2_rdata, rs2_rdata);
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assign rs2_rdata_o = rs2_rdata;
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wire[4:0] i_rd_waddr = flush_i? 5'h0: rd_waddr_i;
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wire[4:0] rd_waddr;
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gen_en_dff #(5) rd_waddr_ff(clk, rst_n, en, i_rd_waddr, rd_waddr);
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assign rd_waddr_o = rd_waddr;
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wire i_rd_we = flush_i? 1'b0: rd_we_i;
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wire rd_we;
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gen_en_dff #(1) rd_we_ff(clk, rst_n, en, i_rd_we, rd_we);
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assign rd_we_o = rd_we;
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wire[31:0] i_inst = flush_i? 32'h0: inst_i;
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wire[31:0] inst;
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gen_en_dff #(32) inst_ff(clk, rst_n, en, i_inst, inst);
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assign inst_o = inst;
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wire i_inst_valid = flush_i? 1'b0: inst_valid_i;
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wire inst_valid;
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gen_en_dff #(1) inst_valid_ff(clk, rst_n, 1'b1, i_inst_valid, inst_valid);
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assign inst_valid_o = inst_valid;
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endmodule
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