129 lines
4.2 KiB
Python
129 lines
4.2 KiB
Python
# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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"""Enumerated types for fields
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Generated by validation, used by backends
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"""
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from enum import Enum
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from .lib import check_str
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class JsonEnum(Enum):
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def for_json(x) -> str:
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return str(x)
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class SwWrAccess(JsonEnum):
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WR = 1
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NONE = 2
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class SwRdAccess(JsonEnum):
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RD = 1
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RC = 2 # Special handling for port
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NONE = 3
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class SwAccess(JsonEnum):
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RO = 1
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RW = 2
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WO = 3
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W1C = 4
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W1S = 5
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W0C = 6
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RC = 7
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R0W1C = 8
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NONE = 9
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class HwAccess(JsonEnum):
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HRO = 1
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HRW = 2
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HWO = 3
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NONE = 4 # No access allowed
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# swaccess permitted values
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# text description, access enum, wr access enum, rd access enum, ok in window
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SWACCESS_PERMITTED = {
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'none': ("No access", # noqa: E241
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SwAccess.NONE, SwWrAccess.NONE, SwRdAccess.NONE, False), # noqa: E241
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'ro': ("Read Only", # noqa: E241
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SwAccess.RO, SwWrAccess.NONE, SwRdAccess.RD, True), # noqa: E241
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'rc': ("Read Only, reading clears", # noqa: E241
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SwAccess.RC, SwWrAccess.WR, SwRdAccess.RC, False), # noqa: E241
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'rw': ("Read/Write", # noqa: E241
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SwAccess.RW, SwWrAccess.WR, SwRdAccess.RD, True), # noqa: E241
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'r0w1c': ("Read zero, Write with 1 clears", # noqa: E241
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SwAccess.W1C, SwWrAccess.WR, SwRdAccess.NONE, False), # noqa: E241
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'rw1s': ("Read, Write with 1 sets", # noqa: E241
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SwAccess.W1S, SwWrAccess.WR, SwRdAccess.RD, False), # noqa: E241
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'rw1c': ("Read, Write with 1 clears", # noqa: E241
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SwAccess.W1C, SwWrAccess.WR, SwRdAccess.RD, False), # noqa: E241
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'rw0c': ("Read, Write with 0 clears", # noqa: E241
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SwAccess.W0C, SwWrAccess.WR, SwRdAccess.RD, False), # noqa: E241
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'wo': ("Write Only", # noqa: E241
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SwAccess.WO, SwWrAccess.WR, SwRdAccess.NONE, True) # noqa: E241
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}
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# hwaccess permitted values
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HWACCESS_PERMITTED = {
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'hro': ("Read Only", HwAccess.HRO),
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'hrw': ("Read/Write", HwAccess.HRW),
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'hwo': ("Write Only", HwAccess.HWO),
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'none': ("No Access Needed", HwAccess.NONE)
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}
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class SWAccess:
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def __init__(self, where: str, raw: object):
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self.key = check_str(raw, 'swaccess for {}'.format(where))
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try:
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self.value = SWACCESS_PERMITTED[self.key]
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except KeyError:
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raise ValueError('Unknown swaccess key, {}, for {}.'
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.format(self.key, where)) from None
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def dv_rights(self) -> str:
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'''Return a UVM access string as used by uvm_field::set_access().'''
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if self.key == 'r0w1c':
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return 'W1C'
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return self.value[1].name
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def swrd(self) -> SwRdAccess:
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return self.value[3]
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def allows_read(self) -> bool:
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return self.value[3] != SwRdAccess.NONE
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def allows_write(self) -> bool:
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return self.value[2] == SwWrAccess.WR
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def needs_we(self) -> bool:
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'''Should the register for this field have a write-enable signal?
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This is almost the same as allows_write(), but doesn't return true for
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RC registers, which should use a read-enable signal (connected to their
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prim_subreg's we port).
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'''
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return self.value[1] != SwAccess.RC and self.allows_write()
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class HWAccess:
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def __init__(self, where: str, raw: object):
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self.key = check_str(raw, 'hwaccess for {}'.format(where))
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try:
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self.value = HWACCESS_PERMITTED[self.key]
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except KeyError:
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raise ValueError('Unknown hwaccess key, {}, for {}.'
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.format(self.key, where)) from None
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def allows_read(self) -> bool:
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return self.key in ['hro', 'hrw']
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def allows_write(self) -> bool:
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return self.key in ['hrw', 'hwo']
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