132 lines
4.9 KiB
Verilog
132 lines
4.9 KiB
Verilog
`include "defines.v"
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module div (
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input wire clk,
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input wire rst,
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input wire[`RegBus] dividend_i,
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input wire[`RegBus] divisor_i,
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input wire start_i,
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output reg[`DoubleRegBus] result_o,
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output reg ready_o
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);
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parameter STATE_IDLE = 0;
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parameter STATE_START = 1;
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parameter STATE_REVERT = 2;
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parameter STATE_END = 3;
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reg[`RegBus] dividend_temp;
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reg[`RegBus] divisor_temp;
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reg[1:0] state;
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reg[6:0] count;
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reg[`RegBus] div_result;
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reg[`RegBus] div_remain;
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reg[`RegBus] minuend;
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reg[`RegBus] divisor_zero_result;
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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state <= STATE_IDLE;
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ready_o <= `DivResultNotReady;
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result_o <= {`ZeroWord, `ZeroWord};
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div_result <= `ZeroWord;
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div_remain <= `ZeroWord;
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divisor_zero_result <= ~32'b00000001 + 1'b1;
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end else begin
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case (state)
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STATE_IDLE: begin
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if (start_i == `DivStart) begin
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if (divisor_i == `ZeroWord) begin
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ready_o <= `DivResultReady;
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result_o <= {`ZeroWord, divisor_zero_result};
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end else begin
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count <= 7'd31;
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state <= STATE_START;
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if (dividend_i[31] == 1'b1) begin
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dividend_temp <= ~dividend_i + 1;
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minuend <= ((~dividend_i + 1) >> 7'd31) & 1'b1;
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end else begin
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dividend_temp <= dividend_i;
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minuend <= (dividend_i >> 7'd31) & 1'b1;
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end
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if (divisor_i[31] == 1'b1) begin
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divisor_temp <= ~divisor_i + 1;
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end else begin
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divisor_temp <= divisor_i;
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end
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div_result <= `ZeroWord;
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div_remain <= `ZeroWord;
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end
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end else begin
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ready_o <= `DivResultNotReady;
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result_o <= {`ZeroWord, `ZeroWord};
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end
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end
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STATE_START: begin
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if (start_i == `DivStart) begin
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if (count >= 7'd1) begin
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if (minuend >= divisor_temp) begin
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div_result <= (div_result << 1'b1) | 1'b1;
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minuend <= ((minuend - divisor_temp) << 1'b1) | ((dividend_temp >> (count - 1'b1)) & 1'b1);
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end else begin
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div_result <= (div_result << 1'b1) | 1'b0;
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minuend <= (minuend << 1'b1) | ((dividend_temp >> (count - 1'b1)) & 1'b1);
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end
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count <= count - 1'b1;
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end else begin
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state <= STATE_REVERT;
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if (minuend >= divisor_temp) begin
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div_result <= (div_result << 1'b1) | 1'b1;
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div_remain <= minuend - divisor_temp;
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end else begin
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div_result <= (div_result << 1'b1) | 1'b0;
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div_remain <= minuend;
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end
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end
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end else begin
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ready_o <= `DivResultReady;
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result_o <= {`ZeroWord, `ZeroWord};
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state <= STATE_IDLE;
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end
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end
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STATE_REVERT: begin
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if (start_i == `DivStart) begin
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if (dividend_i[31] ^ divisor_i[31] == 1'b1) begin
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div_result <= ~div_result + 1'b1;
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end
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if (((dividend_i[31] == 1'b1) && (div_remain >= 0)) || ((dividend_i[31] == 1'b0) && (div_remain < 0))) begin
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div_remain <= ~div_remain + 1'b1;
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end
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state <= STATE_END;
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end else begin
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ready_o <= `DivResultReady;
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result_o <= {`ZeroWord, `ZeroWord};
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state <= STATE_IDLE;
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end
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end
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STATE_END: begin
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if (start_i == `DivStart) begin
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ready_o <= `DivResultReady;
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result_o <= {div_remain, div_result};
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end else begin
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state <= STATE_IDLE;
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ready_o <= `DivResultNotReady;
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end
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end
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endcase
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end
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end
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endmodule
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