146 lines
4.9 KiB
Systemverilog
146 lines
4.9 KiB
Systemverilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.sv"
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// 取指模块
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module ifu #(
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parameter bit BranchPredictor = 1'b1
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)(
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input wire clk,
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input wire rst_n,
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input wire flush_i, // 冲刷标志
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input wire[31:0] flush_addr_i, // 冲刷地址
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input wire[`STALL_WIDTH-1:0] stall_i, // 流水线暂停标志
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input wire id_ready_i, // ID模块可以接收指令
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// to ifu_idu
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output wire[31:0] inst_o,
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output wire[31:0] pc_o,
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output wire inst_valid_o,
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// 指令总线信号
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output wire instr_req_o,
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input wire instr_gnt_i,
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input wire instr_rvalid_i,
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output wire[31:0] instr_addr_o,
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input wire[31:0] instr_rdata_i,
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input wire instr_err_i
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);
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localparam S_RESET = 3'b001;
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localparam S_FETCH = 3'b010;
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localparam S_VALID = 3'b100;
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reg[2:0] state_d, state_q;
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wire inst_valid;
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wire req_valid;
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wire[31:0] fetch_addr_n;
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reg[31:0] fetch_addr_q;
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wire prdt_taken;
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wire[31:0] prdt_addr;
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// 取指请求有效
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assign req_valid = instr_gnt_i & (~stall_i[`STALL_IF]);
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// 状态切换
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// 取指模块需要实现连续不断地取指，因此
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// 在S_FETCH和S_VALID这两个状态都要进行取指操作
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always @ (*) begin
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state_d = state_q;
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case (state_q)
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// 复位
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S_RESET: begin
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// 复位撤销后转到取指状态
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if (rst_n) begin
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state_d = S_FETCH;
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end
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end
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// 取指
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S_FETCH: begin
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// 取指有效
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if (req_valid) begin
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state_d = S_VALID;
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end
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end
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// 指令有效
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S_VALID: begin
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// 取指无效
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if (~req_valid) begin
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state_d = S_FETCH;
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end
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end
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default: ;
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endcase
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end
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// 指令有效
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assign inst_valid = (state_q == S_VALID) & instr_rvalid_i & id_ready_i;
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assign inst_valid_o = inst_valid;
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// 指令无效时有nop指令代替
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assign inst_o = inst_valid ? instr_rdata_i: `INST_NOP;
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assign pc_o = fetch_addr_q;
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// 更新取指地址
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assign fetch_addr_n = flush_i ? flush_addr_i:
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prdt_taken ? prdt_addr:
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//stall_i[`STALL_IF] ? fetch_addr_q:
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inst_valid ? fetch_addr_q + 4'h4:
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fetch_addr_q;
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// 取指请求
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assign instr_req_o = (~stall_i[`STALL_IF]) & (state_q != S_RESET);
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// 取指地址(4字节对齐)
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assign instr_addr_o = {fetch_addr_n[31:2], 2'b00};
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state_q <= S_RESET;
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fetch_addr_q <= `CPU_RESET_ADDR;
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end else begin
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state_q <= state_d;
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// 取指有效时保存当前取指地址
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if (req_valid | flush_i) begin
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fetch_addr_q <= fetch_addr_n;
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end
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end
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end
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// 分支预测
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if (BranchPredictor) begin: g_branch_predictor
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bpu u_bpu(
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.clk(clk),
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.rst_n(rst_n),
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.inst_i(instr_rdata_i),
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.inst_valid_i(inst_valid),
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.pc_i(fetch_addr_q),
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.prdt_taken_o(prdt_taken),
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.prdt_addr_o(prdt_addr)
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);
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end else begin: g_no_branch_predictor
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assign prdt_taken = 1'b0;
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assign prdt_addr = 32'h0;
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end
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endmodule
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