93 lines
3.0 KiB
Systemverilog
93 lines
3.0 KiB
Systemverilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.sv"
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module exu_commit(
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input wire clk,
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input wire rst_n,
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input wire req_muldiv_i,
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input wire muldiv_reg_we_i,
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input wire[4:0] muldiv_reg_waddr_i,
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input wire[31:0] muldiv_reg_wdata_i,
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input wire req_mem_i,
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input wire mem_reg_we_i,
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input wire[4:0] mem_reg_waddr_i,
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input wire[31:0] mem_reg_wdata_i,
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input wire req_csr_i,
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input wire csr_reg_we_i,
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input wire[4:0] csr_reg_waddr_i,
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input wire[31:0] csr_reg_wdata_i,
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input wire req_bjp_i,
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input wire bjp_reg_we_i,
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input wire[31:0] bjp_reg_wdata_i,
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input wire[4:0] bjp_reg_waddr_i,
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input wire rd_we_i,
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input wire[4:0] rd_waddr_i,
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input wire[31:0] alu_reg_wdata_i,
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output wire reg_we_o,
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output wire[4:0] reg_waddr_o,
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output wire[31:0] reg_wdata_o
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);
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wire use_alu_res = (~req_muldiv_i) &
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(~req_mem_i) &
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(~req_csr_i) &
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(~req_bjp_i);
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assign reg_we_o = muldiv_reg_we_i | mem_reg_we_i | csr_reg_we_i | use_alu_res | bjp_reg_we_i;
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reg[4:0] reg_waddr;
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always @ (*) begin
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reg_waddr = 5'h0;
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case (1'b1)
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muldiv_reg_we_i: reg_waddr = muldiv_reg_waddr_i;
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mem_reg_we_i: reg_waddr = mem_reg_waddr_i;
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csr_reg_we_i: reg_waddr = csr_reg_waddr_i;
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bjp_reg_we_i: reg_waddr = bjp_reg_waddr_i;
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rd_we_i: reg_waddr = rd_waddr_i;
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endcase
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end
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assign reg_waddr_o = reg_waddr;
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reg[31:0] reg_wdata;
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always @ (*) begin
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reg_wdata = 32'h0;
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case (1'b1)
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muldiv_reg_we_i: reg_wdata = muldiv_reg_wdata_i;
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mem_reg_we_i: reg_wdata = mem_reg_wdata_i;
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csr_reg_we_i: reg_wdata = csr_reg_wdata_i;
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bjp_reg_we_i: reg_wdata = bjp_reg_wdata_i;
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use_alu_res: reg_wdata = alu_reg_wdata_i;
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endcase
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end
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assign reg_wdata_o = reg_wdata;
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endmodule
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