89 lines
2.5 KiB
Systemverilog
89 lines
2.5 KiB
Systemverilog
/*
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Copyright 2021 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module debug_rom (
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input wire clk_i,
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input wire req_i,
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input wire [31:0] addr_i,
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output wire [31:0] rdata_o
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);
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localparam RomSize = 38;
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wire [RomSize-1:0][31:0] mem;
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assign mem = {
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32'h00000000,
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32'h7b200073,
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32'h7b202473,
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32'h7b302573,
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32'h10852423,
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32'hf1402473,
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32'ha85ff06f,
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32'h7b202473,
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32'h7b302573,
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32'h10052223,
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32'h00100073,
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32'h7b202473,
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32'h7b302573,
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32'h10052623,
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32'h00c51513,
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32'h00c55513,
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32'h00000517,
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32'hfd5ff06f,
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32'hfa041ce3,
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32'h00247413,
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32'h40044403,
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32'h00a40433,
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32'hf1402473,
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32'h02041c63,
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32'h00147413,
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32'h40044403,
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32'h00a40433,
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32'h10852023,
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32'hf1402473,
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32'h00c51513,
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32'h00c55513,
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32'h00000517,
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32'h7b351073,
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32'h7b241073,
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32'h0ff0000f,
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32'h04c0006f,
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32'h07c0006f,
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32'h00c0006f
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};
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reg [5:0] addr_q;
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always @ (posedge clk_i) begin
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if (req_i) begin
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addr_q <= addr_i[7:2];
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end
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end
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reg[31:0] rdata;
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always @ (*) begin
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rdata = 32'h0;
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if (addr_q < 6'd38) begin
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rdata = mem[addr_q];
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end
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end
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assign rdata_o = rdata;
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endmodule
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