341 lines
13 KiB
Verilog
341 lines
13 KiB
Verilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.v"
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// RIB总线模块
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module rib(
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input wire clk,
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input wire rst,
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// master 0 interface
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input wire[`MemAddrBus] m0_addr_i, // 主设备0读、写地址
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input wire[`MemBus] m0_data_i, // 主设备0写数据
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output reg[`MemBus] m0_data_o, // 主设备0读取到的数据
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input wire m0_req_i, // 主设备0访问请求标志
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input wire m0_we_i, // 主设备0写标志
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// master 1 interface
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input wire[`MemAddrBus] m1_addr_i, // 主设备1读、写地址
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input wire[`MemBus] m1_data_i, // 主设备1写数据
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output reg[`MemBus] m1_data_o, // 主设备1读取到的数据
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input wire m1_req_i, // 主设备1访问请求标志
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input wire m1_we_i, // 主设备1写标志
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// master 2 interface
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input wire[`MemAddrBus] m2_addr_i, // 主设备2读、写地址
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input wire[`MemBus] m2_data_i, // 主设备2写数据
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output reg[`MemBus] m2_data_o, // 主设备2读取到的数据
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input wire m2_req_i, // 主设备2访问请求标志
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input wire m2_we_i, // 主设备2写标志
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// master 3 interface
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input wire[`MemAddrBus] m3_addr_i, // 主设备3读、写地址
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input wire[`MemBus] m3_data_i, // 主设备3写数据
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output reg[`MemBus] m3_data_o, // 主设备3读取到的数据
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input wire m3_req_i, // 主设备3访问请求标志
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input wire m3_we_i, // 主设备3写标志
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// slave 0 interface
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output reg[`MemAddrBus] s0_addr_o, // 从设备0读、写地址
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output reg[`MemBus] s0_data_o, // 从设备0写数据
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input wire[`MemBus] s0_data_i, // 从设备0读取到的数据
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output reg s0_we_o, // 从设备0写标志
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// slave 1 interface
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output reg[`MemAddrBus] s1_addr_o, // 从设备1读、写地址
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output reg[`MemBus] s1_data_o, // 从设备1写数据
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input wire[`MemBus] s1_data_i, // 从设备1读取到的数据
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output reg s1_we_o, // 从设备1写标志
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// slave 2 interface
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output reg[`MemAddrBus] s2_addr_o, // 从设备2读、写地址
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output reg[`MemBus] s2_data_o, // 从设备2写数据
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input wire[`MemBus] s2_data_i, // 从设备2读取到的数据
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output reg s2_we_o, // 从设备2写标志
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// slave 3 interface
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output reg[`MemAddrBus] s3_addr_o, // 从设备3读、写地址
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output reg[`MemBus] s3_data_o, // 从设备3写数据
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input wire[`MemBus] s3_data_i, // 从设备3读取到的数据
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output reg s3_we_o, // 从设备3写标志
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// slave 4 interface
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output reg[`MemAddrBus] s4_addr_o, // 从设备4读、写地址
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output reg[`MemBus] s4_data_o, // 从设备4写数据
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input wire[`MemBus] s4_data_i, // 从设备4读取到的数据
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output reg s4_we_o, // 从设备4写标志
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// slave 5 interface
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output reg[`MemAddrBus] s5_addr_o, // 从设备5读、写地址
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output reg[`MemBus] s5_data_o, // 从设备5写数据
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input wire[`MemBus] s5_data_i, // 从设备5读取到的数据
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output reg s5_we_o, // 从设备5写标志
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output reg hold_flag_o // 暂停流水线标志
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);
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// 访问地址的最高4位决定要访问的是哪一个从设备
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// 因此最多支持16个从设备
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parameter [3:0]slave_0 = 4'b0000;
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parameter [3:0]slave_1 = 4'b0001;
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parameter [3:0]slave_2 = 4'b0010;
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parameter [3:0]slave_3 = 4'b0011;
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parameter [3:0]slave_4 = 4'b0100;
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parameter [3:0]slave_5 = 4'b0101;
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parameter [1:0]grant0 = 2'h0;
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parameter [1:0]grant1 = 2'h1;
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parameter [1:0]grant2 = 2'h2;
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parameter [1:0]grant3 = 2'h3;
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wire[3:0] req;
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reg[1:0] grant;
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// 主设备请求信号
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assign req = {m3_req_i, m2_req_i, m1_req_i, m0_req_i};
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// 仲裁逻辑
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// 固定优先级仲裁机制
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// 优先级由高到低：主设备3，主设备0，主设备2，主设备1
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always @ (*) begin
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if (req[3]) begin
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grant = grant3;
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hold_flag_o = `HoldEnable;
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end else if (req[0]) begin
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grant = grant0;
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hold_flag_o = `HoldEnable;
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end else if (req[2]) begin
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grant = grant2;
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hold_flag_o = `HoldEnable;
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end else begin
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grant = grant1;
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hold_flag_o = `HoldDisable;
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end
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end
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// 根据仲裁结果，选择(访问)对应的从设备
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always @ (*) begin
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m0_data_o = `ZeroWord;
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m1_data_o = `INST_NOP;
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m2_data_o = `ZeroWord;
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m3_data_o = `ZeroWord;
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s0_addr_o = `ZeroWord;
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s1_addr_o = `ZeroWord;
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s2_addr_o = `ZeroWord;
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s3_addr_o = `ZeroWord;
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s4_addr_o = `ZeroWord;
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s5_addr_o = `ZeroWord;
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s0_data_o = `ZeroWord;
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s1_data_o = `ZeroWord;
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s2_data_o = `ZeroWord;
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s3_data_o = `ZeroWord;
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s4_data_o = `ZeroWord;
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s5_data_o = `ZeroWord;
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s0_we_o = `WriteDisable;
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s1_we_o = `WriteDisable;
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s2_we_o = `WriteDisable;
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s3_we_o = `WriteDisable;
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s4_we_o = `WriteDisable;
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s5_we_o = `WriteDisable;
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case (grant)
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grant0: begin
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case (m0_addr_i[31:28])
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slave_0: begin
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s0_we_o = m0_we_i;
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s0_addr_o = {{4'h0}, {m0_addr_i[27:0]}};
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s0_data_o = m0_data_i;
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m0_data_o = s0_data_i;
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end
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slave_1: begin
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s1_we_o = m0_we_i;
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s1_addr_o = {{4'h0}, {m0_addr_i[27:0]}};
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s1_data_o = m0_data_i;
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m0_data_o = s1_data_i;
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end
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slave_2: begin
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s2_we_o = m0_we_i;
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s2_addr_o = {{4'h0}, {m0_addr_i[27:0]}};
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s2_data_o = m0_data_i;
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m0_data_o = s2_data_i;
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end
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slave_3: begin
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s3_we_o = m0_we_i;
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s3_addr_o = {{4'h0}, {m0_addr_i[27:0]}};
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s3_data_o = m0_data_i;
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m0_data_o = s3_data_i;
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end
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slave_4: begin
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s4_we_o = m0_we_i;
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s4_addr_o = {{4'h0}, {m0_addr_i[27:0]}};
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s4_data_o = m0_data_i;
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m0_data_o = s4_data_i;
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end
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slave_5: begin
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s5_we_o = m0_we_i;
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s5_addr_o = {{4'h0}, {m0_addr_i[27:0]}};
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s5_data_o = m0_data_i;
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m0_data_o = s5_data_i;
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end
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default: begin
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end
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endcase
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end
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grant1: begin
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case (m1_addr_i[31:28])
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slave_0: begin
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s0_we_o = m1_we_i;
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s0_addr_o = {{4'h0}, {m1_addr_i[27:0]}};
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s0_data_o = m1_data_i;
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m1_data_o = s0_data_i;
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end
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slave_1: begin
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s1_we_o = m1_we_i;
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s1_addr_o = {{4'h0}, {m1_addr_i[27:0]}};
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s1_data_o = m1_data_i;
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m1_data_o = s1_data_i;
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end
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slave_2: begin
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s2_we_o = m1_we_i;
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s2_addr_o = {{4'h0}, {m1_addr_i[27:0]}};
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s2_data_o = m1_data_i;
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m1_data_o = s2_data_i;
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end
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slave_3: begin
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s3_we_o = m1_we_i;
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s3_addr_o = {{4'h0}, {m1_addr_i[27:0]}};
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s3_data_o = m1_data_i;
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m1_data_o = s3_data_i;
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end
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slave_4: begin
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s4_we_o = m1_we_i;
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s4_addr_o = {{4'h0}, {m1_addr_i[27:0]}};
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s4_data_o = m1_data_i;
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m1_data_o = s4_data_i;
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end
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slave_5: begin
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s5_we_o = m1_we_i;
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s5_addr_o = {{4'h0}, {m1_addr_i[27:0]}};
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s5_data_o = m1_data_i;
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m1_data_o = s5_data_i;
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end
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default: begin
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end
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endcase
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end
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grant2: begin
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case (m2_addr_i[31:28])
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slave_0: begin
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s0_we_o = m2_we_i;
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s0_addr_o = {{4'h0}, {m2_addr_i[27:0]}};
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s0_data_o = m2_data_i;
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m2_data_o = s0_data_i;
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end
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slave_1: begin
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s1_we_o = m2_we_i;
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s1_addr_o = {{4'h0}, {m2_addr_i[27:0]}};
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s1_data_o = m2_data_i;
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m2_data_o = s1_data_i;
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end
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slave_2: begin
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s2_we_o = m2_we_i;
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s2_addr_o = {{4'h0}, {m2_addr_i[27:0]}};
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s2_data_o = m2_data_i;
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m2_data_o = s2_data_i;
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end
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slave_3: begin
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s3_we_o = m2_we_i;
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s3_addr_o = {{4'h0}, {m2_addr_i[27:0]}};
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s3_data_o = m2_data_i;
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m2_data_o = s3_data_i;
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end
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slave_4: begin
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s4_we_o = m2_we_i;
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s4_addr_o = {{4'h0}, {m2_addr_i[27:0]}};
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s4_data_o = m2_data_i;
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m2_data_o = s4_data_i;
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end
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slave_5: begin
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s5_we_o = m2_we_i;
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s5_addr_o = {{4'h0}, {m2_addr_i[27:0]}};
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s5_data_o = m2_data_i;
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m2_data_o = s5_data_i;
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end
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default: begin
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end
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endcase
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end
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grant3: begin
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case (m3_addr_i[31:28])
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slave_0: begin
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s0_we_o = m3_we_i;
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s0_addr_o = {{4'h0}, {m3_addr_i[27:0]}};
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s0_data_o = m3_data_i;
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m3_data_o = s0_data_i;
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end
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slave_1: begin
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s1_we_o = m3_we_i;
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s1_addr_o = {{4'h0}, {m3_addr_i[27:0]}};
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s1_data_o = m3_data_i;
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m3_data_o = s1_data_i;
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end
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slave_2: begin
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s2_we_o = m3_we_i;
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s2_addr_o = {{4'h0}, {m3_addr_i[27:0]}};
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s2_data_o = m3_data_i;
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m3_data_o = s2_data_i;
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end
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slave_3: begin
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s3_we_o = m3_we_i;
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s3_addr_o = {{4'h0}, {m3_addr_i[27:0]}};
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s3_data_o = m3_data_i;
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m3_data_o = s3_data_i;
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end
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slave_4: begin
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s4_we_o = m3_we_i;
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s4_addr_o = {{4'h0}, {m3_addr_i[27:0]}};
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s4_data_o = m3_data_i;
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m3_data_o = s4_data_i;
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end
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slave_5: begin
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s5_we_o = m3_we_i;
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s5_addr_o = {{4'h0}, {m3_addr_i[27:0]}};
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s5_data_o = m3_data_i;
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m3_data_o = s5_data_i;
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end
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default: begin
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end
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endcase
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end
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default: begin
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end
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endcase
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end
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endmodule
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