tinyriscv/rtl/core
liangkangnan 8b51737477 add interrupt support and example
Signed-off-by: liangkangnan <liangkangnan@163.com>
2020-03-08 15:09:30 +08:00
..
defines.v add interrupt support and example 2020-03-08 15:09:30 +08:00
div.v support JTAG 2020-03-01 14:55:36 +08:00
ex.v add interrupt support and example 2020-03-08 15:09:30 +08:00
id.v add interrupt support and example 2020-03-08 15:09:30 +08:00
if_id.v add interrupt support and example 2020-03-08 15:09:30 +08:00
pc_reg.v add interrupt support and example 2020-03-08 15:09:30 +08:00
regs.v support JTAG 2020-03-01 14:55:36 +08:00
sim_ram.v add interrupt support and example 2020-03-08 15:09:30 +08:00
tinyriscv_core.v add interrupt support and example 2020-03-08 15:09:30 +08:00