202 lines
5.1 KiB
Smarty
202 lines
5.1 KiB
Smarty
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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#ifndef _TOP_${top["name"].upper()}_H_
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#define _TOP_${top["name"].upper()}_H_
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/**
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* @file
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* @brief Top-specific Definitions
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*
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* This file contains preprocessor and type definitions for use within the
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* device C/C++ codebase.
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*
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* These definitions are for information that depends on the top-specific chip
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* configuration, which includes:
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* - Device Memory Information (for Peripherals and Memory)
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* - PLIC Interrupt ID Names and Source Mappings
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* - Alert ID Names and Source Mappings
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* - Pinmux Pin/Select Names
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* - Power Manager Wakeups
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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% for (inst_name, if_name), region in helper.devices():
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<%
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if_desc = inst_name if if_name is None else '{} device on {}'.format(if_name, inst_name)
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hex_base_addr = "0x{:X}u".format(region.base_addr)
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hex_size_bytes = "0x{:X}u".format(region.size_bytes)
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base_addr_name = region.base_addr_name().as_c_define()
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size_bytes_name = region.size_bytes_name().as_c_define()
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%>\
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/**
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* Peripheral base address for ${if_desc} in top ${top["name"]}.
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*
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* This should be used with #mmio_region_from_addr to access the memory-mapped
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* registers associated with the peripheral (usually via a DIF).
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*/
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#define ${base_addr_name} ${hex_base_addr}
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/**
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* Peripheral size for ${if_desc} in top ${top["name"]}.
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*
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* This is the size (in bytes) of the peripheral's reserved memory area. All
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* memory-mapped registers associated with this peripheral should have an
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* address between #${base_addr_name} and
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* `${base_addr_name} + ${size_bytes_name}`.
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*/
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#define ${size_bytes_name} ${hex_size_bytes}
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% endfor
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% for name, region in helper.memories():
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<%
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hex_base_addr = "0x{:X}u".format(region.base_addr)
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hex_size_bytes = "0x{:X}u".format(region.size_bytes)
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base_addr_name = region.base_addr_name().as_c_define()
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size_bytes_name = region.size_bytes_name().as_c_define()
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%>\
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/**
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* Memory base address for ${name} in top ${top["name"]}.
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*/
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#define ${base_addr_name} ${hex_base_addr}
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/**
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* Memory size for ${name} in top ${top["name"]}.
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*/
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#define ${size_bytes_name} ${hex_size_bytes}
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% endfor
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/**
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* PLIC Interrupt Source Peripheral.
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*
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* Enumeration used to determine which peripheral asserted the corresponding
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* interrupt.
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*/
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${helper.plic_sources.render()}
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/**
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* PLIC Interrupt Source.
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*
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* Enumeration of all PLIC interrupt sources. The interrupt sources belonging to
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* the same peripheral are guaranteed to be consecutive.
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*/
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${helper.plic_interrupts.render()}
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/**
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* PLIC Interrupt Source to Peripheral Map
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*
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* This array is a mapping from `${helper.plic_interrupts.name.as_c_type()}` to
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* `${helper.plic_sources.name.as_c_type()}`.
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*/
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${helper.plic_mapping.render_declaration()}
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/**
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* PLIC Interrupt Target.
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*
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* Enumeration used to determine which set of IE, CC, threshold registers to
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* access for a given interrupt target.
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*/
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${helper.plic_targets.render()}
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/**
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* Alert Handler Source Peripheral.
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*
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* Enumeration used to determine which peripheral asserted the corresponding
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* alert.
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*/
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${helper.alert_sources.render()}
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/**
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* Alert Handler Alert Source.
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*
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* Enumeration of all Alert Handler Alert Sources. The alert sources belonging to
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* the same peripheral are guaranteed to be consecutive.
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*/
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${helper.alert_alerts.render()}
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/**
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* Alert Handler Alert Source to Peripheral Map
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*
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* This array is a mapping from `${helper.alert_alerts.name.as_c_type()}` to
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* `${helper.alert_sources.name.as_c_type()}`.
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*/
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${helper.alert_mapping.render_declaration()}
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#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
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// PERIPH_INSEL ranges from 0 to NUM_MIO_PADS + 2 -1}
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// 0 and 1 are tied to value 0 and 1
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#define NUM_MIO_PADS ${top["pinmux"]["io_counts"]["muxed"]["pads"]}
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#define NUM_DIO_PADS ${top["pinmux"]["io_counts"]["dedicated"]["inouts"] + \
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top["pinmux"]["io_counts"]["dedicated"]["inputs"] + \
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top["pinmux"]["io_counts"]["dedicated"]["outputs"] }
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#define PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3
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/**
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* Pinmux Peripheral Input.
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*/
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${helper.pinmux_peripheral_in.render()}
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/**
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* Pinmux MIO Input Selector.
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*/
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${helper.pinmux_insel.render()}
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/**
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* Pinmux MIO Output.
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*/
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${helper.pinmux_mio_out.render()}
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/**
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* Pinmux Peripheral Output Selector.
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*/
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${helper.pinmux_outsel.render()}
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/**
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* Power Manager Wakeup Signals
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*/
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${helper.pwrmgr_wakeups.render()}
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/**
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* Reset Manager Software Controlled Resets
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*/
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${helper.rstmgr_sw_rsts.render()}
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/**
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* Power Manager Reset Request Signals
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*/
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${helper.pwrmgr_reset_requests.render()}
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/**
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* Clock Manager Software-Controlled ("Gated") Clocks.
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*
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* The Software has full control over these clocks.
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*/
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${helper.clkmgr_gateable_clocks.render()}
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/**
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* Clock Manager Software-Hinted Clocks.
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*
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* The Software has partial control over these clocks. It can ask them to stop,
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* but the clock manager is in control of whether the clock actually is stopped.
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*/
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${helper.clkmgr_hintable_clocks.render()}
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// Header Extern Guard
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#ifdef __cplusplus
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} // extern "C"
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#endif
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#endif // _TOP_${top["name"].upper()}_H_
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