178 lines
7.1 KiB
Verilog
178 lines
7.1 KiB
Verilog
/*
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Copyright 2019 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.v"
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module div(
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input wire clk,
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input wire rst,
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input wire[`RegBus] dividend_i,
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input wire[`RegBus] divisor_i,
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input wire start_i,
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input wire[2:0] op_i,
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input wire[`RegAddrBus] reg_waddr_i,
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output reg[`DoubleRegBus] result_o,
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output reg ready_o,
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output wire busy_o,
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output reg[2:0] op_o,
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output reg[`RegAddrBus] reg_waddr_o
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);
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localparam STATE_IDLE = 0;
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localparam STATE_START = 1;
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localparam STATE_INVERT = 2;
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localparam STATE_END = 3;
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reg[`RegBus] dividend_temp;
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reg[`RegBus] divisor_temp;
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reg[1:0] state;
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reg[6:0] count;
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reg[`RegBus] div_result;
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reg[`RegBus] div_remain;
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reg[`RegBus] minuend;
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reg[`RegBus] divisor_zero_result;
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reg invert_result;
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assign busy_o = (state != STATE_IDLE)? `True : `False;
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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state <= STATE_IDLE;
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ready_o <= `DivResultNotReady;
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result_o <= {`ZeroWord, `ZeroWord};
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div_result <= `ZeroWord;
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div_remain <= `ZeroWord;
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divisor_zero_result <= ~32'b00000001 + 1'b1;
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op_o <= 3'h0;
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reg_waddr_o <= `ZeroWord;
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dividend_temp <= `ZeroWord;
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divisor_temp <= `ZeroWord;
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invert_result <= 1'b0;
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end else begin
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case (state)
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STATE_IDLE: begin
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if (start_i == `DivStart) begin
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op_o <= op_i;
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reg_waddr_o <= reg_waddr_i;
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if (divisor_i == `ZeroWord) begin
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ready_o <= `DivResultReady;
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result_o <= {dividend_i, divisor_zero_result};
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end else begin
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count <= 7'd31;
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state <= STATE_START;
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div_result <= `ZeroWord;
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div_remain <= `ZeroWord;
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if ((op_i == `INST_DIV) || (op_i == `INST_REM)) begin
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if (dividend_i[31] == 1'b1) begin
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dividend_temp <= ~dividend_i + 1;
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minuend <= ((~dividend_i + 1) >> 7'd31) & 1'b1;
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end else begin
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dividend_temp <= dividend_i;
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minuend <= (dividend_i >> 7'd31) & 1'b1;
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end
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if (divisor_i[31] == 1'b1) begin
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divisor_temp <= ~divisor_i + 1;
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end else begin
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divisor_temp <= divisor_i;
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end
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end else begin
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dividend_temp <= dividend_i;
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minuend <= (dividend_i >> 7'd31) & 1'b1;
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divisor_temp <= divisor_i;
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end
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if (((op_i == `INST_DIV) && (dividend_i[31] ^ divisor_i[31] == 1'b1))
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|| ((op_i == `INST_REM) && (dividend_i[31] == 1'b1))) begin
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invert_result <= 1'b1;
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end else begin
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invert_result <= 1'b0;
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end
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end
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end else begin
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ready_o <= `DivResultNotReady;
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result_o <= {`ZeroWord, `ZeroWord};
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end
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end
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STATE_START: begin
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if (start_i == `DivStart) begin
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if (count >= 7'd1) begin
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if (minuend >= divisor_temp) begin
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div_result <= (div_result << 1'b1) | 1'b1;
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minuend <= ((minuend - divisor_temp) << 1'b1) | ((dividend_temp >> (count - 1'b1)) & 1'b1);
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end else begin
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div_result <= (div_result << 1'b1) | 1'b0;
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minuend <= (minuend << 1'b1) | ((dividend_temp >> (count - 1'b1)) & 1'b1);
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end
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count <= count - 1'b1;
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end else begin
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state <= STATE_INVERT;
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if (minuend >= divisor_temp) begin
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div_result <= (div_result << 1'b1) | 1'b1;
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div_remain <= minuend - divisor_temp;
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end else begin
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div_result <= (div_result << 1'b1) | 1'b0;
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div_remain <= minuend;
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end
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end
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end else begin
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ready_o <= `DivResultReady;
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result_o <= {`ZeroWord, `ZeroWord};
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state <= STATE_IDLE;
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end
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end
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STATE_INVERT: begin
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if (start_i == `DivStart) begin
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if (invert_result == 1'b1) begin
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div_result <= ~div_result + 1'b1;
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div_remain <= ~div_remain + 1'b1;
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end
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state <= STATE_END;
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end else begin
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ready_o <= `DivResultReady;
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result_o <= {`ZeroWord, `ZeroWord};
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state <= STATE_IDLE;
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end
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end
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STATE_END: begin
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if (start_i == `DivStart) begin
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ready_o <= `DivResultReady;
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result_o <= {div_remain, div_result};
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state <= STATE_IDLE;
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end else begin
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state <= STATE_IDLE;
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result_o <= {`ZeroWord, `ZeroWord};
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ready_o <= `DivResultNotReady;
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end
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end
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endcase
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end
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end
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endmodule
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