tinyriscv/sim/tinyriscv_core_tb.vcd

74097 lines
1.0 MiB

$date
Sun Feb 23 17:00:47 2020
$end
$version
Icarus Verilog
$end
$timescale
1ps
$end
$scope module tinyriscv_core_tb $end
$var wire 32 ! x26 [31:0] $end
$var wire 32 " x27 [31:0] $end
$var wire 32 # x3 [31:0] $end
$var reg 1 $ clk $end
$var reg 1 % rst $end
$var integer 32 & r [31:0] $end
$scope module u_tinyriscv_core $end
$var wire 1 $ clk $end
$var wire 1 % rst $end
$var wire 32 ' regs_rdata2_o [31:0] $end
$var wire 32 ( regs_rdata1_o [31:0] $end
$var wire 32 ) ram_pc_rdata_o [31:0] $end
$var wire 32 * ram_ex_rdata_o [31:0] $end
$var wire 1 + pc_re_o $end
$var wire 32 , pc_pc_o [31:0] $end
$var wire 32 - if_inst_o [31:0] $end
$var wire 32 . if_inst_addr_o [31:0] $end
$var wire 1 / id_sram_we_o $end
$var wire 1 0 id_sram_re_o $end
$var wire 1 1 id_reg_we_o $end
$var wire 5 2 id_reg_waddr_o [4:0] $end
$var wire 1 3 id_reg2_re_o $end
$var wire 5 4 id_reg2_raddr_o [4:0] $end
$var wire 1 5 id_reg1_re_o $end
$var wire 5 6 id_reg1_raddr_o [4:0] $end
$var wire 1 7 id_inst_valid_o $end
$var wire 32 8 id_inst_o [31:0] $end
$var wire 32 9 id_inst_addr_o [31:0] $end
$var wire 32 : ex_sram_wdata_o [31:0] $end
$var wire 32 ; ex_sram_waddr_o [31:0] $end
$var wire 32 < ex_sram_raddr_o [31:0] $end
$var wire 1 = ex_reg_we_o $end
$var wire 32 > ex_reg_wdata_o [31:0] $end
$var wire 5 ? ex_reg_waddr_o [4:0] $end
$var wire 1 @ ex_jump_flag_o $end
$var wire 32 A ex_jump_addr_o [31:0] $end
$var wire 1 B ex_hold_flag_o $end
$var wire 32 C ex_hold_addr_o [31:0] $end
$var wire 1 D ex_div_start_o $end
$var wire 32 E ex_div_divisor_o [31:0] $end
$var wire 32 F ex_div_dividend_o [31:0] $end
$var wire 64 G div_result_o [63:0] $end
$var wire 1 H div_ready_o $end
$scope module u_div $end
$var wire 1 $ clk $end
$var wire 1 % rst $end
$var wire 1 D start_i $end
$var wire 32 I divisor_i [31:0] $end
$var wire 32 J dividend_i [31:0] $end
$var reg 7 K count [6:0] $end
$var reg 32 L div_remain [31:0] $end
$var reg 32 M div_result [31:0] $end
$var reg 32 N dividend_temp [31:0] $end
$var reg 32 O divisor_temp [31:0] $end
$var reg 32 P divisor_zero_result [31:0] $end
$var reg 32 Q minuend [31:0] $end
$var reg 1 H ready_o $end
$var reg 64 R result_o [63:0] $end
$var reg 2 S state [1:0] $end
$upscope $end
$scope module u_ex $end
$var wire 1 $ clk $end
$var wire 1 H div_ready_i $end
$var wire 64 T div_result_i [63:0] $end
$var wire 1 % rst $end
$var wire 2 U sram_waddr_index [1:0] $end
$var wire 32 V sram_rdata_i [31:0] $end
$var wire 2 W sram_raddr_index [1:0] $end
$var wire 32 X sign_extend_tmp [31:0] $end
$var wire 5 Y shift_bits [4:0] $end
$var wire 1 1 reg_we_i $end
$var wire 5 Z reg_waddr_i [4:0] $end
$var wire 32 [ reg2_rdata_i [31:0] $end
$var wire 32 \ reg1_rdata_i [31:0] $end
$var wire 5 ] rd [4:0] $end
$var wire 7 ^ opcode [6:0] $end
$var wire 32 _ op2_mul [31:0] $end
$var wire 32 ` op1_mul [31:0] $end
$var wire 64 a mulhsu_temp_invert [63:0] $end
$var wire 64 b mulhsu_temp [63:0] $end
$var wire 64 c mulh_temp_invert [63:0] $end
$var wire 64 d mulh_temp [63:0] $end
$var wire 64 e mul_temp [63:0] $end
$var wire 1 7 inst_valid_i $end
$var wire 32 f inst_i [31:0] $end
$var wire 32 g inst_addr_i [31:0] $end
$var wire 7 h funct7 [6:0] $end
$var wire 3 i funct3 [2:0] $end
$var reg 32 j div_dividend_o [31:0] $end
$var reg 32 k div_divisor_o [31:0] $end
$var reg 3 l div_funct3 [2:0] $end
$var reg 5 m div_rd_reg [4:0] $end
$var reg 1 n div_reg_we $end
$var reg 1 D div_start_o $end
$var reg 1 o div_starting $end
$var reg 32 p hold_addr_o [31:0] $end
$var reg 1 B hold_flag_o $end
$var reg 1 q is_jumping $end
$var reg 32 r jump_addr_o [31:0] $end
$var reg 1 @ jump_flag_o $end
$var reg 5 s reg_waddr_o [4:0] $end
$var reg 32 t reg_wdata_o [31:0] $end
$var reg 1 = reg_we_o $end
$var reg 32 u sram_raddr_o [31:0] $end
$var reg 32 v sram_waddr_o [31:0] $end
$var reg 32 w sram_wdata_o [31:0] $end
$upscope $end
$scope module u_id $end
$var wire 1 $ clk $end
$var wire 1 B hold_flag_ex_i $end
$var wire 1 @ jump_flag_ex_i $end
$var wire 1 % rst $end
$var wire 5 x rs2 [4:0] $end
$var wire 5 y rs1 [4:0] $end
$var wire 5 z rd [4:0] $end
$var wire 7 { opcode [6:0] $end
$var wire 32 | inst_i [31:0] $end
$var wire 32 } inst_addr_i [31:0] $end
$var wire 7 ~ funct7 [6:0] $end
$var wire 3 !" funct3 [2:0] $end
$var reg 32 "" inst_addr_o [31:0] $end
$var reg 32 #" inst_o [31:0] $end
$var reg 1 7 inst_valid_o $end
$var reg 5 $" reg1_raddr_o [4:0] $end
$var reg 1 5 reg1_re_o $end
$var reg 5 %" reg2_raddr_o [4:0] $end
$var reg 1 3 reg2_re_o $end
$var reg 5 &" reg_waddr_o [4:0] $end
$var reg 1 1 reg_we_o $end
$var reg 1 0 sram_re_o $end
$var reg 1 / sram_we_o $end
$upscope $end
$scope module u_if_id $end
$var wire 1 $ clk $end
$var wire 1 B hold_flag_ex_i $end
$var wire 1 @ jump_flag_ex_i $end
$var wire 1 % rst $end
$var wire 32 '" inst_i [31:0] $end
$var wire 32 (" inst_addr_i [31:0] $end
$var reg 32 )" inst_addr_o [31:0] $end
$var reg 32 *" inst_o [31:0] $end
$upscope $end
$scope module u_pc_reg $end
$var wire 1 $ clk $end
$var wire 32 +" hold_addr_ex_i [31:0] $end
$var wire 1 B hold_flag_ex_i $end
$var wire 32 ," jump_addr_ex_i [31:0] $end
$var wire 1 @ jump_flag_ex_i $end
$var wire 1 % rst $end
$var reg 32 -" offset [31:0] $end
$var reg 32 ." pc_o [31:0] $end
$var reg 1 + re_o $end
$upscope $end
$scope module u_regs $end
$var wire 1 $ clk $end
$var wire 5 /" raddr1 [4:0] $end
$var wire 5 0" raddr2 [4:0] $end
$var wire 1 5 re1 $end
$var wire 1 3 re2 $end
$var wire 1 % rst $end
$var wire 5 1" waddr [4:0] $end
$var wire 32 2" wdata [31:0] $end
$var wire 1 = we $end
$var reg 32 3" rdata1 [31:0] $end
$var reg 32 4" rdata2 [31:0] $end
$upscope $end
$scope module u_sim_ram $end
$var wire 1 $ clk $end
$var wire 32 5" ex_raddr_i [31:0] $end
$var wire 1 0 ex_re_i $end
$var wire 32 6" pc_raddr_i [31:0] $end
$var wire 1 + pc_re_i $end
$var wire 1 % rst $end
$var wire 32 7" waddr_i [31:0] $end
$var wire 32 8" wdata_i [31:0] $end
$var wire 1 / we_i $end
$var reg 32 9" ex_rdata_o [31:0] $end
$var reg 32 :" pc_rdata_o [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b0 :"
b0 9"
bx 8"
bx 7"
bx 6"
b0 5"
b0 4"
b0 3"
bx 2"
bx 1"
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bx ("
b0 '"
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bx #"
bx ""
bx !"
bx ~
bx }
bx |
bx {
bx z
bx y
bx x
bx w
bx v
b0 u
bx t
bx s
bx r
0q
bx p
0o
0n
bx m
bx l
b0 k
b0 j
bx i
bx h
bx g
bx f
b0 e
b0 d
b0 c
b0 b
b0 a
b0 `
b0 _
bx ^
bx ]
b0 \
b0 [
bx Z
bx Y
bx X
bx W
b0 V
bx U
bx T
bx S
bx R
bx Q
bx P
bx O
bx N
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bx L
bx K
b0 J
b0 I
xH
bx G
b0 F
b0 E
0D
bx C
0B
bx A
0@
bx ?
bx >
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b0 <
bx ;
bx :
bx 9
bx 8
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bx 6
x5
bx 4
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bx .
bx -
bx ,
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b0 *
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b0 (
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bx &
0%
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bx #
bx "
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$end
#10000
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b0 x
b0 y
b0 z
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01
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b11111111111111111111111111111111 P
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1$
#20000
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#40000
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#50000
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b10000000000000000000100010011 '"
b10000000000000000000100010011 :"
b100 -"
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#60000
0$
#70000
b110100010011 )
b110100010011 '"
b110100010011 :"
b10 z
b1000 ~
b10011 {
b10000000000000000000100010011 -
b10000000000000000000100010011 |
b10000000000000000000100010011 *"
b1000 -"
b100 ,
b100 ("
b100 ."
b100 6"
1$
#80000
0$
#90000
b100000000 >
b100000000 t
b100000000 2"
b110110010011 )
b110110010011 '"
b110110010011 :"
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b10 ?
b10 s
b10 1"
b10 U
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b0 6
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#100000
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#110000
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b100110000000000000011101111 )
b100110000000000000011101111 '"
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b100 9
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b10000 -"
b1100 ,
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b11 U
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#220000
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b1111111111111111111111111111111111111111111111111111001000000000 c
b1111111111111111111111111111111111111111111111111111001000000000 a
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