72 lines
2.4 KiB
Verilog
72 lines
2.4 KiB
Verilog
/*
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Copyright 2019 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.v"
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// 控制模块
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// 发出跳转、暂停流水线信号
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module ctrl(
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input wire rst,
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// from ex
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input wire jump_flag_i,
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input wire[`InstAddrBus] jump_addr_i,
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input wire hold_flag_ex_i,
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// from rib
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input wire hold_flag_rib_i,
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// from jtag
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input wire jtag_halt_flag_i,
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output reg[`Hold_Flag_Bus] hold_flag_o,
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// to pc_reg
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output reg jump_flag_o,
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output reg[`InstAddrBus] jump_addr_o
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);
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always @ (*) begin
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if (rst == `RstEnable) begin
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hold_flag_o <= `Hold_None;
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jump_flag_o <= `JumpDisable;
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jump_addr_o <= `ZeroWord;
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end else begin
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jump_addr_o <= jump_addr_i;
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jump_flag_o <= jump_flag_i;
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// 默认不暂停
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hold_flag_o <= `Hold_None;
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// 按优先级处理不同模块的请求
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if (jump_flag_i == `JumpEnable || hold_flag_ex_i == `HoldEnable) begin
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// 暂停整条流水线
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hold_flag_o <= `Hold_Id;
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end else if (hold_flag_rib_i == `HoldEnable) begin
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// 暂停PC，即取指地址不变
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hold_flag_o <= `Hold_Pc;
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end else if (jtag_halt_flag_i == `HoldEnable) begin
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// 暂停整条流水线
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hold_flag_o <= `Hold_Id;
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end else begin
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hold_flag_o <= `Hold_None;
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end
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end
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end
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endmodule
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