149 lines
4.1 KiB
Verilog
149 lines
4.1 KiB
Verilog
/*
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Copyright 2019 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.v"
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// CPU core module
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module openriscv_core (
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input wire clk,
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input wire rst
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);
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// pc_reg
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wire[`SramAddrBus] pc_pc_o;
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wire pc_re_o;
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// if_id
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wire[`SramBus] if_inst_o;
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wire[`SramAddrBus] if_inst_addr_o;
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// id
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wire id_reg1_re_o;
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wire[`RegAddrBus] id_reg1_raddr_o;
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wire id_reg2_re_o;
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wire[`RegAddrBus] id_reg2_raddr_o;
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wire[`SramBus] id_inst_o;
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wire id_inst_valid_o;
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wire id_reg_we_o;
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wire[`RegAddrBus] id_reg_waddr_o;
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wire id_sram_re_o;
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wire id_sram_we_o;
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wire[`SramAddrBus] id_pc_o;
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wire[`SramAddrBus] id_inst_addr_o;
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// ex
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wire[`RegBus] ex_reg_wdata_o;
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wire[`SramBus] ex_sram_wdata_o;
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wire[`SramAddrBus] ex_sram_raddr_o;
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wire[`SramAddrBus] ex_sram_waddr_o;
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wire ex_jump_flag_o;
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wire[`RegBus] ex_jump_addr_o;
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// regs
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wire[`RegBus] regs_rdata1_o;
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wire[`RegBus] regs_rdata2_o;
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// sim_ram
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wire[`SramBus] ram_pc_rdata_o;
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wire[`SramBus] ram_ex_rdata_o;
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sim_ram u_sim_ram(
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.clk(clk),
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.rst(rst),
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.we_i(id_sram_we_o),
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.waddr_i(ex_sram_waddr_o),
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.wdata_i(ex_sram_wdata_o),
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.pc_re_i(pc_re_o),
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.pc_raddr_i(pc_pc_o),
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.pc_rdata_o(ram_pc_rdata_o),
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.ex_re_i(id_sram_re_o),
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.ex_raddr_i(ex_sram_raddr_o),
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.ex_rdata_o(ram_ex_rdata_o)
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);
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pc_reg u_pc_reg(
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.clk(clk),
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.rst(rst),
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.pc_o(pc_pc_o),
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.re_o(pc_re_o),
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.jump_flag_ex_i(ex_jump_flag_o),
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.jump_addr_ex_i(ex_jump_addr_o)
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);
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regs u_regs(
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.clk(clk),
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.rst(rst),
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.we(id_reg_we_o),
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.waddr(id_reg_waddr_o),
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.wdata(ex_reg_wdata_o),
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.re1(id_reg1_re_o),
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.raddr1(id_reg1_raddr_o),
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.rdata1(regs_rdata1_o),
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.re2(id_reg2_re_o),
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.raddr2(id_reg2_raddr_o),
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.rdata2(regs_rdata2_o)
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);
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if_id u_if_id(
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.clk(clk),
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.rst(rst),
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.inst_i(ram_pc_rdata_o),
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.inst_addr_i(pc_pc_o),
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.inst_o(if_inst_o),
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.inst_addr_o(if_inst_addr_o),
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.jump_flag_ex_i(ex_jump_flag_o)
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);
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id u_id(
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.clk(clk),
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.rst(rst),
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.inst_i(if_inst_o),
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.inst_addr_o(id_inst_addr_o),
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.inst_addr_i(if_inst_addr_o),
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.jump_flag_ex_i(ex_jump_flag_o),
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.reg1_re_o(id_reg1_re_o),
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.reg1_raddr_o(id_reg1_raddr_o),
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.reg2_re_o(id_reg2_re_o),
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.reg2_raddr_o(id_reg2_raddr_o),
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.inst_o(id_inst_o),
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.inst_valid_o(id_inst_valid_o),
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.reg_we_o(id_reg_we_o),
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.reg_waddr_o(id_reg_waddr_o),
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.sram_re_o(id_sram_re_o),
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.sram_we_o(id_sram_we_o)
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);
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ex u_ex(
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.clk(clk),
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.rst(rst),
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.inst_i(id_inst_o),
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.inst_addr_i(id_inst_addr_o),
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.inst_valid_i(id_inst_valid_o),
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.reg1_rdata_i(regs_rdata1_o),
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.reg2_rdata_i(regs_rdata2_o),
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.reg_wdata_o(ex_reg_wdata_o),
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.sram_rdata_i(ram_ex_rdata_o),
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.sram_wdata_o(ex_sram_wdata_o),
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.sram_raddr_o(ex_sram_raddr_o),
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.sram_waddr_o(ex_sram_waddr_o),
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.jump_flag_o(ex_jump_flag_o),
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.jump_addr_o(ex_jump_addr_o)
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);
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endmodule
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