99 lines
2.8 KiB
Verilog
99 lines
2.8 KiB
Verilog
/*
|
|
Copyright 2019 Blue Liang, liangkangnan@163.com
|
|
|
|
Licensed under the Apache License, Version 2.0 (the "License");
|
|
you may not use this file except in compliance with the License.
|
|
You may obtain a copy of the License at
|
|
|
|
http://www.apache.org/licenses/LICENSE-2.0
|
|
|
|
Unless required by applicable law or agreed to in writing, software
|
|
distributed under the License is distributed on an "AS IS" BASIS,
|
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
See the License for the specific language governing permissions and
|
|
limitations under the License.
|
|
*/
|
|
|
|
`define RstEnable 1'b0
|
|
`define RstDisable 1'b1
|
|
`define ZeroWord 32'h00000000
|
|
`define WriteEnable 1'b1
|
|
`define WriteDisable 1'b0
|
|
`define ReadEnable 1'b1
|
|
`define ReadDisable 1'b0
|
|
`define InstValid 1'b1
|
|
`define InstInvalid 1'b0
|
|
`define True 1'b1
|
|
`define False 1'b0
|
|
`define ChipEnable 1'b1
|
|
`define ChipDisable 1'b0
|
|
`define JumpEnable 1'b1
|
|
`define JumpDisable 1'b0
|
|
|
|
// I type inst
|
|
`define INST_TYPE_I 7'b0010011
|
|
`define INST_ADDI 3'b000
|
|
`define INST_SLTI 3'b010
|
|
`define INST_SLTIU 3'b011
|
|
`define INST_XORI 3'b100
|
|
`define INST_ORI 3'b110
|
|
`define INST_ANDI 3'b111
|
|
`define INST_SLLI 3'b001
|
|
`define INST_SRI 3'b101
|
|
|
|
// L type inst
|
|
`define INST_TYPE_L 7'b0000011
|
|
`define INST_LB 3'b000
|
|
`define INST_LH 3'b001
|
|
`define INST_LW 3'b010
|
|
`define INST_LBU 3'b100
|
|
`define INST_LHU 3'b101
|
|
|
|
// S type inst
|
|
`define INST_TYPE_S 7'b0100011
|
|
`define INST_SB 3'b000
|
|
`define INST_SH 3'b001
|
|
`define INST_SW 3'b010
|
|
|
|
// R type inst
|
|
`define INST_TYPE_R 7'b0110011
|
|
`define INST_ADD_SUB 3'b000
|
|
`define INST_SLL 3'b001
|
|
`define INST_SLT 3'b010
|
|
`define INST_SLTU 3'b011
|
|
`define INST_XOR 3'b100
|
|
`define INST_SR 3'b101
|
|
`define INST_OR 3'b110
|
|
`define INST_AND 3'b111
|
|
|
|
// J type inst
|
|
`define INST_JAL 7'b1101111
|
|
`define INST_JALR 7'b1100111
|
|
|
|
`define INST_LUI 7'b0110111
|
|
`define INST_AUIPC 7'b0010111
|
|
`define INST_NOP 32'h00000001
|
|
|
|
`define INST_FENCE 7'b0001111
|
|
|
|
// J type inst
|
|
`define INST_TYPE_B 7'b1100011
|
|
`define INST_BEQ 3'b000
|
|
`define INST_BNE 3'b001
|
|
`define INST_BLT 3'b100
|
|
`define INST_BGE 3'b101
|
|
`define INST_BLTU 3'b110
|
|
`define INST_BGEU 3'b111
|
|
|
|
// SIM RAM
|
|
`define SramMemNum 2048 // memory depth(how many words)
|
|
`define SramBus 31:0
|
|
`define SramAddrBus 31:0
|
|
|
|
// common regs
|
|
`define RegAddrBus 4:0
|
|
`define RegBus 31:0
|
|
`define RegWidth 32
|
|
`define RegNum 32 // reg count
|
|
`define RegNumLog2 5
|