tinyriscv

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Blue Liang 60a4f7d6df rtl: add generate block name Signed-off-by: liangkangnan <liangkangnan@163.com>		2020-10-26 17:01:04 +08:00
doc	first release	2020-10-23 21:26:18 +08:00
fpga	first release	2020-10-23 21:26:18 +08:00
pic	pic: update arch.jpg	2020-06-27 10:11:46 +08:00
rtl	rtl: add generate block name	2020-10-26 17:01:04 +08:00
sim	python scripts: remove verison	2020-10-25 12:02:26 +08:00
tb	first release	2020-10-23 21:26:18 +08:00
tests	first release	2020-10-23 21:26:18 +08:00
tools	first release	2020-10-23 21:26:18 +08:00
.gitignore	first release	2020-10-23 21:26:18 +08:00
LICENSE	first release	2019-12-04 08:47:19 +08:00
README.md	first release	2020-10-23 21:26:18 +08:00

本分支(bram)是在master分支的基础上，将指令和数据存储器由LUTRAM(DRAM)改为BRAM，以便可以运行更大的(C语言)程序。