227 lines
7.5 KiB
Verilog
227 lines
7.5 KiB
Verilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.v"
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// CSR寄存器模块
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module csr_reg(
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input wire clk,
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input wire rst,
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// form ex
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input wire we_i, // ex模块写寄存器标志
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input wire[`MemAddrBus] raddr_i, // ex模块读寄存器地址
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input wire[`MemAddrBus] waddr_i, // ex模块写寄存器地址
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input wire[`RegBus] data_i, // ex模块写寄存器数据
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// from clint
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input wire clint_we_i, // clint模块写寄存器标志
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input wire[`MemAddrBus] clint_raddr_i, // clint模块读寄存器地址
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input wire[`MemAddrBus] clint_waddr_i, // clint模块写寄存器地址
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input wire[`RegBus] clint_data_i, // clint模块写寄存器数据
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output wire global_int_en_o, // 全局中断使能标志
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// to clint
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output reg[`RegBus] clint_data_o, // clint模块读寄存器数据
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output wire[`RegBus] clint_csr_mtvec, // mtvec
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output wire[`RegBus] clint_csr_mepc, // mepc
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output wire[`RegBus] clint_csr_mstatus, // mstatus
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// to ex
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output reg[`RegBus] data_o // ex模块读寄存器数据
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);
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reg[`DoubleRegBus] cycle;
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reg[`RegBus] mtvec;
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reg[`RegBus] mcause;
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reg[`RegBus] mepc;
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reg[`RegBus] mie;
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reg[`RegBus] mstatus;
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reg[`RegBus] mscratch;
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assign global_int_en_o = (mstatus[3] == 1'b1)? `True: `False;
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assign clint_csr_mtvec = mtvec;
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assign clint_csr_mepc = mepc;
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assign clint_csr_mstatus = mstatus;
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// cycle counter
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// 复位撤销后就一直计数
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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cycle <= {`ZeroWord, `ZeroWord};
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end else begin
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cycle <= cycle + 1'b1;
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end
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end
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// write reg
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// 写寄存器操作
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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mtvec <= `ZeroWord;
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mcause <= `ZeroWord;
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mepc <= `ZeroWord;
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mie <= `ZeroWord;
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mstatus <= `ZeroWord;
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mscratch <= `ZeroWord;
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end else begin
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// 优先响应ex模块的写操作
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if (we_i == `WriteEnable) begin
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case (waddr_i[11:0])
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`CSR_MTVEC: begin
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mtvec <= data_i;
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end
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`CSR_MCAUSE: begin
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mcause <= data_i;
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end
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`CSR_MEPC: begin
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mepc <= data_i;
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end
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`CSR_MIE: begin
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mie <= data_i;
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end
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`CSR_MSTATUS: begin
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mstatus <= data_i;
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end
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`CSR_MSCRATCH: begin
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mscratch <= data_i;
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end
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default: begin
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end
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endcase
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// clint模块写操作
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end else if (clint_we_i == `WriteEnable) begin
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case (clint_waddr_i[11:0])
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`CSR_MTVEC: begin
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mtvec <= clint_data_i;
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end
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`CSR_MCAUSE: begin
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mcause <= clint_data_i;
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end
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`CSR_MEPC: begin
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mepc <= clint_data_i;
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end
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`CSR_MIE: begin
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mie <= clint_data_i;
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end
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`CSR_MSTATUS: begin
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mstatus <= clint_data_i;
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end
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`CSR_MSCRATCH: begin
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mscratch <= clint_data_i;
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end
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default: begin
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end
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endcase
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end
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end
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end
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// read reg
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// ex模块读CSR寄存器
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always @ (*) begin
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if (rst == `RstEnable) begin
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data_o = `ZeroWord;
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end else begin
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if ((waddr_i[11:0] == raddr_i[11:0]) && (we_i == `WriteEnable)) begin
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data_o = data_i;
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end else begin
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case (raddr_i[11:0])
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`CSR_CYCLE: begin
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data_o = cycle[31:0];
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end
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`CSR_CYCLEH: begin
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data_o = cycle[63:32];
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end
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`CSR_MTVEC: begin
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data_o = mtvec;
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end
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`CSR_MCAUSE: begin
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data_o = mcause;
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end
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`CSR_MEPC: begin
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data_o = mepc;
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end
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`CSR_MIE: begin
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data_o = mie;
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end
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`CSR_MSTATUS: begin
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data_o = mstatus;
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end
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`CSR_MSCRATCH: begin
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data_o = mscratch;
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end
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default: begin
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data_o = `ZeroWord;
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end
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endcase
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end
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end
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end
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// read reg
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// clint模块读CSR寄存器
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always @ (*) begin
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if (rst == `RstEnable) begin
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clint_data_o = `ZeroWord;
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end else begin
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if ((clint_waddr_i[11:0] == clint_raddr_i[11:0]) && (clint_we_i == `WriteEnable)) begin
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clint_data_o = clint_data_i;
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end else begin
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case (clint_raddr_i[11:0])
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`CSR_CYCLE: begin
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clint_data_o = cycle[31:0];
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end
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`CSR_CYCLEH: begin
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clint_data_o = cycle[63:32];
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end
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`CSR_MTVEC: begin
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clint_data_o = mtvec;
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end
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`CSR_MCAUSE: begin
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clint_data_o = mcause;
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end
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`CSR_MEPC: begin
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clint_data_o = mepc;
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end
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`CSR_MIE: begin
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clint_data_o = mie;
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end
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`CSR_MSTATUS: begin
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clint_data_o = mstatus;
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end
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`CSR_MSCRATCH: begin
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clint_data_o = mscratch;
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end
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default: begin
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clint_data_o = `ZeroWord;
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end
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endcase
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end
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end
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end
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endmodule
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