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clint.v
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use = instead of <= in combination logic
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2020-05-02 11:58:44 +08:00 |
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csr_reg.v
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rtl: core: fix data related for csr regs
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2020-06-05 22:22:49 +08:00 |
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ctrl.v
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use = instead of <= in combination logic
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2020-05-02 11:58:44 +08:00 |
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defines.v
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rtl: core: fix data related for csr regs
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2020-06-05 22:22:49 +08:00 |
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div.v
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stop div when interrupt assert
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2020-04-25 17:04:44 +08:00 |
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ex.v
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fix nop inst
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2020-05-07 22:40:31 +08:00 |
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id.v
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fix nop inst
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2020-05-07 22:40:31 +08:00 |
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id_ex.v
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add code comments
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2020-04-18 20:14:37 +08:00 |
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if_id.v
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add code comments
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2020-04-18 20:14:37 +08:00 |
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pc_reg.v
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add code comments
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2020-04-18 20:14:37 +08:00 |
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regs.v
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use = instead of <=
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2020-05-31 14:38:57 +08:00 |
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rib.v
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perips: add spi master
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2020-05-05 18:31:08 +08:00 |
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tinyriscv.v
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add signal
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2020-04-25 17:15:46 +08:00 |
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