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178 Commits
3 Branches
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66 MiB
C 59.1%
Assembly 28%
Verilog 11.4%
Makefile 0.8%
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liangkangnan 5c87fc09ef tb: add jtag testbench 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 		2020-12-06 20:07:06 +08:00
doc first release 2020-10-23 21:26:18 +08:00
fpga rtl: add reset ctrl module 2020-11-18 22:15:08 +08:00
pic pic: update arch.jpg 2020-06-27 10:11:46 +08:00
rtl rtl: debug: support reset cmd 2020-12-06 20:06:12 +08:00
sdk test:example: move C examples to sdk directory 2020-11-08 22:09:38 +08:00
sim tb: add jtag testbench 2020-12-06 20:07:06 +08:00
tb tb: add jtag testbench 2020-12-06 20:07:06 +08:00
tests test:example: move C examples to sdk directory 2020-11-08 22:09:38 +08:00
tools first release 2020-10-23 21:26:18 +08:00
.gitignore first release 2020-10-23 21:26:18 +08:00
LICENSE first release 2019-12-04 08:47:19 +08:00
README.md first release 2020-10-23 21:26:18 +08:00

README.md

本分支(bram)是在master分支的基础上，将指令和数据存储器由LUTRAM(DRAM)改为BRAM，以便可以运行更大的(C语言)程序。