507 lines
9.6 KiB
Verilog
507 lines
9.6 KiB
Verilog
`timescale 1 ns / 1 ps
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`include "defines.v"
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`define TEST_PROG 1
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//`define TEST_JTAG 1
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// testbench module
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module tinyriscv_soc_tb;
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reg clk;
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reg rst;
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always #10 clk = ~clk; // 50MHz
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wire[`RegBus] x3 = tinyriscv_soc_top_0.u_tinyriscv.u_regs.regs[3];
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wire[`RegBus] x26 = tinyriscv_soc_top_0.u_tinyriscv.u_regs.regs[26];
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wire[`RegBus] x27 = tinyriscv_soc_top_0.u_tinyriscv.u_regs.regs[27];
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integer r;
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`ifdef TEST_JTAG
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reg TCK;
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reg TMS;
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reg TDI;
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wire TDO;
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integer i;
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reg[39:0] shift_reg;
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reg in;
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wire[39:0] req_data = tinyriscv_soc_top_0.u_jtag_top.u_jtag_driver.dtm_req_data;
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wire[4:0] ir_reg = tinyriscv_soc_top_0.u_jtag_top.u_jtag_driver.ir_reg;
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wire dtm_req_valid = tinyriscv_soc_top_0.u_jtag_top.u_jtag_driver.dtm_req_valid;
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wire[31:0] dmstatus = tinyriscv_soc_top_0.u_jtag_top.u_jtag_dm.dmstatus;
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`endif
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initial begin
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clk = 0;
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rst = `RstEnable;
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`ifdef TEST_JTAG
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TCK = 1;
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TMS = 1;
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TDI = 1;
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`endif
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$display("test running...");
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#40
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rst = `RstDisable;
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#200
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`ifdef TEST_PROG
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wait(x26 == 32'b1) // wait sim end, when x26 == 1
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#100
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if (x27 == 32'b1) begin
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$display("~~~~~~~~~~~~~~~~~~~ TEST_PASS ~~~~~~~~~~~~~~~~~~~");
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$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
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$display("~~~~~~~~~ ##### ## #### #### ~~~~~~~~~");
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$display("~~~~~~~~~ # # # # # # ~~~~~~~~~");
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$display("~~~~~~~~~ # # # # #### #### ~~~~~~~~~");
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$display("~~~~~~~~~ ##### ###### # #~~~~~~~~~");
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$display("~~~~~~~~~ # # # # # # #~~~~~~~~~");
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$display("~~~~~~~~~ # # # #### #### ~~~~~~~~~");
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$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
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end else begin
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$display("~~~~~~~~~~~~~~~~~~~ TEST_FAIL ~~~~~~~~~~~~~~~~~~~~");
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$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
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$display("~~~~~~~~~~###### ## # # ~~~~~~~~~~");
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$display("~~~~~~~~~~# # # # # ~~~~~~~~~~");
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$display("~~~~~~~~~~##### # # # # ~~~~~~~~~~");
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$display("~~~~~~~~~~# ###### # # ~~~~~~~~~~");
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$display("~~~~~~~~~~# # # # # ~~~~~~~~~~");
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$display("~~~~~~~~~~# # # # ######~~~~~~~~~~");
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$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
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$display("fail testnum = %2d", x3);
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for (r = 0; r < 32; r++)
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$display("x%2d = 0x%x", r, tinyriscv_soc_top_0.u_tinyriscv.u_regs.regs[r]);
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end
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`endif
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`ifdef TEST_JTAG
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// reset
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for (i = 0; i < 8; i++) begin
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TMS = 1;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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end
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// IR
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shift_reg = 40'b10001;
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// IDLE
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TMS = 0;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// SELECT-DR
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TMS = 1;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// SELECT-IR
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TMS = 1;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// CAPTURE-IR
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TMS = 0;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// SHIFT-IR
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TMS = 0;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// SHIFT-IR & EXIT1-IR
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for (i = 5; i > 0; i--) begin
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if (shift_reg[0] == 1'b1)
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TDI = 1'b1;
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else
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TDI = 1'b0;
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if (i == 1)
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TMS = 1;
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TCK = 0;
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#100
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in = TDO;
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TCK = 1;
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#100
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TCK = 0;
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shift_reg = {{(35){1'b0}}, in, shift_reg[4:1]};
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end
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// PAUSE-IR
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TMS = 0;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// EXIT2-IR
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TMS = 1;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// UPDATE-IR
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TMS = 1;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// IDLE
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TMS = 0;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// IDLE
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TMS = 0;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// IDLE
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TMS = 0;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// IDLE
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TMS = 0;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// dmi write
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shift_reg = {6'h10, {(32){1'b0}}, 2'b10};
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// SELECT-DR
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TMS = 1;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// CAPTURE-DR
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TMS = 0;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// SHIFT-DR
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TMS = 0;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// SHIFT-DR & EXIT1-DR
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for (i = 40; i > 0; i--) begin
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if (shift_reg[0] == 1'b1)
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TDI = 1'b1;
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else
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TDI = 1'b0;
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if (i == 1)
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TMS = 1;
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TCK = 0;
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#100
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in = TDO;
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TCK = 1;
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#100
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TCK = 0;
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shift_reg = {in, shift_reg[39:1]};
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end
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// PAUSE-DR
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TMS = 0;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// EXIT2-DR
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TMS = 1;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// UPDATE-DR
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TMS = 1;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// IDLE
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TMS = 0;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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$display("ir_reg = 0x%x", ir_reg);
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$display("dtm_req_valid = %d", dtm_req_valid);
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$display("req_data = 0x%x", req_data);
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// IDLE
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TMS = 0;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// IDLE
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TMS = 0;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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$display("dmstatus = 0x%x", dmstatus);
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// IDLE
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TMS = 0;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// SELECT-DR
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TMS = 1;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// dmi read
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shift_reg = {6'h11, {(32){1'b0}}, 2'b01};
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// CAPTURE-DR
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TMS = 0;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// SHIFT-DR
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TMS = 0;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// SHIFT-DR & EXIT1-DR
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for (i = 40; i > 0; i--) begin
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if (shift_reg[0] == 1'b1)
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TDI = 1'b1;
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else
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TDI = 1'b0;
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if (i == 1)
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TMS = 1;
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TCK = 0;
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#100
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in = TDO;
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TCK = 1;
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#100
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TCK = 0;
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shift_reg = {in, shift_reg[39:1]};
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end
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// PAUSE-DR
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TMS = 0;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// EXIT2-DR
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TMS = 1;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// UPDATE-DR
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TMS = 1;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// IDLE
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TMS = 0;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// IDLE
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TMS = 0;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// IDLE
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TMS = 0;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// IDLE
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TMS = 0;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// SELECT-DR
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TMS = 1;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// dmi read
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shift_reg = {6'h11, {(32){1'b0}}, 2'b00};
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// CAPTURE-DR
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TMS = 0;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// SHIFT-DR
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TMS = 0;
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TCK = 0;
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#100
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TCK = 1;
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#100
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TCK = 0;
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// SHIFT-DR & EXIT1-DR
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for (i = 40; i > 0; i--) begin
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if (shift_reg[0] == 1'b1)
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TDI = 1'b1;
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else
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TDI = 1'b0;
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if (i == 1)
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TMS = 1;
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TCK = 0;
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#100
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in = TDO;
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TCK = 1;
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#100
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TCK = 0;
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shift_reg = {in, shift_reg[39:1]};
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end
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#100
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$display("shift_reg = 0x%x", shift_reg[33:2]);
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`endif
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$finish;
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end
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// sim timeout
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initial begin
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#500000
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$display("Time Out.");
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$finish;
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end
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// read mem data
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initial begin
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$readmemh ("inst.data", tinyriscv_soc_top_0.u_rom._rom);
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end
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// generate wave file, used by gtkwave
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initial begin
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$dumpfile("tinyriscv_soc_tb.vcd");
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$dumpvars(0, tinyriscv_soc_tb);
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end
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tinyriscv_soc_top tinyriscv_soc_top_0(
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.clk(clk),
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.rst(rst)/*
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.jtag_TCK(TCK),
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.jtag_TMS(TMS),
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.jtag_TDI(TDI),
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.jtag_TDO(TDO)*/
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);
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endmodule
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