tinyriscv/fpga/xilinx/constrs
liangkangnan 57690b00bd rtl:perips: add spi master
Signed-off-by: liangkangnan <liangkangnan@163.com>
2021-09-06 10:01:56 +08:00
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tinyriscv.xdc rtl:perips: add spi master 2021-09-06 10:01:56 +08:00