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liangkangnan 4d6f7ad664 FPGA: add jtag download
Signed-off-by: liangkangnan <liangkangnan@163.com>
2020-05-13 21:48:44 +08:00
FPGA FPGA: add jtag download 2020-05-13 21:48:44 +08:00
pic add spi 2020-05-05 19:50:27 +08:00
rtl debug: optimization for jtag 2020-05-13 21:27:40 +08:00
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README.en.md add README.en.md content 2019-12-09 13:49:07 +08:00
README.md add spi 2020-05-05 19:50:27 +08:00

README.en.md

###1.Introduction

This opensource project is a tiny riscv processor core which written by verilog. It is very simple and easy to understand. Tinyriscv has the following characteristics:

1)Implemented RV32I instruction set.

2)Use three-stage flow line.

3)Can run simple C program.

###2.How to use

Tinyriscv run on windows platform, it Compiled and simulated with iverilog. Before to use, you need install these tools below:

1)iverilog

Download from http://bleyer.org/icarus/](http://bleyer.org/icarus/, install it and add to system environment PATH.

2)GNU Toolchain

Download from BaiduNetDisk https://pan.baidu.com/s/1bYgslKxHMjtiZtIPsB2caQ, extraction code is 9n3c, decompress it into tools directory.

3)make tool

Download from BaiduNetDisk https://pan.baidu.com/s/1nFaUIwv171PDXuF7TziDFg, extraction code is 9ntc, decompress it and add to system environment PATH.

Take the "add" instruction as an example to show how to use:

Open the CMD and goto the sim directory and run command below:

sim_new_nowave.bat ..\tests\isa\generated\rv32ui-p-add.bin inst.data

You can see the following print if it run successfully: