126 lines
4.1 KiB
Python
126 lines
4.1 KiB
Python
import filecmp
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import subprocess
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import sys
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import os
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# iverilog程序
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iverilog_cmd = ['iverilog']
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# 顶层模块
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#iverilog_cmd += ['-s', r'tinyriscv_soc_tb']
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# 编译生成文件
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iverilog_cmd += ['-o', r'out.vvp']
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# 头文件(defines.v)路径
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iverilog_cmd += ['-I', r'..\..\rtl\core']
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# 宏定义，仿真输出文件
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iverilog_cmd += ['-D', r'OUTPUT="signature.output"']
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# testbench文件
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iverilog_cmd.append(r'..\..\tb\compliance_test\tinyriscv_soc_tb.v')
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# ..\rtl\core
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iverilog_cmd.append(r'..\..\rtl\core\defines.v')
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iverilog_cmd.append(r'..\..\rtl\core\ex.v')
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iverilog_cmd.append(r'..\..\rtl\core\id.v')
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iverilog_cmd.append(r'..\..\rtl\core\tinyriscv.v')
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iverilog_cmd.append(r'..\..\rtl\core\pc_reg.v')
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iverilog_cmd.append(r'..\..\rtl\core\id_ex.v')
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iverilog_cmd.append(r'..\..\rtl\core\ctrl.v')
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iverilog_cmd.append(r'..\..\rtl\core\regs.v')
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iverilog_cmd.append(r'..\..\rtl\core\if_id.v')
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iverilog_cmd.append(r'..\..\rtl\core\div.v')
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iverilog_cmd.append(r'..\..\rtl\core\rib.v')
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iverilog_cmd.append(r'..\..\rtl\core\clint.v')
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iverilog_cmd.append(r'..\..\rtl\core\csr_reg.v')
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# ..\rtl\perips
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iverilog_cmd.append(r'..\..\rtl\perips\ram.v')
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iverilog_cmd.append(r'..\..\rtl\perips\rom.v')
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iverilog_cmd.append(r'..\..\rtl\perips\spi.v')
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iverilog_cmd.append(r'..\..\rtl\perips\timer.v')
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iverilog_cmd.append(r'..\..\rtl\perips\uart_tx.v')
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iverilog_cmd.append(r'..\..\rtl\perips\gpio.v')
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# ..\rtl\debug
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iverilog_cmd.append(r'..\..\rtl\debug\jtag_dm.v')
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iverilog_cmd.append(r'..\..\rtl\debug\jtag_driver.v')
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iverilog_cmd.append(r'..\..\rtl\debug\jtag_top.v')
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# ..\rtl\soc
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iverilog_cmd.append(r'..\..\rtl\soc\tinyriscv_soc_top.v')
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# 找出path目录下的所有reference_output文件
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def list_ref_files(path):
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files = []
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list_dir = os.walk(path)
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for maindir, subdir, all_file in list_dir:
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for filename in all_file:
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apath = os.path.join(maindir, filename)
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if apath.endswith('.reference_output'):
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files.append(apath)
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return files
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# 根据bin文件找到对应的reference_output文件
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def get_reference_file(bin_file):
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file_path, file_name = os.path.split(bin_file)
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tmp = file_name.split('.')
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# 得到bin文件的前缀部分
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prefix = tmp[0]
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#print('bin prefix: %s' % prefix)
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files = []
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if (bin_file.find('rv32im') != -1):
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files = list_ref_files(r'..\..\tests\riscv-compliance\riscv-test-suite\rv32im\references')
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elif (bin_file.find('rv32i') != -1):
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files = list_ref_files(r'..\..\tests\riscv-compliance\riscv-test-suite\rv32i\references')
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elif (bin_file.find('rv32Zicsr') != -1):
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files = list_ref_files(r'..\..\tests\riscv-compliance\riscv-test-suite\rv32Zicsr\references')
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elif (bin_file.find('rv32Zifencei') != -1):
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files = list_ref_files(r'..\..\tests\riscv-compliance\riscv-test-suite\rv32Zifencei\references')
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else:
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return None
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# 根据bin文件前缀找到对应的reference_output文件
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for file in files:
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if (file.find(prefix) != -1):
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return file
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return None
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# 主函数
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def main():
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#print(sys.argv[0] + ' ' + sys.argv[1] + ' ' + sys.argv[2])
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# 1.将bin文件转成mem文件
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bin_to_mem_cmd = [r'..\..\tools\BinToMem_CLI.exe']
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bin_to_mem_cmd.append(sys.argv[1])
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bin_to_mem_cmd.append(sys.argv[2])
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process = subprocess.Popen(bin_to_mem_cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
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process.wait(timeout=2)
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# 2.编译rtl文件
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logfile = open('complie.log', 'w')
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process = subprocess.Popen(iverilog_cmd, stdout=logfile, stderr=logfile)
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process.wait(timeout=2)
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logfile.close()
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# 3.运行
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logfile = open('run.log', 'w')
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vvp_cmd = [r'vvp']
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vvp_cmd.append(r'out.vvp')
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process = subprocess.Popen(vvp_cmd, stdout=logfile, stderr=logfile)
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process.wait(timeout=2)
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logfile.close()
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# 4.比较结果
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ref_file = get_reference_file(sys.argv[1])
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if (ref_file != None):
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if (filecmp.cmp('signature.output', ref_file, shallow=False) == True):
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print('### PASS ###')
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else:
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print('!!! FAIL !!!')
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else:
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print('No ref file found, please check result by yourself.')
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if __name__ == '__main__':
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sys.exit(main())
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