213 lines
8.4 KiB
Systemverilog
213 lines
8.4 KiB
Systemverilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.sv"
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module exu_dispatch(
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input wire clk,
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input wire rst_n,
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input wire[`DECINFO_WIDTH-1:0] dec_info_bus_i,
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input wire[31:0] dec_imm_i,
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input wire[31:0] dec_pc_i,
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input wire[31:0] rs1_rdata_i,
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input wire[31:0] rs2_rdata_i,
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// dispatch to ALU
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output wire req_alu_o,
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output wire[31:0] alu_op1_o,
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output wire[31:0] alu_op2_o,
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output wire alu_op_lui_o,
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output wire alu_op_auipc_o,
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output wire alu_op_add_o,
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output wire alu_op_sub_o,
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output wire alu_op_sll_o,
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output wire alu_op_slt_o,
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output wire alu_op_sltu_o,
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output wire alu_op_xor_o,
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output wire alu_op_srl_o,
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output wire alu_op_sra_o,
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output wire alu_op_or_o,
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output wire alu_op_and_o,
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// dispatch to BJP
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output wire req_bjp_o,
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output wire[31:0] bjp_op1_o,
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output wire[31:0] bjp_op2_o,
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output wire[31:0] bjp_jump_op1_o,
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output wire[31:0] bjp_jump_op2_o,
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output wire bjp_op_jump_o,
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output wire bjp_op_beq_o,
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output wire bjp_op_bne_o,
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output wire bjp_op_blt_o,
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output wire bjp_op_bltu_o,
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output wire bjp_op_bge_o,
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output wire bjp_op_bgeu_o,
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// dispatch to MULDIV
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output wire req_muldiv_o,
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output wire[31:0] muldiv_op1_o,
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output wire[31:0] muldiv_op2_o,
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output wire muldiv_op_mul_o,
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output wire muldiv_op_mulh_o,
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output wire muldiv_op_mulhsu_o,
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output wire muldiv_op_mulhu_o,
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output wire muldiv_op_div_o,
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output wire muldiv_op_divu_o,
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output wire muldiv_op_rem_o,
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output wire muldiv_op_remu_o,
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// dispatch to CSR
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output wire req_csr_o,
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output wire[31:0] csr_op1_o,
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output wire[31:0] csr_addr_o,
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output wire csr_csrrw_o,
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output wire csr_csrrs_o,
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output wire csr_csrrc_o,
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// dispatch to MEM
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output wire req_mem_o,
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output wire[31:0] mem_op1_o,
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output wire[31:0] mem_op2_o,
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output wire[31:0] mem_rs2_data_o,
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output wire mem_op_lb_o,
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output wire mem_op_lh_o,
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output wire mem_op_lw_o,
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output wire mem_op_lbu_o,
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output wire mem_op_lhu_o,
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output wire mem_op_sb_o,
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output wire mem_op_sh_o,
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output wire mem_op_sw_o,
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// dispatch to SYS
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output wire sys_op_nop_o,
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output wire sys_op_mret_o,
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output wire sys_op_ecall_o,
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output wire sys_op_ebreak_o,
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output wire sys_op_fence_o,
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output wire sys_op_dret_o
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);
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wire[`DECINFO_GRP_WIDTH-1:0] disp_info_grp = dec_info_bus_i[`DECINFO_GRP_BUS];
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// ALU info
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wire op_alu = (disp_info_grp == `DECINFO_GRP_ALU);
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wire[`DECINFO_WIDTH-1:0] alu_info = {`DECINFO_WIDTH{op_alu}} & dec_info_bus_i;
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// ALU op1
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wire alu_op1_pc = alu_info[`DECINFO_ALU_OP1PC];
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wire alu_op1_zero = alu_info[`DECINFO_ALU_LUI];
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wire[31:0] alu_op1 = alu_op1_pc? dec_pc_i: alu_op1_zero? 32'h0: rs1_rdata_i;
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assign alu_op1_o = op_alu? alu_op1: 32'h0;
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// ALU op2
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wire alu_op2_imm = alu_info[`DECINFO_ALU_OP2IMM];
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wire[31:0] alu_op2 = alu_op2_imm? dec_imm_i: rs2_rdata_i;
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assign alu_op2_o = op_alu? alu_op2: 32'h0;
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assign alu_op_lui_o = alu_info[`DECINFO_ALU_LUI];
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assign alu_op_auipc_o = alu_info[`DECINFO_ALU_AUIPC];
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assign alu_op_add_o = alu_info[`DECINFO_ALU_ADD];
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assign alu_op_sub_o = alu_info[`DECINFO_ALU_SUB];
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assign alu_op_sll_o = alu_info[`DECINFO_ALU_SLL];
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assign alu_op_slt_o = alu_info[`DECINFO_ALU_SLT];
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assign alu_op_sltu_o = alu_info[`DECINFO_ALU_SLTU];
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assign alu_op_xor_o = alu_info[`DECINFO_ALU_XOR];
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assign alu_op_srl_o = alu_info[`DECINFO_ALU_SRL];
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assign alu_op_sra_o = alu_info[`DECINFO_ALU_SRA];
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assign alu_op_or_o = alu_info[`DECINFO_ALU_OR];
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assign alu_op_and_o = alu_info[`DECINFO_ALU_AND];
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assign req_alu_o = op_alu;
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// BJP info
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wire op_bjp = (disp_info_grp == `DECINFO_GRP_BJP);
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wire[`DECINFO_WIDTH-1:0] bjp_info = {`DECINFO_WIDTH{op_bjp}} & dec_info_bus_i;
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// BJP op1
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wire bjp_op1_rs1 = bjp_info[`DECINFO_BJP_OP1RS1];
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wire[31:0] bjp_op1 = bjp_op1_rs1? rs1_rdata_i: dec_pc_i;
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assign bjp_jump_op1_o = op_bjp? bjp_op1: 32'h0;
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// BJP op2
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wire[31:0] bjp_op2 = dec_imm_i;
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assign bjp_jump_op2_o = op_bjp? bjp_op2: 32'h0;
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assign bjp_op1_o = op_bjp? rs1_rdata_i: 32'h0;
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assign bjp_op2_o = op_bjp? rs2_rdata_i: 32'h0;
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assign bjp_op_jump_o = bjp_info[`DECINFO_BJP_JUMP];
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assign bjp_op_beq_o = bjp_info[`DECINFO_BJP_BEQ];
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assign bjp_op_bne_o = bjp_info[`DECINFO_BJP_BNE];
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assign bjp_op_blt_o = bjp_info[`DECINFO_BJP_BLT];
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assign bjp_op_bltu_o = bjp_info[`DECINFO_BJP_BLTU];
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assign bjp_op_bge_o = bjp_info[`DECINFO_BJP_BGE];
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assign bjp_op_bgeu_o = bjp_info[`DECINFO_BJP_BGEU];
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assign req_bjp_o = op_bjp;
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// MULDIV info
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wire op_muldiv = (disp_info_grp == `DECINFO_GRP_MULDIV);
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wire[`DECINFO_WIDTH-1:0] muldiv_info = {`DECINFO_WIDTH{op_muldiv}} & dec_info_bus_i;
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// MULDIV op1
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assign muldiv_op1_o = op_muldiv? rs1_rdata_i: 32'h0;
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// MULDIV op2
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assign muldiv_op2_o = op_muldiv? rs2_rdata_i: 32'h0;
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assign muldiv_op_mul_o = muldiv_info[`DECINFO_MULDIV_MUL];
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assign muldiv_op_mulh_o = muldiv_info[`DECINFO_MULDIV_MULH];
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assign muldiv_op_mulhu_o = muldiv_info[`DECINFO_MULDIV_MULHU];
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assign muldiv_op_mulhsu_o = muldiv_info[`DECINFO_MULDIV_MULHSU];
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assign muldiv_op_div_o = muldiv_info[`DECINFO_MULDIV_DIV];
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assign muldiv_op_divu_o = muldiv_info[`DECINFO_MULDIV_DIVU];
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assign muldiv_op_rem_o = muldiv_info[`DECINFO_MULDIV_REM];
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assign muldiv_op_remu_o = muldiv_info[`DECINFO_MULDIV_REMU];
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assign req_muldiv_o = op_muldiv;
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// CSR info
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wire op_csr = (disp_info_grp == `DECINFO_GRP_CSR);
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wire[`DECINFO_WIDTH-1:0] csr_info = {`DECINFO_WIDTH{op_csr}} & dec_info_bus_i;
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// CSR op1
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wire csr_rs1imm = csr_info[`DECINFO_CSR_RS1IMM];
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wire[31:0] csr_rs1 = csr_rs1imm? dec_imm_i: rs1_rdata_i;
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assign csr_op1_o = op_csr? csr_rs1: 32'h0;
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assign csr_addr_o = {{20{1'b0}}, csr_info[`DECINFO_CSR_CSRADDR]};
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assign csr_csrrw_o = csr_info[`DECINFO_CSR_CSRRW];
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assign csr_csrrs_o = csr_info[`DECINFO_CSR_CSRRS];
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assign csr_csrrc_o = csr_info[`DECINFO_CSR_CSRRC];
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assign req_csr_o = op_csr;
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// MEM info
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wire op_mem = (disp_info_grp == `DECINFO_GRP_MEM);
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wire[`DECINFO_WIDTH-1:0] mem_info = {`DECINFO_WIDTH{op_mem}} & dec_info_bus_i;
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assign mem_op_lb_o = mem_info[`DECINFO_MEM_LB];
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assign mem_op_lh_o = mem_info[`DECINFO_MEM_LH];
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assign mem_op_lw_o = mem_info[`DECINFO_MEM_LW];
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assign mem_op_lbu_o = mem_info[`DECINFO_MEM_LBU];
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assign mem_op_lhu_o = mem_info[`DECINFO_MEM_LHU];
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assign mem_op_sb_o = mem_info[`DECINFO_MEM_SB];
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assign mem_op_sh_o = mem_info[`DECINFO_MEM_SH];
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assign mem_op_sw_o = mem_info[`DECINFO_MEM_SW];
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assign mem_op1_o = op_mem? rs1_rdata_i: 32'h0;
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assign mem_op2_o = op_mem? dec_imm_i: 32'h0;
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assign mem_rs2_data_o = op_mem? rs2_rdata_i: 32'h0;
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assign req_mem_o = op_mem;
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// SYS info
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wire op_sys = (disp_info_grp == `DECINFO_GRP_SYS);
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wire[`DECINFO_WIDTH-1:0] sys_info = {`DECINFO_WIDTH{op_sys}} & dec_info_bus_i;
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assign sys_op_nop_o = sys_info[`DECINFO_SYS_NOP];
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assign sys_op_mret_o = sys_info[`DECINFO_SYS_MRET];
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assign sys_op_ecall_o = sys_info[`DECINFO_SYS_ECALL];
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assign sys_op_ebreak_o = sys_info[`DECINFO_SYS_EBREAK];
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assign sys_op_fence_o = sys_info[`DECINFO_SYS_FENCE];
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assign sys_op_dret_o = sys_info[`DECINFO_SYS_DRET];
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endmodule
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