166 lines
9.3 KiB
Systemverilog
166 lines
9.3 KiB
Systemverilog
/*
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Copyright 2021 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// 二选一，都不选时表示测试用户自定义程序
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// tests/isa测试
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//`define TEST_ISA 1
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// tests/riscv-compliance测试
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//`define TEST_RISCV_COMPLIANCE 1
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module tb_top_verilator #(
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) (
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input wire clk_i,
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input wire rst_ni
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);
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wire halted;
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wire[31:0] x3 = u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.regs[3];
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wire[31:0] x26 = u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.regs[26];
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wire[31:0] x27 = u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.regs[27];
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wire[31:0] end_flag = u_tinyriscv_soc_top.u_ram.u_gen_ram.ram[4];
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wire[31:0] begin_signature = u_tinyriscv_soc_top.u_ram.u_gen_ram.ram[2];
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wire[31:0] end_signature = u_tinyriscv_soc_top.u_ram.u_gen_ram.ram[3];
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initial begin: load_prog
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automatic logic [1023:0] firmware;
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if($value$plusargs("firmware=%s", firmware)) begin
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$display("[TESTBENCH] %t: loading firmware %0s ...",
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$time, firmware);
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$readmemh (firmware, u_tinyriscv_soc_top.u_rom.u_gen_ram.ram);
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end else begin
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$display("No firmware specified");
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end
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end
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integer r;
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reg result_printed;
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always @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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result_printed <= 1'b0;
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end else begin
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if (u_tinyriscv_soc_top.ndmreset) begin
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result_printed <= 1'b0;
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end else if (!result_printed) begin
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`ifdef TEST_RISCV_COMPLIANCE
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if (end_flag == 32'h1) begin
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for (r = begin_signature; r < end_signature; r = r + 4) begin
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$display("%x", u_tinyriscv_soc_top.u_rom.u_gen_ram.ram[r[31:2]]);
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end
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$finish;
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end
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`else
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if (x26 == 32'b1) begin
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if (x27 == 32'b1) begin
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$display("~~~~~~~~~~~~~~~~~~~ TEST_PASS ~~~~~~~~~~~~~~~~~~~");
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$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
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$display("~~~~~~~~~ ##### ## #### #### ~~~~~~~~~");
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$display("~~~~~~~~~ # # # # # # ~~~~~~~~~");
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$display("~~~~~~~~~ # # # # #### #### ~~~~~~~~~");
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$display("~~~~~~~~~ ##### ###### # #~~~~~~~~~");
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$display("~~~~~~~~~ # # # # # # #~~~~~~~~~");
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$display("~~~~~~~~~ # # # #### #### ~~~~~~~~~");
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$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
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end else begin
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$display("~~~~~~~~~~~~~~~~~~~ TEST_FAIL ~~~~~~~~~~~~~~~~~~~~");
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$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
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$display("~~~~~~~~~~###### ## # # ~~~~~~~~~~");
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$display("~~~~~~~~~~# # # # # ~~~~~~~~~~");
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$display("~~~~~~~~~~##### # # # # ~~~~~~~~~~");
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$display("~~~~~~~~~~# ###### # # ~~~~~~~~~~");
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$display("~~~~~~~~~~# # # # # ~~~~~~~~~~");
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$display("~~~~~~~~~~# # # # ######~~~~~~~~~~");
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$display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
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`ifdef TEST_ISA
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$display("fail testnum = %2d", x3);
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`endif
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end
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result_printed <= 1'b1;
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end
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`endif
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end
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end
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end
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tinyriscv_soc_top u_tinyriscv_soc_top(
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.clk_50m_i(clk_i),
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.rst_ext_ni(rst_ni),
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.halted_ind_pin(halted)
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);
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wire display_regs = 1'b0;
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wire write_gpr_reg = u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.we_i;
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wire[4:0] write_gpr_addr = u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.waddr_i;
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wire write_csr_reg = u_tinyriscv_soc_top.u_tinyriscv_core.u_csr_reg.exu_we_i;
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wire[31:0] write_csr_addr = u_tinyriscv_soc_top.u_tinyriscv_core.u_csr_reg.exu_waddr_i;
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always @ (posedge clk_i) begin
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if (halted && write_gpr_reg && display_regs && (write_gpr_addr == 5'd31)) begin
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$display("\n");
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$display("ra = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.ra);
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$display("sp = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.sp);
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$display("gp = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.gp);
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$display("tp = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.tp);
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$display("t0 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.t0);
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$display("t1 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.t1);
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$display("t2 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.t2);
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$display("s0 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.s0);
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$display("fp = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.fp);
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$display("s1 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.s1);
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$display("a0 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.a0);
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$display("a1 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.a1);
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$display("a2 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.a2);
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$display("a3 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.a3);
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$display("a4 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.a4);
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$display("a5 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.a5);
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$display("a6 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.a6);
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$display("a7 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.a7);
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$display("s2 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.s2);
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$display("s3 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.s3);
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$display("s4 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.s4);
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$display("s5 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.s5);
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$display("s6 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.s6);
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$display("s7 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.s7);
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$display("s8 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.s8);
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$display("s9 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.s9);
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$display("s10 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.s10);
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$display("s11 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.s11);
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$display("t3 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.t3);
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$display("t4 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.t4);
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$display("t5 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.t5);
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$display("t6 = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_gpr_reg.t6);
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end else if (halted && write_csr_reg && display_regs && (write_csr_addr[11:0] == 12'hc00)) begin
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$display("\n");
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$display("misa = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_csr_reg.misa);
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$display("cycle = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_csr_reg.cycle[31:0]);
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$display("cycleh = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_csr_reg.cycle[63:32]);
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$display("mtvec = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_csr_reg.mtvec);
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$display("mstatus = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_csr_reg.mstatus);
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$display("mepc = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_csr_reg.mepc);
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$display("mie = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_csr_reg.mie);
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$display("dpc = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_csr_reg.dpc);
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$display("dcsr = 0x%x", u_tinyriscv_soc_top.u_tinyriscv_core.u_csr_reg.dcsr);
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end
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end
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endmodule // tb_top_verilator
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