389 lines
9.7 KiB
Verilog
389 lines
9.7 KiB
Verilog
/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "../core/defines.v"
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// tinyriscv soc顶层模块
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module tinyriscv_soc_top(
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input wire clk,
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input wire rst,
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output reg over, // 测试是否完成信号
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output reg succ, // 测试是否成功信号
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output wire halted_ind, // jtag是否已经halt住CPU信号
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output wire tx_pin, // UART发送引脚
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inout wire[1:0] gpio, // GPIO引脚
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input wire jtag_TCK, // JTAG TCK引脚
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input wire jtag_TMS, // JTAG TMS引脚
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input wire jtag_TDI, // JTAG TDI引脚
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output wire jtag_TDO, // JTAG TDO引脚
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input wire spi_miso, // SPI MISO引脚
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output wire spi_mosi, // SPI MOSI引脚
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output wire spi_ss, // SPI SS引脚
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output wire spi_clk // SPI CLK引脚
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);
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// master 0 interface
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wire[`MemAddrBus] m0_addr_i;
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wire[`MemBus] m0_data_i;
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wire[`MemBus] m0_data_o;
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wire m0_ack_o;
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wire m0_req_i;
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wire m0_we_i;
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// master 1 interface
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wire[`MemAddrBus] m1_addr_i;
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wire[`MemBus] m1_data_i;
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wire[`MemBus] m1_data_o;
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wire m1_ack_o;
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wire m1_req_i;
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wire m1_we_i;
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// master 2 interface
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wire[`MemAddrBus] m2_addr_i;
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wire[`MemBus] m2_data_i;
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wire[`MemBus] m2_data_o;
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wire m2_ack_o;
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wire m2_req_i;
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wire m2_we_i;
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// slave 0 interface
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wire[`MemAddrBus] s0_addr_o;
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wire[`MemBus] s0_data_o;
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wire[`MemBus] s0_data_i;
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wire s0_ack_i;
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wire s0_req_o;
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wire s0_we_o;
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// slave 1 interface
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wire[`MemAddrBus] s1_addr_o;
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wire[`MemBus] s1_data_o;
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wire[`MemBus] s1_data_i;
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wire s1_ack_i;
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wire s1_req_o;
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wire s1_we_o;
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// slave 2 interface
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wire[`MemAddrBus] s2_addr_o;
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wire[`MemBus] s2_data_o;
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wire[`MemBus] s2_data_i;
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wire s2_ack_i;
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wire s2_req_o;
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wire s2_we_o;
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// slave 3 interface
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wire[`MemAddrBus] s3_addr_o;
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wire[`MemBus] s3_data_o;
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wire[`MemBus] s3_data_i;
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wire s3_ack_i;
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wire s3_req_o;
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wire s3_we_o;
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// slave 4 interface
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wire[`MemAddrBus] s4_addr_o;
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wire[`MemBus] s4_data_o;
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wire[`MemBus] s4_data_i;
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wire s4_ack_i;
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wire s4_req_o;
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wire s4_we_o;
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// slave 5 interface
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wire[`MemAddrBus] s5_addr_o;
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wire[`MemBus] s5_data_o;
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wire[`MemBus] s5_data_i;
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wire s5_ack_i;
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wire s5_req_o;
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wire s5_we_o;
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// rib
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wire rib_hold_flag_o;
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// jtag
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wire jtag_halt_req_o;
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wire jtag_reset_req_o;
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reg jtag_rst;
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reg[2:0] jtag_rst_cnt;
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wire[`RegAddrBus] jtag_reg_addr_o;
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wire[`RegBus] jtag_reg_data_o;
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wire jtag_reg_we_o;
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wire[`RegBus] jtag_reg_data_i;
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// tinyriscv
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wire[`INT_BUS] int_flag;
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// timer0
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wire timer0_int;
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// gpio
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wire[1:0] io_in;
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wire[31:0] gpio_ctrl;
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wire[31:0] gpio_data;
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assign int_flag = {7'h0, timer0_int};
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// 低电平点亮LED
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// 低电平表示已经halt住CPU
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assign halted_ind = ~jtag_halt_req_o;
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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over <= 1'b1;
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succ <= 1'b1;
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end else begin
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over <= ~u_tinyriscv.u_regs.regs[26]; // when = 1, run over
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succ <= ~u_tinyriscv.u_regs.regs[27]; // when = 1, run succ, otherwise fail
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end
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end
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// tinyriscv处理器核模块例化
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tinyriscv u_tinyriscv(
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.clk(clk),
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.rst(rst),
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.rib_ex_addr_o(m0_addr_i),
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.rib_ex_data_i(m0_data_o),
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.rib_ex_data_o(m0_data_i),
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.rib_ex_req_o(m0_req_i),
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.rib_ex_we_o(m0_we_i),
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.rib_pc_addr_o(m1_addr_i),
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.rib_pc_data_i(m1_data_o),
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.jtag_reg_addr_i(jtag_reg_addr_o),
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.jtag_reg_data_i(jtag_reg_data_o),
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.jtag_reg_we_i(jtag_reg_we_o),
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.jtag_reg_data_o(jtag_reg_data_i),
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.rib_hold_flag_i(rib_hold_flag_o),
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.jtag_halt_flag_i(jtag_halt_req_o),
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.jtag_reset_flag_i(jtag_reset_req_o),
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.int_i(int_flag)
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);
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// rom模块例化
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rom u_rom(
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.clk(clk),
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.rst(rst),
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.we_i(s0_we_o),
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.addr_i(s0_addr_o),
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.data_i(s0_data_o),
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.req_i(s0_req_o),
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.data_o(s0_data_i),
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.ack_o(s0_ack_i)
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);
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// ram模块例化
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ram u_ram(
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.clk(clk),
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.rst(rst),
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.we_i(s1_we_o),
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.addr_i(s1_addr_o),
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.data_i(s1_data_o),
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.req_i(s1_req_o),
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.data_o(s1_data_i),
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.ack_o(s1_ack_i)
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);
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// timer模块例化
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timer timer_0(
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.clk(clk),
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.rst(rst),
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.data_i(s2_data_o),
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.addr_i(s2_addr_o),
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.we_i(s2_we_o),
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.data_o(s2_data_i),
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.int_sig_o(timer0_int),
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.req_i(s2_req_o),
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.ack_o(s2_ack_i)
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);
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// uart_tx模块例化
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uart_tx uart_tx_0(
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.clk(clk),
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.rst(rst),
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.we_i(s3_we_o),
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.req_i(s3_req_o),
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.addr_i(s3_addr_o),
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.data_i(s3_data_o),
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.data_o(s3_data_i),
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.ack_o(s3_ack_i),
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.tx_pin(tx_pin)
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);
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// io0
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assign gpio[0] = (gpio_ctrl[1:0] == 2'b01)? gpio_data[0]: 1'bz;
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assign io_in[0] = gpio[0];
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// io1
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assign gpio[1] = (gpio_ctrl[3:2] == 2'b01)? gpio_data[1]: 1'bz;
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assign io_in[1] = gpio[1];
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// gpio模块例化
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gpio gpio_0(
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.clk(clk),
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.rst(rst),
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.we_i(s4_we_o),
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.req_i(s4_req_o),
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.addr_i(s4_addr_o),
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.data_i(s4_data_o),
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.data_o(s4_data_i),
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.ack_o(s4_ack_i),
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.io_pin_i(io_in),
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.reg_ctrl(gpio_ctrl),
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.reg_data(gpio_data)
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);
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// spi模块例化
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spi spi_0(
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.clk(clk),
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.rst(rst),
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.data_i(s5_data_o),
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.addr_i(s5_addr_o),
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.we_i(s5_we_o),
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.req_i(s5_req_o),
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.data_o(s5_data_i),
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.ack_o(s5_ack_i),
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.spi_mosi(spi_mosi),
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.spi_miso(spi_miso),
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.spi_ss(spi_ss),
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.spi_clk(spi_clk)
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);
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// rib模块例化
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rib u_rib(
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.clk(clk),
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.rst(rst),
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// master 0 interface
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.m0_addr_i(m0_addr_i),
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.m0_data_i(m0_data_i),
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.m0_data_o(m0_data_o),
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.m0_ack_o(m0_ack_o),
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.m0_req_i(m0_req_i),
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.m0_we_i(m0_we_i),
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// master 1 interface
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.m1_addr_i(m1_addr_i),
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.m1_data_i(`ZeroWord),
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.m1_data_o(m1_data_o),
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.m1_ack_o(m1_ack_o),
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.m1_req_i(`RIB_REQ),
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.m1_we_i(`WriteDisable),
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// master 2 interface
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.m2_addr_i(m2_addr_i),
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.m2_data_i(m2_data_i),
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.m2_data_o(m2_data_o),
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.m2_ack_o(m2_ack_o),
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.m2_req_i(m2_req_i),
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.m2_we_i(m2_we_i),
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// slave 0 interface
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.s0_addr_o(s0_addr_o),
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.s0_data_o(s0_data_o),
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.s0_data_i(s0_data_i),
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.s0_ack_i(s0_ack_i),
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.s0_req_o(s0_req_o),
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.s0_we_o(s0_we_o),
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// slave 1 interface
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.s1_addr_o(s1_addr_o),
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.s1_data_o(s1_data_o),
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.s1_data_i(s1_data_i),
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.s1_ack_i(s1_ack_i),
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.s1_req_o(s1_req_o),
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.s1_we_o(s1_we_o),
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// slave 2 interface
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.s2_addr_o(s2_addr_o),
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.s2_data_o(s2_data_o),
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.s2_data_i(s2_data_i),
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.s2_ack_i(s2_ack_i),
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.s2_req_o(s2_req_o),
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.s2_we_o(s2_we_o),
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// slave 3 interface
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.s3_addr_o(s3_addr_o),
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.s3_data_o(s3_data_o),
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.s3_data_i(s3_data_i),
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.s3_ack_i(s3_ack_i),
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.s3_req_o(s3_req_o),
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.s3_we_o(s3_we_o),
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// slave 4 interface
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.s4_addr_o(s4_addr_o),
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.s4_data_o(s4_data_o),
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.s4_data_i(s4_data_i),
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.s4_ack_i(s4_ack_i),
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.s4_req_o(s4_req_o),
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.s4_we_o(s4_we_o),
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// slave 5 interface
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.s5_addr_o(s5_addr_o),
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.s5_data_o(s5_data_o),
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.s5_data_i(s5_data_i),
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.s5_ack_i(s5_ack_i),
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.s5_req_o(s5_req_o),
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.s5_we_o(s5_we_o),
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.hold_flag_o(rib_hold_flag_o)
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);
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// jtag模块复位逻辑
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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jtag_rst <= 1'b1;
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jtag_rst_cnt <= 3'h0;
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end else begin
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if (jtag_rst_cnt < 3'h5) begin
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jtag_rst <= ~jtag_rst;
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jtag_rst_cnt <= jtag_rst_cnt + 1'b1;
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end else begin
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jtag_rst <= 1'b1;
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end
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end
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end
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// jtag模块例化
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jtag_top u_jtag_top(
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.clk(clk),
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.jtag_rst_n(jtag_rst),
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.jtag_pin_TCK(jtag_TCK),
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.jtag_pin_TMS(jtag_TMS),
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.jtag_pin_TDI(jtag_TDI),
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.jtag_pin_TDO(jtag_TDO),
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.reg_we_o(jtag_reg_we_o),
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.reg_addr_o(jtag_reg_addr_o),
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.reg_wdata_o(jtag_reg_data_o),
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.reg_rdata_i(jtag_reg_data_i),
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.mem_we_o(m2_we_i),
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.mem_addr_o(m2_addr_i),
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.mem_wdata_o(m2_data_i),
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.mem_rdata_i(m2_data_o),
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.op_req_o(m2_req_i),
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.halt_req_o(jtag_halt_req_o),
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.reset_req_o(jtag_reset_req_o)
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);
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endmodule
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